diff --git "a/shard_new_new_cleaned_v_text_49.csv" "b/shard_new_new_cleaned_v_text_49.csv" new file mode 100644--- /dev/null +++ "b/shard_new_new_cleaned_v_text_49.csv" @@ -0,0 +1,89089 @@ +text +"/* PR1637208 */ + +module main; + reg clock; + reg [31:0] pixel0; + reg [31:0] mem [0:1]; + + always @(posedge clock) begin + mem[0] <= pixel0; + end + + always @(posedge clock) begin + mem[1] <= mem[0]; + end + + reg sel; + wire [31:0] foo = sel? mem[1] : mem[0]; + + initial begin + clock = 1; + sel = 0; + #1 pixel0 = \'h55555555; + #1 clock = 0; + #1 clock = 1; + #1 pixel0 = \'haaaaaaaa; + #1 clock = 0; + #1 clock = 1; + #1 if (mem[0] !== 32\'haaaaaaaa) begin +\t $display(""FAILED -- mem[0] = %h"", mem[0]); +\t $finish; + end + + if (mem[1] !== 32\'h55555555) begin +\t $display(""FAILED == mem[1] = %h"", mem[1]); +\t $finish; + end + + if (foo !== mem[0]) begin +\t $display(""FAILED -- mem[sel=0] != %h"", foo); +\t $finish; + end + + sel = 1; + + #1 if (foo !== mem[1]) begin +\t $display(""FAILED -- mem[sel=1] != %h"", foo); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"/* + * Copyright (c) 2000 Intrinsity, Inc. + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module test_bufif0 (); + +wire t0, t1, t2, t3, t4, t5, t6, t7, + t8, t9, ta, tb, tc, td, te, tf; + +reg gnd, vdd, x, z; +reg failed; + +wire StH, StL; + +assign (strong1, highz0) StH = 1\'bx; +assign (highz1, strong0) StL = 1\'bx; + +bufif0 n0 ( t0, gnd, gnd); +bufif0 n1 ( t1, gnd, vdd); +bufif0 n2 ( t2, gnd, x); +bufif0 n3 ( t3, gnd, z); + +bufif0 n4 ( t4, vdd, gnd); +bufif0 n5 ( t5, vdd, vdd); +bufif0 n6 ( t6, vdd, x); +bufif0 n7 ( t7, vdd, z); + +bufif0 n8 ( t8, x, gnd); +bufif0 n9 ( t9, x, vdd); +bufif0 na ( ta, x, x); +bufif0 nb ( tb, x, z); + +bufif0 nc ( tc, z, gnd); +bufif0 nd ( td, z, vdd); +bufif0 ne ( te, z, x); +bufif0 nf ( tf, z, z); + +initial begin + + assign gnd = 1\'b1; + assign vdd = 1\'b0; + assign x = 1\'b0; + assign z = 1\'b0; + #10; + + assign gnd = 1\'b0; + assign vdd = 1\'b1; + assign x = 1\'b1; + assign z = 1\'b1; + #10; + + assign gnd = 1\'b0; + assign vdd = 1\'b1; + assign x = 1\'bx; + assign z = 1\'bz; + #10; + + failed = 0; + + if (t0 !== gnd) + begin + failed = 1; + $display (""FAILED: bufif0 s:%d g:%d d:%d expected:0"", gnd, gnd, t0 ); + end + + if (t1 !== z) + begin + failed = 1; + $display (""FAILED: bufif0 s:%d g:%d d:%d expected:z"", gnd, vdd, t1 ); + end + if (t2 !== StL) + begin + failed = 1; + $display (""FAILED: bufif0 s:%d g:%d d:%d expected:StL"", gnd, x, t2 ); + end + + if (t3 !== StL) + begin + failed = 1; + $display (""FAILED: bufif0 s:%d g:%d d:%d expected:StL"", gnd, x, t3 ); + end + + if (t4 !== 1\'b1) + begin + failed = 1; + $display (""FAILED: bufif0 s:%d g:%d d:%d expected:1"", vdd, gnd, t4 ); + end + if (t5 !== z) + begin + failed = 1; + $display (""FAILED: bufif0 s:%d g:%d d:%d expected:z"", vdd, vdd, t5 ); + end + if (t6 !== StH) + begin + failed = 1; + $display (""FAILED: bufif0 s:%d g:%d d:%d expected:StH"", vdd, x, t6 ); + end + if (t7 !== StH) + begin + failed = 1; + $display (""FAILED: bufif0 s:%d g:%d d:%d expected:StH"", vdd, x, t7 ); + end + + if (t8 !== 1\'bx) + begin + failed = 1; + $display (""FAILED: bufif0 s:%d g:%d d:%d expected:x"", x, gnd, t8 ); + end + if (t9 !== 1\'bz) + begin + failed = 1; + $display (""FAILED: bufif0 s:%d g:%d d:%d expected:z"", x, vdd, t9 ); + end + if (ta !== 1\'bx) + begin + failed = 1; + $display (""FAILED: bufif0 s:%d g:%d d:%d expected:x"", x, x, ta ); + end + if (tb !== 1\'bx) + begin + failed = 1; + $display (""FAILED: bufif0 s:%d g:%d d:%d expected:x"", x, z, tb ); + end + + if (tc !== 1\'bx) + begin + failed = 1; + $display (""FAILED: bufif0 s:%d g:%d d:%d expected:x"", z, gnd, tc ); + end + if (td !== 1\'bz) + begin + failed = 1; + $display (""FAILED: bufif0 s:%d g:%d d:%d expected:z"", z, vdd, td ); + end + if (te !== 1\'bx) + begin + failed = 1; + $display (""FAILED: bufif0 s:%d g:%d d:%d expected:x"", z, x, te ); + end + if (tf !== 1\'bx) + begin + failed = 1; + $display (""FAILED: bufif0 s:%d g:%d d:%d expected:x"", z, z, tf ); + end + + if (failed == 0) + $display (""PASSED""); +end +endmodule +" +"module add32(sum, cOut, clock, a, b, cIn); + + input clock; + input a, b, cIn; + output sum, cOut; + + reg [31:0] a, b; + reg cIn; + wire [31:0] sum; + wire cOut; + + always @(posedge clock) + //{cOut, sum} = a + b + cIn; + assign sum = a + b + cIn; + +endmodule + +////////////////////////// + +module main; + + reg CLOCK; + reg [31:0] A, B; + reg C_IN; + reg [31:0] SUM; + wire C_OUT; + + + add32 myAdder(SUM, C_OUT, CLOCK, A, B, C_OUT); + + always #1 CLOCK = ~ CLOCK; + + initial + begin + $monitor($time,, "" CLOCK=%d, A=%x, B=%x, C_IN=%d -- SUM=%x, C_OUT=%d"", +CLOCK, A, B, C_IN, SUM, C_OUT); + end + + initial + begin + CLOCK = 0; + A = 32\'h00000001; + B = 32\'h00000002; + C_IN = 1\'b0; + #20 $finish; + end + +endmodule +" +"// Check behaviour with out-of-range and undefined array indices +// on LHS of non-blocking procedural assignment. + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + +reg array1[2:1]; +reg array2[1:0]; + +`ifndef VLOG95 +real array3[2:1]; +real array4[1:0]; +`endif + +integer index; + +reg failed; + +initial begin + failed = 0; + + array1[1] <= 1\'b0; + array1[2] <= 1\'b0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array1[0] <= 1\'b1; // Constant out of bounds select may be an error +`endif + #1 $display(""array = %b %b"", array1[2], array1[1]); + if ((array1[1] !== 1\'b0) || (array1[2] !== 1\'b0)) failed = 1; + + array1[1] <= 1\'b0; + array1[2] <= 1\'b0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array1[3] <= 1\'b1; // Constant out of bounds select may be an error +`endif + #1 $display(""array = %b %b"", array1[2], array1[1]); + if ((array1[1] !== 1\'b0) || (array1[2] !== 1\'b0)) failed = 1; + + array2[0] <= 1\'b0; + array2[1] <= 1\'b0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array2[\'bx] <= 1\'b1; // Constant undefined out of bounds select may be an error +`endif + #1 $display(""array = %b %b"", array2[1], array2[0]); + if ((array2[0] !== 1\'b0) || (array2[1] !== 1\'b0)) failed = 1; + + index = 0; + array1[1] <= 1\'b0; + array1[2] <= 1\'b0; + array1[index] <= 1\'b1; + #1 $display(""array = %b %b"", array1[2], array1[1]); + if ((array1[1] !== 1\'b0) || (array1[2] !== 1\'b0)) failed = 1; + + index = 3; + array1[1] <= 1\'b0; + array1[2] <= 1\'b0; + array1[index] <= 1\'b1; + #1 $display(""array = %b %b"", array1[2], array1[1]); + if ((array1[1] !== 1\'b0) || (array1[2] !== 1\'b0)) failed = 1; + + index = \'bx; + array2[0] <= 1\'b0; + array2[1] <= 1\'b0; + array2[index] <= 1\'b1; + #1 $display(""array = %b %b"", array2[1], array2[0]); + if ((array2[0] !== 1\'b0) || (array2[1] !== 1\'b0)) failed = 1; + +`ifndef VLOG95 + array3[1] <= 0.0; + array3[2] <= 0.0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array3[0] <= 1.0; // Constant out of bounds select may be an error +`endif + #1 $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + + array3[1] <= 0.0; + array3[2] <= 0.0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array3[3] <= 1.0; // Constant out of bounds select may be an error +`endif + #1 $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + + array4[0] <= 0.0; + array4[1] <= 0.0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array4[\'bx] <= 1.0; // Constant undefined out of bounds select may be an error +`endif + #1 $display(""array = %0g %0g"", array4[1], array4[0]); + if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1; + + index = 0; + array3[1] <= 0.0; + array3[2] <= 0.0; + array3[index] <= 1.0; + #1 $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + + index = 3; + array3[1] <= 0.0; + array3[2] <= 0.0; + array3[index] <= 1.0; + #1 $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + + index = \'bx; + array4[0] <= 0.0; + array4[1] <= 0.0; + array4[index] <= 1.0; + #1 $display(""array = %0g %0g"", array4[1], array4[0]); + if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1; +`endif + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"// Regression test for GitHub issue #33. + +module tb; + + reg [3:0] mem [0:15] [0:15]; + + task cycle; + input [3:0] a, b, c; + reg [3:0] tmp; + begin + tmp = mem[a][b]; + mem[a][b] = c; + $display(""a=%d, b=%d, c=%d -> old=%d, new=%d"", a, b, c, tmp, mem[a][b]); + end + endtask + + initial begin + cycle( 7, 0, 1); + cycle(15, 0, 2); + cycle( 7, 0, 3); + cycle(15, 0, 4); + end + +endmodule +" +"module top; + reg pass; + wire out; + reg drive_val; + reg oe_n; + reg [1:0] pull_vec; + + bufif0 (out, drive_val, oe_n); + assign (pull0, pull1) out = pull_vec[0]; + + initial begin + pass = 1\'b1; + pull_vec = 2\'b00; + oe_n = 1\'b0; + + // Drive is selected. + drive_val = 1\'b0; + #1; + if (out !== drive_val) begin + $display(""Failed to drive 0, got %b"", out); + pass = 1\'b0; + end + + drive_val = 1\'b1; + #1; + if (out !== drive_val) begin + $display(""Failed to drive 1, got %b"", out); + pass = 1\'b0; + end + + // The pull is selected (low). + oe_n = 1\'b1; + drive_val = 1\'b0; + #1; + if (out !== pull_vec[0]) begin + $display(""Failed pull #1, expected 1\'b0, got %b"", out); + pass = 1\'b0; + end + + drive_val = 1\'b1; + #1; + if (out !== pull_vec[0]) begin + $display(""Failed pull #2, expected 1\'b0, got %b"", out); + pass = 1\'b0; + end + + // The pull is selected (high). + pull_vec = 2\'b11; + drive_val = 1\'b0; + #1; + if (out !== pull_vec[0]) begin + $display(""Failed pull #3, expected 1\'b1, got %b"", out); + pass = 1\'b0; + end + + drive_val = 1\'b1; + if (out !== pull_vec[0]) begin + $display(""Failed pull #4, expected 1\'b1, got %b"", out); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"/* + * This test is based on pr1508882. The output from the test module + * should produce a 5 bit result, and the widths of the vectors are + * correct for that assumption. But if an implicit part select is + * mitted in the assign out=tmp, then the vector widths can break. + */ +module main; + + reg [5:0] a, b; + wire [4:0] sum; + + test dut (.out(sum), .a(a), .b(b)); + + wire [5:0] padded = {1\'b0, sum}; + + initial begin + a = 1; + b = 7; + + #1 if (padded !== (a+b)) begin +\t $display(""FAILED -- sum=%0d, a=%0d, b=%0d"", sum, a, b); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main + +module test (output [4:0] out, input [5:0] a, b); + + wire [5:0] tmp = a + b; + assign out = tmp; + +endmodule // test +" +"module top; + reg pass = 1; + initial begin + if (4\'sd2 < -2) begin + $display(""Failed for operator <""); + pass = 0; + end + if (4\'sd2 <= -2) begin + $display(""Failed for operator <=""); + pass = 0; + end + if (-2 > 4\'sd2) begin + $display(""Failed for operator >""); + pass = 0; + end + if (-2 >= 4\'sd2) begin + $display(""Failed for operator >=""); + pass = 0; + end + if (pass) $display(""PASSED""); + end +endmodule +" +"module test; + + reg signed [31:0] mydata; + + + initial + begin + mydata = -6; + repeat ( 11 ) + begin + add_one(mydata); + $display(""mydata = %0d"", mydata); + end + $finish(0); + end + + +task add_one; + inout signed [31:0] myotherdata; + begin + myotherdata = myotherdata + 1; + end +endtask + +endmodule +" +"/* Verify that a tail recursive real ternary expression does not + * overflow the available thread words. */ +module top; + reg pass; + real vout; + integer j; + + always @(j) begin + vout = (j == 0) ? 0.0 : + (j == 1) ? 0.1 : + (j == 2) ? 0.2 : + (j == 3) ? 0.3 : + (j == 4) ? 0.4 : + (j == 5) ? 0.5 : + (j == 6) ? 0.6 : + (j == 7) ? 0.7 : + (j == 8) ? 0.8 : + (j == 9) ? 0.9 : + (j == 10) ? 1.0 : + (j == 11) ? 1.1 : + (j == 12) ? 1.2 : + (j == 13) ? 1.3 : + (j == 14) ? 1.4 : + (j == 15) ? 1.5 : + (j == 16) ? 1.6 : + (j == 17) ? 1.7 : + (j == 18) ? 1.8 : + (j == 19) ? 1.9 : 0.0; + end + + initial begin + pass = 1\'b1; + + for (j=0; j<20; j=j+1) begin + #1; + if (vout != j/10.0) begin + $display(""Failed: at %0d, got %f"", j, vout); + pass = 1\'b0; + end + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module test (); + reg pass = 1\'b1; + reg d; + real f = 0.0; + + always @(d) assign f = 0; + + initial begin + // Verify the initial value. + #1; + if (f != 0.0) begin + $display(""Failed initial value, expected 0.0, got %f"", f); + pass = 1\'b0; + end + + // Verify the value can change. + #1 f = 1.0; + if (f != 1.0) begin + $display(""Failed value change, expected 1.0, got %f"", f); + pass = 1\'b0; + end + + // Verify that the assign changed the value and that a normal assign + // is blocked. + #1 d = 0; + #1 f = 1.0; + if (f != 0.0) begin + $display(""Failed assign holding, expected 0.0, got %f"", f); + pass = 1\'b0; + end + + // Verify that the release holds the previous value. + #1 deassign f; + if (f != 0.0) begin + $display(""Failed release holding, expected 0.0, got %f"", f); + pass = 1\'b0; + end + + // Verify that the value can be changed after a release. + #1 f = 1.0; + if (f != 1.0) begin + $display(""Failed release, expected 1.0, got %f"", f); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"\r +module main;\r +\r + int variable = 0;\r +\r + // A void function returns no value, so can be called\r + // like a task, but without a warning about unused\r + // results.\r + function void test_incr(input int arg);\r + variable = variable + arg;\r + endfunction // test_incr\r +\r + initial begin\r + variable = 0;\r + test_incr(5);\r + if (variable !== 5) begin\r +\t $display(""FAILED"");\r +\t $finish;\r + end\r + $display(""PASSED"");\r + end\r +\r +endmodule // main\r +" +"module test; + parameter SIZE = 3; + + parameter PVALUE = 12; + localparam LVALUE = 88; + + enum byte unsigned { UVAL[256] } unsignedbyte_enum; + enum byte { SVAL[100] } signedbyte_enum; + enum { ADD = 10, SUB[5], JMP[6:8]} E1; // page 28 LRM + enum { REGISTER[2] = 1, REGISTER[2:4] = 10 } vr; // page 28 LRM + enum { P[5] = 12 /*PVALUE*/, Q, S[3] = 88/*LVALUE*/} par_enum; + + initial begin + // 1. Default anonymous enum data type should be int + // don\'t know yet how to quickly check this + // + // 1. Checking initialisations + // + // a. If the first name is not assigned it should be zero + if (UVAL0 !== 8\'h0 || SVAL0 !== 8\'h0) + begin + $display (""FAILED - First un-assigned element of enum type was not zero""); + $finish; + end + // b. Checking initials E1 and vr + if (ADD != 10 || REGISTER0 != 1) + begin + $display (""FAILED - First initialised elements of enums E1 and vr were not elaborated properly""); + $finish; + end + // A name without a value is automatically assigned and increment of the value of the + // previous name (Section 4.10 LRM) + // c. checking initial values for SUB (0-4) in E1 + if (SUB0 != 11 || SUB1 != 12 || SUB2 != 13 || SUB3 != 14 || SUB4 != 15) + begin + $display (""FAILED - Initialised elements SUB (0-4) in enum E1 were not elaborated properly""); + $finish; + end + // c. checking initial values for JMP (6-8) in E1 + if (JMP6 != 16 || JMP7 != 17 || JMP8 != 18) + begin + $display (""FAILED - Initialised elements (6-8) JMP in enum E1 were not elaborated properly""); + $finish; + end + // c. checking initial values in vr + if (REGISTER1 != 2 || REGISTER2 != 10 || REGISTER3 != 11 || REGISTER4 != 12) + begin + $display (""FAILED - Initialised elements REGISTER (1-4) in enum vr were not elaborated properly""); + $finish; + end + // c. checking hand-picked values in unsignedbyte_enum + if (UVAL23 != 23 || UVAL91 != 91 || UVAL138 != 138 || UVAL207 != 207) + begin + $display (""FAILED - Initialised some UVAL in enum unsignedbyte_enum were not elaborated properly""); + $display (""UVAL23 = %0d, UVAL91 = %0d, UVAL138 = %0d, UVAL207 = %0d"", UVAL23, UVAL91, UVAL138, UVAL207); + $finish; + end + // c. checking hand-picked values in signedbyte_enum + if (SVAL7 != 7 || SVAL19 != 19 || SVAL87 != 87) + begin + $display (""FAILED - Initialised some SVAL in enum signedbyte_enum were not elaborated properly""); + $display (""SVAL7 = %0d, SVAL19 = %0d, SVAL87 = %0d"", SVAL7, UVAL91, SVAL19, SVAL87); + $finish; + end + // c. checking final values in unsignedbyte_enum and signedbyte_enum + if (UVAL255 != 255 || SVAL99 != 99) + begin + $display (""FAILED - Initialised final values UVAL and SVAL did not elaborate properly""); + $display (""UVAL255 = %0d, SVAL99 = %0d"", UVAL255, SVAL99); + $finish; + end + // constants elaborated from parameter + if (P0 != PVALUE+0 || P1 != PVALUE+1 || P2 != PVALUE+2 || P3 != PVALUE+3 || P4 != PVALUE + 4 || Q != PVALUE+5) + begin + $display (""FAILED - Initialised values P in par_enum were not elaborated properly""); + $finish; + end + // constants elaborated from localparam + if (S0 != LVALUE+0 || S1 != LVALUE+1 || S2 != LVALUE+2) + begin + $display (""FAILED - Initialised values S in par_enum were not elaborated properly""); + $finish; + end + #1; + // checking num method + if (unsignedbyte_enum.num != 256 || signedbyte_enum.num != 100 || + E1.num != 9 || vr.num != 5 || par_enum.num != 9) + begin + $display (""FAILED - The num method does not report as expected""); + $finish; + end + $display (""PASSED""); + end + + +endmodule +" +" +typedef struct packed { + logic b; +} single_bit; + +typedef struct packed { + single_bit b1; + single_bit b2; +} two_bits; + +module simple(input two_bits b2in, + output two_bits b2out); + assign b2out.b1.b = b2in.b1.b; +endmodule // simple + +module main; + + two_bits src; + wire two_bits dst; + + simple copy(src, dst); + assign dst.b2.b = src.b2.b; + + initial begin + src.b1.b = 1\'b1; + src.b2.b = 1\'b0; + #1 ; // Let values settle. + $display(""src=%b (s.b. 10), dst=%b (s.b. 10)"", src, dst); + if (src !== 2\'b10 || dst !== 2\'b10) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""PASSED""); + $finish; + end + +endmodule // main +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always case ( reg_value) case_item1; case_item2; case_item3; endcase +// D: + +module main ; + +reg [3:0] value1,value2,value3; + +initial +\tbegin + #0; + value3 = 0; + #3 ;\t\t\t\t\t// t=3 + value1 = 4\'b0000 ;\t// Picked up at time 4 + #5 ;\t\t\t\t // check at time 8 + if(value2 != 4\'b0) + begin + $display(""FAILED - always3.1.6A - case 0 at %t"",$time); + value3 = 1; + end + #1 ;\t\t\t\t\t// Picked up at time 10 + value1 = 4\'b0001 ;\t// Set at time 9. + + #5 ;\t\t\t\t\t// Check at time 14 + if(value2 != 4\'b0001) + begin + $display(""FAILED - always3.1.6A - case 1 at %t"",$time); + value3 = 1; + end + #1;\t\t\t\t\t// Picked up at time 16 + value1 = 4\'b0010;\t// Changed at time 15. + + #5;\t\t\t\t\t// Check at time 20... + if(value2 != 4\'b0010) + begin + $display(""FAILED - always3.1.6A - case 2 at %t"",$time); + value3 = 1; + end + + #10; + if(value3 == 0) + $display(""PASSED""); +\t $finish; + end + +always case (value1) + 4\'b0000: begin + #3 ; + value2 = 4\'b0000 ; + #3 ; + end + 4\'b0001: begin + #3 ; + value2 = 4\'b0001 ; + #3 ; + end + 4\'b0010: begin + #3 ; + value2 = 4\'b0010 ; + #3 ; + end + default: #2 ; + endcase + + +endmodule +" +"/* + * Author: Oswaldo Cadenas + */ +module test; + +parameter S = 9; +parameter K = 3; +parameter L = 2**(S-K); +parameter N = 2**(S-1); + +reg signed [S-1:0] a_reg; +bit signed [S-1:0] a_bit; +byte signed a_byte; +shortint signed a_short; +int signed a_int; +longint signed a_long; +byte signed amount; +byte unsigned pos; +int temp; +int i; + +initial begin + // test for style ""a += some"" statement on type reg + for (i = 0; i < N; i = i+1) begin + a_reg = $random % L; + amount = $random % K; + #1; + temp = a_reg + amount; + a_reg += amount; + #1; + //$display (""a = %0d, amount = %0d, temp = %0d"", a, amount, temp); + if (temp !== a_reg) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_reg - amount; + a_reg -= amount; + #1; + if (temp !== a_reg) begin + $display(""FAILED""); + $finish; + end + end + + // test for style ""a += some"" statement on type bit + for (i = 0; i < N; i = i+1) begin + a_bit = $random % L; + amount = $random % K; + #1; + temp = a_bit + amount; + a_bit += amount; + #1; + if (temp !== a_bit) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_bit - amount; + a_bit -= amount; + #1; + if (temp !== a_bit) begin + $display(""FAILED""); + $finish; + end + end // for + + // test for style ""a += some"" statement on type byte + for (i = 0; i < N; i = i+1) begin + a_byte = $random % L; + amount = $random % K; + #1; + temp = a_byte + amount; + a_byte += amount; + #1; + if (temp !== a_byte) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_byte - amount; + a_byte -= amount; + #1; + if (temp !== a_byte) begin + $display(""FAILED""); + $finish; + end + end // for + + // test for style ""a += some"" statement on type shortint + for (i = 0; i < N; i = i+1) begin + a_short = 2*($random % L); + amount = 2*($random % K); + #1; + temp = a_short + amount; + a_short += amount; + #1; + if (temp !== a_short) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_short - amount; + a_short -= amount; + #1; + if (temp !== a_short) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_short * amount; + a_short *= amount; + #1; + if (temp !== a_short) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_short / amount; + a_short /= amount; + #1; + if (temp !== a_short) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_short % amount; + a_short %= amount; + #1; + if (temp !== a_short) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_short & amount; + a_short &= amount; + #1; + if (temp !== a_short) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_short | amount; + a_short |= amount; + #1; + if (temp !== a_short) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_short ^ amount; + a_short ^= amount; + #1; + if (temp !== a_short) begin + $display(""FAILED""); + $finish; + end + #1; + pos = 2*({$random} % K); + temp = a_short << pos; + a_short <<= pos; + #1; + if (temp !== a_short) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_short >> pos; + a_short >>= pos; + #1; + if (temp !== a_short) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_short <<< pos; + a_short <<<= pos; + #1; + if (temp !== a_short) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_short >>> pos; + a_short >>>= pos; + #1; + if (temp !== a_short) begin + $display(""FAILED""); + $finish; + end + end // for + + // test for style ""a += some"" statement on type int + for (i = 0; i < N; i = i+1) begin + a_int = 4*($random % L); + amount = 4*($random % K); + #1; + temp = a_int + amount; + a_int += amount; + #1; + if (temp !== a_int) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_int - amount; + a_int -= amount; + #1; + if (temp !== a_int) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_int * amount; + a_int *= amount; + #1; + if (temp !== a_int) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_int / amount; + a_int /= amount; + #1; + if (temp !== a_int) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_int % amount; + a_int %= amount; + #1; + if (temp !== a_int) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_int & amount; + a_int &= amount; + #1; + if (temp !== a_int) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_int | amount; + a_int |= amount; + #1; + if (temp !== a_int) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_int ^ amount; + a_int ^= amount; + #1; + if (temp !== a_int) begin + $display(""FAILED""); + $finish; + end + #1; + pos = 4*({$random} % K); + temp = a_int << pos; + a_int <<= pos; + #1; + if (temp !== a_int) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_int >> pos; + a_int >>= pos; + #1; + if (temp !== a_int) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_int <<< pos; + a_int <<<= pos; + #1; + if (temp !== a_int) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_int >>> pos; + a_int >>= pos; + #1; + if (temp !== a_int) begin + $display(""FAILED""); + $finish; + end + end // for + + // test for style ""a += some"" statement on type longint + for (i = 0; i < N; i = i+1) begin + a_long = 8*($random % L); + amount = 8*($random % K); + #1; + temp = a_long + amount; + a_long += amount; + #1; + if (temp !== a_long) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_long - amount; + a_long -= amount; + #1; + if (temp !== a_long) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_long * amount; + a_long *= amount; + #1; + if (temp !== a_long) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_long / amount; + a_long /= amount; + #1; + if (temp !== a_long) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_long % amount; + a_long %= amount; + #1; + if (temp !== a_long) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_long & amount; + a_long &= amount; + #1; + if (temp !== a_long) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_long | amount; + a_long |= amount; + #1; + if (temp !== a_long) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_long ^ amount; + a_long ^= amount; + #1; + if (temp !== a_long) begin + $display(""FAILED""); + $finish; + end + #1; + pos = 8*({$random} % K); + temp = a_long << pos; + a_long <<= pos; + #1; + if (temp !== a_long) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_long >> pos; + a_long >>= pos; + #1; + if (temp !== a_long) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_long <<< pos; + a_long <<<= pos; + #1; + if (temp !== a_long) begin + $display(""FAILED""); + $finish; + end + #1; + temp = a_long >>> pos; + a_long >>= pos; + #1; + if (temp !== a_long) begin + $display(""FAILED""); + $finish; + end + end // for + + $display(""PASSED""); + $finish; +end + +endmodule +" +"module bug(); + +wire [7:0] b; + +assign b = $abs(missing); + +endmodule +" +"`begin_keywords ""1364-2005"" +module test(); + +reg signed [15:0] a; +reg signed [7:0] b; +reg signed [31:0] expect; +wire signed [31:0] actual; + +reg signed [127:0] long_x; +real real_x; + +assign actual = a ** b; + +initial begin + for (a = -32768; a < 32767; a = a + 1) begin:outer_loop + long_x = 1; + for (b = 0; b < 127; b = b + 1) begin:inner_loop + real_x = $itor(a) ** $itor(b); + if (real_x < 0.0) real_x = -real_x; + if (real_x >= 2.0**128.0) disable outer_loop; + expect = long_x; + #0; // wait for net propagation + if (actual !== expect) begin + $display(""FAILED : %0d ** %0d = %0d not %0d"", a, b, expect, actual); + $finish; + end + long_x = long_x * a; + end + end + $display(""PASSED""); +end + +endmodule +`end_keywords +" +"// SystemVerilog parameter type test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test (); + + // logic vector + logic [15:0] lv; + + // error counter + bit err = 0; + + // system clock (does not have any real function in the test) + logic clk = 1; + + always #5 clk = ~clk; + + // counters + int cnt; + int cnt_bit ; + int cnt_byte; + int cnt_int ; + int cnt_ar1d; + int cnt_ar2d; + + // sizes + int siz_bit ; + int siz_byte; + int siz_int ; + int siz_ar1d; + int siz_ar2d; + + // add all counters + assign cnt = cnt_bit + cnt_byte + cnt_int + cnt_ar1d + cnt_ar2d; + + // finish report + initial begin + // some unnecessary delay + wait (cnt); + + // check if variable sizes are correct + if (siz_bit != 1) begin $display(""FAILED -- siz_bit = %0d"", siz_bit ); err=1; end + if (siz_byte != 8) begin $display(""FAILED -- siz_byte = %0d"", siz_byte); err=1; end + if (siz_int != 32) begin $display(""FAILED -- siz_int = %0d"", siz_int ); err=1; end + if (siz_ar1d != 24) begin $display(""FAILED -- siz_ar1d = %0d"", siz_ar1d); err=1; end + if (siz_ar2d != 16) begin $display(""FAILED -- siz_ar2d = %0d"", siz_ar2d); err=1; end + + if (!err) $display(""PASSED""); + $finish(); + end + + // instances with various types + mod_typ #(.TYP (bit )) mod_bit (clk, cnt_bit [ 1-1:0], siz_bit ); + mod_typ #(.TYP (byte )) mod_byte (clk, cnt_byte[ 8-1:0], siz_byte); + mod_typ #(.TYP (int )) mod_int (clk, cnt_int [32-1:0], siz_int ); + mod_typ #(.TYP (bit [23:0] )) mod_ar1d (clk, cnt_ar1d[24-1:0], siz_ar1d); + mod_typ #(.TYP (bit [3:0][3:0])) mod_ar2d (clk, cnt_ar2d[16-1:0], siz_ar2d); + +endmodule // test + + +module mod_typ #( + parameter type TYP = byte +)( + input logic clk, + output TYP cnt = 0, + output int siz +); + + always @ (posedge clk) + cnt <= cnt + 1; + + assign siz = $bits (cnt); + +endmodule +" +"`begin_keywords ""1364-2005"" +module main; + wire y1, y2, y3; + reg a; + + initial begin + $monitor($time , "" y1 = %d, y2 = %d, y3 = %d, a = %d"", y1, y2, y3, a); + #1 a = 1; + #1 a = 0; + end + + sub s1(y1, y2, y3, a); + +endmodule // main + +module sub(y1, y2, y3, a); + output y1, y2, y3; + input a; + reg y1, y2, y3; + reg int; + + always @(*) begin + y1 <= a; + y2 <= y1; + + int <= a; + y3 <= int; + end + +endmodule +`end_keywords +" +" +module ivtest + ( + input [3:0]\tx, + input [3:0]\ty, + output [3:0]\tz + ); + + assign z = x ^ y; + +endmodule // ivtest + +" +"module main; + +reg [2:0] a; + +wire e0 = a==3\'h0; wire n0 = a!=3\'h0; +wire e1 = a==3\'h1; wire n1 = a!=3\'h1; +wire e2 = a==3\'h2; wire n2 = a!=3\'h2; +wire e3 = a==3\'h3; wire n3 = a!=3\'h3; +wire e4 = a==3\'h4; wire n4 = a!=3\'h4; +wire e5 = a==3\'h5; wire n5 = a!=3\'h5; +wire e6 = a==3\'h6; wire n6 = a!=3\'h6; +wire e7 = a==3\'h7; wire n7 = a!=3\'h7; +initial begin +\tfor (a=0; a<7; a=a+1) begin +\t\t#1; +\t\t$display(""a="",a); +\t\t$display("" 0 %d %d"", e0, n0); +\t\t$display("" 1 %d %d"", e1, n1); +\t\t$display("" 2 %d %d"", e2, n2); +\t\t$display("" 3 %d %d"", e3, n3); +\t\t$display("" 4 %d %d"", e4, n4); +\t\t$display("" 5 %d %d"", e5, n5); +\t\t$display("" 6 %d %d"", e6, n6); +\t\t$display("" 7 %d %d"", e7, n7); +\tend +end + +endmodule +" +"module test(); + +integer count = 0; + +initial begin + repeat (10.4) begin + count = count + 1; + $display(count); + end + if (count === 10) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"(* this_is_module_bar *) +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + always @(posedge clk) + if (rst) out <= 1\'d0; + else out <= ~inp; + +endmodule + +(* this_is_module_foo *) +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output wire out; + + bar bar_instance (clk, rst, inp, out); + + initial begin + $display(""PASSED""); + end + +endmodule + +" +"/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version.will need a Picture Elements Binary Software + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program demonstrates the mixing of reg and memories in l-value + * contatenations. + */ +module main; + + reg [3:0] mem [2:0]; + reg\t a, b; + + initial begin + mem[0] = 0; + mem[1] = 0; + mem[2] = 0; + + {b, mem[1], a} <= 6\'b0_0000_1; + #1 + if (a !== 1\'b1) begin +\t $display(""FAILED -- a = %b"", a); +\t $finish; + end + if (mem[1] !== 4\'b0000) begin +\t $display(""FAILED -- mem[1] = %b"", mem[1]); +\t $finish; + end + if (b !== 1\'b0) begin +\t $display(""FAILED -- b = %b"", b); +\t $finish; + end + + {b, mem[1], a} <= 6\'b0_1111_0; + #1 + if (a !== 1\'b0) begin +\t $display(""FAILED -- a = %b"", a); +\t $finish; + end + if (mem[0] !== 4\'b0000) begin +\t $display(""FAILED -- mem[0] - %b"", mem[0]); +\t $finish; + end + if (mem[1] !== 4\'b1111) begin +\t $display(""FAILED -- mem[1] = %b"", mem[1]); +\t $finish; + end + if (b !== 1\'b0) begin +\t $display(""FAILED -- b = %b"", b); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"/* + * Copyright (c) 2000 Steve Wilson (stevew@home.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Verify signed constant assignment to an integer. + */ +module test; + +integer I0,I1; +reg [15:0] R0,R1; +reg [3:0] error; + +initial + begin + error = 0; + I0 = -4\'d12; + I1 = -32\'d12; + if(I0 !== 32\'hfffffff4) + begin + $display(""FAILED - negative decimal assignment failed. I0 s/b fffffff4, is %h"", + I0); + error =1; + end + if(I1 !== 32\'hfffffff4) + begin + $display(""FAILED - negative decimal assignment failed. I1 s/b fffffff4, is %h"", + I1); + error = 1; + end + if(error === 0) + $display(""PASSED""); + end + +endmodule +" +"module main; + + reg [3:0] count; + reg\t CLOCK; + reg\t RSTn, SETn; + + (* ivl_synthesis_off *) + initial begin + CLOCK = 0; + RSTn = 0; + SETn = 1; + + #1 CLOCK = 1; + #1 CLOCK = 0; + + if (count !== 4\'b0000) begin +\t $display(""FAILED -- initial reset doesn\'t""); +\t $finish; + end + + RSTn = 1; + #1 CLOCK = 1; + #1 CLOCK = 0; + #1 CLOCK = 1; + #1 CLOCK = 0; + + if (count !== 4\'b0010) begin +\t $display(""FAILED -- count up is %b"", count); +\t $finish; + end + + SETn = 0; + #1 ; + + if (count !== 4\'b1101) begin +\t $display(""FAILED -- Aset failed: count=%b"", count); +\t $finish; + end + + SETn = 1; + #1 CLOCK = 1; + #1 CLOCK = 0; + + if (count !== 4\'b1110) begin +\t $display(""FAILED -- Aset didn\'t release: count=%b"", count); +\t $finish; + end + + RSTn = 0; + #1 ; + if (count !== 4\'b0000) begin +\t $display(""FAILED -- Aclr failed: count=%b"", count); +\t $finish; + end + + $display(""PASSED""); + $finish; + end + + (* ivl_synthesis_on *) + always @(posedge CLOCK or negedge RSTn or negedge SETn) + begin +\tif (!RSTn) +\t count =0; //async clear +\telse +\t if (!SETn) +\t count = 4\'b1101; //async set +\t else +\t count = count + 1; + end + +endmodule +" +"module t; +reg [7:0] x = 1; + +initial #5 x = 2; +always @(x) #5 x = 3; + +final begin + if (x == 3) $display(""x =%d, PASSED"", x); + $finish(0); + $display(""FAILED! Executed past $finish in final block!""); +end +endmodule + +module t2; +final $display(""t2 final""); +endmodule +" +"/* + * blocksyn1.v + * This tests synthesis where statements in a block override previous + * statements in a block and also uses other previous statements in the + * block. Note in this example that the flag assignment is completely + * overruled by the conditional that is directly after it. + */ +module main; + + reg [1:0] out; + reg\t flag; + reg [1:0] sel; + + (* ivl_synthesis_on, ivl_combinational *) + always @* + begin +\tout = 2\'b00; +\tcase (sel) +\t 2\'b00: out = 2\'b11; +\t 2\'b01: out = 2\'b10; +\t 2\'b10: out = 2\'b01; +\t // out for sel==2\'b11 should be inherited from previous statement +\tendcase // case(sel) + +\t// This flag is completely overridden by the conditional, so +\t// the synthesizer should drop it. +\tflag = 1\'b0; +\tif (out == 2\'b00) +\t flag = 1\'b1; +\telse +\t flag = 1\'b0; + end + + reg [2:0] idx; + reg\t test; + + (* ivl_synthesis_off *) + initial begin + for (idx = 0 ; idx < 7 ; idx = idx + 1) begin +\t sel = idx[1:0]; +\t #1 if (out !== ~sel) begin +\t $display(""FAILED -- sel=%b, out=%b, flag=%b"", sel, out, flag); +\t $finish; +\t end + +\t test = (out == 2\'b00)? 1\'b1 : 1\'b0; + +\t if (test !== flag) begin +\t $display(""FAILED -- test=%b, sel=%b, out=%b, flag=%b"", +\t\t test, sel, out, flag); +\t $finish; +\t end + end // for (idx = 0 ; idx < 7 ; idx = idx + 1) + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"`begin_keywords ""1364-2005"" + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass = 1\'b1; +// reg [3:0] var = 4\'b1001; + wire [3:0] var = 4\'b1001; +// parameter [3:0] var = 4\'b1001; + reg [3:0] part; + reg [5:0] big; + + initial begin +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = var[1:-2]; // should be 01xx. + if (part !== 4\'b01xx) begin + $display(""part select [1:-2] failed, expected 4\'b01xx, got %b"", part); + pass = 1\'b0; + end + + part = var[5:2]; // should be xx10. + if (part !== 4\'bxx10) begin + $display(""part select [5:2] failed, expected 4\'bxx10, got %b"", part); + pass = 1\'b0; + end + + big = var[4:-1]; // should be x10100101x. + if (big !== 6\'bx1001x) begin + $display(""part select [4:-1] failed, expected 6\'bx1001x, got %b"", big); + pass = 1\'b0; + end +`endif + + if (pass) $display(""PASSED""); + end +endmodule +`end_keywords +" +"// Check behaviour with out-of-range and undefined array indices +// on LHS of procedural continuous (reg) assignment. + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + +reg [1:0] array1[2:1]; +reg [1:0] array2[1:0]; + +reg [1:0] var1; + +`ifndef VLOG95 +real array3[2:1]; +real array4[1:0]; + +real var2; +`endif + +reg failed; + +initial begin + failed = 0; + + array1[1] = 2\'d0; + array1[2] = 2\'d0; + + array2[0] = 2\'d0; + array2[1] = 2\'d0; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign array1[0] = 2\'d1; + #1 $display(""array = %h %h"", array1[2], array1[1]); + if ((array1[1] !== 2\'d0) || (array1[2] !== 2\'d0)) failed = 1; + deassign array1[0]; +`endif + +/* This is not supported at present + assign array1[1] = 2\'d1; + #1 $display(""array = %h %h"", array1[2], array1[1]); + if ((array1[1] !== 2\'d1) || (array1[2] !== 2\'d0)) failed = 1; + deassign array1[1]; + + assign array1[2] = var1; + var1 = 2\'d1; + #1 $display(""array = %h %h"", array1[2], array1[1]); + if ((array1[1] !== 2\'d0) || (array1[2] !== 2\'d1)) failed = 1; + var1 = 2\'d2; + #1 $display(""array = %h %h"", array1[2], array1[1]); + if ((array1[1] !== 2\'d0) || (array1[2] !== 2\'d2)) failed = 1; + deassign array1[2]; +*/ + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign array1[3] = var1; + #1 $display(""array = %h %h"", array1[2], array1[1]); + if ((array1[1] !== 2\'d0) || (array1[2] !== 2\'d0)) failed = 1; + deassign array1[3]; + + assign array2[\'bx] = 2\'d1; + #1 $display(""array = %h %h"", array2[1], array2[0]); + if ((array2[0] !== 2\'d0) || (array2[1] !== 2\'d0)) failed = 1; + deassign array2[\'bx]; +`endif + +`ifndef VLOG95 + array3[1] = 0.0; + array3[2] = 0.0; + + array4[0] = 0.0; + array4[1] = 0.0; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign array3[0] = 1.0; + #1 $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + deassign array3[0]; +`endif + +/* This is not supported at present + assign array3[1] = 1.0; + #1 $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 1.0) || (array3[2] != 0.0)) failed = 1; + deassign array3[1]; + + assign array3[2] = var2; + var2 = 1.0; + #1 $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 1.0)) failed = 1; + var2 = 2.0; + #1 $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 2.0)) failed = 1; + deassign array3[2]; +*/ + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign array3[3] = var2; + #1 $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + deassign array3[3]; + + assign array4[\'bx] = 1.0; + #1 $display(""array = %0g %0g"", array4[1], array4[0]); + if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1; + deassign array4[\'bx]; +`endif +`endif + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module top; + tb #(1024) dut(); + defparam dut.Y = 2048; +endmodule + +module tb; + reg pass = 1\'b1; + parameter Z = 256; + parameter Y = 128; + parameter B = $clog2(Z); + localparam C = $clog2(Y); + + initial begin + if (B !== 10) begin + $display(""FAILED: parameter value, expected 10, got %0d"", B); + pass = 1\'b0; + end + if (C !== 11) begin + $display(""FAILED: localparam value, expected 11, got %0d"", C); + pass = 1\'b0; + end + if (pass) $display(""PASSED""); + end +endmodule +" +"module negative_genvar; + +wire signed [3:0] value[-7:7]; + +genvar i; + +for (i = 7; i >= -7; i = i - 1) begin:genloop + assign value[i] = i; +end + +integer j; + +reg fail = 0; + +initial begin + #0; + for (j = -7; j <= 7; j = j + 1) begin + $display(""%d"", value[j]); + if (value[j] !== j) fail = 1; + end + + if (fail) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module top; + reg [1:0] lv, rv; + reg pass; + wire res, resb; + + assign res = lv ==? rv; + assign resb = lv !=? rv; + + initial begin + pass = 1\'b1; + + lv = 2\'b00; + rv = 2\'b00; + #1; + if (res !== 1\'b1) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'b1"", lv, rv, res); + pass = 1\'b0; + end + + if (resb !== 1\'b0) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'b0"", lv, rv, resb); + pass = 1\'b0; + end + + #1; + lv = 2\'b00; + rv = 2\'b01; + #1; + if (res !== 1\'b0) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'b0"", lv, rv, res); + pass = 1\'b0; + end + if (resb !== 1\'b1) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'b1"", lv, rv, resb); + pass = 1\'b0; + end + + #1; + lv = 2\'b10; + rv = 2\'b00; + #1; + if (res !== 1\'b0) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'b0"", lv, rv, res); + pass = 1\'b0; + end + if (resb !== 1\'b1) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'b1"", lv, rv, resb); + pass = 1\'b0; + end + + #1; + lv = 2\'b1x; + rv = 2\'b00; + #1; + if (res !== 1\'b0) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'b0"", lv, rv, res); + pass = 1\'b0; + end + if (resb !== 1\'b1) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'b1"", lv, rv, resb); + pass = 1\'b0; + end + + #1; + lv = 2\'b0x; + rv = 2\'b00; + #1; + if (res !== 1\'bx) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'bx"", lv, rv, res); + pass = 1\'b0; + end + if (resb !== 1\'bx) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'bx"", lv, rv, resb); + pass = 1\'b0; + end + + #1; + lv = 2\'b00; + rv = 2\'b0x; + #1; + if (res !== 1\'b1) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'b1"", lv, rv, res); + pass = 1\'b0; + end + if (resb !== 1\'b0) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'b0"", lv, rv, resb); + pass = 1\'b0; + end + + #1; + lv = 2\'b01; + rv = 2\'b0x; + #1; + if (res !== 1\'b1) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'b1"", lv, rv, res); + pass = 1\'b0; + end + if (resb !== 1\'b0) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'b0"", lv, rv, resb); + pass = 1\'b0; + end + + #1; + lv = 2\'b0z; + rv = 2\'b0x; + #1; + if (res !== 1\'b1) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'b1"", lv, rv, res); + pass = 1\'b0; + end + if (resb !== 1\'b0) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'b0"", lv, rv, resb); + pass = 1\'b0; + end + + #1; + lv = 2\'b0x; + rv = 2\'b0x; + #1; + if (res !== 1\'b1) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'b1"", lv, rv, res); + pass = 1\'b0; + end + if (resb !== 1\'b0) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'b0"", lv, rv, resb); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module test(); + +localparam size1 = 4; +localparam size2 = 6; +localparam size3 = 8; + +localparam [5:0] value1 = 6\'h3f; +localparam signed [5:0] value2 = 6\'h3f; + +reg [31:0] result; + +reg failed = 0; + +initial begin + result = size1\'(value1) + \'d0; + $display(""%h"", result); + if (result !== 32\'h0000000f) failed = 1; + + result = size1\'(value1) + \'sd0; + $display(""%h"", result); + if (result !== 32\'h0000000f) failed = 1; + + result = size1\'(value2) + \'d0; + $display(""%h"", result); + if (result !== 32\'h0000000f) failed = 1; + + result = size1\'(value2) + \'sd0; + $display(""%h"", result); + if (result !== 32\'hffffffff) failed = 1; + + result = size2\'(value1) + \'d0; + $display(""%h"", result); + if (result !== 32\'h0000003f) failed = 1; + + result = size2\'(value1) + \'sd0; + $display(""%h"", result); + if (result !== 32\'h0000003f) failed = 1; + + result = size2\'(value2) + \'d0; + $display(""%h"", result); + if (result !== 32\'h0000003f) failed = 1; + + result = size2\'(value2) + \'sd0; + $display(""%h"", result); + if (result !== 32\'hffffffff) failed = 1; + + result = size3\'(value1) + \'d0; + $display(""%h"", result); + if (result !== 32\'h0000003f) failed = 1; + + result = size3\'(value1) + \'sd0; + $display(""%h"", result); + if (result !== 32\'h0000003f) failed = 1; + + result = size3\'(value2) + \'d0; + $display(""%h"", result); + if (result !== 32\'h000000ff) failed = 1; + + result = size3\'(value2) + \'sd0; + $display(""%h"", result); + if (result !== 32\'hffffffff) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule // main +" +"module top(); + tri tdo, tdo_out; + reg tdo_oe; + + assign tdo = tdo_oe ? tdo_out : 1\'bz; + + assign tdo_out = 1\'b1; + + // Check undriven value is Z + initial begin + tdo_oe = 0; + #1; + if (tdo !== 1\'bz) begin + $display(""FAILED -- tdo not z when tdo_oe = 0""); + $finish; + end + + tdo_oe = 1; + #1; + #1; + if (tdo !== 1\'b1) begin + $display(""FAILED -- tdo not tdo_out when tdo_oe = 0""); + $finish; + end + + $display(""PASSED""); + end + +endmodule // top +" +"// Regression test for bug #973 + +module test(); + +typedef enum bit { A0, A1 } A; +typedef enum logic { B0, B1 } B; +typedef enum reg { C0, C1 } C; + +A enum1; +B enum2; +C enum3; + +initial begin + if ($bits(enum1) == 1 && $bits(enum2) == 1 && $bits(enum3) == 1) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"// Test case statements inside a constant function +module constfunc12(); + +function [1:0] onehot_to_binary(input [3:1] x); + +case (x) + default : onehot_to_binary = 0; + 3\'b001 : onehot_to_binary = 1; + 3\'b010 : onehot_to_binary = 2; + 3\'b100 : onehot_to_binary = 3; +endcase + +endfunction + +function [1:0] find_first_one(input [3:1] x); + +casez (x) + 3\'b1?? : find_first_one = 3; + 3\'b01? : find_first_one = 2; + 3\'b001 : find_first_one = 1; + default : find_first_one = 0; +endcase + +endfunction + +function [1:0] find_first_zero(input [3:1] x); + +casex (x) + 3\'b0zz : find_first_zero = 3; + 3\'b10x : find_first_zero = 2; + 3\'b110 : find_first_zero = 1; + default : find_first_zero = 0; +endcase + +endfunction + +function [1:0] match_real_value(input real x); + +case (x) + 1.0 : match_real_value = 1; + 2.0 : match_real_value = 2; + 3.0 : match_real_value = 3; + default : match_real_value = 0; +endcase + +endfunction + +localparam otb0 = onehot_to_binary(3\'b000); +localparam otb1 = onehot_to_binary(3\'b001); +localparam otb2 = onehot_to_binary(3\'b010); +localparam otb3 = onehot_to_binary(3\'b100); +localparam otb4 = onehot_to_binary(3\'b101); +localparam otb5 = onehot_to_binary(3\'b10z); +localparam otb6 = onehot_to_binary(3\'bx01); + +localparam ffo0 = find_first_one(3\'b000); +localparam ffo1 = find_first_one(3\'b001); +localparam ffo2 = find_first_one(3\'b01x); +localparam ffo3 = find_first_one(3\'b1xx); +localparam ffo4 = find_first_one(3\'bxx1); +localparam ffo5 = find_first_one(3\'b00z); +localparam ffo6 = find_first_one(3\'b0zz); +localparam ffo7 = find_first_one(3\'bzzz); + +localparam ffz0 = find_first_zero(3\'b111); +localparam ffz1 = find_first_zero(3\'b110); +localparam ffz2 = find_first_zero(3\'b10x); +localparam ffz3 = find_first_zero(3\'b0xx); +localparam ffz4 = find_first_zero(3\'bzzz); +localparam ffz5 = find_first_zero(3\'b11x); +localparam ffz6 = find_first_zero(3\'b1xx); +localparam ffz7 = find_first_zero(3\'bxxx); + +localparam mrv0 = match_real_value(0.0); +localparam mrv1 = match_real_value(1.0); +localparam mrv2 = match_real_value(2.0); +localparam mrv3 = match_real_value(3.0); +localparam mrv4 = match_real_value(4.0); + +reg failed = 0; + +initial begin + $display(""%d"", otb0); if (otb0 !== 2\'d0) failed = 1; + $display(""%d"", otb1); if (otb1 !== 2\'d1) failed = 1; + $display(""%d"", otb2); if (otb2 !== 2\'d2) failed = 1; + $display(""%d"", otb3); if (otb3 !== 2\'d3) failed = 1; + $display(""%d"", otb4); if (otb4 !== 2\'d0) failed = 1; + $display(""%d"", otb5); if (otb5 !== 2\'d0) failed = 1; + $display(""%d"", otb6); if (otb6 !== 2\'d0) failed = 1; + $display(""""); + $display(""%d"", ffo0); if (ffo0 !== 2\'d0) failed = 1; + $display(""%d"", ffo1); if (ffo1 !== 2\'d1) failed = 1; + $display(""%d"", ffo2); if (ffo2 !== 2\'d2) failed = 1; + $display(""%d"", ffo3); if (ffo3 !== 2\'d3) failed = 1; + $display(""%d"", ffo4); if (ffo4 !== 2\'d0) failed = 1; + $display(""%d"", ffo5); if (ffo5 !== 2\'d1) failed = 1; + $display(""%d"", ffo6); if (ffo6 !== 2\'d2) failed = 1; + $display(""%d"", ffo7); if (ffo7 !== 2\'d3) failed = 1; + $display(""""); + $display(""%d"", ffz0); if (ffz0 !== 2\'d0) failed = 1; + $display(""%d"", ffz1); if (ffz1 !== 2\'d1) failed = 1; + $display(""%d"", ffz2); if (ffz2 !== 2\'d2) failed = 1; + $display(""%d"", ffz3); if (ffz3 !== 2\'d3) failed = 1; + $display(""%d"", ffz4); if (ffz4 !== 2\'d3) failed = 1; + $display(""%d"", ffz5); if (ffz5 !== 2\'d1) failed = 1; + $display(""%d"", ffz6); if (ffz6 !== 2\'d2) failed = 1; + $display(""%d"", ffz7); if (ffz7 !== 2\'d3) failed = 1; + $display(""""); + $display(""%d"", mrv0); if (mrv0 !== 2\'d0) failed = 1; + $display(""%d"", mrv1); if (mrv1 !== 2\'d1) failed = 1; + $display(""%d"", mrv2); if (mrv2 !== 2\'d2) failed = 1; + $display(""%d"", mrv3); if (mrv3 !== 2\'d3) failed = 1; + $display(""%d"", mrv4); if (mrv4 !== 2\'d0) failed = 1; + $display(""""); + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"// Extended version of original test case, covering part-driven operands +// for all logical operations. +module pr2974051; + +wire [7:0] a; +wire [7:0] b; +reg\t c; + +assign a[5:2] = 4\'b0101; +assign b[5:2] = 4\'b1010; + +wire [7:0] d = c ? b : a; + +wire [7:0] e = a & b; +wire [7:0] f = a | b; +wire [7:0] g = a ^ b; + +wire [7:0] h = a; +wire [7:0] i = ~a; + +reg fail; + +initial begin + fail = 0; + + c = 0; + #1 $display(""%b"", d); + if (d !== 8\'bzz0101zz) fail = 1; + c = 1; + #1 $display(""%b"", d); + if (d !== 8\'bzz1010zz) fail = 1; + + #1 $display(""%b"", e); + if (e !== 8\'bxx0000xx) fail = 1; + + #1 $display(""%b"", f); + if (f !== 8\'bxx1111xx) fail = 1; + + #1 $display(""%b"", g); + if (g !== 8\'bxx1111xx) fail = 1; + + #1 $display(""%b"", h); + if (h !== 8\'bzz0101zz) fail = 1; + + #1 $display(""%b"", i); + if (i !== 8\'bxx1010xx) fail = 1; + + if (fail) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"`ifdef __ICARUS__ + `define SUPPORT_REAL_MODULUS_IN_IVTEST +`endif + +module test(); + +function real pre_inc(input real x); +begin + ++x; + pre_inc = x; +end +endfunction + +function real pre_dec(input real x); +begin + --x; + pre_dec = x; +end +endfunction + +function real post_inc(input real x); +begin + x++; + post_inc = x; +end +endfunction + +function real post_dec(input real x); +begin + x--; + post_dec = x; +end +endfunction + +localparam pre_inc_5 = pre_inc(5); +localparam pre_dec_5 = pre_dec(5); + +localparam post_inc_5 = post_inc(5); +localparam post_dec_5 = post_dec(5); + +function real add2(input real x); +begin + x += 2; + add2 = x; +end +endfunction + +function real sub2(input real x); +begin + x -= 2; + sub2 = x; +end +endfunction + +function real mul2(input real x); +begin + x *= 2; + mul2 = x; +end +endfunction + +function real div2(input real x); +begin + x /= 2; + div2 = x; +end +endfunction + +`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST +function real mod2(input real x); +begin + x %= 2; + mod2 = x; +end +endfunction +`endif + +localparam add2_5 = add2(5); +localparam sub2_5 = sub2(5); +localparam mul2_5 = mul2(5); +localparam div2_5 = div2(5); +`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST +localparam mod2_5 = mod2(5); +`endif + +function real add3(input real x); +begin + add3 = x; + add3 += 3; +end +endfunction + +function real sub3(input real x); +begin + sub3 = x; + sub3 -= 3; +end +endfunction + +function real mul3(input real x); +begin + mul3 = x; + mul3 *= 3; +end +endfunction + +function real div4(input real x); +begin + div4 = x; + div4 /= 4; +end +endfunction + +`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST +function real mod3(input real x); +begin + mod3 = x; + mod3 %= 3; +end +endfunction +`endif + +localparam add3_5 = add3(5); +localparam sub3_5 = sub3(5); +localparam mul3_5 = mul3(5); +localparam div4_5 = div4(5); +`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST +localparam mod3_5 = mod3(5); +`endif + +reg failed = 0; + +initial begin + $display(""pre_inc_5 = %0f"", pre_inc_5); + if (pre_inc_5 != pre_inc(5)) failed = 1; + if (pre_inc_5 != 6.0) failed = 1; + + $display(""pre_dec_5 = %0f"", pre_dec_5); + if (pre_dec_5 != pre_dec(5)) failed = 1; + if (pre_dec_5 != 4.0) failed = 1; + + $display(""post_inc_5 = %0f"", post_inc_5); + if (post_inc_5 != post_inc(5)) failed = 1; + if (post_inc_5 != 6.0) failed = 1; + + $display(""post_dec_5 = %0f"", post_dec_5); + if (post_dec_5 != post_dec(5)) failed = 1; + if (post_dec_5 != 4.0) failed = 1; + + $display(""add2_5 = %0f"", add2_5); + if (add2_5 != add2(5)) failed = 1; + if (add2_5 != 7.0) failed = 1; + + $display(""sub2_5 = %0f"", sub2_5); + if (sub2_5 != sub2(5)) failed = 1; + if (sub2_5 != 3.0) failed = 1; + + $display(""mul2_5 = %0f"", mul2_5); + if (mul2_5 != mul2(5)) failed = 1; + if (mul2_5 != 10.0) failed = 1; + + $display(""div2_5 = %0f"", div2_5); + if (div2_5 != div2(5)) failed = 1; + if (div2_5 != 2.5) failed = 1; + +`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST + $display(""mod2_5 = %0f"", mod2_5); + if (mod2_5 != mod2(5)) failed = 1; + if (mod2_5 != 1.0) failed = 1; +`endif + + $display(""add3_5 = %0f"", add3_5); + if (add3_5 != add3(5)) failed = 1; + if (add3_5 != 8.0) failed = 1; + + $display(""sub3_5 = %0f"", sub3_5); + if (sub3_5 != sub3(5)) failed = 1; + if (sub3_5 != 2.0) failed = 1; + + $display(""mul3_5 = %0f"", mul3_5); + if (mul3_5 != mul3(5)) failed = 1; + if (mul3_5 != 15.0) failed = 1; + + $display(""div4_5 = %0f"", div4_5); + if (div4_5 != div4(5)) failed = 1; + if (div4_5 != 1.25) failed = 1; + +`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST + $display(""mod3_5 = %0f"", mod3_5); + if (mod3_5 != mod3(5)) failed = 1; + if (mod3_5 != 2.0) failed = 1; +`endif + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"// Icarus 0.6 AND snapshot 20020728 +// ----------------------------- +// (1) force to nets not supported +// (2) comment the force statement and the release statement will cause +// the compiler to fail silently (no messages, no a.out) +// +// Icarus snapshot 20020817 +// ------------------------ +// Runs fine IFF the whole of a bus is set, cannot force individual bits +// (Fails with a rather incomprehensible error) +// +// To run this, incant: +// iverilog tt.v +// (adding -Wall doesn\'t help) +// vvp a.out (if a.out is generated!) +// +// +// Veriwell +// --------- +// Runs fine IFF the whole of a bus is set, cannot force individual bits +// & crashes if a release of an individual bit is attempted. +// +// To run this, incant: +// veridos tt.v (or use the GUI) +// + +module top (); + + reg [31:0] ii; + reg fail; + reg [1:0] a; + wire [1:0] junk = a; + wire [1:0] junkbus = a; + + initial begin + a = 2\'b01; + #5; a = 2\'b10; + #10; a = 2\'b11; + end + + initial begin + #2; + force junk = 0; + force junkbus[0] = 0; + #10; + release junk; + #5; + release junkbus[0]; + end + + initial begin + $display(""""); + $display(""expecting junk,junkbus to be 1 at T=1""); + $display(""then changing to 0 at T=2""); + $display(""then junk is 0 from T=3 to T=11, while""); + $display(""junkbus changes to 2 at T=5 and remains 2 through to T=16""); + $display(""junk changes to 2 at T=12""); + $display(""then 2 from T=13 to T=14""); + $display(""then changing to 3 at T=15""); + $display(""then 3 from T=16 on""); + $display(""junkbus changes to 3 at T=17 and remains 3 from then on""); + $display(""""); + for(ii = 0; ii < 20; ii = ii + 1) begin + #0; // avoid race + // junk + if((ii == 1) && (junk !== 1)) fail = 1; + if((ii > 2) && (ii < 12) && (junk !== 0)) fail = 1; + if((ii > 12) && (ii < 14) && (junk !== 2\'b10)) fail = 1; + if((ii > 15) && (junk !== 2\'b11)) fail = 1; + // junkbus + if((ii == 1) && (junkbus !== 2\'b01)) fail = 1; + if((ii > 2) && (ii < 4) && (junkbus !== 2\'b00)) fail = 1; + if((ii > 5) && (ii < 17) && (junkbus !== 2\'b10)) fail = 1; + if((ii > 17) && (junkbus !== 2\'b11)) fail = 1; + $display(""time: %0t, a: %b, junk: %b, junkbus: %b"",$time,a,junk,junkbus); + #1; + end + if(fail) $display(""\ +\\t--------- force test failed ---------\ +""); + else $display(""\ +\\t--------- force test passed ---------\ +""); + end + +endmodule +" +"`define STOP_HERE +`define my_macro(a0, a1=HERE, a2=HERE) \\ + `ifdef STOP_``a1 \\ + $display(a0); \\ + `elsif STOP_``a2 \\ + $display(a0, a1); \\ + `else \\ + $display(a0, a1, a2); \\ + `endif \\ + +module test(); + +initial begin + `my_macro(""No args""); + `my_macro(""Args = %s"", ""hello""); + `my_macro(""Args = %0d, %s"", 123, ""hello""); +end + + +endmodule +" +" +module main; + + reg [2:0] X; + wire q_nand, q_nor, q_xnor, q_not; + + test_logic DUT(.A(X[0]), .B(X[1]), .q_nand(q_nand), .q_nor(q_nor), +\t\t .q_xnor(q_xnor), .q_not(q_not)); + + initial begin + for (X = 0 ; X < 4 ; X = X+1) begin +\t #1 /* Let gates settle. */; +\t if (q_nand !== (X[0] ~& X[1])) begin +\t $display(""FAILED -- q_nand=%b, X=%b"", q_nand, X[1:0]); +\t $finish; +\t end +\t if (q_nor !== (X[0] ~| X[1])) begin +\t $display(""FAILED -- q_nor=%b, X=%b"", q_nor, X[1:0]); +\t $finish; +\t end +\t if (q_xnor !== (X[0] ~^ X[1])) begin +\t $display(""FAILED -- q_xnor=%b, X=%b"", q_xnor, X[1:0]); +\t $finish; +\t end +\t if (q_not !== (~X[0])) begin +\t $display(""FAILED -- q_not=%b, X=%b"", q_not, X[0]); +\t $finish; +\t end + + end + $display(""PASSED""); + end + +endmodule // main +" +"module main; + + real rval; + + wire [63:0] wbits = $realtobits(rval); + reg [63:0] rbits; + + initial begin + rval = 1.5; + rbits = $realtobits(rval); + + #1 /* Let the wbits value propagate */ ; + + if (rbits !== 64\'h3ff80000_00000000) begin +\t $display(""FAILED -- rbits=%h"", rbits); +\t $finish; + end + + if (wbits !== rbits) begin +\t $display(""FAILED -- rval=%f, rbits=%h, wbits=%h"", rval, rbits, wbits); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"reg [7:0] v; + +module dut(input wire [7:0] i = v, output wire [7:0] o); + +assign o = i; + +endmodule + +module tb(); + +wire [7:0] result; + +dut dut(,result); + +initial begin + #1; + if (result === 10) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"package p_defs; + class a_class; + int id_; + + function new(int id); + id_ = id; + endfunction + + task display(); + $display(""This is class %0d."", id_); + endtask + + endclass + +endpackage + +// This should print the following: +// This is class 2. +// This is class 1. +module top; + import p_defs::a_class; + + a_class ac1; + a_class ac2; + initial begin + ac1 = new(1); + ac2 = new(2); + ac2.display(); + ac1.display(); + end +endmodule +" +"// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for VHDL procedure calls + +module vhdl_procedure_test; +logic run; +vhdl_procedure dut(run); + +initial begin + run = 0; + #1 run = 1; +end +endmodule +" +"module top; + reg result; + + initial begin + + result = $onehot0(top); + result = $onehot0(""a string""); + result = $onehot0(4\'b001, 1\'b0); + + end + +endmodule +" +"module test; + +wire [7:0] val[3:0]; + +genvar i; + +for (i = 3; i >= 0; i = i - 1) begin + assign val[i] = i; +end + +integer j; + +reg failed = 0; + +initial begin + for (j = 3; j >= 0; j = j - 1) begin + $display(val[j]); + if (val[j] != j) failed = 1; + end + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"// This is currently unsupported, but is legal code. +module test(); + +typedef enum { a, b, c } enum_type; + +enum_type enum_value; + +initial begin + enum_value = enum_type'(1); +end + +endmodule +" +"module main; + + reg [8:0] val; + + ornor8 dut (.O_OR(o_or), .O_NOR(o_nor), +\t .I0(val[0]), .I1(val[1]), .I2(val[2]), .I3(val[3]), +\t .I4(val[4]), .I5(val[5]), .I6(val[6]), .I7(val[7])); + + initial begin + for (val = 0 ; val[8] == 0 ; val = val+1) begin +\t #1 if (o_or !== |val[7:0]) begin +\t $display(""FAILED -- |%b --> %b"", val[7:0], o_or); +\t $finish; +\t end + +\t if (o_nor !== ~|val[7:0]) begin +\t $display(""FAILED -- ~|%b --> %b"", val[7:0], o_nor); +\t $finish; +\t end + end + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate task calling a function + + +module main; + +reg var1,var2; +reg in1; +reg error; + +function foo ; + input in1 ; + foo = in1 ; +endfunction + +task my_task ; + input in1,in2; + output out1,out2; + begin + out1 = foo(~foo(in1)) ; + out2 = foo(in2) ; + end +endtask + +initial + begin + error = 0; + my_task(1\'b1,1\'b0,var1,var2); + if(~(~var1 & ~var2)) + begin + $display(""FAILED - task 3.14E task calling a function (1)""); + error = 1; + end + + in1 = 0; + my_task(~in1,~in1,var1,var2); + if(~(~var1 & var2)) + begin + $display(""FAILED - task 3.14E task calling a function(2)""); + error = 1; + end + + in1 = 0; + my_task(in1,in1,var1,var2); + if(~(var1 & ~var2)) + begin + $display(""FAILED - task 3.14E task calling a function(3)""); + error = 1; + end + + if(error == 0) + $display(""PASSED""); + end + +endmodule // main +" +"module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign (strong1,weak0) value1[3:0] = 4\'b1010; + +nmos buffer[7:0](value2, value1, 1\'b1); + +assign (strong1,weak0) value2 = 8\'b00110011; + +initial begin + #2 $display(""%b %b"", value1, value2); + if (value2 === 8\'b00111011) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Event list_of_event_identifiers, -> event_identifier. +// + +module main (); + +reg [31:0] v1,v2,v3; +reg error; +event event_1, event_2; + +always @ event_1 + begin + v1 = v1 + 1; + end + +always @ event_2 + begin + v2 = 1; + end + +initial + begin + error = 0; + v1 = 0; + v2 = 0; + v3 = 0; +// $dumpfile(""test.vcd""); +// $dumpvars(0,main); + + #(5); + -> event_1; + v3 = 1; + #1 ;\t\t // Need delay here or race with always schedule + if(v1 !== 1) + begin + $display(""FAILED - event3.15 event1 trigger didn\'t occur""); + error = 1; + end + + #5 -> event_2; + #1 ; + if(v2 !== 1) + begin + $display(""FAILED - event3.15 event2 trigger didn\'t occur""); + error = 1; + end + v3 = 2; + + #5 -> event_1; + #1 ; + if(v1 !== 2) + begin + $display(""FAILED - event3.15 event1 trigger didn\'t occur""); + error = 1; + end + v3 = 3; + #5 ; + + if(error === 0) + $display(""PASSED""); + end + +endmodule +" +"/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This problem shows the case of a function with no input ports, + * and also a function with a parameter (not a port). + * + * A function without an argument is an error, so this should fail. + */ + +module main; + + function [3:0] test; + + parameter a = 3; + reg [a:0] out; + + begin +\t out = a; +\t test[3:0] = out[3:0]; + end + + endfunction + + reg [3:0] tmp; + initial begin + tmp = test(); + if (tmp !== 4\'b0011) begin +\t $display(""FAILED -- tmp == %b"", tmp); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Test the ability to resolve resolve tri-state drivers onto a single + * signal. Use multiple continuous assignments to a wire to create + * multiple drivers, and use the ?: operator to tri-state the driven + * value based on the sel value. + */ + +module main; + + wire [1:0] out; + + reg [1:0] sel = 2\'bzz; + reg [1:0] v0 = 0; + reg [1:0] v1 = 1; + reg [1:0] v2 = 2; + reg [1:0] v3 = 3; + + assign out = (sel == 2\'b00)? v0 : 2\'bz; + assign out = (sel == 2\'b01)? v1 : 2\'bz; + assign out = (sel == 2\'b10)? v2 : 2\'bz; + assign out = (sel == 2\'b11)? v3 : 2\'bz; + + initial begin + + #1 if (out !== 2\'bxx) begin +\t $display(""FAILED -- sel==%b, out==%b"", sel, out); +\t $finish; + end + + sel = 0; + #1 if (out !== 2\'b00) begin +\t $display(""FAILED -- sel==%b, out==%b, v0==%b"", sel, out, v0); +\t $finish; + end + + sel = 1; + #1 if (out !== 2\'b01) begin +\t $display(""FAILED -- sel==%b, out==%b"", sel, out); +\t $finish; + end + + sel = 2; + #1 if (out !== 2\'b10) begin +\t $display(""FAILED -- sel==%b, out==%b"", sel, out); +\t $finish; + end + + sel = 3; + #1 if (out !== 2\'b11) begin +\t $display(""FAILED -- sel==%b, out==%b"", sel, out); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +" + +typedef enum logic [3:0] { WORD0, WORD1, WORD9=\'b1001, WORDC=\'b1100 } word_t; + +typedef union packed { + logic [3:0] bits; + word_t words; +} bits_t; + +module main; + + bits_t foo; + + initial begin + foo.bits = \'b1001; + if (foo.bits !== \'b1001) begin +\t $display(""FAILED -- foo.bits=%b"", foo.bits); +\t $finish; + end + + if (foo.words !== WORD9) begin +\t $display(""FAILED -- foo.words=%b"", foo.words); +\t $finish; + end + + foo.words = WORDC; + if (foo.words !== WORDC) begin +\t $display(""FAILED -- foo.words=%b"", foo.words); +\t $finish; + end + if (foo.bits !== \'b1100) begin +\t $display(""FAILED -- foo.bits=%b"", foo.bits); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"module top; + // An implicit value cannot be over range (compile time error). + enum bit[1:0] {a = 3, b , c} val; + + initial $display(""FAILED""); +endmodule +" +"module top; + wire real sml; + wire real big; + wire real prec; + + assign sml = 1e-20; + assign big = 1e20; + assign prec = 0.123456789; + + initial $display(""big: %g, small: %g, precision: %0.11f"", big, sml, prec); +endmodule +" +"module main; + parameter WORD_WID = 3; + parameter WORD_CNT = 8; + + reg [WORD_WID-1: 0] mem [0:WORD_CNT-1], tmp; + + integer\t idx, jdx; + initial begin + for (idx = 0 ; idx < WORD_CNT ; idx = idx+1) +\tmem[idx] = idx; + + for (idx = 0 ; idx < WORD_CNT ; idx = idx+1) begin +\t tmp = idx; + +\t if (mem[idx][2:1] !== tmp[2:1]) begin +\t $display(""FAILED -= mem[%d][2:1]=%b, tmp[2:1]=%b"", +\t\t idx, mem[idx][2:1], tmp[2:1]); +\t $finish; +\t end + +\t if (mem[idx][1:0] !== tmp[1:0]) begin +\t $display(""FAILED -= mem[%d][1:0]=%b, tmp[1:0]=%b"", +\t\t idx, mem[idx][1:0], tmp[1:0]); +\t $finish; +\t end + +\t for (jdx = 0 ; jdx < WORD_WID ; jdx = jdx+1) +\t if (mem[idx][jdx +:2] !== tmp[jdx +:2]) begin +\t $display(""FAILED -- mem[%d][%d +:2]=%b, tmp[%d +:2]=%b"", +\t\t idx, jdx, mem[idx][jdx+:2], jdx, tmp[jdx+:2]); +\t $finish; +\t end + end + + $display(""PASSED""); + end +endmodule // main +" +"module foo(input x); +parameter n = 0; +pulldown p1(x); +initial #n $display(""x(%0d) : %b"", n, x); +endmodule + +module tb; +wire y; +wire z; +foo #1 bar1(1\'b0); +foo #2 bar2(1\'b1); +foo #3 bar3(1\'bz); +foo #4 bar4(y); +foo #5 bar5({z}); +initial #6 $display(""y : "", y); +initial #7 $display(""z : "", z); +endmodule +" +"module array_assign(); + parameter MSB = 1; + integer ii; + reg signed [2:0] ar_reg[0:MSB]; + wire signed [4:0] as_wr; + + // compiled with ""-g2 -g2x"" + // FAILED at this line + assign as_wr = {{2{ar_reg[0][2]}},ar_reg[1]}; + + always @(as_wr) + for(ii=0; ii<(MSB+1); ii=ii+1) + begin + $display("" %t ar_reg=%0d w_assign=%0d"", $time, ar_reg[ii], as_wr); + $display("" %t ar_reg[0]=3\'b%3b ar_reg[1]=3\'b%3b"", $time, ar_reg[0], ar_reg[1]); + $display("" %t as_wr=5\'b%5b"", $time, as_wr); + end + + initial + begin + $display(""\ +*** module %m **************************************""); + + #10; + for(ii=0; ii<(MSB+1); ii=ii+1) + ar_reg[ii] <= 3\'sd1; + #10; + for(ii=0; ii<(MSB+1); ii=ii+1) + ar_reg[ii] <= 3\'sd0; + + $display(""\ +\ +""); + end + +endmodule + +/* expected output - START +module array_assign + 10 ar_reg=1 w_assign=1 + 10 ar_reg[0]=3\'b001 ar_reg[1]=3\'b001 + 10 as_wr=5\'b00001 + 10 ar_reg=1 w_assign=1 + 10 ar_reg[0]=3\'b001 ar_reg[1]=3\'b001 + 10 as_wr=5\'b00001 + + + + 20 ar_reg=0 w_assign=0 + 20 ar_reg[0]=3\'b000 ar_reg[1]=3\'b000 + 20 as_wr=5\'b00000 + 20 ar_reg=0 w_assign=0 + 20 ar_reg[0]=3\'b000 ar_reg[1]=3\'b000 + 20 as_wr=5\'b00000 +expected output - END */ +" +"module main; + reg [2:0] value; + + initial begin + for(value = 0; value <= 6; value = value + 1) begin + $displayh(value,, 1<<(6-value)); + end + end +endmodule +" +"module main; + + reg [2:0] Q; + reg\t clk, clr, up, down; + + (*ivl_synthesis_off *) + initial begin + clk = 0; + up = 0; + down = 0; + clr = 1; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin +\t $display(""FAILED""); +\t $finish; + end + + up = 1; + clr = 0; + + #1 clk = 1; + #1 clk = 0; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 3\'b010) begin +\t $display(""FAILED""); +\t $finish; + end + + up = 0; + down = 1; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 3\'b001) begin +\t $display(""FAILED""); +\t $finish; + end + + down = 0; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 3\'b001) begin +\t $display(""FAILED""); +\t $finish; + end + + $display(""PASSED""); + $finish; + end + + /* + * This statement models a snythesizable UP/DOWN counter. The up + * and down cases are enabled by up and down signals. If both + * signals are absent, the synthesizer should take the implicit + * case that Q <= Q; + */ + (* ivl_synthesis_on *) + always @(posedge clk, posedge clr) + if (clr) begin + Q <= 0; + end else begin +\tif (up) +\t Q <= Q + 1; +\telse if (down) +\t Q <= Q - 1; + end + +endmodule // main +" +"module check (input unsigned [22:0] a, b, c); + wire unsigned [22:0] int_AB; + + assign int_AB = a / b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB != c) begin + $display(""ERROR""); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [22:0] A, B); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; B = 1; + for (i=0; i= ((z + 1)*(z + 1))) +\t\t begin +\t\t $display(""test=%d x=%d, y=%d ERROR: y is too small"", idx, A, Z); +\t\t $display(""FAILED""); +\t\t $finish; +\t\t end +\t end +\t else +\t begin +\t\t$display (""Could not verify above number""); +\t end + +\tend + +\t$display (""Running tests Amax=%d random input numbers"", Amax); + +\tfor (idx = 0 ; idx < Amax; idx = 1+ idx) begin + A = $random; + // A = A - ((A / Amax) * Amax);\t //this is needed only if <32 bit + + //A = idx; //sequential -- comment out to get random tests + +\t if (A < 1<<(w-1)) begin + + reset_dut; + run_dut; + + //$display(""%d: x=%d, y=%d"", idx, A, Z); + +\t a = A; +\t z = Z; + +\t if (a < (z *z)) begin +\t\t $display(""test=%d x=%d, y=%d ERROR:y is too big"", idx, A, Z); +\t\t $display(""FAILED""); +\t\t $finish; +\t end + +\t if (z<65535) // at this number y*y overflows, so cannot test this way +\t\tbegin +\t\t if (a >= ((z + 1)*(z + 1))) +\t\t begin +\t\t\t$display(""test=%d x=%d, y=%d ERROR: y is too small"", idx, A, Z); +\t\t\t$display(""FAILED""); +\t\t\t$finish; +\t\t end +\t\tend +\t else +\t\tbegin +\t\t $display (""Could not verify above number""); +\t\tend + + + //$display(""%d: x=%d, y=%d"", idx, A, Z); +\t if (idx%1000 == 0) $display(""Finished %d tests"", idx); +\t end // if (A < Amax) begin +\tend +\t$display (""PASSED""); +\t$finish; + + end + +endmodule +`end_keywords +" +"/* + * This is frpm PR#138. It is supposed to generate an error. + */ +module bug; + wire[1:0] dout; + wire[1:0] din; + + assign dout = din[3:2]; + /* foo.vl:9: bit/part select [3:2] out of range for bug.din */ +endmodule +" +"// +// Test the specify block (pr1587634) +// + +`timescale 1 ns / 1 ps + +/* +module top(); + reg in; + initial begin + in = 0; + #10 in = 1; + end + + inv1 g1 (out, in); +endmodule +*/ + +module inv1 (z, a); + output z; + input a; + + not g1(z, a); + + specify + specparam tpd_a_z_lh = 0.400; + specparam tpd_a_z_hl = 0.300:0.400:0.500; + + (a -=> z) = (tpd_a_z_lh, tpd_a_z_hl); + + endspecify +endmodule +" +"module loop(); + +reg [3:0] a; +reg [3:0] b; +reg [3:0] c; +reg [3:0] d; + +integer i; + +always @* begin + for (i = 0; i < 4; i = i + 1) begin + b[i] = a[i]; + $display(""process 1 : %0d %b"", i, b); + end +end + +always @* begin + for (i = 0; i < 4; i = i + 1) begin + d[i] = c[i]; + $display(""process 2 : %0d %b"", i, d); + end +end + +initial begin + #0; + a = 5; + #0; + c = 6; + #0; + if ((b === 5) && (c === 6)) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate defparam with list +// + +module NameA (); + +parameter ident0 = 12; +parameter ident1 = 20 ; + +wire [31:0] value0 = ident0; +wire [31:0] value1 = ident1; + +endmodule + +module main (); + +defparam main.testmodA.ident0 = 15; // Validate single val +defparam main.testmodB.ident1 = 16, // Validate list of vals + main.testmodB.ident0 = 17; // Validate single val + +reg error; + +NameA testmodA (); +NameA testmodB (); + +initial + begin + error = 0; + # 1; + if(main.testmodA.value0 !== 15) + begin + error = 1; + $display(""FAILED - defparam.v main.testmodA.value0 != 15""); + end + # 1; + if(main.testmodA.value1 !== 20) + begin + error = 1; + $display(""FAILED - defparam.v main.testmodA.value1 != 20""); + end + # 1; + if(main.testmodB.value0 !== 17) + begin + error = 1; + $display(""FAILED - defparam.v main.testmodB.value0 != 17""); + end + # 1; + if(main.testmodB.value1 !== 16) + begin + error = 1; + $display(""FAILED - defparam.v main.testmodB.value1 != 16""); + end + # 1; + if(error == 0) + $display(""PASSED""); + end + + +endmodule +" +"module top; + + integer fail; + reg cmd, reset; + + initial begin + #1; + reset = 0; + fail = 0; + #1; + cmd = 0; + #2; + reset = 1; + #2; + cmd = 1; + #2; + cmd = 0; + #2; + reset = 0; + #2; + reset = 1; + #4; + if(fail) $display(""***** disable test FAILED *****""); + else $display(""***** disable test PASSED *****""); + $finish(0); + end + + always @(cmd) begin: command_block + fork + begin + #0; // avoid fork race +\tdisable command_block_reset; + end + begin: command_block_reset +\t@(reset); +\tfail = 1; +\tdisable command_block; + end + join + end + +endmodule +" +"module top; + reg a, pass; + wire x, y, ab; + + assign (weak1, weak0) x = (a === 1\'b1) ? 1\'b0 : 1\'b1; + assign y = a; + // We need this since Icarus currently has a bug when forcing from + // an expression (it only uses the value when the force ran). + assign ab = ~a; + + tran (x, y); + + initial begin + // $monitor ($realtime,, x,y,,a); + pass = 1\'b1; + // Check matching values. + #1 if ( x !== 1\'bx || y !== 1\'bx) begin + $display(""Failed initial value, expected 1\'bx, 1\'bx, got %b %b"", x, y); + pass = 1\'b0; + end + #1 a = 1\'b0; + #1 if ( x !== 1\'b0 || y !== 1\'b0) begin + $display(""Failed same value, expected 1\'b0, 1\'b0, got %b %b"", x, y); + pass = 1\'b0; + end + #1 a = 1\'b1; + #1 if ( x !== 1\'b1 || y !== 1\'b1) begin + $display(""Failed same value, expected 1\'b1, 1\'b1, got %b %b"", x, y); + pass = 1\'b0; + end + // Check force with opposite values. + #1 force x = ab; + #1 if ( x !== 1\'b0 || y !== 1\'bx) begin + $display(""Failed force value, expected 1\'b0, 1\'bx, got %b %b"", x, y); + pass = 1\'b0; + end + #1 a = 1\'b0; + #1 if ( x !== 1\'b1 || y !== 1\'bx) begin + $display(""Failed force value, expected 1\'b1, 1\'bx, got %b %b"", x, y); + pass = 1\'b0; + end + // Now release. + #1 release x; + #1 if ( x !== 1\'b0 || y !== 1\'b0) begin + $display(""Failed release value, expected 1\'b0, 1\'b0, got %b %b"", x, y); + pass = 1\'b0; + end + #1 a = 1\'b1; + #1 if ( x !== 1\'b1 || y !== 1\'b1) begin + $display(""Failed release value, expected 1\'b1, 1\'b1, got %b %b"", x, y); + pass = 1\'b0; + end + // Now force and release the driving signal. + #1 force a = 1\'bx; + #1 if ( x !== 1\'bx || y !== 1\'bx) begin + $display(""Failed driver value, expected 1\'bx, 1\'bx, got %b %b"", x, y); + pass = 1\'b0; + end + #1 release a; + a = 1\'b0; + #1 if ( x !== 1\'b0 || y !== 1\'b0) begin + $display(""Failed driver value, expected 1\'b0, 1\'b0, got %b %b"", x, y); + pass = 1\'b0; + end + // Check that the other driver works. + #1 a = 1\'bz; + #1 if ( x !== 1\'b1 || y !== 1\'b1) begin + $display(""Failed alt. value, expected 1\'b1, 1\'b1, got %b %b"", x, y); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"`define TESTFILE ""ivltests/pr3012758.inc"" +module top; +`include `TESTFILE +endmodule +" +"// pr1913918c + +module test ( output reg a); + + parameter [9:1] b = 9\'b0_0000_0010; + + initial begin + a = b[1] ^ b[9]; + if (a !== 1\'b0) begin +\t $display(""FAILED -- b=%b, a=%b"", b, a); +\t $finish; + end + $display(""PASSED""); + end + +endmodule +" +"module test; + parameter foo = 5; + initial $display(""%m foo = %d"", foo); +endmodule + +module test_defparam; + test U_test(); + defparam U_test.foo = 2; +endmodule + +module test_inline; + test #(.foo(2)) U_test(); +endmodule + +module testcase_defparam; + test_defparam test_defparam_a(); + test_defparam test_defparam_b(); + test_defparam test_defparam_c(); +endmodule + +module testcase_inline; + test_inline test_inline_a(); + test_inline test_inline_b(); + test_inline test_inline_c(); +endmodule +" +"module check (input unsigned [22:0] a, b, c); + wire unsigned [22:0] int_AB; + + assign int_AB = a + b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB != c) begin + $display(""ERROR""); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [22:0] A, B); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; B= 0; + for (i=0; i \'0, \'z -> \'0 + begin + $display (""FAILED - incorrect assigment to byte (when \'x \'z): %b"", bu); + $finish; + end + end + // converting unsigned integers to signed bytes + // truncation expected (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ui = {$random} % 2*(MAX+1); // full range as unsigned + #1; + force bu = ui; + #1; + if (bu !== ui[LEN-1:0]) + begin + $display (""FAILED - incorrect truncation from unsigned integer to byte: %b"", bu); + $finish; + end + end + release bu; + // converting signed integers to signed bytes + // truncation expected (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + si = $random % MAX; + #1; + force bu = si; + #1; + if (bu !== si[LEN-1:0]) + begin + $display (""FAILED - incorrect truncation from signed integer to byte: %b mismatchs %b"", bu, si[LEN-1:0]); + $finish; + end + end + release bu; + // converting signed integers having \'x \'z values into type signed bytes + // \'x \'z injections (Section 4.3.2 of IEEE 1850 LRM) + // truncation and coercion to zero expected + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + si = $random; + ar_xz = xz_inject (si[LEN-1:0]); + si = {si[31:LEN], ar_xz}; + ar_expected = xz_expected (ar_xz); + #1; + force bu_xz = si; + #1; + if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0 + begin + $display (""FAILED - incorrect conversion from integer (with \'x \'z) to byte: %b mismatchs %b"", bu_xz, ar_expected); + $finish; + end + end + release bu_xz; + // trying signed sums + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = $random % MAX; + ar_xz = $random % MAX; + #1; + bresult = bu + bu_xz; + #1; + if ( bresult !== s_sum(ar, ar_xz) ) + begin + $display (""FAILED - incorrect addition of signed bytes: %0d mismatchs %0d"", bresult, s_sum(ar, ar_xz)); + $finish; + end + // invoking byte sum function + if ( fs_sum (bu, bu_xz) !== s_sum(ar, ar_xz) ) + begin + $display (""FAILED - incorrect addition of signed bytes in function""); + $finish; + end + // invoking byte sum task + ts_sum (bu, bu_xz, bresult); + if ( bresult !== s_sum(ar, ar_xz) ) + begin + $display (""FAILED - incorrect addition of signed bytes in task: %0d mismatchs %0d"", bresult, s_sum(ar, ar_xz)); + $finish; + end + // checking byte sum from module + if ( mcaresult !== s_sum(ar, ar_xz) || mabresult !== s_sum(ar, ar_xz)) + begin + $display (""FAILED - incorrect addition of signed bytes from module""); + $finish; + end + end + + // trying signed mults, forcing truncation + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = ($random % MAX) << LEN/2; + ar_xz = ($random % MAX) << (LEN/2 - 1); + #1; + bresult = bu * bu_xz; + #1; + if ( bresult !== s_mul(ar, ar_xz) ) + begin + $display (""FAILED - incorrect product of signed bytes: %0d mismatchs %0d"", bresult, s_mul(ar, ar_xz)); + $finish; + end + // invoking byte mult function + if ( fs_mul (bu, bu_xz) !== s_mul(ar, ar_xz) ) + begin + $display (""FAILED - incorrect product of signed bytes in function""); + $finish; + end + // invoking byte mult task + ts_mul (bu, bu_xz, bresult); + if ( bresult !== s_mul(ar, ar_xz) ) + begin + $display (""FAILED - incorrect product of signed bytes in task: %0d mismatchs %0d"", bresult, s_mul(ar, ar_xz)); + $finish; + end + end + // trying relational operators + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = $random % MAX; + ar_xz = $random % MAX; + #1; + if ( (bu < bu_xz ) !== (ar < ar_xz) ) + begin + $display (""FAILED - incorrect \'less than\' on signed bytes""); + $finish; + end + if ( (bu <= bu_xz ) !== (ar <= ar_xz) ) + begin + $display (""FAILED - incorrect \'less than or equal\' on signed bytes""); + $finish; + end + if ( (bu > bu_xz ) !== (ar > ar_xz) ) + begin + $display (""FAILED - incorrect \'greater than\' on signed bytes""); + $finish; + end + if ( (bu >= bu_xz ) !== (ar >= ar_xz) ) + begin + $display (""FAILED - incorrect \'greater than or equal\' than on signed bytes""); + $finish; + end + if ( (bu == bu_xz ) !== (ar == ar_xz) ) + begin + $display (""FAILED - incorrect \'equal to\' on signed bytes""); + $finish; + end + if ( (bu != bu_xz ) !== (ar != ar_xz) ) + begin + $display (""FAILED - incorrect \'not equal to\' on signed bytes""); + $finish; + end + end + // signed small number to signed byte + for (i = 0; i < (1< out) = (0.1:0.1:0.1, 0.1:0.1:0.1); + endspecify +endmodule +" +"module top; + real a, b, c, d, e, f; + initial begin + a = 0.4; + b = 0.5; + c = 0.6; + d = 2.4; + e = 2.5; + f = 2.6; + $display(""a: %.1f %0d %0x %0b"", a, a, a, a); + $display(""b: %.1f %0d %0x %0b"", b, b, b, b); + $display(""c: %.1f %0d %0x %0b"", c, c, c, c); + $display(""d: %.1f %0d %0x %0b"", d, d, d, d); + $display(""e: %.1f %0d %0x %0b"", e, e, e, e); + $display(""f: %.1f %0d %0x %0b"", f, f, f, f); + a = -0.4; + b = -0.5; + c = -0.6; + d = -2.4; + e = -2.5; + f = -2.6; + $display(""a: %.1f %0d %0x %0b"", a, a, a, a); + $display(""b: %.1f %0d %0x %0b"", b, b, b, b); + $display(""c: %.1f %0d %0x %0b"", c, c, c, c); + $display(""d: %.1f %0d %0x %0b"", d, d, d, d); + $display(""e: %.1f %0d %0x %0b"", e, e, e, e); + $display(""f: %.1f %0d %0x %0b"", f, f, f, f); + end +endmodule +" +"// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place / Suite 330, Boston, MA 02111/1307, USA + + +// Example to test prefix for VTypeArray (and using function as index). + +module test_prefix_aray(); + logic [1:0] sel_word; + logic [31:0] out_word; + + prefix_array dut(sel_word, out_word); + + initial begin + sel_word = 2; + #1; + + if(out_word !== 32\'d5) begin + $display(""FAILED out_word = %d"", out_word); + $finish(); + end + + $display(""PASSED""); + end +endmodule +" +"module stimulus (output reg A, B); + + + initial begin + {A, B} = 2\'b00; + #10 {A, B} = 2\'b01; + #10 {A, B} = 2\'b10; + #10 {A, B} = 2\'b11; + end + +endmodule + +module scoreboard (input Y, A, B); + +function truth_table (input a, b); + reg [1:0] gate_operand; + reg gate_output; + begin + gate_operand[1:0] = {a, b}; + case (gate_operand) + 2\'b00: gate_output = 0; + 2\'b01: gate_output = 0; + 2\'b10: gate_output = 0; + 2\'b11: gate_output = 1; + endcase + + truth_table = gate_output; + end +endfunction + + +reg Y_t; + +always @(A or B) begin + Y_t = truth_table (A, B); + #1; + //$display (""a = %b, b = %b, Y_s = %b, Y = %b"", A, B, Y_s, Y); + if (Y_t !== Y) begin + $display(""FAILED! - mismatch found for inputs %b and %b in AND operation"", A, B); + $finish; + end +end + +endmodule + +module test; + stimulus stim (A, B); + and_gate duv (.a_i(A), .b_i(B), .c_o(Y) ); + scoreboard mon (Y, A, B); + + initial begin + #100; + $display(""PASSED""); + $finish; + end + +endmodule +" +"module main; + + reg [1:-10] foo; + + initial begin + foo = 12\'b0000_0000_0100; + + if (foo[-7-1] !== 1\'b1) begin +\t $display(""FAILED""); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"`begin_keywords ""1364-2005"" +module main; + + reg [3:0] foo, bar; + reg [1:0] adr; + + reg\t bit, rst, clk; + reg\t load_enable, write_enable; + + (* ivl_synthesis_on *) + always @(posedge clk or posedge rst) + if (rst) begin +\tfoo <= 0; + + end else if (load_enable) begin +\tfoo <= bar; + + end else if (write_enable) begin +\tfoo[adr] <= bit; + + end + + (* ivl_synthesis_off *) + initial begin + rst = 1; + clk = 0; + bar = 4\'bzzzz; + load_enable = 0; + write_enable = 0; + + #1 clk = 1; + #1 clk = 0; + + if (foo !== 4\'b0000) begin +\t $display(""FAILED -- reset foo=%b"", foo); +\t $finish; + end + + rst = 0; + bar = 4\'b1001; + load_enable = 1; + write_enable = 0; + + #1 clk = 1; + #1 clk = 0; + + if (foo !== bar) begin +\t $display(""FAILED -- load foo=%b, bar=%b"", foo, bar); +\t $finish; + end + + load_enable = 0; + write_enable = 0; + + #1 clk = 1; + #1 clk = 0; + if (foo !== 4\'b1001) begin +\t $display(""FAILED -- foo=%b after clk"", foo); +\t $finish; + end + + adr = 1; + bit = 1; + load_enable = 0; + write_enable = 1; + + #1 clk = 1; + #1 clk = 0; + + if (foo !== 4\'b1011) begin +\t $display(""FAILED -- foo=%b, adr=%b, bit=%b"", foo, adr, bit); +\t $finish; + end + + $display(""PASSED""); + $finish; + end + +endmodule // main +`end_keywords +" +"/* + * Verilog-A math library test code for Icarus Verilog. + * http://www.icarus.com/eda/verilog/ + * + * Copyright (C) 2007-2009 Cary R. (cygcary@yahoo.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * As of Dec. 2009 some systems have started returning the sign of + * a NaN, because of this we can for some conditions get -nan. This + * will cause mismatches with the gold file. Alan M. Feldstein + * suggested on the iverilog-devel mailing list that we use fabs + * (abs()) since C99 speifies that it will remove the sign of the + * NaN. This appears to work, so I wrapped all functions that we + * expect to return NaN with a call to abs(). + */ + +// Get the Verilog-A constants. +`include ""constants.vams"" + +module top; + real zero, mzero, pinf, minf, nan; + + initial begin + // Define a few constants. + zero = 0.0; + mzero = -1.0 * zero; + pinf = 1/0.0; + minf = ln(0); + nan = abs(sqrt(-1.0)); + + $display(""Using +0 = %f, -0 = %f, nan = %f, inf = %f and -inf = %f.\ +"", + zero, mzero, nan, pinf, minf); + + // Check that the comparisons used to detection a NaN work correctly. + if (nan != nan) $display(""NaN != comparison works correctly.""); + else $display(""NaN != comparison failed.""); + if (nan == nan) $display(""NaN == comparison failed.\ +""); + else $display(""NaN == comparison works correctly.\ +""); + + check_sqrt; + $display(""""); + check_ln; + $display(""""); + check_log; + $display(""""); + check_exp; + $display(""""); + check_abs; + $display(""""); + check_ceil; + $display(""""); + check_floor; + $display(""""); + check_sin; + $display(""""); + check_cos; + $display(""""); + check_tan; + $display(""""); + check_asin; + $display(""""); + check_acos; + $display(""""); + check_atan; + $display(""""); + check_sinh; + $display(""""); + check_cosh; + $display(""""); + check_tanh; + $display(""""); + check_asinh; + $display(""""); + check_acosh; + $display(""""); + check_atanh; + $display(""""); + check_min; + $display(""""); + check_max; + $display(""""); + check_pow; + $display(""""); + check_atan2; + $display(""""); + check_hypot; + $display(""""); + check_constants; + end + + // Task to check the square root function. + task check_sqrt; + begin + $display(""--- Checking the sqrt function ---""); + $display(""The square root of 2.0 is %f."", sqrt(2.0)); + $display(""The square root of 1.0 is %f."", sqrt(1.0)); + $display(""The square root of 0.0 is %f."", sqrt(zero)); + $display(""The square root of -0.0 is %f."", sqrt(mzero)); + $display(""The square root of -1.0 is %f."", abs(sqrt(-1.0))); + $display(""The square root of inf is %f."", sqrt(pinf)); + $display(""The square root of -inf is %f."", abs(sqrt(minf))); + $display(""The square root of nan is %f."", abs(sqrt(nan))); + end + endtask + + // Task to check the natural log function. + task check_ln; + begin + $display(""--- Checking the ln function ---""); + $display(""The natural log of 10.0 is %f."", ln(10.0)); + $display(""The natural log of 1.0 is %f."", ln(1.0)); + $display(""The natural log of 0.5 is %f."", ln(0.5)); + $display(""The natural log of 0.0 is %f."", ln(zero)); + $display(""The natural log of -0.0 is %f."", ln(mzero)); + $display(""The natural log of -1.0 is %f."", abs(ln(-1.0))); + $display(""The natural log of inf is %f."", ln(pinf)); + $display(""The natural log of -inf is %f."", abs(ln(minf))); + $display(""The natural log of nan is %f."", abs(ln(nan))); + end + endtask + + // Task to check the log base 10 function. + task check_log; + begin + $display(""--- Checking the log function ---""); + $display(""The log base 10 of 10.0 is %f."", log(10.0)); + $display(""The log base 10 of 1.0 is %f."", log(1.0)); + $display(""The log base 10 of 0.5 is %f."", log(0.5)); + $display(""The log base 10 of 0.0 is %f."", log(zero)); + $display(""The log base 10 of -0.0 is %f."", log(mzero)); + $display(""The log base 10 of -1.0 is %f."", abs(log(-1.0))); + $display(""The log base 10 of inf is %f."", log(pinf)); + $display(""The log base 10 of -inf is %f."", abs(log(minf))); + $display(""The log base 10 of nan is %f."", abs(log(nan))); + end + endtask + + // Task to check the exponential function. + task check_exp; + begin + $display(""--- Checking the exp function ---""); + $display(""The exponential of 1.0 is %f."", exp(1.0)); + $display(""The exponential of 0.0 is %f."", exp(zero)); + $display(""The exponential of -0.0 is %f."", exp(mzero)); + $display(""The exponential of -1.0 is %f."", exp(-1.0)); + $display(""The exponential of inf is %f."", exp(pinf)); + $display(""The exponential of -inf is %f."", exp(minf)); + $display(""The exponential of nan is %f."", abs(exp(nan))); + end + endtask + + // Task to check the absolute value function. + task check_abs; + begin + $display(""--- Checking the abs function ---""); + $display(""The absolute value of 1.0 is %f."", abs(1.0)); + $display(""The absolute value of 0.0 is %f."", abs(zero)); + $display(""The absolute value of -0.0 is %f."", abs(mzero)); + $display(""The absolute value of -1.0 is %f."", abs(-1.0)); + $display(""The absolute value of inf is %f."", abs(pinf)); + $display(""The absolute value of -inf is %f."", abs(minf)); + $display(""The absolute value of nan is %f."", abs(nan)); + end + endtask + + // Task to check the ceiling function. + task check_ceil; + begin + $display(""--- Checking the ceil function ---""); + $display(""The ceiling of 2.1 is %f."", ceil(2.1)); + $display(""The ceiling of 0.5 is %f."", ceil(0.5)); + $display(""The ceiling of -0.5 is %f."", ceil(-0.5) + 0.0); + $display(""The ceiling of -1.1 is %f."", ceil(-1.1)); + $display(""The ceiling of inf is %f."", ceil(pinf)); + $display(""The ceiling of -inf is %f."", ceil(minf)); + $display(""The ceiling of nan is %f."", abs(ceil(nan))); + end + endtask + + // Task to check the floor function. + task check_floor; + begin + $display(""--- Checking the floor function ---""); + $display(""The floor of 2.1 is %f."", floor(2.1)); + $display(""The floor of 0.5 is %f."", floor(0.5)); + $display(""The floor of -0.5 is %f."", floor(-0.5)); + $display(""The floor of -1.1 is %f."", floor(-1.1)); + $display(""The floor of inf is %f."", floor(pinf)); + $display(""The floor of -inf is %f."", floor(minf)); + $display(""The floor of nan is %f."", abs(floor(nan))); + end + endtask + + // Task to check the sin function. + task check_sin; + begin + $display(""--- Checking the sin function ---""); + $display(""The sin of 4.0 is %f."", sin(4.0)); + $display(""The sin of 1.0 is %f."", sin(1.0)); + $display(""The sin of 0.0 is %f."", sin(zero)); + $display(""The sin of -0.0 is %f."", sin(mzero)); + $display(""The sin of -1.0 is %f."", sin(-1.0)); + $display(""The sin of -4.0 is %f."", sin(-4.0)); + $display(""The sin of inf is %f."", abs(sin(pinf))); + $display(""The sin of -inf is %f."", abs(sin(minf))); + $display(""The sin of nan is %f."", abs(sin(nan))); + end + endtask + + // Task to check the cos function. + task check_cos; + begin + $display(""--- Checking the cos function ---""); + $display(""The cos of 4.0 is %f."", cos(4.0)); + $display(""The cos of 1.0 is %f."", cos(1.0)); + $display(""The cos of 0.0 is %f."", cos(zero)); + $display(""The cos of -0.0 is %f."", cos(mzero)); + $display(""The cos of -1.0 is %f."", cos(-1.0)); + $display(""The cos of -4.0 is %f."", cos(-4.0)); + $display(""The cos of inf is %f."", abs(cos(pinf))); + $display(""The cos of -inf is %f."", abs(cos(minf))); + $display(""The cos of nan is %f."", abs(cos(nan))); + end + endtask + + // Task to check the tan function. + task check_tan; + begin + $display(""--- Checking the tan function ---""); + $display(""The tan of 4.0 is %f."", tan(4.0)); + $display(""The tan of 1.0 is %f."", tan(1.0)); + $display(""The tan of 0.0 is %f."", tan(zero)); + $display(""The tan of -0.0 is %f."", tan(mzero)); + $display(""The tan of -1.0 is %f."", tan(-1.0)); + $display(""The tan of -4.0 is %f."", tan(-4.0)); + // The underlying math libraries can give different results for + // this corner case, so we can only use four significant digits + // for these two tests. + $display(""The tan of pi/2 is %.4g."", tan(asin(1.0))); + $display(""The tan of -pi/2 is %.4g."", tan(asin(-1.0))); + $display(""The tan of inf is %f."", abs(tan(pinf))); + $display(""The tan of -inf is %f."", abs(tan(minf))); + $display(""The tan of nan is %f."", abs(tan(nan))); + end + endtask + + // Task to check the asin function. + task check_asin; + begin + $display(""--- Checking the asin function ---""); + $display(""The asin of 1.1 is %f."", abs(asin(1.1))); + $display(""The asin of 1.0 is %f."", asin(1.0)); + $display(""The asin of 0.5 is %f."", asin(0.5)); + $display(""The asin of 0.0 is %f."", asin(zero)); + $display(""The asin of -0.0 is %f."", asin(mzero)); + $display(""The asin of -0.5 is %f."", asin(-0.5)); + $display(""The asin of -1.0 is %f."", asin(-1.0)); + $display(""The asin of -1.1 is %f."", abs(asin(-1.1))); + $display(""The asin of inf is %f."", abs(asin(pinf))); + $display(""The asin of -inf is %f."", abs(asin(minf))); + $display(""The asin of nan is %f."", abs(asin(nan))); + end + endtask + + // Task to check the acos function. + task check_acos; + begin + $display(""--- Checking the acos function ---""); + $display(""The acos of 1.1 is %f."", abs(acos(1.1))); + $display(""The acos of 1.0 is %f."", acos(1.0)); + $display(""The acos of 0.5 is %f."", acos(0.5)); + $display(""The acos of 0.0 is %f."", acos(zero)); + $display(""The acos of -0.0 is %f."", acos(mzero)); + $display(""The acos of -0.5 is %f."", acos(-0.5)); + $display(""The acos of -1.0 is %f."", acos(-1.0)); + $display(""The acos of -1.1 is %f."", abs(acos(-1.1))); + $display(""The acos of inf is %f."", abs(acos(pinf))); + $display(""The acos of -inf is %f."", abs(acos(minf))); + $display(""The acos of nan is %f."", abs(acos(nan))); + end + endtask + + // Task to check the atan function. + task check_atan; + begin + $display(""--- Checking the atan function ---""); + $display(""The atan of 2.0 is %f."", atan(2.0)); + $display(""The atan of 0.5 is %f."", atan(0.5)); + $display(""The atan of 0.0 is %f."", atan(zero)); + $display(""The atan of -0.0 is %f."", atan(mzero)); + $display(""The atan of -0.5 is %f."", atan(-0.5)); + $display(""The atan of -2.0 is %f."", atan(-2.0)); + $display(""The atan of inf is %f."", atan(pinf)); + $display(""The atan of -inf is %f."", atan(minf)); + $display(""The atan of nan is %f."", abs(atan(nan))); + end + endtask + + // Task to check the sinh function. + task check_sinh; + begin + $display(""--- Checking the sinh function ---""); + $display(""The sinh of 2.0 is %f."", sinh(2.0)); + $display(""The sinh of 1.0 is %f."", sinh(1.0)); + $display(""The sinh of 0.5 is %f."", sinh(0.5)); + $display(""The sinh of 0.0 is %f."", sinh(zero)); + $display(""The sinh of -0.0 is %f."", sinh(mzero)); + $display(""The sinh of -0.5 is %f."", sinh(-0.5)); + $display(""The sinh of -1.0 is %f."", sinh(-1.0)); + $display(""The sinh of -2.0 is %f."", sinh(-2.0)); + $display(""The sinh of inf is %f."", sinh(pinf)); + $display(""The sinh of -inf is %f."", sinh(minf)); + $display(""The sinh of nan is %f."", abs(sinh(nan))); + end + endtask + + // Task to check the cosh function. + task check_cosh; + begin + $display(""--- Checking the cosh function ---""); + $display(""The cosh of 2.0 is %f."", cosh(2.0)); + $display(""The cosh of 1.0 is %f."", cosh(1.0)); + $display(""The cosh of 0.5 is %f."", cosh(0.5)); + $display(""The cosh of 0.0 is %f."", cosh(zero)); + $display(""The cosh of -0.0 is %f."", cosh(mzero)); + $display(""The cosh of -0.5 is %f."", cosh(-0.5)); + $display(""The cosh of -1.0 is %f."", cosh(-1.0)); + $display(""The cosh of -2.0 is %f."", cosh(-2.0)); + $display(""The cosh of inf is %f."", cosh(pinf)); + $display(""The cosh of -inf is %f."", cosh(minf)); + $display(""The cosh of nan is %f."", abs(cosh(nan))); + end + endtask + + // Task to check the tanh function. + task check_tanh; + begin + $display(""--- Checking the tanh function ---""); + $display(""The tanh of 2.0 is %f."", tanh(2.0)); + $display(""The tanh of 1.0 is %f."", tanh(1.0)); + $display(""The tanh of 0.5 is %f."", tanh(0.5)); + $display(""The tanh of 0.0 is %f."", tanh(zero)); + $display(""The tanh of -0.0 is %f."", tanh(mzero)); + $display(""The tanh of -0.5 is %f."", tanh(-0.5)); + $display(""The tanh of -1.0 is %f."", tanh(-1.0)); + $display(""The tanh of -2.0 is %f."", tanh(-2.0)); + $display(""The tanh of inf is %f."", tanh(pinf)); + $display(""The tanh of -inf is %f."", tanh(minf)); + $display(""The tanh of nan is %f."", abs(tanh(nan))); + end + endtask + + // Task to check the asinh function. + task check_asinh; + begin + $display(""--- Checking the asinh function ---""); + $display(""The asinh of 2.0 is %f."", asinh(2.0)); + $display(""The asinh of 1.0 is %f."", asinh(1.0)); + $display(""The asinh of 0.5 is %f."", asinh(0.5)); + $display(""The asinh of 0.0 is %f."", asinh(zero)); + $display(""The asinh of -0.0 is %f."", asinh(mzero)); + $display(""The asinh of -0.5 is %f."", asinh(-0.5)); + $display(""The asinh of -1.0 is %f."", asinh(-1.0)); + $display(""The asinh of -2.0 is %f."", asinh(-2.0)); + $display(""The asinh of inf is %f."", asinh(pinf)); + $display(""The asinh of -inf is %f."", asinh(minf)); + $display(""The asinh of nan is %f."", abs(asinh(nan))); + end + endtask + + // Task to check the acosh function. + task check_acosh; + begin + $display(""--- Checking the acosh function ---""); + $display(""The acosh of 2.0 is %f."", acosh(2.0)); + $display(""The acosh of 1.0 is %f."", acosh(1.0)); + $display(""The acosh of 0.5 is %f."", abs(acosh(0.5))); + $display(""The acosh of 0 is %f."", abs(acosh(zero))); + $display(""The acosh of -0 is %f."", abs(acosh(mzero))); + $display(""The acosh of -0.5 is %f."", abs(acosh(-0.5))); + $display(""The acosh of -1.0 is %f."", abs(acosh(-1.0))); + $display(""The acosh of -2.0 is %f."", abs(acosh(-2.0))); + $display(""The acosh of inf is %f."", acosh(pinf)); + $display(""The acosh of -inf is %f."", abs(acosh(minf))); + $display(""The acosh of nan is %f."", abs(acosh(nan))); + end + endtask + + // Task to check the atanh function. + task check_atanh; + begin + $display(""--- Checking the atanh function ---""); + $display(""The atanh of 2.0 is %f."", abs(atanh(2.0))); + $display(""The atanh of 1.0 is %f."", atanh(1.0)); + $display(""The atanh of 0.5 is %f."", atanh(0.5)); + $display(""The atanh of 0.0 is %f."", atanh(zero)); + $display(""The atanh of -0.0 is %f."", atanh(mzero)); + $display(""The atanh of -0.5 is %f."", atanh(-0.5)); + $display(""The atanh of -1.0 is %f."", atanh(-1.0)); + $display(""The atanh of -2.0 is %f."", abs(atanh(-2.0))); + $display(""The atanh of inf is %f."", abs(atanh(pinf))); + $display(""The atanh of -inf is %f."", abs(atanh(minf))); + $display(""The atanh of nan is %f."", abs(atanh(nan))); + end + endtask + + // Task to check the min function. + task check_min; + begin + $display(""--- Checking the min function ---""); + $display(""The minimum of 1.0 and 2.0 is %f."", min(1.0, 2.0)); + $display(""The minimum of 2.0 and 1.0 is %f."", min(2.0, 1.0)); + $display(""The minimum of 1.0 and -1.0 is %f."", min(1.0, -1.0)); + $display(""The minimum of -1.0 and -2.0 is %f."", min(-1.0, -2.0)); + $display(""The minimum of 2.0 and inf is %f."", min(2.0, pinf)); + $display(""The minimum of inf and 2.0 is %f."", min(pinf, 2.0)); + $display(""The minimum of 2.0 and -inf is %f."", min(2.0, minf)); + $display(""The minimum of -inf and 2.0 is %f."", min(minf, 2.0)); + $display(""The minimum of 2.0 and nan is %f."", min(2.0, nan)); + $display(""The minimum of nan and 2.0 is %f."", min(nan, 2.0)); + end + endtask + + // Task to check the max function. + task check_max; + begin + $display(""--- Checking the max function ---""); + $display(""The maximum of 1.0 and 2.0 is %f."", max(1.0, 2.0)); + $display(""The maximum of 2.0 and 1.0 is %f."", max(2.0, 1.0)); + $display(""The maximum of 1.0 and -1.0 is %f."", max(1.0, -1.0)); + $display(""The maximum of -1.0 and -2.0 is %f."", max(-1.0, -2.0)); + $display(""The maximum of 2.0 and inf is %f."", max(2.0, pinf)); + $display(""The maximum of inf and 2.0 is %f."", max(pinf, 2.0)); + $display(""The maximum of 2.0 and -inf is %f."", max(2.0, minf)); + $display(""The maximum of -inf and 2.0 is %f."", max(minf, 2.0)); + $display(""The maximum of 2.0 and nan is %f."", max(2.0, nan)); + $display(""The maximum of nan and 2.0 is %f."", max(nan, 2.0)); + end + endtask + + // Task to check the power function. + task check_pow; + begin + $display(""--- Checking the pow function ---""); + $display("" 0.0 to the power of 0.0 is %f."", pow(zero, zero)); + $display("" 1.0 to the power of 0.0 is %f."", pow(1.0, zero)); + $display(""-1.0 to the power of 0.0 is %f."", pow(-1.0, zero)); + $display("" 0.0 to the power of 1.0 is %f."", pow(zero, 1.0)); + $display("" 1.0 to the power of 1.0 is %f."", pow(1.0, 1.0)); + $display(""-1.0 to the power of 1.0 is %f."", pow(-1.0, 1.0)); + $display("" 8.0 to the power of 1/3 is %f."", pow(8.0, 1.0/3.0)); + $display("" 8.0 to the power of -1/3 is %f."", pow(8.0, -1.0/3.0)); + $display("" 2.0 to the power of 3.0 is %f."", pow(2.0, 3.0)); + $display("" 2.0 to the power of 5000 is %f."", pow(2.0, 5000)); + $display(""-2.0 to the power of 5001 is %f."", pow(-2.0, 5001)); + $display("" 2.0 to the power of -5000 is %f."", pow(2.0, -5000)); + $display("" inf to the power of 0.0 is %f."", pow(pinf, zero)); + $display(""-inf to the power of 0.0 is %f."", pow(minf, zero)); + $display("" inf to the power of 1.0 is %f."", pow(pinf, 1.0)); + $display(""-inf to the power of 1.0 is %f."", pow(minf, 1.0)); + $display("" inf to the power of 2.0 is %f."", pow(pinf, 2.0)); + $display(""-inf to the power of 2.0 is %f."", pow(minf, 2.0)); + $display("" 1.0 to the power of inf is %f."", pow(1.0, pinf)); + $display(""-1.0 to the power of inf is %f."", pow(-1.0, pinf)); + $display("" 0.5 to the power of inf is %f."", pow(0.5, pinf)); + $display("" 2.0 to the power of inf is %f."", pow(2.0, pinf)); + $display("" 1.0 to the power of -inf is %f."", pow(1.0, minf)); + $display(""-1.0 to the power of -inf is %f."", pow(-1.0, minf)); + $display("" 0.5 to the power of -inf is %f."", pow(0.5, minf)); + $display("" 2.0 to the power of -inf is %f."", pow(2.0, minf)); + $display(""-1.0 to the power of -1/3 is %f."", abs(pow(-1.0, -1.0/3.0))); + $display("" 1.0 to the power of nan is %f."", pow(1.0, nan)); + $display("" nan to the power of 1.0 is %f."", abs(pow(nan, 1.0))); + $display("" nan to the power of 0.0 is %f."", pow(nan, zero)); + $display("" nan to the power of nan is %f."", abs(pow(nan, nan))); + end + endtask + + // Task to check the atan of x/y function. + task check_atan2; + begin + $display(""--- Checking the atan2 function ---""); + $display(""The atan of 0.0/ 0.0 is %f."", atan2(zero, zero)); + $display(""The atan of -0.0/ 0.0 is %f."", atan2(mzero, zero)); + $display(""The atan of 0.0/-0.0 is %f."", atan2(zero, mzero)); + $display(""The atan of -0.0/-0.0 is %f."", atan2(mzero, mzero)); + $display(""The atan of 0.0/ 1.0 is %f."", atan2(zero, 1.0)); + $display(""The atan of 1.0/ 0.0 is %f."", atan2(1.0, zero)); + $display(""The atan of 1.0/ 1.0 is %f."", atan2(1.0, 1.0)); + $display(""The atan of 0.0/-1.0 is %f."", atan2(zero, -1.0)); + $display(""The atan of -1.0/ 0.0 is %f."", atan2(-1.0, zero)); + $display(""The atan of -1.0/-1.0 is %f."", atan2(-1.0, -1.0)); + $display(""The atan of inf/ 0.0 is %f."", atan2(pinf, zero)); + $display(""The atan of 0.0/ inf is %f."", atan2(zero, pinf)); + $display(""The atan of inf/ inf is %f."", atan2(pinf, pinf)); + $display(""The atan of -inf/ 0.0 is %f."", atan2(minf, zero)); + $display(""The atan of 0.0/-inf is %f."", atan2(zero, minf)); + $display(""The atan of -inf/-inf is %f."", atan2(minf, minf)); + $display(""The atan of nan/ 0.0 is %f."", abs(atan2(nan, zero))); + $display(""The atan of nan/ 1.0 is %f."", abs(atan2(nan, 1.0))); + $display(""The atan of 1.0/ nan is %f."", abs(atan2(1.0, nan))); + end + endtask + + // Task to check the distance from origin function. + task check_hypot; + begin + $display(""--- Checking the hypot function ---""); + $display(""The distance to ( 0.0, 0.0) is %f."", hypot(zero, zero)); + $display(""The distance to ( 2.0, 0.0) is %f."", hypot(2.0, zero)); + $display(""The distance to ( -2.0, 0.0) is %f."", hypot(-2.0, zero)); + $display(""The distance to ( 0.0, 2.0) is %f."", hypot(zero, 2.0)); + $display(""The distance to ( 0.0, -2.0) is %f."", hypot(zero, -2.0)); + $display(""The distance to ( inf, 0.0) is %f."", hypot(pinf, zero)); + $display(""The distance to ( 0.0, inf) is %f."", hypot(zero, pinf)); + $display(""The distance to ( -inf, 0.0) is %f."", hypot(minf, zero)); + $display(""The distance to ( nan, 0.0) is %f."", abs(hypot(nan, zero))); + $display(""The distance to ( 0.0, nan) is %f."", abs(hypot(zero, nan))); + end + endtask + + // Task to check the mathematical constants. + task check_constants; + begin + $display(""--- Checking the mathematical constants ---""); + $display("" Pi is %.16f."", `M_PI); + $display("" 2*Pi is %.16f."", `M_TWO_PI); + $display("" Pi/2 is %.16f."", `M_PI_2); + $display("" Pi/4 is %.16f."", `M_PI_4); + $display("" 1/Pi is %.16f."", `M_1_PI); + $display("" 2/Pi is %.16f."", `M_2_PI); + $display(""2/sqrt(Pi) is %.16f."", `M_2_SQRTPI); + $display("" e is %.16f."", `M_E); + $display("" log2(e) is %.16f."", `M_LOG2E); + $display("" log10(e) is %.16f."", `M_LOG10E); + $display("" loge(2) is %.16f."", `M_LN2); + $display("" loge(10) is %.16f."", `M_LN10); + $display("" sqrt(2) is %.16f."", `M_SQRT2); + $display("" 1/sqrt(2) is %.16f."", `M_SQRT1_2); + end + endtask +endmodule +" +"// Regression test for GitHub issue 25 +// This should result in a compile-time error when the language generation +// is 1364-2005 or earlier. + +task test(input i, output o); + +begin + o = i; +end + +endtask + +module tb; + +reg passed = 0; + +initial begin + test(1, passed); + if (passed) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module top; + parameter irparam = -1.0; + parameter iiparam = -1; + parameter [7:0] uparam = -1.0; + parameter signed [7:0] sparam = -1.0; + parameter real rparam = -1; + parameter realtime rtparam = -1; + parameter integer iparam = -1.0; + parameter time tparam = -1.0; + + initial begin + $display(""Implicit real: "", irparam); + $display(""Implicit integer: "", iiparam); + $display(""Unsigned: "", uparam); + $display(""Signed: "", sparam); + $display(""Real: "", rparam); + $display(""Real time: "", rtparam); + $display(""Integer: "", iparam); + $display(""Time: "", tparam); + end +endmodule +" +"// A few simple tests of translating parameters to generics +module top(); + wire [7:0] v1, v2, v3; + wire [7:0] w1, w2, w3; + + child c1(v1, w1); + child c2(v2, w2); + child c3(v3, w3); + + defparam c1.MY_VALUE = 6; + defparam c2.MY_VALUE = 44; + + initial begin + #2; + $display(""c1 reg value: %d"", v1); + $display(""c2 reg value: %d"", v2); + $display(""c3 reg value: %d"", v3); + $display(""c1 wire value: %d"", w1); + $display(""c2 wire value: %d"", w2); + $display(""c3 wire value: %d"", w3); + if (v1 !== 6) + $display(""FAILED - v1 !== 6""); + else if (v2 !== 44) + $display(""FAILED - v2 !== 44""); + else if (v3 !== 12) + $display(""FAILED - v3 !== 12""); + else if (w1 !== 7) + $display(""FAILED - v1 !== 7""); + else if (w2 !== 45) + $display(""FAILED - v2 !== 45""); + else if (w3 !== 13) + $display(""FAILED - v3 !== 13""); + else + $display(""PASSED""); + end + +endmodule // top + +module child(value, value_w); + output [7:0] value, value_w; + reg [7:0] value; + + parameter MY_VALUE = 12; + + assign value_w = MY_VALUE + 1; + + // Make a non-trivial process + initial begin + #1; + value <= MY_VALUE; + end +endmodule // child +" +"module top; + reg pass = 1\'b1; + reg [14:-1] big = 16\'h0123; + + reg signed [15:0] a; + + wire [3:0] w_big = big[a+:4]; + + initial begin + #1; // Wait for the assigns above to happen. + + /* If this fails it is likely because the index width is less + * than an int width. */ + a = -2; + #1; + if (w_big !== 4\'b011x) begin + $display(""Failed: .part/v check, expected 4\'b011x, got %b."", w_big); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"/* + * Copyright (c) 2000 Steven Wilson (stevew@homeaddress.org) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test looks for != operation in a continuous assignment. + */ +module test; + +integer a; +integer b; +wire result; +integer error; + +assign result = (a != b); + +initial + begin + a = 0; + b = 0; + error = 0; + #5 ; + if( result === 1\'b1) + error =1; + a = 1; + #5; + if( result === 1\'b0) + error =1; + + b = 1; + #5 ; + if( result === 1\'b1) + error =1; + + a = 1002; + b = 1001; + #5 ; + if( result === 1\'b0) + error =1; + a = 1001; + #5 ; + if( result === 1\'b1) + error =1; + + if(error === 0) +\t $display(""PASSED""); + else +\t $display(""FAILED""); + end + +endmodule +" +"/* real9.v + * This tests comparison of a real variable with integer constants. + */ +module main; + + real value; + parameter param = 2; + + initial begin + value = 3.0; + + if (value < param) begin +\t $display(""FAILED -- %f < %d"", value, param); +\t $finish; + end + + if (value < 2) begin +\t $display(""FAILED -- %f < 2"", value); +\t $finish; + end + + if (value <= param) begin +\t $display(""FAILED -- %f <= %d"", value, param); +\t $finish; + end + + if (value <= 2) begin +\t $display(""FAILED -- %f <= 2"", value); +\t $finish; + end + + if (value == param) begin +\t $display(""FAILED -- %f == %d"", value, param); +\t $finish; + end + + if (value == 2) begin +\t $display(""FAILED -- %f == 2"", value); +\t $finish; + end + + if (param >= value) begin +\t $display(""FAILED -- %d >= %f"", param, value); +\t $finish; + end + + if (2 >= value) begin +\t $display(""FAILED -- 2 >= %f"", value); +\t $finish; + end + + value = 2.0; + + if (value < param) begin +\t $display(""FAILED -- %f < %d"", value, param); +\t $finish; + end + + if (value < 2) begin +\t $display(""FAILED -- %f < 2"", value); +\t $finish; + end + + if (value != param) begin +\t $display(""FAILED -- %f != %d"", value, param); +\t $finish; + end + + if (value != 2) begin +\t $display(""FAILED -- %f != 2"", value); +\t $finish; + end + + if (value > param) begin +\t $display(""FAILED -- %f > %d"", value, param); +\t $finish; + end + + if (value > 2) begin +\t $display(""FAILED -- %f > 2"", value); +\t $finish; + end + + value = 1.6; + + if (value == param) begin +\t $display(""FAILED -- %f == %d"", value, param); +\t $finish; + end + + if (value == 2) begin +\t $display(""FAILED -- %f == 2"", value); +\t $finish; + end + + if (value >= param) begin +\t $display(""FAILED -- %f >= %d"", value, param); +\t $finish; + end + + if (value >= 2) begin +\t $display(""FAILED -- %f >= 2"", value); +\t $finish; + end + + if (value > param) begin +\t $display(""FAILED -- %f > %d"", value, param); +\t $finish; + end + + if (value > 2) begin +\t $display(""FAILED -- %f > 2"", value); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + + +endmodule +" +"`timescale 1ns/1ps +module test; + reg in, pass; + wire out; + + assign #(1?2:1) out = in; +// assign #(1+1) out = in; + + initial begin + pass = 1\'b1; + in = 1\'b0; + #1.999; + if (out !== 1\'bx) begin + $display(""Failed signal at begining, expected 1\'bx, got %b"", out); + pass = 1\'b0; + end + #0.002; + if (out !== in) begin + $display(""Failed signal at end, expected %b, got %b"", in, out); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Rewrite of stmt002_bassign.v from vbs test suite. +// +module main; + +reg [0:7] var1, var2;\t// Note the obtuse bit ordering. +reg [3:0] var3;\t\t// A more sane ordering on a nibble boundary... +reg var4;\t\t// Single bit. +reg [2:9] var5;\t\t// Use a non-alligned, reversed bit - still 8 bits +reg error; + +initial + begin + // First verify that all the defined variables are x\'s. + error = 0; + if(var1 !== 8\'hxx) + begin + $display(""FAILED - sdw_stmt002 - var1 not 8\'hxx""); + error = 1; + end + if(var2 !== 8\'hxx) + begin + $display(""FAILED - sdw_stmt002 -var2 not 8\'hxx""); + error = 1; + end + if(var3 !== 4\'bx_xxx) + begin + $display(""FAILED - sdw_stmt002 -var3 not 4\'hx""); + error = 1; + end + if(var4 !== 1\'bx) + begin + $display(""FAILED - sdw_stmt002 -var4 not 1\'bx""); + error = 1; + end + if(var5 !== 8\'hxx) + begin + $display(""FAILED - sdw_stmt002 -var5 not 8\'hxx""); + error = 1; + end + + var1 = 8\'b1001_0010;\t// Do some binary bits + var2 = 255;\t\t// Fill it with decimal version of ff + var3 = 4\'hf;\t\t// hex + var4 = 0; + var5 = 8\'h99;\t\t// Still 8 bits + + if(var1 != 8\'h92) + begin + $display(""FAILED - sdw_stmt002 - var1 not 8\'h96""); + error = 1; + end + if(var2 != 8\'hff) + begin + $display(""FAILED - sdw_stmt002 -var2 not 8\'hff""); + error = 1; + end + if(var3 != 4\'b1111) + begin + $display(""FAILED - sdw_stmt002 -var3 not 4\'hf""); + error = 1; + end + if(var4 != 1\'b0) + begin + $display(""FAILED - sdw_stmt002 -var4 not 1\'b0""); + error = 1; + end + if(var5 != 8\'h99) + begin + $display(""FAILED - sdw_stmt002 -var5 not 8\'h99""); + error = 1; + end + + // Next - assign sub-portion of vector + var1 [3:6] = var3; + + if(var1 != 8\'h9e) + begin + $display(""FAILED - sdw_stmt002 - subfield assign failed""); + error = 1; + end + + var3 = 4\'o11;\t// Lets try octal now + var4 = 1\'b1;\t// And set that bit to 1, it WAS 0 + var5 = 8\'h66;\t// Invert it + + if(var3 != 4\'b1001) + begin + $display(""FAILED - sdw_stmt002 -var3 octal assign""); + error = 1; + end + if(var4 != 1\'b1) + begin + $display(""FAILED - sdw_stmt002 -var4 not 1\'b1""); + error = 1; + end + if(var5 != 8\'h66) + begin + $display(""FAILED - sdw_stmt002 -var5 not 8\'h66""); + error = 1; + end + + // 9e, 9 + + var3 = var1[4:7];\t\t// Should be an 4\'he + var1[0:3] = var3[3:2];\t// Now should give 8\'hce + + if(var1 != 8\'h3e) + begin + $display(""FAILED - sdw_stmt002 - subfield assign(1) w/ 0 extension""); + error = 1; + end + if(var3 != 4\'b1110) + begin + $display(""FAILED - sdw_stmt002 -subfield assign(2)""); + error = 1; + end + + var3 = var5;\t\t// 4 bit from 8 bit(4\'h6) + var5[5] = var4;\t\t// Set var5 to 8\'h76 + + if(var3 != 4\'h6) + begin + $display(""FAILED - sdw_stmt002 - 4bit from 8 bit assign""); + error = 1; + end + if(var5 != 8\'h76) + begin + $display(""FAILED - sdw_stmt002 - single sub-bit assign ""); + error = 1; + end + + if(error == 0) + $display(""PASSED""); + end + +endmodule +" +"/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + */ +`timescale 1ns / 1ns + +module main; + + initial begin + #3 $display(""$time = %t (unformatted)"", $time); + $timeformat(-6, 6, ""ns"", 12); + $display(""$time = %t (-6,6)"", $time); + $timeformat(-6, 1, ""ns"", 12); + $display(""$time = %t (-6,1)"", $time); + end + + +endmodule // main +" +"module top; + wire [2:-1] vec; + integer idx; + + initial begin + idx = 'bx; + force vec[idx] = 1'b1; + release vec[idx]; + end +endmodule +" +"// Memory test for index bug +module main (); +reg [7:0] mem [0:64]; +reg [7:0] val_reg; +wire [7:0] val_wire; + +// Works ok +assign val_wire = mem[67]; + +initial + begin + + // This should generate an error. + val_reg = mem; + + end + + +endmodule +" +"module top; + reg pass; + reg [31:0] in2; + integer in1; + reg signed [128:0] res; + + initial begin + pass = 1\'b1; + + in1 = -2; in2 = 63; + res = in1 ** in2; + if (res !== -128\'sd9223372036854775808) begin + $display(""Failed: -2 ** 65, expected -9223372036854775808, got %0d"", res); + pass = 1\'b0; + end + + in1 = -2; in2 = 65; + res = in1 ** in2; + if (res !== -128\'sd36893488147419103232) begin + $display(""Failed: -2 ** 65, expected -36893488147419103232, got %0d"", res); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module test(); + +reg\t clk; +reg [1:0] state; + +always begin + case (state) + 0 : state = 1; + 1 : state = 2; + default : /* do nothing */ ; + endcase + @(posedge clk); +end + +reg failed = 0; + +initial begin + clk = 0; + state = 0; + #1 clk = 1; + #1 clk = 0; + if (state !== 1) failed = 1; + #1 clk = 1; + #1 clk = 0; + if (state !== 2) failed = 1; + #1 clk = 1; + #1 clk = 0; + if (state !== 2) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"// test.v program starts here +// This program is based on iverilog report [ 1367855 ] vvp simulation error +module test(); + reg [3:0] S; + + mux m( .SEL(S) ); + + initial begin + S=3; #100; + S=2; #100; + $display(""PASSED""); + $finish; + end +endmodule + +module mux(SEL); +input [3:0] SEL; +wire [3:0] SEL; +integer offset; + +always @(SEL) begin + offset = SEL[3] + SEL[0]*128 + SEL[2:1]*2; + $display(""MUX: SEL=%d offset=%b"", SEL, offset); + + case (SEL) + + \'bxxxx: begin + end + + 2: if (offset !== \'b00000000000000000000000000000010) begin +\t$display(""FAILED""); +\t$finish; + end + + 3: if (offset !== \'b00000000000000000000000010000010) begin +\t$display(""FAILED""); +\t$finish; + end + + default: begin +\t$display(""FAILED -- SEL=%b"", SEL); +\t$finish; + end + + endcase +end +endmodule +" +"/* + * Copyright (c) 2000 Chris Lattner + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test catches the definition of a null task. The statement is + * empty, so the compiler can do some optimizations. + */ +module test; + task mod; + input [31:0] a; + begin + end + endtask + + initial begin + mod(5\'d0); + $display(""PASSED""); + end +endmodule +" +"module tb; +initial $finish(0); +final $display(""In final statement.""); +endmodule +" +"// Copyright (c) 2000 Steve Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +// SDW: Try the always @ * construct from Verilog 2000 LRM spec + +module test; + + +// +// Define a procedural assignment based mux. +// +reg [1:0] sel; +reg [1:0] out, a,b,c,d; +reg error; + +always @ * + case (sel) + 2\'b00: out = a; + 2\'b01: out = b; + 2\'b10: out = c; + 2\'b11: out = d; + endcase + +initial + begin + error = 0; + #1 ; + sel = 0; + a = 0; + #1; + if(out !== 2\'b00) + begin + $display(""FAILED - Wildcard sensitivy list a != 0(1)""); + error =1; + end + #1; + a = 1; + #1; + if(out !== 2\'b01) + begin + $display(""FAILED - Wildcard sensitivity list a != 1 (2)""); + error =1; + end + if(error == 0) + $display(""PASSED""); + end + +endmodule +" +"module dff(); + +reg clk; +reg rst; +reg ce; +reg [3:0] d; +reg [3:0] q; + +always @(negedge clk or posedge rst) begin + if (rst) + q <= 4\'b1001; + else if (ce) + q <= d; +end + +(* ivl_synthesis_off *) +reg failed = 0; + +initial begin + $monitor(""%b %b %b %b"", rst, clk, d, q); + clk = 1\'b0; + ce = 1\'b0; + rst = 1\'b0; + d = 4\'b0110; + #1; + if (q !== 4\'bxxxx) failed = 1; + rst = 1\'b1; + #1; + if (q !== 4\'b1001) failed = 1; + clk = 1\'b1; + #1; + if (q !== 4\'b1001) failed = 1; + clk = 1\'b0; + #1; + if (q !== 4\'b1001) failed = 1; + rst = 1\'b0; + #1; + if (q !== 4\'b1001) failed = 1; + clk = 1\'b1; + #1; + if (q !== 4\'b1001) failed = 1; + clk = 1\'b0; + #1; + if (q !== 4\'b1001) failed = 1; + ce = 1\'b1; + #1; + if (q !== 4\'b1001) failed = 1; + clk = 1\'b1; + #1; + if (q !== 4\'b1001) failed = 1; + clk = 1\'b0; + #1; + if (q !== 4\'b0110) failed = 1; + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule // dff +" +" +// This tests the basic support for default arguments to task/function +// ports. The default port syntax gives SystemVerilog a limited form +// of variable argument lists. + +program main; + + class foo_t; + int int_val; + string text_val; + + function new (int int_init, string text_init = ""default text""); +\t int_val = int_init; +\t text_val = text_init; + endfunction : new + + endclass : foo_t + + + foo_t obj1; + + initial begin + obj1 = new (5, ""new text""); + if (obj1.int_val != 5 || obj1.text_val != ""new text"") begin +\t $display(""FAILED -- obj1.int_val=%0d, obj1.text_val=%0s"", obj1.int_val, obj1.text_val); +\t $finish; + end + + obj1 = new (7); + if (obj1.int_val != 7 || obj1.text_val != ""default text"") begin +\t $display(""FAILED -- obj1.int_val=%0d, obj1.text_val=%0s"", obj1.int_val, obj1.text_val); +\t $finish; + end + + $display(""PASSED""); + end + +endprogram // main +" +"// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +module br985_test; +logic [3:0] sel; +logic value, spi_sdo; +bug3 dut(sel, value, spi_sdo); + +initial begin + int i; + sel = 4\'b0000; + + #1 if(spi_sdo !== 1\'b1) + begin + $display(""FAILED""); + $finish(); + end + + for(i = 1; i < 16; i = i + 1) + begin + sel = i; + #1 if(spi_sdo !== 1\'b0) + begin + $display(""FAILED""); + $finish(); + end + end + + $display(""PASSED""); +end + +endmodule +" +"module top; + integer res, ival; + reg [7:0] rg; + reg [7:0] mem [3:0]; + + initial begin + res = $fread(ival, 1); // 1st arg. must be a reg. or memory. + res = $fread(rg); // Too few argument. + res = $fread(mem, ""a""); // Not a valid fd. + res = $fread(mem, 1, ""a""); // Not a valid start. + res = $fread(mem, 1, 0, ""a""); // Not a valid count. + res = $fread(mem, 1, 0, 2, 3); // Too many argument. + end +endmodule +" +"module top; + real q_tst [$]; + real q_tmp [$]; + real elem; + integer idx; + bit passed; + + task automatic check_size(integer size, + string fname, + integer lineno); + if (q_tst.size !== size) begin + $display(""%s:%0d: Failed: queue size != %0d (%0d)"", + fname, lineno, size, q_tst.size); + passed = 1\'b0; + end + endtask + + task automatic check_idx_value(integer idx, + real expected, + string fname, + integer lineno); + if (q_tst[idx] != expected) begin + $display(""%s:%0d: Failed: element [%0d] != %.1f (%.1f)"", + fname, lineno, idx, expected, q_tst[idx]); + passed = 1\'b0; + end + endtask + + initial begin + passed = 1\'b1; + + q_tst.delete(0); // Warning: skip delete on an empty queue + check_size(0, `__FILE__, `__LINE__); + check_idx_value(0, 0.0, `__FILE__, `__LINE__); + + elem = q_tst.pop_front(); // Warning: cannot pop_front() an empty queue + if (elem != 0.0) begin + $display(""Failed: pop_front() != 0.0 (%.1f)"", elem); + passed = 1\'b0; + end + + elem = q_tst.pop_back(); // Warning: cannot pop_back() an empty queue + if (elem != 0.0) begin + $display(""Failed: pop_back() != 0.0 (%.1f)"", elem); + passed = 1\'b0; + end + + q_tst.push_back(2.0); + q_tst.push_front(1.0); + q_tst.push_back(3.0); + q_tst.push_back(100.0); + q_tst.delete(3); // Should $ work here? + q_tst.delete(3); // Warning: skip an out of range delete() + q_tst.delete(-1); // Warning: skip delete with negative index + q_tst.delete(\'X); // Warning: skip delete with undefined index + + check_size(3, `__FILE__, `__LINE__); + + if (q_tst[0] != 1.0) begin + $display(""Failed: element [0] != 1.0 (%.1f)"", q_tst[0]); + passed = 1\'b0; + end + + if (q_tst[1] != 2.0) begin + $display(""Failed: element [1] != 2.0 (%.1f)"", q_tst[1]); + passed = 1\'b0; + end + + if (q_tst[2] != 3.0) begin + $display(""Failed: element [2] != 3.0 (%.1f)"", q_tst[2]); + passed = 1\'b0; + end + + if (q_tst[3] != 0.0) begin + $display(""Failed: element [3] != 0.0 (%.1f)"", q_tst[3]); + passed = 1\'b0; + end + + if (q_tst[-1] != 0.0) begin + $display(""Failed: element [-1] != 0.0 (%.1f)"", q_tst[-1]); + passed = 1\'b0; + end + + if (q_tst[\'X] != 0.0) begin + $display(""Failed: element [\'X] != 0.0 (%.1f)"", q_tst[\'X]); + passed = 1\'b0; + end + + check_idx_value(-1, 0.0, `__FILE__, `__LINE__); + check_idx_value(\'X, 0.0, `__FILE__, `__LINE__); + + elem = q_tst.pop_front(); + if (elem != 1.0) begin + $display(""Failed: element pop_front() != 1.0 (%.1f)"", elem); + passed = 1\'b0; + end + + elem = q_tst.pop_back(); + if (elem != 3.0) begin + $display(""Failed: element pop_back() != 3.0 (%.1f)"", elem); + passed = 1\'b0; + end + + check_size(1, `__FILE__, `__LINE__); + + if ((q_tst[0] != q_tst[$]) || (q_tst[0] != 2.0)) begin + $display(""Failed: q_tst[0](%.1f) != q_tst[$](%.1f) != 2.0"", + q_tst[0], q_tst[$]); + passed = 1\'b0; + end + + q_tst.delete(); + + check_size(0, `__FILE__, `__LINE__); + + q_tst.push_front(5.0); + q_tst.push_front(100.0); + q_tst.push_back(100.0); + elem = q_tst.pop_back; + elem = q_tst.pop_front; + + check_size(1, `__FILE__, `__LINE__); + check_idx_value(0, 5.0, `__FILE__, `__LINE__); + + q_tst[0] = 1.0; + q_tst[1] = 2.5; + q_tst[1] = 2.0; + q_tst[2] = 3.0; + q_tst[-1] = 10.0; // Warning: will not be added (negative index) + q_tst[\'X] = 10.0; // Warning: will not be added (undefined index) + q_tst[4] = 10.0; // Warning: will not be added (out of range index) + + idx = -1; + q_tst[idx] = 10.0; // Warning: will not be added (negative index) + idx = 3\'b0x1; + q_tst[idx] = 10.0; // Warning: will not be added (undefined index) + idx = 4; + q_tst[idx] = 10.0; // Warning: will not be added (out of range index) + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, 1.0, `__FILE__, `__LINE__); + check_idx_value(1, 2.0, `__FILE__, `__LINE__); + check_idx_value(2, 3.0, `__FILE__, `__LINE__); + + q_tst.delete(); + q_tst[0] = 2.0; + q_tst.insert(1, 4.0); + q_tst.insert(0, 1.0); + q_tst.insert(2, 3.0); + q_tst.insert(-1, 10.0); // Warning: will not be added (negative index) + q_tst.insert(\'X, 10.0); // Warning: will not be added (undefined index) + q_tst.insert(5, 10.0); // Warning: will not be added (out of range index) + + check_size(4, `__FILE__, `__LINE__); + check_idx_value(0, 1.0, `__FILE__, `__LINE__); + check_idx_value(1, 2.0, `__FILE__, `__LINE__); + check_idx_value(2, 3.0, `__FILE__, `__LINE__); + check_idx_value(3, 4.0, `__FILE__, `__LINE__); + + q_tst = \'{3.0, 2.0, 1.0}; + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, 3.0, `__FILE__, `__LINE__); + check_idx_value(1, 2.0, `__FILE__, `__LINE__); + check_idx_value(2, 1.0, `__FILE__, `__LINE__); + + q_tmp = \'{1.0, 2.0}; + q_tst = q_tmp; + q_tmp[0] = 3.0; + q_tmp[2] = 1.0; + + check_size(2, `__FILE__, `__LINE__); + check_idx_value(0, 1.0, `__FILE__, `__LINE__); + check_idx_value(1, 2.0, `__FILE__, `__LINE__); + + q_tst[2] = 3.0; + check_size(3, `__FILE__, `__LINE__); + check_idx_value(2, 3.0, `__FILE__, `__LINE__); + + q_tst = {1.0, 2.0}; + check_size(2, `__FILE__, `__LINE__); + check_idx_value(0, 1.0, `__FILE__, `__LINE__); + check_idx_value(1, 2.0, `__FILE__, `__LINE__); + + q_tst = \'{}; + + check_size(0, `__FILE__, `__LINE__); + + if (passed) $display(""PASSED""); + + end +endmodule : top +" +" +/* + * This is a post-synthesis test for the blif_sign_ext.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif_sign_ext.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif_sign_ext_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter W=3, WO=5; + reg signed [W:0] D; + reg signed [WO:0] q; + wire [WO:0] Q; + + sign_ext se(.\\D[3] (D[3]), .\\D[2] (D[2]), .\\D[1] (D[1]), .\\D[0] (D[0]), + .\\Q[5] (Q[5]), .\\Q[4] (Q[4]), .\\Q[3] (Q[3]), .\\Q[2] (Q[2]), .\\Q[1] (Q[1]), .\\Q[0] (Q[0])); + + int\t\t ddx; + initial begin + for (ddx = 0 ; ddx < 1 << (W+1) ; ddx = ddx+1) begin +\t D = ddx[W:0]; + q = D; + + $display(""D = %b, q = %b"", D, q); + + #1; +\t if (Q !== q) begin +\t $display(""FAILED -- D=%b, Q=%b (should be %b)"", D, Q, q); +\t $finish; + end + end + $display(""PASSED""); + end + +endmodule // main +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW - Validation of assign construct +// +// D: Create a 32 bit vector and assign succesive values to +// D: the Right hand side expression. Verify the result is +// D: correct. +// + +module main (); + +wire [31:0] result; +reg [31:0] a,b ; + +assign result = a | b; + +initial\t// Excitation block + begin + a = 0; + b = 0; + # 5; + a = 32\'haaaaaaaa ; + # 5; + b = 32\'h55555555 ; + # 5 ; + end + +initial // Validation block + begin + # 1; + if(result != 32\'h0) + begin + $display(""FAILED - result not initialized\ +""); + $finish ; + end + + # 5; + if(result != 32\'haaaaaaaa) + begin + $display(""FAILED - result not updated\ +""); + $finish ; + end + + # 5; + if(result != 32\'hffffffff) + begin + $display(""FAILED - result not updated\ +""); + $finish ; + end + + $display(""PASSED\ +""); + $finish ; + end + +endmodule +" +"`ifndef MACRO1 +`define MACRO1 21 +`endif +`ifndef MACRO2 +`define MACRO2 22 +`endif +`ifndef MACRO3 +`define MACRO3 23 +`endif + +module test2(input w); + +buf(a,b); + +initial #2 begin + $display(""test2 macro1 = %0d"", `MACRO1 ); + $display(""test2 macro2 = %0d"", `MACRO2 ); + $display(""test2 macro3 = %0d"", `MACRO3 ); + $display(""test2 wire = %b"", a); +end + +endmodule +" +"module main; + + generate + genvar i; + for( i=0; i<4; i=i+2 ) +\tbegin : U +\t reg [1:0] a; +\t initial begin : V +\t a = 2\'b0; +\t #10; +\t a = i; +\t end +\tend + endgenerate + + initial begin + #5 ; + if (U[0].V.a !== 2\'d0) begin +\t $display(""FAILED -- U[0].V.a = %d"", U[0].V.a); +\t $finish; + end + if (U[2].V.a !== 2\'d0) begin +\t $display(""FAILED -- U[2].V.a = %d"", U[2].V.a); +\t $finish; + end + #10 ; + if (U[0].V.a !== 2\'d0) begin +\t $display(""FAILED -- U[0].V.a = %d"", U[0].V.a); +\t $finish; + end + if (U[2].V.a !== 2\'d2) begin +\t $display(""FAILED -- U[2].V.a = %d"", U[2].V.a); +\t $finish; + end + $display(""PASSED""); + $finish; + end + +endmodule +" +"module main; + + wire [15:0] out; + reg [16:0] in; + + mask dut (.\\output (out), .\\input (in[15:0])); + + wire [15:0] out_ref = in[15:0] & 16\'haaaa; + initial begin + for (in = 0 ; in[16] == 0 ; in = in+1) +\t#1 if (out !== out_ref) begin +\t $display(""FAILED: in=%b, out=%b, out_ref=%b"", in, out, out_ref); +\t $finish; +\tend + + $display(""PASSED""); + end + +endmodule // main +" +"/* + * integer1 - a verilog test for integer conditionals + * + * Copyright (C) 1999 Stephen G. Tell + * Portions inspired by qmark.v by Steven Wilson (stevew@home.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ + +module integer1lt; + + integer a; + integer b; + reg\t error; + + initial begin + error = 0; + + a = 2; + if(a < 2) begin +\t $display(""FAILED 2 < 2""); +\t error = 1; + end + + a = 3; + if(a < 2) begin +\t $display(""FAILED 3 < 2""); +\t error = 1; + end + + a = 1; + if(a < 2) begin +\t b = 1; + end else begin +\t $display(""FAILED 1 < 2""); +\t error = 1; + end + + b = 0; + for(a = 0; a < 5; a = a + 1) begin +\t b = b + a; + end // for (a = 0; a < 5; a = a + 1) + + if(b != 10) begin +\t $display(""FAILED forloop b=%d expected 10"", b); +\t error = 1; + end + + if(error == 0) +\t $display(""PASSED""); + $finish; + + end // initial begin + +endmodule +" +"module top; + // This should be a compilation error. + parameter PARAMB = PARAMB + 6; + + initial $display(""FAILED""); +endmodule +" +"/* + * Copyright (c) 2001 Peter Bain + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* This is based on PR#124. */ + +`timescale 1ns/1ns +module paramtest(clk, dat); + parameter dat_width = 32; + input clk; + output [dat_width-1:0] dat; + + reg [dat_width-1:0]\t dat; + reg [4-1:0]\t\t exp_dat; + parameter\t\t pay_init = 32\'h01020304; + parameter\t\t pay_inc = 32\'h01010101; + + parameter\t\t cell_size = (53 * 8); + parameter\t\t transfers = cell_size/dat_width + ((cell_size%dat_width)?1:0); + + initial begin + exp_dat = 0; + dat = 0; + end + + + initial begin + #10; + for (exp_dat = 0; exp_dat != 4\'hf; exp_dat = exp_dat + 1) begin + dat <= exp_dat; + #1 + if (dat !== exp_dat) begin + $display(""ERROR: dat = %h, exp_dat = %h"", dat, exp_dat); +\t end else begin + $display(""OKAY: dat = %h, exp_dat = %h"", dat, exp_dat); + end + end + end +endmodule +" +"module top; + reg q, en, d; + event foo; + + always_latch begin + if (en) @foo q <= d; + end + + initial $display(""Expected compile failure!""); + +endmodule +" +"`timescale 1ns/1ps + +module top; + realtime rtime; + time itime; + + initial begin + repeat (5) begin + rtime = $realtime; + itime = $time; + $display(""%t %.2f %2d, %t %0.2f %2d, %t %.2f, %t %0.2f, %t %.2f,"", + $time, $time, $time, itime, itime, itime, + $realtime, $realtime, rtime, rtime, rtm($realtime), + rtm($realtime),, $time,, $realtime); + #0.6; + end + end + + function real rtm; + input real rin; + rtm = rin; + endfunction +endmodule +" +"module stimulus (output reg A); + + initial begin + A = 1\'b0; + #10 A = 1\'b1; + end + +endmodule + +module scoreboard (input Y, A); + +function truth_table (input a); + reg gate_operand; + reg gate_output; + begin + gate_operand = a; + case (gate_operand) + 1\'b0: gate_output = 1; + 1\'b1: gate_output = 0; + endcase + + truth_table = gate_output; + end +endfunction + + +reg Y_t; + +always @(A) begin + Y_t = truth_table (A); + #1; + //$display (""a = %b, b = %b, Y_s = %b, Y = %b"", A, B, Y_s, Y); + if (Y_t !== Y) begin + $display(""FAILED! - mismatch found for inputs %b in NOT operation"", A); + $finish; + end +end + +endmodule + +module test; + stimulus stim (A); + not_gate duv (.a_i(A), .c_o(Y) ); + scoreboard mon (Y, A); + + initial begin + #100; + $display(""PASSED""); + $finish; + end + +endmodule +" +"module sub8(output wire [7:0] out, input wire [7:0] A, input wire [7:0] B); + + assign out = A - B; + +endmodule +" +"module check (input unsigned [103:0] a, b, c); + wire [103:0] int_AB; + + assign int_AB = ~(a ^ b); + +always @(a, b, int_AB, c) begin + #1; + if (int_AB !== c) begin + $display(""ERROR""); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [103:0] A, B); + parameter S = 2000; + int unsigned i; + + + initial begin + A = 0; B= 0; + // values with 0, 1 + for (i=0; i>4); + end +endmodule +" +"// This tests SystemVerilog packages +// +// This tests the elaboration infrastructure of packages in +// SystemVerilog. It actually covers a fair number of features, +// given the small size of the program: +// +// *) Parsing of package blocks and import statements +// *) Manage scope of names in package +// *) Actual references of imported names from packages. +// + +package pkg; + parameter int foo = 1; +endpackage + + +module test (); + + // import all from p1 + import pkg::foo; + + initial begin + $display(""pkg::foo = %0d"", foo); + if (foo != 1) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""PASSED""); + end + +endmodule // test +" +"module top; + real rval1=1.0, rval2=2.0; + realtime rtval=1.0; + + initial begin + $display(""rval1="", rval1,,""rval2="", rval2,,""rtval="",rtval); + end +endmodule +" +"module test; + +// force leading zero on outer scope genblk numbers +localparam genblk1 = 0; +localparam genblk2 = 0; +localparam genblk3 = 0; +localparam genblk4 = 0; +localparam genblk5 = 0; +localparam genblk6 = 0; +localparam genblk7 = 0; +localparam genblk8 = 0; +localparam genblk9 = 0; + +parameter TRUE = 1; + +genvar i; +genvar j; + +for (i = 0; i < 2; i = i + 1) begin + reg r1 = 1; +end + +for (i = 0; i < 2; i = i + 1) begin + for (j = 0; j < 2; j = j + 1) begin + reg r2 = 1; + end +end + +for (i = 0; i < 2; i = i + 1) begin + case (TRUE) + 0: begin + reg r3a = 1; + end + 1: begin + reg r3b = 1; + end + endcase +end + +for (i = 0; i < 2; i = i + 1) begin + if (TRUE) + begin + reg r4a = 1; + end + else + begin + reg r4b = 1; + end +end + +for (i = 0; i < 2; i = i + 1) begin + if (!TRUE) + begin + reg r5a = 1; + end + else + begin + if (TRUE) + begin + reg r5b = 1; + end + else + begin + reg r5c = 1; + end + end +end + +for (i = 0; i < 2; i = i + 1) begin + if (!TRUE) + begin + reg r6a = 1; + end + else + begin + if (!TRUE) + begin + reg r6b = 1; + end + else + begin + reg r6c = 1; + end + end +end + +case (TRUE) + 0: begin + reg r7a = 1; + end + 1: begin + reg r7b = 1; + end +endcase + +case (TRUE) + 0: begin + case (TRUE) + 0: begin + reg r8a = 1; + end + 1: begin + reg r8b = 1; + end + endcase + end + 1: begin + case (TRUE) + 0: begin + reg r8c = 1; + end + 1: begin + reg r8d = 1; + end + endcase + end +endcase + +case (TRUE) + 0: begin + if (TRUE) + begin + reg r9a = 1; + end + else + begin + reg r9b = 1; + end + end + 1: begin + if (TRUE) + begin + reg r9c = 1; + end + else + begin + reg r9d = 1; + end + end +endcase + +case (TRUE) + 0: begin + if (!TRUE) + begin + reg r10a = 1; + end + else + begin + if (TRUE) + begin + reg r10b = 1; + end + else + begin + reg r10c = 1; + end + end + end + 1: begin + if (!TRUE) + begin + reg r10d = 1; + end + else + begin + if (TRUE) + begin + reg r10e = 1; + end + else + begin + reg r10f = 1; + end + end + end +endcase + +case (TRUE) + 0: begin + if (!TRUE) + begin + reg r11a = 1; + end + else + begin + if (!TRUE) + begin + reg r11b = 1; + end + else + begin + reg r11c = 1; + end + end + end + 1: begin + if (!TRUE) + begin + reg r11d = 1; + end + else + begin + if (!TRUE) + begin + reg r11e = 1; + end + else + begin + reg r11f = 1; + end + end + end +endcase + +case (TRUE) + 0: begin + if (!TRUE) + begin + reg r12a = 1; + end + else if (TRUE) + begin + reg r12b = 1; + end + else + begin + reg r12c = 1; + end + end + 1: begin + if (!TRUE) + begin + reg r12d = 1; + end + else if (TRUE) + begin + reg r12e = 1; + end + else + begin + reg r12f = 1; + end + end +endcase + +case (TRUE) + 0: begin + if (!TRUE) + begin + reg r13a = 1; + end + else if (!TRUE) + begin + reg r13b = 1; + end + else + begin + reg r13c = 1; + end + end + 1: begin + if (!TRUE) + begin + reg r13d = 1; + end + else if (!TRUE) + begin + reg r13e = 1; + end + else + begin + reg r13f = 1; + end + end +endcase + +if (TRUE) + begin + reg r14a = 1; + end +else + begin + reg r14b = 1; + end + +if (!TRUE) + begin + reg r15a = 1; + end +else + begin + if (TRUE) + begin + reg r15b = 1; + end + else + begin + reg r15c = 1; + end + end + +if (!TRUE) + begin + reg r16a = 1; + end +else + begin + if (!TRUE) + begin + reg r16b = 1; + end + else + begin + reg r16c = 1; + end + end + +if (!TRUE) + begin + reg r17a = 1; + end +else if (TRUE) + begin + reg r17b = 1; + end +else + begin + reg r17c = 1; + end + +if (!TRUE) + begin + reg r18a = 1; + end +else if (!TRUE) + begin + reg r18b = 1; + end +else + begin + reg r18c = 1; + end + +if (TRUE) + begin + if (TRUE) + begin + reg r19a = 1; + end + else + begin + reg r19b = 1; + end + end +else + begin + reg r19c = 1; + end + +if (TRUE) + begin + if (!TRUE) + begin + reg r20a = 1; + end + else + begin + reg r20b = 1; + end + end +else + begin + reg r20c = 1; + end + +if (TRUE) + begin + case (TRUE) + 0: begin + reg r21a = 1; + end + 1: begin + reg r21b = 1; + end + endcase + end +else + begin + case (TRUE) + 0: begin + reg r21c = 1; + end + 1: begin + reg r21d = 1; + end + endcase + end + +if (!TRUE) + begin + case (TRUE) + 0: begin + reg r22a = 1; + end + 1: begin + reg r22b = 1; + end + endcase + end +else if (TRUE) + begin + case (TRUE) + 0: begin + reg r22c = 1; + end + 1: begin + reg r22d = 1; + end + endcase + end +else + begin + case (TRUE) + 0: begin + reg r22e = 1; + end + 1: begin + reg r22f = 1; + end + endcase + end + +if (!TRUE) + begin + case (TRUE) + 0: begin + reg r23a = 1; + end + 1: begin + reg r23b = 1; + end + endcase + end +else if (!TRUE) + begin + case (TRUE) + 0: begin + reg r23c = 1; + end + 1: begin + reg r23d = 1; + end + endcase + end +else + begin + case (TRUE) + 0: begin + reg r23e = 1; + end + 1: begin + reg r23f = 1; + end + endcase + end + +initial begin + $list_regs; +end + +endmodule +" +"// +// Copyright (c) 2000 Paul Campbell (paul@verifarm.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +module compl1000; +\treg\t[158:143]r0; +\treg\t[128:104]r1; +\treg\t[200:173]r2; +\treg\t[165:162]r3; +\treg\t[150:129]r4; +\treg\t[123:93]r5; +\treg\t[55:54]r6; +\treg\t[24:3]r7; +\treg\t[109:93]r8; +\treg\t[30:14]r9; +\treg\t[184:174]r10; +\treg\t[59:30]r11; +\treg\t[153:124]r12; +\treg\t[248:221]r13; +\treg\t[258:250]r14; +\treg\t[158:147]r15; +\treg\t[54:48]r16; +\treg\t[159:136]r17; +\treg\t[214:187]r18; +\treg\t[60:29]r19; +\treg\t[71:71]r20; +\treg\t[177:169]r21; +\treg\t[219:205]r22; +\treg\t[24:21]r23; +\treg\t[153:141]r24; +\treg\t[85:54]r25; +\treg\t[227:202]r26; +\treg\t[251:237]r27; +\treg\t[98:73]r28; +\treg\t[24:0]r29; +\treg\t[166:135]r30; +\treg\t[184:183]r31; +\treg\t[219:189]r32; +\treg\t[81:54]r33; +\treg\t[164:148]r34; +\treg\t[170:158]r35; +\treg\t[171:168]r36; +\treg\t[255:226]r37; +\treg\t[197:191]r38; +\treg\t[113:105]r39; +\treg\t[221:198]r40; +\treg\t[135:104]r41; +\treg\t[153:143]r42; +\treg\t[281:253]r43; +\treg\t[101:76]r44; +\treg\t[24:12]r45; +\treg\t[217:203]r46; +\treg\t[244:218]r47; +\treg\t[128:111]r48; +\treg\t[136:107]r49; +\treg\t[260:242]r50; +\treg\t[157:156]r51; +\treg\t[242:220]r52; +\treg\t[278:255]r53; +\treg\t[196:194]r54; +\treg\t[148:121]r55; +\treg\t[71:63]r56; +\treg\t[166:157]r57; +\treg\t[200:180]r58; +\treg\t[230:199]r59; +\treg\t[212:191]r60; +\treg\t[264:248]r61; +\treg\t[136:124]r62; +\treg\t[131:117]r63; +\treg\t[148:126]r64; +\treg\t[51:30]r65; +\treg\t[166:140]r66; +\treg\t[166:143]r67; +\treg\t[44:27]r68; +\treg\t[259:248]r69; +\treg\t[167:143]r70; +\treg\t[210:189]r71; +\treg\t[73:50]r72; +\treg\t[225:205]r73; +\treg\t[255:240]r74; +\treg\t[208:194]r75; +\treg\t[222:217]r76; +\treg\t[217:189]r77; +\treg\t[100:83]r78; +\treg\t[275:255]r79; +\treg\t[39:34]r80; +\treg\t[98:72]r81; +\treg\t[55:25]r82; +\treg\t[246:240]r83; +\treg\t[170:157]r84; +\treg\t[218:198]r85; +\treg\t[225:223]r86; +\treg\t[186:172]r87; +\treg\t[241:213]r88; +\treg\t[263:238]r89; +\treg\t[272:253]r90; +\treg\t[105:103]r91; +\treg\t[211:209]r92; +\treg\t[89:82]r93; +\treg\t[30:9]r94; +\treg\t[246:241]r95; +\treg\t[170:147]r96; +\treg\t[229:224]r97; +\treg\t[107:83]r98; +\treg\t[60:54]r99; +\treg\t[154:154]r100; +\treg\t[105:97]r101; +\treg\t[127:104]r102; +\treg\t[219:190]r103; +\treg\t[114:98]r104; +\treg\t[267:251]r105; +\treg\t[169:145]r106; +\treg\t[64:45]r107; +\treg\t[227:224]r108; +\treg\t[186:176]r109; +\treg\t[101:84]r110; +\treg\t[219:194]r111; +\treg\t[11:9]r112; +\treg\t[236:222]r113; +\treg\t[271:240]r114; +\treg\t[232:218]r115; +\treg\t[78:74]r116; +\treg\t[191:191]r117; +\treg\t[242:227]r118; +\treg\t[135:108]r119; +\treg\t[24:15]r120; +\treg\t[250:233]r121; +\treg\t[125:102]r122; +\treg\t[165:140]r123; +\treg\t[63:63]r124; +\treg\t[235:206]r125; +\treg\t[264:237]r126; +\treg\t[241:234]r127; +\treg\t[188:188]r128; +\treg\t[71:59]r129; +\treg\t[181:170]r130; +\treg\t[106:83]r131; +\treg\t[245:229]r132; +\treg\t[239:219]r133; +\treg\t[10:8]r134; +\treg\t[45:45]r135; +\treg\t[23:22]r136; +\treg\t[197:178]r137; +\treg\t[57:50]r138; +\treg\t[264:253]r139; +\treg\t[53:36]r140; +\treg\t[187:164]r141; +\treg\t[153:140]r142; +\treg\t[235:226]r143; +\treg\t[236:228]r144; +\treg\t[262:238]r145; +\treg\t[76:55]r146; +\treg\t[49:25]r147; +\treg\t[191:163]r148; +\treg\t[197:170]r149; +\treg\t[151:143]r150; +\treg\t[126:122]r151; +\treg\t[188:173]r152; +\treg\t[93:78]r153; +\treg\t[175:175]r154; +\treg\t[249:247]r155; +\treg\t[214:200]r156; +\treg\t[60:43]r157; +\treg\t[263:233]r158; +\treg\t[54:34]r159; +\treg\t[202:184]r160; +\treg\t[250:240]r161; +\treg\t[99:80]r162; +\treg\t[175:165]r163; +\treg\t[189:188]r164; +\treg\t[52:38]r165; +\treg\t[74:48]r166; +\treg\t[232:202]r167; +\treg\t[24:13]r168; +\treg\t[209:180]r169; +\treg\t[173:147]r170; +\treg\t[264:243]r171; +\treg\t[115:99]r172; +\treg\t[94:91]r173; +\treg\t[195:188]r174; +\treg\t[36:33]r175; +\treg\t[136:114]r176; +\treg\t[82:56]r177; +\treg\t[204:173]r178; +\treg\t[116:111]r179; +\treg\t[124:103]r180; +\treg\t[76:71]r181; +\treg\t[178:163]r182; +\treg\t[156:149]r183; +\treg\t[124:110]r184; +\treg\t[240:220]r185; +\treg\t[164:151]r186; +\treg\t[133:104]r187; +\treg\t[59:46]r188; +\treg\t[47:42]r189; +\treg\t[219:189]r190; +\treg\t[99:87]r191; +\treg\t[86:73]r192; +\treg\t[222:191]r193; +\treg\t[23:7]r194; +\treg\t[239:238]r195; +\treg\t[240:222]r196; +\treg\t[27:4]r197; +\treg\t[191:160]r198; +\treg\t[106:84]r199; +\treg\t[22:8]r200; +\treg\t[204:191]r201; +\treg\t[133:115]r202; +\treg\t[225:207]r203; +\treg\t[126:95]r204; +\treg\t[161:147]r205; +\treg\t[193:164]r206; +\treg\t[69:61]r207; +\treg\t[130:116]r208; +\treg\t[142:124]r209; +\treg\t[50:20]r210; +\treg\t[175:154]r211; +\treg\t[102:87]r212; +\treg\t[114:85]r213; +\treg\t[225:223]r214; +\treg\t[131:127]r215; +\treg\t[24:19]r216; +\treg\t[84:84]r217; +\treg\t[223:223]r218; +\treg\t[171:159]r219; +\treg\t[76:47]r220; +\treg\t[162:139]r221; +\treg\t[67:41]r222; +\treg\t[88:74]r223; +\treg\t[60:44]r224; +\treg\t[114:104]r225; +\treg\t[142:141]r226; +\treg\t[262:236]r227; +\treg\t[16:12]r228; +\treg\t[66:51]r229; +\treg\t[40:24]r230; +\treg\t[150:141]r231; +\treg\t[209:199]r232; +\treg\t[152:148]r233; +\treg\t[162:147]r234; +\treg\t[82:80]r235; +\treg\t[245:214]r236; +\treg\t[35:12]r237; +\treg\t[18:3]r238; +\treg\t[270:246]r239; +\treg\t[183:170]r240; +\treg\t[122:121]r241; +\treg\t[60:42]r242; +\treg\t[99:91]r243; +\treg\t[61:51]r244; +\treg\t[154:150]r245; +\treg\t[5:3]r246; +\treg\t[275:246]r247; +\treg\t[113:92]r248; +\treg\t[136:118]r249; +\treg\t[94:71]r250; +\treg\t[104:91]r251; +\treg\t[169:139]r252; +\treg\t[22:14]r253; +\treg\t[255:236]r254; +\treg\t[213:186]r255; +\tinitial begin +\t\tr0 = 32'h3d24; +\t\tr1 = 32'h70fd; +\t\tr2 = 32'h47aa; +\t\tr3 = 32'h39ed; +\t\tr4 = 32'h2ca3; +\t\tr5 = 32'he68; +\t\tr6 = 32'h1160; +\t\tr7 = 32'h5636; +\t\tr8 = 32'h2305; +\t\tr9 = 32'h1257; +\t\tr10 = 32'h4e74; +\t\tr11 = 32'h3835; +\t\tr12 = 32'h3857; +\t\tr13 = 32'h3f6f; +\t\tr14 = 32'h7b33; +\t\tr15 = 32'h2f37; +\t\tr16 = 32'h10a; +\t\tr17 = 32'h6cff; +\t\tr18 = 32'h3f3; +\t\tr19 = 32'h70e2; +\t\tr20 = 32'h4cb3; +\t\tr21 = 32'h510; +\t\tr22 = 32'h1837; +\t\tr23 = 32'h425; +\t\tr24 = 32'h1488; +\t\tr25 = 32'h5731; +\t\tr26 = 32'h1388; +\t\tr27 = 32'h6ee0; +\t\tr28 = 32'h559b; +\t\tr29 = 32'h4bff; +\t\tr30 = 32'h180e; +\t\tr31 = 32'h1252; +\t\tr32 = 32'h52d4; +\t\tr33 = 32'h4576; +\t\tr34 = 32'h36f1; +\t\tr35 = 32'h6246; +\t\tr36 = 32'h7aaf; +\t\tr37 = 32'h37fb; +\t\tr38 = 32'h4272; +\t\tr39 = 32'h62fd; +\t\tr40 = 32'h6cbb; +\t\tr41 = 32'h4825; +\t\tr42 = 32'h25c7; +\t\tr43 = 32'h19da; +\t\tr44 = 32'h5ace; +\t\tr45 = 32'h794f; +\t\tr46 = 32'h5ebb; +\t\tr47 = 32'h5cd0; +\t\tr48 = 32'h4209; +\t\tr49 = 32'h38de; +\t\tr50 = 32'h7502; +\t\tr51 = 32'h2c8c; +\t\tr52 = 32'h378f; +\t\tr53 = 32'h5252; +\t\tr54 = 32'hb5d; +\t\tr55 = 32'h561; +\t\tr56 = 32'h4504; +\t\tr57 = 32'h180f; +\t\tr58 = 32'h6672; +\t\tr59 = 32'h52f7; +\t\tr60 = 32'h10c7; +\t\tr61 = 32'h4ce9; +\t\tr62 = 32'h569; +\t\tr63 = 32'h72b3; +\t\tr64 = 32'h4df0; +\t\tr65 = 32'h1a72; +\t\tr66 = 32'h2846; +\t\tr67 = 32'h70e5; +\t\tr68 = 32'h3008; +\t\tr69 = 32'h2003; +\t\tr70 = 32'h6009; +\t\tr71 = 32'h6cb5; +\t\tr72 = 32'h5e8b; +\t\tr73 = 32'h668b; +\t\tr74 = 32'h487; +\t\tr75 = 32'h4eca; +\t\tr76 = 32'h241e; +\t\tr77 = 32'h451a; +\t\tr78 = 32'h2c06; +\t\tr79 = 32'h3ebf; +\t\tr80 = 32'h5590; +\t\tr81 = 32'h22c; +\t\tr82 = 32'h9b; +\t\tr83 = 32'h347; +\t\tr84 = 32'h2c92; +\t\tr85 = 32'h3db6; +\t\tr86 = 32'hf44; +\t\tr87 = 32'h391a; +\t\tr88 = 32'h1237; +\t\tr89 = 32'h6ff2; +\t\tr90 = 32'h6cc5; +\t\tr91 = 32'hca7; +\t\tr92 = 32'h152a; +\t\tr93 = 32'h8eb; +\t\tr94 = 32'h4c43; +\t\tr95 = 32'h6277; +\t\tr96 = 32'h7b1; +\t\tr97 = 32'h7cc8; +\t\tr98 = 32'h63a2; +\t\tr99 = 32'h1a62; +\t\tr100 = 32'h165; +\t\tr101 = 32'h48d8; +\t\tr102 = 32'h399e; +\t\tr103 = 32'h5975; +\t\tr104 = 32'h40ae; +\t\tr105 = 32'h3d61; +\t\tr106 = 32'h39ab; +\t\tr107 = 32'h69f; +\t\tr108 = 32'h2801; +\t\tr109 = 32'h1828; +\t\tr110 = 32'h298d; +\t\tr111 = 32'h661e; +\t\tr112 = 32'h52d9; +\t\tr113 = 32'h3bc0; +\t\tr114 = 32'h5cb7; +\t\tr115 = 32'h7fac; +\t\tr116 = 32'h7e76; +\t\tr117 = 32'hf93; +\t\tr118 = 32'h4165; +\t\tr119 = 32'h3b68; +\t\tr120 = 32'h4258; +\t\tr121 = 32'h54b2; +\t\tr122 = 32'h2378; +\t\tr123 = 32'h6186; +\t\tr124 = 32'h547a; +\t\tr125 = 32'h7b5c; +\t\tr126 = 32'h4115; +\t\tr127 = 32'h68b6; +\t\tr128 = 32'h554f; +\t\tr129 = 32'h4550; +\t\tr130 = 32'hcfc; +\t\tr131 = 32'h3f55; +\t\tr132 = 32'h5f7d; +\t\tr133 = 32'h40d2; +\t\tr134 = 32'h3aa8; +\t\tr135 = 32'h7b56; +\t\tr136 = 32'h575c; +\t\tr137 = 32'h687f; +\t\tr138 = 32'h702c; +\t\tr139 = 32'h1cee; +\t\tr140 = 32'h362d; +\t\tr141 = 32'h73d2; +\t\tr142 = 32'h39c8; +\t\tr143 = 32'h5003; +\t\tr144 = 32'h4d1a; +\t\tr145 = 32'h2472; +\t\tr146 = 32'h1b4e; +\t\tr147 = 32'h5852; +\t\tr148 = 32'h3bf2; +\t\tr149 = 32'h1c41; +\t\tr150 = 32'h5b37; +\t\tr151 = 32'h1462; +\t\tr152 = 32'h17a1; +\t\tr153 = 32'h825; +\t\tr154 = 32'h6384; +\t\tr155 = 32'h432c; +\t\tr156 = 32'h7c70; +\t\tr157 = 32'h2b94; +\t\tr158 = 32'h5456; +\t\tr159 = 32'h7887; +\t\tr160 = 32'h802; +\t\tr161 = 32'h18e2; +\t\tr162 = 32'h244c; +\t\tr163 = 32'h6c55; +\t\tr164 = 32'h770a; +\t\tr165 = 32'h224a; +\t\tr166 = 32'h6aa0; +\t\tr167 = 32'h1070; +\t\tr168 = 32'h62cd; +\t\tr169 = 32'h4fbe; +\t\tr170 = 32'h2f01; +\t\tr171 = 32'h1952; +\t\tr172 = 32'h5a5b; +\t\tr173 = 32'h656e; +\t\tr174 = 32'h5b2e; +\t\tr175 = 32'h6586; +\t\tr176 = 32'h538d; +\t\tr177 = 32'h471a; +\t\tr178 = 32'h2a57; +\t\tr179 = 32'h6fd2; +\t\tr180 = 32'h2fbd; +\t\tr181 = 32'h4418; +\t\tr182 = 32'h3233; +\t\tr183 = 32'h3821; +\t\tr184 = 32'h5048; +\t\tr185 = 32'h1824; +\t\tr186 = 32'h61e0; +\t\tr187 = 32'h4f33; +\t\tr188 = 32'h76c5; +\t\tr189 = 32'h2ceb; +\t\tr190 = 32'h127f; +\t\tr191 = 32'h7103; +\t\tr192 = 32'h6d02; +\t\tr193 = 32'h6856; +\t\tr194 = 32'h58b; +\t\tr195 = 32'h59fb; +\t\tr196 = 32'h30c3; +\t\tr197 = 32'h1397; +\t\tr198 = 32'h6cfd; +\t\tr199 = 32'h42da; +\t\tr200 = 32'h1f39; +\t\tr201 = 32'h26f4; +\t\tr202 = 32'h5922; +\t\tr203 = 32'h2f61; +\t\tr204 = 32'h5c44; +\t\tr205 = 32'h656; +\t\tr206 = 32'h2837; +\t\tr207 = 32'h7bc1; +\t\tr208 = 32'h7168; +\t\tr209 = 32'h7a91; +\t\tr210 = 32'h53ca; +\t\tr211 = 32'h54c4; +\t\tr212 = 32'h6091; +\t\tr213 = 32'h7371; +\t\tr214 = 32'h37d0; +\t\tr215 = 32'h6bd; +\t\tr216 = 32'h2687; +\t\tr217 = 32'h5e88; +\t\tr218 = 32'h2f85; +\t\tr219 = 32'h4f31; +\t\tr220 = 32'h692f; +\t\tr221 = 32'h1eba; +\t\tr222 = 32'h2407; +\t\tr223 = 32'h1d42; +\t\tr224 = 32'h4d87; +\t\tr225 = 32'h7085; +\t\tr226 = 32'h68b1; +\t\tr227 = 32'h6cdf; +\t\tr228 = 32'h315f; +\t\tr229 = 32'h4711; +\t\tr230 = 32'h138; +\t\tr231 = 32'h28ad; +\t\tr232 = 32'h44d8; +\t\tr233 = 32'h6dfb; +\t\tr234 = 32'h2d88; +\t\tr235 = 32'h3eb4; +\t\tr236 = 32'h3f9e; +\t\tr237 = 32'h7be1; +\t\tr238 = 32'h575c; +\t\tr239 = 32'h53ca; +\t\tr240 = 32'h2de5; +\t\tr241 = 32'h61ad; +\t\tr242 = 32'h3d9f; +\t\tr243 = 32'h41c0; +\t\tr244 = 32'h1124; +\t\tr245 = 32'h22a2; +\t\tr246 = 32'h7986; +\t\tr247 = 32'h4c4e; +\t\tr248 = 32'h5094; +\t\tr249 = 32'h128; +\t\tr250 = 32'h396a; +\t\tr251 = 32'h38be; +\t\tr252 = 32'h3567; +\t\tr253 = 32'h2c57; +\t\tr254 = 32'h4d66; +\t\tr255 = 32'h345b; +\t\t#10; r201 = $stime; +\t\t#10; r153 = ( ~ ( r189)); +\t\t#10; r200 = (3'h7 !== r2); +\t\t#10; r186 = r155; +\t\t#10; r208 = (((((( ( + ( (((16'h46d9 || r190) - $time) > (r127 >= (2'h0 !== r81))))) || ( | ( r150))) > r11) !== ((20'h617c * ( & ( r207))) > (r158 && (31'h6f3f - 19'h3eb3)))) * 17'h5321) - 25'h116f) ^ ((((($stime === r219) <= ($stime | (r43 < ((($stime ^ (( ( & ( ( ( & ( 26'h3af4)) | ( | ( 12'h8c7))))) && (r97 | 7'h3)) && 17'h7a8a)) == 9'h84) + ((18'h7e64 >= r240) >= r111))))) ^ 8'ha9) ^ ( - ( r15))) & (( ( & ( $time)) == r235) >= (( ( | ( r90)) || (r56 & r182)) !== r72)))); +\t\t#10; r175 = (($time / ((15'h7f3d === ( ( & ( r1)) == r2)) >= ((9'h78 % ( ( ^ ( ( - ( (r164 & (2'h2 >= (((((6'h1f == 28'h4032) / ( | ( 16'h5821))) | 28'h7b43) >= (r191 & $stime)) < ( + ( ((2'h3 % (12'hf20 - 16'h2734)) ? ( + ( (16'h1317 && 31'h16ee))) : (r137 < (6'h27 >= 3'h2)))))))))))) & ((( ( - ( (r169 ? ((r155 != 31'h60f0) >= ((r166 % (15'h587f - 30'h5197)) < r187)) : (((23'h220b <= 20'h46a) & (29'h584 > (10'h17 - 19'h53b7))) != ( & ( ( | ( (9'h1d0 <= 2'h0))))))))) ? r92 : ((($time <= 27'h6600) < (5'h13 ^ r99)) <= ( ! ( (((17'h2640 ? 2'h1 : r189) > $time) >= r248))))) ? (3'h2 - (9'h97 == ( ^ ( 4'h5)))) : ((1'h0 ? ( ( ! ( r34)) && ((r61 >= r73) == ((r184 === (19'h2c6c != 19'h34df)) | ( ~ ( r72))))) : 19'h64ff) >= (( ( ! ( (r24 !== ((7'h2b >= 1'h1) && ( ~ ( 4'he)))))) <= ( ^ ( r86))) / 12'hff3))) % (r35 < ( - ( 13'h8b9)))))) && r67))) - (((8'h12 !== (14'h2d97 <= ((r183 !== (((((r19 | r178) | (32'h743d != (r199 > ((28'h6bbb - 9'hc1) / ( + ( 18'h25d4)))))) | r255) < ( ( | ( (r12 | ((r255 % (30'h5e7b >= 11'h753)) < ( ( ~ ( 29'hc71)) || (20'h1ffc <= 17'h7cc5)))))) !== ((r181 * (((11'h18f || 17'h7265) ? 29'h485f : 4'he) == ( ( ~ ( 14'h1c84)) + 23'h298c))) || (((20'h79b3 ? (25'h1681 * 4'h9) : (12'ha6e * 26'h3ed1)) <= (r84 | (1'h1 % 2'h3))) ^ (r0 < ( ( ! ( 10'h336)) % (10'h149 / 3'h4))))))) || (r184 <= 26'h55e8))) ? 5'h17 : ( & ( (1'h0 >= r248)))))) + r191) | r65)); +\t\t#10; r28 = ( ( ! ( ($time <= r162))) !== r91); +\t\t#10; r125 = ($stime === ( - ( r231))); +\t\t#10; r237 = r93; +\t\t#10; r150 = (( ( - ( r183)) & ( ~ ( (23'h3dd8 === $time)))) > r75); +\t\t#10; r59 = (23'h7ddf * $stime); +\t\t#10; r157 = (3'h4 + (r27 | ( ^ ( (r175 ^ 8'h7b))))); +\t\t#10; r65 = r109; +\t\t#10; r241 = r88; +\t\t#10; r96 = 7'h62; +\t\t#10; r229 = (r248 + (r37 >= $time)); +\t\t#10; r112 = r160; +\t\t#10; r73 = 26'h5f00; +\t\t#10; r72 = r17; +\t\t#10; r2 = ( ( | ( (r124 + (( ( | ( (7'hf && (r196 ? r84 : ( ( & ( r51)) / r215))))) <= r7) <= ( | ( (r250 + ((20'h6268 % r214) / r19)))))))) * ( ( ! ( ((r249 % ($stime && (r140 * ( - ( ((r104 / 4'h4) <= (( ( + ( r250)) - ( | ( r68))) & ( ~ ( $time))))))))) || (r96 > (23'h4f58 < r185))))) !== 27'h5720)); +\t\t#10; r66 = r133; +\t\t#10; r199 = ( & ( (r2 % ( ^ ( ( - ( ( - ( r20))))))))); +\t\t#10; r47 = r109; +\t\t#10; r55 = (r96 / (r204 | ( + ( (((14'h519 / ((32'h2b24 ? ( ( | ( ( ^ ( r184)))) * (r123 < r123)) : ((((((r37 - (5'h13 == 10'h211)) == ( ! ( $time))) * 19'h76aa) >= ( ( | ( r211)) != r116)) ^ ( + ( 10'h25c))) ? (31'h68d3 !== (28'h6b7 ? ((($stime || ( + ( 25'h7c9a))) | (r74 === ( & ( 31'h28e9)))) % ( + ( ((1'h0 && 28'h6335) | ( - ( 13'h130c)))))) : 1'h0)) : ((r115 || ( | ( ( ( ~ ( r133)) && ((23'h30d3 ^ 32'h4295) % (18'h417d >= 22'h51c3)))))) && (((23'h7803 != ( ( ! ( 14'h1906)) ^ (19'h837 > 2'h2))) * (r198 <= (23'h1ee0 <= r55))) >= $stime)))) < ( ( ^ ( ((16'h5ded | (r217 / 17'h171e)) || 1'h0))) > r250))) < (8'h89 && (r15 | ( - ( r224))))) !== (((r244 === (((r229 <= 28'h441b) - ( ( | ( ((r244 - ((29'h24d7 != 17'h334f) == (8'h9f ^ 32'h3180))) ^ ( ^ ( (r238 * (21'h5f35 / 20'h5115))))))) * ( ( + ( ( - ( ( ~ ( (19'h79a9 ^ 24'h5d6a))))))) % r113))) > (((((r92 * (r232 * (22'h261f <= 14'h2bc3))) & (((20'h309a & 22'h7de2) && r181) < ((19'h7534 | 29'h18ae) > r188))) == ((((13'h46f && 25'h1d09) % r161) - ( ^ ( 30'h7cd8))) + ( - ( ((22'h6d8b || 29'h3b) ^ (21'h24f3 > 8'h7f)))))) | (r59 && (r191 >= ( ( & ( (12'h473 & 7'h69))) <= ((30'h162e !== 27'h1a0d) | 18'h5c9a))))) & (r182 - (( ( ~ ( (23'h70cb * (24'h246d > 2'h1)))) - (( ( & ( 26'h6e6c)) == 28'h21af) !== 8'h6f)) % (4'h4 >= r168)))))) != (( ( ~ ( r31)) && ( ( + ( r130)) / r96)) > 19'h1be5)) / ( ~ ( ( + ( ( ( ! ( (((r154 ? (r253 !== ( | ( (1'h0 % 22'h7fd4)))) : ((r133 > (29'h70f ? 6'h3a : 19'hff4)) === 26'h9dd)) <= r109) != 4'h2))) * ( & ( 4'h4))))))))))))); +\t\t#10; r70 = r113; +\t\t#10; r111 = ( ! ( ( ( ^ ( ( - ( ( | ( ( | ( ((r207 * ((((r224 !== (15'h2f78 < 32'h5844)) > (r246 === ( + ( ( ! ( r150)))))) >= r24) && 2'h1)) * r208))))))))) || ( ( ^ ( ((((r144 % r39) < ( - ( ((9'h103 + ( ( & ( ( ~ ( (r176 || (2'h1 ^ 3'h1)))))) ? $stime : r132)) ^ ( + ( (27'h3a07 ? ( ( ^ ( r12)) && ( ( & ( r164)) - ( + ( (2'h0 > 29'h1ec3))))) : r114))))))) && r126) && ((15'h4051 !== (r0 >= 27'h7733)) ^ (((22'h3da3 | ( ( & ( ( ^ ( r90)))) & 2'h1)) / 2'h1) === (r51 % r189)))))) !== (r252 == 4'h5))))); +\t\t#10; r162 = 6'h25; +\t\t#10; r183 = ( ( - ( (r110 ? ( ^ ( ( ( + ( ((26'h7b30 != 7'h4c) - r124))) * $time))) : ( + ( (r178 * r22)))))) ^ ((r155 && r52) < (r118 ^ ( ( | ( ( ( ! ( (24'h35fc ^ ((( ( & ( ((r53 - r49) >= 5'ha))) ? r251 : r162) <= 21'h5575) ? (r163 != (( ( ~ ( r203)) - r130) + r153)) : r97)))) == (((r154 | ( ! ( (r105 | r241)))) !== ((18'h6bbe + ( ^ ( (r193 !== ( ^ ( r26)))))) == 6'h1d)) - ((((((((11'h11f || 7'h25) ? r117 : (3'h4 > 19'h2c65)) + ((29'h1842 | 18'h1c77) + ( | ( 13'h19b)))) == $stime) != 11'h491) - 18'h69a8) & (((r206 ? ( - ( (30'hd83 ^ (30'h7ac6 | 2'h2)))) : (((10'h9d && 32'h5721) === $time) !== (r190 === (9'hd9 / 27'h2d)))) && (r232 || (r76 > ( + ( 25'hd8b))))) < $stime)) == r191))))) + $time)))); +\t\t#10; r30 = r66; +\t\t#10; r60 = (22'h3eec ^ (11'h1dd ^ 9'h113)); +\t\t#10; r229 = ( ~ ( 5'hc)); +\t\t#10; r180 = ( ^ ( ( & ( r127)))); +\t\t#10; r30 = r124; +\t\t#10; r149 = ( - ( (30'h743 === ((((((13'hc2 * (( ( & ( 30'h12da)) + 26'h7fc3) + ($stime ? ( ( ~ ( 27'h75f6)) | (r62 !== ( - ( 21'h3b14)))) : r238))) !== (r248 == 30'h7a43)) || 22'hfbe) * $stime) ? r240 : r4) >= (12'hd38 ^ (r147 + ((r36 - 23'h1ed1) ? ((r123 >= ( ( ~ ( (( ( + ( ( ~ ( (15'h32ce / 32'h6ae6))))) | 12'hf22) > $stime))) ? (((r200 == ($stime && r86)) >= (( ( & ( (1'h0 <= 22'h4156))) != 2'h3) === ((r118 && r106) * r249))) || 16'h629a) : (28'h6bec !== r65))) % ((21'h5864 * 2'h0) % $time)) : ((( ( & ( ( ~ ( ( ~ ( (((17'h19fd != 2'h1) > (23'h4f5d & 26'h14e6)) >= ( & ( r236))))))))) === ( ( ^ ( ((r146 && ( ( + ( 26'h40d8)) % (11'h5ba ? 16'h7254 : 32'h7877))) != 22'h3cba))) !== ( ( - ( ( ! ( r162)))) / 2'h3))) != ( ^ ( (r135 & ( ~ ( (((26'hc01 !== r252) || ((4'hd | 8'h62) > ( & ( 16'h4d14)))) == 18'h6094))))))) & (( ( ~ ( r147)) > r72) !== 13'h1f75))))))))); +\t\t#10; r173 = 5'h0; +\t\t#10; r103 = $time; +\t\t#10; r239 = $time; +\t\t#10; r23 = r22; +\t\t#10; r77 = ((13'h16b3 == ( & ( r9))) / ( - ( ($time && 5'h1c)))); +\t\t#10; r132 = ((r22 >= (r212 ^ (((($stime === ((r241 % (( ( | ( ($time % ((11'h4b7 && 2'h3) >= ( ! ( 32'h71f5)))))) - $stime) ? (r98 && 2'h3) : ( ^ ( (21'h384f === 27'h85))))) <= ( ! ( (20'h4d8 <= $time))))) !== (r147 == (r51 / r226))) | r15) / r114))) ? r208 : (( ( ~ ( ( + ( $stime)))) != r7) == ( ( - ( ( ! ( ( ( - ( ( ( & ( ((( ( ~ ( 22'h2cd1)) != (((14'h176d <= 29'h32ef) + (16'h23d1 != 2'h1)) * ((1'h0 ^ 14'hf5b) + r98))) || r212) === (r154 ? 5'h4 : ((((6'h18 !== 4'h7) / (27'h2c4d & 14'h1ea)) > ( | ( $time))) > (( ( + ( 22'h2996)) !== 32'h70cf) && (r135 - r79))))))) | (r98 / r221)))) + ( ^ ( (r198 !== (9'h10d === 7'h11))))))))) - ( ~ ( 30'h1aa4))))); +\t\t#10; r43 = (28'h3e31 != ( - ( ((r204 ? ( ~ ( r214)) : r7) && 16'h2745)))); +\t\t#10; r161 = ($stime % (( ( | ( (r185 % ( ^ ( r104))))) % ($time * (((r170 | 17'h229d) ? ((($stime >= (23'h16aa & (r64 != ((r100 & (r61 | $stime)) === r136)))) === 27'h349d) ? ((( ( & ( 4'h8)) ? ( + ( r122)) : ( ! ( ( ^ ( r70))))) > ( ~ ( r159))) + r79) : (7'h72 ^ (r55 / ( + ( ( | ( ( ^ ( ( ( ~ ( (23'h7fda + 10'h17))) * ( - ( r1)))))))))))) : ( ! ( ( ( - ( $stime)) % ( ~ ( 5'h2)))))) >= ( ( ^ ( r226)) * r107)))) <= 31'h78c1)); +\t\t#10; r132 = ((1'h0 === r227) != 24'h6058); +\t\t#10; r128 = 3'h1; +\t\t#10; r15 = 19'h5239; +\t\t#10; r17 = 15'ha01; +\t\t#10; r77 = ((r242 === r221) * (r179 !== r249)); +\t\t#10; r87 = (32'h57ec | r63); +\t\t#10; r116 = r136; +\t\t#10; r20 = r148; +\t\t#10; r53 = 30'h6650; +\t\t#10; r140 = r198; +\t\t#10; r246 = ($stime / ( ( | ( $stime)) / ( ( ! ( ( + ( r215)))) & 20'h3e0e))); +\t\t#10; r69 = r246; +\t\t#10; r172 = r163; +\t\t#10; r94 = r157; +\t\t#10; r107 = $stime; +\t\t#10; r74 = ( + ( ( - ( $time)))); +\t\t#10; r130 = r195; +\t\t#10; r197 = (29'ha48 > ((((r121 ^ r165) <= r124) & r226) ^ ((((((r79 * ( ( ~ ( (4'h7 != ( ~ ( r188))))) ^ r70)) & ( ( & ( ((r140 - ( ( ! ( ((32'h6c24 >= 7'h2d) == (2'h1 || 32'h1866)))) || 29'h16f1)) > (2'h1 || ( + ( ($stime == (r68 | 11'h34b)))))))) == r193)) !== r211) | r227) % (r16 == (r10 && (r229 / 4'hc)))) + (r242 ^ r117)))); +\t\t#10; r130 = (20'h23ae | 18'h14b8); +\t\t#10; r136 = 9'h20; +\t\t#10; r249 = 15'h1805; +\t\t#10; r224 = 1'h0; +\t\t#10; r47 = r200; +\t\t#10; r153 = 21'h2587; +\t\t#10; r137 = 29'h4926; +\t\t#10; r241 = ( | ( (r228 ? ((((27'h60f7 < ( ^ ( ( ( ^ ( ( - ( (r82 / 8'hb9))))) & ( ( ^ ( r124)) >= (r222 ^ (($stime ^ ( & ( ( ! ( 8'h30))))) * r146))))))) == r4) | ($time % (1'h0 / ( | ( (( ( | ( ( ^ ( ((( ( ^ ( 29'h3ca3)) / (8'h37 == 26'h3dbc)) + ((30'h160b >= 23'h7433) ^ r114)) >= (18'h2332 ? (20'h14e1 / (18'h1626 && 28'h64b1)) : r88)))))) < r219) ^ ( ( - ( ( & ( ( + ( ( ( ! ( (25'h7e80 | 5'h14))) > ( - ( (16'h12d2 || 9'h1c2)))))))))) ? $time : $stime))))))) !== r104) : ((((r252 || r121) | ((6'h37 == (((17'h697e === r43) + (18'h44f4 % 5'h1a)) ? r117 : r30)) < $stime)) + ((((r167 ? ( | ( (r87 + ( ! ( (19'h6a46 < r109)))))) : ( ! ( 16'hb75))) == 32'h4122) | r99) / (((15'h25b8 === ( ^ ( r158))) == ( ( ~ ( 23'h693a)) - ( | ( ( ^ ( r249)))))) / (r168 ? ( ( ^ ( r95)) - $time) : r204)))) * (r139 !== 24'h3813))))); +\t\t#10; r166 = ( ( - ( ((r111 === r215) && r112))) | ((((($stime != r97) / ((22'h6297 != (((20'h58b | (r76 ? $time : (r57 > (( ( - ( 22'h52e5)) - (14'h105e === 4'hc)) ^ ( & ( (28'h7a38 || 14'h3a92))))))) | (23'h2ee7 / (r70 + r159))) > 17'h862)) >= (24'h4bd6 > $stime))) < (((((22'h38cf * r181) - ( + ( (r36 == r49)))) !== 18'h15e4) & r185) ^ ( ^ ( 19'h2b9c)))) == ( & ( r150))) == ( & ( r137)))); +\t\t#10; r236 = ( ( + ( ((((((r148 || ( ( ~ ( ( - ( ( ~ ( r254)))))) != (6'h20 <= r133))) > 26'h163c) !== ( & ( (($time === r13) != 15'h637b)))) === 24'h7118) < ( + ( r42))) / r251))) ? (r43 % (6'h2 === ( + ( r209)))) : ($stime == ( + ( r82)))); +\t\t#10; r35 = 32'h194c; +\t\t#10; r242 = 12'h485; +\t\t#10; r163 = r152; +\t\t#10; r143 = (r53 >= ((r240 || 4'h8) / r146)); +\t\t#10; r32 = r221; +\t\t#10; r161 = (((((r79 || 17'h2a79) % $time) !== ($stime + (9'h164 > (r94 * 18'h8a0)))) | (((r104 ^ ((r190 > r53) + $time)) >= r217) > r32)) - r130); +\t\t#10; r10 = ( & ( ((( ( ! ( r18)) > r10""b""2) & ((7'h2c > $time) || (r33 < ( ! ( ($stime - (((18'h2403 && (((2'h3 <= 7'h46) & r199) + (r138 == ( ( + ( (25'h643f !== 6'h1))) + r82)))) ^ (( ( + ( ( ! ( ((21'h2864 && 4'h9) || (22'h1c12 == 9'he3)))))) || ( ( - ( ((31'h23bf ^ 11'h44f) !== (21'h2257 || 20'h3d63)))) !== (r128 < ( ! ( (21'h49bf + 25'h936)))))) !== ((($stime ^ ( + ( (7'h52 != 23'h5ce2)))) * ((26'h33f0 | 2'h3) % ( ( ~ ( 24'hafc)) !== r32))) != (r219 == 28'h20f3)))) != r20))))))) | 16'h3a6a))); +\t\t#10; r15 = (24'h31d2 != r30); +\t\t#10; r210 = (r97 | ((8'h4 || r34) ^ (r72 == 11'h724))); +\t\t#10; r214 = ((((( ( ~ ( ( ( & ( 23'h74ba)) > (r92 + (r77 + 4'h1))))) == r26) || ($time != ((12'heb1 < ( ^ ( ((17'h21be - ($stime >= ((r174 - r230) >= (((30'h1aa7 % 29'h622f) + ( ! ( 12'h297))) ^ (15'h4020 && r79))))) === r159)))) != $time))) * ((((13'h836 ^ ( ( | ( ((r120 && ( + ( ( + ( ((8'he + 30'h2a02) !== r44)))))) % 27'h4d2c))) | ( & ( (r238 | r214))))) !== (26'h327a != (4'h5 === ( ( ! ( ( & ( ( & ( (((13'h1896 & 22'h33) % ( + ( 29'h63e4))) + r148))))))) == $time)))) / r173) / ( - ( r12)))) / r109) && (23'h44f8 > ( ( ! ( $time)) + r205))); +\t\t#10; r182 = ( ( ~ ( 28'h4852)) === 11'h1d2); +\t\t#10; r11 = ( ^ ( ( ! ( (r142 && ( & ( ((r127 <= r51) - 32'h6ebd)))))))); +\t\t#10; r221 = 9'h20; +\t\t#10; r97 = ($time + (11'he8 != (( ( ! ( ($time ^ 2'h3))) % (((r175 - (31'h5de9 + 2'h2)) / r70) <= r189)) % ( ( | ( ((r1 || ( ( & ( (5'h11 >= ((7'h3c <= r198) > 16'h5796)))) | 28'h32a)) ^ ((r221 & (($time ^ ((((r220 % (20'h6874 + 4'h0)) !== r219) + 14'h1bd8) / 30'h7574)) + r251)) < (19'h11a4 > r61))))) === ( - ( (((r253 + 30'h72b5) < r68) && (((15'h6bf0 > r153) < $stime) !== 6'h20)))))))); +\t\t#10; r205 = (((24'h1906 != (( ( ~ ( ( | ( ( - ( $stime)))))) == r74) / 18'h6640)) === r94) + (((27'h1683 == (14'h13fa < ( & ( r72)))) > r48) * (((((r173 == (4'hd | ((13'ha23 && 1'h1) <= ( ! ( (9'h1ea ? ( ~ ( 16'h4ec3)) : ( ( ! ( ( ~ ( (27'h3b76 == 18'h6606))))) * ( ( - ( (23'h3f36 ^ 27'h1521))) % r231)))))))) & ( ( - ( 14'he7b)) <= ( | ( ( - ( 12'h1d)))))) + r168) <= r217) >= $stime))); +\t\t#10; r231 = (r213 | (((30'h7dd6 && r127) == (r109 | 29'h1794)) != r130)); +\t\t#10; r150 = ( - ( $stime)); +\t\t#10; r116 = (r139 > (( ( | ( r219)) <= (29'h25ec && ( ! ( 4'h9)))) / ( ( ~ ( r79)) > (r25 ^ 1'h1)))); +\t\t#10; r56 = 24'h6d7b; +\t\t#10; r214 = ( ! ( ( + ( r90)))); +\t\t#10; r207 = 19'h5602; +\t\t#10; r116 = ( ( + ( r130)) <= ( ( ^ ( 6'ha)) < r200)); +\t\t#10; r220 = (((15'h5ceb + 6'h25) === ( ~ ( 11'h1dd))) < r161); +\t\t#10; r10 = r63; +\t\t#10; r63 = $time; +\t\t#10; r214 = r201; +\t\t#10; r225 = $stime; +\t\t#10; r58 = r103; +\t\t#10; r78 = ( ( ! ( ( ! ( r28)))) <= ( ( & ( ( ~ ( ( - ( (r165 && r66))))))) >= ( ~ ( 6'hd)))); +\t\t#10; r243 = 1'h0; +\t\t#10; r25 = ((((21'h9f5 == ((((r24 >= r227) || ( ^ ( (r63 === ( & ( (r92 >= 21'hc2d))))))) < (32'h71e6 % r124)) - 25'h51f4)) && ( ~ ( 5'h17))) != ((r138 || (8'h91 === ( & ( (( ( | ( ( | ( r186)))) | r196) !== r186))))) && r103)) + 12'h5cf); +\t\t#10; r175 = (r171 * r99); +\t\t#10; r193 = ( ~ ( 29'h5007)); +\t\t#10; r141 = r64; +\t\t#10; r22 = (5'h11 + ( - ( ((26'h2b69 ^ $stime) <= (((r129 < (((( ( ! ( 7'h23)) + (4'h5 === (6'h35 >= 24'h20d7))) || (( ( & ( r226)) & (16'h6572 >= (r173 ^ 18'h2888))) - $stime)) ? $stime : 15'hb3d) * ( ! ( ( | ( r3)))))) < (( ( & ( ((( ( - ( ( ( ~ ( r109)) % ( ^ ( ( + ( 2'h3))))))) >= ($stime < r136)) ? 7'h5b : ( & ( ( & ( (((18'h71e * 8'haa) <= (22'h651b - 26'h499e)) | r83)))))) === r134))) == (((20'h65de & (r227 % 7'h63)) > ( + ( r213))) >= ((9'h18b == 16'h7f14) && ((( ( | ( r78)) < ( ( ~ ( (27'h3ae8 + 31'h566b))) + ($stime >= (16'h55d9 % 17'h7bb4)))) < 28'h3f8b) <= ((r132 != (( ( ^ ( 29'h5761)) ? (6'h5 != 3'h5) : r21) !== r23)) === (2'h0 === r235)))))) == (r49 && ( ! ( 9'h11a))))) < r188))))); +\t\t#10; r49 = ( ^ ( (((((25'h4e96 === r46) && r73) > ( ^ ( ( | ( ( ( | ( 10'h1b2)) & ((r159 - ( ( & ( r109)) / $time)) >= 14'h1323))))))) - r165) % (r28 > r247)))); +\t\t#10; r4 = 30'h3703; +\t\t#10; r165 = r95; +\t\t#10; r39 = ( + ( (r224 == r178))); +\t\t#10; r248 = $stime; +\t\t#10; r209 = ((12'h657 | ($stime ^ ( ^ ( (r198 != ((22'h1825 + r140) === 26'h5d53)))))) == ( ~ ( (( ( & ( ((r21 % (($time | ( ( ! ( (r6 == (((21'h2c09 == 3'h5) == (4'h7 ? 18'h3c25 : 25'h3224)) !== (r13 !== (16'h68df <= 20'haf4)))))) % 9'hc5)) >= $time)) ? 8'hef : (r247 & (r180 ^ ((((16'h31e9 - ($stime & 10'h1bc)) && (18'h7f94 | ($time ? r16 : ((5'hb ? 29'h7896 : 19'h5aba) ^ (19'h52e0 === 1'h0))))) == (((24'h201f !== ( | ( ( ! ( 5'h1f))))) || ( ~ ( ( ~ ( r100))))) / ((r60 ? (r99 || (9'h6 ? 10'h2fe : 27'h72e7)) : (r234 <= (11'h74b % 30'h6ba6))) > ( & ( ((29'h4113 !== 29'h4226) && (5'h1e > 15'h3bb0))))))) != ( ( + ( ((1'h1 - 1'h1) >= (r31 * ($time ? 22'h7283 : (10'h25c == 1'h0)))))) & (r57 === (9'h1e9 < r56))))))))) >= 7'h17) != r163)))); +\t\t#10; r1 = (r78 % r79); +\t\t#10; r101 = ( ( ! ( (((r143 - 30'h78e0) / (14'h1c2e - (((( ( ~ ( 27'h5102)) !== 23'h5656) * ( + ( (r127 >= (((((31'h4150 == 9'h7f) ? (21'h40b0 >= 1'h1) : 20'h7e04) >= ( | ( 31'h6fed))) ? ( ( + ( r11)) && (15'h1543 && (8'h45 < 24'h382b))) : r189) > (r201 <= r171)))))) && ($stime > r42)) && ( & ( 14'h39ec))))) == r110))) === ((($time / ( - ( ( ! ( ( + ( 1'h1))))))) & r199) !== 12'h112)); +\t\t#10; r111 = $time; +\t\t#10; r58 = r34; +\t\t#10; r1 = (21'h4628 & (r206 >= r167)); +\t\t#10; r130 = (( ( ^ ( r212)) + r148) !== ((r51 !== ( + ( ( ~ ( ((8'h68 == $stime) > ( & ( $time)))))))) || 6'h0)); +\t\t#10; r12 = (( ( & ( ( ( - ( (((r233 && (r155 || r64)) > (r224 != ((19'h1e80 * (24'h7122 & ( ( ! ( r79)) | (r81 >= r68)))) != 11'h3de))) ? ((r139 > (21'h58b4 < (($time - ($time | 1'h0)) === (((14'hf05 | 9'h90) ? (r180 - ( - ( ( ~ ( 4'h3))))) : ( - ( 12'h8e9))) >= ((9'h195 > ((13'h19a8 < 23'h5a73) && 7'h21)) && $stime))))) ^ r46) : ((r171 !== ((((9'h120 != (2'h0 % ( + ( r237)))) & ( ! ( 3'h6))) || (( ( & ( (31'h7 || 23'h777a))) !== ( - ( (r102 + (1'h0 + 26'h4b6a))))) & $time)) * r78)) !== ( ^ ( $stime)))))) != 13'haee))) ? r59 : (29'h3976 / r181)) % r221); +\t\t#10; r246 = r187; +\t\t#10; r122 = 32'h7516; +\t\t#10; r63 = r192; +\t\t#10; r68 = 21'h5966; +\t\t#10; r221 = (( ( - ( (r154 === 2'h3))) && ( ( ~ ( ( - ( $stime)))) > $stime)) ^ ((27'h464f <= r132) < 24'h4012)); +\t\t#10; r179 = r107; +\t\t#10; r15 = 26'h1958; +\t\t#10; r27 = (r197 != r242); +\t\t#10; r251 = (2'h1 <= 7'h69); +\t\t#10; r252 = (r50 <= r231); +\t\t#10; r228 = r192; +\t\t#10; r181 = r218; +\t\t#10; r129 = ((r187 & (($time || (r85 > ( ~ ( r13)))) > 32'h2b02)) | ($stime !== ( ( ^ ( r164)) + ( ^ ( ( & ( ((((((( ( - ( 9'h133)) - r240) && 10'h1e0) <= 12'h481) >= ( ( ~ ( (r78 !== (r132 | r63)))) % ( + ( ( - ( ((r159 & ( & ( 29'h376e))) >= ((1'h1 || 30'h4e92) && (19'h1691 & 26'h2629))))))))) * (r200 == ((r202 > (((r83 % (14'h2086 == 12'h1ca)) > ( & ( r246))) <= (((6'h7 + 23'h27fb) ? (1'h0 !== 15'h3dbc) : $time) - (r117 <= (9'hcb != 19'h31ef))))) ? 2'h0 : ( ( - ( 8'hb7)) || r65)))) ? ((r92 != ( ( - ( ( ( ! ( 25'hc76)) && 17'h27e3))) >= ($time == (r196 ? (((19'h842 != 17'h44a4) && ( ^ ( 3'h3))) / r124) : 1'h1)))) * ( ^ ( r17))) : (10'h300 <= (($time | (r161 !== $time)) - r55))) & ( + ( ( + ( $time)))))))))))); +\t\t#10; r69 = (( ( ! ( r209)) != 27'h73e0) / 30'h5ff5); +\t\t#10; r36 = ( ^ ( (($stime % 22'h7f73) / ( ! ( (r60 / r187)))))); +\t\t#10; r195 = r61; +\t\t#10; r148 = ( ! ( ((r1 != r174) & r111))); +\t\t#10; r61 = r232; +\t\t#10; r86 = (11'h627 / (( ( | ( r110)) < ( ^ ( 25'he53))) > (((( ( & ( (20'h1ed3 - 4'h9))) < ( ^ ( ( & ( 15'h48a3))))) | ((r73 % r163) && (((($stime !== ((r195 || ((18'h61d8 | (2'h2 + 32'h6491)) ? ((9'h1bd & 21'hdab) * (16'h597b == 5'h15)) : 27'h1e00)) & r87)) ? ((16'h6477 | r71) > ( ( ! ( 17'h49a5)) == r179)) : (( ( - ( ( ( ! ( ( & ( 26'h2396)))) + (19'h3d37 & (30'h1edf === 18'h2788))))) && (((r165 != 14'h13b0) ? r203 : $time) >= (r242 + r68))) <= r147)) ? ( ~ ( $time)) : (r189 + r151)) >= 8'h98))) === 25'h4203) ? $time : ((29'h133a ^ ( - ( (r137 !== 6'h1d)))) || ((( ( + ( r50)) || ((r216 === 32'h7fe7) >= (9'h13d >= r229))) && ( + ( 19'h2336))) & r246))))); +\t\t#10; r19 = (r85 | (24'h5e3d ^ ( ^ ( (r246 == (18'h6068 & ( & ( r152)))))))); +\t\t#10; r4 = ( + ( $time)); +\t\t#10; r152 = ((( ( - ( r140)) | ((1'h0 ? (1'h1 && r199) : (( ( + ( r212)) == r72) * ((r4 !== 5'h3) > (($stime >= 31'h742c) <= (13'h131c < r213))))) > (r246 || ((r116 < (((r189 < ( & ( ($stime === ( ( ^ ( r100)) | r189))))) !== ((r96 | ( ( ^ ( (r40 & r20))) * r167)) - (((r219 || 5'ha) === r185) != 20'h34fd))) | 17'h2d95)) + (( ( + ( (r114 % 25'hab5))) <= (( ( | ( r206)) || ( & ( ((18'h2670 & ( + ( ( & ( 14'h24d9))))) ? (14'h3df < (r253 | 19'h514e)) : (r5 * ((29'h88e != 15'h202c) <= (25'h7dd4 || 21'h4915))))))) === 7'h7d)) === 32'h2450))))) / r139) >= ( ^ ( ( ( ^ ( ( | ( 31'hc9a)))) >= 27'h5ce1)))); +\t\t#10; r83 = r149; +\t\t#10; r106 = (((r142 + (18'hff6 - r189)) ? ( & ( (r109 && 30'hb4f))) : ( - ( ( | ( ( | ( r115))))))) <= r180); +\t\t#10; r227 = ( ! ( ( ! ( ($stime / ((r194 * 26'h6311) === ((r105 % r76) != ((r79 != (1'h0 || (((2'h3 >= ( ^ ( 4'h4))) - 23'h5b50) > r48))) ^ 27'h702)))))))); +\t\t#10; r38 = r32; +\t\t#10; r177 = (r151 ^ ( & ( r53))); +\t\t#10; r132 = r245; +\t\t#10; r135 = ( + ( (r141 - ((r169 != r178) !== ( | ( (r241 != ( & ( ((r102 & ( ~ ( ( ! ( r18))))) ^ r25)))))))))); +\t\t#10; r121 = ( | ( 18'h61eb)); +\t\t#10; r253 = (((r123 >= 13'h18f9) & 26'h1e42) === ( + ( (r185 < r245)))); +\t\t#10; r58 = r52; +\t\t#10; r1 = (( ( - ( 21'h3df1)) === r43) && r195); +\t\t#10; r180 = ( ( | ( ( + ( 23'h51f6)))) | $time); +\t\t#10; r147 = r50; +\t\t#10; r212 = (r48 / ( | ( ( ( - ( ( & ( (r78 & r199))))) ^ (((r190 != ( & ( (r11 * (( ( - ( (($stime <= ((5'hd ? 11'h55e : 21'h7496) === (6'h23 % 15'h406b))) || r52))) / $time) > 18'h68f1))))) - ((($stime == r49) & r191) > (( ( ^ ( (13'h11e6 - 2'h0))) === (((8'h77 > ((( ( & ( 18'h6c31)) + r247) + (r154 < ( ! ( 15'h2dda)))) >= ( ( - ( $time)) ^ ((4'h0 * 19'h3e9c) | r11)))) != (r70 != ((((18'h2d84 != 2'h3) != r202) / ((29'hf27 !== 29'h5512) + r43)) !== (18'h1db < ( & ( r221)))))) / r255)) || ( + ( (r32 + (r106 - r168))))))) || $time))))); +\t\t#10; r140 = (r210 - ((((r91 >= 25'h6118) & r15) >= $time) - (((((23'h4c9c ? r228 : ( ( + ( 27'h4433)) == (r117 == ((($stime | (($stime | ( & ( 23'h52a9))) === (r138 || r157))) === r106) * (r190 != $stime))))) | ( + ( r200))) - 28'h7a48) === 12'h1be) / ((r45 - ($stime + 4'h2)) != (( ( + ( (27'h7bf7 | (((27'h1e92 % 5'h17) ? 17'h4f68 : r240) >= ( + ( ( ( & ( ( - ( ((27'h6ca1 | 4'h5) ? (1'h0 ? 15'h551a : 19'h3554) : (2'h1 ^ 24'h62bd)))))) > ( ~ ( r248))))))))) ^ r123) * r183))))); +\t\t#10; r116 = ((($time * (7'hd !== $stime)) >= 12'h528) + 2'h2); +\t\t#10; r16 = r182; +\t\t#10; r188 = ( - ( 15'haa4)); +\t\t#10; r235 = ($stime ? ( ~ ( (30'h4340 > $stime))) : r134); +\t\t#10; r206 = (21'h355e && 16'h3c42); +\t\t#10; r32 = ( - ( (22'h3162 < ((r236 === 17'h4e9f) != ( ~ ( r231)))))); +\t\t#10; r2 = 4'h4; +\t\t#10; r227 = ( - ( ( ~ ( r70)))); +\t\t#10; r123 = r227; +\t\t#10; r52 = 11'h62c; +\t\t#10; r187 = ( & ( (28'h554a !== r129))); +\t\t#10; r15 = ( ! ( ( - ( ((14'h23b | ((24'h5d96 < ( ( ^ ( r81)) % ((26'h13a2 - (((10'h2d4 <= (((7'h1d < 23'h784b) <= 2'h0) <= r41)) % ( ( - ( r76)) >= (7'h54 || ((20'h667a * 7'h4a) != (16'h3c25 | 18'h732))))) ? (r125 ? ( ( ^ ( (r6 == (32'h1414 + 30'h61ef)))) & (r75 != 27'h17c1)) : (r157 - ($stime / ( ( ^ ( 1'h1)) ? ( ! ( 22'h5660)) : r112)))) : (r244 & ((1'h0 >= r112) === ((r203 >= r3) + ( ( | ( 12'h2a8)) < (30'h838 + 17'hb72))))))) - r84))) | ( ( ^ ( ((23'h151 / ( ( ~ ( ( ( ^ ( ((6'h29 - 11'h624) % $stime))) + ( ! ( ((32'h5711 ? 3'h6 : 28'h4941) % (19'haad === 12'h299))))))) + 14'h340c)) ^ 12'he4f))) !== r64))) | (( ( | ( ( ( ! ( ( ( & ( ( ( | ( ( | ( 9'h1a2)))) / ( ^ ( (11'h15b ? (r141 == $time) : ( | ( r242)))))))) == (24'h338 == r170)))) !== 20'h28f8))) <= (((r75 >= ( ~ ( ((( ( & ( 16'h5800)) && ( ~ ( r186))) & ((r215 / r60) <= (((32'h1ce6 | 15'h3e47) <= (1'h0 <= 29'h3f9c)) !== ((23'h5d5d <= 23'ha77) | (9'h20 < 22'h43a4))))) % ((9'h39 + r179) || r82))))) - ( ~ ( r243))) > $stime)) ? ((r105 > (r217 + 27'h2e68)) ? r223 : r81) : r31)))))); +\t\t#10; r228 = r194; +\t\t#10; r187 = 7'h29; +\t\t#10; r109 = ( ( ^ ( ((13'h1f6 >= r210) + r112))) > r235); +\t\t#10; r121 = 13'h5bb; +\t\t#10; r213 = ((r30 * 18'h2845) === ( ! ( r237))); +\t\t#10; r180 = ((r241 | (((r106 - (( ( + ( ( ~ ( ( + ( 28'he39)))))) !== ( - ( (($stime | ($stime != (((r139 % r97) !== r94) >= r251))) ^ r45)))) | r97)) === (r79 < ((r109 * 2'h0) !== ( & ( 27'h3293))))) / (((r238 + 15'h60cb) == ((( ( + ( ( | ( r65)))) <= ( & ( 29'h7fa4))) > (($stime | (((r24 < ( - ( 10'h116))) % ((($stime >= (14'h2dac | 4'h2)) / (5'h1 && (11'h68e != 12'hfd))) | r57)) - r252)) ? 30'h2533 : r239)) < r117)) === r175))) % 25'h5022); +\t\t#10; r7 = (( ( | ( (15'h7910 && ( & ( (r66 <= r105)))))) < (29'h6770 % ( ^ ( r24)))) + (r27 - (($time * (( ( ~ ( ( ( & ( r72)) || ( ~ ( ((16'h613e ? (6'h18 + r105) : ((r58 ^ ( ( - ( 1'h0)) > (15'hd9d | 12'h8d8))) > ($time === r11))) + ((r60 + r170) >= (30'h109b ^ ( - ( ( + ( (19'h3346 ? 12'hf5 : 21'h2119))))))))))))) < 5'hf) - $time)) !== ( ~ ( ((r246 >= (((r90 - 14'h34ad) != ( | ( 25'h6134))) && ( ( ! ( ( ( | ( ( | ( (r152 | r232))))) | ( ~ ( (r196 || r35)))))) || ( - ( ( & ( ((r73 >= ( & ( $time))) || ( - ( (23'h1d25 !== ( + ( (20'h672d === 24'h194b)))))))))))))) == ( ( & ( r34)) !== (r30 / ( & ( (( ( ^ ( 17'h6d41)) ? ( + ( ( ~ ( (11'h77f || ((1'h0 - 31'h185d) == (28'h1b96 ^ 15'h2a2a))))))) : $stime) != ((19'h7835 == ( ! ( 32'h4eb6))) || ( ! ( (( ( ^ ( $time)) ^ ( + ( (16'h1f16 + 22'h17f)))) == r118))))))))))))))); +\t\t#10; r21 = 24'h1fe8; +\t\t#10; r145 = (( ( - ( 17'h64a4)) !== ((r131 > (r109 | ( ( ~ ( 14'hd50)) + (r228 !== (( ( ~ ( ((29'hc3f - (( ( | ( 27'h6286)) <= 18'h6b93) === 31'h2432)) && ($stime || ( ( | ( 23'h35a)) <= 32'h496))))) && r113) == r175))))) <= r252)) && r171); +\t\t#10; r210 = ( - ( (r171 != (r235 > r32)))); +\t\t#10; r212 = ( & ( ( ~ ( ((r90 != r45) & 11'h491))))); +\t\t#10; r158 = ( - ( 14'h3cb)); +\t\t#10; r152 = (r137 == ( & ( ( + ( ( ~ ( 18'h3802))))))); +\t\t#10; r152 = r114; +\t\t#10; r28 = (r72 % r210); +\t\t#10; r69 = ( & ( ( ( - ( ( ~ ( (( ( ^ ( (((((22'h7b4e < ( ( & ( (7'hb > 31'h50d8))) ^ (4'hb / (17'h3b5d == 7'hf)))) & r220) % (8'h4e < ( ! ( 18'h2d17)))) - r130) * (16'h4fd5 * ((( ( ^ ( 24'h716d)) && ( ! ( r221))) >= $stime) == (31'h4a6f > ((r24 & ( ( ^ ( 30'h309)) <= (29'h475 == 28'h2d97))) >= ( & ( ((30'h151f <= 22'h6762) * 17'h646b)))))))))) - ( ( | ( r45)) * r211)) == ((r114 / $stime) === (21'h2915 != ( ~ ( ( ! ( $time))))))))))) == ((r197 || 27'h73e0) <= 14'h3d7)))); +\t\t#10; r60 = (( ( | ( r187)) == ( ( - ( r55)) + (((11'h335 > (r232 != r5)) == (r89 ? ( ( | ( $time)) !== r6) : ((22'h6cc5 && (9'h161 <= $stime)) <= $stime))) <= r123))) / (((( ( ~ ( $stime)) >= ( | ( r221))) < ( - ( r115))) !== ( ( ! ( (( ( ^ ( (( ( & ( r95)) + (13'h49d < ( | ( 18'h1a82)))) !== ((r78 != (r34 >= ( ( ! ( (14'h588 | 16'h507))) && (1'h1 > 12'hbfd)))) && (r91 + r249))))) !== ( ^ ( ( ( | ( r205)) == r71)))) == 15'h113d))) === 32'h60ad)) / ( + ( ( - ( 15'h7b84)))))); +\t\t#10; r213 = ( ( + ( 3'h0)) / (8'hc6 < r26)); +\t\t#10; r27 = 19'h54d6; +\t\t#10; r235 = (10'h2ce || (14'h18b5 * ((($stime & ( ( ~ ( ( ^ ( (((((r39 ? ($stime % 7'h68) : ( ( ^ ( 7'h38)) || (14'h99b % 24'h613f))) != (r116 < r163)) | r154) ? ( - ( 22'h2d1e)) : 12'hf49) - ((((((19'hee0 + 25'h4274) === r189) + 21'h1c66) * 25'h2b72) && ( ~ ( (( ( ~ ( 18'h4339)) & 6'h3e) % ( + ( (10'h218 | 19'h4ea1))))))) == ( ( - ( r117)) | ( ( | ( r118)) | (r63 !== ( + ( ( ~ ( 27'h3763))))))))))))) < r82)) & r142) == ( + ( (23'h74ab && ( ~ ( r108)))))))); +\t\t#10; r3 = 24'h3a7b; +\t\t#10; r60 = ( ( ! ( 22'h5ca)) | ( ! ( (r38 / (r0 ^ ((30'h7151 ^ ( ( + ( 1'h0)) ^ (4'hc || (r49 > (14'h1287 % ( | ( (3'h2 !== (((26'h1516 != 4'ha) + 19'h7343) < (r225 * ( & ( 27'h380d)))))))))))) < r55)))))); +\t\t#10; r209 = $stime; +\t\t#10; r88 = 30'h47b0; +\t\t#10; r190 = ( ( - ( r25)) != (r230 % r145)); +\t\t#10; r242 = (((r31 ^ r98) ^ (( ( | ( r110)) < ((( ( - ( ((( ( | ( (r147 != r193))) | 15'h2197) && ( ~ ( ((((9'h1b / 3'h6) - (16'h66b5 !== 13'h15aa)) <= (r188 || (24'h1e3f >= 30'h41da))) <= (r181 / ((11'h317 - 30'h7563) <= (32'h1a3a && 8'h20))))))) * $stime))) ? ( & ( ( & ( 21'h5bc5)))) : (3'h2 - 10'h332)) % r29) <= r182)) == r131)) ^ (24'h3d27 && (28'h3b13 !== 20'h1322))); +\t\t#10; r227 = 23'h11c3; +\t\t#10; r242 = ((21'h5910 == (19'h6d6f - ( ! ( ( | ( r100)))))) <= ( + ( (r208 - ( ( ^ ( ( & ( ( ~ ( r170)))))) / (((r216 && r115) != (r68 ? (1'h1 * r149) : 2'h3)) && r233)))))); +\t\t#10; r178 = r186; +\t\t#10; r44 = ( ( - ( r213)) && ((r59 % r72) / r65)); +\t\t#10; r26 = ( - ( r97)); +\t\t#10; r120 = $time; +\t\t#10; r251 = r73; +\t\t#10; r78 = 25'h4661; +\t\t#10; r105 = ((27'h3d8e | r115) || 19'h65b7); +\t\t#10; r212 = (11'h727 > r67); +\t\t#10; r198 = r128; +\t\t#10; r59 = ( + ( r140)); +\t\t#10; r125 = 19'h6ff4; +\t\t#10; r99 = ( ( + ( r41)) === 30'h295e); +\t\t#10; r197 = r17; +\t\t#10; r5 = (r172 === r139); +\t\t#10; r252 = (((17'h64d7 ^ 4'hd) + ( ( | ( ((13'h19cb && r127) % ( + ( (25'h69d4 >= ( + ( 17'h956)))))))) > (((( ( ~ ( 18'h5835)) | ((((r63 | 22'h33eb) < 19'h7c40) | 22'h1c7e) % ( ( - ( (r77 >= ($stime ? 21'h1762 : (((4'ha > 14'h2fb0) < 16'h2d72) | ( - ( ( ! ( 32'h2f02))))))))) + ( + ( ( ( ~ ( (r60 ? $time : r244))) >= 28'h67c5)))))) <= (r106 & 32'h28a6)) != r242) / 6'h39))) == ( & ( 9'h1e2))); +\t\t#10; r58 = r119; +\t\t#10; r102 = 17'h597e; +\t\t#10; r148 = r206; +\t\t#10; r22 = (r194 ^ ( | ( 26'h249c))); +\t\t#10; r133 = (((r34 | (20'h12d2 === r166)) != ($stime !== ( ^ ( (($time == r53) == ( - ( 4'h6))))))) !== ( ~ ( 5'h13))); +\t\t#10; r182 = r102; +\t\t#10; r165 = ((r60 / r30) % r33); +\t\t#10; r20 = ( ( + ( r17)) != r90); +\t\t#10; r102 = (((r105 - (20'h3e12 < 24'h5669)) > (((21'h12ed != ( ( | ( (r82 > ( ( ! ( ( & ( (r187 < ( + ( ((12'haa1 === 4'h8) + (32'h2954 % 11'h3be))))))))) + (21'h74de * 3'h4))))) - ( ~ ( 16'h6332)))) / ((r178 || ( - ( 30'h6f10))) | 31'h5072)) ? ( ( ~ ( (( ( ~ ( (r197 >= $time))) >= r254) > (r51 ^ 5'h5)))) !== ((((r82 > ((r40 != (r68 < ((((23'ha77 * 20'h39dc) * (31'h87c / 16'h5e84)) | (32'h666b % (13'haac >= 31'h757c))) === 6'h5))) || (r254 <= ((((7'h3c / r179) + r196) != r61) !== ((11'h27e - r0) <= (($stime >= r0) / 15'h2676)))))) !== r49) * ( - ( ((r106 && ( ~ ( 23'h50ed))) >= (11'h77e < ( ^ ( ( ~ ( 2'h1))))))))) !== $time)) : ((r242 >= ($time !== (r169 > (18'h129 == 32'h4fe8)))) < ( & ( (((32'h925 || r56) ? r180 : 18'h5ecc) === (( ( - ( 14'h23fa)) & (r203 == ( | ( (17'h78cf <= ( - ( (r223 | ((1'h1 < 14'h251f) ? 5'h1c : (28'h52ce >= 27'h1c52)))))))))) - r233))))))) <= (( ( ~ ( ( ^ ( ($stime / r49))))) + r27) !== $time)); +\t\t#10; r21 = ((r8 ? 2'h1 : (( ( ~ ( (r82 + $time))) < r44) | r98)) / r188); +\t\t#10; r4 = r126; +\t\t#10; r91 = 11'h2c3; +\t\t#10; r113 = 18'h3ed2; +\t\t#10; r47 = r29; +\t\t#10; r128 = ( ( | ( 9'h35)) ^ 27'h35ad); +\t\t#10; r120 = r110; +\t\t#10; r54 = ((r68 !== ( ! ( r28))) == (25'h571a & ( ( - ( ((r161 & 23'h6f59) !== ((r150 || 18'h6a2f) | 5'h19)))) || ( ~ ( ( ~ ( ( ( ~ ( $stime)) ^ r68)))))))); +\t\t#10; r246 = ((23'h18f0 ^ r230) + ((((18'h4781 ^ r148) > (((r247 - 2'h3) == $stime) >= ((((r170 || (r209 !== ((6'h18 % r248) === r170))) > r2) || ((((4'h5 + ((( ( + ( 4'h9)) & (31'h206f <= 32'h74e0)) <= ($time / (12'ha4e !== 12'h1b8))) > $stime)) === ($time > (((r98 <= r156) | r171) || ( - ( ((2'h0 > 29'h52a5) - r155)))))) & (r80 ^ $stime)) == r118)) == ((r122 % ( ( ^ ( 9'h61)) === ( ^ ( ( & ( r57)))))) ^ ((((r168 || ((r149 > (r65 - ( | ( 16'h3096)))) >= $stime)) < ( | ( (20'h30d5 - r250)))) != (((( ( | ( 8'h72)) ^ r193) < ( & ( (17'h13cf ^ (18'h57e0 <= 5'h1d))))) * r163) * (9'h1ff === ($time | 29'h1f07)))) > ($stime || ( | ( ( ^ ( ($stime > (r182 >= $time)))))))))))) === ((32'h7235 + ( + ( r63))) != (25'h5617 !== r193))) > (26'h3b84 <= r37))); +\t\t#10; r61 = ((( ( + ( ( - ( ( | ( (9'h123 < ((((r131 == $stime) !== r221) ^ $time) >= (26'h7d2b && (16'h4c88 === 28'h630e)))))))))) / (29'h2ad5 <= ( + ( ((r198 * ((r25 * (r33 + 4'h9)) <= r172)) != ((r173 >= 27'h16a3) < (r24 != 10'h27d))))))) & ($time / ($stime && ( + ( (23'h2212 ? (r86 <= ( ^ ( (10'h2f2 > (r126 / 30'hc28))))) : (r16 | ( - ( ( + ( (r0 <= (((14'h3e2f <= r129) < r115) !== ( - ( r156))))))))))))))) || 20'h118); +\t\t#10; r132 = ( ^ ( r44)); +\t\t#10; r100 = (r14 == ( | ( ((r236 != r163) & $stime)))); +\t\t#10; r46 = (30'hc90 - r136); +\t\t#10; r99 = (r38 + (r75 && ( ^ ( 1'h1)))); +\t\t#10; r110 = ((5'h1c + 12'hd0d) ? (( ( ! ( r29)) | ( ~ ( (5'h4 < (8'h1a != 9'h11))))) == r103) : ( & ( ((((r69 & ( & ( ( & ( r222))))) % ((6'h39 < ( + ( 10'hd3))) === r11)) ? (r252 === 6'h25) : ( ^ ( (( ( ! ( 20'h774a)) | 30'h2641) | ( | ( (((5'h4 !== r29) == ((r204 ^ r33) || 14'h465)) > (r161 <= r169)))))))) >= r231)))); +\t\t#10; r227 = (r186 ^ (($stime / ( - ( ((((30'h5a52 != (( ( ! ( 8'h49)) === (r202 | 8'h31)) == r148)) <= ( - ( (11'h388 & 11'h6fb)))) === r104) < r226)))) + 1'h1)); +\t\t#10; r62 = 19'h4ab; +\t\t#10; r231 = r234; +\t\t#10; r111 = (r230 * $time); +\t\t#10; r25 = $time; +\t\t#10; r186 = ( ( ! ( ( | ( $time)))) ^ r243); +\t\t#10; r235 = r235; +\t\t#10; r38 = ( & ( (( ( ! ( ( ! ( 15'h298c)))) / (((r103 % (5'ha >= r102)) ^ 16'h6162) / 24'h2416)) < ( ( - ( r135)) && ( & ( r148)))))); +\t\t#10; r49 = ((( ( ~ ( $time)) < (r116 % 23'h2cb1)) > (20'h4454 ? ( | ( (21'h198e | $stime))) : r116)) ^ (r55 ? r252 : ( ! ( (r154 ? ( ^ ( 16'h6adc)) : (23'h284 > (( ( - ( ( - ( 27'h2f79)))) <= r130) <= (( ( | ( ( ~ ( $stime)))) !== ((r25 ^ r1) === r199)) !== ($stime > ( ( & ( 23'h2b4)) < (r247 || 10'h190))))))))))); +\t\t#10; r169 = (((r12 | r195) > $stime) * ( ( + ( ( - ( (r20 >= (13'h508 === 18'h11fc)))))) || ( ! ( 18'h2923)))); +\t\t#10; r199 = $time; +\t\t#10; r224 = ( ~ ( ((23'h4d5 & r216) && r228))); +\t\t#10; r46 = 23'h79a5; +\t\t#10; r94 = 6'h1e; +\t\t#10; r46 = r181; +\t\t#10; r103 = (( ( ~ ( (((8'he6 - r129) < ((r204 + (10'h139 % r112)) < r75)) | ((r96 >= 25'h4652) != (r216 * r46))))) > ( ! ( ((20'h7cc1 < 19'h1460) || r74)))) & r190); +\t\t#10; r61 = ( ( & ( (r33 < (r53 <= r38)))) !== r135); +\t\t#10; r12 = ( + ( (( ( ! ( $stime)) || 3'h7) + (( ( ~ ( (3'h4 + ((r189 ? (30'hc61 > ( - ( (7'h21 ? ((((29'h5467 | 3'h2) || (31'h2f57 >= 11'h760)) ^ ((4'h0 & 16'h5c22) * 7'h39)) === ( + ( $time))) : (21'h546f > (1'h1 | ( ( - ( 4'h5)) * ( - ( 26'h144))))))))) : ( ! ( r186))) === r251)))) + r49) | r241)))); +\t\t#10; r173 = ( - ( r247)); +\t\t#10; r65 = $time; +\t\t#10; r57 = 10'h120; +\t\t#10; r230 = ( ( ~ ( (r203 * r115))) ? r16 : ( ~ ( ( ^ ( r204))))); +\t\t#10; r201 = (r58 <= r7); +\t\t#10; r63 = r217; +\t\t#10; r93 = (17'h70ab - ( ( ~ ( 5'hd)) ^ (( ( ~ ( ((( ( & ( ((17'h63e4 % ((((19'h70fc * 10'h1fa) === 23'h5ba5) - 25'h830) ^ r254)) - 1'h0))) != ( ^ ( (((( ( - ( r27)) & r177) % r226) / 8'h24) * r209)))) | 30'h1439) != 22'h7b4b))) / (r51 + r174)) <= ( + ( r65))))); +\t\t#10; r243 = 8'heb; +\t\t#10; r97 = ( ( & ( ((r126 % 15'h4856) < ( + ( r14))))) !== r25); +\t\t#10; r233 = 18'h5ffb; +\t\t#10; r157 = (r172 >= 29'h2fdf); +\t\t#10; r22 = ( | ( 5'hd)); +\t\t#10; r231 = r89; +\t\t#10; r144 = 26'hd4f; +\t\t#10; r83 = $stime; +\t\t#10; r108 = 12'hbe2; +\t\t#10; r45 = (r215 === (( ( + ( 30'h2e06)) <= r205) == (( ( | ( r142)) !== 13'h1108) == ( ( - ( ( ^ ( r253)))) == 31'h19c2)))); +\t\t#10; r22 = r8""b'4; +\t\t#10; r251 = ((( ( & ( ( ! ( r75)))) <= r183) * r79) < ((1\'h0 !== 29\'h11fc) !== r124)); +\t\t#10; r216 = (r168 && ( + ( r70))); +\t\t#10; r104 = (28\'h322b ? $time : (r71 - ((r27 ? ( ( ! ( 18\'h42a9)) < ($time === (12\'hfca * (13\'haae <= ( ( + ( ( - ( r86)))) + ( ( ^ ( 3\'h3)) == r20)))))) : r86) | ((((22\'h689 + ((11\'h164 ? r93 : (31\'h5fb0 / ( ~ ( ((((13\'h228 === 30\'h1aac) && (32\'h6fa6 / 13\'hce9)) - ((2\'h0 & 14\'h32e3) < (5\'h5 > 9\'h1f4))) && 14\'h2bcb))))) % (17\'h2ebf ? 2\'h3 : ( & ( r237))))) <= ((r84 * ( ( | ( r121)) || r158)) * r54)) / ( ! ( r74))) != r209)))); +\t\t#10; r195 = (r229 ^ (r139 - ( ( ! ( ( - ( r80)))) !== ((10\'h17b >= (r243 > (r164 != 2\'h1))) < 5\'hd)))); +\t\t#10; r234 = (r252 ^ (((r76 | r123) / r202) && r219)); +\t\t#10; r235 = ( | ( r121)); +\t\t#10; r163 = ( ( ! ( $time)) != (2\'h3 ? r30 : (r38 % 26\'h781f))); +\t\t#10; r118 = ( & ( r48)); +\t\t#10; r27 = ( | ( ( ! ( r110)))); +\t\t#10; r226 = (r163 * 20\'h3fca); +\t\t#10; r170 = (r217 && r180); +\t\t#10; r22 = ((r234 > 27\'h2e9d) / 6\'h35); +\t\t#10; r158 = (1\'h1 === 9\'h122); +\t\t#10; r83 = r244; +\t\t#10; r189 = r11; +\t\t#10; r233 = ( & ( (4\'h6 <= (((r254 / r74) + (r104 < ((31\'h6871 !== ( ( ^ ( (r235 === $time))) ? (($time % r158) && (23\'h4695 > ( ~ ( 9\'h165)))) : r225)) || (( ( + ( r138)) - r213) < (r43 ^ ( | ( r91))))))) >= ($time + (r186 ? 27\'h3860 : r182)))))); +\t\t#10; r29 = (((((5\'hf + (r171 == $stime)) !== (30\'h4076 === (((11\'h1e2 <= (17\'h234d || ( | ( 20\'h6b6b)))) < r173) || 24\'h400b))) | r90) % (22\'h620b <= ((5\'h4 * 19\'h67f7) > r168))) & ( + ( $stime))); +\t\t#10; r251 = r250; +\t\t#10; r192 = r214; +\t\t#10; r126 = r114; +\t\t#10; r91 = (25\'h4e2b + ((((r213 || ( ! ( (r79 % r144)))) !== (r251 ^ r127)) % 5\'h1) == ( ( ^ ( 7\'h2e)) * r254))); +\t\t#10; r156 = 23\'h3c0; +\t\t#10; r224 = r158; +\t\t#10; r255 = (( ( ! ( ( & ( ( | ( r88)))))) == r179) >= (r137 || 31\'h4d5f)); +\t\t#10; r69 = (((r77 || 15\'h4f09) ^ ((( ( ~ ( ((r190 ? 4\'h6 : ((r135 && ((r151 || 13\'hb64) - ( ! ( (r38 % r115))))) != r54)) | ((((r8 + ( ( ~ ( ((22\'h50de >= 4\'h5) || (10\'h3af !== 10\'h188)))) < (((13\'h8ac * 28\'h65db) ^ ( - ( 32\'h108))) - ((14\'h13c7 == 28\'h60f6) !== r253)))) < ($time - ((r11 & ( - ( (17\'h29f6 == 25\'h56c9)))) == (5\'hb > r51)))) <= r88) < 15\'h7b0f)))) * ( - ( r197))) & ( ( - ( r234)) >= ((((12\'h529 < ((20\'h486a <= (8\'hbb == (r4 !== r114))) > ((r68 == 1\'h0) - ((r172 ^ r108) >= ( ( ~ ( (22\'h5e34 + 25\'h35ec))) == r26))))) ? (r30 * ( ! ( (r65 != (((r105 | 3\'h3) - ((3\'h5 - 10\'h315) - 25\'h4df9)) | ((9\'h1e6 ^ 21\'h2aa2) - ((13\'h17bb >= 21\'h7f98) == $time))))))) : 17\'h7c99) / ((r174 | ((r61 != (r233 == ( + ( ( ( | ( 20\'h6357)) !== r173))))) != r219)) % (24\'h6372 === ( | ( (((((15\'h5a99 / 19\'h2862) || (4\'h0 & 28\'h5982)) == r65) && $time) / (( ( + ( (12\'h15f + 8\'h97))) < r96) != (r100 <= (r142 >= 3\'h3))))))))) * (( ( - ( (r30 !== ( | ( ((((2\'h0 | 9\'h61) && (14\'h3841 && 11\'h620)) !== (r236 / r38)) && r68)))))) & r95) ^ ( ~ ( r92)))))) < ( + ( (r76 === $stime))))) == ( ! ( ( ^ ( (((31\'h5d2f >= r92) - (($stime >= r103) < ((r128 | 23\'h22f1) % (20\'h47b3 < ($time === ( | ( r180))))))) / 25\'hb6e)))))); +\t\t#10; r233 = ((r44 >= ( ! ( ( & ( (21\'h38fd || (r106 % (r184 & ( ~ ( (r158 & r174))))))))))) / (7\'h38 % (r100 & ((r11 - r201) ? (r130 + ( ^ ( $stime))) : (( ( ~ ( (1\'h1 ^ r76))) - ( & ( (3\'h0 >= ( ( & ( r50)) != ($stime | r49)))))) + (30\'h6282 * 29\'hfe6)))))); +\t\t#10; r214 = (30\'h1532 / ((((r137 && (r27 - $time)) | ((r222 >= ((r101 ? ( & ( (( ( + ( r93)) & ( ~ ( ( ~ ( ((12\'ha8d && 10\'h1b2) > r62)))))) + ( ~ ( r201))))) : r235) !== (($stime ^ ( | ( r92))) & (20\'h3e39 > ((32\'h39ff - (r181 === r17)) || r160))))) ^ (32\'h4120 * ( - ( (22\'h7d08 < ((32\'h74fd != (( ( - ( 4\'he)) >= ((23\'h7cee <= r20) & ( + ( (20\'h4711 / 32\'h1bb6))))) + ((((21\'h2fec === 13\'hd08) === 7\'h22) <= ( ( ! ( 17\'h6a6)) == r109)) | ((9\'h1c + (1\'h0 | 29\'h4e54)) >= $time)))) - 29\'h5ff4))))))) !== r237) / 10\'h256)); +\t\t#10; r26 = (27\'h3abb & ($stime * r112)); +\t\t#10; r28 = (r212 < 4\'hd); +\t\t#10; r128 = r109; +\t\t#10; r59 = $time; +\t\t#10; r180 = r37; +\t\t#10; r109 = 6\'h10; +\t\t#10; r80 = (r0 > r215); +\t\t#10; r26 = 2\'h1; +\t\t#10; r185 = (7\'h76 !== ((((r221 - (((r159 !== ( ~ ( 16\'h110b))) || (r133 % $stime)) & (r66 - 30\'h5f20))) !== 8\'h99) - r170) == (25\'h345f !== (r78 ^ ( ( + ( ( ^ ( ( - ( (r196 ^ $time))))))) !== (5\'h1 && (10\'hee - (19\'h4256 ^ r246)))))))); +\t\t#10; r146 = 26\'h1c07; +\t\t#10; r69 = ( + ( r129)); +\t\t#10; r187 = (((r245 | ( & ( 6\'h32))) == 28\'h34e2) || r128); +\t\t#10; r38 = $stime; +\t\t#10; r233 = ( ^ ( 18\'h57d6)); +\t\t#10; r174 = (22\'h93b !== 20\'h10d4); +\t\t#10; r150 = ( ( ^ ( r156)) && (((( ( | ( r211)) != r229) + (r249 - ((r17 ? ( + ( ( ~ ( (( ( ! ( ( & ( 31\'h6a65)))) || r174) && r229))))) : (r109 - r100)) | (((31\'h15d == (12\'h2b & ( ( ! ( r246)) + $time))) <= r14) >= ((30\'h34b2 != r120) - (((((r100 === (r251 ^ 22\'h665)) ? ((19\'h2712 || r233) - ((8\'h17 * 32\'h4a8) * (12\'h98c % 11\'h480))) : r56) > (r104 ^ r14)) - ( ~ ( ( - ( ( ( | ( (4\'h2 !== 29\'h34bc))) != ( & ( r57)))))))) >= ( ^ ( r63)))))))) && 7\'h66) !== 14\'h1b9f)); +\t\t#10; r162 = r235; +\t\t#10; r172 = (r216 > ($time > (28\'h5158 % r196))); +\t\t#10; r184 = (( ( - ( r45)) != (((r130 >= ( ! ( (r19 === $stime)))) > (14\'h520 / ( ^ ( 15\'h5fdb)))) && $time)) === ( & ( (r242 && ( ^ ( (((r120 * r148) <= ((r231 < r248) | r48)) != r187))))))); +\t\t#10; r17 = 11\'h50b; +\t\t#10; r55 = (12\'h425 !== $time); +\t\t#10; r153 = r221; +\t\t#10; r74 = 29\'h4919; +\t\t#10; r117 = r42; +\t\t#10; r28 = $time; +\t\t#10; r32 = (r204 ? ((r140 >= $time) > (r15 % ( | ( ((9\'h109 * r58) * r240))))) : ( ( & ( ((5\'h8 / r5) ? 3\'h2 : r72))) > (3\'h0 - ( ^ ( r104))))); +\t\t#10; r11 = (r105 | ((r67 >= (((((11\'h6cc == 20\'h5279) - (((( ( ^ ( 2\'h0)) >= (25\'h262e % (((1\'h1 ^ 4\'h5) < (32\'h34e3 + 32\'h3f3f)) ^ r81))) !== (3\'h1 - r162)) & ( ( + ( ( ! ( r171)))) === ((r95 && 3\'h1) % 11\'h241))) < $time)) / 14\'h3e43) - r219) - 5\'h0)) % ((22\'h6f46 < ( ( ^ ( ( ! ( ((15\'h4328 == (9\'h7a < r234)) > r75))))) && r179)) && ( & ( (r174 * r120)))))); +\t\t#10; r152 = ( ( & ( r53)) % (r193 - ((((r106 % r173) && r85) / $time) * ( - ( r82))))); +\t\t#10; r181 = r166; +\t\t#10; r189 = 23\'h5062; +\t\t#10; r129 = 12\'h998; +\t\t#10; r39 = 32\'h51e9; +\t\t#10; r16 = (($time % 12\'h63f) + r134); +\t\t#10; r223 = 12\'h62; +\t\t#10; r51 = (( ( ^ ( 9\'h6b)) & ( ! ( (28\'h7eb0 | (r13 > (((r131 % (r176 != ((21\'h7647 === ((22\'h4cf1 ^ r217) * ( ( + ( 15\'h40e1)) / r15))) ^ r191))) / ($stime || ( ( & ( ( ( - ( 7\'h51)) <= ((19\'h3479 > ((11\'h518 > 25\'h3c63) | (11\'h243 ? 14\'h3d56 : 11\'h19e))) == (((25\'h42 == 29\'h4a37) > r19) * r255))))) && r196))) % r91)))))) + r104); +\t\t#10; r177 = (22\'h187d + (23\'h2808 < ((r46 >= ( - ( 8\'hef))) & ((20\'h68db != ( - ( r158))) + r185)))); +\t\t#10; r194 = $stime; +\t\t#10; r219 = r208; +\t\t#10; r94 = r73; +\t\t#10; r61 = ((r25 - 26\'h3cec) && ( - ( (r171 & r51)))); +\t\t#10; r249 = (17\'h1cad > $stime); +\t\t#10; r238 = (((r100 === r94) ? ((( ( + ( 31\'h39d9)) == r226) === (r220 + $time)) === ( ^ ( ( ( ^ ( 20\'h5654)) != ((r147 + ( | ( r163))) - $stime))))) : ((28\'ha75 >= (19\'h59e0 - 32\'h11eb)) > 25\'h2ad6)) > 6\'h32); +\t\t#10; r176 = r71; +\t\t#10; r239 = ( & ( (r64 ? ( - ( 25\'h3d72)) : r249))); +\t\t#10; r34 = ((((((r153 == r230) && (( ( ^ ( ((r127 != (((28\'h4dc6 != ( ! ( ( ! ( 18\'h3da9))))) - ( ! ( ((9\'h12e % 4\'h0) <= (19\'h2020 | 20\'h2df2))))) & r166)) != 24\'h3de8))) === (((r106 == ( ( & ( ( ~ ( r47)))) % ( ~ ( ((r127 || r121) - (r238 !== (1\'h1 >= 17\'h5887))))))) - ( & ( (12\'h8b2 <= 17\'hb10)))) + ( + ( $time)))) ? 19\'h55b5 : ( | ( ( ^ ( ( ! ( (r147 ? (24\'h3adc && 20\'h2e20) : (r121 % ((( ( ~ ( 15\'h1caa)) <= r178) <= (r238 ? ( ! ( 27\'h4907)) : (27\'h1b95 && 19\'h699e))) <= r225))))))))))) / r224) / r141) != ( + ( r154))) * (( ( ^ ( r176)) + 1\'h0) || r214)); +\t\t#10; r195 = ( ( ! ( (20\'h568d / ( ( | ( ( ( | ( (((r179 && ( ~ ( ( ( & ( ((14\'h31b8 + 13\'hab0) != 14\'h758))) & ( ! ( 4\'h6)))))) < (11\'h7d9 % ( ! ( (21\'h59ed != r91))))) - $stime))) + r10))) - r23)))) * 12\'h86); +\t\t#10; r198 = ((r185 == (24\'h38c1 & (29\'h636c != ( - ( (((r236 >= ( & ( r244))) >= ( ( - ( ($time & ( + ( r76))))) ? 17\'h7d27 : ( - ( 28\'h42b0)))) - ( + ( (19\'hb62 === ((8\'hc9 && ( ^ ( r143))) || (23\'h13e0 !== (((17\'h5c98 < r59) === (r141 >= ( ( ^ ( 27\'h5389)) || (8\'h5c != 10\'h2ba)))) <= r136)))))))))))) < ((((23\'h68e8 >= r212) ? (r115 < ( ( ^ ( ( ^ ( $stime)))) & (((((4\'h7 ? ((r7 - $time) & (17\'h6c4b > (26\'h1d90 !== (22\'h6c66 < 6\'h2f)))) : 26\'h1f77) >= (20\'h5a16 > ( ^ ( ( ^ ( ((11\'h2f1 > 10\'h3f7) ^ ( - ( 32\'h719e))))))))) - $time) == 24\'h11e0) * ( ( + ( r122)) - 5\'h6)))) : r221) >= ( | ( ( + ( (14\'h2a24 - (16\'h6dd0 >= 25\'h1376))))))) > r54)); +\t\t#10; r79 = (( ( + ( ( ( + ( (((((20\'h5369 && r249) ? (((r87 == (((5\'h0 ? 14\'h2f85 : 14\'h1dae) / 30\'h3c96) !== ((18\'h7d54 >= 27\'h19b) / (32\'h6e73 != 32\'h6d1e)))) === 15\'h25af) * ( + ( ( | ( (((24\'h4069 !== 23\'h5c26) && r36) && ( ! ( 29\'h4aa6)))))))) : 9\'h14e) / (9\'h19b !== ( ( & ( $stime)) + 8\'hb2))) || ((( ( | ( ((((26\'h6ff8 ? 4\'h9 : 10\'h23d) ? (15\'h1a1e || 17\'h6cd9) : (11\'h689 === 9\'h1ac)) != 24\'h16e8) == ( ( + ( r140)) & $time)))) & (30\'h3029 > (4\'ha * (r208 * ((8\'h8b <= 27\'h63d4) < r215))))) * (r123 > 3\'h3)) | (27\'h527f + r177))) + (19\'h722e <= 6\'h27)))) | (r183 >= ((7\'h6a % ((10\'h9e !== (r8 || ( ( ~ ( (r75 == (r104 !== ( & ( 7\'h23)))))) != ((r222 / ( | ( 26\'h1023))) !== $stime)))) > (r255 | $stime))) % ( ! ( 23\'h34ec))))))) == (( ( - ( 21\'h6210)) * r195) !== ((28\'h4979 > r232) | r22))) ^ (r125 * (r212 ^ (r10 != (((r201 >= 9\'h39) < (( ( ~ ( (31\'h2ca8 && ((18\'h7958 - (((31\'h50bf == 7\'h73) === (10\'h184 < 7\'h0)) || ( & ( r100)))) + 17\'h3580)))) >= ((r69 !== (r86 - (( ( & ( $time)) | ( & ( ( - ( 22\'h5f1b))))) > ( ~ ( $time))))) ? 29\'h6b06 : ((r236 >= 1\'h1) < r25))) && 19\'h2808)) === $time))))); +\t\t#10; r100 = (((r202 <= ( ~ ( r244))) == (r147 ? ( ( & ( (( ( | ( r167)) == r42) == r141))) + ( ( + ( ( + ( (((r254 ? $time : 18\'h1c54) | r79) >= ((r25 === r206) != (r38 % r148))))))) * (7\'h67 >= r127))) : ( + ( ((( ( + ( (12\'h4f9 !== ( | ( r221))))) == ((r156 && (11\'h216 | (((22\'h66d5 || ((22\'h1dd4 - 25\'hd54) & (26\'h133f | 12\'h270))) * ( ( ! ( (23\'h6438 > 6\'h5))) ? ( ( - ( 7\'h7b)) & r203) : ((23\'h5cb4 ^ 28\'h1157) <= (32\'h4b39 + 23\'h3ce5)))) <= (((30\'h76b5 ? r69 : (24\'h216b != 28\'h41db)) | ( + ( r123))) * ($stime !== ((28\'hf8e >= 22\'h7349) > r202)))))) ^ ((r9 != r99) || ( & ( (r224 >= r134)))))) || r56) ^ r235))))) ? r79 : ( ( ^ ( ((15\'h2d1e !== ((((5\'h11 >= $stime) | 6\'h2a) * ((27\'hfa0 < ( ~ ( ( | ( ( ~ ( r156))))))) & (11\'hb2 * r48))) === r166)) == ( + ( (((r136 || ( + ( ((( ( - ( 5\'h1b)) == ( ( + ( (19\'h2300 / 10\'h2df))) <= 2\'h0)) ^ ( ( ! ( ( - ( 10\'hd2)))) / (((27\'h3b64 * 16\'h3f17) - (10\'h3d4 | 5\'h18)) == r74))) * r112)))) < 28\'h4d35) * ( | ( ( ( ! ( (29\'h355f <= ( ! ( r124))))) | ((r221 | ( - ( ((r23 + r167) > ( ! ( r106)))))) % r22)))))))))) ^ ( ! ( ((r246 & 27\'h151c) >= 5\'h1e))))); +\t\t#10; r54 = 10\'h1cf; +\t\t#10; r51 = ((r132 >= ( | ( (r228 && 24\'h35b3)))) / 3\'h7); +\t\t#10; r43 = (r28 > ( - ( (r24 % ((r100 & (r249 % r181)) ? 28\'h6c6d : (26\'h6a62 && (r47 > ((13\'haae != (r63 == ( ! ( ((((r48 || 4\'h4) ^ (r249 >= (18\'h3348 ? 30\'h2e36 : 23\'hf79))) / ( & ( r72))) ^ ((r147 || (r217 >= (29\'h77b4 >= 14\'h585))) >= ( ^ ( 10\'h1ba)))))))) % ((( ( + ( ( - ( $stime)))) | $stime) > 30\'h2161) % ($time % (( ( ~ ( ( & ( 5\'h3)))) == r206) || r203))))))))))); +\t\t#10; r49 = ( + ( (( ( ^ ( (32\'h73e8 <= ((13\'h372 < ((r196 / ( ! ( ( ( - ( (r29 / (17\'h609c && 6\'h2f)))) / r103)))) && ((r245 + 21\'h5feb) === (r195 < (r240 % ((((23\'h27da + 26\'hc96) == ( & ( 25\'h7a84))) >= ( ( - ( 29\'h33a4)) !== (5\'he * 3\'h0))) % (( ( + ( 1\'h0)) ^ (18\'h6e7e != 30\'h3fba)) & $stime))))))) * 16\'h88f)))) * 10\'h3fb) < ((($stime % 26\'h3cd3) * ((((r63 !== 32\'h1ea4) + (13\'hd6c != 3\'h4)) < (($time > 31\'h6440) + ((r51 && ( ( ! ( r108)) == (r28 % 10\'h25e))) ^ r75))) - 22\'h20d8)) & 10\'h396)))); +\t\t#10; r248 = 23\'h1af5; +\t\t#10; r125 = 17\'h1787; +\t\t#10; r156 = $time; +\t\t#10; r200 = (($stime ? 20\'h295e : r19) != r135); +\t\t#10; r209 = (( ( ~ ( (((((r97 + r9) - 12\'h97a) - r11) > ((((r69 == ( ~ ( (r37 / ( & ( (((26\'h2658 == 3\'h1) && (12\'h375 && 11\'h76f)) * r35))))))) != 10\'h290) % (r169 && ( ! ( ( + ( (($time % (r31 % (r216 | (13\'h4f9 * 11\'hd9)))) / r216))))))) * r94)) / (r8 + r209)))) < 1\'h0) > ( | ( r166))); +\t\t#10; r165 = (9\'hd2 - r156); +\t\t#10; r126 = 7\'h15; +\t\t#10; r90 = ((r171 != ( ( ~ ( ((((20\'h4f9f <= (r116 & r103)) >= ((r111 % 15\'h61e6) == r145)) == $stime) == 29\'h475b))) && ( - ( (r207 ? r100 : ( ( - ( ( ! ( 9\'hd0)))) / ( | ( $time)))))))) / r85); +\t\t#10; r82 = 26\'h4010; +\t\t#10; r112 = r191; +\t\t#10; r222 = 9\'h31; +\t\t#10; r185 = (( ( ~ ( ( & ( ($stime != (( ( | ( (1\'h1 ^ $time))) != r163) < (((r136 === (r43 % $stime)) == r192) <= ( + ( (r211 ^ (20\'h60aa != ( ^ ( (( ( ^ ( (4\'h1 <= 20\'h42af))) ? ( ! ( (1\'h1 - 16\'h105))) : (16\'h18a6 && 10\'h379)) | r63)))))))))))))) && (r71 ^ 30\'h3a7e)) >= r52); +\t\t#10; r63 = (( ( ! ( 19\'h71d2)) || r72) && r82); +\t\t#10; r67 = r122; +\t\t#10; r201 = (r110 ^ ( | ( ($stime ? ((r117 - 4\'h5) && ( ( - ( (r35 / (18\'h7494 == (22\'h463d % ( & ( 22\'h302e))))))) / (r141 % ((4\'h2 | (r78 * 19\'h741d)) <= ( + ( ($stime != 16\'h441e))))))) : r252)))); +\t\t#10; r14 = 8\'h25; +\t\t#10; r227 = ( ( ! ( (((( ( ! ( (((12\'ha44 - 13\'h5b3) ? ((r235 || ((((8\'he9 ? 27\'h1dce : 10\'h4a) !== ( - ( 32\'h4efe))) !== 24\'h5642) > r86)) <= (7\'h76 % ((((5\'h1e | 28\'h60ab) != (13\'hd0a + 21\'h76b8)) === ((19\'h402 % 20\'h77e0) || r205)) + r145))) : r242) == ( ! ( ( ( | ( ( | ( (r120 <= ( ( & ( 8\'h25)) - $time)))))) > ( | ( ( ( - ( r5)) ? 11\'h276 : ( ( ^ ( 31\'hbc7)) <= r90)))))))))) - ( - ( (((( ( + ( r232)) && $stime) & $time) * r150) ? r41 : ( | ( ((18\'h22f3 / 4\'h6) == (r76 ? ( ( | ( ($stime && (5\'h18 <= 12\'h483)))) & $stime) : ((((9\'h54 <= 32\'h2f44) | (3\'h5 <= 16\'h57af)) > 30\'h3427) < $time))))))))) - (( ( | ( ( ( ~ ( ( ! ( ((r235 > r232) ^ ( ^ ( ( | ( ( - ( 3\'h0))))))))))) && r240))) + r116) - ( ( ^ ( ( ! ( r19)))) % (r176 != r71)))) ? (r82 != 19\'h5d16) : ((((r247 + (r124 - ((10\'h13b > r155) === (r73 / $stime)))) < r246) / ((r9 - r190) + ((r25 ^ ((25\'h720b / ( ( | ( ((19\'h3f50 && 4\'h8) & (30\'h1773 || 5\'h13)))) > (r150 | 19\'h5393))) || ((r12 >= (((17\'h434d === 8\'hd9) * 29\'h5a0b) > r21)) & r129))) * ( ( - ( r99)) == r227)))) < (22\'h791f <= 5\'h1b))) + r18))) && ((8\'h71 == 3\'h7) !== r85)); +\t\t#10; r112 = $stime; +\t\t#10; r9 = ( ^ ( (r91 !== ( + ( ((r23 >= r175) | (((14\'h144a + ((3\'h6 * (r67 || ((( ( | ( (2\'h2 != 22\'h5093))) && 17\'h18af) + (32\'h3d27 > 9\'h11)) - (((12\'h474 && $time) != ((13\'h1f06 * 4\'he) == (6\'h20 + 20\'h106))) ? ( ! ( ( & ( ( - ( 18\'h7b24)))))) : r173)))) != 6\'h15)) + 4\'h1) & $time))))))); +\t\t#10; r143 = 14\'h2865; +\t\t#10; r123 = 6\'h3d; +\t\t#10; r68 = (10\'h296 * ( ^ ( ( ( + ( ((((((26\'h6a45 - ( - ( ((27\'h5a8b ^ (r216 || (19\'h67a3 + 16\'h4b36))) ^ ( + ( 2\'h3)))))) && 14\'h1816) || r144) * ( - ( r153))) / r192) ^ ((r128 * r13) & ( | ( r212)))))) != ((11\'h5f0 ^ 9\'h17e) == ((27\'h62f3 > r48) | r84)))))); +\t\t#10; r233 = r38; +\t\t#10; r11 = r39; +\t\t#10; r138 = (( ( - ( 25\'h745)) === (23\'h560d >= ( | ( ( ~ ( r208)))))) ^ (((r193 % r112) % (25\'h2df3 === 30\'h2e15)) || r198)); +\t\t#10; r122 = 24\'h62ec; +\t\t#10; r255 = 24\'h4ba0; +\t\t#10; r107 = (((r202 || ((19\'h6de4 | 18\'h4463) | (7\'h7 + (2\'h0 % ( - ( ( ! ( ( ( ^ ( (r46 !== ((29\'h1a74 ^ ( ( - ( 7\'h69)) != ( ! ( 15\'h777)))) - (((9\'h90 / 29\'h787c) && (29\'h2626 !== 10\'h11c)) | (5\'hb == ( ! ( 14\'h2aec)))))))) || r224))))))))) <= ((($stime % r96) || (( ( & ( ( ( ^ ( ((((((8\'hc5 < 30\'h3fbc) ? r59 : (26\'h6bb6 !== 20\'h4c53)) & ( ( ~ ( 32\'h1e0d)) != ( - ( 14\'h85c)))) !== ((r245 ? 18\'h5cb8 : (6\'h8 | 31\'h321c)) != ((15\'h260b - 18\'h4db3) >= (18\'h4dd >= 16\'h703b)))) % r225) < r158))) + 22\'h6c04))) >= (r216 + $time)) ? (((r243 | ( ~ ( ( ^ ( 3\'h4))))) < ((((26\'h5eda ? $time : (r243 + 32\'h15fb)) != 31\'h1d73) < ((r52 <= r10) < (((31\'h5a7c === (r163 & (10\'h2e4 >= 29\'h1549))) || r119) != ($time !== r184)))) || ( ^ ( ( ( ~ ( (((12\'h669 ^ (25\'h5139 | 22\'h54d2)) & r123) !== 7\'h56))) != r7))))) / (r81 | 8\'h39)) : ( ! ( r60)))) ? ( ^ ( r135)) : r94)) / 21\'h5e3f); +\t\t#10; r80 = ((r16 ? r183 : ($time <= r178)) / ( + ( ( ( | ( ((r54 !== r222) + (( ( ~ ( ( + ( 3\'h3)))) && ((((((( ( ! ( 2\'h1)) != (23\'h4dc1 || 25\'h6418)) & ((15\'h3134 + 2\'h1) * (4\'h4 ? 29\'h7aeb : 24\'h1db3))) || r131) < r248) + ($time & ( | ( r78)))) | ((((8\'he9 || ((28\'h64f2 != 31\'h5ecb) == (5\'h10 !== 16\'h7020))) || (((20\'h1b88 % 27\'h7c75) - (1\'h0 === 5\'h0)) % ( | ( (12\'h4b9 & 19\'h5c3b))))) - (17\'he76 <= 2\'h3)) / ( ~ ( r73)))) <= (17\'h386e | (r194 % ( - ( ( ! ( ($time - r125))))))))) > 15\'h7f04)))) === 13\'h1828)))); +\t\t#10; r37 = (($stime == ((r41 !== ( | ( 27\'h1da6))) === (r35 === ( & ( 27\'h2564))))) || ((16\'h512e ? r184 : $stime) & 25\'h56a4)); +\t\t#10; r96 = ( - ( ( ~ ( r31)))); +\t\t#10; r246 = $stime; +\t\t#10; r251 = 28\'h62ae; +\t\t#10; r143 = r4; +\t\t#10; r123 = (r86 - $time); +\t\t#10; r65 = r247; +\t\t#10; r188 = r248; +\t\t#10; r89 = ( ( & ( r73)) & r43); +\t\t#10; r185 = 1\'h1; +\t\t#10; r45 = (( ( | ( ( ^ ( 24\'h1a2d)))) !== r2) <= ( + ( 22\'h7447))); +\t\t#10; r92 = (($stime % ( ^ ( (((r236 ? (((((10\'h240 ? 22\'h7a0d : r163) * 20\'h71a2) >= ( ( - ( r186)) < ((r104 * (((27\'h7436 === 20\'hbfb) || (13\'h1d62 | 26\'h6221)) != ((29\'h823 && 6\'h34) ^ r170))) % ( ( - ( r11)) % (((32\'h611e / 31\'h3c4c) + ( & ( 20\'h30a4))) - ((12\'h85b == 26\'hfd9) < 22\'h74bb)))))) | (24\'h4b4e > ( ! ( ( | ( (( ( + ( (29\'h63b9 >= 31\'h5396))) < (28\'h24a0 & (4\'h5 | 6\'h1c))) | ( - ( ((13\'h6a7 & 5\'h3) >= ( | ( 1\'h0)))))))))))) % (r164 === r50)) : 13\'h25d) == 19\'h4390) || r105)))) | r180); +\t\t#10; r23 = (5\'h5 ^ ( ! ( $stime))); +\t\t#10; r8 = ($time ? (32\'h605f >= ((r233 > ( ~ ( ( ( ^ ( (r28 * 26\'h48ea))) ^ (((16\'h617e & (10\'he4 / r234)) ? 29\'h1e10 : ( ( & ( 11\'h22)) | $stime)) * ( | ( ( - ( ((r200 | r159) == ((r226 < ((22\'h50da ^ r22) >= (19\'h5845 > ( + ( 16\'h3e29))))) !== (( ( ! ( (29\'h34fe && 6\'hc))) !== ((26\'h35c4 < 20\'h5230) * (30\'h14f8 === 6\'he))) < (((10\'hc9 >= 12\'h616) / (24\'h6357 ^ 29\'he15)) >= 31\'h2b58))))))))))))) - ( ( ^ ( 10\'h2af)) == ((32\'h50d6 < 24\'h30c0) > 22\'h570e)))) : r232); +\t\t#10; r245 = (r165 === (r147 === r18)); +\t\t#10; r57 = ( - ( r200)); +\t\t#10; r208 = ( | ( (r75 > 5\'h2))); +\t\t#10; r153 = ( + ( r49)); +\t\t#10; r80 = ( ( - ( (r204 === ((4\'h8 <= 14\'h3eda) / r161)))) % ( ( | ( 17\'h27bf)) != r40)); +\t\t#10; r230 = ((r196 & ((28\'h44ec / r235) - ( ( | ( r84)) ^ ( | ( r199))))) & ( ( - ( (r215 % ((21\'h63b8 < (r247 || ((9\'h1b4 - 5\'he) ? r129 : (((7\'h48 / r63) < 30\'h6df7) <= $time)))) - (r161 <= r141))))) == $time)); +\t\t#10; r58 = r227; +\t\t$displayb(""r0 = "",r0); +\t\t$displayb(""r1 = "",r1); +\t\t$displayb(""r2 = "",r2); +\t\t$displayb(""r3 = "",r3); +\t\t$displayb(""r4 = "",r4); +\t\t$displayb(""r5 = "",r5); +\t\t$displayb(""r6 = "",r6); +\t\t$displayb(""r7 = "",r7); +\t\t$displayb(""r8 = "",r8); +\t\t$displayb(""r9 = "",r9); +\t\t$displayb(""r10 = "",r10); +\t\t$displayb(""r11 = "",r11); +\t\t$displayb(""r12 = "",r12); +\t\t$displayb(""r13 = "",r13); +\t\t$displayb(""r14 = "",r14); +\t\t$displayb(""r15 = "",r15); +\t\t$displayb(""r16 = "",r16); +\t\t$displayb(""r17 = "",r17); +\t\t$displayb(""r18 = "",r18); +\t\t$displayb(""r19 = "",r19); +\t\t$displayb(""r20 = "",r20); +\t\t$displayb(""r21 = "",r21); +\t\t$displayb(""r22 = "",r22); +\t\t$displayb(""r23 = "",r23); +\t\t$displayb(""r24 = "",r24); +\t\t$displayb(""r25 = "",r25); +\t\t$displayb(""r26 = "",r26); +\t\t$displayb(""r27 = "",r27); +\t\t$displayb(""r28 = "",r28); +\t\t$displayb(""r29 = "",r29); +\t\t$displayb(""r30 = "",r30); +\t\t$displayb(""r31 = "",r31); +\t\t$displayb(""r32 = "",r32); +\t\t$displayb(""r33 = "",r33); +\t\t$displayb(""r34 = "",r34); +\t\t$displayb(""r35 = "",r35); +\t\t$displayb(""r36 = "",r36); +\t\t$displayb(""r37 = "",r37); +\t\t$displayb(""r38 = "",r38); +\t\t$displayb(""r39 = "",r39); +\t\t$displayb(""r40 = "",r40); +\t\t$displayb(""r41 = "",r41); +\t\t$displayb(""r42 = "",r42); +\t\t$displayb(""r43 = "",r43); +\t\t$displayb(""r44 = "",r44); +\t\t$displayb(""r45 = "",r45); +\t\t$displayb(""r46 = "",r46); +\t\t$displayb(""r47 = "",r47); +\t\t$displayb(""r48 = "",r48); +\t\t$displayb(""r49 = "",r49); +\t\t$displayb(""r50 = "",r50); +\t\t$displayb(""r51 = "",r51); +\t\t$displayb(""r52 = "",r52); +\t\t$displayb(""r53 = "",r53); +\t\t$displayb(""r54 = "",r54); +\t\t$displayb(""r55 = "",r55); +\t\t$displayb(""r56 = "",r56); +\t\t$displayb(""r57 = "",r57); +\t\t$displayb(""r58 = "",r58); +\t\t$displayb(""r59 = "",r59); +\t\t$displayb(""r60 = "",r60); +\t\t$displayb(""r61 = "",r61); +\t\t$displayb(""r62 = "",r62); +\t\t$displayb(""r63 = "",r63); +\t\t$displayb(""r64 = "",r64); +\t\t$displayb(""r65 = "",r65); +\t\t$displayb(""r66 = "",r66); +\t\t$displayb(""r67 = "",r67); +\t\t$displayb(""r68 = "",r68); +\t\t$displayb(""r69 = "",r69); +\t\t$displayb(""r70 = "",r70); +\t\t$displayb(""r71 = "",r71); +\t\t$displayb(""r72 = "",r72); +\t\t$displayb(""r73 = "",r73); +\t\t$displayb(""r74 = "",r74); +\t\t$displayb(""r75 = "",r75); +\t\t$displayb(""r76 = "",r76); +\t\t$displayb(""r77 = "",r77); +\t\t$displayb(""r78 = "",r78); +\t\t$displayb(""r79 = "",r79); +\t\t$displayb(""r80 = "",r80); +\t\t$displayb(""r81 = "",r81); +\t\t$displayb(""r82 = "",r82); +\t\t$displayb(""r83 = "",r83); +\t\t$displayb(""r84 = "",r84); +\t\t$displayb(""r85 = "",r85); +\t\t$displayb(""r86 = "",r86); +\t\t$displayb(""r87 = "",r87); +\t\t$displayb(""r88 = "",r88); +\t\t$displayb(""r89 = "",r89); +\t\t$displayb(""r90 = "",r90); +\t\t$displayb(""r91 = "",r91); +\t\t$displayb(""r92 = "",r92); +\t\t$displayb(""r93 = "",r93); +\t\t$displayb(""r94 = "",r94); +\t\t$displayb(""r95 = "",r95); +\t\t$displayb(""r96 = "",r96); +\t\t$displayb(""r97 = "",r97); +\t\t$displayb(""r98 = "",r98); +\t\t$displayb(""r99 = "",r99); +\t\t$displayb(""r100 = "",r100); +\t\t$displayb(""r101 = "",r101); +\t\t$displayb(""r102 = "",r102); +\t\t$displayb(""r103 = "",r103); +\t\t$displayb(""r104 = "",r104); +\t\t$displayb(""r105 = "",r105); +\t\t$displayb(""r106 = "",r106); +\t\t$displayb(""r107 = "",r107); +\t\t$displayb(""r108 = "",r108); +\t\t$displayb(""r109 = "",r109); +\t\t$displayb(""r110 = "",r110); +\t\t$displayb(""r111 = "",r111); +\t\t$displayb(""r112 = "",r112); +\t\t$displayb(""r113 = "",r113); +\t\t$displayb(""r114 = "",r114); +\t\t$displayb(""r115 = "",r115); +\t\t$displayb(""r116 = "",r116); +\t\t$displayb(""r117 = "",r117); +\t\t$displayb(""r118 = "",r118); +\t\t$displayb(""r119 = "",r119); +\t\t$displayb(""r120 = "",r120); +\t\t$displayb(""r121 = "",r121); +\t\t$displayb(""r122 = "",r122); +\t\t$displayb(""r123 = "",r123); +\t\t$displayb(""r124 = "",r124); +\t\t$displayb(""r125 = "",r125); +\t\t$displayb(""r126 = "",r126); +\t\t$displayb(""r127 = "",r127); +\t\t$displayb(""r128 = "",r128); +\t\t$displayb(""r129 = "",r129); +\t\t$displayb(""r130 = "",r130); +\t\t$displayb(""r131 = "",r131); +\t\t$displayb(""r132 = "",r132); +\t\t$displayb(""r133 = "",r133); +\t\t$displayb(""r134 = "",r134); +\t\t$displayb(""r135 = "",r135); +\t\t$displayb(""r136 = "",r136); +\t\t$displayb(""r137 = "",r137); +\t\t$displayb(""r138 = "",r138); +\t\t$displayb(""r139 = "",r139); +\t\t$displayb(""r140 = "",r140); +\t\t$displayb(""r141 = "",r141); +\t\t$displayb(""r142 = "",r142); +\t\t$displayb(""r143 = "",r143); +\t\t$displayb(""r144 = "",r144); +\t\t$displayb(""r145 = "",r145); +\t\t$displayb(""r146 = "",r146); +\t\t$displayb(""r147 = "",r147); +\t\t$displayb(""r148 = "",r148); +\t\t$displayb(""r149 = "",r149); +\t\t$displayb(""r150 = "",r150); +\t\t$displayb(""r151 = "",r151); +\t\t$displayb(""r152 = "",r152); +\t\t$displayb(""r153 = "",r153); +\t\t$displayb(""r154 = "",r154); +\t\t$displayb(""r155 = "",r155); +\t\t$displayb(""r156 = "",r156); +\t\t$displayb(""r157 = "",r157); +\t\t$displayb(""r158 = "",r158); +\t\t$displayb(""r159 = "",r159); +\t\t$displayb(""r160 = "",r160); +\t\t$displayb(""r161 = "",r161); +\t\t$displayb(""r162 = "",r162); +\t\t$displayb(""r163 = "",r163); +\t\t$displayb(""r164 = "",r164); +\t\t$displayb(""r165 = "",r165); +\t\t$displayb(""r166 = "",r166); +\t\t$displayb(""r167 = "",r167); +\t\t$displayb(""r168 = "",r168); +\t\t$displayb(""r169 = "",r169); +\t\t$displayb(""r170 = "",r170); +\t\t$displayb(""r171 = "",r171); +\t\t$displayb(""r172 = "",r172); +\t\t$displayb(""r173 = "",r173); +\t\t$displayb(""r174 = "",r174); +\t\t$displayb(""r175 = "",r175); +\t\t$displayb(""r176 = "",r176); +\t\t$displayb(""r177 = "",r177); +\t\t$displayb(""r178 = "",r178); +\t\t$displayb(""r179 = "",r179); +\t\t$displayb(""r180 = "",r180); +\t\t$displayb(""r181 = "",r181); +\t\t$displayb(""r182 = "",r182); +\t\t$displayb(""r183 = "",r183); +\t\t$displayb(""r184 = "",r184); +\t\t$displayb(""r185 = "",r185); +\t\t$displayb(""r186 = "",r186); +\t\t$displayb(""r187 = "",r187); +\t\t$displayb(""r188 = "",r188); +\t\t$displayb(""r189 = "",r189); +\t\t$displayb(""r190 = "",r190); +\t\t$displayb(""r191 = "",r191); +\t\t$displayb(""r192 = "",r192); +\t\t$displayb(""r193 = "",r193); +\t\t$displayb(""r194 = "",r194); +\t\t$displayb(""r195 = "",r195); +\t\t$displayb(""r196 = "",r196); +\t\t$displayb(""r197 = "",r197); +\t\t$displayb(""r198 = "",r198); +\t\t$displayb(""r199 = "",r199); +\t\t$displayb(""r200 = "",r200); +\t\t$displayb(""r201 = "",r201); +\t\t$displayb(""r202 = "",r202); +\t\t$displayb(""r203 = "",r203); +\t\t$displayb(""r204 = "",r204); +\t\t$displayb(""r205 = "",r205); +\t\t$displayb(""r206 = "",r206); +\t\t$displayb(""r207 = "",r207); +\t\t$displayb(""r208 = "",r208); +\t\t$displayb(""r209 = "",r209); +\t\t$displayb(""r210 = "",r210); +\t\t$displayb(""r211 = "",r211); +\t\t$displayb(""r212 = "",r212); +\t\t$displayb(""r213 = "",r213); +\t\t$displayb(""r214 = "",r214); +\t\t$displayb(""r215 = "",r215); +\t\t$displayb(""r216 = "",r216); +\t\t$displayb(""r217 = "",r217); +\t\t$displayb(""r218 = "",r218); +\t\t$displayb(""r219 = "",r219); +\t\t$displayb(""r220 = "",r220); +\t\t$displayb(""r221 = "",r221); +\t\t$displayb(""r222 = "",r222); +\t\t$displayb(""r223 = "",r223); +\t\t$displayb(""r224 = "",r224); +\t\t$displayb(""r225 = "",r225); +\t\t$displayb(""r226 = "",r226); +\t\t$displayb(""r227 = "",r227); +\t\t$displayb(""r228 = "",r228); +\t\t$displayb(""r229 = "",r229); +\t\t$displayb(""r230 = "",r230); +\t\t$displayb(""r231 = "",r231); +\t\t$displayb(""r232 = "",r232); +\t\t$displayb(""r233 = "",r233); +\t\t$displayb(""r234 = "",r234); +\t\t$displayb(""r235 = "",r235); +\t\t$displayb(""r236 = "",r236); +\t\t$displayb(""r237 = "",r237); +\t\t$displayb(""r238 = "",r238); +\t\t$displayb(""r239 = "",r239); +\t\t$displayb(""r240 = "",r240); +\t\t$displayb(""r241 = "",r241); +\t\t$displayb(""r242 = "",r242); +\t\t$displayb(""r243 = "",r243); +\t\t$displayb(""r244 = "",r244); +\t\t$displayb(""r245 = "",r245); +\t\t$displayb(""r246 = "",r246); +\t\t$displayb(""r247 = "",r247); +\t\t$displayb(""r248 = "",r248); +\t\t$displayb(""r249 = "",r249); +\t\t$displayb(""r250 = "",r250); +\t\t$displayb(""r251 = "",r251); +\t\t$displayb(""r252 = "",r252); +\t\t$displayb(""r253 = "",r253); +\t\t$displayb(""r254 = "",r254); +\t\t$finish(0); +\tend +endmodule +" +"module top; + real rl1, rl2; + wire eq, ne, gt, ge, lt, le; + reg passed = 1\'b1; + + // Check that a decimal constant is converted to a real value. + assign eq = rl2 == 0; +// assign eq = rl2 == rl1; + assign ne = rl2 != rl1; + assign gt = rl2 > rl1; + assign ge = rl2 >= rl1; + assign lt = rl2 < rl1; + assign le = rl2 <= rl1; + + initial begin + rl1 = 0.0; + rl2 = 0.0; + #1 if ({eq,ne,gt,ge,lt,le} != 6\'b100101) begin + $display(""Failed: expected %b, received %b"", 6\'b100101, + {eq,ne,gt,ge,lt,le}); + passed = 1\'b0; + end + #1 rl2 = -1.0; + #1 if ({eq,ne,gt,ge,lt,le} != 6\'b010011) begin + $display(""Failed: expected %b, received %b"", 6\'b010011, + {eq,ne,gt,ge,lt,le}); + passed = 1\'b0; + end + #1 rl2 = 1.0; + #1 if ({eq,ne,gt,ge,lt,le} != 6\'b011100) begin + $display(""Failed: expected %b, received %b"", 6\'b001100, + {eq,ne,gt,ge,lt,le}); + passed = 1\'b0; + end + if (passed) $display(""PASSED""); + end +endmodule +" +"module pr3592746(); + +reg Iteration; + +integer RepeatCount[1:0]; + +task RepeatTest; + +begin + repeat(Iteration == 1 ? 3 : 2) begin + $display(""Iteration = %b"", Iteration); + RepeatCount[Iteration] = RepeatCount[Iteration] + 1; + end +end + +endtask + +initial begin + RepeatCount[0] = 0; + RepeatCount[1] = 0; + Iteration = 0; + RepeatTest; + Iteration = 1; + RepeatTest; + if ((RepeatCount[0] == 2) && (RepeatCount[1] == 3)) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module br918b(); + +wire [3:0] w; + +assign (pull1,strong0) w[1:0] = 2\'b00; +assign (pull1,strong0) w[1:0] = 2\'b10; + +assign (pull1,strong0) w[3:2] = 2\'b11; +assign (pull1,strong0) w[3:2] = 2\'b10; + +initial begin + #1 $display(""%b"", w); + if (w === 4\'b1000) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"// +// Author: Pawel Szostek (pawel.szostek@cern.ch) +// Date: 01.08.2011 + +`timescale 1ns/1ps +module count_ones_v(input [15:0] vec, output reg [4:0] count); + integer i; + integer result; + always @(vec) begin + result = 0; + for (i=15; i>=0; i=i-1) begin + if(vec[i] == 1\'b1) begin + result = result + 1; + end + end + count = result; + end +endmodule + +module check(input [15:0] a, input [4:0] o_vhdl, input [4:0] o_verilog); + reg ena; +initial begin + ena = 0; + #10; + ena = 1; +end +always @(a)begin + #1 if (ena == 0) begin end + else if (o_vhdl !== o_verilog) begin + $display(""ERROR!""); + $display(""VERILOG: "", o_verilog); + $display(""VHDL: "", o_vhdl); + end +end +endmodule + +module stimulus (output reg [15:0] a); + parameter S = 20000; + int unsigned i,j,k,l; + initial begin //stimulate data + for (i=0; i= 10) + inject = 1\'b1; + else + inject = 1\'b0; + end + endfunction +endmodule + +module main; + wire [15:0] a; + wire [4:0] o_vhdl, o_verilog; + + count_ones_v c_vhdl(a,o_vhdl); + count_ones c_verilog(a,o_verilog); + stimulus stim(a); + check c(a,o_vhdl, o_verilog); + + initial begin + #120000; + $display(""PASSED""); + end + +endmodule +" +"primitive latch(q, e, d); + +output q; +input e; +input d; + +reg q; + +table +// e d | q | q+ | + 1 1 : ? : 1 ; + 1 0 : ? : 0 ; + 0 ? : ? : - ; +endtable + +endprimitive + +module test(); + +wire q; +reg e; +reg d; +reg r; + +latch latch(q, e, d); + +always @(q) begin + r = 1; +end + +initial begin + #1; + $display(""%b %b"", q, r); + // the \'x\' should propagate to q before the start of simulation + if (r === 1\'bx && q === 1\'bx) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"/* + * This program handles the case of a system task within a user + * defined function. + */ +module main; + + reg [31:0] tmp1; + reg [31:0] tmp2; + + function [31:0] test; + input [31:0] op1; + + $write(""op1 = %h\ +"", op1); + + endfunction + + initial + begin + tmp1 = \'hdeadbeef; + tmp2 = test(tmp1); + $display(""PASSED""); + end + +endmodule +" +"/* + * This program tests the simple parameter override from the command + * line. This program should be compiled with the -Pmain.foo=2 argument. + */ +module main; + + parameter foo = 1; + + initial begin + if (foo != 2) begin +\t $display(""FAILED: %m.foo = %d"", foo); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule +" +"// pr1866215 + +module A (CH, CL, SH, SL); + +wire\t[31:6]\tS1L; +wire\t[39:32]\tS1H; +wire\t[31:6]\tC1L; +wire\t[38:32]\tC1H; + +output\t[31:0]\tSL; +output\t[31:0]\tCL; +output\t[47:32]\tSH; +output\t[47:32]\tCH; + +B B0\t(C1H[38:32], {C1L[31:6], CL[5:0]}, S1H[39:32], {S1L[31:6], SL[5:0]}); + +initial begin + #1 $display(""C1H=%h, {C1L, CL}={%h, %h}, S1H=%h, {S1L, SL}={%h, %h}"", +\t C1H, C1L, CL, S1H, S1L, SL); +end + +endmodule + +module B (CH, CL, SH, SL); + +output\t[37:32]\tCH; +output\t[31:0]\tCL; +output\t[38:32]\tSH; +output\t[31:0]\tSL; + +C C0\t(CH, CL, SH, SL); + +endmodule + +module C (CH, CL, SH, SL); + +output\t[38:32]\tCH; +output\t[31:0]\tCL; +output\t[39:32]\tSH; +output\t[31:0]\tSL; + + assign\tCH = 6\'h33; + assign\tCL = 32\'h55555555; + assign\tSH = 7\'h66; + assign\tSL = 32\'haaaaaaaa; +endmodule +" +"module test(); + +wire [7:0] value1; +wire [9:0] value2; + +assign value1[3:0] = 4\'d2; + +assign value2 = {1\'b0, value1, 1\'b1}; + +initial begin + #2 $display(""%b %b"", value1, value2); + if (value2 === 10\'b0zzzz00101) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"// +// Copyright (c) 2000 Steve Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// force3.17A - Template 1 - force reg_lvalue = constant. +// + +module test ; + +reg [3:0] val1; +reg [3:0] val2; + +initial + begin + val2 = 0; + val1 = 2; + #50 ; + if(val2 !== 4\'b0001) + $display(""FAILED""); + else + $display(""PASSED""); + end + +initial + begin + #20; + force val2 = (val1 == 2); + end +endmodule +" +"// pr1784984 +module signed_test; + + reg [31:0] a; + + initial begin + a = (32\'h80000000); + a = a / 2; + $display (""Current Value of a = %h"", a); + if (a !== 32\'h40000000) begin +\t $display(""FAILED""); +\t $finish; + end + + a = a * 2; + $display(""Current value of a = %h"", a); + if (a !== 32\'h80000000) begin +\t $display(""FAILED""); +\t $finish; + end + + a = (32\'h80000000)/2; + $display (""Current Value of a = %h"", a); + if (a !== 32\'h40000000) begin +\t $display(""FAILED""); +\t $finish; + end + + a = (32\'h40000000)*2; + $display (""Current Value of a = %h"", a); + if (a !== 32\'h80000000) begin +\t $display(""FAILED""); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // signed_test +" +"/* + * This is interesting, and not completely intuitive. In the code + * below, the variable ""tmp"" is assigned the value 4\'bxxxx, then + * compated with the unsized literal \'hx. Since \'hx is unsized, it + * is padded to the width of an integer, and the padding is done + * by extending the \'bx. But in the comparison, the unsigned ""tmp"" + * is ZERO extended. Therefore, ""tmp"" and \'hx are NOT equal. + */ +module main; + + reg [3:0] tmp; + + initial begin + tmp = \'hx; + if (tmp !== \'hx) begin +\t $display(""PASSED""); +\t $finish; + end + $display(""FAILED""); + end + +endmodule // main +" +"module check (input signed [22:0] a, b, c); + wire signed [22:0] int_AB; + + assign int_AB = a + b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB !== c) begin + $display(""ERROR""); + $finish; + end +end + +endmodule + +module stimulus (output reg signed [22:0] A, B); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; B= 0; + for (i=0; i + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// test case to show vector ordering bugs. + +module test; + +reg [4:0] foo40;\t// works great. + +reg\t[0:4] foo04;\t// only works for time=0; +//reg\t[4:0] foo04; + +reg\t[5:1] foo51;\t// never works. +//reg\t[4:0] foo51; + +reg\t[1:5] foo15;\t// never works. +//reg\t[4:0] foo15; + +initial begin +\t#102; $finish(0); +end + +initial #1 begin +\tfoo40 = 0; +\tfoo04 = 0; +\tfoo51 = 0; +\tfoo15 = 0; +end + +always #10 begin +\tfoo40 <= foo40 + 1; +\tfoo04 <= foo04 + 1; +\tfoo51 <= foo51 + 1; +\tfoo15 <= foo15 + 1; +end + +always @(foo40) begin +\t$write(""foo40=%8d\ +"", foo40); +end + +always @(foo04) begin +\t$write("" foo04=%8d\ +"", foo04); +end + +always @(foo51) begin +\t$write("" foo51=%8d\ +"", foo51); +end + +always @(foo15) begin +\t$write("" foo15=%8d\ +"", foo15); +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate unary or |(value) +// + + +module main; + +reg [3:0] vect; +reg\terror; +wire\tresult; + +assign result = |(vect); + +initial + begin + error = 0; + for(vect=4\'b0001;vect<4\'b1111;vect = vect + 1) + begin + #1; + if(result !== 1\'b1) + begin + $display(""FAILED - Unary or |(%b)=%b"",vect,result); + error = 1\'b1; + end + end + #1; + vect = 4\'b0000; + #1; + if(result !== 1\'b0) + begin + $display(""FAILED - Unary or |(%b)=%b"",vect,result); + error = 1\'b1; + end + if(error === 0 ) + $display(""PASSED""); + end + +endmodule // main +" +" +module subN + #(parameter WID = 4) + (input wire [WID-1:0] A, + input wire [WID-1:0] B, + output wire [WID:0] Q + /* */); + + assign Q = A - B; + +endmodule // add +" +"// PR1841300 +// The output should be: +// a is \'14\'; b is \'fffffff4\'; c is \'fffffff4\' +module test; + reg[4:0] a; + reg [31:0] b, c; + initial begin + a = 5\'b10100; + b = $signed(a); + c = $signed(_$Finv5(32\'hab)); + $display(""a is \'%h\'; b is \'%h\'; c is \'%h\'"", a, b, c); + end + function [4:0] _$Finv5; + input l; + reg [4:0] l; + _$Finv5 = ~l; + endfunction +endmodule +" +"`timescale 1ns/1ps + +module BUFGCE( + output O, + input I, + input CE +); + +bufif1(O, I, CE); + +specify + (I => O) = (0.1, 0.2); + (CE => O) = (0.3, 0.4); +endspecify + +endmodule + +module dut( + output out, + input in, + input en +); + +BUFGCE clk_IBUF_BUFG_inst(.O(out), .I(in), .CE(en)); + +endmodule + +module top; + +wire out; +reg in, en; + +dut dut(out, in, en); + +initial begin + $sdf_annotate(""ivltests/br_ml20190814.sdf"", dut); +end + +endmodule +" +"/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + reg [3:0] test; + + initial begin +/* A zero count repeat by it self is not allowed by the standard, + test = {0{1\'b1}}; + if (test !== 4\'b0000) begin +\t $display(""FAILED -- {0{1\'b1} == %b"", test); +\t $finish; + end + + but it can be used in a valid concatenation (1364-2005). */ + test = {{0{1\'b1}}, 1\'b0}; + if (test !== 4\'b0000) begin +\t $display(""FAILED -- {0{1\'b1} == %b"", test); +\t $finish; + end + + test = {1{1\'b1}}; + if (test !== 4\'b0001) begin +\t $display(""FAILED -- {1{1\'b1} == %b"", test); +\t $finish; + end + + test = {2{1\'b1}}; + if (test !== 4\'b0011) begin +\t $display(""FAILED -- {2{1\'b1} == %b"", test); +\t $finish; + end + + test = {3{1\'b1}}; + if (test !== 4\'b0111) begin +\t $display(""FAILED -- {3{1\'b1} == %b"", test); +\t $finish; + end + + test = {4{1\'b1}}; + if (test !== 4\'b1111) begin +\t $display(""FAILED -- {4{1\'b1} == %b"", test); +\t $finish; + end + + test = {5{1\'b1}}; + if (test !== 4\'b1111) begin +\t $display(""FAILED -- {5{1\'b1} == %b"", test); +\t $finish; + end + + $display(""PASSED""); + + end // initial begin + +endmodule // main +" +"module top; + reg pass = 1\'b1; + real in, bin; + wire [7:0] out = in; + wire signed [34:0] big = bin; + + initial begin +// $monitor(in,, out,, bin,, big); + bin = 8589934592.5; // 2**33+0.5 overflows a 32 bit long. + #1; + if (big !== 35\'sd8589934593) begin + $display(""Failed: multiword check, expected 8589934593, got %d"", big); + pass = 1\'b0; + end + + if (out !== \'b0) begin + $display(""Failed: initial value, expected 8\'b0, got %b"", out); + pass = 1\'b0; + end + + in = 0.499999; + bin = -25.5; // This test a different branch (small result -> big vec.). + #1; + if (big !== -26) begin + $display(""Failed: small value multiword check, expected -26, got %d"", out); + pass = 1\'b0; + end + + if (out !== 8\'b0) begin + $display(""Failed: rounding value (down, +), expected 8\'b0, got %b"", out); + pass = 1\'b0; + end + + in = -0.499999; + #1; + if (out !== 8\'b0) begin + $display(""Failed: rounding value (down, -), expected 8\'b0, got %b"", out); + pass = 1\'b0; + end + + in = 0.5; + #1; + if (out !== 8\'b01) begin + $display(""Failed: rounding value (up, +), expected 8\'b01, got %b"", out); + pass = 1\'b0; + end + + in = -0.5; + #1; + if (out !== 8\'b11111111) begin + $display(""Failed: rounding value (up, -), expected 8\'b11111111, got %b"", out); + pass = 1\'b0; + end + + in = 256.0; + #1; + if (out !== 8\'b0) begin + $display(""Failed: overflow expected 8\'b0, got %b"", out); + pass = 1\'b0; + end + + in = 511.0; + #1; + if (out !== 8\'b11111111) begin + $display(""Failed: pruning expected 8\'b11111111, got %b"", out); + pass = 1\'b0; + end + + in = 1.0/0.0; + #1; + if (out !== 8\'bxxxxxxxx) begin + $display(""Failed: +inf expected 8\'bxxxxxxxx, got %b"", out); + pass = 1\'b0; + end + + in = -1.0/0.0; + #1; + if (out !== 8\'bxxxxxxxx) begin + $display(""Failed: -inf expected 8\'bxxxxxxxx, got %b"", out); + pass = 1\'b0; + end + + in = $sqrt(-1.0); + #1; + if (out !== 8\'bxxxxxxxx) begin + $display(""Failed: nan expected 8\'bxxxxxxxx, got %b"", out); + pass = 1\'b0; + end + + in = 8589934720.5; + #1; + if (out !== 129) begin + $display(""Failed: overflow value expected 129, got %d"", out); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"// Check the various variable indexed up selects (MSB > LSB). +module top; + parameter [4:1] ap = 4\'h8; + parameter [4:1] bp = 4\'h7; + parameter [0:-3] cp = 4\'h8; + parameter [0:-3] dp = 4\'h7; + + reg passed; + + wire [4:1] a = 4\'h8; + wire [4:1] b = 4\'h7; + wire [0:0] s0 = 0; + wire [1:0] s1 = 0; + wire [2:0] s2 = 0; + reg [4:1] ar = 4\'h8; + reg [4:1] br = 4\'h7; + + wire [0:-3] c = 4\'h8; + wire [0:-3] d = 4\'h7; + wire [0:0] s3 = 0; + wire [1:0] s4 = 0; + reg [0:-3] cr = 4\'h8; + reg [0:-3] dr = 4\'h7; + + wire [1:0] res_a0 = a[s0+:2]; + wire [1:0] res_b0 = b[s0+:2]; + wire [1:0] res_a1 = a[s1+:2]; + wire [1:0] res_b1 = b[s1+:2]; + wire [1:0] res_a2 = a[s2+:2]; + wire [1:0] res_b2 = b[s2+:2]; + + wire [1:0] res_c3 = c[s3+:2]; + wire [1:0] res_d3 = d[s3+:2]; + wire [1:0] res_c4 = c[s4+:2]; + wire [1:0] res_d4 = d[s4+:2]; + + reg [4:1] res_ab; + reg [0:-3] res_cd; + + initial begin + #1; + passed = 1\'b1; + + // Check procedural R-value variable index up selects of a net. + + $display(""a[s0+:2]: %b"", a[s0+:2]); + if (a[s0+:2] !== 2\'b0x) begin + $display(""Failed a[s0+:2], expected 2\'b0x, got %b"", a[s0+:2]); + passed = 1\'b0; + end + + $display(""b[s0+:2]: %b"", b[s0+:2]); + if (b[s0+:2] !== 2\'b1x) begin + $display(""Failed b[s0+:2], expected 2\'b1x, got %b"", b[s0+:2]); + passed = 1\'b0; + end + + $display(""a[s1+:2]: %b"", a[s1+:2]); + if (a[s1+:2] !== 2\'b0x) begin + $display(""Failed a[s1+:2], expected 2\'b0x, got %b"", a[s1+:2]); + passed = 1\'b0; + end + + $display(""b[s1+:2]: %b"", b[s1+:2]); + if (b[s1+:2] !== 2\'b1x) begin + $display(""Failed b[s1+:2], expected 2\'b1x, got %b"", b[s1+:2]); + passed = 1\'b0; + end + + $display(""a[s2+:2]: %b"", a[s2+:2]); + if (a[s2+:2] !== 2\'b0x) begin + $display(""Failed a[s2+:2], expected 2\'b0x, got %b"", a[s2+:2]); + passed = 1\'b0; + end + + $display(""b[s2+:2]: %b"", b[s2+:2]); + if (b[s2+:2] !== 2\'b1x) begin + $display(""Failed b[s2+:2], expected 2\'b1x, got %b"", b[s2+:2]); + passed = 1\'b0; + end + + $display(""c[s3+:2]: %b"", c[s3+:2]); + if (c[s3+:2] !== 2\'bx1) begin + $display(""Failed c[s3+:2], expected 2\'bx1, got %b"", c[s3+:2]); + passed = 1\'b0; + end + + $display(""d[s3+:2]: %b"", d[s3+:2]); + if (d[s3+:2] !== 2\'bx0) begin + $display(""Failed d[s3+:2], expected 2\'bx0, got %b"", d[s3+:2]); + passed = 1\'b0; + end + + $display(""c[s4+:2]: %b"", c[s4+:2]); + if (c[s4+:2] !== 2\'bx1) begin + $display(""Failed c[s4+:2], expected 2\'bx1, got %b"", c[s4+:2]); + passed = 1\'b0; + end + + $display(""d[s4+:2]: %b"", d[s4+:2]); + if (d[s4+:2] !== 2\'bx0) begin + $display(""Failed d[s4+:2], expected 2\'bx0, got %b"", d[s4+:2]); + passed = 1\'b0; + end + + // Check procedural R-value variable index up selects of a parameter. + + $display(""ap[s0+:2]: %b"", ap[s0+:2]); + if (ap[s0+:2] !== 2\'b0x) begin + $display(""Failed ap[s0+:2], expected 2\'b0x, got %b"", ap[s0+:2]); + passed = 1\'b0; + end + + $display(""bp[s0+:2]: %b"", bp[s0+:2]); + if (bp[s0+:2] !== 2\'b1x) begin + $display(""Failed bp[s0+:2], expected 2\'b1x, got %b"", bp[s0+:2]); + passed = 1\'b0; + end + + $display(""ap[s1+:2]: %b"", ap[s1+:2]); + if (ap[s1+:2] !== 2\'b0x) begin + $display(""Failed ap[s1+:2], expected 2\'b0x, got %b"", ap[s1+:2]); + passed = 1\'b0; + end + + $display(""bp[s1+:2]: %b"", bp[s1+:2]); + if (bp[s1+:2] !== 2\'b1x) begin + $display(""Failed bp[s1+:2], expected 2\'b1x, got %b"", bp[s1+:2]); + passed = 1\'b0; + end + + $display(""ap[s2+:2]: %b"", ap[s2+:2]); + if (ap[s2+:2] !== 2\'b0x) begin + $display(""Failed ap[s2+:2], expected 2\'b0x, got %b"", ap[s2+:2]); + passed = 1\'b0; + end + + $display(""bp[s2+:2]: %b"", bp[s2+:2]); + if (bp[s2+:2] !== 2\'b1x) begin + $display(""Failed bp[s2+:2], expected 2\'b1x, got %b"", bp[s2+:2]); + passed = 1\'b0; + end + + $display(""cp[s3+:2]: %b"", cp[s3+:2]); + if (cp[s3+:2] !== 2\'bx1) begin + $display(""Failed cp[s3+:2], expected 2\'bx1, got %b"", cp[s3+:2]); + passed = 1\'b0; + end + + $display(""dp[s3+:2]: %b"", dp[s3+:2]); + if (dp[s3+:2] !== 2\'bx0) begin + $display(""Failed dp[s3+:2], expected 2\'bx0, got %b"", dp[s3+:2]); + passed = 1\'b0; + end + + $display(""cp[s4+:2]: %b"", cp[s4+:2]); + if (cp[s4+:2] !== 2\'bx1) begin + $display(""Failed cp[s4+:2], expected 2\'bx1, got %b"", cp[s4+:2]); + passed = 1\'b0; + end + + $display(""dp[s4+:2]: %b"", dp[s4+:2]); + if (dp[s4+:2] !== 2\'bx0) begin + $display(""Failed dp[s4+:2], expected 2\'bx0, got %b"", dp[s4+:2]); + passed = 1\'b0; + end + + // Check procedural R-value variable index up selects of a reg. + + $display(""ar[s0+:2]: %b"", ar[s0+:2]); + if (ar[s0+:2] !== 2\'b0x) begin + $display(""Failed ar[s0+:2], expected 2\'b0x, got %b"", ar[s0+:2]); + passed = 1\'b0; + end + + $display(""br[s0+:2]: %b"", br[s0+:2]); + if (br[s0+:2] !== 2\'b1x) begin + $display(""Failed br[s0+:2], expected 2\'b1x, got %b"", br[s0+:2]); + passed = 1\'b0; + end + + $display(""ar[s1+:2]: %b"", ar[s1+:2]); + if (ar[s1+:2] !== 2\'b0x) begin + $display(""Failed ar[s1+:2], expected 2\'b0x, got %b"", ar[s1+:2]); + passed = 1\'b0; + end + + $display(""br[s1+:2]: %b"", br[s1+:2]); + if (br[s1+:2] !== 2\'b1x) begin + $display(""Failed br[s1+:2], expected 2\'b1x, got %b"", br[s1+:2]); + passed = 1\'b0; + end + + $display(""ar[s2+:2]: %b"", ar[s2+:2]); + if (ar[s2+:2] !== 2\'b0x) begin + $display(""Failed ar[s2+:2], expected 2\'b0x, got %b"", ar[s2+:2]); + passed = 1\'b0; + end + + $display(""br[s2+:2]: %b"", br[s2+:2]); + if (br[s2+:2] !== 2\'b1x) begin + $display(""Failed br[s2+:2], expected 2\'b1x, got %b"", br[s2+:2]); + passed = 1\'b0; + end + + $display(""cr[s3+:2]: %b"", cr[s3+:2]); + if (cr[s3+:2] !== 2\'bx1) begin + $display(""Failed cr[s3+:2], expected 2\'bx1, got %b"", cr[s3+:2]); + passed = 1\'b0; + end + + $display(""dr[s3+:2]: %b"", dr[s3+:2]); + if (dr[s3+:2] !== 2\'bx0) begin + $display(""Failed dr[s3+:2], expected 2\'bx0, got %b"", dr[s3+:2]); + passed = 1\'b0; + end + + $display(""cr[s4+:2]: %b"", cr[s4+:2]); + if (cr[s4+:2] !== 2\'bx1) begin + $display(""Failed cr[s4+:2], expected 2\'bx1, got %b"", cr[s4+:2]); + passed = 1\'b0; + end + + $display(""dr[s4+:2]: %b"", dr[s4+:2]); + if (dr[s4+:2] !== 2\'bx0) begin + $display(""Failed dr[s4+:2], expected 2\'bx0, got %b"", dr[s4+:2]); + passed = 1\'b0; + end + + // Check continuous assignment R-value variable index up selects. + + if (res_a0 !== 2\'b0x) begin + $display(""Failed res_a0, expected 2\'b0x, got %b"", res_a0); + passed = 1\'b0; + end + + if (res_b0 !== 2\'b1x) begin + $display(""Failed res_b0, expected 2\'b1x, got %b"", res_b0); + passed = 1\'b0; + end + + if (res_a1 !== 2\'b0x) begin + $display(""Failed res_a1, expected 2\'b0x, got %b"", res_a1); + passed = 1\'b0; + end + + if (res_b1 !== 2\'b1x) begin + $display(""Failed res_b1, expected 2\'b1x, got %b"", res_b1); + passed = 1\'b0; + end + + if (res_a2 !== 2\'b0x) begin + $display(""Failed res_a2, expected 2\'b0x, got %b"", res_a2); + passed = 1\'b0; + end + + if (res_b2 !== 2\'b1x) begin + $display(""Failed res_b2, expected 2\'b1x, got %b"", res_b2); + passed = 1\'b0; + end + + if (res_c3 !== 2\'bx1) begin + $display(""Failed res_c3, expected 2\'bx1, got %b"", res_c3); + passed = 1\'b0; + end + + if (res_d3 !== 2\'bx0) begin + $display(""Failed res_d3, expected 2\'bx0, got %b"", res_d3); + passed = 1\'b0; + end + + if (res_c4 !== 2\'bx1) begin + $display(""Failed res_c4, expected 2\'bx1, got %b"", res_c4); + passed = 1\'b0; + end + + if (res_d4 !== 2\'bx0) begin + $display(""Failed res_d4, expected 2\'bx0, got %b"", res_d4); + passed = 1\'b0; + end + + // Check procedural L-value variable index up selects. + + res_ab = 4\'bxxxx; + res_ab[s0+:2] = 2\'b00; + if (res_ab !== 4\'bxxx0) begin + $display(""Failed res_ab[s0], expected 4\'bxxx0, got %b"", res_ab); + passed = 1\'b0; + end + + res_ab = 4\'bxxxx; + res_ab[s1+:2] = 2\'b00; + if (res_ab !== 4\'bxxx0) begin + $display(""Failed res_ab[s1], expected 4\'bxxx0, got %b"", res_ab); + passed = 1\'b0; + end + + res_ab = 4\'bxxxx; + res_ab[s2+:2] = 2\'b00; + if (res_ab !== 4\'bxxx0) begin + $display(""Failed res_ab[s2], expected 4\'bxxx0, got %b"", res_ab); + passed = 1\'b0; + end + + res_cd = 4\'bxxxx; + res_cd[s3+:2] = 2\'b00; + if (res_cd !== 4\'b0xxx) begin + $display(""Failed res_cd[s3], expected 4\'b0xxx, got %b"", res_cd); + passed = 1\'b0; + end + + res_cd = 4\'bxxxx; + res_cd[s4+:2] = 2\'b00; + if (res_cd !== 4\'b0xxx) begin + $display(""Failed res_cd[s4], expected 4\'b0xxx, got %b"", res_cd); + passed = 1\'b0; + end + + if (passed) $display(""Compare tests passed""); + end +endmodule +" +"module top(); + +localparam signed [31:0] SizedValue = -1; +localparam UnsizedValue = -1; + +reg [35:0] Result; +reg Failed; + +initial begin + Failed = 0; + // check for sign extension + Result = SizedValue; + $display(""%h"", Result); + if (Result !== 36\'hfffffffff) Failed = 1; + Result = UnsizedValue; + $display(""%h"", Result); + if (Result !== 36\'hfffffffff) Failed = 1; + + // check for zero extension + Result = \'d0 + SizedValue; + $display(""%h"", Result); + if (Result !== 36\'h0ffffffff) Failed = 1; + Result = \'d0 + UnsizedValue; + $display(""%h"", Result); +`ifdef OLD_UNSIZED + if (Result !== 36\'hfffffffff) Failed = 1; +`else + if (Result !== 36\'h0ffffffff) Failed = 1; +`endif + + if (Failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module top; + real rval1, rval2; + reg val1, val2; + reg [3:0] wval1, wval2; + reg [1:0] wres; + reg res; + reg pass; + + initial begin + pass = 1\'b1; + + val1 = 1\'b0; + val2 = 1\'b0; + res = val1 <-> val2; + if (res !== 1\'b1) begin + $display(""FAILED: 1\'b0 <-> 1\'b0 returned %b not 1\'b1"", res); + pass = 1\'b0; + end + val2 = 1\'b1; + res = val1 <-> val2; + if (res !== 1\'b0) begin + $display(""FAILED: 1\'b0 <-> 1\'b1 returned %b not 1\'b0"", res); + pass = 1\'b0; + end + val2 = 1\'bx; + res = val1 <-> val2; + if (res !== 1\'bx) begin + $display(""FAILED: 1\'b0 <-> 1\'bx returned %b not 1\'bx"", res); + pass = 1\'b0; + end + val2 = 1\'bz; + res = val1 <-> val2; + if (res !== 1\'bx) begin + $display(""FAILED: 1\'b0 <-> 1\'bz returned %b not 1\'bx"", res); + pass = 1\'b0; + end + val1 = 1\'b1; + val2 = 1\'b0; + res = val1 <-> val2; + if (res !== 1\'b0) begin + $display(""FAILED: 1\'b1 <-> 1\'b0 returned %b not 1\'b0"", res); + pass = 1\'b0; + end + val2 = 1\'b1; + res = val1 <-> val2; + if (res !== 1\'b1) begin + $display(""FAILED: 1\'b1 <-> 1\'b1 returned %b not 1\'b1"", res); + pass = 1\'b0; + end + val2 = 1\'bx; + res = val1 <-> val2; + if (res !== 1\'bx) begin + $display(""FAILED: 1\'b1 <-> 1\'bx returned %b not 1\'bx"", res); + pass = 1\'b0; + end + val2 = 1\'bz; + res = val1 <-> val2; + if (res !== 1\'bx) begin + $display(""FAILED: 1\'b1 <-> 1\'bz returned %b not 1\'bx"", res); + pass = 1\'b0; + end + val1 = 1\'bx; + val2 = 1\'b0; + res = val1 <-> val2; + if (res !== 1\'bx) begin + $display(""FAILED: 1\'bx <-> 1\'b0 returned %b not 1\'bx"", res); + pass = 1\'b0; + end + val2 = 1\'b1; + res = val1 <-> val2; + if (res !== 1\'bx) begin + $display(""FAILED: 1\'bx <-> 1\'b1 returned %b not 1\'bx"", res); + pass = 1\'b0; + end + val2 = 1\'bx; + res = val1 <-> val2; + if (res !== 1\'bx) begin + $display(""FAILED: 1\'bx <-> 1\'bx returned %b not 1\'bx"", res); + pass = 1\'b0; + end + val2 = 1\'bz; + res = val1 <-> val2; + if (res !== 1\'bx) begin + $display(""FAILED: 1\'bx <-> 1\'bz returned %b not 1\'bx"", res); + pass = 1\'b0; + end + val1 = 1\'bz; + val2 = 1\'b0; + res = val1 <-> val2; + if (res !== 1\'bx) begin + $display(""FAILED: 1\'bz <-> 1\'b0 returned %b not 1\'bx"", res); + pass = 1\'b0; + end + val2 = 1\'b1; + res = val1 <-> val2; + if (res !== 1\'bx) begin + $display(""FAILED: 1\'bz <-> 1\'b1 returned %b not 1\'bx"", res); + pass = 1\'b0; + end + val2 = 1\'bx; + res = val1 <-> val2; + if (res !== 1\'bx) begin + $display(""FAILED: 1\'bz <-> 1\'bx returned %b not 1\'bx"", res); + pass = 1\'b0; + end + val2 = 1\'bz; + res = val1 <-> val2; + if (res !== 1\'bx) begin + $display(""FAILED: 1\'bz <-> 1\'bz returned %b not 1\'bx"", res); + pass = 1\'b0; + end + + rval1 = 0.0; + val2 = 1\'b0; + res = rval1 <-> val2; + if (res !== 1\'b1) begin + $display(""FAILED: 0.0 <-> 1\'b0 returned %b not 1\'b1"", res); + pass = 1\'b0; + end + val1 = 1\'b0; + rval2 = 2.0; + res = val1 <-> rval2; + if (res !== 1\'b0) begin + $display(""FAILED: 1\'b0 <-> 2.0 returned %b not 1\'b0"", res); + pass = 1\'b0; + end + rval1 = 2.0; + val2 = 1\'bx; + res = rval1 <-> val2; + if (res !== 1\'bx) begin + $display(""FAILED: 2.0 <-> 1\'bx returned %b not 1\'bx"", res); + pass = 1\'b0; + end + rval1 = -5.0; + rval2 = 2.0; + res = rval1 <-> rval2; + if (res !== 1\'b1) begin + $display(""FAILED: -5.0 <-> -2.0 returned %b not 1\'b1"", res); + pass = 1\'b0; + end + wval1 = 4\'b0110; + wval2 = 4\'b1001; + wres = wval1 <-> wval2; + if (wres !== 2\'b01) begin + $display(""FAILED: 4\'b0110 <-> 4\'b1001 returned %b not 2\'b01"", wres); + pass = 1\'b0; + end + wres = $signed(wval1 <-> wval2); + if (wres !== 2\'b11) begin + $display(""FAILED: 4\'b0110 <-> 4\'b1001 returned %b not 2\'b11"", wres); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"/* + * Copyright (c) 2001 Steve Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* Check that display prints the right signed value. */ + +module signed1(); + + reg [7:0] x; + reg signed [7:0] y; + + initial + begin +\tx = 8\'b0000_0011; +\ty = 8\'b1111_1101; + +\t$display(""x = %0d (should be 3)"",x); +\t$display(""y = %0d (should be -3)"",y); + +\tx = y; +\t$display(""x = %0d (should be 253)"",x); + + + end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate continuous sub in assignment..dependent on always - working +// + + +module main; + +reg globvar; + +reg [3:0] var1,var2,var3; +wire [3:0] var3a; +reg error; + +assign var3a = var1 - var2; + +always @( var1 or var2) + var3 = var1 - var2 ; + +initial +begin +error = 0; +for ( var1 = 4\'b0; var1 != 4\'hf; var1 = var1 + 1) + for ( var2 = 4\'b0; var2 != 4\'hf; var2 = var2 + 1) + begin + #1 ; + if(var3 !== var3a) + begin + #1 ; + error = 1; + end + #1; + end +if(error == 0) + $display(""PASSED""); +else + $display(""FAILED""); +end + +endmodule // main +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always disable block_identifier ; + + +module main ; + + +reg [3:0] value1 ; + +always begin : block_id + #1 ; + $display(""Hi there""); + $finish ; + end + +always disable block_id ; + +endmodule +" +"module top; + + task delay; + z.delay; + endtask + + always begin + delay; + end + + initial begin + #10 $display(""PASSED""); + $finish; + end +endmodule + +module z; + task delay; + #1; + endtask +endmodule +" +"module top; + reg [6:0] ltl; + reg signed [6:0] ltl_s; + reg [15:0] big; + reg result, pass; + + initial begin + pass = 1\'b1; + + // An unsigned value should be zero padded. + ltl = 7\'d127; + result = test(ltl); + if (result) begin + $display(""Failed: unsigned argument was sign extended""); + pass = 1\'b0; + end + + // This should be evaluated in an eight bit context since the + // function argument is eight bits. This will set the eight bit. + result = test(ltl+7\'d1); + if (!result) begin + $display(""Failed: function width does not determines expression width.""); + pass = 1\'b0; + end + + // A signed value should be sign padded. + ltl_s = -7\'d1; + result = test(ltl_s); + if (!result) begin + $display(""Failed: signed argument was not sign extended""); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end + + function test ; + input signed [7:0] in; + begin + if (in[7]) test = 1\'b1; + else test = 1\'b0; + end + endfunction +endmodule +" +"// +// Copyright (c) 1999 Thomas Coonan (tcoonan@mindspring.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// Integer Multicycle Divide circuit (divide a 16-bit number by a 16-bit number in 16 cycles). +// +// a / b = q with remainder r +// +// Where a is 16-bits, +// Where b is 16 bits +// +// Module is actually parameterized if you want other widths. +// +// *** Test the ranges of values for which you\'ll use this. For example, you +// can\'t divide FFFF by FF without underflow (overflow?). Mess with +// the testbench. You may need to widen some thing. *** +// +// The answer is 16-bits and the remainder is also 16-bits. +// After the start pulse, the module requires 16 cycles to complete. +// The q/r outputs stay the same until next start pulse. +// Start pulse should be a single cycle. +// Division by zero results in a quotient equal to FFFF and remainder equal to \'a\'. +// +// +// Written by tom coonan. +// +// Notes: +// - This ain\'t fancy. I wanted something straight-forward quickly. Go study +// more elaborate algorithms if you want to optimize area or speed. If you +// have an isolated divide and can spare N cycles for N bits; this may meet your needs. +// - You might want to think more about the sizes of things. I wanted a basic estimate +// of gates plus I specifically needed to divide 16-bits (not even full range) +// by 8-bits. +// - Handle divide by zero at higher level.. +// - I needed a remainder so I could easily to truncate and rounding stuff, +// but remove this to save gates if you don\'t need a remainder. +// - This is about 800 asic gates (0.25um, Standard Cell, 27Mhz). 27Mhz +// is my system clock and NOT the maximum it can go.. +// - I tried to keep everything parameterized by N, but I only worked through +// the N=16 case because that\'s what I needed... +// +module div16 (clk, resetb, start, a, b, q, r, done); + +parameter N = 16;\t// a/b = q remainder r, where all operands are N wide. + +input\t\tclk; +input\t\tresetb;\t// Asynchronous, active low reset. +input\t\tstart;\t// Pulse this to start the division. +input [N-1:0]\ta;\t// This is the number we are dividing (the dividend) +input [N-1:0]\tb;\t// This is the \'divisor\' +output [N-1:0]\tq;\t// This is the \'quotient\' +output [N-1:0]\tr;\t// Here is the remainder. +output\t\tdone;\t// Will be asserted when q and r are available. + +// Registered q +reg [N-1:0]\tq; +reg\t\tdone; + +// Power is the current 2^n bit we are considering. Power is a shifting +// \'1\' that starts at the highest power of 2 and goes all the way down +// to ...00001 Shift this until it is zero at which point we stop. +// +reg [N-1:0]\tpower; + +// This is the accumulator. We are start with the accumulator set to \'a\' (the dividend). +// For each (divisor*2^N) term, we see if we can subtract (divisor*2^N) from the accumulator. +// We subtract these terms as long as adding in the term doesn\'t cause the accumulator +// to exceed a. When we are done, whatever is left in the accumulator is the remainder. +// +reg [N-1:0]\taccum; + +// This is the divisor*2^N term. Essentually, we are taking the divisor (\'b\'), initially +// shifting it all the way to the left, and shifting it 1 bit at a time to the right. +// +reg [(2*N-1):0]\tbpower; + +// Remainder will be whatever is left in the accumulator. +assign r = accum; + +// Do this addition here for resource sharing. +// ** Note that \'accum\' is N bits wide, but bpower is 2*N-1 bits wide ** +// +wire [2*N-1:0] accum_minus_bpower = accum - bpower; + +always @(posedge clk or negedge resetb) begin + if (~resetb) begin + q <= 0; + accum <= 0; + power <= 0; + bpower <= 0; + done <= 0; + end + else begin + if (start) begin + // Reinitialize the divide circuit. + q <= 0; + accum <= a; // Accumulator initially gets the dividend. + power[N-1] <= 1\'b1; // We start with highest power of 2 (which is a \'1\' in MSB) + bpower <= b << N-1; // Start with highest bpower, which is (divisor * 2^(N-1)) + done <= 0; + end + else begin + // Go until power is zero. + // + if (power != 0) begin + // + // Can we add this divisor*2^(power) to the accumulator without going negative? + // Just test the MSB of the subtraction. If it is \'1\', then it must be negative. + // + if ( ~accum_minus_bpower[2*N-1]) begin + // Yes! Set this power of 2 in the quotieny and + // then actually comitt to the subtraction from our accumulator. + // + q <= q | power; + accum <= accum_minus_bpower; + end + // Regardless, always go to next lower power of 2. + // + power <= power >> 1; + bpower <= bpower >> 1; + end + else begin + // We\'re done. Set done flag. + done <= 1; + end + end + end +end +endmodule + +// synopsys translate_off +module test_div16; +reg\t\tclk; +reg\t\tresetb; +reg\t\tstart; +reg [15:0]\ta; +reg [15:0]\tb; +wire [15:0]\tq; +wire [15:0]\tr; +wire\t\tdone; + +integer\t\tnum_errors; + +div16 div16 ( + .clk(clk), + .resetb(resetb), + .start(start), + .a(a), + .b(b), + .q(q), + .r(r), + .done(done) +); + +initial begin + num_errors = 0; + + start = 0; + + // Wait till reset is completely over. + #200; + + // Do some divisions where divisor is constrained to 8-bits and dividend is 16-bits + $display (""16-bit Dividend, 8-bit divisor""); + repeat (25) begin + do_divide ($random, $random & 255); + end + + // Do some divisions where divisor is constrained to 12-bits and dividend is 16-bits + $display (""\ +16-bit Dividend, 12-bit divisor""); + repeat (25) begin + do_divide ($random, $random & 4095); + end + + // Do some divisions where both divisor and dividend is 16-bits + $display (""\ +16-bit Dividend, 16-bit divisor""); + repeat (25) begin + do_divide ($random, $random); + end + + // Special cases + $display (""\ +Special Cases:""); + do_divide (16\'hFFFF, 16\'hFFFF); // largest possible quotient + do_divide (312, 1); // divide by 1 + do_divide ( 0, 42); // divide 0 by something else + do_divide (312, 0); // divide by zero + + // That\'s all. Summarize the test. + if (num_errors === 0) begin + $display (""\ +\ +PASSED""); + end + else begin + $display (""\ +\ +FAILED - There were %0d Errors."", num_errors); + end + + $finish; +end + +task do_divide; + input [15:0] arga; + input [15:0] argb; + + begin + a = arga; + b = argb; + @(posedge clk); + #1 start = 1; + @(posedge clk); + #1 start = 0; + while (~done) @(posedge clk); + #1; + + $display (""Circuit: %0d / %0d = %0d, rem = %0d\\t\\t......... Reality: %0d, rem = %0d"", arga, argb, q, r, a/b, a%b); + if (b !== 0) begin + if (q !== a/b) begin + $display ("" Error! Unexpected Quotient\ +\ +""); + num_errors = num_errors + 1; + end + if (r !== a % b) begin + $display ("" Error! Unexpected Remainder\ +\ +""); + num_errors = num_errors + 1; + end + end + end +endtask + +initial begin + clk = 0; + forever begin + #10 clk = 1; + #10 clk = 0; + end +end + +initial begin + resetb = 0; + #133 resetb = 1; +end + +//initial begin +// $dumpfile (""test_div16.vcd""); +// $dumpvars (0,test_div16); +//end + +endmodule +" +"`define display_passed \\ + initial begin // comment \\ + $display(""PASSED""); \\ + end + +module test(); + +`display_passed + +endmodule +" +"module top; + reg a, pass; + wire x, y, ab; + + assign (weak1, weak0) x = (a === 1\'b1) ? 1\'b0 : 1\'b1; + assign y = a; + // We need this since Icarus currently has a bug when forcing from + // an expression (it only uses the value when the force ran). + assign ab = ~a; + + tran (x, y); + + initial begin + // $monitor ($realtime,, x,y,,a); + pass = 1\'b1; + // Check matching values. + #1 if ( x !== 1\'bx || y !== 1\'bx) begin + $display(""Failed initial value, expected 1\'bx, 1\'bx, got %b %b"", x, y); + pass = 1\'b0; + end + #1 a = 1\'b0; + #1 if ( x !== 1\'b0 || y !== 1\'b0) begin + $display(""Failed same value, expected 1\'b0, 1\'b0, got %b %b"", x, y); + pass = 1\'b0; + end + #1 a = 1\'b1; + #1 if ( x !== 1\'b1 || y !== 1\'b1) begin + $display(""Failed same value, expected 1\'b1, 1\'b1, got %b %b"", x, y); + pass = 1\'b0; + end + // Now force and release the driving signal. + #1 force a = 1\'bx; + #1 if ( x !== 1\'bx || y !== 1\'bx) begin + $display(""Failed driver value, expected 1\'bx, 1\'bx, got %b %b"", x, y); + pass = 1\'b0; + end + #1 release a; + a = 1\'b0; + #1 if ( x !== 1\'b0 || y !== 1\'b0) begin + $display(""Failed driver value, expected 1\'b0, 1\'b0, got %b %b"", x, y); + pass = 1\'b0; + end + // Check that the other driver works. + #1 a = 1\'bz; + #1 if ( x !== 1\'b1 || y !== 1\'b1) begin + $display(""Failed alt. value, expected 1\'b1, 1\'b1, got %b %b"", x, y); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"/* + * This example pulled from comp.lang.verilog. It was written + * by Russell Fredrickson to test + * arithmetic shift for other compilers, and caught mine. + */ + +module ArithmeticShiftTest; + reg signed [31:0] in; + reg [5:0] shift; + reg signed [31:0] out; + + //calculate arithmetic barrel shift right + always@(*) out = in >>> shift; + + initial begin + //set up inputs for always block + in = 32\'sh80000000;//set to highest value negative number(-2147483648) + shift = 6\'d32; //shift the entire width of the word + + #1; //allow time for inputs to propagate + + //check output + if(out === (32\'sh80000000 >>> 6\'d32)) begin + $display(""PASS: 32\'sh80000000 >>> 6\'d32 = 0x%h"", out); + end + else begin + $display(""FAIL: 32\'sh80000000 >>> 6\'d32 != 0x%h,"", + (32\'sh80000000 >>> 6\'d32), "" actual = 0x%h."", out); + end + end // initial begin +endmodule // ArithmeticShiftTest +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate casez/endcase w/ z in label - no match case + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 ) + casez (val1) + 5\'b0000z: result = 0; + 5\'b001z0: result = 1 ; + 5\'b01zz0: result = 2; + endcase + +initial + begin + error = 0; + + val1 = 5\'b0000z ; + if(result !=0) + begin + $display(""FAILED casez 3.10C - case (expr) lab1: ""); + error = 1; + end + + val1 = 5\'b001z0; + if(result !=1) + begin + $display(""FAILED casez 3.10C - case (expr) lab2: ""); + error = 1; + end + + val1 = 5\'b1zzzz;\t// Should get no-action - expr = 3\'b011 + if(result !=1) + begin + $display(""FAILED casez 3.10C - case (expr) lab1: ""); + error = 1; + end + + if(error == 0) + $display(""PASSED""); + end + +endmodule // main +" +"// We don\'t (currently) support a case statement where both the case select +// and one or more case items are variables in asynchronous logic synthesis. +// Check the compiler handles and rejects this code. +module mux( + +input wire [2:0] sel, +input wire [2:0] i1, +input wire [2:0] i2, +input wire [2:0] i3, +input wire [2:0] i4, +input wire [2:0] i5, +output reg [2:0] o + +); + +(* ivl_synthesis_on *) +always @* begin + case (sel) + 0 : o = 0; + 1 : o = i1; + 2 : o = i2; + 3 : o = i3; + i5 : o = i4; + default: + o = 3\'bx; + endcase +end +(* ivl_synthesis_off *) + +initial $display(""PASSED""); + +endmodule +" +"package my_package1; + +parameter p1 = 1; +localparam p2 = p1 + 2; + +typedef logic [15:0] word; + +typedef struct packed { + word v; +} st; + +endpackage + +package my_package2; + +import my_package1::*; + +st s; + +event e; + +function word f(word g); + f = g + 1; +endfunction + +task h(word i); + s.v = s.v + i; + $display(s.v); +endtask + +endpackage + +module test(); + +import my_package1::*; +import my_package2::*; + +word my_v; + +initial begin + my_v = p1; + #1 ->e; +end + +initial begin + @e s.v = my_v; + h(f(1)); + if (p2 === 3 && s.v === 3) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module if_fail_test(); + +`ifdef +`ifndef +`elsif +`else +`endif + + initial $display(""FAILED""); + +endmodule +" +"module top; + task tsk; + $display(""In task %m()""); + endtask + + function void fnc(); + $display(""In function %m()""); + endfunction + + initial begin + $display(""In %m.initial""); + tsk(); + fnc(); + #10; + $display(""Done with simulation at %0d"", $time); + end + + final begin +// tsk(); // This is from gh442 and is now an error + fnc(); + $display(""In %m.final""); + $display(""PASSED""); + end +endmodule +" +"module test; + +wire w; +wire q; +reg g; + +pullup(w); +bufif1(w, 1\'b1, g); +pmos(q, w, 1\'b0); +bufif0(q, 1\'b0, g); + +initial + begin + g = 1; + #10 + $display(q, w);\t// should print ""11"" + #20 + g = 0;\t\t// w changes from St1 to Pu1 + #30 + $display(q, w);\t// should print ""01"" + if (q == 1\'b0) + $display(""PASSED""); + else + $display(""FAILED""); + #40 + $finish; + end + +endmodule +" +"module test(); + +function void do_nothing(); + ; +endfunction + +initial begin + do_nothing(); + $display(""PASSED""); +end + +endmodule +" +"// +// Copyright (c) 2003 Steve Williams +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module main; + + parameter offset = 7.0; + time result; + initial begin + #9 result = $time + offset; + $display(""result = %d"", result); + if (result !== 64\'d16) begin +\t $display(""FAILED -- incorrect result""); +\t $finish; + end + + $display(""PASSED""); + $finish; + end + +endmodule +" +"module top; + reg pass; + uwire zero, one; + + assign one = 1\'b1; + + initial begin + pass = 1\'b1; + #1; + if (zero !== 1\'bz) begin + $display(""Failed: undriven uwire gave %b"", zero); + pass = 1\'b0; + end + if (one !== 1\'b1) begin + $display(""Failed: driven uwire gave %b"", one); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for VHDL std.textio & ieee.std_logic_textio functions implemented using VPI. + +`timescale 1ns/1ns + +typedef enum integer { false, true } boolean; +typedef enum integer { read_mode , write_mode , append_mode } file_open_kind; + +module vhdl_textio_test; + +string line; +int file; + +string str; +bit [3:0][7:0] str_lim; +real r; +int in; +integer i; +byte by; +time t; +boolean boo; + +logic l; +logic [7:0] lv; +bit bi; +bit [7:0] biv; + +initial begin + static string filename = ""vpi_textio_text.tmp""; + + // values to be saved + str = ""test_string""; + str_lim = ""TEST""; + r = -2.5e3; + in = 120; + i = -12; + by = 8\'h1f; + t = 100ns; + boo = true; + l = 1\'bx; + lv = 8\'b110101xz; + bi = 1\'b0; + biv = 8\'b10111001; + + // write test + $ivlh_file_open(file, filename, write_mode); + + $ivlh_write(line, str, 0); // standard format + $ivlh_write(line, "" "", 0); + $ivlh_write(line, str_lim, 4); // string format + $ivlh_write(line, "" "", 0); + $ivlh_write(line, r, 0); + $ivlh_write(line, "" "", 0); + $ivlh_write(line, in, 0); + $ivlh_write(line, "" "", 0); + $ivlh_write(line, i, 0); + $ivlh_write(line, "" "", 0); + $ivlh_write(line, by, 0); + $ivlh_write(line, "" "", 0); + $ivlh_write(line, t, 2); // time format + + // this will be intentionally skipped during the read test + $ivlh_write(line, "" "", 0); + $ivlh_write(line, l, 0); + $ivlh_write(line, "" "", 0); + $ivlh_write(line, lv, 0); + + if(line != ""test_string TEST -2500.000000 120 -12 31 100 ns X 110101XZ"") begin + $display(""FAILED 1""); + $finish(); + end + + $ivlh_writeline(file, line); + + // writeline should clear the written string + if(line != """") begin + $display(""FAILED 2""); + $finish(); + end + + $ivlh_write(line, boo, 1); // boolean format + $ivlh_write(line, "" "", 0); + $ivlh_write(line, l, 0); + $ivlh_write(line, "" "", 0); + $ivlh_write(line, lv, 0); + $ivlh_write(line, "" "", 0); + $ivlh_write(line, bi, 0); + $ivlh_write(line, "" "", 0); + $ivlh_write(line, biv, 0); + $ivlh_write(line, "" "", 0); + $ivlh_write(line, biv, 3); // hex format + + if(line != ""TRUE X 110101XZ 0 10111001 B9"") begin + $display(""FAILED 3""); + $finish(); + end + + $ivlh_writeline(file, line); + $fclose(file); + + // reset variables + str = """"; + r = 0; + in = 0; + i = 0; + by = 0; + t = 0s; + boo = false; + l = 0; + lv = 0; + bi = 0; + biv = 0; + + // read test + $ivlh_file_open(file, filename, read_mode ); + + $ivlh_readline(file, line); + $ivlh_read(line, str, 0); // standard format + $ivlh_read(line, str_lim, 4); // string format + $ivlh_read(line, r, 0); + $ivlh_read(line, in, 0); + $ivlh_read(line, i, 0); + $ivlh_read(line, by, 0); + $ivlh_read(line, t, 2); // time format + + $ivlh_readline(file, line); + $ivlh_read(line, boo, 1); // boolean format + $ivlh_read(line, l, 0); + $ivlh_read(line, lv, 0); + $ivlh_read(line, bi, 0); + $ivlh_read(line, biv, 0); + $ivlh_read(line, biv, 3); // hex format + + $fclose(file); + + // compare read and expected values + if(str != ""test_string"") begin + $display(""FAILED 5""); + $finish(); + end + + if(str_lim != ""TEST"") begin + $display(""FAILED 6""); + $finish(); + end + + if(r != -2.5e3) begin + $display(""FAILED 7""); + $finish(); + end + + if(in !== 120) begin + $display(""FAILED 8""); + $finish(); + end + + if(i !== -12) begin + $display(""FAILED 9""); + $finish(); + end + + if(by !== 8\'h1f) begin + $display(""FAILED 10""); + $finish(); + end + + if(t != 100ns) begin + $display(""FAILED 11""); + $finish(); + end + + if(boo !== true) begin + $display(""FAILED 12""); + $finish(); + end + + if(l !== 1\'bx) begin + $display(""FAILED 13""); + $finish(); + end + + if(lv !== 8\'b110101xz) begin + $display(""FAILED 14""); + $finish(); + end + + if(bi !== 1\'b0) begin + $display(""FAILED 15""); + $finish(); + end + + if(biv !== 8\'b10111001) begin + $display(""FAILED 16""); + $finish(); + end + + $display(""PASSED""); +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate continuous % in assignment..dependent on always % working +// + + +module main; + +reg globvar; + +reg [3:0] var1,var2,var3; +wire [3:0] var3a; +reg error; + +assign var3a = var1 % var2; + +always @( var1 or var2) + var3 = var1 % var2 ; + +initial +begin +for ( var1 = 4\'b0; var1 != 4\'hf; var1 = var1 + 1) + for ( var2 = 4\'b0; var2 != 4\'hf; var2 = var2 + 1) + begin + error = 0; + #1 ; + if(var3 != var3a) + begin + $display(""FAILED continuous 1=%h,2=%h,3=%h,3a=%h"", + var1,var2,var3,var3a); + error = 1; + end + #1; + end +if(error == 0) + $display(""PASSED""); +end +endmodule // main +" +"module m1(); +parameter p = 0; +endmodule + +module m2(); + +generate + genvar i; + for (i = 0; i < 2; i = i + 1) begin : Loop1 + m1 m(); + defparam m.p = 1 + i; + end + for (i = 2; i < 4; i = i + 1) begin : Loop2 + m1 m(); + defparam Loop2[i].m.p = 1 + i; + end + for (i = 4; i < 6; i = i + 1) begin : Loop3 + m1 m(); + defparam m2.Loop3[i].m.p = 1 + i; + end +endgenerate + +reg failed = 0; + +initial begin + $display(""Loop1[0].m.p = %0d"", Loop1[0].m.p); + if (Loop1[0].m.p !== 1) failed = 1; + $display(""Loop1[1].m.p = %0d"", Loop1[1].m.p); + if (Loop1[1].m.p !== 2) failed = 1; + $display(""Loop2[2].m.p = %0d"", Loop2[2].m.p); + if (Loop2[2].m.p !== 3) failed = 1; + $display(""Loop2[3].m.p = %0d"", Loop2[3].m.p); + if (Loop2[3].m.p !== 4) failed = 1; + $display(""Loop3[4].m.p = %0d"", Loop3[4].m.p); + if (Loop3[4].m.p !== 5) failed = 1; + $display(""Loop3[5].m.p = %0d"", Loop3[5].m.p); + if (Loop3[5].m.p !== 6) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module top; + reg a; + reg q, d; + event foo; + real rl; + int ar []; + int start = 0; + int stop = 1; + int step = 1; + int done = 0; + + task a_task; + real trl; + event tevt; + reg tvr; + $display(""user task""); + endtask + + always_comb begin: blk_name + event int1, int2; + real intrl; + q <= d; + -> foo; + rl = 0.0; + rl <= 1.0; + ar = new [2]; + for (int idx = start; idx < stop; idx += step) $display(""For: %0d"", idx); + for (int idx = 0; done; idx = done + 1) $display(""Should never run!""); + for (int idx = 0; idx; done = done + 1) $display(""Should never run!""); + for (int idx = 0; idx; {done, idx} = done + 1) $display(""Should never run!""); + for (int idx = 0; idx; idx <<= 1) $display(""Should never run!""); + for (int idx = 0; idx; idx = idx << 1) $display(""Should never run!""); + $display(""array size: %0d"", ar.size()); + ar.delete(); + $display(""array size: %0d"", ar.size()); + a_task; + assign a = 1\'b0; + deassign a; + do $display(""do/while""); + while (a); + force a = 1\'b1; + release a; + while(a) begin + $display(""while""); + a = 1\'b0; + end + repeat(2) $display(""repeat""); + disable out_name; + forever begin + $display(""forever""); + disable blk_name; // This one should not generate a warning + end + end + + initial #1 $display(""Expect compile warnings!\ +PASSED""); + + initial begin: out_name + #2 $display(""FAILED""); + end + +endmodule +" +"/* From PR#516 */ +module top (); + + parameter GEORGE = 8\'d5; + parameter HARRY = 10; + + initial begin + #1; + $display(""decimal GEORGE: %0d, HARRY: %0d"",GEORGE, HARRY); + $display(""binary GEORGE: \'b%0b, HARRY: \'b%0b"",GEORGE, HARRY); + $finish(0); + end + +endmodule +" +"/* + * This program demonstrates non-constant part selects + * applied to a parameter value. + */ +module main; + + parameter foo = 32\'h76543210; + + reg [3:0] tmp; + reg [3:0] idx; + + initial begin + if (foo[0 +: 4] !== 4\'h0) begin +\t $display(""FAILED -- %b !== 0"", foo[0 +: 4]); +\t $finish; + end + + if (foo[4 +: 4] !== 4\'h1) begin +\t $display(""FAILED -- %b !== 1"", foo[4 +: 4]); +\t $finish; + end + + if (foo[8 +: 4] !== 4\'h2) begin +\t $display(""FAILED -- %b !== 2"", foo[8 +: 4]); +\t $finish; + end + + if (foo[12+: 4] !== 4\'h3) begin +\t $display(""FAILED -- %b !== 3"", foo[12 +: 4]); +\t $finish; + end + + for (idx = 0 ; idx < 8 ; idx = idx + 1) begin +\t tmp = foo[(idx*4) +: 4]; +\t if (tmp !== idx) begin +\t $display(""FAILED -- %b !== %b"", idx, tmp); +\t $finish; +\t end + + end + + for (idx = 0 ; idx < 8 ; idx = idx + 1) begin +\t tmp = foo[(idx*4+3) -: 4]; +\t if (tmp !== idx) begin +\t $display(""FAILED -- %b !== %b"", idx, tmp); +\t $finish; +\t end + + end + + $display(""PASSED""); + end + +endmodule // main +" +"/* + * See pr245 in the ivtest test suite. + */ + +`timescale 1ns/1ns + +module t; + wire [11:0] iodata; + integer i; + + + initial + begin + $timeformat(-9,0,""ns"",7); +\t$display("" TIME:IOD""); +\t$monitor( ""%t:%3x"", +\t\t $time,iodata); +\t#0 +\t force iodata =0; +\tfor (i=0; i<512;i=i+1) +\t #10 +\t force iodata =i; + end // initial begin +endmodule // t +" +" +/* + * This tests a trivial class. This tests that properties can be + * given types, and that the types behave properly. + */ +program main; + + // Trivial example of a class + class foo_t ; + real a; + real b; + endclass : foo_t // foo_t + + foo_t obj; + + initial begin + obj = new; + + // This is the most trivial assignment of class properties. + obj.a = 0.5; + obj.b = -1.5; + + if (obj.a != 0.5 || obj.b != -1.5) begin +\t $display(""FAILED -- assign to object: obj.a=%f, obj.b=%f"", obj.a, obj.b); +\t $finish; + end + + obj.a = obj.a - 0.5; + obj.b = obj.b + 1.5; + if (obj.a != 0.0 || obj.b != 0.0) begin +\t $display(""FAILED -- increment properties: obj.a=%f, obj.b=%f"", obj.a, obj.b); +\t $finish; + end + + $display(""PASSED""); + $finish; + end +endprogram // main +" +"/* + * Copyright (c) 2001 Uwe Bonnes + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +`define ADC_DATA_OFFSET 5 +`define ADC_CHANELS 8*48 +//`define ADC_CHANELS 348 + +module mymod (out1,out2,state,reset); + + input [8:0] state; + input reset; + output out1,out2; + assign out1 = (state > `ADC_DATA_OFFSET) ? 1 : 0; + assign out2 = (state > `ADC_CHANELS + `ADC_DATA_OFFSET +1)|| (reset); + +endmodule // mymod + +module t; + reg [8:0] state; + reg reset; + wire out1,out2; + + mymod m1 (out1,out2,state,reset); + + initial + begin + //$timeformat(-9,0,""ns"",5); + $display("" TIME:state:out1:out2""); + $monitor(""%t:%5d:%4d:%4d"",$time,state,out1,out2); + state =0; + reset = 0; + #10 + reset=1; + #20 + reset=0; + #5110 + $finish; + end + always + begin + #10 + if (reset) + state = 0; + else + state=state+1; + end +endmodule // t +" +"module top; + reg a, b; + reg q, d; + event foo; + + always_comb begin + q = d; + fork + $display(""fork/join 1""); + join + fork + $display(""fork/join_any 1""); + join_any + fork + $display(""fork/join_none 1""); + join_none + a <= @foo 1\'b1; + @(b) a <= repeat(2) @foo 1\'b0; + wait (!a) $display(""wait""); + end + + initial #1 $display(""Expect compile errors!""); + +endmodule +" +"/*********************************************************************** + + Incorrect direction non-detection test case + Copyright (C) 2001 Eric LaForest, ecl@pet.dhs.org + Licenced under GPL + +***********************************************************************/ + +module CPU (data, address, rw, clock, reset); + inout [15:0] data; + output [15:0] address; + // This should be an output really.... + input rw; + input clock, reset; + + reg [15:0] data, address; // XXX error on data + reg rw; // error on rw + + // I presume these should not be allowed to occur.... + always @(posedge clock) begin + rw <= 1'b1; + end + + always @(negedge clock) begin + rw <= 1'b0; + end + +endmodule + +module BENCH (); + + reg [15:0] address, data; + reg rw, clock, reset; + + CPU fm (address, data, rw, clock, reset); + + initial begin + clock <= 0; + reset <= 1; + #1000; + $finish; + end + + always begin + # 10 clock <= ~clock; + end + +endmodule +" +"/* + * Author: Oswaldo Cadenas + * + * The test checks that an unspecified output type is elaborated as Net. + * If an intial value is given to an unspecified ouput type it does + * not compile. + */ + +module clkgen(output clk); + +logic iclk = \'x; +assign clk = iclk; + +initial begin + #100; + disable checking; + disable gen; + $display (""PASSED""); + $finish; +end + +initial begin + fork + checking; +\t gen; + join +end + + +task gen; + begin + iclk = 0; + forever #10 iclk = ~iclk; + end +endtask + +task checking; + forever begin + #1; + if (clk === 1\'bx ) begin + $display (""FAILED!""); +\t $finish; + end + end +endtask +endmodule +" +"module top; + parameter real rpar1 = 1.0; + parameter real rpar2 = 2.0; + parameter real rparb = {rpar1, rpar2}; + parameter real rpar = {2.0, 1.0}; +endmodule +" +"/* + * Copyright (c) 2006 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + * $Id: casesynth1.v,v 1.1 2006/01/01 01:01:31 stevewilliams Exp $"" + */ + + +module main; + + reg clk, rst, set; + reg [3:0] out, load; + reg [1:0] op; + + (* ivl_synthesis_on *) + always @(posedge clk or posedge rst) + if (rst) begin +\tout <= 0; + + end else if (set) begin +\tout <= load; + + end else + case (op) +\t 2\'b01: /* increment */ out <= out + 1; +\t 2\'b10: /* decrement */ out <= out - 1; +\t 2\'b11: /* Invert */ out <= ~out; +\t /* Other ops cause out to not change. */ + endcase // case(mod) + + + (* ivl_synthesis_off *) + initial begin + /* Test rst behavior. */ + op = 2\'b00; + rst = 1; + set = 0; + load = 0; + clk = 0; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4\'b0000) begin +\t $display(""FAILED -- out=%b (reset)"", out); +\t $finish; + end + + /* Test set behavior */ + rst = 0; + set = 1; + load = 4\'b0100; + #1 clk = 1; + #1 clk = 0; + + if (out !== 4\'b0100) begin +\t $display(""FAILED -- out=%b (load)"", out); +\t $finish; + end + + /* Test increment behavior */ + op = 2\'b01; + rst = 0; + set = 0; + load = 0; + #1 clk = 1; + #1 clk = 0; + + if (out !== 4\'b0101) begin +\t $display(""FAILED -- out=%b (increment 1)"", out); +\t $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4\'b0110) begin +\t $display(""FAILED -- out=%b (increment 2)"", out); +\t $finish; + end + + /* Test invert behavior */ + op = 2\'b11; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4\'b1001) begin +\t $display(""FAILED == out=%b (invert)"", out); +\t $finish; + end + + /* Test NO-OP behavior */ + op = 2\'b00; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4\'b1001) begin +\t $display(""FAILED -- out=%b (noop)"", out); +\t $finish; + end + + /* Test decrement behavior */ + op = 2\'b10; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4\'b1000) begin +\t $display(""FAILED -- out=%b (decrement 1)"", out); +\t $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4\'b0111) begin +\t $display(""FAILED -- out=%b (decrement 2)"", out); +\t $finish; + end + + $display(""PASSED""); + $finish; + end +endmodule // main +" +"/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Test the select of a memory word in a continuous assignment. + */ + +module main; + + reg [1:0] a [3:0]; + reg [1:0] s = 0; + + wire [1:0] b = a[s]; + + initial begin + a[0] = 3; + a[1] = 2; + a[2] = 1; + a[3] = 0; + end + + initial begin + #1 if (b !== 3) begin +\t $display(""FAILED -- s=%b, b=%b"", s, b); +\t $finish; + end + + s = 1; + + #1 if (b !== 2) begin +\t $display(""FAILED -- s=%b, b=%b"", s, b); +\t $finish; + end + + s = 2; + + #1 if (b !== 1) begin +\t $display(""FAILED -- s=%b, b=%b"", s, b); +\t $finish; + end + + s = 3; + + #1 if (b !== 0) begin +\t $display(""FAILED -- s=%b, b=%b"", s, b); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"module Top; + +generate + genvar i; + + for (i = 0; i < 1; i = i + 1) begin + Sub1 SubMod1(); + end +endgenerate + +endmodule + + +module Sub1; + +wire [7:0] Value; + +Sub2 SubMod2(Value); + +defparam SubMod2.Width = 8; + +initial begin + #1; + $display(""Value = %h"", Value); + if (Value === 8\'hff) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule + + +module Sub2(Out); + +parameter Width = 4; + +output [Width-1:0] Out; + +assign Out = {Width{1\'b1}}; + +endmodule +" +"`begin_keywords ""1364-2005"" +module top; + reg [31:0] var; + + initial begin + $monitor(var); + var = 0; + repeat (60) begin + #1 var = $urandom_range(16,0); +// #1 var = $urandom_range(4294967295,0); +// #1 var = $urandom_range(-1,0); + end + end +endmodule +`end_keywords +" +"/* + * This program is explicitly placed in the public domain for any uses + * whatsoever. + */ + +module TestMultiplier(); + + reg clk; + initial begin + clk = 0; + forever #0.5 clk = ~clk; + end + + reg[5:0] left, right; + wire[2:0] exp; + Multiplier mul(clk, left, right, exp); + + parameter ONE = {3\'b011, 3\'b0}; // 1.000 * 2**(3 - bias of 3) == 1.000 + + always @ (posedge clk) begin + left = ONE; + right = ONE; + + #10 + + if (exp !== 3\'b011) + $display(""FAIL: expected %b, got %b"", + 3\'b011, exp); + else + $display(""PASSED""); + + $finish(); + end +endmodule + + +/** + * A little bit of an incomplete floating-point multiplier. In/out format is + * [5:3] specify biased exponent (and hidden bit), [2:0] specify fraction. + * + * @param left[5:0], right[5:0] + * values being multiplied + * @param exp[2:0] + * exponent from product of left and right when put in the floating-point + * format of left/right + */ +module Multiplier(clk, + left, right, + exp); + input clk; + input[5:0] left, right; + + output[2:0] exp; + reg[2:0] exp; + + + // IMPLEMENTATION + + wire signed[2:0] expl = left[5:3] - 3; + wire signed[2:0] expr = right[5:3] - 3; + + /** Sum of unbiased exponents in operands. */ + reg signed[3:0] sumExp; + + + always @ (posedge clk) begin + + + + + sumExp <= (expl + expr) < -2 // why can\'t I move -2 to the right-hand side? + + ? -3 + : expl + expr; + + exp[2:0] <= sumExp + 3; + end +endmodule +" +"module top; + initial begin: b_label + $display(""PASSED""); + end: b_label + + initial fork:fj_label + join:fj_label + + initial fork:fja_label + join_any:fja_label + + initial fork:fjn_label + join_none:fjn_label + + task t_label; + endtask: t_label + + task twa_label(input arg); + endtask: twa_label + + function fn_label; + input arg; + endfunction: fn_label + + function fa_label(input in); + endfunction: fa_label + +endmodule:top + +macromodule extra; + parameter add_inv = 1; + reg a; + wire y, yb; + pbuf dut(y, a); + + if (add_inv) begin: g_label + pinv dut2(yb, y); + end: g_label + +endmodule: extra + +package pkg; +endpackage: pkg + +program pgm; + class foo; + endclass: foo +endprogram: pgm + +primitive pbuf (out, in); + output out; + input in; + table + 0 : 0; + 1 : 1; + endtable +endprimitive: pbuf + +primitive pinv (output out, input in); + table + 0 : 1; + 1 : 0; + endtable +endprimitive: pinv +" +"`timescale 10ns/1ps + +module main; + logic [1:0] counter = 2\'b00; + logic clk = 1\'b0; + + initial forever #1 clk <= ~clk; + + always @(posedge clk) begin + counter <= counter + 2\'d1; + + unique case (counter) + 2\'d0: $display(""case 0""); + 2\'d1: $display(""case 1""); + 2\'d3: $display(""case 3""); + endcase // priority case (counter) + + if (counter == 2\'d3) begin + $display(""PASSED""); + $finish(0); + end + end +endmodule +" +"module ts_pad ( + inout wire pad, + input wire oe, + input wire op +); + +assign pad = oe ? op : 1\'bz; + +endmodule + +module test(); + +wire bus0; +wire bus1; + +reg oe1 = 1\'b0; +reg oe2 = 1\'b0; +reg oe3 = 1\'b0; +reg oe4 = 1\'b0; +reg oe5 = 1\'b0; +reg oe6 = 1\'b0; + +wire op1 = 1\'b0; +wire op2 = 1\'b1; +wire op3 = 1\'b1; +wire op4 = 1\'b0; +wire op5 = 1\'bx; +wire op6 = 1\'bx; + +ts_pad pad1(bus0, oe1, op1); +ts_pad pad2(bus1, oe2, op2); + +ts_pad pad3(bus0, oe3, op3); +ts_pad pad4(bus1, oe4, op4); + +bufif1(bus0, op5, oe5); +bufif1(bus1, op6, oe6); + +integer multi; +integer forced; +integer countD; +integer count0; +integer count1; +integer countX; + +reg failed = 0; + +task check_results; + +input integer expected_multi; +input integer expected_forced; +input integer expected_countD; +input integer expected_count0; +input integer expected_count1; +input integer expected_countX; + +begin + $write(""multi = %0d "", multi); + if (multi !== expected_multi) failed = 1; + if (expected_forced != -1) begin + $write(""forced = %0d "", forced); + if (forced !== expected_forced) failed = 1; + end + if (expected_countD != -1) begin + $write(""countD = %0d "", countD); + if (countD !== expected_countD) failed = 1; + end + if (expected_count0 != -1) begin + $write(""count0 = %0d "", count0); + if (count0 !== expected_count0) failed = 1; + end + if (expected_count1 != -1) begin + $write(""count1 = %0d "", count1); + if (count1 !== expected_count1) failed = 1; + end + if (expected_countX != -1) begin + $write(""countX = %0d "", countX); + if (countX !== expected_countX) failed = 1; + end + $write(""\ +""); +end + +endtask + +initial begin + #1; + multi = $countdrivers(bus0, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + multi = $countdrivers(bus1, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + $display(""""); + + oe1 = 1\'b1; + #1; + multi = $countdrivers(bus0, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(bus1, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + $display(""""); + + oe2 = 1\'b1; + #1; + multi = $countdrivers(bus0, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(bus1, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + $display(""""); + + oe3 = 1\'b1; + #1; + multi = $countdrivers(bus0, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(bus1, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + $display(""""); + + oe4 = 1\'b1; + #1; + multi = $countdrivers(bus0, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(bus1, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + $display(""""); + + oe5 = 1\'b1; + #1; + multi = $countdrivers(bus0, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(bus1, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + $display(""""); + + oe6 = 1\'b1; + #1; + multi = $countdrivers(bus0, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(bus1, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + $display(""""); + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module main; + + function [7:0] add; + input [7:0] a, b; + + reg [8:0] tmp; + begin +\t tmp = a + b; +\t if (tmp < 9\'h100) +\t add = tmp; +\t else +\t add = 8\'hff; + end + endfunction // add + + reg[7:0] out; + initial begin + + out = 1? add(8,9) : 0; + + if (out !== 8\'d17) begin +\t $display(""FAILED -- out = %b"", out); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"// A global timeprecision and local time units. + +timeprecision 10ps; + +module gtp_ltu1; + timeunit 1ns; +endmodule + +module gtp_ltu2; + timeunit 1us; +endmodule + +`timescale 1s/1s +module check3; + +initial begin + $printtimescale(gtp_ltu1); + $printtimescale(gtp_ltu2); +end + +endmodule +" +"// Check variable initialisation in constant functions. +module constfunc8(); + +function real uninitialised_r(input dummy); + real value; + uninitialised_r = value; +endfunction + +function [7:0] uninitialised_2(input dummy); + reg bool [5:0] value; + uninitialised_2 = {1\'b1, value, 1\'b1}; +endfunction + +function [7:0] uninitialised_4(input dummy); + reg [5:0] value; + uninitialised_4 = {1\'b1, value, 1\'b1}; +endfunction + +localparam result_r = uninitialised_r(0); +localparam result_2 = uninitialised_2(0); +localparam result_4 = uninitialised_4(0); + +reg failed; + +initial begin + failed = 0; + + $display(""%0g"", result_r); + if (result_r != 0.0) failed = 1; + + $display(""%b"", result_2); + if (result_2 !== 8\'b10000001) failed = 1; + + $display(""%b"", result_4); + if (result_4 !== 8\'b1xxxxxx1) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module main; + + localparam int int_lparm = 11; + parameter int int_param = 10; + int\t\t int_var; + + initial begin + if (int_lparm != 11) begin +\t $display(""FAILED: int_lparm=%b"", int_lparm); +\t $finish; + end + + if ($bits(int_lparm) != 32) begin +\t $display(""FAILED: $bits(int_lparm) = %d"", $bits(int_lparm)); +\t $finish; + end + + if (int_param != 10) begin +\t $display(""FAILED: int_param=%b"", int_param); +\t $finish; + end + + if ($bits(int_param) != 32) begin +\t $display(""FAILED: $bits(int_param) = %d"", $bits(int_param)); +\t $finish; + end + + int_var = int_param; + if (int_var != 10) begin +\t $display(""FAILED: int_var=%b"", int_var); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"module automatic_events3(); + +reg [1:0] Source; + +initial begin + Source[0] = 1\'b0; + forever begin + #20 Source[0] = 1\'b1; + #20 Source[0] = 1\'b0; + end +end + +initial begin + Source[1] = 1\'b0; + #15; + forever begin + #10 Source[1] = 1\'bx; + #10 Source[1] = 1\'b1; + #10 Source[1] = 1\'bx; + #10 Source[1] = 1\'b0; + end +end + +task automatic ReportPosEdge0; + +begin + @(posedge Source[0]); + $display(""Time %t : Source[0] rise"", $time); +end + +endtask + +task automatic ReportNegEdge0; + +begin + @(negedge Source[0]); + $display(""Time %t : Source[0] fall"", $time); +end + +endtask + +task automatic ReportAnyEdge0; + +time t; + +begin + @(Source[0]) t = $time; + #1 $display(""Time %t : Source[0] edge"", t); +end + +endtask + +task automatic ReportPosEdge1; + +begin + @(posedge Source[1]); + $display(""Time %t : Source[1] rise"", $time); +end + +endtask + +task automatic ReportNegEdge1; + +begin + @(negedge Source[1]); + $display(""Time %t : Source[1] fall"", $time); +end + +endtask + +task automatic ReportAnyEdge1; + +time t; + +begin + @(Source[1]) t = $time; + #1 $display(""Time %t : Source[1] edge"", t); +end + +endtask + +initial begin + #1; + fork + repeat(2) ReportPosEdge0; + repeat(2) ReportNegEdge0; + repeat(4) ReportAnyEdge0; + + repeat(4) ReportPosEdge1; + repeat(4) ReportNegEdge1; + repeat(8) ReportAnyEdge1; + join + $finish(0); +end + +endmodule +" +"module main; + + reg [3:0] cond; + reg [2:0] t; + + always @* + case (cond&4\'b1110) + \'h0: t = 7; + \'h2: t = 6; + \'h4: t = 5; + \'h6: t = 4; + \'h8: t = 3; + \'ha: t = 2; + \'hc: t = 1; + \'he: t = 0; + endcase + + integer i; + initial begin + + for (i = 0 ; i < 8 ; i = i + 1) begin +\t cond = i << 1; +\t #1 if (t !== (7 - i)) begin +\t $display(""FAILED -- i=%d, cond=%b, t=%b"", i, cond, t); +\t $finish; +\t end + end + + $display(""PASSED""); + end + +endmodule // main +" +"// Test implicit casts during module input assignments. + +`ifdef __ICARUS__ + `define SUPPORT_REAL_NETS_IN_IVTEST + `define SUPPORT_TWO_STATE_NETS_IN_IVTEST +`endif + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +module cp_r(output wire real dst, + input wire real src); + assign dst = src; +endmodule +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +module cp_u2s(output wire bit unsigned [3:0] dst, + input wire bit unsigned [3:0] src); + assign dst = src; +endmodule + +module cp_s2s(output wire bit signed [3:0] dst, + input wire bit signed [3:0] src); + assign dst = src; +endmodule + +module cp_u2l(output wire bit unsigned [11:0] dst, + input wire bit unsigned [11:0] src); + assign dst = src; +endmodule + +module cp_s2l(output wire bit signed [11:0] dst, + input wire bit signed [11:0] src); + assign dst = src; +endmodule +`endif + +module cp_u4s(output wire logic unsigned [3:0] dst, + input wire logic unsigned [3:0] src); + assign dst = src; +endmodule + +module cp_s4s(output wire logic signed [3:0] dst, + input wire logic signed [3:0] src); + assign dst = src; +endmodule + +module cp_u4l(output wire logic unsigned [11:0] dst, + input wire logic unsigned [11:0] src); + assign dst = src; +endmodule + +module cp_s4l(output wire logic signed [11:0] dst, + input wire logic signed [11:0] src); + assign dst = src; +endmodule + +module implicit_cast(); + +real src_r; + +bit unsigned [7:0] src_u2; +bit signed [7:0] src_s2; + +logic unsigned [7:0] src_u4; +logic signed [7:0] src_s4; + +logic unsigned [7:0] src_ux; +logic signed [7:0] src_sx; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +wire real dst1_r; +wire real dst2_r; +wire real dst3_r; +wire real dst4_r; +wire real dst5_r; +wire real dst6_r; +wire real dst7_r; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +wire bit unsigned [3:0] dst1_u2s; +wire bit unsigned [3:0] dst2_u2s; +wire bit unsigned [3:0] dst3_u2s; +wire bit unsigned [3:0] dst4_u2s; +wire bit unsigned [3:0] dst5_u2s; +wire bit unsigned [3:0] dst6_u2s; +wire bit unsigned [3:0] dst7_u2s; + +wire bit signed [3:0] dst1_s2s; +wire bit signed [3:0] dst2_s2s; +wire bit signed [3:0] dst3_s2s; +wire bit signed [3:0] dst4_s2s; +wire bit signed [3:0] dst5_s2s; +wire bit signed [3:0] dst6_s2s; +wire bit signed [3:0] dst7_s2s; + +wire bit unsigned [11:0] dst1_u2l; +wire bit unsigned [11:0] dst2_u2l; +wire bit unsigned [11:0] dst3_u2l; +wire bit unsigned [11:0] dst4_u2l; +wire bit unsigned [11:0] dst5_u2l; +wire bit unsigned [11:0] dst6_u2l; +wire bit unsigned [11:0] dst7_u2l; + +wire bit signed [11:0] dst1_s2l; +wire bit signed [11:0] dst2_s2l; +wire bit signed [11:0] dst3_s2l; +wire bit signed [11:0] dst4_s2l; +wire bit signed [11:0] dst5_s2l; +wire bit signed [11:0] dst6_s2l; +wire bit signed [11:0] dst7_s2l; +`endif + +wire logic unsigned [3:0] dst1_u4s; +wire logic unsigned [3:0] dst2_u4s; +wire logic unsigned [3:0] dst3_u4s; +wire logic unsigned [3:0] dst4_u4s; +wire logic unsigned [3:0] dst5_u4s; +wire logic unsigned [3:0] dst6_u4s; +wire logic unsigned [3:0] dst7_u4s; + +wire logic signed [3:0] dst1_s4s; +wire logic signed [3:0] dst2_s4s; +wire logic signed [3:0] dst3_s4s; +wire logic signed [3:0] dst4_s4s; +wire logic signed [3:0] dst5_s4s; +wire logic signed [3:0] dst6_s4s; +wire logic signed [3:0] dst7_s4s; + +wire logic unsigned [11:0] dst1_u4l; +wire logic unsigned [11:0] dst2_u4l; +wire logic unsigned [11:0] dst3_u4l; +wire logic unsigned [11:0] dst4_u4l; +wire logic unsigned [11:0] dst5_u4l; +wire logic unsigned [11:0] dst6_u4l; +wire logic unsigned [11:0] dst7_u4l; + +wire logic signed [11:0] dst1_s4l; +wire logic signed [11:0] dst2_s4l; +wire logic signed [11:0] dst3_s4l; +wire logic signed [11:0] dst4_s4l; +wire logic signed [11:0] dst5_s4l; +wire logic signed [11:0] dst6_s4l; +wire logic signed [11:0] dst7_s4l; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +cp_r cp1_r(dst1_r, src_r); +cp_r cp2_r(dst2_r, src_u2); +cp_r cp3_r(dst3_r, src_s2); +cp_r cp4_r(dst4_r, src_u4); +cp_r cp5_r(dst5_r, src_s4); +cp_r cp6_r(dst6_r, src_ux); +cp_r cp7_r(dst7_r, src_sx); +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +cp_u2s cp1_u2s(dst1_u2s, src_r); +cp_u2s cp2_u2s(dst2_u2s, src_u2); +cp_u2s cp3_u2s(dst3_u2s, src_s2); +cp_u2s cp4_u2s(dst4_u2s, src_u4); +cp_u2s cp5_u2s(dst5_u2s, src_s4); +cp_u2s cp6_u2s(dst6_u2s, src_ux); +cp_u2s cp7_u2s(dst7_u2s, src_sx); + +cp_s2s cp1_s2s(dst1_s2s, src_r); +cp_s2s cp2_s2s(dst2_s2s, src_u2); +cp_s2s cp3_s2s(dst3_s2s, src_s2); +cp_s2s cp4_s2s(dst4_s2s, src_u4); +cp_s2s cp5_s2s(dst5_s2s, src_s4); +cp_s2s cp6_s2s(dst6_s2s, src_ux); +cp_s2s cp7_s2s(dst7_s2s, src_sx); + +cp_u2l cp1_u2l(dst1_u2l, src_r); +cp_u2l cp2_u2l(dst2_u2l, src_u2); +cp_u2l cp3_u2l(dst3_u2l, src_s2); +cp_u2l cp4_u2l(dst4_u2l, src_u4); +cp_u2l cp5_u2l(dst5_u2l, src_s4); +cp_u2l cp6_u2l(dst6_u2l, src_ux); +cp_u2l cp7_u2l(dst7_u2l, src_sx); + +cp_s2l cp1_s2l(dst1_s2l, src_r); +cp_s2l cp2_s2l(dst2_s2l, src_u2); +cp_s2l cp3_s2l(dst3_s2l, src_s2); +cp_s2l cp4_s2l(dst4_s2l, src_u4); +cp_s2l cp5_s2l(dst5_s2l, src_s4); +cp_s2l cp6_s2l(dst6_s2l, src_ux); +cp_s2l cp7_s2l(dst7_s2l, src_sx); +`endif + +cp_u4s cp1_u4s(dst1_u4s, src_r); +cp_u4s cp2_u4s(dst2_u4s, src_u2); +cp_u4s cp3_u4s(dst3_u4s, src_s2); +cp_u4s cp4_u4s(dst4_u4s, src_u4); +cp_u4s cp5_u4s(dst5_u4s, src_s4); +cp_u4s cp6_u4s(dst6_u4s, src_ux); +cp_u4s cp7_u4s(dst7_u4s, src_sx); + +cp_s4s cp1_s4s(dst1_s4s, src_r); +cp_s4s cp2_s4s(dst2_s4s, src_u2); +cp_s4s cp3_s4s(dst3_s4s, src_s2); +cp_s4s cp4_s4s(dst4_s4s, src_u4); +cp_s4s cp5_s4s(dst5_s4s, src_s4); +cp_s4s cp6_s4s(dst6_s4s, src_ux); +cp_s4s cp7_s4s(dst7_s4s, src_sx); + +cp_u4l cp1_u4l(dst1_u4l, src_r); +cp_u4l cp2_u4l(dst2_u4l, src_u2); +cp_u4l cp3_u4l(dst3_u4l, src_s2); +cp_u4l cp4_u4l(dst4_u4l, src_u4); +cp_u4l cp5_u4l(dst5_u4l, src_s4); +cp_u4l cp6_u4l(dst6_u4l, src_ux); +cp_u4l cp7_u4l(dst7_u4l, src_sx); + +cp_s4l cp1_s4l(dst1_s4l, src_r); +cp_s4l cp2_s4l(dst2_s4l, src_u2); +cp_s4l cp3_s4l(dst3_s4l, src_s2); +cp_s4l cp4_s4l(dst4_s4l, src_u4); +cp_s4l cp5_s4l(dst5_s4l, src_s4); +cp_s4l cp6_s4l(dst6_s4l, src_ux); +cp_s4l cp7_s4l(dst7_s4l, src_sx); + +bit failed; + +initial begin + failed = 0; + + src_r = -7; + src_u2 = 7; + src_s2 = -7; + src_u4 = 7; + src_s4 = -7; + src_ux = 8\'bx0z00111; + src_sx = 8\'bx0z00111; + + #1; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST + $display(""cast to real""); + $display(""%g"", dst1_r); if (dst1_r != -7.0) failed = 1; + $display(""%g"", dst2_r); if (dst2_r != 7.0) failed = 1; + $display(""%g"", dst3_r); if (dst3_r != -7.0) failed = 1; + $display(""%g"", dst4_r); if (dst4_r != 7.0) failed = 1; + $display(""%g"", dst5_r); if (dst5_r != -7.0) failed = 1; + $display(""%g"", dst6_r); if (dst6_r != 7.0) failed = 1; + $display(""%g"", dst7_r); if (dst7_r != 7.0) failed = 1; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST + $display(""cast to small unsigned bit""); + $display(""%d"", dst1_u2s); if (dst1_u2s !== 4\'d9) failed = 1; + $display(""%d"", dst2_u2s); if (dst2_u2s !== 4\'d7) failed = 1; + $display(""%d"", dst3_u2s); if (dst3_u2s !== 4\'d9) failed = 1; + $display(""%d"", dst4_u2s); if (dst4_u2s !== 4\'d7) failed = 1; + $display(""%d"", dst5_u2s); if (dst5_u2s !== 4\'d9) failed = 1; + $display(""%d"", dst6_u2s); if (dst6_u2s !== 4\'d7) failed = 1; + $display(""%d"", dst7_u2s); if (dst7_u2s !== 4\'d7) failed = 1; + + $display(""cast to small signed bit""); + $display(""%d"", dst1_s2s); if (dst1_s2s !== -4\'sd7) failed = 1; + $display(""%d"", dst2_s2s); if (dst2_s2s !== 4\'sd7) failed = 1; + $display(""%d"", dst3_s2s); if (dst3_s2s !== -4\'sd7) failed = 1; + $display(""%d"", dst4_s2s); if (dst4_s2s !== 4\'sd7) failed = 1; + $display(""%d"", dst5_s2s); if (dst5_s2s !== -4\'sd7) failed = 1; + $display(""%d"", dst6_s2s); if (dst6_s2s !== 4\'sd7) failed = 1; + $display(""%d"", dst7_s2s); if (dst7_s2s !== 4\'sd7) failed = 1; + + $display(""cast to large unsigned bit""); + $display(""%d"", dst1_u2l); if (dst1_u2l !== 12\'d4089) failed = 1; + $display(""%d"", dst2_u2l); if (dst2_u2l !== 12\'d7) failed = 1; + $display(""%d"", dst3_u2l); if (dst3_u2l !== 12\'d4089) failed = 1; + $display(""%d"", dst4_u2l); if (dst4_u2l !== 12\'d7) failed = 1; + $display(""%d"", dst5_u2l); if (dst5_u2l !== 12\'d4089) failed = 1; + $display(""%b"", dst6_u2l); if (dst6_u2l !== 12\'b000000000111) failed = 1; + $display(""%b"", dst7_u2l); if (dst7_u2l !== 12\'b000000000111) failed = 1; + + $display(""cast to large signed bit""); + $display(""%d"", dst1_s2l); if (dst1_s2l !== -12\'sd7) failed = 1; + $display(""%d"", dst2_s2l); if (dst2_s2l !== 12\'sd7) failed = 1; + $display(""%d"", dst3_s2l); if (dst3_s2l !== -12\'sd7) failed = 1; + $display(""%d"", dst4_s2l); if (dst4_s2l !== 12\'sd7) failed = 1; + $display(""%d"", dst5_s2l); if (dst5_s2l !== -12\'sd7) failed = 1; + $display(""%b"", dst6_s2l); if (dst6_s2l !== 12\'b000000000111) failed = 1; + $display(""%b"", dst7_s2l); if (dst7_s2l !== 12\'b000000000111) failed = 1; +`endif + + $display(""cast to small unsigned logic""); + $display(""%d"", dst1_u4s); if (dst1_u4s !== 4\'d9) failed = 1; + $display(""%d"", dst2_u4s); if (dst2_u4s !== 4\'d7) failed = 1; + $display(""%d"", dst3_u4s); if (dst3_u4s !== 4\'d9) failed = 1; + $display(""%d"", dst4_u4s); if (dst4_u4s !== 4\'d7) failed = 1; + $display(""%d"", dst5_u4s); if (dst5_u4s !== 4\'d9) failed = 1; + $display(""%d"", dst6_u4s); if (dst6_u4s !== 4\'d7) failed = 1; + $display(""%d"", dst7_u4s); if (dst7_u4s !== 4\'d7) failed = 1; + + $display(""cast to small signed logic""); + $display(""%d"", dst1_s4s); if (dst1_s4s !== -4\'sd7) failed = 1; + $display(""%d"", dst2_s4s); if (dst2_s4s !== 4\'sd7) failed = 1; + $display(""%d"", dst3_s4s); if (dst3_s4s !== -4\'sd7) failed = 1; + $display(""%d"", dst4_s4s); if (dst4_s4s !== 4\'sd7) failed = 1; + $display(""%d"", dst5_s4s); if (dst5_s4s !== -4\'sd7) failed = 1; + $display(""%d"", dst6_s4s); if (dst6_s4s !== 4\'sd7) failed = 1; + $display(""%d"", dst7_s4s); if (dst7_s4s !== 4\'sd7) failed = 1; + + $display(""cast to large unsigned logic""); + $display(""%d"", dst1_u4l); if (dst1_u4l !== 12\'d4089) failed = 1; + $display(""%d"", dst2_u4l); if (dst2_u4l !== 12\'d7) failed = 1; + $display(""%d"", dst3_u4l); if (dst3_u4l !== 12\'d4089) failed = 1; + $display(""%d"", dst4_u4l); if (dst4_u4l !== 12\'d7) failed = 1; + $display(""%d"", dst5_u4l); if (dst5_u4l !== 12\'d4089) failed = 1; + $display(""%b"", dst6_u4l); if (dst6_u4l !== 12\'b0000x0z00111) failed = 1; + $display(""%b"", dst7_u4l); if (dst7_u4l !== 12\'bxxxxx0z00111) failed = 1; + + $display(""cast to large signed logic""); + $display(""%d"", dst1_s4l); if (dst1_s4l !== -12\'sd7) failed = 1; + $display(""%d"", dst2_s4l); if (dst2_s4l !== 12\'sd7) failed = 1; + $display(""%d"", dst3_s4l); if (dst3_s4l !== -12\'sd7) failed = 1; + $display(""%d"", dst4_s4l); if (dst4_s4l !== 12\'sd7) failed = 1; + $display(""%d"", dst5_s4l); if (dst5_s4l !== -12\'sd7) failed = 1; + $display(""%b"", dst6_s4l); if (dst6_s4l !== 12\'b0000x0z00111) failed = 1; + $display(""%b"", dst7_s4l); if (dst7_s4l !== 12\'bxxxxx0z00111) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module test(); + + string str1 = ""abcd""; + string str2 = ""efgh""; + + typedef logic [31:0] vector; + + vector data[1:0]; + + initial begin + data[0] = vector\'(str1); + data[1] = vector\'(str2); + $display(""%s %s"", data[0], data[1]); + if (data[0] === ""abcd"" && data[1] === ""efgh"") + $display(""PASSED""); + else + $display(""FAILED""); + end + +endmodule +" +"module top; + wire [15:0] number =16\'h20; + wire shift_cmp = (number == (1 << 5)); + + initial begin + #1; // Make sure things are settled. + if (shift_cmp === 1\'b1) $display(""PASSED""); + else $display(""FAILED, got %b expected 1\'b1"", shift_cmp); + end +endmodule +" +"// Eleven basic tests in here: +// 1. longint must be initialised before any initial or always block +// 2. assignments to (unsigned) longint with random numbers +// 3. assignments to (unsigned) longint with random values including X and Z +// 4. converting unsigned 64-bit integer time to unsigned longint +// 5. converting signed integers to unsigned longint +// 6. converting 64-bit integers including X and Z states to unsigned longint +// 7. trying unsigned sums (procedural, function, task and module) +// 8. trying unsigned mults (procedural, function and task) +// 9. trying relational operators +// 10. smaller signed numbers to unsigned longint (signed extension) +// 11. trying some concatenations from bytes, shortints, ints to longints + +module mu_add (input longint unsigned a, b, output longint unsigned sc, ss); + assign sc = a + b; + always @(a, b) ss = a + b; +endmodule + +module main; + parameter N_REPS = 500; // repetition with random numbers + parameter XZ_REPS = 500; // repetition with \'x \'z values + parameter MAX8 = 256; + parameter MAX16 = 65536; + parameter LEN = 64; + // variables used as golden references + reg unsigned [LEN-1:0] ar; // holds numbers + reg unsigned [LEN-1:0] ar_xz; // holds \'x and/or \'z in random positions + reg unsigned [LEN-1:0] ar_expected; + reg unsigned [LEN-1:0] ui; // unsigned 64-bit integer + reg signed [LEN/2-1:0] slice; + + // type assumed to be tested before hand + byte unsigned pt1, pt2; + shortint unsigned ps1, ps2; + int unsigned pv1, pv2; + + // types to be tested + longint unsigned bu; // holds numbers + longint unsigned bu_xz; // \'x and \'z are attempted on this + longint unsigned bresult; // hold results from sums and mults + longint unsigned mcaresult; // wired to a module instance + longint unsigned mabresult; // also wired to a module instance + + + integer i; + + // continuous assigments + // type LHS type RHS + // --------- --------- + // longint 4-value logic + assign bu = ar; + assign bu_xz = ar_xz; + + // module instantiation + mu_add duv (.a(bu), .b(bu_xz), .sc(mcaresult), .ss(mabresult) ); + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if (bu !== 64\'b0 || bu_xz != 64\'b0 || bresult !== 64\'b0 || mcaresult !== 64\'b0 || mabresult !== 64\'b0) + begin + $display (""FAILED - time zero initialisation incorrect: %b %b"", bu, bu_xz); + $finish; + end + // driving longint type with unsigned random numbers from a variable + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = { {$random}, {$random} }; + #1; + if (bu !== ar) + begin + $display (""FAILED - incorrect assigment to int: %b"", bu); + $finish; + end + end + # 1; + // attempting to drive variables having \'x \'z values into type unsigned longint + // \'x \'z injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + ar = { {$random}, {$random} }; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0 + begin + $display (""FAILED - incorrect assigment to longint (when \'x \'z): %b"", bu); + $finish; + end + end + // converting unsigned 64-bit integers (time) to unsigned longint + // this should pass trivially + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ui = { {$random}, {$random} }; + #1; + force bu = ui; + #1; + if (bu !== ui) + begin + $display (""FAILED - incorrect assignment from 64-bit integer to longint: %b"", bu); + $finish; + end + end + release bu; + // converting signed integers to unsigned ints + // keeping the same bit representation is expected + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ui = { {$random}, {$random} }; + #1; + force bu = -ui; + #1; + if (-bu !== ui) + begin + $display (""FAILED - incorrect assignment from 64-bit signed integer to longint: %d mismatchs %d"", bu, -ui); + $finish; + end + end + release bu; + // converting integers having \'x \'z values into type unsigned longint + // \'x \'z injections (Section 4.3.2 of IEEE 1850 LRM) + // coercion to zero expected + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + ui = { {$random}, {$random} }; + ar_xz = xz_inject (ui); + ui = ar_xz; + ar_expected = xz_expected (ar_xz); + #1; + force bu_xz = ui; + #1; + if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0 + begin + $display (""FAILED - incorrect conversion from 64-bit integer (with \'x \'z) to longint: %b mismatchs %b"", bu_xz, ar_expected); + $finish; + end + end + release bu_xz; + // trying unsigned sums + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = { {$random}, {$random} }; + ar_xz = { {$random}, {$random} }; + #1; + bresult = bu + bu_xz; + #1; + if ( bresult !== u_sum(ar, ar_xz) ) + begin + $display (""FAILED - incorrect addition of unsigned longints: %0d mismatchs %0d"", bresult, u_sum(ar, ar_xz)); + $finish; + end + // invoking longint sum function + if ( fu_sum (bu, bu_xz) !== u_sum(ar, ar_xz) ) + begin + $display (""FAILED - incorrect addition of unsigned longint in function""); + $finish; + end + // invoking longint sum task + tu_sum (bu, bu_xz, bresult); + if ( bresult !== u_sum(ar, ar_xz) ) + begin + $display (""FAILED - incorrect addition of unsigned longint in task: %0d mismatchs %0d"", bresult, u_sum(ar, ar_xz)); + $finish; + end + // checking longint sum from module + if ( mcaresult !== u_sum(ar, ar_xz) || mabresult !== u_sum(ar, ar_xz)) + begin + $display (""FAILED - incorrect addition of unsigned longtint from module""); + $finish; + end + end + // trying unsigned mults + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = { {$random} % 32\'d65536, {$random} % 32\'d32768 }; + ar_xz = { {$random} % 32\'d32768, {$random} % 32\'d65536 }; + #1; + bresult = bu * bu_xz; // truncated mult + #1; + if ( bresult !== uh_mul(ar, ar_xz) ) + begin + $display (""FAILED - incorrect multiplication of unsigned longints: %0d mismatchs %0d"", bresult, uh_mul(ar, ar_xz)); + $finish; + end + #1; + pv1 = {$random}; + pv2 = {$random}; + #1; + bresult = pv1 * pv2; // longint = int x int + #1; + if ( bresult !== u_mul(pv1, pv2) ) + begin + $display (""FAILED - incorrect multiplication of unsigned longints for int inputs""); + $finish; + end + // invoking longint mult function (int*int) + if ( fu_mul (pv1, pv2) !== u_mul(pv1, pv2) ) + begin + $display (""FAILED - incorrect product of unsigned ints for a function returning unsigned longint""); + $finish; + end + // invoking longint mult task (int*int) + tu_mul (pv1, pv2, bresult); + if ( bresult !== u_mul(pv1, pv2) ) + begin + $display (""FAILED - incorrect product of unsigned int in task returning unsigned longint""); + $finish; + end + end + // trying relational operators + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = { {$random}, {$random} }; + ar_xz = { {$random}, {$random} }; + #1; + if ( (bu < bu_xz ) != (ar < ar_xz) ) + begin + $display (""FAILED - incorrect \'less than\' on unsigned longints""); + $finish; + end + if ( (bu <= bu_xz ) != (ar <= ar_xz) ) + begin + $display (""FAILED - incorrect \'less than or equal\' on unsigned longints""); + $finish; + end + if ( (bu > bu_xz ) != (ar > ar_xz) ) + begin + $display (""FAILED - incorrect \'greater than\' on unsigned longints""); + $finish; + end + if ( (bu >= bu_xz ) != (ar >= ar_xz) ) + begin + $display (""FAILED - incorrect \'greater than or equal\' than on unsigned longints""); + $finish; + end + if ( (bu == bu_xz ) != (ar == ar_xz) ) + begin + $display (""FAILED - incorrect \'equal to\' on unsigned longints""); + $finish; + end + if ( (bu != bu_xz ) != (ar != ar_xz) ) + begin + $display (""FAILED - incorrect \'not equal to\' on unsigned ints""); + $finish; + end + end + # 1; + // signed small number to unsigned shorint + for (i = 0; i < N_REPS; i = i+1) + begin + #1; + slice = $random % \'h7fff_ffff; + force bu = slice; + ar = slice; + #1; + if (bu !== ar) + begin + $display (""FAILED - incorrect signed extend to unsigned longint""); + $finish; + end + end + release bu; + // trying concatenations (and replication) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + pt1 = {$random} % MAX8; + pt2 = {$random} % MAX8; + #1; + bresult = { {4{pt1}}, {4{pt2}} }; + #1; + if ( bresult[63:56] !== pt1 || bresult[55:48] !== pt1 || bresult[47:40] !== pt1 || bresult[39:32] !== pt1 || + bresult[31:24] !== pt2 || bresult[23:16] !== pt2 || bresult[15:8] !== pt2 || bresult[7:0] !== pt2) + begin + $display (""FAILED - incorrect concatenation and replication of bytes into unsigned longints""); + $finish; + end + #1; + ps1 = {$random} % MAX16; + ps2 = {$random} % MAX16; + #1; + bresult = { {2{ps1}}, {2{ps2}} }; + #1; + if ( bresult[63:48] !== ps1 || bresult[47:32] !== ps1 || bresult[31:16] !== ps2 || bresult[15:0] !== ps2) + begin + $display (""FAILED - incorrect concatenation and replication of shortint into unsigned long ints""); + $finish; + end + #1; + pv1 = {$random}; + pv2 = {$random}; + #1; + bresult = { pv1, pv2 }; + #1; + if ( bresult[63:32] !== pv1 || bresult[31:0] !== pv2) + begin + $display (""FAILED - incorrect concatenation and replication of int into unsigned longints""); + $finish; + end + end + #1; + $display(""PASSED""); + end + + // this returns X and Z states into bit random positions for a value + function [LEN-1:0] xz_inject (input unsigned [LEN-1:0] value); + integer i, k; + time temp; + begin + temp = {$random, $random}; + for (i=0; i> 3; + $write(""Calculated: %b\ +Actually in mem: %b\ +"",((ram_temp & 8\'h08) >> 3), +mem); + if (mem !== 1\'b1) begin +\t $display(""FAILED == mem = %b"", mem); +\t $finish; + end + + $display(""PASSED""); + $finish; + end + +endmodule +" +"// Copyright (c) 2002\tMichael Ruff (mruff at chiaro.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +module lvl2; + reg r; + time t; + event e; + integer i; + + task t_my; +\tr = 1'b0; + endtask + + function f_my; +\tinput in; + begin +\tf_my = !in; + end + endfunction + + initial begin: init +\tt_my; +\tr = f_my(r); +\tr = f_my(i); +\tr = f_my(t); +\t->e; + end +endmodule + +module lvl1; + lvl2 lvl2(); +endmodule + +module top0; + reg r; + time t; + event e; + integer i; + + task t_my; +\tr = 1'b0; + endtask + + function f_my; +\tinput in; + begin +\tf_my = !in; + end + endfunction + + initial begin: init +\tt_my; +\tr = f_my(r); +\tr = f_my(i); +\tr = f_my(t); +\t->e; + end + + lvl1 lvl1_0(); + lvl1 lvl1_1(); +endmodule + + +module top1; + initial begin: init +\t$test; + end +endmodule +" +"module main(); + parameter INIT_00 = 32\'hffffffff; + reg [17:0] t; + reg [8:0] c; + reg error ; + initial begin + error = 0; + c = 0; + $display(""%b"",INIT_00[c]); + c = 1; + $display(""%b"",INIT_00[c]); + + t = {17\'d0,INIT_00[0]}<<1; + if(t !== 17\'b0_0000_0000_0000_0010) + begin + $display(""FAILED - shift operation {17\'d0,INIT_00[0]}<<1; %b"",t); +\t error = 1; + end + else + $display(""%b"",t); + c = 0; + t = {17\'d0,INIT_00[c]}<<1; + if(t !== 17\'b0_0000_0000_0000_0010) + begin + $display(""FAILED - shift operation {17\'d0,INIT_00[c]}<<1 %b"",t); +\t error = 1; + end + else + $display(""%b"",t); + c = 16; + t = {17\'d0,INIT_00[c]}<<1; + if(t !== 17\'b0_0000_0000_0000_0010) + begin + $display(""FAILED - shift operation {17\'d0,INIT_00[c]}<<1 %b"",t); +\t error = 1; + end + else + $display(""%b"",t); + + if(error == 1) + $display(""FAILED""); + else + $display(""PASSED""); + end +endmodule +" +"module top; + reg pass = 1\'b1; + + integer count; + reg clk = 0, in = 0; + reg result; + + always #10 clk = ~clk; + always #20 in = ~in; + + initial begin + count = 3; + result = repeat(count) @(posedge clk) in; + if ($simtime != 30 && result != 1\'b0) begin + $display(""Failed blocking repeat(3) at %0t, expected 1\'b0, got %b"", + $simtime, result); + pass = 1\'b0; + end + + #15; + count = 0; + result = repeat(count) @(posedge clk) in; + if ($simtime != 45 && result != 1\'b1) begin + $display(""Failed blocking repeat(0) at %0t, expected 1\'b1, got %b"", + $simtime, result); + pass = 1\'b0; + end + + #20; + count = -1; + result = repeat(count) @(posedge clk) in; + if ($simtime != 55 && result != 1\'b0) begin + $display(""Failed blocking repeat(0) at %0t, expected 1\'b0, got %b"", + $simtime, result); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + $finish; + end +endmodule +" +"/* + * This module instantiates the fa4 entity, which in turn + * instantiates other entities. This demonstrates hierarchical + * constructs in VHDL. + */ +module test; + +reg [3:0] a, b; +reg cin; + +wire [3:0] s; +wire cout; + +initial begin + cin = 0; + a = 4\'h2; + b = 4\'h3; +end + +initial begin + #1; + if (s !== 4\'h5) begin + $display(""Error in trivial sum""); + $finish; + end + $display (""PASSED""); +end + +fa4 duv (.c_i(cin), .va_i(a), .vb_i(b), .vs_o(s), .c_o(cout) ); + +endmodule // test +" +"module top; + reg pass = 1\'b1; + + parameter one = 1\'b1; + parameter zero = 1\'b0; + parameter udef = 1\'bx; + + real rl1 = one ? 4 : 4.5; // 4.0 + real rl2 = zero ? 4.0 : 5; // 5.0 + real rl3 = udef ? 6 : 6.0; // 6.0 + real rl4 = udef ? 7 : 7; // 7.0 + + initial begin + #1; + if (rl1 != 4.0) begin + $display(""FAILED: real expression one, expected 4.0, got %f"", rl1); + pass = 1\'b0; + end + + if (rl2 != 5.0) begin + $display(""FAILED: real expression two, expected 5.0, got %f)"", rl2); + pass = 1\'b0; + end + + if (rl3 != 6.0) begin + $display(""FAILED: real expression three, expected 6.0, got %f"", rl3); + pass = 1\'b0; + end + + if (rl4 != 7.0) begin + $display(""FAILED: real expression four, expected 7.0, got %f"", rl4); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"package MyPackage; + +typedef enum logic [1:0] { + A = 2\'b00, + B = 2\'b01, + C = 2\'b10 +} MyEnum; + +endpackage + +module test(); + +import MyPackage::*; + +localparam MyB = B; + +localparam C = 4; + +initial begin + $display(""B = %0d"", MyB); + $display(""C = %0d"", C); + if (MyB === 1 && C === 4) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module dut(input EN, input I, inout O); + +assign O = EN ? I : 1\'bz; + +specify + (I => O) = (2); + (EN *> O) = (4); +endspecify + +endmodule + +module test(); + +reg EN; +reg I; +tri O; + +pulldown(O); + +dut dut(EN, I, O); + +reg failed = 0; + +initial begin + $monitor($time,,EN,,I,,O); + EN = 0; + #4; + #0 if (O !== 0) failed = 1; + #1 I = 1; + #1 EN = 1; + #3; + #0 if (O !== 0) failed = 1; + #1; + #0 if (O !== 1) failed = 1; + + #1; + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"/* + * Copyright (c) 2000 Steven Wilson (stevew@homeaddress.org) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test looks for <= operation in a continuous assignment. + */ +module test; + +integer a; +integer b; +wire result; +integer error; + +assign result = (a <= b); + +initial + begin + a = 0; + b = 0; + error = 0; + #5 ; + if( result !== 1\'b1) + error =1; + a = 1; + #5; + if( result !== 1\'b0) + error =1; + + b = 1; + #5 ; + if( result !== 1\'b1) + error =1; + + a = 1001; + b = 1002; + #5 ; + if( result !== 1\'b1) + error =1; + a = 1003; + #5 ; + if( result !== 1\'b0) + error =1; + + if(error === 0) +\t $display(""PASSED""); + else +\t $display(""FAILED""); + end + +endmodule +" +"package pkg; + +typedef enum logic [3:0] { + ABC = 4\'h1 +} enum_t; + +typedef struct packed { + enum_t item; +} w_enum; + +typedef struct packed { + logic [3:0] item; +} w_logic; + +typedef union packed { + w_enum el1; + w_logic el2; +} foo_t; + +endpackage + +module main(); + +import pkg::*; + +foo_t val; + +initial begin + val.el1.item = ABC; + if (val.el2.item === 4\'h1) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module a; + initial begin : b + reg x; + end + initial fork : c + reg x; + join + + initial begin + a.b.x = 1\'b0; + a.c.x = 1\'b1; + $display(""PASSED""); + end +endmodule +" +"/* + * Copyright (c) 2000 Steve Wilson (stevew@home.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This checks bit select from/to vectors with odd bit arrangements. + */ +module test; + + reg [1:4] a; + reg [4:1] b; + integer i; + + initial begin + a = 4\'b1100; + for (i = 1 ; i <= 4 ; i = i + 1) +\tb[i] = a[i]; + + $display(""a=%b, b=%b"", a, b); + if (b !== 4\'b0011) begin +\t $display(""FAILED -- b == %b"", b); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule +" +"/* + * Copyright (c) 2000 Guy Hutchison (ghutchis@pacbell.net) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module xnor_test; + + reg onebit1, onebit2; + reg [3:0] small1, small2; + reg [15:0] large1, large2, large3, large4; + reg\t fail; + initial + begin + fail = 0; + + // single bit xnor testing + if ((1\'b0 ~^ 1\'b1) === 1\'b1) fail = 1; + if ((1\'b1 ^~ 1\'b0) === 1\'b1) fail = 1; + if ((1\'b0 ^~ 1\'b0) === 1\'b0) fail = 1; + if ((1\'b1 ~^ 1\'b1) === 1\'b0) fail = 1; + + // different sized operands (equality) + for (small1=0; small1 < 15; small1=small1+1) +\tbegin +\t large1 = { 12\'b0, small1 }; + +\t large2 = small1 ~^ large1; +\t if (large2 !== {16{1\'b1}}) fail = 1; +\t large2 = large1 ^~ small1; +\t if (large2 !== {16{1\'b1}}) fail = 1; +\tend + + // random test + // assumes +, &, |, and ~ work correctly + for (large1 = 0; large1 < 1000; large1=large1+1) +\tbegin +\t large2 = large1 + 1511; // prime number + +\t large3 = large1 ^~ large2; +\t large4 = (large1 & large2) | (~large1 & ~large2); + +\t if (large3 !== large4) +\t begin +\t fail = 1; +\t $display (""Pattern failed: %h != %h"", large3, large4); +\t end +\tend // for (large1 = 0; large1 < 1000; large1=large1+1) + + if (fail) +\t$display (""FAILED""); + else $display (""PASSED""); + $finish; + end // initial begin + +endmodule // xnor_test +" +"// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for \'range, \'left and \'right attributes in VHDL subprograms. + +module range_func_test; + +range_func dut(); + +initial begin + #1; + + if(dut.neg_out !== 4\'b0011) + begin + $display(""FAILED 1""); + $finish(); + end + + if(dut.rev_out !== 4\'b0001) + begin + $display(""FAILED 2""); + $finish(); + end + + $display(""PASSED""); +end +endmodule +" +"`begin_keywords ""1364-2005"" +module top; + reg pass = 1\'b1; + reg [1:0] var = 2\'b0; + real rvar = 0.0; + integer delay = 3; + + initial begin + // These should both happen at time 2. + var <= #2 2\'b01; + rvar <= #2 1.0; + #3 if (var !== 2\'b01) begin + $display(""FAILED: constant delay (bits)""); + pass = 1\'b0; + end + if (rvar != 1.0) begin + $display(""FAILED: constant delay (real)""); + pass = 1\'b0; + end + + // These should both happen at time 6. + var <= #(delay) 2\'b10; + rvar <= #(delay) 2.0; + #4 if (var !== 2\'b10) begin + $display(""FAILED: calculated delay (bits)""); + pass = 1\'b0; + end + if (rvar != 2.0) begin + $display(""FAILED: calculated delay (real)""); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +`end_keywords +" +"`timescale 1ns/1ns + +// Run this with -pRECURSIVE_MOD_LIMIT=5 to keep the output file small. +module sum_test; + reg clk; + wire [10:0] s; + + initial begin + clk = 0; + forever #10 clk = ~clk; + end + + sum #(5, 8) sum (clk, {8\'d10,8\'d20,8\'d30,8\'d40,8\'d50}, s); + + initial begin + $display(""Starting...""); + repeat (50) @(posedge clk); + $display(""sum = %d"",s); + if (s !== 150) + $display(""FAILED: expected 150, received %0d"",s); + else + $display(""PASSED""); + $finish; + end +endmodule + +module sum + #( + parameter n = 4, + parameter width = 8, + parameter log_n = $clog2(n) + ) + ( + input clk, + input [n*width-1:0]addends, + output reg [log_n+width-1:0] s + ); + + generate + // This does not terminate and should fail after 100 loops. + if (n==-1) + always @(*) s = addends; + else begin + wire [$clog2(n/2)+width-1:0] a1; + wire [$clog2(n-n/2)+width-1:0] a2; + sum #(n/2, width) s0 (clk, addends[(n/2)*width-1:0], a1); + sum #(n-n/2, width) s1 (clk, addends[n*width-1:(n/2)*width], a2); + always @(posedge clk) s <= a1 + a2; + end + endgenerate + +endmodule // sum +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate assign identifier = expression ; + +module main ; + +wire a; +wire [31:0] b; +wire [15:0] c; + +reg [31:0] val; +reg error; + +assign a = val [0];\t\t// Pull single bit +assign b = val;\t\t\t// full variable +assign c = val[31:16];\t\t// Top portion bit select + +initial + begin + error = 0; + if(a != 1\'bx) + begin + $display(""FAILED - 3.2A assign ident = expr""); + error = 1; + end + if(b != 32\'bx) + begin + $display(""FAILED - 3.2A assign ident = expr""); + error = 1; + end + if(c != 16\'bx) + begin + $display(""FAILED - 3.2A assign ident = expr""); + error = 1; + end + #1 ; + val = 32\'h87654321; + #1 ; + if(a != 1\'b1) + begin + $display(""FAILED - 3.2A assign ident = expr""); + error = 1; + end + if(b != 32\'h87654321) + begin + $display(""FAILED - 3.2A assign ident = expr""); + error = 1; + end + if(c != 16\'h8765) + begin + $display(""FAILED - 3.2A assign ident = expr""); + error = 1; + end + if(error == 0) + $display(""PASSED""); + + $finish ; + end + + +endmodule +" +"module top; + wire real result; + wire [63:0] bits; + real in; + + assign bits = $realtobits(in); + + // This generates incorrect code: + // The .net/real temporary is not needed. + // The .alias/real temporary is not needed. + // The .sfunc should connect directly to the ""results"" net. + // The .part is not needed and is causing a core dump. + // + // Once these are fixed it appears there is a concurrency issues + assign result = $bitstoreal(bits); + + initial begin + $monitor(result,, bits,, in); + + in = 0.0; + #1 in = 2.0; + end +endmodule +" +"// These don't do anything useful, but check for compiler errors. + +module test(); + +integer i; + +always begin + for (i = 0; i < 10; i = i + 1) ; +end + +always begin + repeat (1) ; +end + +always begin + while (1) ; +end + +always begin + do ; while (1); +end + +always begin + forever ; +end + +endmodule +" +" +module main; + + reg [1:0] D0, D1; + reg\t sel; + wire [1:0] Q; + + test_mux DUT(.\\S[1] (1\'b0), .\\S[0] (sel), +\t\t.\\D0[1] (D0[1]), .\\D0[0] (D0[0]), +\t\t.\\D1[1] (D1[1]), .\\D1[0] (D1[0]), +\t\t.\\Q[1] (Q[1]), .\\Q[0] (Q[0])); + + initial begin + D0 = \'b01; + D1 = \'b10; + sel = 0; + #1 ; + if (Q !== D0) begin +\t $display(""FAILED -- D0=%b, D1=%b, S=%b, Q=%b"", D0, D1, sel, Q); +\t $finish; + end + + sel = 1; + #1 ; + if (Q !== D1) begin +\t $display(""FAILED -- D0=%b, D1=%b, S=%b, Q=%b"", D0, D1, sel, Q); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"module main; + + reg [7:0] foo; + reg [7:0] bar; + + initial begin + foo = \'hff; + + if ($bits(foo) !== 8) begin +\t $display(""FAILED -- $bits(foo) = %d"", $bits(foo)); +\t $finish; + end + + if ($bits( 4\'(foo) ) !== 4) begin +\t $display(""FAILED -- $bits( 4\'(foo) ) = %d"", $bits( 4\'(foo) )); +\t $finish; + end + + bar = {4\'d0, 4\'(foo)}; + if (bar !== 8\'h0f) begin +\t $display(""FAILED -- foo=%b, bar=%b"", foo, bar); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"// This tests end labes (test should pass compilation) +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test (); + + // error counter + bit err = 0; + + initial + begin : dummy_label + if (!err) $display(""PASSED""); + end : dummy_label + +endmodule : test +" +"/* tern9.v + */ +module main; + + reg flag; + reg val; + wire test1 = flag? val : 1\'bx; + wire test2 = flag? 1\'b0 : 1\'bx; + wire test3 = flag? 1\'bx : val; + + initial begin + flag = 1; + val = 0; + + #1 if (test1 !== 1\'b0) begin +\t $display(""FAILED -- flag=%b, val=%b, test1=%b"", flag, val, test1); +\t $finish; + end + + if (test2 !== 1\'b0) begin +\t $display(""FAILED -- flag=%b, test2=%b"", flag, test2); +\t $finish; + end + + if (test3 !== 1\'bx) begin +\t $display(""FAILED -- flag=%b, test3=%b"", flag, test3); +\t $finish; + end + + val = 1; + + #1 if (test1 !== 1\'b1) begin +\t $display(""FAILED -- flag=%b, val=%b, test1=%b"", flag, val, test1); +\t $finish; + end + + val = 1\'bx; + + #1 if (test1 !== 1\'bx) begin +\t $display(""FAILED -- flag=%b, val=%b, test1=%b"", flag, val, test1); +\t $finish; + end + + val = 1\'bz; + + #1 if (test1 !== 1\'bz) begin +\t $display(""FAILED -- flag=%b, val=%b, test1=%b"", flag, val, test1); +\t $finish; + end + + flag = 0; + val = 0; + + #1 if (test1 !== 1\'bx) begin +\t $display(""FAILED -- flag=%b, val=%b, test1=%b"", flag, val, test1); +\t $finish; + end + + if (test2 !== 1\'bx) begin +\t $display(""FAILED -- flag=%b, test2=%b"", flag, test2); +\t $finish; + end + + if (test3 !== 1\'b0) begin +\t $display(""FAILED -- flag=%b, test3=%b"", flag, test3); +\t $finish; + end + + val = 1; + + #1 if (test1 !== 1\'bx) begin +\t $display(""FAILED -- flag=%b, val=%b, test1=%b"", flag, val, test1); +\t $finish; + end + + if (test3 !== 1\'b1) begin +\t $display(""FAILED -- flag=%b, test3=%b"", flag, test3); +\t $finish; + end + + val = 1\'bx; + + #1 if (test3 !== 1\'bx) begin +\t $display(""FAILED -- flag=%b, val=%b, test3=%b"", flag, val, test3); +\t $finish; + end + + val = 1\'bz; + + #1 if (test3 !== 1\'bz) begin +\t $display(""FAILED -- flag=%b, val=%b, test3=%b"", flag, val, test3); +\t $finish; + end + + $display(""PASSED""); + $finish; + end // initial begin + +endmodule +" +" +/* + * Generate a combinational adder of any width. The width parameter can + * be any integer value >0. The A and B inputs have WID bits, and the Q + * output has WID+1 bits to include the overflow. + */ +module addN + #(parameter WID = 4) + (input wire [WID-1:0] A, + input wire [WID-1:0] B, + output wire [WID:0] Q + /* */); + + wire [WID-1:0]\tCout; + + /* The least significant slice has no Cin */ + add1 U0 (.A(A[0]), .B(B[0]), .Cin(1'b0), .Q(Q[0]), .Cout(Cout[0])); + + /* Generate all the remaining slices */ + genvar i; + for (i = 1 ; i < WID ; i = i+1) begin : U + add1 Un (.A(A[i]), .B(B[i]), .Cin(Cout[i-1]), .Q(Q[i]), .Cout(Cout[i])); + end + + assign Q[WID] = Cout[WID-1]; + +endmodule // add + +/* + * This is a single-bit combinational adder used by the addH module + * above. + */ +module add1(input A, input B, input Cin, output reg Q, output reg Cout); + + always @* begin + Q = A ^ B ^ Cin; + Cout = A&B | A&Cin | B&Cin; + end + +endmodule // hadd +" +"`begin_keywords ""1364-2005"" +module generate_multi_loop(); + +reg [31:0] input_value; + +wire [31:0] output_value; + +generate + genvar i; + genvar j; + + for (i = 0; i < 4; i = i + 1) begin:byte + wire [7:0] byte_value; + + for (j = 0; j < 8; j = j + 1) begin:bit + wire bit_value; + + buf buffer(bit_value, input_value[i*8+j]); + + assign byte_value[j] = bit_value; + end + + assign output_value[i*8+7:i*8] = byte_value; + end +endgenerate + +initial begin + input_value = 32\'h12345678; + #1; + $write(""byte_value =""); + $write("" %b"", byte[3].byte_value); + $write("" %b"", byte[2].byte_value); + $write("" %b"", byte[1].byte_value); + $write("" %b"", byte[0].byte_value); + $write(""\ +""); + $write(""bit_value = ""); + $write(""%b"", byte[3].bit[7].bit_value); + $write(""%b"", byte[3].bit[6].bit_value); + $write(""%b"", byte[3].bit[5].bit_value); + $write(""%b"", byte[3].bit[4].bit_value); + $write(""%b"", byte[3].bit[3].bit_value); + $write(""%b"", byte[3].bit[2].bit_value); + $write(""%b"", byte[3].bit[1].bit_value); + $write(""%b"", byte[3].bit[0].bit_value); + $write("" ""); + $write(""%b"", byte[2].bit[7].bit_value); + $write(""%b"", byte[2].bit[6].bit_value); + $write(""%b"", byte[2].bit[5].bit_value); + $write(""%b"", byte[2].bit[4].bit_value); + $write(""%b"", byte[2].bit[3].bit_value); + $write(""%b"", byte[2].bit[2].bit_value); + $write(""%b"", byte[2].bit[1].bit_value); + $write(""%b"", byte[2].bit[0].bit_value); + $write("" ""); + $write(""%b"", byte[1].bit[7].bit_value); + $write(""%b"", byte[1].bit[6].bit_value); + $write(""%b"", byte[1].bit[5].bit_value); + $write(""%b"", byte[1].bit[4].bit_value); + $write(""%b"", byte[1].bit[3].bit_value); + $write(""%b"", byte[1].bit[2].bit_value); + $write(""%b"", byte[1].bit[1].bit_value); + $write(""%b"", byte[1].bit[0].bit_value); + $write("" ""); + $write(""%b"", byte[0].bit[7].bit_value); + $write(""%b"", byte[0].bit[6].bit_value); + $write(""%b"", byte[0].bit[5].bit_value); + $write(""%b"", byte[0].bit[4].bit_value); + $write(""%b"", byte[0].bit[3].bit_value); + $write(""%b"", byte[0].bit[2].bit_value); + $write(""%b"", byte[0].bit[1].bit_value); + $write(""%b"", byte[0].bit[0].bit_value); + $write(""\ +""); + if (output_value == input_value) + $display(""Test passed""); + else + $display(""Test FAILED""); +end + +endmodule +`end_keywords +" +"// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test real to integer conversion + +module vhdl_rtoi_testbench; + vhdl_rtoi dut(); + + initial begin + #1; // wait for the no_init signal assignment + + if (dut.a !== 2) begin + $display(""FAILED 1""); + $finish; + end + + if (dut.b !== 4) begin + $display(""FAILED 2""); + $finish; + end + + if (dut.c !== 5) begin + $display(""FAILED 3""); + $finish; + end + + if (dut.d !== 17) begin + $display(""FAILED 4""); + $finish; + end + + $display(""PASSED""); + end +endmodule +" +"module top; + reg pass = 1\'b1; + reg result; + + function freg; + input reg in; + freg = in; + endfunction + + function fnreg(input reg in); + fnreg = in; + endfunction + + task toreg; + output reg out; + input reg in; + out = in; + endtask + + task tnoreg(output reg out, input reg in); + out = in; + endtask + + task tioreg; + inout reg io; + io = 1\'b1; + endtask + + task tnioreg(inout reg io); + io = 1\'b0; + endtask + + initial begin + result = freg(1\'b1); + if (result !== 1\'b1) begin + $display(""FAILED: freg()""); + pass = 1\'b0; + end + + result = fnreg(1\'b0); + if (result !== 1\'b0) begin + $display(""FAILED: fnreg()""); + pass = 1\'b0; + end + + toreg(result, 1\'b1); + if (result !== 1\'b1) begin + $display(""FAILED: toreg()""); + pass = 1\'b0; + end + + tnoreg(result, 1\'b0); + if (result !== 1\'b0) begin + $display(""FAILED: tnoreg()""); + pass = 1\'b0; + end + + tioreg(result); + if (result !== 1\'b1) begin + $display(""FAILED: tioreg()""); + pass = 1\'b0; + end + + tnioreg(result); + if (result !== 1\'b0) begin + $display(""FAILED: tnioreg()""); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module top; + reg[63:0] a; + + initial begin + a = 64\'h7fe8000000000000; + // This used to fail because we printed floating point using + // the default buffer which was only 256 bytes long. To fix + // this the default size was changed to 512 bytes and this is + // increased when needed (%400.300f, etc.). + $display(""%6.3f"", $bitstoreal(a)); + $display(""PASSED""); + end +endmodule +" +"/* + * This test is based on PR#978. + * Check that user defined functions can have real-valued + * results, and that the result gets properly returned. + */ +module test(); + real m; + + function real dummy; + input b; + begin +\t dummy=2.5; + end + endfunction + + initial + begin +\tm=dummy(0); + +\tif (m != 2.5) begin +\t $display(""FAILED: return result is %f"", m); +\t $finish; +\tend + +\t$display(""PASSED""); + end + +endmodule +" +"module top; + // We expect bits for the zero or mone parameters. The + // big test must also be at least , but Icarus currently + // creates 48 bits. I personally think this is the correct behavior. + parameter zero = 0; + parameter mone = -1; + parameter big = \'hffffffffffff; + + parameter max = 2**16; // We will call this many bits unlimited. + reg pass; + integer idx; + + initial begin + pass = 1\'b1; + + /* + * Check with a bit select. + */ + $display(""Checking the size with a bit select.""); + $display(""------------------------------------""); + // Test to see how far a decimal 0 is extended. + begin: loop_zero + for (idx = 0; idx < max; idx = idx + 1) begin + if (zero[idx] !== 0) disable loop_zero; + end + end + if (idx != max) begin + $display(""The size of a decimal 0 parameter is %0d bits."", idx); + // Check that after the parameter is 1\'bx. + if (zero[idx] !== 1\'bx) begin + $display("" Failed: after bit must be 1\'bx, got %b."", zero[idx]); + pass = 1\'b0; + end + end else begin + $display(""The size of a decimal 0 parameter is unlimited.""); + end + // An unsized parameter must be at least 32 bits. + if (idx < 32) begin + $display("" Failed: unsized parameter must be >= 32 bits, got %0d."", idx); + pass = 1\'b0; + end + // Check that before the parameter is 1\'bx. + idx = -1; + if (zero[idx] !== 1\'bx) begin + $display("" Failed: before bit must be 1\'bx, got %b."", zero[idx]); + pass = 1\'b0; + end + // Check that an undefined index gives 1\'bx. + idx = \'bx; + if (zero[idx] !== 1\'bx) begin + $display("" Failed: undefined select must be 1\'bx, got %b."", zero[idx]); + pass = 1\'b0; + end + + // Test to see how far a decimal -1 is extended. + begin: loop_mone + for (idx = 0; idx < max; idx = idx + 1) begin + if (mone[idx] !== 1) disable loop_mone; + end + end + if (idx != max) begin + $display(""The size of a decimal -1 parameter is %0d bits."", idx); + // Check that after the parameter is 1\'bx. + if (mone[idx] !== 1\'bx) begin + $display("" Failed: after bit must be 1\'bx, got %b"", mone[idx]); + pass = 1\'b0; + end + end else begin + $display(""The size of a decimal -1 parameter is unlimited.""); + end + // An unsized parameter must be at least 32 bits. + if (idx < 32) begin + $display("" Failed: unsized parameter must be >= 32 bits, got %0d."", idx); + pass = 1\'b0; + end + // Check that before the parameter is 1\'bx. + idx = -1; + if (mone[idx] !== 1\'bx) begin + $display("" Failed: before bit must be 1\'bx, got %b."", mone[idx]); + pass = 1\'b0; + end + // Check that an undefined index gives 1\'bx. + idx = \'bx; + if (mone[idx] !== 1\'bx) begin + $display("" Failed: undefined select must be 1\'bx, got %b."", mone[idx]); + pass = 1\'b0; + end + + // Check to see if a parameter can be more than 32 bits (I expect + // unlimited or 48 bits). If they exist the first 48 bits must be 1 + // any remaining bits are 0. + begin: loop_big + for (idx = 0; idx < max; idx = idx + 1) begin + if (big[idx] !== (idx < 48)) disable loop_big; + end + end + if (idx != max) begin + $display(""The size of a big decimal parameter is %0d bits."", idx); + // Check that after the parameter is 1\'bx. + if (big[idx] !== 1\'bx) begin + $display("" Failed: after bit must be 1\'bx, got %b"", big[idx]); + pass = 1\'b0; + end + end else begin + $display(""The size of a big decimal parameter is unlimited.""); + end + // An unsized parameter must be at least 32 bits. + if (idx < 48) begin + $display("" Warning: 48 bit unsized parameter was truncated to %0d bits"", + idx); + end + if (idx < 32) begin + $display("" Failed: unsized parameter must be >= 32 bits, got %0d."", idx); + pass = 1\'b0; + end + // Check that before the parameter is 1\'bx. + idx = -1; + if (big[idx] !== 1\'bx) begin + $display("" Failed: before bit must be 1\'bx, got %b."", big[idx]); + pass = 1\'b0; + end + // Check that an undefined index gives 1\'bx. + idx = \'bx; + if (big[idx] !== 1\'bx) begin + $display("" Failed: undefined select must be 1\'bx, got %b."", big[idx]); + pass = 1\'b0; + end + + + /* + * Check with an indexed up select. + */ + $display(""""); + $display(""Checking the size with an indexed part select.""); + $display(""----------------------------------------------""); + // Test to see how far a decimal 0 is extended. + begin: loop_zero2 + for (idx = 0; idx < max; idx = idx + 1) begin + if (zero[idx+:1] !== 0) disable loop_zero2; + end + end + if (idx != max) begin + $display(""The size of a decimal 0 parameter is %0d bits."", idx); + // Check that after the parameter is 1\'bx. + if (zero[idx+:1] !== 1\'bx) begin + $display("" Failed: after bit must be 1\'bx, got %b"", zero[idx+:1]); + pass = 1\'b0; + end + end else begin + $display(""The size of a decimal 0 parameter is unlimited.""); + end + // An unsized parameter must be at least 32 bits. + if (idx < 32) begin + $display("" Failed: unsized parameter must be >= 32 bits, got %0d."", idx); + pass = 1\'b0; + end + // Check that before the parameter is 1\'bx. + idx = -1; + if (zero[idx+:1] !== 1\'bx) begin + $display("" Failed: before bit must be 1\'bx, got %b."", zero[idx+:1]); + pass = 1\'b0; + end + // Check that an undefined index gives 1\'bx. + idx = \'bx; + if (zero[idx+:1] !== 1\'bx) begin + $display("" Failed: undefined select must be 1\'bx, got %b."", zero[idx+:1]); + pass = 1\'b0; + end + + // Test to see how far a decimal -1 is extended. + begin: loop_mone2 + for (idx = 0; idx < max; idx = idx + 1) begin + if (mone[idx+:1] !== 1) disable loop_mone2; + end + end + if (idx != max) begin + $display(""The size of a decimal -1 parameter is %0d bits."", idx); + // Check that after the parameter is 1\'bx. + if (mone[idx+:1] !== 1\'bx) begin + $display("" Failed: after bit must be 1\'bx, got %b"", mone[idx+:1]); + pass = 1\'b0; + end + end else begin + $display(""The size of a decimal -1 parameter is unlimited.""); + end + // An unsized parameter must be at least 32 bits. + if (idx < 32) begin + $display("" Failed: unsized parameter must be >= 32 bits, got %0d."", idx); + pass = 1\'b0; + end + // Check that before the parameter is 1\'bx. + idx = -1; + if (mone[idx+:1] !== 1\'bx) begin + $display("" Failed: before bit must be 1\'bx, got %b."", mone[idx+:1]); + pass = 1\'b0; + end + // Check that an undefined index gives 1\'bx. + idx = \'bx; + if (mone[idx+:1] !== 1\'bx) begin + $display("" Failed: undefined select must be 1\'bx, got %b."", mone[idx+:1]); + pass = 1\'b0; + end + + // Check to see if a parameter can be more than 32 bits (I expect + // unlimited or 48 bits). If they exist the first 48 bits must be 1 + // any remaining bits are 0. + begin: loop_big2 + for (idx = 0; idx < max; idx = idx + 1) begin + if (big[idx+:1] !== (idx < 48)) disable loop_big2; + end + end + if (idx != max) begin + $display(""The size of a big decimal parameter is %0d bits."", idx); + // Check that after the parameter is 1\'bx. + if (big[idx+:1] !== 1\'bx) begin + $display(""Failed: after bit must be 1\'bx, got %b"", big[idx+:1]); + pass = 1\'b0; + end + end else begin + $display(""The size of a big decimal parameter is unlimited.""); + end + // An unsized parameter must be at least 32 bits. + if (idx < 48) begin + $display("" Warning: 48 bit unsized parameter was truncated to %0d bits"", + idx); + end + if (idx < 32) begin + $display("" Failed: unsized parameter must be >= 32 bits, got %0d."", idx); + pass = 1\'b0; + end + // Check that before the parameter is 1\'bx. + idx = -1; + if (big[idx+:1] !== 1\'bx) begin + $display("" Failed: before bit must be 1\'bx, got %b."", big[idx+:1]); + pass = 1\'b0; + end + // Check that an undefined index gives 1\'bx. + idx = \'bx; + if (big[idx+:1] !== 1\'bx) begin + $display("" Failed: undefined select must be 1\'bx, got %b."", big[idx+:1]); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +" +module main; + + localparam AMAX = 7; + localparam SHIFT = 4; + byte foo [AMAX:0]; + byte unsigned foo_u [AMAX:0]; + int idx; + + initial begin + for (idx = 0 ; idx <= AMAX ; idx = idx+1) begin +\t foo[idx] = idx - SHIFT; +\t foo_u[idx] = idx; + end + + for (idx = 0 ; idx <= AMAX ; idx = idx+1) begin +\t if (idx < SHIFT && foo[idx] > 0) begin +\t $display(""FAIL -- foo[%0d] = %0d (not signed?)"", idx, foo[idx]); +\t $finish; +\t end +\t if (foo[idx] != (idx-SHIFT)) begin +\t $display(""FAIL -- foo[%0d] = %0d"", idx, foo[idx]); +\t $finish; +\t end +\t if (foo_u[idx] != idx) begin +\t $display(""FAIL -- foo_u[%0d] = %0d"", idx, foo[idx]); +\t $finish; +\t end + end + + $display(""PASSED""); + $finish; + end // initial begin + +endmodule // main +" +"// Check a global timeprecision that is too large. +`resetall +timeunit 1ns/10ns; +module gtp_large; +endmodule + +" +" +/* + * This demonstrates a basic dynamic array + */ +module main; + + longint foo[]; + int idx; + + initial begin + if (foo.size() != 0) begin +\t $display(""FAILED -- foo.size()=%0d, s.b. 0"", foo.size()); +\t $finish; + end + + foo = new[10]; + if (foo.size() != 10) begin +\t $display(""FAILED -- foo.size()=%0d, s.b. 10"", foo.size()); +\t $finish; + end + + for (idx = 0 ; idx < foo.size() ; idx += 1) begin +\t foo[idx] = idx; + end + + $display(""foo[7] = %d"", foo[7]); + if (foo[7] != 7) begin +\t $display(""FAILED -- foo[7] = %0d (s.b. 7)"", foo[7]); +\t $finish; + end + + $display(""foo[9] = %d"", foo[9]); + if (foo[9] != 9) begin +\t $display(""FAILED -- foo[9] = %0d (s.b. 9)"", foo[9]); +\t $finish; + end + + for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin +\t if (foo[idx%10] != (idx%10)) begin +\t $display(""FAILED -- foo[%0d%%10] = %0d"", idx, foo[idx%10]); +\t $finish; +\t end + end + + foo.delete(); + if (foo.size() != 0) begin +\t $display(""FAILED -- foo.size()=%0d (after delete: s.b. 0)"", foo.size()); +\t $finish; + end + + $display(""PASSED""); + end +endmodule // main +" +"module example(); + +reg [7:0] scale, a, b; + +wire [7:0] c; + +function [7:0] scaled; + +input [7:0] value; + +begin + scaled = value * scale; +end + +endfunction + +assign c = scaled(a) + scaled(b); + +initial begin + #1 a = 2; + #1 scale = 2; + #1 b = 3; + #1 $display(c); + if (c === 10) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +" +// output ports may be uwire, or even a variable, if wire-ness +// or variable-ness are not explicitly stated. + +typedef struct packed { + logic [1:0] a; + logic [1:0] b; +} sample_t; + +module main; + sample_t dst; + logic [1:0] src_a, src_b; + + DUT dut(.out(dst), .a(src_a), .b(src_b)); + + initial begin + src_a = 1; + src_b = 2; + + #1 /* wait for dst */; + if (dst.a !== 1) begin +\t $display(""FAILED -- dst.a=%b (dst=%b)"", dst.a, dst); +\t $finish; + end + + if (dst.b !== 2) begin +\t $display(""FAILED -- dst.b=%b (dst=%b)"", dst.b, dst); +\t $finish; + end + + $display(""PASSED""); + end +endmodule // main + +module DUT(output sample_t out, +\t input logic [1:0] a, b); + + always @* begin + out.a = a; + out.b = b; + end + +endmodule +" +"/* + * Copyright (c) 2003 The ASIC Group (www.asicgroup.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module mult58s(input [4:0] a, input signed [7:0] b, output signed [15:0] p); + +wire signed [12:0] pt; + +wire signed [5:0] ta; + +assign ta = a; +assign pt = b * ta; + +assign p=pt; + +endmodule + + +module test_mult; + +integer a,b, prod; + +wire [15:0] p; +mult58s dut(a[4:0], b[7:0], p); + +initial begin + for(a = 0; a < (1<<5); a=a+1 ) + for(b=-127; b<128; b=b+1) + begin + prod = a * b; + #1 if(p !== prod[15:0]) begin + $display(""Error Miscompare with a=%h, b=%h expect = %0d (%h) acutal = %h"", +\t\t\t\t\ta[4:0], b[7:0], prod, prod[15:0], p); + $finish; + end + + end + + $display(""PASSED""); +end + +endmodule +" +"// Copyright (c) 2006 Stephen Williams +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module main; + + parameter foo = 4\'b0101; + parameter str = ""String Text""; + + initial begin + $listparams(""foo"", ""str""); + end + +endmodule // main +" +"/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program checks that some basics of real value support work. + */ +module main; + + realtime x; + real a3, a4; + + initial begin + a3 = 0.3; + a4 = 0.4; + + x = 2 * a4 + a3; + + $display(""a3 = %f, a4 = %f, x = %f"", a3, a4, x); + if (x > 1.1001) begin +\t $display(""FAILED""); +\t $finish; + end + if (x < 1.0999) begin +\t $display(""FAILED""); +\t $finish; + end + + $display(""PASSED""); + end // initial begin +endmodule // main +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue = @ event_identifier boolean_expression +// D: There is a dependency here between this and event keyword and -> + +module main ; + +reg [3:0] value1 ; +event event_ident ; + +initial +begin + # 5 -> event_ident ; +end + +initial + begin + if(value1 !== 4\'bxxxx) +\t$display(""FAILED - always reg_lvalue = @ event_identifier boolean_expression\ +""); + #10 ; + if(value1 != 4\'b1) +\t$display(""FAILED - always reg_lvalue = @ event_identifier boolean_expression\ +""); + else + begin + $display(""PASSED\ +""); + $finish ; + end + end + +always value1 = @ event_ident 1\'b1 && 1\'b1 ; + + +endmodule +" +"module top(); + +reg foo; + +tri [1:0] a; + +assign a[0] = foo; + +tran(a[0], a[1]); + +initial begin + foo = 1\'b1; + #1 $display(""%b"", a); + if (a === 2\'b11) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module main; + + reg a, b; + + trior net; + + assign net = a; + assign net = b; + + initial begin + a = \'b0; + b = \'b0; + #1 if (net !== 1\'b0) begin +\t $display(""FAILED -- a=%b, b=%b, net=%b"", a, b, net); +\t $finish; + end + + a = \'b0; + b = \'b1; + #1 if (net !== 1\'b1) begin +\t $display(""FAILED -- a=%b, b=%b, net=%b"", a, b, net); +\t $finish; + end + + a = \'b0; + b = \'bx; + #1 if (net !== 1\'bx) begin +\t $display(""FAILED -- a=%b, b=%b, net=%b"", a, b, net); +\t $finish; + end + + a = \'b0; + b = \'bz; + #1 if (net !== 1\'b0) begin +\t $display(""FAILED -- a=%b, b=%b, net=%b"", a, b, net); +\t $finish; + end + + a = \'b1; + b = \'b1; + #1 if (net !== 1\'b1) begin +\t $display(""FAILED -- a=%b, b=%b, net=%b"", a, b, net); +\t $finish; + end + + a = \'b1; + b = \'bx; + #1 if (net !== 1\'b1) begin +\t $display(""FAILED -- a=%b, b=%b, net=%b"", a, b, net); +\t $finish; + end + + a = \'b1; + b = \'bz; + #1 if (net !== 1\'b1) begin +\t $display(""FAILED -- a=%b, b=%b, net=%b"", a, b, net); +\t $finish; + end + + a = \'bx; + b = \'bx; + #1 if (net !== 1\'bx) begin +\t $display(""FAILED -- a=%b, b=%b, net=%b"", a, b, net); +\t $finish; + end + + a = \'bx; + b = \'bz; + #1 if (net !== 1\'bx) begin +\t $display(""FAILED -- a=%b, b=%b, net=%b"", a, b, net); +\t $finish; + end + + a = \'bz; + b = \'bz; + #1 if (net !== 1\'bz) begin +\t $display(""FAILED -- a=%b, b=%b, net=%b"", a, b, net); +\t $finish; + end + + $display(""PASSED""); + end +endmodule // main +" +"/* + * Copyright (c) 2005 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* tern8.v + * This tests types. + */ +module main; + + reg b; + real c, d; + wire real a = b ? c : d; + + initial begin + + b <= 0; + c <= 1.0; + d <= 2.0; + #1 if (a != 2.0) begin +\t $display(""FAILED (1)""); +\t $finish; + end + + b <= 1; + #1 if (a != 1.0) begin +\t $display(""FAILED (2)""); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"module test; + reg fail = 1\'b0; + reg [3:0] in = 4\'b0; + wire [3:0] bus = in; + wire [3:0] val = bus; // to check the propagated value is correct + + initial begin + // Check the initial value. + #1 if (val !== 4\'b0) begin + $display(""FAILED: initial value, got %b, expected 0000."", val); + fail = 1\'b1; + end + + // Check a bit froce and verify a normal bit assign does nothing. + #1 force bus[0] = 1\'b1; + #1 in[0] = 1\'bz; + #1 if (val !== 4\'b0001) begin + $display(""FAILED: force of bus[0], got %b, expected 0001."", val); + fail = 1\'b1; + end + + // Check a part force. + #1 force bus[3:2] = 2\'b11; + #1 if (val !== 4\'b1101) begin + $display(""FAILED: force of bus[3:2], got %b, expected 1101."", val); + fail = 1\'b1; + end + + // Check that we can change an unforced bit. + #1 in[1] = 1\'bz; + #1 if (val !== 4\'b11z1) begin + $display(""FAILED: assignment of bus[1], got %b, expected 11z1."", val); + fail = 1\'b1; + end + #1 in[1] = 1\'b0; + + // Check a bit release. + #1 release bus[0]; + #1 if (val !== 4\'b110z) begin + $display(""FAILED: release of bus[0], got %b, expected 110z."", val); + fail = 1\'b1; + end + + // Check a part release. + #1 release bus[3:2]; + #1 if (val !== 4\'b000z) begin + $display(""FAILED: release of bus[3:2], got %b, expected 000z."", val); + fail = 1\'b1; + end + + // Check a force from the upper thread bits (>= 8). + #1 force bus[2:1] = 2\'bx1; + #1 if (val !== 4\'b0x1z) begin + $display(""FAILED: force of bus[2:1], got %b, expected 0x1z."", val); + fail = 1\'b1; + end + + if (!fail) $display(""PASSED""); + end +endmodule +" +"`ifdef __ICARUS__ + `define SUPPORT_TWO_STATE_NETS_IN_IVTEST +`endif + +module test(); + +int x2; +int z2; + +function int y2(int x); +endfunction + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +wire int w2 = y2(x2); +`else +wire integer w2 = 0; +`endif + +integer x4; +integer z4; + +function integer y4(integer x); +endfunction + +wire integer w4 = y4(x4); + +initial begin + #1; + $display(w2); + z2 = y2(x2); + $display(z2); + $display(w4); + z4 = y4(x4); + $display(z4); + if (w2 === 0 && z2 === 0 && w4 === \'bx && z4 === \'bx) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module eqne(output wire eq1, output wire ne1, +\t output wire eq2, output wire ne2, +\t output wire eq5, output wire ne5, +\t input wire [7:0] x, input wire [7:0] y); + + assign\t eq1 = x[0] == y[0]; + assign\t ne1 = x[0] != y[0]; + assign\t eq2 = x[1:0] == y[1:0]; + assign\t ne2 = x[1:0] != y[1:0]; + assign\t eq5 = x[4:0] == y[4:0]; + assign\t ne5 = x[4:0] != y[4:0]; + +endmodule // eqne +" +"`define ADDR_DEC_W\t 8 // Number of bits used to decode. +`define ADDR_DEVICE0\t `ADDR_DEC_W\'h10 // Device 0 located at address 20xx_xxxxh +`define ADDR_DEVICE1\t `ADDR_DEC_W\'h1F // Device 1 located at address 20xx_xxxxh + +module top ( ) ; + +// Instantiation of the module +// +child_module #(`ADDR_DEC_W, `ADDR_DEVICE0, `ADDR_DEVICE1) my_module ( ); + +initial begin + #1 ; +end + +endmodule + +module child_module ( ); + +// Parameters: +parameter\t\tdec_addr_w = 4 ; +parameter\t\tt0_addr = 4\'d0 ; +parameter\t\tt1_addr = 4\'d0 ; + +// Instantiation of the grandchild module +// +grandchild_module #(dec_addr_w, t0_addr, t1_addr) my_grandchild_module ( ); + +initial begin + $display (""CHILD parameters are: %h %h %h"", dec_addr_w, t0_addr, t1_addr) ; +end + +endmodule + +module grandchild_module ( ); + +// Parameters: +parameter\t\tdec_addr_w = 4 ; +parameter\t\tt0_addr = 4\'d0 ; +parameter\t\tt1_addr = 4\'d0 ; + +initial begin + $display (""GRANDCHILD parameters are: %h %h %h"", dec_addr_w, t0_addr, t1_addr) ; +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate the ? operator + + +module main; + +reg globvar; + +reg [3:0] bvec; +reg [3:0] var1,var2,var3; +reg cond, a,b,out1,out2; +reg error; + +initial + begin + error = 0; + bvec = 4\'bzx10 ; + for(var1 = 0;var1 <= 4\'h3; var1 = var1+1) + begin + for(var2 = 0;var2 <= 4\'h3;var2 = var2+1) + begin + for(var3= 0; var3 <= 4\'h3;var3 = var3+1) + begin + + cond = bvec[var1]; + a = bvec[var2]; + b = bvec[var3]; + + out1 = cond ? a: b ; + + if(cond) + out2 = a ; + else + out2 = b; + + if(out1 != out2) + begin + $display(""FAILED - qmark2 - %b %b %b %b %b"", + cond,a,b,out1,out2); + error = 1; + end + end + end + end + if(error == 0) + $display(""PASSED""); + end + +endmodule // main +" +"module whoever_wrote_this_should_be_shot ( Q, D, G ); + output Q; + input D, G; + + wire Q_int; + + assign ( pull0, pull1 ) Q_int = Q_int; + + bufif1 buf_D ( Q_int, D, G ); + buf buf_Q ( Q, Q_int ); +endmodule + +module testbench; + wire Q; + reg D, G; + + whoever_wrote_this_should_be_shot uut ( Q, D, G ); + + initial begin + D = 1\'b0; + forever #5 D = ~ D; + end + + initial begin + G = 1\'b0; + forever #27 G = ~ G; + end + + initial begin + $monitor( $time,,,G,,,D,,,Q ); + + // time 28: G=1, D=1, Q=1 + #28 if (Q !== 1) begin +\t $display(""FAILED -- Q should be 1, is %b"", Q); +\t $finish; +\tend + + // time 31: G=1, D=0, Q=0 + #3 if (Q !== 0) begin +\t $display(""FAILED -- Q should be 0, is %b"", Q); +\t $finish; +\tend + + // time 51: G=1, D=0, Q=0 + #20 if (Q !== 0) begin +\t $display(""FAILED -- Q should be 0, is %b"", Q); +\t $finish; +\tend + + // time 56: G=0, D=1, Q=0 + #5 if (Q !== 0) begin +\t $display(""FAILED -- Q should be 0, is %b"", Q); +\t $finish; +\tend + + // time 82: G=1, D=0, Q=0 + #26 if (Q !== 0) begin +\t $display(""FAILED -- Q should be 0, is %b"", Q); +\t $finish; +\tend + + // time 86: G=1, D=1, Q=1 + #5 if (Q !== 1) begin +\t $display(""FAILED -- Q should be 1, is %b"", Q); +\t $finish; +\tend + + #1000 $display(""PASSED""); + $finish; + end +endmodule +" +"module copy(output [1:0] out, input [1:0] in); + +assign out = in; + +endmodule + +module top(); + +reg [2:0] r; +wire [0:0] i1; +wire [1:0] i2; +wire [2:0] i3; +wire [1:0] o1; +wire [1:0] o2; +wire [1:0] o3; + +assign i1 = r; +assign i2 = r; +assign i3 = r; + +copy copy1(o1, i1); +copy copy2(o2, i2); +copy copy3(o3, i3); + +reg failed; + +initial begin + failed = 0; + for (r = 0; r < 4; r = r + 1) begin + #1 $display(""%b : %b %b : %b %b : %b %b"", r[1:0], i1, o1, i2, o2, i3, o3); + if (o1 !== {1\'b0, r[0]}) failed = 1; + if (o2 !== r[1:0]) failed = 1; + if (o3 !== r[1:0]) failed = 1; + end + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module test; + reg [128:1] str [0:0]; + reg [31:0] idx; + + initial begin + str[0] = ""test_counter""; + idx = 0; + $write(""String is %s\ +"", str[0]); // This works. + $write(""String is %s\ +"", str[idx]); // This fails. + end +endmodule +" +"/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +module main; + + reg foo = 0; + + initial #10 foo = 1; + + initial #1 begin + if (foo !== 1\'b0) begin +\t $display(""FAILED -- foo before wait is %b"", foo); +\t $finish; + end + + // This wait without a statement has caused a few bugs. + wait (foo) ; + + if (foo !== 1\'b1) begin +\t $display(""FAILED -- foo after wait is %b"", foo); +\t $finish; + end + + if ($time != 10) begin +\t $display(""FAILED -- $time after wait is %t"", $time); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"// +// Copyright (c) 1999 Thomas Coonan (tcoonan@mindspring.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// **** Here\'s a simple, sequential multiplier. Very simple, unsigned.. +// Not very well tested, play with testbench, use at your own risk, blah blah blah.. +// + +// +// Unsigned 16-bit multiply (multiply two 16-bit inputs to get a 32-bit output) +// +// Present data and assert start synchronous with clk. +// Assert start for ONLY one cycle. +// Wait N cycles for answer (at most). Answer will remain stable until next start. +// You may use DONE signal as handshake. +// +// Written by tom coonan +// +module mult16 (clk, resetb, start, done, ain, bin, yout); +parameter N = 16; +input\t\t\tclk; +input\t\t\tresetb; +input\t\t\tstart; // Register the ain and bin inputs (they can change afterwards) +//input [N-1:0]\t\tain; +//input [N-1:0]\t\tbin; +//output [2*N-1:0]\tyout; +input [15:0]\t\tain; +input [15:0]\t\tbin; +output [31:0]\tyout; + +output\t\t\tdone; + +//reg [2*N-1:0]\t\ta; +//reg [N-1:0]\t\tb; +//reg [2*N-1:0]\t\tyout; +reg [31:0]\t\ta; +reg [15:0]\t\tb; +reg [31:0]\t\tyout; + +reg\t\tdone; + +always @(posedge clk or negedge resetb) begin + if (~resetb) begin + a <= 0; + b <= 0; + yout <= 0; + done <= 1\'b1; + end + else begin + // Load will register the input and clear the counter. + if (start) begin + a <= ain; + b <= bin; + yout <= 0; + done <= 0; + end + else begin + // Go until b is zero + if (~done) begin + if (b != 0) begin + // If \'1\' then add a to sum + if (b[0]) begin + yout <= yout + a; + end + b <= b >> 1; + a <= a << 1; + $display (""a = %h, b = %h, yout = %h"", a,b,yout); + end + else begin + done <= 1\'b1; + end + end + end + end +end +endmodule + + +module mul16; +reg clk, resetb, start; +reg [15:0] a; +reg [15:0] b; +wire [31:0] y; +wire done; + +mult16 mult16inst (clk, resetb, start, done, a, b, y); + +initial begin + clk = 0; + forever begin + #10 clk = ~clk; + end +end + +initial begin + resetb = 0; + #30 resetb = 1; +end + +integer num_errors; +parameter MAX_TRIALS = 10; + +initial begin +// $dumpfile (""multdiv.vcd""); +// $dumpvars (0,a); +// $dumpvars (0,b); +// $dumpvars (0,y); +// $dumpvars (0,resetb); +// $dumpvars (0,done); + num_errors = 0; + + #100; + + // Do a bunch of random multiplies + repeat (MAX_TRIALS) begin + test_multiply ($random, $random); + end + + // Special cases + test_multiply ($random, 1); + test_multiply (1, $random); + test_multiply ($random, 0); + test_multiply (0, $random); + + $display (""Done. %0d Errors"", num_errors); + if(num_errors == 0) + $display(""PASSED""); + #800; + $finish; +end + +task test_multiply; + input [15:0] aarg; + input [15:0] barg; + + integer expected_answer; + + begin + if (~done) begin + $display (""Multiplier is Busy!!""); + end + else begin + @(negedge clk); + start = 1; + a = aarg; + b = barg; + @(negedge clk) start = 0; + @(posedge done); + expected_answer = a*b; + $display (""%0d * %0d = %0h, Reality = %0h"", a, b, y, expected_answer); + if (y !== expected_answer) begin + $display ("" FAILED!""); + num_errors = num_errors + 1; + end + end + end +endtask + +endmodule +" +"// Check that the >> and >>> operators with unsigned values. +module top; + parameter py = 8\'b10101010 >> 3\'b101; + parameter pz = 8\'b10101010 >>> 3\'b101; + + reg passed; + reg [7:0] a; + reg [2:0] b; + wire [7:0] wy, wz; + reg [7:0] ry, rz; + + // Check CA code. + assign wy = a >> b; + assign wz = a >>> b; + + initial begin + passed = 1\'b1; + // Example vector + a = 8\'b10101010; + b = 3\'b101; + #1; + + // Check the parameter results. + if (py !== 8\'b00000101) begin + $display(""Failed param. >>, expected 8\'b00000101, got %b"", py); + passed = 1\'b0; + end + if (pz !== 8\'b00000101) begin + $display(""Failed param. >>>, expected 8\'b00000101, got %b"", pz); + passed = 1\'b0; + end + + // Check the procedural results. + ry = a >> b; + if (ry !== 8\'b00000101) begin + $display(""Failed procedural >>, expected 8\'b00000101, got %b"", ry); + passed = 1\'b0; + end + rz = a >>> b; + if (rz !== 8\'b00000101) begin + $display(""Failed procedural >>>, expected 8\'b00000101, got %b"", rz); + passed = 1\'b0; + end + + // Check the CA results. + if (wy !== 8\'b00000101) begin + $display(""Failed CA >>, expected 8\'b00000101, got %b"", wy); + passed = 1\'b0; + end + if (wz !== 8\'b00000101) begin + $display(""Failed CA >>>, expected 8\'b00000101, got %b"", wz); + passed = 1\'b0; + end + + if (passed) $display(""PASSED""); + end +endmodule +" +" +// This tests SystemVerilog packages. Make sure that typedef +// names work. + +package p1; + typedef struct packed { + bit [7:0] high; + bit [7:0] low; + } word_t; + + word_t word; +endpackage + +module main; + + import p1::word; + + initial begin + if ($bits(word) != 16) begin +\t $display(""FAILED -- $bits(p1::word) == %0d"", $bits(p1::word)); +\t $finish; + end + + word = \'haa55; + + if (word != \'haa55) begin +\t $display(""FAILED -- p1::word = %h"", word); +\t $finish; + end + + word.low = \'h66; + word.high = \'hbb; + if (word != \'hbb66 || word.low != 8\'h66) begin +\t $display(""FAILED -- p1::word = %h"", word); +\t $finish; + end + + $display(""PASSED""); + $finish; + end // initial begin +endmodule // main +" +"/* + * Based on PR#1024 + */ + +module test; + + initial begin + wait(1) ; /* This is weird, but legal. */ + $display(""PASSED""); + end +endmodule // test +" +"module counter(out, clk, reset); + + parameter WIDTH = 8; + + output [WIDTH-1 : 0] out; + input clk, reset; + + reg [WIDTH-1 : 0] out; + wire clk, reset; + +(* ivl_synthesis_on *) + always @(posedge clk) + out <= out + 1; + + always @(posedge reset) + assign out = 0; + + always @(negedge reset) + deassign out; +(* ivl_synthesis_off *) + +initial $display(""PASSED""); + +endmodule // counter +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate declared wire and implicit wires displayed. +// + + +// This circuit has 3 i/os and 3 implicit wires. Both should be +// present in vcd file?? +module xorckt (out,in0,in1); +input in0; +input in1; + +wire junk; + +nand #1 na1 (na1_out,in0,in1); +nand #1 na2 (na2_out,in0,na1_out); +nand #1 na3 (na3_out,in1,na1_out); +nand #1 na4 (out,na2_out,na3_out); + +assign junk = in0; + +endmodule + +module main; + +wire xout; +reg i1,i2; + +xorckt myckt (.out(xout),.in0(i1),.in1(i2)); + +initial + begin + $dumpfile(""work/test.vcd""); + $dumpvars(0,main.myckt); + i1 = 1\'b0; + i2 = 1\'b0; + #5; + $display(""%b xor %b = %b"",i1,i2,xout); + i1 = 1\'b1; + i2 = 1\'b0; + #5; + $display(""%b xor %b = %b"",i1,i2,xout); + i1 = 1\'b1; + i2 = 1\'b1; + #5; + $display(""%b xor %b = %b"",i1,i2,xout); + i1 = 1\'b0; + i2 = 1\'b1; + #5 ; + $display(""%b xor %b = %b"",i1,i2,xout); + end + +endmodule // main +" +"module automatic_events(); + +reg [5:1] any; + +integer i; + +initial begin + any = 5\'b00000; + #200; + for (i = 1; i <= 5; i = i + 1) begin + #10 any[i] = 1; + #10 any[i] = 0; + end +end + +task automatic report_events; + +input integer n; + +reg [5:1] pos; +reg [5:1] neg; + +integer i; +integer j; + +begin + #n; + pos = 5\'b00000; + neg = 5\'b00000; + fork + for (i = 1; i <= 5; i = i + 1) begin + #10 neg[i] = 1; + #10 pos[i] = 1; + #10 neg[i] = 0; + #10 pos[i] = 0; + end + for (j = 1; j <= 20; j = j + 1) begin + @( any[1] or posedge pos[1] or negedge neg[1] + or any[2] or posedge pos[2] or negedge neg[2] + or any[3] or posedge pos[3] or negedge neg[3] + or any[4] or posedge pos[4] or negedge neg[4] + or any[5] or posedge pos[5] or negedge neg[5] ); + #n $display(""task %0d triggered: %b %b %b %4d"", n, any, pos, neg, $time); + end + join +end + +endtask + +initial begin + fork + report_events(1); + report_events(2); + join + $finish(0); +end + +endmodule +" +"`timescale 1ns/100ps + +primitive udp_and( + output y, + input a, + input b +); + +table +//a b : y + 0 0 : 0 ; + 0 1 : 0 ; + 1 0 : 0 ; + 1 1 : 1 ; + x 0 : 0 ; + 0 x : 0 ; +endtable + +endprimitive + +module test(); + +reg a; +reg b; +wire y; + +udp_and #0.5 gate(y, a, b); + +reg failed = 0; + +initial begin + $monitor($realtime,,a,,b,,y); + a = 0; b = 0; + #0.6 if (y !== 1\'b0) failed = 1; + a = 1; b = 1; + #0.4 if (y !== 1\'b0) failed = 1; + #0.2 if (y !== 1\'b1) failed = 1; + a = 0; b = 1; + #0.4 if (y !== 1\'b1) failed = 1; + #0.2 if (y !== 1\'b0) failed = 1; + a = 1; b = 1; + #0.4 if (y !== 1\'b0) failed = 1; + #0.2 if (y !== 1\'b1) failed = 1; + a = 1; b = 0; + #0.4 if (y !== 1\'b1) failed = 1; + #0.2 if (y !== 1\'b0) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"`timescale 100ns/100ps +module dummy; + parameter [1:0] ipval = 2; +endmodule + +`timescale 1us/1ns + +module top; + parameter [1:0] ipval = 2; + parameter spval = ""Help""; + parameter rpval = 1.0; + event evt; + reg [1:0] rgval; + reg rgarr [2:0]; + wire [1:0] wval; + wire warr [2:0]; + integer ival; + real rval; + real rarr [2:0]; + time tval; + + initial begin:blk + $printtimescale(dummy); + $printtimescale(dummy.ipval); + // These should all print a timescale of 1us / 1ns. + $printtimescale; + $printtimescale(top.ipval); + /* This does not currently work because Icarus does not know how + * to keep the parameter reference in the part select. For now + * it just returns a constant which the runtime will complain + * does not have a vpiModule. */ +// $printtimescale(top.ipval[0]); + $printtimescale(top.spval); + /* The same goes here. */ +// $printtimescale(top.spval[0]); + $printtimescale(top.rpval); + $printtimescale(top.evt); + $printtimescale(top.rgval); + $printtimescale(top.rgval[0]); + $printtimescale(top.rgarr); + $printtimescale(top.rgarr[0]); + $printtimescale(top.wval); + $printtimescale(top.wval[0]); + $printtimescale(top.warr); + $printtimescale(top.warr[0]); + $printtimescale(top.ival); + $printtimescale(top.ival[1]); + $printtimescale(top.rval); + $printtimescale(top.rarr); + $printtimescale(top.rarr[0]); + $printtimescale(top.tval); + $printtimescale(top.blk); + $printtimescale(top.frk); + $printtimescale(top.tsk); + $printtimescale(top.fnc); + end + + initial fork:frk + $write(""""); + join + + task tsk; + begin + end + endtask + + function integer fnc; + input integer tmp; + fnc = 2 * tmp; + endfunction + +endmodule +" +"// This tests SystemVerilog packages +// +// This tests the elaboration infrastructure of packages in +// SystemVerilog. It actually covers a fair number of features, +// given the small size of the program: +// +// *) Parsing of package blocks and import statements +// *) Manage scope of names in package +// *) Actual references of imported names from packages. +// + +package pkg; + parameter int foo = 1; +endpackage + + +module test (); + + // import all from p1 + import pkg::*; + + initial begin + $display(""pkg::foo = %0d"", foo); + if (foo != 1) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""PASSED""); + end + +endmodule // test +" +"// deliberately empty +" +"/* + * Test support for multi-dimension unpacked arrays. + */ +module main; + + localparam ISIZE = 6; + localparam JSIZE = 8; + reg [7:0] array[0:ISIZE-1][0:JSIZE-1]; + + reg [3:0] idx, jdx; + integer count; + initial begin + // Load array contents. + for (idx = 0 ; idx < ISIZE ; idx = idx+1) begin +\t for (jdx = 0 ; jdx < JSIZE ; jdx = jdx+1) begin +\t array[idx][jdx] = {idx, jdx}; +\t end + end + + if (array[3][2] !== 8\'h32) begin +\t $display(""FAILED -- array[3][2] == %h"", array[3][2]); +\t $finish; + end + + for (count = 0 ; count < 4096 ; count = count+1) begin +\t idx = {$random} % ISIZE; +\t jdx = {$random} % JSIZE; +\t if (array[idx][jdx] !== {idx,jdx}) begin +\t $display(""FAILED -- array[%d][%d] == %h"", idx, jdx, array[idx][jdx]); +\t $finish; +\t end + end + + $display(""PASSED""); + $finish; + end // initial begin + +endmodule // main +" +"module top; + reg [1:0] lv, rv; + reg res, pass; + + initial begin + pass = 1\'b1; + + lv = 2\'b00; + rv = 2\'b00; + res = lv ==? rv; + if (res !== 1\'b1) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'b1"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b00; + rv = 2\'b01; + res = lv ==? rv; + if (res !== 1\'b0) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'b0"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b10; + rv = 2\'b00; + res = lv ==? rv; + if (res !== 1\'b0) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'b0"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b1x; + rv = 2\'b00; + res = lv ==? rv; + if (res !== 1\'b0) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'b0"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b0x; + rv = 2\'b00; + res = lv ==? rv; + if (res !== 1\'bx) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'bx"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b00; + rv = 2\'b0x; + res = lv ==? rv; + if (res !== 1\'b1) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'b1"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b01; + rv = 2\'b0x; + res = lv ==? rv; + if (res !== 1\'b1) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'b1"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b0z; + rv = 2\'b0x; + res = lv ==? rv; + if (res !== 1\'b1) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'b1"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b0x; + rv = 2\'b0x; + res = lv ==? rv; + if (res !== 1\'b1) begin + $display(""Failed: %b ==? %b returned 1\'b%b not 1\'b1"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b00; + rv = 2\'b00; + res = lv !=? rv; + if (res !== 1\'b0) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'b0"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b00; + rv = 2\'b01; + res = lv !=? rv; + if (res !== 1\'b1) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'b1"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b10; + rv = 2\'b00; + res = lv !=? rv; + if (res !== 1\'b1) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'b1"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b1x; + rv = 2\'b00; + res = lv !=? rv; + if (res !== 1\'b1) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'b1"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b0x; + rv = 2\'b00; + res = lv !=? rv; + if (res !== 1\'bx) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'bx"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b00; + rv = 2\'b0x; + res = lv !=? rv; + if (res !== 1\'b0) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'b0"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b01; + rv = 2\'b0x; + res = lv !=? rv; + if (res !== 1\'b0) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'b0"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b0z; + rv = 2\'b0x; + res = lv !=? rv; + if (res !== 1\'b0) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'b0"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b0x; + rv = 2\'b0x; + res = lv !=? rv; + if (res !== 1\'b0) begin + $display(""Failed: %b !=? %b returned 1\'b%b not 1\'b0"", lv, rv, res); + pass = 1\'b0; + end + + // Check in a few other contexts. + + lv = 2\'b01; + rv = 2\'b0x; + res = (lv ==? rv) ? 1\'b1 : 1\'b0; + if (res !== 1\'b1) begin + $display(""Failed: %b ==? %b (ternary) returned 1\'b%b not 1\'b1"", lv, rv, res); + pass = 1\'b0; + end + + if (lv !=? rv) begin + $display(""Failed: %b ==? %b (if) returned 1\'b%b not 1\'b1"", lv, rv, res); + pass = 1\'b0; + end + + lv = 2\'b00; + while (lv ==? rv) lv += 2\'b01; + if (lv !== 2\'b10) begin + $display(""Failed: %b ==? %b (while) expected lv to be 2\'b10"", lv, rv); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"// This should generate an error + +module main; + + reg[7:0] shared; + wire [7:0] not_shared = ~shared; + +program test1; + initial shared = \'h55; // ERROR: only non-blocking assign allowed here. +endprogram :test1 + +program test2; + reg [7:0] tmp; + final begin + if (shared !== \'h55) begin +\t $display(""FAILED -- shared=%b is not correct"", shared); +\t $finish; + end + + tmp = ~shared; + if (not_shared !== \'haa) begin +\t $display(""FAILED == not_shared is not correct"", not_shared); +\t $finish; + end + + $display(""PASSED""); + end + +endprogram :test2 + +endmodule // main +" +"/* PR#445 */ +module foo (); + +initial + if (!(1\'b0)) + $display(""PASSED""); + else + $display(""FAILED""); + +endmodule +" +"`begin_keywords ""1364-2005"" +module top; + +localparam [8*8:0] expect = ""0123456789""; + +reg [8*8:0] str; +reg passed; + +initial begin + passed = $value$plusargs(""string=%s"", str); + $display(""%h"", str); + if (passed && (str == expect)) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +`end_keywords +" +"module test(); + reg [1:0] array[1:0]; + reg\t sign; + reg\t clk = 1\'b0; + + always @(posedge clk) + sign = array[1][1]; + + initial begin + array[0] = 1; + array[1] = 2; + + #1 clk = 1; + + #1 if (sign !== 1\'b1) begin +\t $display(""FAILED -- array[1][1] = %b, sign=%b"", array[1][1], sign); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // test +" +"module test(); + wire [2:0] var1 = 3\'bx01; // Incorrect results 101 vs x01. + wire [2:0] var2 = 3\'bx10; // Incorrect results 010 vs x10. + wire [2:0] var3 = 3\'bx0z; // Incorrect results zzz vs x0z. + wire [2:0] var4 = 3\'bx1z; // Incorrect results zzz vs x1z. + wire [2:0] var5 = 3\'bxz1; // Incorrect results 1z1 vs xz1. + wire [2:0] var6 = 3\'bxz0; // Incorrect results 0z0 vs xz0. + wire [3:0] var7 = 4\'bx0z0; // Incorrect results 0000 vs x0z0. + wire [2:0] var8 = 3\'bxxx; // This works correctly. + + initial begin + $displayb(""Should be:\ +x01 x10 x0z x1z xz1 xz0 x0z0 xxx""); + $strobeb (var1,, var2,, var3,, var4,, var5,, var6,, var7,, var8); + end +endmodule +" +"module top; + + initial begin +`ifdef CAUSES_PROBLEM + /* + * C-Style comment in a skipped `ifdef is loosing the '\ +'. + */ +`endif + // This should report an error at line 10. + fail_at_line_10(); + end + +endmodule +" +"module top; + parameter C1 = 1.0e-6; + + reg pass; + real rval; + real exp_result; + + initial begin + pass = 1\'b1; + exp_result = -1000000.0; + + // Check with a constant and a parameter. + rval = -1 / C1; + if (rval != exp_result) begin + $display (""FAILED: -1/%f gave %f, expected %f"", C1, rval, exp_result); + pass = 1\'b0; + end + + // Check with both constants. + rval = -1 / 1.0e-6; + if (rval != exp_result) begin + $display (""FAILED: -1/1.0e-6 gave %f, expected %f"", rval, exp_result); + pass = 1\'b0; + end + + // Check with a positive value. + exp_result = 1000000.0; + rval = 1 / C1; + if (rval != exp_result) begin + $display (""FAILED: 1/%f gave %f, not expected %f"", C1, rval, exp_result); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module main; + + reg clk; + reg Q, D, ce; + + (* ivl_synthesis_on *) + always @(posedge clk) + if (ce) + begin + end + else + Q <= D; + + (* ivl_synthesis_off *) + initial begin + clk = 0; + ce = 0; + D = 0; + #1 clk = 1; + #1 clk = 0; + + if (Q !== 1\'b0) begin +\t $display(""FAILED --- initial setup failed: Q=%b, D=%b, ce=%b"", +\t\t Q, D, ce); +\t $finish; + end + + ce = 1; + D = 1; + #1 clk = 1; + #1 clk = 0; + + if (Q !== 1\'b0) begin +\t $display(""FAILED --- disable didnot work: Q=%b, D=%b, ce=%b"", +\t\t Q, D, ce); +\t $finish; + end + + ce = 0; + #1 clk = 1; + #1 clk = 0; + + if (Q !== 1\'b1) begin +\t $display(""FAILED --- disabled disable not OK: Q=%b, D=%b, ce=%b"", +\t\t Q, D, ce); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"// Regression test for br962 - based on test case provided in bug report +module qtest; + parameter width = 32; + parameter depth = 32; + + reg [width-1:0] values[$]; + reg [$clog2(depth)+width-1:0] sum1; + reg [$clog2(depth)+width-1:0] sum2; + + task new_sample; + input [width-1:0] data; + + int i; + + begin + reg [width-1:0] popped; + if (values.size >= depth) +\tsum1 = sum1 - values.pop_back(); + sum1 = sum1 + data; + values.push_front(data); + sum2 = 0; + for (i = 0; i < values.size; i++) begin + sum2 = sum2 + values[i]; + end + $display(""sum1 = %d sum2 = %d"", sum1, sum2); + if (sum1 !== sum2) begin + $display(""FAILED""); + $finish; + end + end + endtask + + initial begin + sum1 = 0; + repeat (2*depth) new_sample({$random}); + $display(""PASSED""); + end + +endmodule +" +"module main; + + reg [7:0] mem; + reg [2:0] addr; + reg\t out; + reg\t clk; + + (* ivl_synthesis_on *) + always @(posedge clk) out <= mem[addr]; + + integer idx; + (* ivl_synthesis_off *) + initial begin + mem = 8\'hca; + addr = 0; + clk = 0; + + for (idx = 0 ; idx < 8 ; idx = idx+1) begin +\t addr = idx[2:0]; +\t #1 clk = 1; +\t #1 clk = 0; +\t if (out !== mem[idx]) begin +\t $display(""FAILED -- mem[%d] = %b"", idx, out); +\t $finish; +\t end + end + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"// Copyr (c) 2015-2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for shift operators (logical and arithmetic) + +module shifter_test; +reg signed [7:0] inp, out_srl, out_sll, out_sra, out_sla, out_shl_u, out_shr_u, out_shl_s, out_shr_s; +shifter dut(inp, out_srl, out_sll, out_sra, out_sla, out_shl_u, out_shr_u, out_shl_s, out_shr_s); + +initial begin + inp = 8\'b11101100; + #1; // wait for signal assignments + + if(out_srl !== 8\'b01110110) + begin + $display(""FAILED 1""); + $finish(); + end + + if(out_sll !== 8\'b11011000) + begin + $display(""FAILED 2""); + $finish(); + end + + if(out_sra !== 8\'b11110110) + begin + $display(""FAILED 3""); + $finish(); + end + + if(out_sla !== 8\'b11011000) + begin + $display(""FAILED 4""); + $finish(); + end + + if(out_shl_u !== 8\'b10110000) + begin + $display(""FAILED 5""); + $finish(); + end + + if(out_shr_u !== 8\'b00111011) + begin + $display(""FAILED 6""); + $finish(); + end + + if(out_shl_s !== 8\'b10110000) + begin + $display(""FAILED 7""); + $finish(); + end + + if(out_shr_s !== 8\'b11111011) + begin + $display(""FAILED 8""); + $finish(); + end + + $display(""PASSED""); +end +endmodule + +" +"module test (); + + reg [2:0] in; + wire Oand, Oor; + + dut #(.is_and(1)) dand (.O(Oand), .A(in[1]), .B(in[0])); + dut #(.is_and(0)) dor (.O(Oor ), .A(in[1]), .B(in[0])); + + initial begin + for (in = 0 ; in < 4 ; in = in+1) begin +\t #1 /* settle time. */ ; +\t if (Oand !== &in[1:0]) begin +\t $display(""FAILED -- in=%b, Oand=%b"", in, Oand); +\t $finish; +\t end +\t if (Oor !== |in[1:0]) begin +\t $display(""FAILED -- in=%b, Oor=%b"", in, Oor); +\t $finish; +\t end + end // for (in = 0 ; in < 4 ; in = in+1) + $display(""PASSED""); + end + +endmodule + +module dut (output O, input A, input B); + + parameter is_and = 1; + + generate + if (is_and) +\tand g(O, A, B); + else +\tor g(O, A, B); + endgenerate + +endmodule // dut +" +"// +// Verifies disable terminates a forked forever. +// +module test; + initial begin + fork: F + forever #10; + disable F; + join + $display(""PASSED""); + $finish; + end + + initial begin + #20; + $display(""FAILED""); + $finish; + end + +endmodule +" +"module pr3561350(); + +reg [31:0] source; +reg [31:0] result; + +initial begin + source = 10; + // the following expression results in a compiler internal error + result = (source * 2) + 2 + 3 + 4; + // check we get the expected result when the bug has been fixed + if (result === 29) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module top; + wire net; + + assign (pull1, strong0) net = 1\'b1; + + initial begin + #1; +// You can get the correct result by uncommenting the following line. +// $display(""The value is: %b."", net); + $display(""The strength is: %v:"", net); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW - Comma separated parameter def used as a width subscript +// +// +// D: This validates that parameters can be used as literals +// D: in the width subscript. +// + +module main(); + +parameter VAL_1 = 5, + VAL_2 = 0; + +reg [VAL_1: VAL_2] temp_var; + +initial // Excitation block + begin + temp_var = 6\'h11; + #5 ; + end + +initial // Validation block + begin + #1 ; + if(temp_var != 6\'h11) + begin + $display(""FAILED - parameter assignment didn\'t work\ +""); + $finish ; + end + + + $display(""PASSED\ +""); + $finish ; + end + +endmodule +" +"module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:0]; + +assign Array[N][0] = In[0]; +assign Array[0][7:1] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:1] = Array[0][7:N]; +end + +endmodule +" +"`begin_keywords ""1364-2005"" +module automatic_error(); + +task automatic auto_task; + +integer local; + +begin + local = 1; + $strobe(""%0d"", local); +end + +endtask + +initial auto_task; + +endmodule +`end_keywords +" +"module test(); + +logic [1:0] array = new[4]; + +endmodule +" +"// +// Author: Pawel Szostek (pawel.szostek@cern.ch) +// Date: 01.08.2011 + +`timescale 1ns/1ps + +module dummy_v( input [7:0] in, output reg [7:0] out); + assign out = {in[7], 7\'b1111111}; //there is no equivalent to vhdl\'s `others\' +endmodule + +module stimulus (output reg [7:0] a); + parameter S = 20000; + int unsigned j,i; + initial begin + for(i=0; i= 10) + ret = 1\'b1; + else if(temp >= 4) + ret = 1\'b0; + else if(temp >= 2) + ret = 1\'bx; + else + ret = 1\'b0; + inject = ret; + end + endfunction +endmodule +module main; + wire [7:0] i,o; + wire [7:0] veri; + dummy dummy_vhdl(i,o); + dummy_v dummy_verilog(i, veri); + stimulus stim(i); + + + always @(i) begin + #1; + if(o != veri) begin + $display(""ERROR!""); + $display(""VERILOG: "", veri); + $display(""VHDL: "", o); + $stop; + end + end + initial begin + #12000; + #10; + $display(""PASSED""); + //stop; + end +endmodule +" +"// This tests unalligned write/read access to packed structures +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test; + + typedef struct packed { + logic [7:0] high; + logic [7:0] low; + } word_t; + + // Declare word* as a VARIABLE + wire word_t word_se0, word_se1, word_se2, word_se3; + wire word_t word_sw0, word_sw1, word_sw2, word_sw3; + wire word_t word_sp0, word_sp1, word_sp2, word_sp3; + wire word_t word_ep0, word_ep1, word_ep2, word_ep3; + + // error counter + bit err = 0; + + // access to structure elements + assign word_se1.high = {8+0{1\'b1}}; + assign word_se1.low = {8+0{1\'b0}}; + assign word_se2.high = {8+1{1\'b1}}; + assign word_se2.low = {8+1{1\'b0}}; + assign word_se3.high = {8-1{1\'b1}}; + assign word_se3.low = {8-1{1\'b0}}; + // access to whole structure + assign word_sw1 = {16+0{1\'b1}}; + assign word_sw2 = {16+1{1\'b1}}; + assign word_sw3 = {16-1{1\'b1}}; + // access to parts of structure elements + assign word_ep1.high [3:0] = {4+0{1\'b1}}; + assign word_ep1.low [3:0] = {4+0{1\'b0}}; + assign word_ep2.high [3:0] = {4+1{1\'b1}}; + assign word_ep2.low [3:0] = {4+1{1\'b0}}; + assign word_ep3.high [3:0] = {4-1{1\'b1}}; + assign word_ep3.low [3:0] = {4-1{1\'b0}}; + // access to parts of the whole structure + assign word_sp1 [11:4] = {8+0{1\'b1}}; + assign word_sp2 [11:4] = {8+1{1\'b1}}; + assign word_sp3 [11:4] = {8-1{1\'b1}}; + + initial begin + #1; + // access to structure elements + if (word_se0 !== 16\'bzzzzzzzz_zzzzzzzz) begin $display(""FAILED -- word_se0 = \'b%b"", word_se0 ); err=1; end + if (word_se1 !== 16\'b11111111_00000000) begin $display(""FAILED -- word_se1 = \'b%b"", word_se1 ); err=1; end + if (word_se1.high !== 8\'b11111111 ) begin $display(""FAILED -- word_se1.high = \'b%b"", word_se1.high); err=1; end + if (word_se1.low !== 8\'b00000000 ) begin $display(""FAILED -- word_se1.low = \'b%b"", word_se1.low ); err=1; end + if (word_se2 !== 16\'b11111111_00000000) begin $display(""FAILED -- word_se2 = \'b%b"", word_se2 ); err=1; end + if (word_se2.high !== 8\'b11111111 ) begin $display(""FAILED -- word_se2.high = \'b%b"", word_se2.high); err=1; end + if (word_se2.low !== 8\'b00000000 ) begin $display(""FAILED -- word_se2.low = \'b%b"", word_se2.low ); err=1; end + if (word_se3 !== 16\'b01111111_00000000) begin $display(""FAILED -- word_se3 = \'b%b"", word_se3 ); err=1; end + if (word_se3.high !== 8\'b01111111 ) begin $display(""FAILED -- word_se3.high = \'b%b"", word_se3.high); err=1; end + if (word_se3.low !== 8\'b00000000 ) begin $display(""FAILED -- word_se3.low = \'b%b"", word_se3.low ); err=1; end + // access to whole structure + if (word_sw0 !== 16\'bzzzzzzzz_zzzzzzzz) begin $display(""FAILED -- word_sw0 = \'b%b"", word_sw0 ); err=1; end + if (word_sw1 !== 16\'b11111111_11111111) begin $display(""FAILED -- word_sw1 = \'b%b"", word_sw1 ); err=1; end + if (word_sw2 !== 16\'b11111111_11111111) begin $display(""FAILED -- word_sw2 = \'b%b"", word_sw2 ); err=1; end + if (word_sw3 !== 16\'b01111111_11111111) begin $display(""FAILED -- word_sw3 = \'b%b"", word_sw3 ); err=1; end + // access to parts of structure elements + if (word_ep0 !== 16\'bzzzzzzzz_zzzzzzzz) begin $display(""FAILED -- word_ep0 = \'b%b"", word_ep0 ); err=1; end + if (word_ep1 !== 16\'bzzzz1111_zzzz0000) begin $display(""FAILED -- word_ep1 = \'b%b"", word_ep1 ); err=1; end + if (word_ep1.high !== 8\'bzzzz1111 ) begin $display(""FAILED -- word_ep1.high = \'b%b"", word_ep1.high); err=1; end + if (word_ep1.low !== 8\'bzzzz0000 ) begin $display(""FAILED -- word_ep1.low = \'b%b"", word_ep1.low ); err=1; end + if (word_ep2 !== 16\'bzzzz1111_zzzz0000) begin $display(""FAILED -- word_ep2 = \'b%b"", word_ep2 ); err=1; end + if (word_ep2.high !== 8\'bzzzz1111 ) begin $display(""FAILED -- word_ep2.high = \'b%b"", word_ep2.high); err=1; end + if (word_ep2.low !== 8\'bzzzz0000 ) begin $display(""FAILED -- word_ep2.low = \'b%b"", word_ep2.low ); err=1; end + if (word_ep3 !== 16\'bzzzz0111_zzzz0000) begin $display(""FAILED -- word_ep3 = \'b%b"", word_ep3 ); err=1; end + if (word_ep3.high !== 8\'bzzzz0111 ) begin $display(""FAILED -- word_ep3.high = \'b%b"", word_ep3.high); err=1; end + if (word_ep3.low !== 8\'bzzzz0000 ) begin $display(""FAILED -- word_ep3.low = \'b%b"", word_ep3.low ); err=1; end + // access to parts of the whole structure + if (word_sp0 !== 16\'bzzzzzzzz_zzzzzzzz) begin $display(""FAILED -- word_sp0 = \'b%b"", word_sp0 ); err=1; end + if (word_sp1 !== 16\'bzzzz1111_1111zzzz) begin $display(""FAILED -- word_sp1 = \'b%b"", word_sp1 ); err=1; end + if (word_sp2 !== 16\'bzzzz1111_1111zzzz) begin $display(""FAILED -- word_sp2 = \'b%b"", word_sp2 ); err=1; end + if (word_sp3 !== 16\'bzzzz0111_1111zzzz) begin $display(""FAILED -- word_sp3 = \'b%b"", word_sp3 ); err=1; end + + if (!err) $display(""PASSED""); + end + +endmodule // test +" +"module test; + + reg [2:0] tmp1; + integer tmp2; + real tmp3; + + initial begin + t1(tmp1, 1); + if (tmp1 !== 2) begin +\t $display(""FAILED -- tmp1=%b"", tmp1); +\t $finish; + end + + t2(tmp2, 4); + if (tmp2 !== 6) begin +\t $display(""FAILED == tmp2=%d"", tmp2); +\t $finish; + end + + t3(tmp3, 0.5); + if (tmp3 != 2.0) begin +\t $display(""FAILED -- tmp3=%f"", tmp3); +\t $finish; + end + + $display(""PASSED""); + end + + task t1(output [2:0] o, input [2:0] i); + begin +\t o = i + 1; + end + endtask // tt + + task t2(output integer o, input integer i); + o = i + 2; + endtask // t2 + + task t3(output real o, input real i); + o = i + 1.5; + endtask // t3 + +endmodule +" +"/* + * this test attempts to show a problem with the waits. This skip + * and skip2 modules should have identical behavior. + */ + +module skip(r,a); +input r; +output a; +wire r; +reg a; +initial + a=0; +always begin + wait(r); + #1 a=1; + wait(!r); + #1 a=0; +end +endmodule + +module skip2(r,a); +input r; +output a; +wire r; +reg a; +initial + a=0; +always @ (r or a) begin + case ({r,a}) + 00: ; // idle + 10: #1 a=1; + 11: ; // idle + 01: #1 a=0; + endcase +end +endmodule + +module test; +reg r1; +wire a1; +reg clk; +// skip2 skip1(r1,a1); // simulates as expected +skip skip1(r1,a1); // simulation hangs + +always #50 clk= !clk; + +initial begin + $monitor($time,"" "",r1,a1); + $display(""starting""); + #100 r1=0; + #100 r1=1; + wait(a1); + #100 r1=0; + #1000 $display(""timeout""); $finish(0); +end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always fork parallel_statements join + + + +module main ; + +reg [3:0] value1,value2,value3; + +always fork + #5 value1 = 1 ; + #8 value1 = 2; + join + +initial + begin + value1 = 0; + value2 = 0; + #4 ; + if(value1 != 0) + begin + $display(""FAILED - 3.1.12A always fork statements join (0)""); + value2 = 1; + end + #2 ; + if(value1 != 1) + begin + $display(""FAILED - 3.1.12A always fork statements join (1)""); + value2 = 1; + end + #3 ; + if(value1 != 2) + begin + $display(""FAILED - 3.1.12A always fork statements join (2)""); + value2 = 1; + end + #5 ; + if(value1 != 1) + begin + $display(""FAILED - 3.1.12A always fork statements join (3)""); + value2 = 1; + end + if(value2 == 0) $display(""PASSED""); + $finish ; + end +endmodule +" +"// +// Copyright (c) 2002 Steven Wilson (steve@ka6s.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Synth of basic reg form +// +// +module basicreg ( clk, d, q); +input clk, d; +output [2:0] q; +reg [2:0] q; + +always @(posedge clk) + begin +\tq <= d + d; + end + +endmodule + +module test ; + +reg clk, d; + +wire [2:0] q; + +basicreg u_reg (clk,d,q); + +initial + begin +// $dumpfile(""test.vcd""); +// $dumpvars(0,test); + clk = 0; + d = 0; + # 1; + clk = 1; + # 1; + if (q !== 3\'b0) + begin + $display(""FAILED - Q isn\'t 0 on first edge""); +\t $finish; + end + d = 1; + # 1; + clk = 0; + # 1; + if (q !== 3\'b0) + begin + $display(""FAILED - Q isn\'t 0 after first falling edge""); +\t $finish; + end + # 1; + clk = 1; + # 1; + if (q !== 3\'b010) + begin +\t #1 ; + $display(""FAILED - Q isn\'t 2 2nd raising edge""); +\t $finish; + end + # 1; + clk = 0; + # 1; + if (q !== 3\'b010) + begin + $display(""FAILED - Q isn\'t 2 after 2nd falling edge""); +\t $finish; + end + $display(""PASSED""); + + end +endmodule +" +"// Check the power operator (compile time). +module top; + reg pass; + + integer res; + + initial begin + pass = 1\'b1; + + // Check the constant ** with various arguments (table 5-6 1364-2005). + + res = -3**\'bx; + if (res !== \'bx) begin + $display(""Failed: constant -3**\'bx, expected \'bx, got %0d"", res); + pass = 1\'b0; + end + res = -1**\'bx; + if (res !== \'bx) begin + $display(""Failed: constant -1**\'bx, expected \'bx, got %0d"", res); + pass = 1\'b0; + end + res = 0**\'bx; + if (res !== \'bx) begin + $display(""Failed: constant 0**\'bx, expected \'bx, got %0d"", res); + pass = 1\'b0; + end + res = 1**\'bx; + if (res !== \'bx) begin + $display(""Failed: constant 1**\'bx, expected \'bx, got %0d"", res); + pass = 1\'b0; + end + res = 3**\'bx; + if (res !== \'bx) begin + $display(""Failed: constant 3**\'bx, expected \'bx, got %0d"", res); + pass = 1\'b0; + end + + res = \'bx**-3; + if (res !== \'bx) begin + $display(""Failed: constant \'bx**-3, expected \'bx, got %0d"", res); + pass = 1\'b0; + end + res = \'bx**-2; + if (res !== \'bx) begin + $display(""Failed: constant \'bx**-2, expected \'bx, got %0d"", res); + pass = 1\'b0; + end + res = \'bx**-1; + if (res !== \'bx) begin + $display(""Failed: constant \'bx**-1, expected \'bx, got %0d"", res); + pass = 1\'b0; + end + res = \'bx**0; + if (res !== \'bx) begin + $display(""Failed: constant \'bx**0, expected \'bx, got %0d"", res); + pass = 1\'b0; + end + res = \'bx**1; + if (res !== \'bx) begin + $display(""Failed: constant \'bx**1, expected \'bx, got %0d"", res); + pass = 1\'b0; + end + res = \'bx**2; + if (res !== \'bx) begin + $display(""Failed: constant \'bx**2, expected \'bx, got %0d"", res); + pass = 1\'b0; + end + res = \'bx**3; + if (res !== \'bx) begin + $display(""Failed: constant \'bx**3, expected \'bx, got %0d"", res); + pass = 1\'b0; + end + + // Check the 1st line (rvalue is positive). + res = -3**3; + if (res !== -27) begin + $display(""Failed: constant -3**3, expected -27, got %0d"", res); + pass = 1\'b0; + end + res = -3**2; + if (res !== 9) begin + $display(""Failed: constant -3**2, expected 9, got %0d"", res); + pass = 1\'b0; + end + + res = -1**3; + if (res !== -1) begin + $display(""Failed: constant -1**3, expected -1, got %0d"", res); + pass = 1\'b0; + end + res = -1**2; + if (res !== 1) begin + $display(""Failed: constant -1**2, expected 1, got %0d"", res); + pass = 1\'b0; + end + + res = 0**3; + if (res !== 0) begin + $display(""Failed: constant 0**3, expected 0, got %0d"", res); + pass = 1\'b0; + end + res = 0**2; + if (res !== 0) begin + $display(""Failed: constant 0**2, expected 0, got %0d"", res); + pass = 1\'b0; + end + + res = 1**3; + if (res !== 1) begin + $display(""Failed: constant 1**3, expected 1, got %0d"", res); + pass = 1\'b0; + end + res = 1**2; + if (res !== 1) begin + $display(""Failed: constant 1**2, expected 1, got %0d"", res); + pass = 1\'b0; + end + + res = 3**3; + if (res !== 27) begin + $display(""Failed: constant 3**3, expected 27, got %0d"", res); + pass = 1\'b0; + end + res = 3**2; + if (res !== 9) begin + $display(""Failed: constant 3**2, expected 9, got %0d"", res); + pass = 1\'b0; + end + + // Check the 2nd line (rvalue is zero). + res = -3**0; + if (res !== 1) begin + $display(""Failed: constant -3**0, expected 1, got %0d"", res); + pass = 1\'b0; + end + res = -2**0; + if (res !== 1) begin + $display(""Failed: constant -2**0, expected 1, got %0d"", res); + pass = 1\'b0; + end + + res = -1**0; + if (res !== 1) begin + $display(""Failed: constant -1**0, expected 1, got %0d"", res); + pass = 1\'b0; + end + + res = 0**0; + if (res !== 1) begin + $display(""Failed: constant 0**0, expected 1, got %0d"", res); + pass = 1\'b0; + end + + res = 1**0; + if (res !== 1) begin + $display(""Failed: constant 1**0, expected 1, got %0d"", res); + pass = 1\'b0; + end + + res = 2**0; + if (res !== 1) begin + $display(""Failed: constant 2**0, expected 1, got %0d"", res); + pass = 1\'b0; + end + res = 3**0; + if (res !== 1) begin + $display(""Failed: constant 3**0, expected 1, got %0d"", res); + pass = 1\'b0; + end + + // Check the 3rd line (rvalue is negative). + res = -2**-3; + if (res !== 0) begin + $display(""Failed: constant -2**-3, expected 0, got %0d"", res); + pass = 1\'b0; + end + res = -2**-2; + if (res !== 0) begin + $display(""Failed: constant -2**-2, expected 0, got %0d"", res); + pass = 1\'b0; + end + + res = -1**-3; + if (res !== -1) begin + $display(""Failed: constant -1**-3, expected -1, got %0d"", res); + pass = 1\'b0; + end + res = -1**-2; + if (res !== 1) begin + $display(""Failed: constant -1**-2, expected 1, got %0d"", res); + pass = 1\'b0; + end + + res = 0**-3; + if (res !== \'bx) begin + $display(""Failed: constant 0**-3, expected \'bx, got %0d"", res); + pass = 1\'b0; + end + res = 0**-2; + if (res !== \'bx) begin + $display(""Failed: constant 0**-2, expected \'bx, got %0d"", res); + pass = 1\'b0; + end + + res = 1**-3; + if (res !== 1) begin + $display(""Failed: constant 1**-3, expected 1, got %0d"", res); + pass = 1\'b0; + end + res = 1**-2; + if (res !== 1) begin + $display(""Failed: constant 1**-2, expected 1, got %0d"", res); + pass = 1\'b0; + end + + res = 2**-3; + if (res !== 0) begin + $display(""Failed: constant 2**-3, expected 0, got %0d"", res); + pass = 1\'b0; + end + res = 2**-2; + if (res !== 0) begin + $display(""Failed: constant 2**-2, expected 0, got %0d"", res); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test catches the case where the operands of the ?: operator + * have different sizes. + */ +module main; + + reg [3:0] r; + reg [3:0] a; + reg [4:0] b; + reg\t f; + + + initial begin + a = 4\'b1010; + b = 5\'b10101; + + f = 1; + r = f? a : b; + if (r !== 4\'b1010) begin +\t $display(""FAILED: r === %b"", r); +\t $finish; + end + + f = 0; + r = f? a : b; + if (r !== 4\'b0101) begin +\t $display(""FAILED: r === %b"", r); +\t $finish; + end + + $display(""PASSED""); + + end // initial begin +endmodule // main +" +"/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: ldelay5.v,v 1.1 2001/12/26 23:45:57 sib4 Exp $ + +// Test for delays in structural logic. Multiple UDP instances. + +module test; + + wire [1:2] q, a, b; + drec U1(q[1], a[1], b[1]); + drec U2(q[2], a[2], b[2]); + + initial $display(""PASSED""); + +endmodule + +module drec (q, a, b); + output q; + input a, b; + U_drec #1 U(q, a, b); +endmodule + +primitive U_drec (q, a, b); + output q; + input a, b; + table + 1 0 : 1 ; + 0 1 : 0 ; + endtable +endprimitive +" +"/* + * Author: Oswaldo Cadenas + * + * The test checks the module bit ouput type accepts default + * initialization value. + */ + +module clkgen(output bit clk = 0); + +initial begin + #100; + disable checking; + disable gen; + $display (""PASSED""); + $finish; +end + +initial begin + fork + gen; + checking; + join +end + +task gen; + forever #10 clk = ~clk; +endtask + +task checking; + forever begin + #1; + if (clk ==! 1\'b0 && clk ==! 1\'b1 ) begin + $display (""FAILED!""); +\t $finish; + end + end +endtask + +endmodule +" +"// This module generate all 8 inputs for three boolean variables + +module stimulus #(parameter M = 8, T = 10) ( + output reg i0, i1, + output reg s + ); + +bit [2:0] i; + +initial begin + for (i = 0; i < M; i=i+1) begin + #T; + {i0, i1, s} = i; + end + #T; +end + + +endmodule + +// This module always checks the internal generated muxed output complies with the received one + +module check (input i0, i1, s, y); + +logic y_check; + +always @(i0, i1, s) + y_check = s ? i1 : i0; + +always @(y, y_check) begin + #1 if (y != y_check) begin + $display(""ERROR""); + $finish; + end +end + +endmodule + + +module test; + parameter M = 8; + parameter T = 10; + parameter S = (M+1)*T + 40; + + wire i0, i1, s, y; + + + stimulus #(M, T) stim (.i0(i0), .i1(i1), .s(s) ); + mux2to1 duv (.i0(i0), .i1(i1), .s(s), .y(y) ); + check check (.i0(i0), .i1(i1), .s(s), .y(y) ); + + initial begin + #S; + $display(""PASSED""); + $finish; + end + +endmodule +" +"module test; + + wire [10:0] a = 7\'d 16; + + initial + begin + #1; + $display("">%0d<"", a); + $display("">%4d<"", a); + $display("">%h<"", a); + $display("">%4h<"", a); + $display(""%d, %d"", a); + end + +endmodule +" +"`ifdef __ICARUS__ + `define SUPPORT_REAL_NETS_IN_IVTEST +`endif + +module top; + reg pass = 1\'b1; + integer scale = 2, offset = 1; + real rin; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST + wire real ress = scale * rin; + wire real reso = rin + offset; +`endif + + initial begin +`ifdef SUPPORT_REAL_NETS_IN_IVTEST + #1 if (ress != 0.0 || reso != 1.0) begin +\t $display(""FAILED: initial value, expected 0.0/1.0, got %f/%f"", ress, reso); +\t pass = 1\'b0; + end + rin = 2.0; + #1 if (ress != 4.0 || reso != 3.0) begin +\t $display(""FAILED: rin=%f, scale=%f, expected 2.0/2.0, got %f/%f"", rin, scale, ress, reso); +\t pass = 1\'b0; + end +`endif + + if (pass) +\t$display(""PASSED""); + end +endmodule +" +"module pr2132552(); + +task test_task; + +parameter depth = 16; +parameter width = 8; + +reg [width-1:0] mem [depth-1:0]; + +integer i; + +begin + for (i = 0; i < depth; i = i + 1) begin + mem[i] = i; + end + for (i = 0; i < depth; i = i + 1) begin + $display(""%0d"", mem[i]); + end +end + +endtask + +initial test_task; + +endmodule +" +"// This test verifies that an incorrect function and task definition +// does not crash the compiler. +module main(); + // A number of errors here: int and return are not supported + // (SystemVerilog), so the function definition will fail. The + // return should also be inside the begin/end pair. + function int pick; + input myvar; + begin + end + return 0 + endfunction + + // This is a syntax error missing ';' on the task line. + task foo + endtask +endmodule +" +"`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + reg [1:-1][3:0] vec; + + initial begin + pass = 1\'b1; + + vec[1] = 4\'bxxxx; + vec[0] = 4\'bxxxx; + vec[-1] = 4\'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1\'bx] = 4\'b1001; +`endif + if ((vec[1] !== 4\'bxxx) && (vec[0] !== 4\'bxxxx) && + (vec[-1] !== 4\'bxxxx)) begin + $display(""Failed vec[1\'bx], expected 4\'bxxxx, got %b, %b,%b"", + vec[1], vec[0], vec[-1]); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"/* + * This program tests that enumeration values work and are + * implicitly translated to integer values. + */ +module main; + + enum { RED, ORANGE, YELLOW, GREEN, BLUE, VIOLET, +\t BLACK = 10, WHITE = \'d11 +\t} color1; + + int\tvar1; + + initial begin + color1 = RED; + var1 = RED; + $display(""color1 = %0d, var1 = %0d"", color1, var1); + if (color1 !== 0) begin +\t $display(""FAILED""); +\t $finish; + end + if (var1 !== 0) begin +\t $display(""FAILED""); +\t $finish; + end + + color1 = GREEN; + var1 = GREEN; + $display(""color1 = %0d, var1 = %0d"", color1, var1); + if (color1 !== 3) begin +\t $display(""FAILED""); +\t $finish; + end + if (var1 !== 3) begin +\t $display(""FAILED""); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"module top; + + initial begin + if (""this matches"" == ""this\\ + matches"") $display(""PASSED""); + else $display(""FAILED""); + end + +endmodule +" +"`define world World +`define test Hello `world + +module test; + initial $display(""The `test definition is: `define %s"", ``test); +endmodule +" +"/* + * integer2le - a verilog test for integer less-or-equal conditional <= + * + * Copyright (C) 1999 Stephen G. Tell + * Portions inspired by qmark.v by Steven Wilson (stevew@home.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ + +module integer2le; + + integer a; + integer b; + integer c; + reg error; + +initial + begin + error = 0; + + a = 1; + if(a <= 2) + begin +\t b = 1; + end + else + begin +\t $display(""FAILED 1 <= 2""); +\t error = 1; + end + + a = 2; + + if(a <= 2) + begin +\t b = 1; + end + else + begin +\t $display(""FAILED 2 <= 2""); +\t error = 1; + end + + a = 3; + + if(a <= 2) + begin +\t $display(""FAILED 3 <= 2""); +\t error = 1; + end + + c = 0; + a = 10; + for(b = 0; a <= 5; b = b + 1) + begin +\t b = b + a; +\t c = c + 1; +\t if(c > 10) + begin +\t $display(""FAILED (infinite loop) a=%d b=%d"", a, b); +\t error = 1; +\t $finish; +\t end + end + if(b != 0) + begin +\t $display(""FAILED forloop a=%d b=%d"", a, b); +\t error = 1; + end + if(a != 10) + begin +\t $display(""FAILED forloop a=%d b=%d"", a, b); +\t error = 1; + end + + b = 0; + c = 0; + for(a = 0; a <= 5; a = a + 1) + begin +\t b = b + a; +\t c = c + 1; +\t if(c > 10) + begin +\t $display(""FAILED (infinite loop) a=%d b=%d"", a, b); +\t error = 1; +\t $finish; +\t end + end + + if(b != 15) + begin +\t $display(""FAILED forloop b=%d expected 15"", b); +\t error = 1; + end + + if(error == 0) +\t $display(""PASSED""); + + $finish; + end // initial begin + +endmodule +" +"/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// $Id: dangling_port.v,v 1.1 2001/07/08 03:22:08 sib4 Exp $ +// $Log: dangling_port.v,v $ +// Revision 1.1 2001/07/08 03:22:08 sib4 +// Test for PR#209 +// +// +// Test for PR#209, VVP wrong nodangle of dangling port. + +module main; + + reg retval; + reg a, b; + + function f; + input dangle; + begin +\t f = retval; + end + endfunction + + initial + begin +\t#1 retval <= 1; +\t#1 a <= f(0); +\t#1 b <= f(1); +\t#1 $display(""PASSED""); +\t$finish; + end + +endmodule +" +"// This program is based on pr2138979. In particular, the signed +// expressions are sign-extended before the \'|\' is evaluated. This +// behavior is verified by modelsim and ncverilog. (It appears that +// gplcver gets this wrong.) + +module main; + + reg [7:0] a, b; + wire [15:0] y; + reg [15:0] z; + + // Use $signed() to sign extend operands before logic OR + // - Note that Icarus Verilog is not sign extending as expected + assign y = $signed(a) | $signed(b); + + initial begin + a = 8\'h55; + b = 8\'haa; + z = $signed(a) | $signed(b); + + #1 if (y !== 16\'hff_ff || y !== z) begin +\t $display(""FAILED -- a=%h, b=%h, y=%h, z=%h"", a, b, y, z); +\t $finish; + end + + a = 8\'haa; + b = 8\'h55; + z = $signed(a) | $signed(b); + + #1 if (y !== 16\'hff_ff || y !== z) begin +\t $display(""FAILED -- a=%h, b=%h, y=%h, z=%h"", a, b, y, z); +\t $finish; + end + + a = 8\'h7f; + b = 8\'h00; + z = $signed(a) | $signed(b); + + #1 if (y !== 16\'h00_7f || y !== z) begin +\t $display(""FAILED -- a=%h, b=%h, y=%h, z=%h"", a, b, y, z); +\t $finish; + end + + $display(""PASSED""); + $finish; + end // initial begin + +endmodule +" +"/* fopen2 - test $fopen and $fclose system tasks */ + +module fopen2; + integer fp1, fp2, fp3, fp4; + integer dfp; + + reg error; + reg [31:0] foo; + + initial begin + error = 0; + fp1 = $fopen(""work/fopen2.out1""); + checkfp(fp1); + dfp = fp1|1; + $fdisplay(dfp, ""fp1=%d"", fp1); + + fp2 = $fopen(""work/fopen2.out2""); + checkfp(fp2); + dfp = fp2|1; + $fdisplay(dfp, ""fp2=%d"", fp2); + + fp3 = $fopen(""work/fopen2.out3""); + checkfp(fp3); + dfp = fp3|1; + $fdisplay(dfp, ""fp3=%d"", fp3); + + $fclose(fp2); + + fp4 = $fopen(""work/fopen2.out4""); + checkfp(fp4); + dfp = fp4|1; + $fdisplay(dfp, ""fp4=%d"", fp4); + + $fclose(fp1); + $fclose(fp2); + $fclose(fp3); + $fclose(fp4); + if(error == 0) + $display(""PASSED""); + + end // initial begin + + task checkfp; + input [31:0] fp; + begin +\t if(fp != 2 && fp != 4 && fp != 8 && fp != 16 && fp != 32 && fp != 64) begin +\t $display(""FAILED fopen fp=%d"", fp); + error = 1; +\t end + end + endtask // checkfp + +endmodule +" +"// Copyright (c) 2003 Michael Ruff (mruff at chiaro.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +// +// Test basic functionality of convertion system VPI functions. +// +module test; + + integer\terr, i; + real\tr; + reg [63:0]\tb; + + parameter PI = 3.1415926535_8979323846_2643383279; + + initial begin +\terr = 0; + +\t// +\t// $rtoi() +\t// +\ti = $rtoi(0.1); +\tif (i != 0) begin +\t err = 1; +\t $display(""$rtoi(0.1): %0d != 0"", i); +\tend +\ti = $rtoi(9.6); +\tif (i != 9) begin +\t err = 1; +\t $display(""$rtoi(9.6): %0d != 9"", i); +\tend + +\t// +\t// $realtobits() +\t// +\tb = $realtobits(PI); +\tif (b != 64\'h400921FB54442D18) begin +\t err = 1; +\t $display(""$realtobits(PI): \'h%x != \'h400921FB54442D18"", b); +\tend +\tb = $realtobits(1.1); +\tif (b != 64\'h3ff199999999999a) begin +\t err = 1; +\t $display(""$realtobits(1.1): \'h%x != \'h400921FB54442D18"", b); +\tend + +\t// +\t// $bitstoreal() +\t// +\tr = $bitstoreal(64\'h400921FB54442D18); +\tif (r != PI) begin +\t err = 1; +\t $display(""$realtobits(PI): %20.17f != %20.17f"", r, PI); +\tend +\tr = $bitstoreal(64\'h3FF4CCCCCCCCCCCD); +\tif (r != 1.3) begin +\t err = 1; +\t $display(""$realtobits(1.3): %20.17f != 1.3"", r); +\tend + +\t// +\t// $itor() +\t// +\tr = $itor(1); +\tif (r != 1.0) begin +\t err = 1; +\t $display(""$itor(1): %20.1f != 1.0"", r); +\tend +\tr = $itor(123456789); +\tif (r != 123456789.0) begin +\t err = 1; +\t $display(""$itor(123456789): %20.1f != 123456789.0"", r); +\tend + +\tif (err) +\t $display(""FAILED""); +\telse +\t $display(""PASSED""); + +\t$finish; + end + +endmodule +" +"/* Crash.v - reproduces a simulation-time crash (PLI assertion failure) + +Copyright: Bluespec, Inc. 2010 +License: GPLv2 or later + +Transcript: +> uname -a +Linux jnewbern-laptop 2.6.32-21-generic #32-Ubuntu SMP Fri Apr 16 08:09:38 UTC 2010 x86_64 GNU/Linux +> iverilog -V +Icarus Verilog version 0.9.2 (v0_9_2) + ... +> iverilog -v -o crash -Wall Crash.v +... +/usr/lib/ivl/system.sft: Processing System Function Table file. +/usr/lib/ivl/v2005_math.sft: Processing System Function Table file. +/usr/lib/ivl/va_math.sft: Processing System Function Table file. +Using language generation: IEEE1364-2005,no-specify,xtypes,icarus-misc +PARSING INPUT +LOCATING TOP-LEVEL MODULES + Crash + ... done, 0 seconds. +ELABORATING DESIGN + ... done, 0 seconds. +RUNNING FUNCTORS + -F cprop ... + -F nodangle ... + ... 1 iterations deleted 0 dangling signals and 0 events. + ... 2 iterations deleted 0 dangling signals and 1 events. +CALCULATING ISLANDS + ... done, 0 seconds. +CODE GENERATION + ... invoking target_design + ... done, 0 seconds. +STATISTICS +lex_string: add_count=50 hit_count=17 +> ./crash +VCD info: dumpfile dump.vcd opened for output. +VCD warning: $dumpvars ignored, previously called at simtime 0 +vvp: vpi_priv.cc:165: PLI_INT32 vpi_free_object(__vpiHandle*): Assertion `ref\' failed. +Aborted +*/ +module Crash(); + + // Create clock + reg CLK; + + initial begin + CLK = 1\'b0; + end + + always begin + #5; + CLK = 1\'b1; + #5; + CLK = 1\'b0; + end + + // Setup dumpfile at startup + initial begin + $dumpfile(""dump.vcd""); + $dumpvars; + end + + // Count cycles + reg [7:0] counter; + + initial begin + counter = 8\'d0; + end + + always @(posedge CLK) begin + counter <= counter + 1; + end + + // Call system tasks on particular cycles + always@(posedge CLK) + begin + if (counter == 8\'d2) $dumpvars; // repeated! + if (counter >= 8\'d200) begin + $display(""PASSED""); + $finish(32\'d0); + end + end + +endmodule +" +"module top; + parameter NAME = ""test""; + wire i = 0; + + generate + case(NAME) + ""test"" : assign i = 1\'b1; + default : ; + endcase + endgenerate + + initial begin + #1 if (i !== 1\'bx) $display(""FAILED""); + else $display(""PASSED""); + end +endmodule +" +"// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for vvp_net_fun_t::recv_vec4_pv() implementation (vvp). + +module vvp_recv_vec4_pv (input wire logic clk, input wire logic inp, + output wire logic[16:0] arr_out); +logic[16:0] arr; + +always begin + arr[15:0] <= arr[16:1]; + @(clk); wait(clk == 1\'b1); +end + +assign arr[16] = inp; +assign arr_out = arr; + +endmodule + + +module vvp_recv_vec4_pv_test; +logic clk, inp; +logic [16:0] arr, src; +vvp_recv_vec4_pv dut(clk, inp, arr); + +always #5 clk <= ~clk; + +initial begin + int i; + + src <= 17\'b01101110010011011; + clk <= 1\'b1; + #5; + + for(i = 0; i < 17; i = i + 1) begin + #10 inp = src[i]; + end + + #5; // wait for the last assignment occuring in the for loop above + + if(arr !== src) begin + $display(""FAILED""); + end else begin + $display(""PASSED""); + end + + $finish(); +end + +endmodule + +" +"module test(); + + reg [0:(8*6)-1] identstr= ""PASSED""; + reg [7:0] identdata= 8\'b0; + integer i; + + initial + begin +//\t$dumpfile(""indexed_part.vcd""); +//\t$dumpvars; + end + + initial + begin +\tfor (i=0; i<6; i=i+1) +\t begin +\t #10 identdata = identstr[i*8 +:8]; +\t $write(""%c"", identdata); +\t end +\t$write(""\ +""); +\t$finish; + end + +endmodule // test +" +"module part3 ( +\\6A_A , +\\6Y_A , +VCC , +GND , +\\6A_B , +\\6Y_B , +\\6A_C , +\\6Y_C , +\\6A_D , +\\6Y_D , +\\6A_E , +// note: with space before the nl below +\\6Y_E +) ; + +input \\6A_A ; +output \\6Y_A ; +input VCC ; +input GND ; +input \\6A_B ; +output \\6Y_B ; +input \\6A_C ; +output \\6Y_C ; +input \\6A_D ; +output \\6Y_D ; +input \\6A_E ; +output \\6Y_E ; + +assign \\6Y_A = ~\\6A_A ; +assign \\6Y_B = ~\\6A_B ; +assign \\6Y_C = ~\\6A_C ; +assign \\6Y_D = ~\\6A_D ; +assign \\6Y_E = ~\\6A_E ; + +endmodule +" +"`timescale 1ns/10ps + +module top; + reg a, pass; + wire z; + time edge_time; + + always @(z) begin + if ((z === 0) && (($time - edge_time) != 2)) begin + $display(""Falling took %d, expected 2"", $time - edge_time); + pass = 1\'b0; + end + if ((z === 1) && (($time - edge_time) != 1)) begin + $display(""Rising took %d, expected 1"", $time - edge_time); + pass = 1\'b0; + end + end + + initial begin + pass = 1\'b1; + $sdf_annotate(""ivltests/sdf_del.sdf"", top); + #10; + edge_time = $time; + a = 1\'b0; + #10; + edge_time = $time; + a = 1\'b1; + #10 if (pass) $display(""PASSED""); + end + + my_buf dut(z, a); +endmodule + +module my_buf (output z, input a); + buf (z, a); + specify + (a => z) = (0, 0); + endspecify +endmodule +" +"`timescale 1ns/1ns + +module sum_test; + reg clk; + wire [10:0] s; + + initial begin + clk = 0; + forever #10 clk = ~clk; + end + + sum #(5, 8) sum (clk, {8\'d10,8\'d20,8\'d30,8\'d40,8\'d50}, s); + + initial begin + $display(""Starting...""); + repeat (50) @(posedge clk); + $display(""sum = %d"",s); + if (s !== 150) + $display(""FAILED: expected 150, received %0d"",s); + else + $display(""PASSED""); + $finish; + end +endmodule + +module sum + #( + parameter n = 4, + parameter width = 8, + parameter log_n = $clog2(n) + ) + ( + input clk, + input [n*width-1:0]addends, + output reg [log_n+width-1:0] s + ); + + generate + if (n==1) + always @(*) s = addends; + else begin + wire [$clog2(n/2)+width-1:0] a1; + wire [$clog2(n-n/2)+width-1:0] a2; + sum #(n/2, width) s0 (clk, addends[(n/2)*width-1:0], a1); + sum #(n-n/2, width) s1 (clk, addends[n*width-1:(n/2)*width], a2); + always @(posedge clk) s <= a1 + a2; + end + endgenerate + +endmodule // sum +" +"`timescale 1ns/1ps +module top; + + initial begin + $timeformat(-9,6,""ns"",20); + $display(""here""); + $display(""in top, time: %t"",$time); + + $finish(0); + end + +endmodule +" +"module modname; +`define macro1(arg1=d1) $display(`""arg1`""); +`define macro2(arg1=d1, arg2=d2) $display(`""arg1 arg2`""); + initial begin + `macro1() // Works + `macro1(1) // Works + + `macro2() // Cause wrong number of arguments error + `macro2(1) // Cause wrong number of arguments error + `macro2(1,2) // Works + + `macro2(,) // Works + `macro2(1,) // Works + `macro2(1,2) // Works + + `macro2(,2) // Works + end +endmodule +" +"// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Tests initialization of records with aggregate expressions. +// (based on the vhdl_struct_array test) + +module vhdl_record_elab_test; + reg [15:0] in; + wire [15:0] out; + + vhdl_record_elab dut( + .o_high1(out[15:12]), .o_low1(out[11:8]), + .o_high0(out[7:4]), .o_low0(out[3:0]), + + .i_high1(in[15:12]), .i_low1(in[11:8]), + .i_high0(in[7:4]), .i_low0(in[3:0])); + + initial begin + for (in = 0 ; in < 256 ; in = in+1) begin + #1 if (in !== out[15:0]) begin + $display(""FAILED -- out=%h, in=%h"", out, in); + $finish; + end + end + + if (dut.dword_a[0].low !== 4\'b0110 || dut.dword_a[0].high !== 4\'b1001 || + dut.dword_a[1].low !== 4\'b0011 || dut.dword_a[1].high !== 4\'b1100) + begin + $display(""FAILED 2""); + $finish; + end + + $display(""PASSED""); + end +endmodule + +" +"module dummy; + +integer i; +integer foo_value; +reg [1:0] foo_bit; + +initial +begin + i = 1; + foo_value = 10; + foo_bit[i] <= #foo_value 1\'b0; + + /* + NOTE: + if you replace previous line either with: + foo_bit[1] <= #foo_value 1\'b0; + or with: + foo_bit[i] <= #10 1\'b0; + then ""invalid opcode"" is not shown + */ + + #20 if (foo_bit[1] !== 1\'b0) begin +\t $display(""FAILED -- foo_bit[1] = %b"", foo_bit[1]); +\t $finish; +\tend + $display(""PASSED""); +end + +endmodule +" +"`begin_keywords ""1364-2005"" + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass = 1\'b1; +// reg [3:0] var = 4\'b1001; +// wire [3:0] var = 4\'b1001; + parameter [3:0] var = 4\'b1001; + reg [3:0] part; + reg [5:0] big; + + initial begin +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = var[-2 +: 4]; // should be 01xx. + if (part !== 4\'b01xx) begin + $display(""part select [1:-2] failed, expected 4\'b01xx, got %b"", part); + pass = 1\'b0; + end + + part = var[2 +: 4]; // should be xx10. + if (part !== 4\'bxx10) begin + $display(""part select [5:2] failed, expected 4\'bxx10, got %b"", part); + pass = 1\'b0; + end + + big = var[-1 +: 6]; // should be x10100101x. + if (big !== 6\'bx1001x) begin + $display(""part select [4:-1] failed, expected 6\'bx1001x, got %b"", big); + pass = 1\'b0; + end +`endif + + if (pass) $display(""PASSED""); + end +endmodule +`end_keywords +" +"`timescale 1us/1us +module top_timescale; + initial begin + $printtimescale(top_timescale); + $printtimescale(top_timescale2); + end +endmodule + +`resetall +`timescale 1ns/1ns +module top_timescale2; + reg a; + initial a = 1'b1; +endmodule +" +"module mod #( + parameter A = 1, + localparam B = A + 1, + parameter C = B - 1 +) ( + input [A-1:0] a, + input [B-1:0] b, + input [C-1:0] c +); + +endmodule + +module top(); + +reg [3:0] a = \'ha; +reg [4:0] b = \'hb; +reg [5:0] c = \'hc; + +mod #(4, 6) m(a, b, c); + +initial begin + $display(""%0d %0d %0d"", m.A, m.B, m.C); + $display(""%0d %0d %0d"", $bits(m.a), $bits(m.b), $bits(m.c)); + if (m.A === 4 && $bits(m.a) === 4 + && m.B === 5 && $bits(m.b) === 5 + && m.C === 6 && $bits(m.c) === 6) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module test; + +reg [15:0] x; +reg [15:0] y; + +initial begin + x = 0; + y = 0; + $monitor(x,,y); + $background_copy(x, y); + #1 $display(""started background copy""); + #1 x = 1; + #1 x = 2; + #1 $display(""finished background copy""); +end + +endmodule +" +"module top; + reg pass = 1\'b1; + reg a, b; + real c, d; + + initial begin + c = 0.0; + d = 1.0; + a = 1\'b0; + b = 1\'b0; + assign c = 6/(2 - d*(b & ~a) + d*(a & ~b)); + + #1; + if (c != 3.0) begin + $display(""FAILED, expected 3.0, got %f"", c); + pass = 1\'b0; + end + + a = 1\'b1; + b = 1\'b0; + assign c = 6/(2 - d*(b & ~a) + d*(a & ~b)); + #1; + if (c != 2.0) begin + $display(""FAILED, expected 2.0, got %f"", c); + pass = 1\'b0; + end + + a = 1\'b0; + b = 1\'b1; + assign c = 6/(2 - d*(b & ~a) + d*(a & ~b)); + #1; + if (c != 6.0) begin + $display(""FAILED, expected 6.0, got %f"", c); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"`define MACRO2 12 +`define MACRO3 13 + +`default_nettype tri1 + +module test1(); + +buf(a,b); + +initial #1 begin + $display(""test1 macro1 = %0d"", `MACRO1 ); + $display(""test1 macro2 = %0d"", `MACRO2 ); + $display(""test1 macro3 = %0d"", `MACRO3 ); + $display(""test1 wire = %b"", a); +end + +endmodule + +`undef MACRO1 +" +"module test(); + +integer j; +integer jel; +integer x; +integer xel; + +`define A(j) (jel == 1 && j == 2) +`define B(j) (jel \\ + == 1 && \\ + j == 2) + +initial +begin +\tj = 0; +\tjel = 1; +\tx = 2; +\txel = 3; + +\tif(`A(x) && `B(x)) +\t\t$display(""PASSED""); +\telse +\t\t$display(""FAILED""); +end +endmodule +" +"module top; + reg passed; + reg [63:0] wide; + reg [31:0] norm; + + initial begin + passed = 1\'b1; + if (! $value$plusargs(""option=%h"", wide)) begin + $display(""FAILED: Unable to read wide option""); + passed = 1\'b0; + end + if (wide !== 64\'h0123456789abcdef) begin + $display(""FAILED: wide expected 64\'h0123456789abcdef, got %h"", wide); + passed = 1\'b0; + end + + if (! $value$plusargs(""option=%h"", norm)) begin + $display(""FAILED: Unable to read normal option""); + passed = 1\'b0; + end + if (norm !== 32\'h89abcdef) begin + $display(""FAILED: normal expected 32\'h89abcdef, got %h"", norm); + passed = 1\'b0; + end + + if (passed) $display(""PASSED""); + end +endmodule +" +"// pr1868991 + +module test(); + + reg [31:0] mpr1[35-1:16]; + reg [29:0] dtlreq_addr; + wire [7-1:0] select_mpr_inx = dtlreq_addr[7-1:0]; + wire [31:0]\tselect_dcs_mpr = mpr1[select_mpr_inx]; + + integer\tidx; + initial begin + for (idx = 16 ; idx < 35 ; idx = idx+1) +\tmpr1[idx] = idx; + + for (idx = 16 ; idx < 35 ; idx = idx+1) begin +\t dtlreq_addr = idx; +\t #1 if (select_dcs_mpr !== idx) begin +\t $display(""FAILED - select_dcs_mpr=%d, idx=%d"", select_dcs_mpr, idx); +\t $finish; +\t end + end + + $display(""PASSED""); + end +endmodule +" +"module test; + + parameter PVALUE = 12; + localparam LVALUE = 88; + + enum byte unsigned { UVAL[256] } unsignedbyte_enum; + enum byte { SVAL[100] } signedbyte_enum; + enum { ADD = 10, SUB[5], JMP[6:8]} E1; // page 28 LRM + enum { REGISTER[2] = 1, REGISTER[2:4] = 10 } vr; // page 28 LRM + enum { P[5] = PVALUE, Q, S[3] = LVALUE} par_enum; + enum reg [2:0] { state[8] } bin_enum; + enum integer {IDLE, XX=\'bx, XY=\'b01, YY=\'b10, XZ = 32\'h1x2z3xxz} next_state; + + int i; + + initial begin + // 1. Default anonymous enum data type should be int + // don\'t know yet how to quickly check this + // + // 1. Checking initialisations + // + // a. If the first name is not assigned it should be zero + if (UVAL0 !== 8\'h0 || SVAL0 !== 8\'h0) + begin + $display (""FAILED - First un-assigned element of enum type was not zero""); + $finish; + end + // b. Checking initials E1 and vr + if (ADD != 10 || REGISTER0 != 1) + begin + $display (""FAILED - First initialised elements of enums E1 and vr were not elaborated properly""); + $finish; + end + // A name without a value is automatically assigned and increment of the value of the + // previous name (Section 4.10 LRM) + // c. checking initial values for SUB (0-4) in E1 + if (SUB0 != 11 || SUB1 != 12 || SUB2 != 13 || SUB3 != 14 || SUB4 != 15) + begin + $display (""FAILED - Initialised elements SUB (0-4) in enum E1 were not elaborated properly""); + $finish; + end + // c. checking initial values for JMP (6-8) in E1 + if (JMP6 != 16 || JMP7 != 17 || JMP8 != 18) + begin + $display (""FAILED - Initialised elements (6-8) JMP in enum E1 were not elaborated properly""); + $finish; + end + // c. checking initial values in vr + if (REGISTER1 != 2 || REGISTER2 != 10 || REGISTER3 != 11 || REGISTER4 != 12) + begin + $display (""FAILED - Initialised elements REGISTER (1-4) in enum vr were not elaborated properly""); + $finish; + end + // c. checking hand-picked values in unsignedbyte_enum + if (UVAL23 != 23 || UVAL91 != 91 || UVAL138 != 138 || UVAL207 != 207) + begin + $display (""FAILED - Initialised some UVAL in enum unsignedbyte_enum were not elaborated properly""); + $display (""UVAL23 = %0d, UVAL91 = %0d, UVAL138 = %0d, UVAL207 = %0d"", UVAL23, UVAL91, UVAL138, UVAL207); + $finish; + end + // c. checking hand-picked values in signedbyte_enum + if (SVAL7 != 7 || SVAL19 != 19 || SVAL87 != 87) + begin + $display (""FAILED - Initialised some SVAL in enum signedbyte_enum were not elaborated properly""); + $display (""SVAL7 = %0d, SVAL19 = %0d, SVAL87 = %0d"", SVAL7, UVAL91, SVAL19, SVAL87); + $finish; + end + // c. checking final values in unsignedbyte_enum and signedbyte_enum + if (UVAL255 != 255 || SVAL99 != 99) + begin + $display (""FAILED - Initialised final values UVAL and SVAL did not elaborate properly""); + $display (""UVAL255 = %0d, SVAL99 = %0d"", UVAL255, SVAL99); + $finish; + end + // d. checking xz values in next_state + if (XX !== \'bx || XZ !== 32\'h1x2z3xxz) + begin + $display (""FAILED - Initialised x,z values in next_state did not elaborate properly""); + $finish; + end + // e. constants elaborated from parameter + if (P0 != PVALUE+0 || P1 != PVALUE+1 || P2 != PVALUE+2 || P3 != PVALUE+3 || P4 != PVALUE + 4 || Q != PVALUE+5) + begin + $display (""FAILED - Initialised values P in par_enum were not elaborated properly""); + $finish; + end + // f. constants elaborated from localparam + if (S0 != LVALUE+0 || S1 != LVALUE+1 || S2 != LVALUE+2) + begin + $display (""FAILED - Initialised values S in par_enum were not elaborated properly""); + $finish; + end + #1; + // g. checking num method + if (unsignedbyte_enum.num != 256 || signedbyte_enum.num != 100 || + E1.num != 9 || vr.num != 5 || par_enum.num != 9 ) + begin + $display (""FAILED - The num method does not report as expected""); + $finish; + end + // h. checking first method + if (unsignedbyte_enum.first != 0 || signedbyte_enum.first != 0 || + E1.first != 10 || vr.first != 1 || par_enum.first != PVALUE ) + begin + $display (""FAILED - The first method does not report as expected""); + $finish; + end + // i. checking last method + if (unsignedbyte_enum.last != 255 || signedbyte_enum.last != 99 || + E1.last != 18 || vr.last != 12 || par_enum.last != LVALUE+2 ) + begin + $display (""FAILED - The last method does not report as expected""); + $finish; + end + // checking the next method on unsignedbyte_enum + unsignedbyte_enum = unsignedbyte_enum.first; + for (i=1; i<=255; i=i+1) begin + unsignedbyte_enum = unsignedbyte_enum.next; + if (unsignedbyte_enum != i) begin + $display (""FAILED - The next method does not report as expected for unsignedbyte_enum""); + $finish; + end + end + unsignedbyte_enum = unsignedbyte_enum.next; + // checking wrap to the first element for signedbyte_enum + if (unsignedbyte_enum != unsignedbyte_enum.first) begin + $display (""FAILED - The next method did not wrap to the first element for unsignedbyte_enum""); + $finish; + end + // checking the next method on signedbyte_enum + signedbyte_enum = signedbyte_enum.first; + for (i=1; i<100; i=i+1) begin + signedbyte_enum = signedbyte_enum.next; + if (signedbyte_enum != i) begin + $display (""FAILED - The next method does not report as expected for signedbyte_enum""); + $finish; + end + end + signedbyte_enum = signedbyte_enum.next; + // checking wrap to the first element for signedbyte_enum + if (signedbyte_enum != signedbyte_enum.first) begin + $display (""FAILED - The next method did not wrap to the first element for signedbyte_enum""); + $finish; + end + // checking the next method on E1 + E1 = E1.first; + for (i=E1.first; i<= E1.last; i=i+1) begin + if (E1 != i) begin + $display (""FAILED - The next method does not report as expected for E1""); + $finish; + end + E1 = E1.next; + end + // checking wrap to the first element in E1 + if (E1 != E1.first) begin + $display (""FAILED - The next method did not wrap to the first element for E1""); + $finish; + end + // checking the next method on vr, manual walk + vr = vr.first; + vr = vr.next; + if (vr != 2) begin + $display (""FAILED - The next method does not report as expected for vr in element REGISTER1""); + $finish; + end + vr = vr.next; + if (vr != 10) begin + $display (""FAILED - The next method does not report as expected for vr in element REGISTER2""); + $finish; + end + vr = vr.next; + if (vr != 11) begin + $display (""FAILED - The next method does not report as expected for vr in element REGISTER3""); + $finish; + end + vr = vr.next; + if (vr != 12) begin + $display (""FAILED - The next method does not report as expected for vr in element REGISTER4""); + $finish; + end + // checking wrap to the first element in vr + vr = vr.next; + if (vr != vr.first) begin + $display (""FAILED - The next method did not wrap to the first element for vr""); + $finish; + end + // checking the next method for bin_enum + bin_enum = bin_enum.first; + for (i=bin_enum.first; i<= bin_enum.last; i = i+1) begin + if (bin_enum != i) begin + $display (""FAILED - The next method does not report as expected for bin_enum""); + $finish; + end + bin_enum = bin_enum.next; + end + // checking wrap to the first element in bin_enum + if (bin_enum != bin_enum.first) begin + $display (""FAILED - The next method did not wrap to the first element for bin_enum""); + $finish; + end + $display (""PASSED""); + end + + +endmodule +" +"module top; + reg res; + reg [1:0] in; + + initial begin + in = 2\'b00; + + res = ~ |in; + res = ~ ∈ + res = ~ ^in; + + $display(""FAILED: These expressions should be a syntax error.""); + end +endmodule +" +"/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test uses the level sensitive wait to notice the scheduling of + * the expression evaluation. The FAILED message detects cases where + * the value of test is true, even when the value of a is set to + * false. + */ + +module main; + + reg a; + + wire test = a == 1\'b1; + + always #1 wait (test) begin + if (a !== 1\'b1) begin +\t $display(""FAILED -- a == %b, test == %b"", a, test); +\t $finish; + end + + a = 1\'b0; + end + + initial begin + a = 0; + + #10 a = 1; + #10 a = 0; + #10 $display(""PASSED""); + end +endmodule // main +" +"/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * SDW: This test is a first expression test inside a parameter declaration. + */ +module test; + +parameter A0 = 2\'b10 | 2\'b01 ; + +initial + begin + if(A0 !== 2\'b11) + $display(""FAILED - A0 expression OR doesn\'t work.""); + else + $display(""PASSED""); + end + +endmodule +" +"module main; + + reg [7:0] mem [7:0], D; + reg [2:0] radr, wadr; + reg\t wr, rst, clk; + + /* + * This implements the synchronous write port to the memory. + */ + always @(posedge clk) + + if (rst) begin +\tmem[0] <= 0; +\tmem[1] <= 0; +\tmem[2] <= 0; +\tmem[3] <= 8\'h33; +\tmem[5] <= 8\'h55; +\tmem[6] <= 0; +\tmem[7] <= 0; + end else + if (wr) begin +\t mem[wadr] <= D; + end + + // This is the asynchronous read port from the memory. + wire[7:0] Q = mem[radr]; + + initial begin + wr = 0; + rst = 1; + clk = 0; + #1 clk = 1; + #1 clk = 0; + + radr = 3; + #1 if (Q !== 8\'h33) begin +\t $display(""FAILED -- mem[3] == \'b%b"", Q); +\t $finish; + end + + radr = 5; + #1 if (Q !== 8\'h55) begin +\t $display(""FAILED == mem[5] == \'b%b"", Q); +\t $finish; + end + + wadr = 4; + wr = 1; + rst = 0; + D = \'h44; + #1 clk = 1; + #1 clk = 0; + + radr = 4; + #1 if (Q !== 8\'h44) begin +\t $display(""FAILED -- mem[4] == \'b%b"", Q); +\t $finish; + end + + $display(""PASSED""); + end +endmodule +" +"/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + reg [1:0] out; + reg\t in; + + initial begin + in = 1; + out = in << 1; + if (out !== 2\'b10) begin +\t $display(""FAILED (1) -- out == %b"", out); +\t $finish; + end + + out <= in << 1; + + #1 if (out !== 2\'b10) begin +\t $display(""FAILED (2) -- out == %b"", out); +\t $finish; + end + + $display(""PASSED""); + end // initial begin +endmodule // main +" +"// pr1697250 + +module test(); + + wire active; + reg [63:0] bus; + + assign active = ((|(bus)===0)?0:1); + + initial begin + bus = \'haaaa; + #1 if (active !== 1) begin +\t $display(""FAILED -- bus=%h, active=%b"", bus, active); +\t $finish; + end + + bus = 0; + #1 if (active !== 0) begin +\t $display(""FAILED == bus=%h, active=%b"", bus, active); +\t $finish; + end + + $display(""PASSED""); + end +endmodule +" +"/* + * See pr245 in the ivtest test suite. + */ + +`timescale 1ns/1ns + +module t; + wire [11:0] iodata; + integer i; + + + initial + begin + $timeformat(-9,0,""ns"",5); +\t$display("" TIME:IOD""); +\t$monitor( ""%7t:%3x"", +\t\t $time,iodata); +\t#0 +\t force iodata =0; +\tfor (i=0; i<512;i=i+1) +\t #10 +\t force iodata =i; + end // initial begin +endmodule // t +" +"`timescale 1ns/1ns + +module test; + +reg pass = 1; + +reg [3 : 0] A = 4\'hf; +wire [3 : 0] a_lls, a_lrs; + +reg signed [3 : 0] B = 7; +wire signed [3 : 0] b_als, b_ars; + +assign a_lls = A<<4; +assign a_lrs = A>>4; +assign b_als = B<<<4; +assign b_ars = B>>>4; + +initial begin +\t#1; +\tif (a_lls !== 4\'b0) begin +\t\t$display(""FAILED assigning logical left shift""); +\t\tpass = 0; +\tend +\tif (a_lrs !== 4\'b0) begin +\t\t$display(""FAILED assigning logical right shift""); +\t\tpass = 0; +\tend +\tif (b_als !== 4\'b0) begin +\t\t$display(""FAILED assigning arithmetic left shift""); +\t\tpass = 0; +\tend +\tif (b_ars !== 4\'h0) begin +\t\t$display(""FAILED assigning arithmetic right shift (0)""); +\t\tpass = 0; +\tend +\t#1 B = -8; +\t#1; +\tif (b_ars !== 4\'hf) begin +\t\t$display(""FAILED assigning arithmetic right shift (1)""); +\t\tpass = 0; +\tend + +\tif (pass) $display(""PASSED""); +end + +endmodule // test +" +"`timescale 1ns/100ps + +module top; + reg pass; + real rarr[0:3]; + realtime del; + reg signed [1:0] idx; + integer count; + event evt; + + initial begin + pass = 1\'b1; + + // Check the initial values. + if (rarr[1] != 0.0) begin + $display(""FAILED initial value, expected 0.0, got %f"", rarr[1]); + pass = 1\'b0; + end + + // Check a negative index value. + rarr[3] = 3.0; + idx = -1; + rarr[idx] <= 0.0; + #0.1; + if (rarr[3] != 3.0) begin + $display(""FAILED negative index 1, expected 3.0, got %f"", rarr[3]); + pass = 1\'b0; + end + + del = 1.0; + rarr[idx] <= #(del) 0.0; + #1.1; + if (rarr[3] != 3.0) begin + $display(""FAILED negative index 2, expected 3.0, got %f"", rarr[3]); + pass = 1\'b0; + end + + count = 0; + rarr[idx] <= repeat(count) @(evt) 0.0; + #0.1; + if (rarr[3] != 3.0) begin + $display(""FAILED negative index 3, expected 3.0, got %f"", rarr[3]); + pass = 1\'b0; + end + + // Check a non-blocking assignment. + rarr[1] <= 2.0; + if (rarr[1] != 0.0) begin + $display(""FAILED non-blocking assign 1, expected 0.0, got %f"", rarr[1]); + pass = 1\'b0; + end + #0.1; + if (rarr[1] != 2.0) begin + $display(""FAILED non-blocking assign 2, expected 2.0, got %f"", rarr[1]); + pass = 1\'b0; + end + + // Check a delayed non-blocking assignment. + rarr[1] <= #2 3.0; + #1.9; + if (rarr[1] != 2.0) begin + $display(""FAILED delayed NB assign 1, expected 2.0, got %f"", rarr[1]); + pass = 1\'b0; + end + #0.2; + if (rarr[1] != 3.0) begin + $display(""FAILED delayed NB assign 2, expected 3.0, got %f"", rarr[1]); + pass = 1\'b0; + end + + // Check a variable delay non-blocking assignment. + del = 3.0; + rarr[1] <= #(del) 4.0; + #2.9; + if (rarr[1] != 3.0) begin + $display(""FAILED var. delay NB assign 1, expected 3.0, got %f"", rarr[1]); + pass = 1\'b0; + end + #0.2; + if (rarr[1] != 4.0) begin + $display(""FAILED var. delay NB assign 2, expected 4.0, got %f"", rarr[1]); + pass = 1\'b0; + end + + // Check a zero count event non-blocking assignment. + rarr[1] <= repeat(count) @(evt) 5.0; + #0.1; + if (rarr[1] != 5.0) begin + $display(""FAILED NB EC count=0, expected 5.0, got %f"", rarr[1]); + pass = 1\'b0; + end + + // Check for an event non-blocking assignment. + rarr[1] <= @(evt) 6.0; + fork + #1 ->evt; + begin + #0.9; + if (rarr[1] != 5.0) begin + $display(""FAILED NB EC initial, expected 5.0, got %f"", rarr[1]); + pass = 1\'b0; + end + #0.2; + if (rarr[1] != 6.0) begin + $display(""FAILED NB EC final, expected 6.0, got %f"", rarr[1]); + pass = 1\'b0; + end + end + join + + if (pass) $display(""PASSED""); + end +endmodule +" +"/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// $Id: rop.v,v 1.2 2001/06/20 00:04:09 ka6s Exp $ +// $Log: rop.v,v $ +// Revision 1.2 2001/06/20 00:04:09 ka6s +// Updated the code to print out ""PASSED"" when appropriate. +// +// Revision 1.1 2001/06/19 13:52:13 ka6s +// Added 4 tests from Stephan Boettcher +// +// +// Test of === operator + +module rop; + + reg [2:0] a; + reg\t b; + reg\t error; + + initial + begin + error = 0; +\ta = 3\'b 10z; +\tb = & a; +\t$display("" & 3\'b%b === %b"", a, b); +\tif (b !== 1\'b0) +\tbegin +\t $display(""FAILED""); +\t error = 1; + end +\tb = | a; +\t$display("" | 3\'b%b === %b"", a, b); +\tif (b !== 1\'b1) + begin +\t error = 1; +\t $display(""FAILED""); +\t end +\tb = ^ a; +\t$display("" ^ 3\'b%b === %b"", a, b); +\tif (b !== 1\'bx) + begin +\t $display(""FAILED""); +\t error = 1; + end +\tb = ~& a; +\t$display(""~& 3\'b%b === %b"", a, b); +\tif (b !== 1\'b1) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ~| a; +\t$display(""~| 3\'b%b === %b"", a, b); +\tif (b !== 1\'b0) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ~^ a; +\t$display(""~^ 3\'b%b === %b"", a, b); +\tif (b !== 1\'bx) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\ta = 3\'b 0xz; +\tb = & a; +\t$display("" & 3\'b%b === %b"", a, b); +\tif (b !== 1\'b0) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = | a; +\t$display("" | 3\'b%b === %b"", a, b); +\tif (b !== 1\'bx) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ^ a; +\t$display("" ^ 3\'b%b === %b"", a, b); +\tif (b !== 1\'bx) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ~& a; +\t$display(""~& 3\'b%b === %b"", a, b); +\tif (b !== 1\'b1) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ~| a; +\t$display(""~| 3\'b%b === %b"", a, b); +\tif (b !== 1\'bx) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ~^ a; +\t$display(""~^ 3\'b%b === %b"", a, b); +\tif (b !== 1\'bx) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\ta = 3\'b 1xz; +\tb = & a; +\t$display("" & 3\'b%b === %b"", a, b); +\tif (b !== 1\'bx) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = | a; +\t$display("" | 3\'b%b === %b"", a, b); +\tif (b !== 1\'b1) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ^ a; +\t$display("" ^ 3\'b%b === %b"", a, b); +\tif (b !== 1\'bx) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ~& a; +\t$display(""~& 3\'b%b === %b"", a, b); +\tif (b !== 1\'bx) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ~| a; +\t$display(""~| 3\'b%b === %b"", a, b); +\tif (b !== 1\'b0) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ~^ a; +\t$display(""~^ 3\'b%b === %b"", a, b); +\tif (b !== 1\'bx) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\ta = 3\'b 000; +\tb = & a; +\t$display("" & 3\'b%b === %b"", a, b); +\tif (b !== 1\'b0) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = | a; +\t$display("" | 3\'b%b === %b"", a, b); +\tif (b !== 1\'b0) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ^ a; +\t$display("" ^ 3\'b%b === %b"", a, b); +\tif (b !== 1\'b0) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ~& a; +\t$display(""~& 3\'b%b === %b"", a, b); +\tif (b !== 1\'b1) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ~| a; +\t$display(""~| 3\'b%b === %b"", a, b); +\tif (b !== 1\'b1) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ~^ a; +\t$display(""~^ 3\'b%b === %b"", a, b); +\tif (b !== 1\'b1) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\ta = 3\'b 111; +\tb = & a; +\t$display("" & 3\'b%b === %b"", a, b); +\tif (b !== 1\'b1) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = | a; +\t$display("" | 3\'b%b === %b"", a, b); +\tif (b !== 1\'b1) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ^ a; + $display("" ^ 3\'b%b === %b"", a, b); +\tif (b !== 1\'b1) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ~& a; +\t$display(""~& 3\'b%b === %b"", a, b); +\tif (b !== 1\'b0) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ~| a; +\t$display(""~| 3\'b%b === %b"", a, b); +\tif (b !== 1\'b0) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end +\tb = ~^ a; +\t$display(""~^ 3\'b%b === %b"", a, b); +\tif (b !== 1\'b0) +\t begin +\t $display(""FAILED""); +\t error = 1; +\t end + if(error === 0) +\t $display(""PASSED""); + end + +endmodule +" +" +program main; + + function int sum_array(bit[7:0] array[]); + int idx; + sum_array = 0; + for (idx = 0 ; idx < array.size() ; idx = idx+1) +\tsum_array += array[idx]; + endfunction // sum_array + + bit [7:0] obj[]; + int\t foo; + initial begin + foo = sum_array(\'{}); + if (foo !== 0) begin +\t $display(""FAILED -- sum of empty array returns %0d"", foo); +\t $finish; + end + + obj = new[3]; + obj = \'{1,2,3}; + foo = sum_array(obj); + if (foo !== 6) begin +\t $display(""FAILED -- sum of \'{1,2,3} is %0d"", foo); +\t $finish; + end + + obj = new[3] (\'{4,5,6}); + foo = sum_array(obj); + if (foo !== 15) begin +\t $display(""FAILED -- sum of \'{4,5,6} is %0d"", foo); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endprogram // main +" +"/* + * Copyright (c) 2005 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +/* $Id: real8.v,v 1.1 2005/07/07 16:26:05 stevewilliams Exp $ */ + +/* + * This test demonstrates (and checks) the handling of real values and + * expressions in some ways that baseline IEEE1364-2001. Particularly, + * reg and wire values with types, and nets able to carry real values + * through delays. + */ +module main; + + // This is *not* valid baseline Verilog, but iverilog extensions + // support this. These statements declare a real valued variable + // and a real valued net. + reg real target; + wire real feedback; + + // The feedback should take the target value 10 time units + // after any change in the target value. + assign #(10) feedback = target; + + // The control value is calculated from the current target + // and feedback values. This is recalculated whenever either + // of the inputs change. + wire real control = (feedback - target)/2.0; + + initial begin + target = 16.0; + // The target should, after this assignment, have a well + // defined value 16, but the feedback should remain at NaN + // for a while. + #1 $display($time,,""target=%f, feedback=%f, control=%f"", +\t\t target, feedback, control); + + if (target != 16.0) begin +\t $display(""FAILED -- target value is not correct.""); +\t $finish; + end + + // feedback is still undefined. + + // By now, the feedback as taken on a value, and the control + // should have been calcluated. + #10 $display($time,,""target=%f, feedback=%f, control=%f"", +\t\t target, feedback, control); + + if (feedback != 16.0) begin +\t $display(""FAILED -- feedback has wrong value.""); +\t $finish; + end + + if (control != 0.0) begin +\t $display(""FAILED -- control has wrong value.""); +\t $finish; + end + + target = 8.0; + + #9 $display($time,,""target=%f, feedback=%f, control=%f"", +\t\t target, feedback, control); + + if (feedback != 16.0) begin +\t $display(""FAILED -- feedback has wrong value.""); +\t $finish; + end + + if (control != 4.0) begin +\t $display(""FAILED -- control has wrong value.""); +\t $finish; + end + + #2 $display($time,,""target=%f, feedback=%f, control=%f"", +\t\t target, feedback, control); + + if (feedback != 8.0) begin +\t $display(""FAILED -- feedback has wrong value.""); +\t $finish; + end + + if (control != 0.0) begin +\t $display(""FAILED -- control has wrong value.""); +\t $finish; + end + + $display(""PASSED""); + $finish; + end + +endmodule // main +" +"module test(); + wire\t d; + wire [5:0]\t f; + b u1 (.c({d, f})); +endmodule + +module b (c); + +output [6:0] c; + +endmodule +" +"module check (input unsigned [103:0] a, b, c); + wire [103:0] int_AB; + + assign int_AB = a & b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB !== c) begin + $display(""ERROR""); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [103:0] A, B); + parameter S = 2000; + int unsigned i; + + + initial begin + A = 0; B= 0; + // values with 0, 1 + for (i=0; i read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter WID = 4; + reg [WID-1:0] A, B; + wire [WID:0] Q; + + addN usum(.\\A[3] (A[3]), .\\A[2] (A[2]), .\\A[1] (A[1]), .\\A[0] (A[0]), +\t .\\B[3] (B[3]), .\\B[2] (B[2]), .\\B[1] (B[1]), .\\B[0] (B[0]), +\t .\\Q[4] (Q[4]), .\\Q[3] (Q[3]), .\\Q[2] (Q[2]), .\\Q[1] (Q[1]), .\\Q[0] (Q[0])); + + int\t\t adx; + int\t\t bdx; + initial begin + for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin +\t for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin +\t A <= adx[WID-1:0]; +\t B <= bdx[WID-1:0]; +\t #1 if (Q !== (adx+bdx)) begin +\t $display(""FAILED -- A=%b, B=%b, Q=%b"", A, B, Q); +\t $finish; +\t end +\t end + end + $display(""PASSED""); + end + +endmodule // main +" +"/* + * A D-type flip-flop to check synchronous logic works + * correctly. + */ + +module testbench; + reg d, clk, rst, enable; + wire q, q_bar; + + dff uut(q, q_bar, d, clk, rst); + + initial clk <= 0; + + always @(clk) + if (enable) + #1 clk <= !clk; + + initial begin + enable <= 1; + rst <= 1; + d <= 1\'bx; + #2; + if (q !== 0) + begin + $display(""FAILED -- Not reset""); + $finish; + end + rst <= 0; + d <= 1\'b1; + #2; + if (q !== 1) + begin + $display(""FAILED -- q not 1 as expected""); + $finish; + end + d <= 1\'b0; + #2; + if (q !== 0) + begin + $display(""FAILED -- q not 0 as expected""); + $finish; + end + rst <= 1; + #2; + enable <= 0; // Alternative to using $finish + $display(""PASSED""); + end + +endmodule // testbench + +module dff(q, q_bar, d, clk, rst); + output q, q_bar; + input d, clk, rst; + reg q; + + always @(posedge clk or posedge rst) + if (rst) + q <= 1\'b0; + else + q <= d; + + not(q_bar, q); + +endmodule // dff +" +"module top; + reg passed; + reg [7:0] val; + reg signed [7:0] sval; + real rval; + + initial begin + passed = 1\'b1; + val = 8\'hff; + sval = 8\'hff; + /* Check a constant unsigned value cast to signed. */ + rval = $itor($signed(8\'hff)); + if (rval != -1.0) begin + $display(""Failed unsigned constant cast to signed conversion, "", + ""expected -1.0, got %g."", rval); + passed = 1\'b0; + end + /* Check an unsigned variable cast to signed. */ + rval = $itor($signed(val)); + if (rval != -1.0) begin + $display(""Failed unsigned variable cast to signed conversion, "", + ""expected -1.0, got %g."", rval); + passed = 1\'b0; + end + /* Check a constant signed value. */ + rval = $itor(8\'shff); + if (rval != -1.0) begin + $display(""Failed signed constant conversion, "", + ""expected -1.0, got %g."", rval); + passed = 1\'b0; + end + /* Check a variable signed value. */ + rval = $itor(sval); + if (rval != -1.0) begin + $display(""Failed signed variable conversion, "", + ""expected -1.0, got %g."", rval); + passed = 1\'b0; + end + + if (passed) $display(""PASSED""); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validates Non-blocking order determinism IEEE1364-Draft, page 5-3, +// SDW - section 5.4.1. + +module main (); + +reg x,clock; +reg inval; +reg error; + +always @(posedge clock) + begin + x <= ~inval; + x <= inval; + end + +initial + begin + clock = 0; + error = 0; + #1; + inval = 0; + #5 ; + clock = 1; + #1 ; + if(x !== inval) + begin + $display(""FAILED - parallel non-blocking assign s/b 0, is %b"",x); + error = 1; + end + #6 + clock = 0; + #1 ; + inval = 1; + #5 ; + clock = 1; + #1 ; + if(x !== inval) + begin + $display(""FAILED - parallel non-blocking assign s/b 1, is %b"",x); + error = 1; + end + #1 ; + if(error == 0) + $display(""PASSED""); + end +endmodule +" +"`timescale 1ns/1ns +module top; + reg itrig = 1'b0; + wire [31:0] tm, stm; + + assign tm = itrig * $time; + assign stm = itrig * $stime; + + initial begin + $monitor(tm,, stm); + #1 itrig = 1'b1; + #1 itrig = 1'b0; + #1 itrig = 1'b1; + #1 itrig = 1'b0; + end + +endmodule +" +"module top; + reg pass = 1\'b1; + + reg [1:0] rval = 2\'b10; + wire [1:0] wval = (wval > 0) ? 2\'b01 : 2\'b00; + // This works as follows: + // rlval starts are 0.0 which is not greater than 0.0 (false). + // This sets rlval to 2.0 which is greater than 0.0 (true). + // This then sets the value to 1.0 which is still true and stable. + wire real rlval = (rlval > 0.0) ? 1.0 : 2.0; + + initial begin + #1; + if (rval != 2\'b10) begin + $display(""FAILED initial value expected 2\'b10, got %b."", rval); + pass = 1\'b0; + end + + if (wval !== 2\'b0x) begin + $display(""FAILED net value expected 2\'b0x, got %b."", wval); + pass = 1\'b0; + end + + if (rlval != 1.0) begin + $display(""FAILED net real value expected 1.0, got %f."", rlval); + pass = 1\'b0; + end + + #1 assign rval = (rval > 0) ? 2\'b01 : 2\'b00; + if (rval != 2\'b01) begin + $display(""FAILED forced value expected 2\'b01, got %b."", rval); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"`begin_keywords ""1364-2005"" +module automatic_error(); + +task automatic auto_task; + +integer local; + +begin + $monitor(""%0d"", local); + #1 local = 0; + #1 local = 1; +end + +endtask + +initial auto_task; + +endmodule +`end_keywords +" +"// +// Copyright (c) 1999 Peter Monta (pmonta@imedia.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module main; + reg [3:0] b; + wire [1:0] a; + assign a = b[3:2] + 1; + + initial begin + b = 4\'b1011; + #1; + if (a===2\'b11) + $display(""PASSED""); + else + $display(""FAILED""); + end +endmodule +" +"/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program checks that a function execution that includes part + * selects properly evaluates expressions. This is inspired by PR#95. + */ +module main; + + wire [3:0] a = 4\'h1; + wire [3:0] b = 4\'h3; + reg [1:0] got1, got2; + reg [7:0] line; + + initial + begin + line = 8\'h30; + + #1; // Need some delay for the assignments to run. +\tgot1 = { (b[3:0] == line[7:4]), (a[3:0] == line[3:0]) }; +\tgot2 = test(a, b, line); + +\t$display(""a=%b, b=%b, line=%b, got1=%b, got2=%b"", +\t\t a, b, line, got1, got2); + +\tif (got1 !== 2\'b10) begin +\t $display(""FAILED -- got1 is wrong: %b !== 2\'b10"", got1); +\t $finish; +\tend + +\tif (got1 !== got2) begin +\t $display(""FAILED -- got2 is incorrect: %b !== %b"", got1, got2); +\t $finish; +\tend + +\t$display(""PASSED""); + $finish; + end + + function [1:0] test; + input [3:0] a, b; + input [7:0] line; + test = { (b == line[7:4]), (a[3:0] == line[3:0]) }; + + endfunction // test + + +endmodule // main +" +"// +// Copyright (c) 1999 Peter Monta (pmonta@imedia.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module main; + wire [3:0] a,b,c; + + assign a=4\'d5, b=4\'d8, c=4\'d12; + + initial begin + #1; + if (a===4\'d5 && b===4\'d8 && c==4\'d12) + $display(""PASSED""); + else + $display(""FAILED""); + end +endmodule +" +"// This tests end labes (should fail compilation) +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test (); + + // error counter + bit err = 0; + + initial + begin : dummy_label + if (!err) $display(""PASSED""); + end : dummy_label_bad + +endmodule : test_bad +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate that arrays spread across the input range of an arrayed +// module instantiation are supported. +// + +module my_and (out,a,b); +input [3:0] a,b; +output [3:0] out; + +and u0 (out[0],a[0],b[0]); +and u1 (out[1],a[1],b[1]); +and u2 (out[2],a[2],b[2]); +and u3 (out[3],a[3],b[3]); + +endmodule + +module main; + +reg globvar; + +wire [15:0] out; +reg [15:0] a,b, rslt; +reg error; + +// The test gate goes HERE! + +my_and foo [0:3] (out,a,b); + +always @(a or b) + rslt = a & b; + +initial + begin // { + error = 0; + # 1; + for(a = 16\'h1; a != 16\'hffff; a = (a << 1) | 1) + begin // { + for(b = 16\'hffff; b !== 16\'h0; b = b >> 1) + begin // { + #1 ; + if(out !== rslt) + begin // { + $display(""FAILED - GA And a=%h,b=%h,expct=%h - rcvd=%h"", + a,b,rslt,out); + error = 1; + end // } + end // } + end // } + if( error == 0) + $display(""PASSED""); + end // } +endmodule // main +" +"module top; + reg pass = 1\'b1; + reg in [1:1]; + wire out = in[1]; + + initial begin + in[1] = 1\'b0; + #1 if(out != 1\'b0) begin + $display(""FAILED: CA from array, expected 1\'b0, got %b"", out); + pass = 1\'b0; + end + if (pass) $display(""PASSED""); + end +endmodule +" +"/* + * Copyright (c) 2001 Philip Blundell + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module m(a); +input a; +endmodule + +module n; +wire a; +m #(1,2,3) am(a); +initial $display(""PASSED""); +endmodule +" +"module main; + + // Declare word1 as a VARIABLE + struct packed { + logic [7:0] high; + logic [7:0] low; + } word1; + + // Declare word2, word3 as a NET + wire struct packed { + logic [7:0] high; + logic [7:0] low; + } word2, word3; + + assign word2.high = word1.high; + assign word2.low = word1.low; + assign {word3.high, word3.low} = {word1.low, word1.high}; + + initial begin + word1 = 16\'haa_55; + if (word1.high !== 8\'haa || word1.low !== 8\'h55) begin +\t $display(""FAILED: word1 = %h, word1.high = %h, word1.low = %h"", +\t\t word1, word1.high, word1.low); +\t $finish; + end + + #1 /* Make sure word2 assign propagates */; + + if (word2.high !== 8\'haa || word2.low !== 8\'h55) begin +\t $display(""FAILED: word2 = %h, word2.high = %h, word2.low = %h"", +\t\t word1, word2.high, word2.low); +\t $finish; + end + + /* and also for word3 */ + if (word3.low !== 8\'haa || word3.high !== 8\'h55) begin +\t $display(""FAILED: word3 = %h, word3.high = %h, word3.low = %h (should be reverse)"", +\t\t word1, word3.high, word3.low); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"module testbench; +foo #(ASDF) bar(); +endmodule + +module foo #(parameter A=1); +endmodule +" +"module top; + wire real minus; + real in; + + assign minus = -in; // Should be arith/sub.r Cr<0>, + + initial begin + $monitor(minus,, in); + + in = 3.0; + #1 in = 4.0; + #1 in = 6.0; + end +endmodule +" +" +/* + * This tests a trivial class. This tests that properties can be + * given types, and that the types behave properly. + */ +program main; + + class bar_t; + int a; + int b; + endclass // bar_t + + // Trivial example of a class + class foo_t ; + byte a; + bar_t b; + endclass : foo_t // foo_t + + foo_t obj; + bar_t tmp; + + initial begin + obj = new; + + // This is the most trivial assignment of class properties. + obj.a = \'hf_ff; + obj.b = new; + + tmp = obj.b; + tmp.a = 0; + tmp.b = 1; + + if (obj.a != -1) begin +\t $display(""FAILED -- assign to object: obj.a=%0d"", obj.a); +\t $finish; + end + + if (tmp.a != 0 || tmp.b != 1) begin +\t $display(""FAILED -- obj.b.a=%0d, obj.b.b=%0d"", tmp.a, tmp.b); +\t $finish; + end + + $display(""PASSED""); + $finish; + end +endprogram // main +" +"// This program is about testing that the value ranges parse and work for +// integer parameters. +module test(input wire in); + + parameter real foo = 0.0 from [-10.0 : 10.0] exclude [1:2); + parameter real bar = 0 from (-inf:0]; + + initial begin + $display(""foo = %f"", foo); + $display(""PASSED""); + $finish; + end + +endmodule // test + +module main; + + reg rrr = 0; + test #(.foo(2), .bar(-5.0)) dut (rrr); + +endmodule // main +" +"// pr1960548 + +module test; + initial + $display(""B`x""); +endmodule +" +"`timescale 1ns / 100ps + +module main; + + integer rc; + reg [7:0] x, y; + reg [23:0] z; + + initial begin + rc = $sscanf(""a b cd e"", ""%c %c %s"", x, y, z); + + if (rc !== 3) begin +\t $display(""FAILED -- rc = %d"", rc); +\t $finish; + end + + if (x != \'h61) begin +\t $display(""FAILED -- x=%h"", x); +\t $finish; + end + + if (y != \'h62) begin +\t $display(""FAILED -- y=%h"", y); +\t $finish; + end + + if (z !== 24\'h00_63_64) begin +\t $display(""FAILED == z=%h"", z); +\t $finish; + end + + $display(""PASSED""); + end +endmodule // main +" +"/* + * This program tests the synthesis of small memories, including + * aysnchronous read w/ synchronous write. + */ +module main; + + reg clk; + + reg Q, D; + (* ivl_synthesys_on *) + always @(negedge clk) + Q <= D; + + (* ivl_synthesys_off *) + initial begin + clk = 1; + D = 0; + #2 clk = 0; + #2 clk = 1; + #2 if (Q !== 0) begin +\t $display(""FAILED -- initial setup D=%b, Q=%b"", D, Q); +\t $finish; + end + + D = 1; + #2 clk = 0; + + #2 if (Q !== 1) begin +\t $display(""FAILED -- negedge clk failed D=%b, Q=%b"", D, Q); +\t $finish; + end + + D = 0; + #2 clk = 1; + #2 if (Q !== 1) begin +\t $display(""FAILED -- posedge clk tripped FF. D=%b, Q=%b"", D, Q); +\t $finish; + end + + $display(""PASSED""); + $finish; + end + +endmodule // main +" +"module test(); + +reg a, b, en; + +wire a1, a2, a3, a4, a5, a6, a7; + +assign (supply1, supply0) a1 = a; + +tranif1 t1(a1, a2, en); +tranif1 t2(a2, a3, en); +tranif1 t3(a3, a4, en); +tranif1 t4(a4, a5, en); +tranif1 t5(a5, a6, en); +tranif1 t6(a6, a7, en); + +wire a11, a12, a13, a14, a15, b11, b12, b13, b14, b15; +wire a21, a22, a23, a24, a25, b21, b22, b23, b24, b25; +wire a31, a32, a33, a34, a35, b31, b32, b33, b34, b35; +wire a41, a42, a43, a44, a45, b41, b42, b43, b44, b45; +wire a51, a52, a53, a54, a55, b51, b52, b53, b54, b55; + +assign (supply1, supply0) a11 = a, b11 = b; +assign (supply1, strong0) a12 = a, b12 = b; +assign (supply1, pull0) a13 = a, b13 = b; +assign (supply1, weak0) a14 = a, b14 = b; +assign (supply1, highz0) a15 = a, b15 = b; + +assign (strong1, supply0) a21 = a, b21 = b; +assign (strong1, strong0) a22 = a, b22 = b; +assign (strong1, pull0) a23 = a, b23 = b; +assign (strong1, weak0) a24 = a, b24 = b; +assign (strong1, highz0) a25 = a, b25 = b; + +assign ( pull1, supply0) a31 = a, b31 = b; +assign ( pull1, strong0) a32 = a, b32 = b; +assign ( pull1, pull0) a33 = a, b33 = b; +assign ( pull1, weak0) a34 = a, b34 = b; +assign ( pull1, highz0) a35 = a, b35 = b; + +assign ( weak1, supply0) a41 = a, b41 = b; +assign ( weak1, strong0) a42 = a, b42 = b; +assign ( weak1, pull0) a43 = a, b43 = b; +assign ( weak1, weak0) a44 = a, b44 = b; +assign ( weak1, highz0) a45 = a, b45 = b; + +assign ( highz1, supply0) a51 = a, b51 = b; +assign ( highz1, strong0) a52 = a, b52 = b; +assign ( highz1, pull0) a53 = a, b53 = b; +assign ( highz1, weak0) a54 = a, b54 = b; + +tranif1 t11(a11, b11, en); +tranif1 t12(a12, b12, en); +tranif1 t13(a13, b13, en); +tranif1 t14(a14, b14, en); +tranif1 t15(a15, b15, en); + +tranif1 t21(a21, b21, en); +tranif1 t22(a22, b22, en); +tranif1 t23(a23, b23, en); +tranif1 t24(a24, b24, en); +tranif1 t25(a25, b25, en); + +tranif1 t31(a31, b31, en); +tranif1 t32(a32, b32, en); +tranif1 t33(a33, b33, en); +tranif1 t34(a34, b34, en); +tranif1 t35(a35, b35, en); + +tranif1 t41(a41, b41, en); +tranif1 t42(a42, b42, en); +tranif1 t43(a43, b43, en); +tranif1 t44(a44, b44, en); +tranif1 t45(a45, b45, en); + +tranif1 t51(a51, b51, en); +tranif1 t52(a52, b52, en); +tranif1 t53(a53, b53, en); +tranif1 t54(a54, b54, en); +tranif1 t55(a55, b55, en); + +task display_strengths; + +input ta, tb, ten; + +begin + a = ta; + b = tb; + en = ten; + #1; + $display(""a = %b b = %b en = %b"", a, b, en); + $display(""a1(%v) a2(%v) a3(%v) a4(%v) a5(%v) a6(%v) a7(%v)"", a1, a2, a3, a4, a5, a6, a7); + $display(""t11(%v %v) t12(%v %v) t13(%v %v) t14(%v %v) t15(%v %v)"", a11, b11, a12, b12, a13, b13, a14, b14, a15, b15); + $display(""t21(%v %v) t22(%v %v) t23(%v %v) t24(%v %v) t25(%v %v)"", a21, b21, a22, b22, a23, b23, a24, b24, a25, b25); + $display(""t31(%v %v) t32(%v %v) t33(%v %v) t34(%v %v) t35(%v %v)"", a31, b31, a32, b32, a33, b33, a34, b34, a35, b35); + $display(""t41(%v %v) t42(%v %v) t43(%v %v) t44(%v %v) t45(%v %v)"", a41, b41, a42, b42, a43, b43, a44, b44, a45, b45); + $display(""t51(%v %v) t52(%v %v) t53(%v %v) t54(%v %v) t55(%v %v)"", a51, b51, a52, b52, a53, b53, a54, b54, a55, b55); +end + +endtask + +initial begin + display_strengths(1\'bz, 1\'bz, 1\'bz); + display_strengths(1\'bz, 1\'bz, 1\'bx); + display_strengths(1\'bz, 1\'bz, 1\'b0); + display_strengths(1\'bz, 1\'bz, 1\'b1); + + display_strengths(1\'bx, 1\'bz, 1\'bz); + display_strengths(1\'bx, 1\'bz, 1\'bx); + display_strengths(1\'bx, 1\'bz, 1\'b0); + display_strengths(1\'bx, 1\'bz, 1\'b1); + + display_strengths(1\'b0, 1\'bz, 1\'bz); + display_strengths(1\'b0, 1\'bz, 1\'bx); + display_strengths(1\'b0, 1\'bz, 1\'b0); + display_strengths(1\'b0, 1\'bz, 1\'b1); + + display_strengths(1\'b1, 1\'bz, 1\'bz); + display_strengths(1\'b1, 1\'bz, 1\'bx); + display_strengths(1\'b1, 1\'bz, 1\'b0); + display_strengths(1\'b1, 1\'bz, 1\'b1); + + display_strengths(1\'bz, 1\'bx, 1\'bz); + display_strengths(1\'bz, 1\'bx, 1\'bx); + display_strengths(1\'bz, 1\'bx, 1\'b0); + display_strengths(1\'bz, 1\'bx, 1\'b1); + + display_strengths(1\'bx, 1\'bx, 1\'bz); + display_strengths(1\'bx, 1\'bx, 1\'bx); + display_strengths(1\'bx, 1\'bx, 1\'b0); + display_strengths(1\'bx, 1\'bx, 1\'b1); + + display_strengths(1\'b0, 1\'bx, 1\'bz); + display_strengths(1\'b0, 1\'bx, 1\'bx); + display_strengths(1\'b0, 1\'bx, 1\'b0); + display_strengths(1\'b0, 1\'bx, 1\'b1); + + display_strengths(1\'b1, 1\'bx, 1\'bz); + display_strengths(1\'b1, 1\'bx, 1\'bx); + display_strengths(1\'b1, 1\'bx, 1\'b0); + display_strengths(1\'b1, 1\'bx, 1\'b1); + + display_strengths(1\'bz, 1\'b0, 1\'bz); + display_strengths(1\'bz, 1\'b0, 1\'bx); + display_strengths(1\'bz, 1\'b0, 1\'b0); + display_strengths(1\'bz, 1\'b0, 1\'b1); + + display_strengths(1\'bx, 1\'b0, 1\'bz); + display_strengths(1\'bx, 1\'b0, 1\'bx); + display_strengths(1\'bx, 1\'b0, 1\'b0); + display_strengths(1\'bx, 1\'b0, 1\'b1); + + display_strengths(1\'b0, 1\'b0, 1\'bz); + display_strengths(1\'b0, 1\'b0, 1\'bx); + display_strengths(1\'b0, 1\'b0, 1\'b0); + display_strengths(1\'b0, 1\'b0, 1\'b1); + + display_strengths(1\'b1, 1\'b0, 1\'bz); + display_strengths(1\'b1, 1\'b0, 1\'bx); + display_strengths(1\'b1, 1\'b0, 1\'b0); + display_strengths(1\'b1, 1\'b0, 1\'b1); + + display_strengths(1\'bz, 1\'b1, 1\'bz); + display_strengths(1\'bz, 1\'b1, 1\'bx); + display_strengths(1\'bz, 1\'b1, 1\'b0); + display_strengths(1\'bz, 1\'b1, 1\'b1); + + display_strengths(1\'bx, 1\'b1, 1\'bz); + display_strengths(1\'bx, 1\'b1, 1\'bx); + display_strengths(1\'bx, 1\'b1, 1\'b0); + display_strengths(1\'bx, 1\'b1, 1\'b1); + + display_strengths(1\'b0, 1\'b1, 1\'bz); + display_strengths(1\'b0, 1\'b1, 1\'bx); + display_strengths(1\'b0, 1\'b1, 1\'b0); + display_strengths(1\'b0, 1\'b1, 1\'b1); + + display_strengths(1\'b1, 1\'b1, 1\'bz); + display_strengths(1\'b1, 1\'b1, 1\'bx); + display_strengths(1\'b1, 1\'b1, 1\'b0); + display_strengths(1\'b1, 1\'b1, 1\'b1); +end + +endmodule +" +"module top; + parameter parg0 = 0.0; + parameter parg1 = 1.0; + parameter parg2 = 2.0; + parameter pargi = 1.0/0.0; // Inf. + parameter pargn = $sqrt(-1.0); // NaN. + real arg0, arg1, arg2, argi, argn; + reg result, pass; + + initial begin + pass = 1\'b1; + + arg0 = 0.0; + arg1 = 1.0; + arg2 = 2.0; + argi = 1.0/0.0; // Inf. + argn = $sqrt(-1.0); // NaN. + + /* Check ! on a constant real value. */ + result = !parg0; + if (result !== 1\'b1) begin + $display(""Failed: constant !0.0, expected 1\'b1, got %b"", result); + pass = 1\'b0; + end + + result = !parg1; + if (result !== 1\'b0) begin + $display(""Failed: constant !1.0, expected 1\'b0, got %b"", result); + pass = 1\'b0; + end + + result = !parg2; + if (result !== 1\'b0) begin + $display(""Failed: constant !2.0, expected 1\'b0, got %b"", result); + pass = 1\'b0; + end + + result = !pargi; + if (result !== 1\'b0) begin + $display(""Failed: constant !Inf, expected 1\'b0, got %b"", result); + pass = 1\'b0; + end + + result = !pargn; + if (result !== 1\'b0) begin + $display(""Failed: constant !NaN, expected 1\'b0, got %b"", result); + pass = 1\'b0; + end + + /* Check ! on a real variable. */ + result = !arg0; + if (result !== 1\'b1) begin + $display(""Failed: !0.0, expected 1\'b1, got %b"", result); + pass = 1\'b0; + end + + result = !arg1; + if (result !== 1\'b0) begin + $display(""Failed: !1.0, expected 1\'b0, got %b"", result); + pass = 1\'b0; + end + + result = !arg2; + if (result !== 1\'b0) begin + $display(""Failed: !2.0, expected 1\'b0, got %b"", result); + pass = 1\'b0; + end + + result = !argi; + if (result !== 1\'b0) begin + $display(""Failed: !Inf, expected 1\'b0, got %b"", result); + pass = 1\'b0; + end + + result = !argn; + if (result !== 1\'b0) begin + $display(""Failed: !NaN, expected 1\'b0, got %b"", result); + pass = 1\'b0; + end + + /* Check && on a constant real value. */ + result = parg0 && parg1; + if (result !== 1\'b0) begin + $display(""Failed: constant 0.0 && 1.0, expected 1\'b0, got %b"", result); + pass = 1\'b0; + end + + result = parg0 && parg2; + if (result !== 1\'b0) begin + $display(""Failed: constant 0.0 && 2.0, expected 1\'b0, got %b"", result); + pass = 1\'b0; + end + + result = parg1 && parg2; + if (result !== 1\'b1) begin + $display(""Failed: constant 1.0 && 2.0, expected 1\'b1, got %b"", result); + pass = 1\'b0; + end + + /* Check && on a real variable. */ + result = arg0 && arg1; + if (result !== 1\'b0) begin + $display(""Failed: 0.0 && 1.0, expected 1\'b0, got %b"", result); + pass = 1\'b0; + end + + result = arg0 && arg2; + if (result !== 1\'b0) begin + $display(""Failed: 0.0 && 2.0, expected 1\'b0, got %b"", result); + pass = 1\'b0; + end + + result = arg1 && arg2; + if (result !== 1\'b1) begin + $display(""Failed: 1.0 && 2.0, expected 1\'b1, got %b"", result); + pass = 1\'b0; + end + + /* Check || on a constant real value. */ + result = parg0 || 0; + if (result !== 1\'b0) begin + $display(""Failed: constant 0.0 || 0, expected 1\'b0, got %b"", result); + pass = 1\'b0; + end + + result = parg0 || parg1; + if (result !== 1\'b1) begin + $display(""Failed: constant 0.0 || 1.0, expected 1\'b1, got %b"", result); + pass = 1\'b0; + end + + result = parg0 || parg2; + if (result !== 1\'b1) begin + $display(""Failed: constant 0.0 || 2.0, expected 1\'b1, got %b"", result); + pass = 1\'b0; + end + + /* Check || on a real variable. */ + result = arg0 || 0; + if (result !== 1\'b0) begin + $display(""Failed: 0.0 || 0, expected 1\'b0, got %b"", result); + pass = 1\'b0; + end + + result = arg0 || arg1; + if (result !== 1\'b1) begin + $display(""Failed: 0.0 || 1.0, expected 1\'b1, got %b"", result); + pass = 1\'b0; + end + + result = arg0 || arg2; + if (result !== 1\'b1) begin + $display(""Failed: 0.0 || 2.0, expected 1\'b1, got %b"", result); + pass = 1\'b0; + end + + /* Check the ternary with a constant real cond. value. */ + result = parg0 ? 1\'b1 : 1\'b0; + if (result !== 1\'b0) begin + $display(""Failed: constant 0.0 ? ..., expected 1\'b0, got %b"", result); + pass = 1\'b0; + end + + result = parg1 ? 1\'b1 : 1\'b0; + if (result !== 1\'b1) begin + $display(""Failed: constant 1.0 ? ..., expected 1\'b1, got %b"", result); + pass = 1\'b0; + end + + result = parg2 ? 1\'b1 : 1\'b0; + if (result !== 1\'b1) begin + $display(""Failed: constant 2.0 ? ..., expected 1\'b1, got %b"", result); + pass = 1\'b0; + end + + result = pargi ? 1\'b1 : 1\'b0; + if (result !== 1\'b1) begin + $display(""Failed: constant Inf ? ..., expected 1\'b1, got %b"", result); + pass = 1\'b0; + end + + result = pargn ? 1\'b1 : 1\'b0; + if (result !== 1\'b1) begin + $display(""Failed: constant NaN ? ..., expected 1\'b1, got %b"", result); + pass = 1\'b0; + end + + /* Check the ternary with a real cond. variable. */ + result = arg0 ? 1\'b1 : 1\'b0; + if (result !== 1\'b0) begin + $display(""Failed: 0.0 ? ..., expected 1\'b0, got %b"", result); + pass = 1\'b0; + end + + result = arg1 ? 1\'b1 : 1\'b0; + if (result !== 1\'b1) begin + $display(""Failed: 1.0 ? ..., expected 1\'b1, got %b"", result); + pass = 1\'b0; + end + + result = arg2 ? 1\'b1 : 1\'b0; + if (result !== 1\'b1) begin + $display(""Failed: 2.0 ? ..., expected 1\'b1, got %b"", result); + pass = 1\'b0; + end + + result = argi ? 1\'b1 : 1\'b0; + if (result !== 1\'b1) begin + $display(""Failed: Inf ? ..., expected 1\'b1, got %b"", result); + pass = 1\'b0; + end + + result = argn ? 1\'b1 : 1\'b0; + if (result !== 1\'b1) begin + $display(""Failed: NaN ? ..., expected 1\'b1, got %b"", result); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module test(); + +localparam [7:0] dly1 = 1; +wire [7:0] dly2 = 2; +reg [7:0] dly3 = 3; + +reg en; +wire i = 1; +wire [6:1] o; + +tranif1 #(dly1, dly2) buf1(o[1], i, en); +tranif1 #(dly2, dly1) buf2(o[2], i, en); +tranif1 #(dly1, dly3) buf3(o[3], i, en); +tranif1 #(dly3, dly1) buf4(o[4], i, en); +tranif1 #(dly2, dly3+1) buf5(o[5], i, en); +tranif1 #(4, 2) buf6(o[6], i, en); + +function check(input o1, input o2, input o3, input o4, input o5, input o6); + +begin + check = (o[1] == o1) && (o[2] == o2) && (o[3] == o3) + && (o[4] == o4) && (o[5] == o5) && (o[6] == o6); +end + +endfunction + +reg failed = 0; + +initial begin + #1 $monitor($time,,en,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]); + + en = 1\'b1; + #0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx)) failed = 1; + #1; #0 if (!check(1\'b1, 1\'bx, 1\'b1, 1\'bx, 1\'bx, 1\'bx)) failed = 1; + #1; #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'bx, 1\'b1, 1\'bx)) failed = 1; + #1; #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'bx)) failed = 1; + #1; #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1)) failed = 1; + + en = 1\'b0; + #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1)) failed = 1; + #1; #0 if (!check(1\'b1, 1\'bz, 1\'b1, 1\'bz, 1\'b1, 1\'b1)) failed = 1; + #1; #0 if (!check(1\'bz, 1\'bz, 1\'b1, 1\'bz, 1\'b1, 1\'bz)) failed = 1; + #1; #0 if (!check(1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'b1, 1\'bz)) failed = 1; + #1; #0 if (!check(1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bz)) failed = 1; + + #1; + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"/* + * Bug report: + * + * From: Hendrik + * Subject: gEDA: Pass array element into module in iverilog 0.5 + * To: geda-dev@seul.org + * Date: Mon, 10 Sep 2001 11:53:04 +0800 + */ + +module top; + reg [6:0] x[2:0]; + + speak i0 (x[0], x[1], x[2]); + + initial + begin + #10 x[0] = 0; + x[1] = 0; + x[2] = 0; + #100 x[0] = 1; + #100 x[0] = 0; + x[1] = 1; + #100 x[1] = 0; + x[2] = 1; + #100 $finish; + end +endmodule + +module speak(x1, x2, x3); + input [6:0] x1, x2, x3; + always #100 + $display (""%d: x1=%d, x2=%d, x3=%d"", $time, x1, x2, x3); + + integer\t errors; + initial + begin +\terrors = 0; +\t#100 if (x1 !== 7\'b0 || x2 !== 7\'b0 || x3 !== 7\'b0) +\t begin errors = errors + 1; $display(""FAILED""); end +\t#100 if (x1 !== 7\'b1 || x2 !== 7\'b0 || x3 !== 7\'b0) +\t begin errors = errors + 1; $display(""FAILED""); end +\t#100 if (x1 !== 7\'b0 || x2 !== 7\'b1 || x3 !== 7\'b0) +\t begin errors = errors + 1; $display(""FAILED""); end +\t#100 if (x1 !== 7\'b0 || x2 !== 7\'b0 || x3 !== 7\'b1) +\t begin errors = errors + 1; $display(""FAILED""); end +\tif (errors === 0) +\t $display(""PASSED""); + end + +endmodule +" +" +/* + * This is a post-synthesis test for the blif_shift.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif_shift.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif_shift_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter W=3; + reg [W:0] D; + reg [W:0] S; + + parameter WO=5; + wire [WO:0] SHL; + wire [WO:0] SHR; + wire [WO:0] ASHL; + wire [WO:0] ASHR; + reg [WO:0] shl; + reg [WO:0] shr; + reg [WO:0] ashl; + reg [WO:0] ashr; + +`ifdef DUMMY + shift ss(.D (D), .S (S), .SHL (SHL), .SHR (SHR), .ASHL (ASHL), .ASHR (ASHR)); +`else + shift ss(.\\D[3] (D[3]), .\\D[2] (D[2]), .\\D[1] (D[1]), .\\D[0] (D[0]), + .\\S[3] (S[3]), .\\S[2] (S[2]), .\\S[1] (S[1]), .\\S[0] (S[0]), + .\\SHL[5] (SHL[5]), .\\SHL[4] (SHL[4]), .\\SHL[3] (SHL[3]), .\\SHL[2] (SHL[2]), .\\SHL[1] (SHL[1]), .\\SHL[0] (SHL[0]), + .\\SHR[5] (SHR[5]), .\\SHR[4] (SHR[4]), .\\SHR[3] (SHR[3]), .\\SHR[2] (SHR[2]), .\\SHR[1] (SHR[1]), .\\SHR[0] (SHR[0]), + .\\ASHL[5] (ASHL[5]), .\\ASHL[4] (ASHL[4]), .\\ASHL[3] (ASHL[3]), .\\ASHL[2] (ASHL[2]), .\\ASHL[1] (ASHL[1]), .\\ASHL[0] (ASHL[0]), + .\\ASHR[5] (ASHR[5]), .\\ASHR[4] (ASHR[4]), .\\ASHR[3] (ASHR[3]), .\\ASHR[2] (ASHR[2]), .\\ASHR[1] (ASHR[1]), .\\ASHR[0] (ASHR[0])); +`endif + + int\t\t ddx; + int\t\t sdx; + initial begin + for (ddx = 0 ; ddx < 1 << (W+1) ; ddx = ddx+1) + for (sdx = 0 ; sdx < WO + 2 ; sdx = sdx+1) begin +\t D = ddx[W:0]; +\t S = sdx[W:0]; + + shl = D << S; + shr = D >> S; + ashl = $signed(D) <<< S; + ashr = $signed(D) >>> S; + +// $display(""D = %b, S = %b"", D, S); +// $display(""shl = %b, shr = %b"", shl, shr); +// $display(""ashl = %b, ashr = %b"", ashl, ashr); + + #1; +\t if (SHL !== shl) begin +\t $display(""FAILED -- D=%b, S=%b, SHL=%b (should be %b)"", D, S, SHL, shl); +\t $finish; + end +\t if (SHR !== shr) begin +\t $display(""FAILED -- D=%b, S=%b, SHR=%b (should be %b)"", D, S, SHR, shr); +\t $finish; + end +\t if (ASHL !== ashl) begin +\t $display(""FAILED -- D=%b, S=%b, ASHL=%b (should be %b)"", D, S, ASHL, ashl); +\t $finish; + end +\t if (ASHR !== ashr) begin +\t $display(""FAILED -- D=%b, S=%b, SHL=%b (should be %b)"", D, S, ASHR, ashr); +\t $finish; + end + end + $display(""PASSED""); + end + +endmodule // main +" +"/* + * Based on Request id 1313366 in the iverilog Bugs database, or + * pr699 in the ivl-bugs database. + * Modified to force the comparison net. + */ +module bug; + +wire a, b, c, d; + +assign c = 1\'b0; +assign a = 1\'b1; +assign b = 1\'b0; + +assign d = c ? a : b; + +initial + begin + force c = 1\'b1; + #1 if (c !== 1\'b1) begin + $display(""FAILED -- b = %b"", b); + $finish; + end + + if (d !== 1\'b1) begin + $display(""FAILED -- d = %b"", d); + $finish; + end + + release c; + $display(""PASSED""); + $finish; + end + +endmodule // bug +" +"module bug05_integerRem; + +reg passed; + +reg signed[31:0] reg0; +reg signed[31:0] reg1; +reg signed[31:0] rrem; +wire signed[31:0] dividend=reg0; +wire signed[31:0] divisor=reg1; +wire signed[31:0] remainder; + +assign remainder= dividend%divisor; + +initial begin +\tpassed = 1\'b1; +\treg0=32\'hffffffff; +\treg1=32\'h0d1f0796; +\t//BUG here: remainder==32\'h06b26fdd, should be 32\'hffffffff +\t#1 if (remainder !== 32\'hffffffff) begin +\t\t$display(""Failed: CA remainder, expected 32\'hffffffff, got %h"", +\t\t remainder); +\t\tpassed = 1\'b0; +\tend + + rrem = reg0 % reg1; +\t#1 if (rrem !== 32\'hffffffff) begin +\t\t$display(""Failed: remainder, expected 32\'hffffffff, got %h"", +\t\t rrem); +\t\tpassed = 1\'b0; +\tend + +\tif (passed) $display(""PASSED""); +end + +endmodule +" +"module top; + + // packed 2D array, arranged as 4 bytes of 8 bits each. + logic [3:0][7:0] word32; + int\t\t idx; + int\t\t x; + + // Show a slice select in a continuous assignment + wire [7:0]\t word1 = word32[1]; + + initial begin + // Const slice select in l-values. + word32[0] = \'h00; + word32[1] = \'h11; + word32[2] = \'h22; + word32[3] = \'h33; + + if (word32 !== \'h33_22_11_00) begin +\t $display(""FAILED -- word32 = %h (1)"", word32); +\t $finish; + end + + #1 if (word1 !== 8\'h11) begin +\t $display(""FAILED -- word1 = %h"", word1); +\t $finish; + end + + // Non-constant slice indices, l-value and r-value. + for (idx = 0 ; idx < 4 ; idx = idx+1) +\tword32[idx] = ~word32[idx]; + + if (word32 !== ~ \'h33_22_11_00) begin +\t $display(""FAILED -- word32 = %h (2)"", word32); +\t $finish; + end + + word32[0][3:0] = \'h0; + word32[1][3:0] = \'h1; + word32[2][3:0] = \'h2; + word32[3][3:0] = \'h3; + + word32[0][7:4] = \'h3; + word32[1][7:4] = \'h2; + word32[2][4 +: 4] = \'h1; + word32[3][4 +: 4] = \'h0; + + if (word32 !== \'h03_12_21_30) begin +\t $display(""FAILED -- word32 = %h (3)"", word32); +\t $finish; + end + + if (word32[1][7:4] !== word32[1][4 +: 4]) begin +\t $display(""FAILED -- word32[1][7:4]=%h, word32[1][4 +: 4]=%h"", +\t\t word32[1][7:4],word32[1][4 +: 4]); +\t $finish; + end + + x = 4; + word32[1][x +: 4] = \'h2; + if (word32[1][7:4] !== word32[1][x +: 4]) begin +\t $display(""FAILED -- word32[1][7:4]=%h, word32[1][4 +: 4]=%h"", +\t\t word32[1][7:4],word32[1][x +: 4]); +\t $finish; + end + + for (idx = 0 ; idx < 8 ; idx = idx+1) begin +\t word32[0][idx] = idx[0]; +\t word32[2][idx] = idx[0]; +\t word32[1][idx] = ~idx[0]; +\t word32[3][idx] = ~idx[0]; + end + + if (word32 !== \'h55_aa_55_aa) begin +\t $display(""FAILED -- word32 = %h (4)"", word32); +\t $finish; + end + + for (idx = 0 ; idx < 8 ; idx = idx+1) begin +\t if (word32[0][idx] !== word32[2][idx]) begin +\t $display(""FAILED -- word32[0][%0d]=%b, word32[2][%0d]=%b"", +\t\t idx, word32[0][idx], idx, word32[2][idx]); +\t $finish; +\t end +\t if (word32[1][idx] !== word32[3][idx]) begin +\t $display(""FAILED -- word32[1][%0d]=%b, word32[3][%0d]=%b"", +\t\t idx, word32[1][idx], idx, word32[3][idx]); +\t $display(""FAILED""); +\t $finish; +\t end + end + + $display(""PASSED""); + end + +endmodule +" +"// When registering a simulation time callback, some simulators interpret +// the specified time value as relative to the current simulation time. To +// support this case, define the macro CB_TIME_IS_RELATIVE when compiling +// this module. + +module main; + + integer val; + + initial begin + val = 0; + #1 $poke_at_simtime(val, 1, 10); + +`ifdef CB_TIME_IS_RELATIVE + #1; +`endif + #8 if (val !== 0) begin +\t $display(""FAILED -- val==%0d before delayed poke"", val); +\t $finish; + end + + #1 if (val !== 1) begin +\t $display(""FAILED -- val==%0d: poke didn\'t happen"", val); +\t $finish; + end + + $display(""PASSED""); + $finish(0); + end + +endmodule // main +" +"/* + * This tests the latching of an output that isn\'t really an output, + * but an intermediate symbol that is only used in some clauses. + */ +module main; + + reg [15:0] out, a; + reg [7:0] b; + reg\t cy; + reg\t with_carry; + + (* ivl_combinational *) + always @(with_carry, a, b, cy) + if (with_carry) begin +\t{cy, out[7:0]} = {1\'b0, a[7:0]} + {1\'b0, b[7:0]}; +\tout[15:8] = a[15:8] + {7\'b0, cy}; + end else begin +\tout = a + {8\'h00, b}; + end + + (* ivl_synthesis_off *) + initial begin + a = 16\'h00fe; + b = 8\'h00; + with_carry = 0; + #1 if (out !== 16\'h00fe) begin +\t $display(""FAILED -- a=%h, b=%h, out=%h"", a, b, out); +\t $finish; + end + + with_carry = 1; + #1 if (out !== 16\'h00fe) begin +\t $display(""FAILED -- a=%h, b=%h, out=%h"", a, b, out); +\t $finish; + end + + b = 2; + #1 if (out !== 16\'h0100) begin +\t $display(""FAILED -- a=%h, b=%h, out=%h"", a, b, out); +\t $finish; + end + + with_carry = 0; + #1 if (out !== 16\'h0100) begin +\t $display(""FAILED -- a=%h, b=%h, out=%h"", a, b, out); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"`begin_keywords ""1364-2005"" +/* + * This program is based on PR#1077. + * + * Expected output: + * one + * y = x + * one + * y = 1 + * one + * y = 1 + */ +module bool; + +reg clk,y; +reg [31:0] count; + +initial clk=0; +always #2.5 clk = ~clk; + +initial begin +\tcount = \'h8; +\t#20 +\t$finish(0); +end + +always @(posedge clk) +begin +\t// BUG: this should eval to ""1"" but does not! +\ty <= count[10] || ~count[5:3]; + +\t// this should print ""one"" and does +\tif(count[10] || ~(count[5:3])) +\t\t$display(""one""); +\telse +\t\t$display(""zero""); +\t$display(""y = %b"",y); + +end + +endmodule +`end_keywords +" +"module main; + + function [15:0] sum; + input [15:0] a; + input [15:0] b; + + sum = a + b; + endfunction // sum + + reg\t\t clk; + reg [15:0]\t d, e, out; + (* ivl_synthesis_on *) + always @(posedge clk) + out <= sum(d, e); + + + initial begin + clk = 0; + d = 0; + e = 0; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 16\'d0) begin +\t $display(""FAILED -- sum(%0d,%d) --> %0d"", d, e, out); +\t $finish; + end + + d = 5; + e = 13; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 16\'d18) begin +\t $display(""FAILED -- sum(%0d,%d) --> %0d"", d, e, out); +\t $finish; + end + + $display(""PASSED""); + $finish; + end +endmodule // main +" +"`define PREFIX_\t\tmy_prefix_ +`define SUFFIX\t\tmy_suffix + +`define BACKTICK\t""`"" + +`define name1\t\t`PREFIX``_```SUFFIX +`define name2(p,s)\tp``_``s + +`define stringify(text)\t`""text`"" + +module test(); + +initial begin + $display(`BACKTICK); + $display(`stringify(`name1)); + $display(`stringify(`name2(`PREFIX, `SUFFIX))); +end + +endmodule +" +"// Copyright C(O) 2004 Burnell G West +// The following text may be utilized and / or reproduced by anybody for +// any reason. +// +// verr.v +// + +module verr (clk, vout); + +input clk; +output vout; + +reg vout; +real start_edge; +real end_edge; + +wire trigger_en; +wire [9:0] v_value; + +initial vout = 1\'b0; + +always @( posedge clk) + begin + if (trigger_en) + begin + start_edge = ( v_value[0] * 1.95) + + ( v_value[1] * 3.9 ) + + ( v_value[2] * 7.8 ) + + ( v_value[3] * 15.6 ) + + ( v_value[4] * 31.2 ) + + ( v_value[5] * 62.5 ) + + ( v_value[6] * 125 ) + + ( v_value[7] * 250 ) + + ( v_value[8] * 0 ) + + ( v_value[9] * 0 ) + + 0; + end_edge = start_edge + 100; // make pulse width = 1ns + end + else + begin + start_edge <= start_edge; + end_edge <= end_edge; + end + end + +endmodule + +module vtest; + +wire vout0, vout1, vout2, vout3, vout4, vout5, vout6, vout7, vout8, vout9; +wire vout10, vout11, vout12, vout13, vout14, vout15, vout16, vout17, +vout18, vout19; + +reg clk, bit0; + +verr v0 (clk, vout0); +verr v1 (clk, vout1); +verr v2 (clk, vout2); +verr v3 (clk, vout3); +verr v4 (clk, vout4); +verr v5 (clk, vout5); +verr v6 (clk, vout6); +verr v7 (clk, vout7); +verr v8 (clk, vout8); +verr v9 (clk, vout9); +verr v10 (clk, vout10); +verr v11 (clk, vout11); +verr v12 (clk, vout12); +verr v13 (clk, vout13); +verr v14 (clk, vout14); +verr v15 (clk, vout15); +verr v16 (clk, vout16); +verr v17 (clk, vout17); +verr v18 (clk, vout18); +verr v19 (clk, vout19); + +initial begin + #10000 $display(""This test doesn\'t check itself.""); + $display(""PASSED""); +end + +endmodule +" +"/* + * land3 - a verilog test for logical and operator && in a conditional. + * + * Copyright (C) 1999 Stephen G. Tell + * Portions inspired by qmark.v by Steven Wilson (stevew@home.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ + +module land3; + + reg Clk; + reg a; + reg b; + reg c; + reg error; + + wire q; + wire q_calc; + + tand tand_m(q,q_calc, a, b, c); + + initial Clk = 0; + always #10 Clk = ~Clk; + + always @(posedge Clk) + begin + #1 ; + if(q != q_calc) + begin + $display(""FAILED - Cond && failed for vect %b%b%b - was %b, s/b %b"", + a,b,c,q,q_calc); + error = 1; + end + end + + + reg [3:0] bvec; + integer xa, xb, xc; + initial begin + error = 0; + bvec = 4\'bzx10 ; + for(xa = 0; xa < 4; xa = xa + 1) +\t for(xb = 0; xb < 4; xb = xb + 1) +\t for(xc = 0; xc < 4; xc = xc + 1) +\t begin +\t\t @(posedge Clk) +\t\t a = bvec[xa]; +\t\t b = bvec[xb]; +\t\t c = bvec[xc]; +\t end // for (var3 = 0; var3 <= 3; var3 = var3 + 1) + @(posedge Clk) ; + @(posedge Clk) ; + if(error == 0) + $display(""PASSED""); + $finish; + end + +endmodule + +module tand(q, q_calc, a, b, c); + output q; + output q_calc; + input a; + input b; + input c; + + reg\t q; + reg q_calc; + + always @(a or b or c) begin + if(a===b && b===c) +\t q <= 1; + else +\t q <= 0; + end // always @ (a or b or c) + + // Added to allow 2nd calculation + // We use the if (a === b) formulation - it\'s part + // of the base set that is need to do ANY tests.. + always @(a or b or c) + begin + if( a===b) + begin + if(b === c) + q_calc = 1\'b1; + else + q_calc = 1\'b0; + end + else + q_calc = 1\'b0; + end + +endmodule // foo +" +"/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test checks that times within modules are scaled up to the + * precision of the simulation. + */ + +`timescale 100us / 1us +module slow (out); + output out; + reg\t out; + + initial begin + #0 out = 0; + #1 out = 1; + end + +endmodule // slow + + +`timescale 10us / 1us +module fast (out); + output out; + reg\t out; + + initial begin + #0 out = 0; + #1 out = 1; + end + +endmodule // fast + +`timescale 1us / 1us +module main; + + wire slow, fast; + + slow m1 (slow); + fast m2 (fast); + + initial begin + #5 +\tif (slow !== 1\'b0) begin +\t $display(""FAILED""); +\t $finish; +\tend + + if (fast !== 1\'b0) begin +\t $display(""FAILED""); +\t $finish; +\tend + + #10 +\tif (slow !== 1\'b0) begin +\t $display(""FAILED""); +\t $finish; +\tend + + if (fast !== 1\'b1) begin +\t $display(""FAILED""); +\t $finish; +\tend + + #80 +\tif (slow !== 1\'b0) begin +\t $display(""FAILED""); +\t $finish; +\tend + + if (fast !== 1\'b1) begin +\t $display(""FAILED""); +\t $finish; +\tend + + #10 +\tif (slow !== 1\'b1) begin +\t $display(""FAILED""); +\t $finish; +\tend + + if (fast !== 1\'b1) begin +\t $display(""FAILED""); +\t $finish; +\tend + + $display(""PASSED""); + + end // initial begin +endmodule // main +" +"/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This sample tests that the supply0 and supply1 nets take on + * the proper initial value. + */ + +module test; + + supply0 gnd; + supply1 vdd; + + initial begin + #1; + if (gnd !== 0) begin +\t $display(""FAILED -- gnd == %b"", gnd); +\t $finish; + end + + if (vdd !== 1) begin +\t $display(""FAILED -- vdd == %b"", vdd); +\t $finish; + end + + $display(""PASSED""); + end +endmodule +" +"// Regression test for bug reported by Niels Moeller on 21-Mar-2015 via +// iverilog-devel mailing list. Extended to cover similar problems. This +// is just testing compiler error recovery. + +module test(); + +integer array[3:0]; + +integer i1; + +always @* begin + for (i1 = 0; i1 < 4; i1 = i1 + 1) begin + array[i1] = undeclared; + end +end + +integer i2; + +always @* begin + for (i2 = 0; i2 < 4; i2 = i2 + 1) begin + undeclared = array[i2]; + end +end + +integer i3; + +always @* begin + for (i3 = undeclared; i3 < 4; i3 = i3 + 1) begin + array[i3] = i3; + end +end + +integer i4; + +always @* begin + for (i4 = 0; i4 < undeclared; i4 = i4 + 1) begin + array[i4] = i4; + end +end + +integer i5; + +always @* begin + for (i5 = 0; i5 < 4; i5 = i5 + undeclared) begin + array[i5] = i5; + end +end + +integer i6; + +always @* begin + i6 = 0; + while (i6 < undeclared) begin + array[i6] = i6; + i6 = i6 + 1; + end +end + +integer i7; + +always @* begin + i7 = 0; + while (i7 < 4) begin + array[i7] = undeclared; + i7 = i7 + 1; + end +end + +integer i8; + +always @* begin + i8 = 0; + repeat (undeclared) begin + array[i8] = i8; + i8 = i8 + 1; + end +end + +integer i9; + +always @* begin + i9 = 0; + repeat (4) begin + array[i9] = undeclared; + i9 = i9 + 1; + end +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate constant multiplication in array define. +// +// + +module main (); + +reg [5 * 2: 0] val1; +reg [10\'h1 * 10: 0 ] val2 ; + +initial + begin + val1 = 11\'h1 * 5; + val2 = 11\'h2 * 4; + if((val1 === 11\'h5) && (val2 === 11\'h8)) + $display(""PASSED""); + else + $display(""FAILED""); + end + +endmodule +" +"module top; + + wire clock, clock_2x, reset, phase; + + phaser ph(.clock_1x(clock), .clock_2x(clock_2x), reset, phase); + phaser ph2(.clock_1x(clock), .clock_2x(clock_2x), reset, .phase(phase)); +endmodule + +module phaser(clock_1x, clock_2x, reset, phase); + input clock_1x, clock_2x, reset; + output phase; +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate function w/ single input + +module main (); + +reg [31:0] val1,val2 ; +reg error; + +function [31:0] myfunc ; + input [31:0] in1 ; + myfunc = in1 ; +endfunction + +initial + begin + error = 0; + val1 = myfunc(32\'h0) ; + if(val1 != 32\'h0) + begin + $display(""FAILED - function3.11B - func(lit) != lit ""); + error = 1; + end + + val2 = 32\'h12345678 ; + val1 = myfunc(val2); + if(val1 != val2) + begin + $display(""FAILED - function3.11B - func(reg var) != reg var ""); + error = 1; + end + + if(myfunc(32\'h10101010) != 32\'h10101010) + begin + $display(""FAILED - function3.11B - if(func(reg var) != reg var) ""); + error = 1; + end + + if(error == 0) + $display(""PASSED""); + end + +endmodule // main +" +"module top; + parameter parg0 = 0.0; + parameter parg1 = 1.0; + parameter parg2 = 2.0; + parameter pargi = 1.0/0.0; // Inf. + parameter pargn = $sqrt(-1.0); // NaN. + real arg0, arg1, arg2, argi, argn; + reg pass; + + wire r_p0_b = !parg0; + wire r_p1_b = !parg1; + wire r_p2_b = !parg2; + wire r_pi_b = !pargi; + wire r_pn_b = !pargn; + + wire r_0_b = !arg0; + wire r_1_b = !arg1; + wire r_2_b = !arg2; + wire r_i_b = !argi; + wire r_n_b = !argn; + + wire r_p01_a = parg0 && parg1; + wire r_p02_a = parg0 && parg2; + wire r_p12_a = parg1 && parg2; + + wire r_01_a = arg0 && arg1; + wire r_02_a = arg0 && arg2; + wire r_12_a = arg1 && arg2; + + wire r_p00_o = parg0 || 0; + wire r_p01_o = parg0 || parg1; + wire r_p02_o = parg0 || parg2; + + wire r_00_o = arg0 || 0; + wire r_01_o = arg0 || arg1; + wire r_02_o = arg0 || arg2; + + wire r_p0_t = parg0 ? 1\'b1 : 1\'b0; + wire r_p1_t = parg1 ? 1\'b1 : 1\'b0; + wire r_p2_t = parg2 ? 1\'b1 : 1\'b0; + wire r_pi_t = pargi ? 1\'b1 : 1\'b0; + wire r_pn_t = pargn ? 1\'b1 : 1\'b0; + + wire r_0_t = arg0 ? 1\'b1 : 1\'b0; + wire r_1_t = arg1 ? 1\'b1 : 1\'b0; + wire r_2_t = arg2 ? 1\'b1 : 1\'b0; + wire r_i_t = argi ? 1\'b1 : 1\'b0; + wire r_n_t = argn ? 1\'b1 : 1\'b0; + + initial begin + pass = 1\'b1; + + arg0 = 0.0; + arg1 = 1.0; + arg2 = 2.0; + argi = 1.0/0.0; // Inf. + argn = $sqrt(-1.0); // NaN. + + #1; + + /* Check ! on a constant real value. */ + if (r_p0_b !== 1\'b1) begin + $display(""Failed: CA constant !0.0, expected 1\'b1, got %b"", r_p0_b); + pass = 1\'b0; + end + + if (r_p1_b !== 1\'b0) begin + $display(""Failed: CA constant !1.0, expected 1\'b0, got %b"", r_p1_b); + pass = 1\'b0; + end + + if (r_p2_b !== 1\'b0) begin + $display(""Failed: CA constant !2.0, expected 1\'b0, got %b"", r_p2_b); + pass = 1\'b0; + end + + if (r_pi_b !== 1\'b0) begin + $display(""Failed: CA constant !Inf, expected 1\'b0, got %b"", r_pi_b); + pass = 1\'b0; + end + + if (r_pn_b !== 1\'b0) begin + $display(""Failed: CA constant !NaN, expected 1\'b0, got %b"", r_pn_b); + pass = 1\'b0; + end + + /* Check ! on a real variable. */ + if (r_0_b !== 1\'b1) begin + $display(""Failed: !0.0, expected 1\'b1, got %b"", r_0_b); + pass = 1\'b0; + end + + if (r_1_b !== 1\'b0) begin + $display(""Failed: !1.0, expected 1\'b0, got %b"", r_1_b); + pass = 1\'b0; + end + + if (r_2_b !== 1\'b0) begin + $display(""Failed: !2.0, expected 1\'b0, got %b"", r_2_b); + pass = 1\'b0; + end + + if (r_i_b !== 1\'b0) begin + $display(""Failed: !Inf, expected 1\'b0, got %b"", r_i_b); + pass = 1\'b0; + end + + if (r_n_b !== 1\'b0) begin + $display(""Failed: !NaN, expected 1\'b0, got %b"", r_n_b); + pass = 1\'b0; + end + + /* Check && on a constant real value. */ + if (r_p01_a !== 1\'b0) begin + $display(""Failed: constant 0.0 && 1.0, expected 1\'b0, got %b"", r_p01_a); + pass = 1\'b0; + end + + if (r_p02_a !== 1\'b0) begin + $display(""Failed: constant 0.0 && 2.0, expected 1\'b0, got %b"", r_p02_a); + pass = 1\'b0; + end + + if (r_p12_a !== 1\'b1) begin + $display(""Failed: constant 1.0 && 2.0, expected 1\'b1, got %b"", r_p12_a); + pass = 1\'b0; + end + + /* Check && on a real variable. */ + if (r_01_a !== 1\'b0) begin + $display(""Failed: 0.0 && 1.0, expected 1\'b0, got %b"", r_01_a); + pass = 1\'b0; + end + + if (r_02_a !== 1\'b0) begin + $display(""Failed: 0.0 && 2.0, expected 1\'b0, got %b"", r_02_a); + pass = 1\'b0; + end + + if (r_12_a !== 1\'b1) begin + $display(""Failed: 1.0 && 2.0, expected 1\'b1, got %b"", r_12_a); + pass = 1\'b0; + end + + /* Check || on a constant real value. */ + if (r_p00_o !== 1\'b0) begin + $display(""Failed: constant 0.0 || 0, expected 1\'b0, got %b"", r_p00_o); + pass = 1\'b0; + end + + if (r_p01_o !== 1\'b1) begin + $display(""Failed: constant 0.0 || 1.0, expected 1\'b1, got %b"", r_p01_o); + pass = 1\'b0; + end + + if (r_p02_o !== 1\'b1) begin + $display(""Failed: constant 0.0 || 2.0, expected 1\'b1, got %b"", r_p02_o); + pass = 1\'b0; + end + + /* Check || on a real variable. */ + if (r_00_o !== 1\'b0) begin + $display(""Failed: 0.0 || 0, expected 1\'b0, got %b"", r_00_o); + pass = 1\'b0; + end + + if (r_01_o !== 1\'b1) begin + $display(""Failed: 0.0 || 1.0, expected 1\'b1, got %b"", r_01_o); + pass = 1\'b0; + end + + if (r_02_o !== 1\'b1) begin + $display(""Failed: 0.0 || 2.0, expected 1\'b1, got %b"", r_02_o); + pass = 1\'b0; + end + + /* Check the ternary with a constant real cond. value. */ + if (r_p0_t !== 1\'b0) begin + $display(""Failed: constant 0.0 ? ..., expected 1\'b0, got %b"", r_p0_t); + pass = 1\'b0; + end + + if (r_p1_t !== 1\'b1) begin + $display(""Failed: constant 1.0 ? ..., expected 1\'b1, got %b"", r_p1_t); + pass = 1\'b0; + end + + if (r_p2_t !== 1\'b1) begin + $display(""Failed: constant 2.0 ? ..., expected 1\'b1, got %b"", r_p2_t); + pass = 1\'b0; + end + + if (r_pi_t !== 1\'b1) begin + $display(""Failed: constant Inf ? ..., expected 1\'b1, got %b"", r_pi_t); + pass = 1\'b0; + end + + if (r_pn_t !== 1\'b1) begin + $display(""Failed: constant NaN ? ..., expected 1\'b1, got %b"", r_pn_t); + pass = 1\'b0; + end + + /* Check the ternary with a real cond. variable. */ + if (r_0_t !== 1\'b0) begin + $display(""Failed: 0.0 ? ..., expected 1\'b0, got %b"", r_0_t); + pass = 1\'b0; + end + + if (r_1_t !== 1\'b1) begin + $display(""Failed: 1.0 ? ..., expected 1\'b1, got %b"", r_1_t); + pass = 1\'b0; + end + + if (r_2_t !== 1\'b1) begin + $display(""Failed: 2.0 ? ..., expected 1\'b1, got %b"", r_2_t); + pass = 1\'b0; + end + + if (r_i_t !== 1\'b1) begin + $display(""Failed: Inf ? ..., expected 1\'b1, got %b"", r_i_t); + pass = 1\'b0; + end + + if (r_n_t !== 1\'b1) begin + $display(""Failed: NaN ? ..., expected 1\'b1, got %b"", r_n_t); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate casex/endcase w/ null_statement - no default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 or val2) + casex (val1 & val2 ) + 3\'b000,3\'b001: result = 0; + 3\'b10x: ; + 3\'b001: result = 1; + endcase + +initial + begin + error = 0; + + val1 = 3\'b0; + val2 = 3\'b0; + if(result !=0) + begin + $display(""FAILED casex 3.9D - lab w/ null expr: ""); + error = 1; + end + + val1 = 3\'b001; + val2 = 3\'b011; + if(result !=1) + begin + $display(""FAILED casex 3.9D - lab w/ null expr: ""); + error = 1; + end + + + val1 = 3\'b111;\t// Should get no-action - expr = 3\'b010 + val2 = 3\'b010; + if(result !=1) + begin + $display(""FAILED casex 3.9D - lab w/ null expr: ""); + error = 1; + end + + if(error == 0) + $display(""PASSED""); + end + +endmodule // main +" +"module automatic_error(); + +reg global; + +task automatic auto_task; + +reg local; + +begin:block + @(local || global); +end + +endtask + +endmodule +" +"/* + * This is the essence of tracker id#1421777. The problem is the error + * message around the ""... dut.tmp"" expression. This probram won\'t + * compile while the reported bug still lives. + */ +module main; + + reg b; + wire a; + // The a.tmp is valid, but tricky because it is an implicit wire. + wire foo = dut.tmp; + X dut(a, b); + + initial begin + b = 0; + #1 $display(""a=%b, tmp=%b"", a, foo); + if (a !== foo) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""PASSED""); + end + +endmodule // main + +module X(output a, input b); + + not (tmp, b); + buf(a, tmp); + +endmodule // X +" +"module test(); + wire a, b; + a__a a_( + .b_buf(b), + .b (a) + ); +endmodule + +module a__a(b_buf, b); +output b_buf; +input b; +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Compound ifdef (two) with interior not defined +// + + +`define DOUBLE +module ifdef1; + +reg error ; + +`ifdef DOUBLE +`ifdef NOCODE +initial + begin + #20; + error = 1; + #20; + end +`endif\t// NOCODE +`endif // DOUBLE + +initial + begin + #1; + error = 0; + #40; + if(error == 0) + $display(""PASSED""); + else + $display(""FAILED""); + end + +endmodule // main +" +"// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for accessing constant records & arrays of records in VHDL. + +module vhdl_const_record_test; +int sel; +logic [7:0] hex; +logic [7:0] aval; +vhdl_const_record dut(sel, hex, aval); + +initial begin + if(dut.sig !== 8\'h66) + begin + $display(""FAILED 1""); + $finish(); + end + + sel = 0; + #1; + if(hex !== 8\'h14 || aval !== 8\'haa || dut.sig2 !== 8\'h00) + begin + $display(""FAILED 2""); + $finish(); + end + + sel = 1; + #1; + if(hex !== 8\'h24 || aval !== 8\'hbb || dut.sig2 !== 8\'h11) + begin + $display(""FAILED 3""); + $finish(); + end + + sel = 2; + #1; + if(hex !== 8\'h34 || aval !== 8\'hcc || dut.sig2 !== 8\'h22) + begin + $display(""FAILED 4""); + $finish(); + end + + sel = 3; + #1; + if(hex !== 8\'h56 || aval !== 8\'hdd || dut.sig2 !== 8\'h33) + begin + $display(""FAILED 5""); + $finish(); + end + + $display(""PASSED""); +end +endmodule + +" +"/*********************************************************************** + + Duplicate input declaration test case + Duplicate port declarations should generate an error + +***********************************************************************/ + +module port_test4 ( +\t\t a,\t\t// Input +\t\t b,\t\t// Output + ); + +input a; +input a; + +output b; + +assign b=a; + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always if ( constant) statement_1 else statement_2 ; + +module main ; + +reg [3:0] value1 ; + +initial +\tbegin + value1 = 0; + # 5 ; + if(value1 != 4\'d4) + $display(""FAILED - always 3.1.5C always if ( constant) statementelse ;""); + else + $display(""PASSED""); +\t $finish; + end + +always if( 1\'b1) begin + # 1; + value1 = value1 + 1; + end + else value1 = 0 ; + +endmodule +" +"/* + * This is based on bug report PR#860. + */ +module stam () ; + + parameter WIDTH_IN = 8; + parameter ABS = 0; + parameter M = (!ABS) ? 7 : WIDTH_IN; + + parameter AFTER_DC_WIDTH = M; + + initial begin + $display(""AFTER_DC_WIDTH=%d"", AFTER_DC_WIDTH); + if (AFTER_DC_WIDTH !== 7) begin +\t $display(""FAILED -- M = %d"", M); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // stam +" +"module top; + reg [8:1] val; + wire [1:4] wval; + reg [3:0] wdrv; + real r_arr [1:8]; + integer i_arr [8:1]; + integer lp; + + assign wval = wdrv; + + initial begin + wdrv = 4\'b1010; + for (lp=1; lp<=8; lp=lp+1) begin + val[lp] = lp % 2; + r_arr[lp] = lp + 0.25; + i_arr[lp] = lp - 1; + end + + #1; + $check_val(val, 3, 1); + $check_val(wval, 4, 0); + $check_val(r_arr, 5, 5.25); + $check_val(i_arr, 2, 1); + $display(""Original value is %b"", val); + $put_val(val, 2, 1); + $put_val(val, 1, 0); + $display("" New value is %b"", val); + $display(""Original net value is %b"", wval); + $put_val(wval, 2, 1); + $put_val(wval, 1, 0); + $display("" New net value is %b"", wval); + #1; + // Verify that an update overrides the put value + wdrv = 4\'b1001; + $display("" net value is now %b"", wval); + end + +endmodule +" +"module top; + reg [7:0] val; + reg [3:0] idx; + reg [7:0] res; + + initial begin + val = 8\'hff; + idx = 4\'bx; + $sformat(res, ""%b"", val[idx]); + if (res !== ""x"") $display(""Failed: expected \'bx , got \'b%s"", res); + else $display(""PASSED""); + end +endmodule +" +"module top; + integer correct, incorrect; + reg [5:0] bits; + + initial begin + bits = 32; + incorrect = -180 + bits*(360.0/63.0); + correct = bits*(360.0/63.0) - 180; + $display(""Both of these should be the same (3): %3d, %3d"", incorrect, + correct); + $finish(0); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate defparam + +module module_a (out0,in0); + +input\t\tin0; +output [5:0]\tout0; + +parameter [5:0] ident0 = 0; +parameter [5:0] ident1 = 5\'h11; + +reg [5:0] out0; + +// Basic MUX switches on in0 +always @ (in0) + begin + if(in0) + out0 = ident0; + else + out0 = ident1; + end + +endmodule // module_a + +module module_b (out0,out1,in0,in1); + +input\t\tin0; +input\t\tin1; +output [5:0]\tout0; +output [5:0]\tout1; + +module_a testmodA (.out0(out0),.in0(in0)); +module_a testmodB (.out0(out1),.in0(in1)); + +endmodule // module_b + +module main (); + +reg in0,in1; +reg\t error; +wire [5:0] out0,out1; + +defparam NameB.testmodA.ident0 = 5\'h4; +defparam NameB.testmodB.ident0 = 5\'h5; +defparam NameB.testmodB.ident1 = 5\'h6; + +module_b NameB (.out0(out0),.out1(out1), + .in0(in0),.in1(in1)); + + +initial + begin + error = 0; + #1 ; + in0 = 0; + #1 ; + if(out0 != 5\'h11) + begin + $display(""FAILED - defparam3.5A - Defparam testmodA.ident0""); + $display(""out0 = %h"",out0); + error = 1; + end + #1 ; + in0 = 1; + #1 ; + if(out0 != 5\'h4) + begin + $display(""FAILED - defparam3.5A - Defparam testmodA.ident0""); + error = 1; + end + #1; + in1 = 0; + #1; + if(out0 != 5\'h4)\t// Validate the 0 side didn\'t change! + begin + $display(""FAILED - defparam3.5A - Defparam testmodA.ident0""); + error = 1; + end + if(out1 != 5\'h6) + begin + $display(""FAILED - defparam3.5A - Defparam testmodB.ident1""); + error = 1; + end + #1; + in1 = 1; + #1; + if(out1 != 5\'h5) + begin + $display(""FAILED - defparam3.5A - Defparam testmodB.ident0""); + error = 1; + end + + + if(error == 0) + $display(""PASSED""); + end +endmodule // main +" +"// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +// Test for $sformatf system function. + +module ivl_sformatf_test; +wire test_net; +assign (pull1, strong0) test_net = 1\'b1; + +struct packed { + logic [15:0] high; + logic [15:0] low; +} word; + +initial begin + string f; + word = 32\'b0101_0101_0101_0101_0101_0101_0101_0101; + + // Test constant values + // Integers + f = $sformatf(""sformatf test 1: %b %d %o %x"", 8\'d120, -12, 331, 120, 97); + if(f != ""sformatf test 1: 01111000 -12 00000000513 00000078 97"") begin + $display(f); + $display(""FAILED 1""); + $finish(); + end + + // Floats + f = $sformatf(""sformatf test 2: %e %f %g"", 123.45, 100e12, 100e12); + if(f != ""sformatf test 2: 1.234500e+02 100000000000000.000000 1e+14"") begin + $display(f); + $display(""FAILED 2""); + $finish(); + end + + // Strings + f = $sformatf(""sformatf test 3: %s %c"", ""\'string test\'"", 97); + if(f != ""sformatf test 3: \'string test\' a"") begin + $display(f); + $display(""FAILED 3""); + $finish(); + end + + // Other stuff + f = $sformatf(""sformatf test 4: %t %v %u %z"", 120s, test_net, word, word); + if(f != ""sformatf test 4: 120 Pu1 UUUU UUUU"") begin + $display(f); + $display(""FAILED 4""); + $finish(); + end + + $display(""PASSED""); +end +endmodule +" +"/* + * Copyright (c) 1999 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +primitive BUFG ( O, I ); + output O; + input I; + table + 0 : 0 ; + 1 : 1 ; + endtable +endprimitive + +module main; + wire out; + reg in; + + BUFG #5 bg(out, in); + + initial begin + in = 0; + #10 if (out !== 0) begin +\t $display(""FAILED -- %b != 0"", out); +\t $finish; + end + in = 1; + #4 if (out !== 0) begin +\t $display(""FAILED -- %b != 0"", out); +\t $finish; + end + #2 if (out !== 1) begin +\t $display(""FAILED -- %b != 1"", out); +\t $finish; + end + $display(""PASSED""); + end +endmodule +" +"module baz; + parameter Q = 10; +endmodule + +module bar; + parameter P = 1; + baz #(P+1) baz1(); +endmodule + +module foo; + bar #3 bar1(); + initial + $display(""PASSED""); +endmodule +" +"`timescale 1us / 1ns + +module usns; + initial begin +\t#123; +\t$mytest; + end +endmodule + +`timescale 1ns / 1ns + +module nsns; + initial begin +\t#456; +\t$mytest; + end +endmodule +" +"module br993a(); + +reg clk; +reg a; +reg b; +reg [1:0] q; + +(* ivl_synthesis_on *) +always @(posedge clk) begin + if (a) q <= 1; + if (b) q <= 2; +end +(* ivl_synthesis_off *) + +reg failed; +initial begin + clk = 0; + + a = 1; + b = 1; + #1 clk = 1; + #1 clk = 0; + $display(""%d"", q); + if (q !== 2\'d2) failed = 1; + + a = 0; + b = 0; + #1 clk = 1; + #1 clk = 0; + $display(""%d"", q); + if (q !== 2\'d2) failed = 1; + + a = 1; + b = 0; + #1 clk = 1; + #1 clk = 0; + $display(""%d"", q); + if (q !== 2\'d1) failed = 1; + + a = 0; + b = 0; + #1 clk = 1; + #1 clk = 0; + $display(""%d"", q); + if (q !== 2\'d1) failed = 1; + + a = 0; + b = 1; + #1 clk = 1; + #1 clk = 0; + $display(""%d"", q); + if (q !== 2\'d2) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module top; + reg pass; + reg result; + reg [3:0] expr; + + initial begin + pass = 1\'b1; + + result = $onehot(1\'b0); + if (result != 0) begin + $display(""FAILED: for 1\'b0 expected 0, got %b"", result); + pass = 1\'b0; + end + + result = $onehot(1\'b1); + if (result != 1) begin + $display(""FAILED: for 1\'b1 expected 1, got %b"", result); + pass = 1\'b0; + end + + result = $onehot(2\'b01); + if (result != 1) begin + $display(""FAILED: for 2\'b01 expected 1, got %b"", result); + pass = 1\'b0; + end + + result = $onehot(4\'b0x11); + if (result != 0) begin + $display(""FAILED: for 4\'b0x11 expected 0, got %b"", result); + pass = 1\'b0; + end + + expr = 4\'b1100; + result = $onehot(expr); + if (result != 0) begin + $display(""FAILED: for 4\'b1100 expected 0, got %b"", result); + pass = 1\'b0; + end + + result = $onehot(34\'b1100000000000000000000000000000001); + if (result != 0) begin + $display(""FAILED: for 34\'1100000000000000000000000000000001 expected 0, got %b"", result); + pass = 1\'b0; + end + + result = $onehot(34\'b1000000000000000000000000000000000); + if (result != 1) begin + $display(""FAILED: for 34\'1000000000000000000000000000000000 expected 1, got %b"", result); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end + +endmodule +" +"module check (input unsigned [22:0] a, b, c); + wire [22:0] int_AB; + + assign int_AB = ~(a | b); + +always @(a, b, int_AB, c) begin + #1; + if (int_AB != c) begin + $display(""ERROR""); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [22:0] A, B); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; B= 0; + for (i=0; i %0d"", x); +\t $finish; + end + + x = p2::next_step(0); + if (x != 2) begin +\t $display(""FAILED -- p2::next_step(0) --> %0d"", x); +\t $finish; + end + + $display(""PASSED""); + end +endprogram // main +" +"module testbench(); + wire [3:0] q; + reg clr, clk, enable; + + counter uut(q, clr, clk); + + always @(clk) + if (enable) + #1 clk <= !clk; + + initial begin + enable <= 1; + clk <= 0; + clr <= 1; + #2; + clr <= 0; + #7; + enable <= 0; + if (q == 4\'b0011) + $display(""PASSED""); + else + $display(""FAILED -- counter not correct (%d)"", q); + end + +endmodule // testbench + +module counter(q, clr, clk); + output [3:0] q; + input clr, clk; + reg [3:0] q; + + always @(posedge clk or posedge clr) + if (clr) + q <= 4\'b0000; + else + q <= q + 1\'b1; + +endmodule // counter +" +"module main; + + reg [16:0] in; + wire [15:0] out; + + foo_entity dut (.o_high1(out[15:12]), .o_low1(out[11:8]), +\t\t .o_high0(out[7:4]), .o_low0(out[3:0]), + +\t\t .i_high1(in[15:12]), .i_low1(in[11:8]), +\t\t .i_high0(in[7:4]), .i_low0(in[3:0])); + + initial begin + for (in = 0 ; in < 256 ; in = in+1) begin +\t #1 if (in !== out[15:0]) begin +\t $display(""FAILED -- out=%h, in=%h"", out, in); +\t $finish; +\t end + end + $display(""PASSED""); + end + +endmodule // main +" +"`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + parameter [7:0] in = 8\'b10100101; + reg [3:0] out; + + initial begin + pass = 1\'b1; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out = in[7:\'dx]; +`else + out = 4\'bxxxx; +`endif + if (out !== 4\'bxxxx) begin + $display(""FAILED: part select LSB is X, expected 4\'bxxxx, got %b"", out); + pass = 1\'b0; + end + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out = in[\'dx:0]; +`else + out = 4\'bxxxx; +`endif + if (out !== 4\'bxxxx) begin + $display(""FAILED: part select MSB is X, expected 4\'bxxxx, got %b"", out); + pass = 1\'b0; + end + + out = 4\'b0000; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out[0] = in[\'dx]; +`else + out[0] = 1\'bx; +`endif + if (out !== 4\'b000x) begin + $display(""FAILED: bit select is X, expected 4\'b000x, got %b"", out); + pass = 1\'b0; + end + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out = in[7:\'dz]; +`else + out = 4\'bxxxx; +`endif + if (out !== 4\'bxxxx) begin + $display(""FAILED: part select LSB is Z, expected 4\'bxxxx, got %b"", out); + pass = 1\'b0; + end + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out = in[\'dz:0]; +`else + out = 4\'bxxxx; +`endif + if (out !== 4\'bxxxx) begin + $display(""FAILED: part select MSB is Z, expected 4\'bxxxx, got %b"", out); + pass = 1\'b0; + end + + out = 4\'b0000; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out[0] = in[\'dz]; +`else + out[0] = 1\'bx; +`endif + if (out !== 4\'b000x) begin + $display(""FAILED: bit select is Z, expected 4\'b000x, got %b"", out); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"////////////////////////////////////////////////////////////////////////////// +// +// using `timescale, test rounding up to specified precision and +// scaling to specified time unit +// +// run with +// iverilog lrm_eg.v +// vvp a.out +// +// (uncomment $display statements for help in debugging) +// +////////////////////////////////////////////////////////////////////////////// +`timescale 10 ns / 1 ns + +module test; + reg set; + parameter d = 1.55; + reg fail; + reg [7:0] ii; + + initial begin + fail = 0; + #d set = 0; + //$display(""time in units of 10ns: %0t, in ns: %0d, set: %0b"",$time,ii,set); + if((ii < 15) || (ii > 16)) fail = 1; + #d set = 1; + //$display(""time in units of 10ns: %0t, in ns: %0d, set: %0b"",$time,ii,set); + if((ii < 31) || (ii > 32)) fail = 1; + end + + initial begin + //$dumpvars; + for(ii = 0; ii < 50; ii = ii + 1) begin + //$display(""time in ns: %0d, set: %0b"",ii,set); + #0.1; + end + $display(""\ +\\t\\t**********************************************""); + if(fail) $display(""\\t\\t********** timescale test FAILED *************""); + else $display(""\\t\\t********** timescale test PASSED *************""); + $display(""\\t\\t**********************************************\ +""); + $finish(0); + end +endmodule +" +"// Regression test for bug reported by Niels Moeller on +// 15-Mar-2015 via the iverilog-devel mailing list. +module test(); + +wire [7:0] my_net; + +assign my_net[3:0] = 1; +assign my_net[7:4] = 2; + +initial begin + #1 $monitor(""At time %0t, field 1 = %h, field 2 = %h"", + $time, my_net[3:0], my_net[7:4]); + #1 $finish(0); +end + +endmodule +" +"// $abs should take a real argument and return a real result. +module test(); + +localparam s = 0; +localparam a = 1.5; +localparam b = 1; +localparam r = $abs((s ? a : b) / 2); + +initial begin + $display(""%g"", r); + if (r == 0.5) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"// +// Copyright (c) 2000 Stephen Williams (steve@icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// single bit positive events +// + +module main (); + + reg flag1; + reg event_1; + + always @ (posedge event_1) flag1 = ~flag1; + + initial begin + event_1 = 1\'b0; + #1 flag1 = 0; + + #1 event_1 = 1\'b1; + + #1 +\tif (flag1 !== 1\'b1) begin +\t $display(""FAILED -- 0->1 didn\'t trigger flag1""); +\t $finish; +\tend + + event_1 = 1\'b0; + + #1 +\tif (flag1 !== 1\'b1) begin +\t $display(""FAILED -- 1->0 DID trigger flag1""); +\t $finish; +\tend + + $display(""PASSED""); + end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always @ (event_expr) reg_lvalue = constant ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1,value2 ; + +initial +\tbegin + # 1; + if(value1 != 4\'bxxxx) + $display(""FAILED - 3.1.4H - initial value not xxxx;\ +""); + value2 = 4\'h1;\t// Cause @ to execute. + #15 ; + if(value1 != 4\'h5) + $display(""FAILED - 3.1.4H - always @ (event_expression) reg_lvalue = constant ;\ +""); + else + begin +\t\t $display(""PASSED\ +""); +\t\t $finish; + end + end + +always @ (value2) value1 = ~value1; + +endmodule +" +"module test; +reg [63:0] i, j; + +initial +main; +task main; +integer k, l, m, n; +begin +i = 64\'hffff_ffff_ffff_ffff; +j = 64\'hffff_ffff_ffff_fffe; + +k = $signed(i) < $signed(j); +l = $signed(i) <= $signed(j); +m = $signed(i) > $signed(j); +n = $signed(i) >= $signed(j); + +$display(""< : %s"", k? ""Y"":""N""); +$display(""<=: %s"", l? ""Y"":""N""); +$display(""> : %s"", m? ""Y"":""N""); +$display("">=: %s"", n? ""Y"":""N""); +end +endtask +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue <= @ (event_expression) constant +// + +module main ; + +reg [3:0] value1 ; +reg event_var ; + +initial +begin + # 2 ; + value1 = 5\'h 0 ; + # 3 ; + event_var = 1\'b0 ; + # 2 ; + value1 = 5\'h 0 ; + # 3 ; + event_var = 1\'b1 ; + #5 ; +end + +initial + begin\t\t\t// Should be xxxx at initial time + if(value1 !== 4\'bxxxx) +\t$display(""FAILED - always reg_lvalue <= @ (event_expression) constant \ +""); + # 6 ; + if(value1 != 4\'h5)\t// Time 5 should see a change of 0 to 1 +\t$display(""FAILED - always reg_lvalue <= @ event_identifier boolean_expression\ +""); + # 5 ; + if(value1 != 4\'h5)\t// Time 5 should see a change of 0 to 1 +\t$display(""FAILED - always reg_lvalue <= @ event_identifier boolean_expression\ +""); + begin + $display(""PASSED\ +""); + $finish ; + end + end + +always value1 <= @ (event_var) 4\'h5 ; + + +endmodule +" +"module test(); + parameter N_N = 3; + + reg signed [2*N_N-1:0] val_neg; + reg signed [2*N_N-1:0] val_pos; + + + initial + begin +\tval_neg = {{N_N+1{1\'b1}},{N_N-1{1\'b0}}}; +\tval_pos = {{N_N+1{1\'b0}},{N_N-1{1\'b1}}}; +\t#1 $display(""Var %d vs signed(concat) %d"", +\t\t val_neg, +\t\t $signed({{N_N+1{1\'b1}},{N_N-1{1\'b0}}})); +\t$finish(0); + end // initial begin +endmodule // test +" +" +module subN + #(parameter WID = 4) + (input wire [WID-1:0] A, + input wire [WID-1:0] B, + output reg [WID:0] Q + /* */); + + always @(A or B) Q = A - B; + +endmodule // add +" +"module check (input unsigned [22:0] a, b, c); + wire unsigned [22:0] int_AB; + + assign int_AB = a - b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB !== c) begin + $display(""ERROR""); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [22:0] A, B); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; B= 0; + for (i=0; i Z) = (0.1, 0.2); + (EN => Z) = (0.3, 0.4); + endspecify +endmodule + +module ckt (out, in, en); + output out; + input in, en; + + TBUF_X2 dut (.A ( in ) , .EN ( en ) , .Z ( out ) ) ; +endmodule + +module top; + wire out; + reg in, en; + + ckt dut(out, in, en); + + initial begin + $monitor($realtime,,out,""="",in,,en); + $sdf_annotate(""ivltests/br960b.sdf"", dut); + in = 1\'b0; + en = 1\'b0; + $display(""Max (X->Z)""); + // X -> Z = max(enable)) + #10; + en = 1\'b1; + $display(""Fall (Z->0)""); + // Z -> 0 = tf(enable) + #10; + en = 1\'b0; + $display(""To High-Z (0->Z)""); + // 0 -> Z = to High-Z + #5; + in = 1\'b1; + #5; + en = 1\'b1; + $display(""Rise (Z->1)""); + // Z -> 1 = tr(enable) + #10; + en = 1\'b0; + $display(""To High-Z (1->Z)""); + // 1 -> Z = to High-Z + #10; + end +endmodule +" +"module main; + + wire [2:0] value1, value2, value3, value4; + + dut #( .select(1) ) dut1(value1); + dut #( .select(2) ) dut2(value2); + dut #( .select(3) ) dut3(value3); + dut #( .select(4) ) dut4(value4); + + initial begin + #1 $display(""value1=%d, value2=%d, value3=%d, value4=%d"", +\t\t value1, value2, value3, value4); + + if (value1 !== 1) begin +\t $display(""FAILED -- value1=%b"", value1); +\t $finish; + end + + if (value2 !== 2) begin +\t $display(""FAILED -- value2=%b"", value2); +\t $finish; + end + + if (value3 !== 3) begin +\t $display(""FAILED -- value3=%b"", value3); +\t $finish; + end + + if (value4 !== 7) begin +\t $display(""FAILED -- value4=%b"", value4); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main + +module dut(output wire [2:0] value); + + parameter select = 0; + + case (select) + 0: begin +\tfunction [2:0] funfun; +\t input integer in; +\t funfun = in; +\tendfunction // funfun + +\tassign value = funfun(select); + end + 1: begin +\tfunction [2:0] funfun; +\t input integer in; +\t funfun = in; +\tendfunction // funfun + +\tassign value = funfun(1); + end + 2: assign value = 2; + 3: assign value = 3; + default: + assign value = 7; + endcase // case endcase + +endmodule // dut +" +"module test; + +// This example was adapted from: + +// DRAFT STANDARD VERILOG HARDWARE DESCRIPTION LANGUAGE +// IEEE P1364-2005/D3, 1/7/04 +// Section 4.4.2 ""An example of an expression bit-length problem"" +// pg. 59 + +reg [15:0] a, b, answer; // 16-bit regs + +initial + begin + a = 16\'h8000; + b = 16\'h8000; + answer = (a + b + 0) >> 1; //will work correctly + if ( answer != 16\'h8000 ) + begin + $display(""FAILED -- expected 16\'h8000 received 16\'h%h"", answer); + $finish; + end + $display(""PASSED""); + end + +endmodule +" +"module test; + reg fail = 1\'b0; + reg [3:0] in = 4\'b0; + wire [3:0] bus; + wire [3:0] val; + assign (pull1, pull0) bus = in; + assign val = bus; + + initial begin + // Check the initial value. + #1 if (val !== 4\'b0) begin + $display(""FAILED: initial value, got %b, expected 0000."", val); + fail = 1\'b1; + end + + // Check a bit force and verify a normal bit assign does nothing. + #1 force bus[0] = 1\'b1; + #1 in[0] = 1\'bz; + #1 if (val !== 4\'b0001) begin + $display(""FAILED: force of bus[0], got %b, expected 0001."", val); + fail = 1\'b1; + end + + // Check a part force. + #1 force bus[3:2] = 2\'b11; + #1 if (val !== 4\'b1101) begin + $display(""FAILED: force of bus[3:2], got %b, expected 1101."", val); + fail = 1\'b1; + end + + // Check that we can change an unforced bit. + #1 in[1] = 1\'bz; + #1 if (val !== 4\'b11z1) begin + $display(""FAILED: assignment of bus[1], got %b, expected 11z1."", val); + fail = 1\'b1; + end + #1 in[1] = 1\'b0; + + // Check a bit release. + #1 release bus[0]; + #1 if (val !== 4\'b110z) begin + $display(""FAILED: release of bus[0], got %b, expected 110z."", val); + fail = 1\'b1; + end + + // Check a part release. + #1 release bus[3:2]; + #1 if (val !== 4\'b000z) begin + $display(""FAILED: release of bus[3:2], got %b, expected 000z."", val); + fail = 1\'b1; + end + + // Check a force from the upper thread bits (>= 8). + #1 force bus[2:1] = 2\'bx1; + #1 if (val !== 4\'b0x1z) begin + $display(""FAILED: force of bus[2:1], got %b, expected 0x1z."", val); + fail = 1\'b1; + end + + if (!fail) $display(""PASSED""); + end +endmodule +" +"/* + * Copyright (c) 2000 Peter Monta + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module main; + parameter foo = { 2\'b01, 2\'b10 }; + initial + if (foo==4\'b0110) + $display(""PASSED""); + else + $display(""FAILED""); +endmodule +" +"/* + * Based on bug report pr772. + */ + +module err (); + +parameter kuku = ""AAAAA""; + + +reg reset_b,clk; +initial begin + reset_b = 0; + repeat (10) @(posedge clk); + #1 reset_b = 1; +end + +initial begin + clk = 1\'b1; + #3 forever #10 clk=~clk; +end + + + + + + +always @(posedge clk or negedge reset_b) + if (!reset_b) begin + end + else begin + if ((kuku==""RRRRR"") || (kuku==""AAAAA"") || (kuku==""BBBBB"")) +\t$display(""PASSED""); + else $display(""FAILED""); + $finish; + end + + +endmodule +" +"// Icarus has a number of places where it can calculate %. +module top; + parameter out0 = 64\'shF333333333333392 % 3\'sd3; + reg passed; + wire signed [63:0] in; + wire signed [2:0] const_w0; + reg signed [63:0] out1; + wire signed [63:0] out2; + reg signed [63:0] out3; + + assign in = 64\'hF333333333333392; + assign const_w0 = 3\'sd3; + + always @* begin + out1 = (in % const_w0); + end + + assign out2 = (in % const_w0); + + initial begin + passed = 1\'b1; + #1; + $display(""Testing %0d %% %0d."", in, const_w0); + // Check the parameter result. + if (out0 !== -2) begin + $display(""Failed: constant %%, expected -2, got %0d."", out0); + passed = 1\'b0; + end + // Check the always result. + if (out1 !== -2) begin + $display(""Failed: procedural %%, expected -2, got %0d."", out1); + passed = 1\'b0; + end + // Check the CA result. + if (out2 !== -2) begin + $display(""Failed: CA %%, expected -2, got %0d."", out2); + passed = 1\'b0; + end + // Check a compile time constant result. + out3 = 64\'shF333333333333392 % 3\'sd3; + if (out3 !== -2) begin + $display(""Failed: CA %%, expected -2, got %0d."", out3); + passed = 1\'b0; + end + + if (passed) $display(""PASSED""); + $finish; + end +endmodule +" +"/* + * Copyright (c) 2001 Philip Blundell + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module m; + +task t; + input [255:0] s; + begin + $display(""%s"", s); + end +endtask + +initial + begin + t(""Hello world of Verilog""); + end + +endmodule +" +"module test(); +reg\t\tc; + + a #(1) ua( .c(c), .b(h)); + + initial begin + c = 0; + #1 c = 1; + #1 c = 0; + $display(""PASSED""); + end + +endmodule +module a( +\t\tc, +\t\tb, +\t\t); + parameter e = 2; + + input\t c; + output [e-1:0] b; + + reg [e-1:0] f; + reg [e-1:0] g; + reg [e-1:0] b; + integer\t d; + + always @(posedge c) begin + for(d=0; d= 10) + ret = 1\'b1; + else if(temp >= 4) + ret = 1\'b0; + else if(temp >= 2) + ret = 1\'bx; + else + ret = 1\'b0; + inject = ret; + end + endfunction +endmodule +module main; + wire [7:0] i, o; + wire [0:7] o_vl; + dummy dummy_vhdl(o, i); + stimulus stim(i); + assign o_vl = i; + + always @(i) begin + #1 + if(o !== o_vl) begin + $display(""OUTPUT: "", o); + $display(""INPUT: "", i); + $display(""CORRECT: "", o_vl); + end + end + initial begin + #120000; + $display(""PASSED""); + $finish; + end +endmodule +" +"// This is the most trivial example of a program block. +// It contains only an initial statement and final statement, +// and prints ""PASSED"" so the test bench knows that it works. + +program main (); + + initial $display(""Hello, World.""); + final $display(""PASSED""); + +endprogram : main +" +"module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4\'d2; + +bufif1 buffer[7:0](value2, value1, 1\'b1); + +initial begin + #2 $display(""%b %b"", value1, value2); + if (value2 === 8\'bxxxx0010) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always disable task_identifier ; + + +module main ; + + +reg [3:0] value1 ; + +task foo ; + value1 = #1 1; +endtask + +initial + begin + value1 = 0; + #2 ; + $display(""value = %d"",value1); + #1 ; + $finish ; + end + +always disable foo ; + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always 3.1.1B always reg_lvalue = boolean_expression ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + if(value1 != 4\'b1) +\t$display(""FAILED - 3.1.1B always reg_lvalue = boolean_expression\ +""); + else +\tbegin + $display(""PASSED\ +""); +\t $finish; + end + +always value1 = 1\'b1 && 1\'b1 ; + +endmodule +" +"module dpram #( +\tparameter aw=8, +\tparameter dw=8 +) (input clka, clkb, wena, +\tinput [aw-1:0] addra, addrb, +\tinput [dw-1:0] dina, +\toutput [dw-1:0] doutb +); +// minimalist dual-port RAM model, hope most tools can synthesize it +localparam sz=(32\'b1<> 1) + 0; + $display(""%b"", result); + if (result !== 4\'bxxxx) failed = 1; + result = unknown - 0; + $display(""%b"", result); + if (result !== 4\'bxxxx) failed = 1; + result = unknown * 0; + $display(""%b"", result); + if (result !== 4\'bxxxx) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"`timescale 1ns/1ps + +module top; + parameter length = 17; + reg [length*8-1:0] result; + wire [3:0] net; + + assign (pull1, strong0) net = 4\'b0110; + + initial begin + #1; + $swrite(result, ""%v"", net); + $display(""All three lines should match:""); + $display(""-----------------------------""); + $display(""St0_Pu1_Pu1_St0 (reference)""); + $display(""%v (display)\ +%0s (swrite)"", net, result); + end +endmodule +" +"`timescale 1s/1s + +module test(outp, outm, outl, in); + output outp, outm, outl; + input in; + + // Check a primitive. + assign #1 outp = ~in; + + // Check a multiplexer. + assign #1 outm = in ? in : 1\'b0; + + // Check a LPM. + assign #1 outl = in === 1\'b1; +endmodule + +// This is not exactly the same as the original code, but it is effectively +// the same and should test the same things that were failing. +`timescale 1ns/100ps + +module top; + reg in, passed; + wire outp, outm, outl; + + test dut(outp, outm, outl, in); + + initial begin + passed = 1\'b1; + + #1100000000; + if (outp !== 1\'bx) begin + $display(""Failed initial prim. check, expected 1\'bx, got %b."", outp); + passed = 1\'b0; + end + if (outm !== 1\'bx) begin + $display(""Failed initial mux. check, expected 1\'bx, got %b."", outm); + passed = 1\'b0; + end + if (outl !== 1\'b0) begin + $display(""Failed initial LPM check, expected 1\'b0, got %b."", outl); + passed = 1\'b0; + end + + in = 0; + #1100000000; + if (outp !== 1\'b1) begin + $display(""Failed in=0 prim. check, expected 1\'b1, got %b."", outp); + passed = 1\'b0; + end + if (outm !== 1\'b0) begin + $display(""Failed in=0 mux. check, expected 1\'b0, got %b."", outm); + passed = 1\'b0; + end + if (outl !== 1\'b0) begin + $display(""Failed in=0 LPM check, expected 1\'b0, got %b."", outl); + passed = 1\'b0; + end + + in = 1; + #1100000000; + if (outp !== 1\'b0) begin + $display(""Failed in=1 prim. check, expected 1\'b0, got %b."", outp); + passed = 1\'b0; + end + if (outm !== 1\'b1) begin + $display(""Failed in=1 mux. check, expected 1\'b1, got %b."", outm); + passed = 1\'b0; + end + if (outl !== 1\'b1) begin + $display(""Failed in=1 LPM check, expected 1\'b1, got %b."", outl); + passed = 1\'b0; + end + + if (passed) $display(""PASSED""); + + end +endmodule +" +"/* + * Check that the initial value can be out of range and that the next()/prev() + * enumeration methods do not change to a defined state. + */ +module top; + reg pass; + enum bit [3:0] {a2 = 1, b2 = 2, c2 = 3, d2 = 4} evar2; + enum reg [3:0] {a4 = 1, b4 = 2, c4 = 3, d4 = 4} evar4; + + initial begin + pass = 1\'b1; + + if (evar2 !== 0) begin + $display(""Failed initial/2 value should be 0, got %d"", evar2); + pass = 1\'b0; + end + if (evar4 !== 4\'bx) begin + $display(""Failed initial/4 value should be \'bx, got %d"", evar4); + pass = 1\'b0; + end + + evar2 = evar2.next; + if (evar2 !== 0) begin + $display(""Failed next/2 of an invalid value should be 0, got %d"", evar2); + pass = 1\'b0; + end + evar4 = evar4.next; + if (evar4 !== 4\'bx) begin + $display(""Failed next/4 of an invalid value should be 0, got %d"", evar4); + pass = 1\'b0; + end + + evar2 = evar2.prev; + if (evar2 !== 0) begin + $display(""Failed prev/2 of an invalid value should be 0, got %d"", evar2); + pass = 1\'b0; + end + evar4 = evar4.prev; + if (evar4 !== 4\'bx) begin + $display(""Failed prev/4 of an invalid value should be 0, got %d"", evar4); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"/* + * Verify that the various non-blocking assignments support a delay + * that is greater than 32 bits. The top delays are in seconds and + * the other delays are in ps. The second delays all require more + * than 32 bits to work correctly. They will use the /d version. + */ + +`timescale 1s/1s +module gt32b; + real rlval; + reg rval; + reg aval[1:0]; + reg [7:0] psval; + + initial begin + $timeformat(-12, 0, "" ps"", 16); + #1; + $display(""dl:gt32b- %t"", $realtime); + rlval <= #1 1.0; + rval <= #2 1\'b1; + aval[0] <= #3 1\'b0; + psval[1] <= #4 1\'b1; + end + + always @(rlval) begin + $display(""rl:gt32b- %t"", $realtime); + end + + always @(rval) begin + $display(""rg:gt32b- %t"", $realtime); + end + + always @(aval[0]) begin + $display(""ar:gt32b- %t"", $realtime); + end + + always @(psval) begin + $display(""ps:gt32b- %t"", $realtime); + end +endmodule + +`timescale 1ps/1ps +module ls32b; + real rlval; + reg rval; + reg aval[1:0]; + reg [7:0] psval; + + initial begin + #1; + $display(""dl:ls32b- %t"", $realtime); + rlval <= #1 1.0; + rval <= #2 1\'b1; + aval[0] <= #3 1\'b0; + psval[1] <= #4 1\'b1; + end + + always @(rlval) begin + $display(""rl:ls32b- %t"", $realtime); + end + + always @(rval) begin + $display(""rg:ls32b- %t"", $realtime); + end + + always @(aval[0]) begin + $display(""ar:ls32b- %t"", $realtime); + end + + always @(psval) begin + $display(""ps:ls32b- %t"", $realtime); + end +endmodule +" +"module main; + + wire a; + device U1(a); + + task work; + begin +\t$deposit(U1.r, 1); +\t$display(""PASSED""); +\t$finish; + end + endtask + + initial work; + +endmodule + +module device(r); + output r; + reg r; +endmodule +" +"module top; + integer result; + + initial begin + + result = $countbits(top); + result = $countbits(""a string""); + result = $countbits(1\'bx); + result = $countbits(""a string"", 1\'bx); + result = $countbits(1\'bx, ""a string""); + result = $countbits(1\'bx, 1\'bx, ""a string""); + + end + +endmodule +" +"module naughty_module( +\tinput clk, +\tinput [71:0] pzw, +\tinput [95:0] xy_d, +\tinput [23:0] pbit, +\toutput [95:0] xas, +\toutput [95:0] yas +); + +initial $display(""PASSED""); + +function [3:0] xa; +\tinput pbit; +\tinput [1:0] ix_in; +\tinput [1:0] iy_in; +\tinput [3:0] pzw; +begin +\txa = +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h0} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h1} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h2} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h3} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h4} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h5} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h6} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h7} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h0} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h1} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h2} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h3} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h4} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h5} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h6} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h7} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h0} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h1} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h2} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h3} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h4} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h5} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h6} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h7} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h0} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h1} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h2} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h3} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h4} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h5} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h6} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h7} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h0} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h1} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h2} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h3} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h4} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h5} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h6} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h7} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h0} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h1} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h2} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h3} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h4} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h5} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h6} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h7} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h0} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h1} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h2} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h3} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h4} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h5} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h6} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h7} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h0} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h1} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h2} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h3} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h4} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h5} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h6} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h7} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h0} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h1} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h2} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h3} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h4} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h5} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h6} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h7} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h0} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h1} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h2} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h3} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h4} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h5} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h6} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h7} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h0} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h1} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h2} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h3} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h4} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h5} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h6} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h7} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h0} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h1} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h2} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h3} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h4} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h5} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h6} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h7} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h0} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h1} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h2} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h3} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h4} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h5} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h6} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h7} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h0} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h1} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h2} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h3} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h4} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h5} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h6} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h7} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h0} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h1} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h2} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h3} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h4} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h5} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h6} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h7} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h0} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h1} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h2} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h3} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h4} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h5} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h6} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h7} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h0} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h1} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h2} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h3} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h4} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h5} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h6} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h7} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h0} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h1} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h2} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h3} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h4} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h5} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h6} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h7} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h0} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h1} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h2} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h3} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h4} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h5} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h6} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h7} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h0} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h1} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h2} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h3} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h4} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h5} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h6} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h7} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h0} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h1} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h2} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h3} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h4} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h5} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h6} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h7} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h0} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h1} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h2} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h3} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h4} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h5} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h6} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h7} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h0} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h1} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h2} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h3} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h4} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h5} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h6} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h7} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h0} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h1} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h2} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h3} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h4} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h5} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h6} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h7} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h0} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h1} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h2} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h3} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h4} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h5} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h6} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h7} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h0} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h1} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h2} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h3} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h4} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h5} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h6} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h7} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h0} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h1} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h2} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h3} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h4} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h5} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h6} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h7} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h0} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h1} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h2} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h3} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h4} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h5} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h6} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h7} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h0} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h1} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h2} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h3} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h4} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h5} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h6} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h7} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h0} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h1} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h2} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h3} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h4} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h5} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h6} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h7} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h0} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h1} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h2} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h3} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h4} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h5} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h6} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h7} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h0} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h1} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h2} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h3} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h4} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h5} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h6} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h7} ? 4\'h3 : +\t4\'h0; +end +endfunction + +function [3:0] ya; +\tinput pbit; +\tinput [1:0] ix_in; +\tinput [1:0] iy_in; +\tinput [3:0] pzw; +begin +\tya = +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h0} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h1} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h2} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h3} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h4} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h5} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h6} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h0, 3\'h7} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h0} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h1} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h2} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h3} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h4} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h5} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h6} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h1, 3\'h7} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h0} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h1} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h2} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h3} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h4} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h5} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h6} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h2, 3\'h7} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h0} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h1} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h2} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h3} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h4} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h5} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h6} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h0, 2\'h3, 3\'h7} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h0} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h1} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h2} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h3} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h4} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h5} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h6} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h0, 3\'h7} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h0} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h1} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h2} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h3} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h4} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h5} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h6} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h1, 3\'h7} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h0} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h1} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h2} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h3} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h4} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h5} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h6} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h2, 3\'h7} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h0} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h1} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h2} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h3} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h4} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h5} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h6} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h1, 2\'h3, 3\'h7} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h0} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h1} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h2} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h3} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h4} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h5} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h6} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h0, 3\'h7} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h0} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h1} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h2} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h3} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h4} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h5} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h6} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h1, 3\'h7} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h0} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h1} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h2} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h3} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h4} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h5} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h6} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h2, 3\'h7} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h0} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h1} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h2} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h3} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h4} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h5} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h6} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h2, 2\'h3, 3\'h7} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h0} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h1} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h2} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h3} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h4} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h5} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h6} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h0, 3\'h7} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h0} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h1} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h2} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h3} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h4} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h5} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h6} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h1, 3\'h7} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h0} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h1} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h2} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h3} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h4} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h5} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h6} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h2, 3\'h7} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h0} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h1} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h2} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h3} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h4} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h5} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h6} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h0, 2\'h3, 2\'h3, 3\'h7} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h0} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h1} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h2} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h3} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h4} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h5} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h6} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h0, 3\'h7} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h0} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h1} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h2} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h3} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h4} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h5} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h6} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h1, 3\'h7} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h0} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h1} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h2} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h3} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h4} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h5} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h6} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h2, 3\'h7} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h0} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h1} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h2} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h3} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h4} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h5} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h6} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h0, 2\'h3, 3\'h7} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h0} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h1} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h2} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h3} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h4} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h5} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h6} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h0, 3\'h7} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h0} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h1} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h2} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h3} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h4} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h5} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h6} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h1, 3\'h7} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h0} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h1} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h2} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h3} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h4} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h5} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h6} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h2, 3\'h7} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h0} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h1} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h2} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h3} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h4} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h5} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h6} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h1, 2\'h3, 3\'h7} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h0} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h1} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h2} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h3} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h4} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h5} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h6} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h0, 3\'h7} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h0} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h1} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h2} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h3} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h4} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h5} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h6} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h1, 3\'h7} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h0} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h1} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h2} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h3} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h4} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h5} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h6} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h2, 3\'h7} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h0} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h1} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h2} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h3} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h4} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h5} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h6} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h2, 2\'h3, 3\'h7} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h0} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h1} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h2} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h3} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h4} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h5} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h6} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h0, 3\'h7} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h0} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h1} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h2} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h3} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h4} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h5} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h6} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h1, 3\'h7} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h0} ? 4\'h5 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h1} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h2} ? 4\'h8 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h3} ? 4\'h7 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h4} ? 4\'h4 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h5} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h6} ? 4\'h1 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h2, 3\'h7} ? 4\'h2 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h0} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h1} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h2} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h3} ? 4\'h9 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h4} ? 4\'h6 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h5} ? 4\'h3 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h6} ? 4\'h0 : +\t{pbit, ix_in, iy_in, pzw} == {1\'h1, 2\'h3, 2\'h3, 3\'h7} ? 4\'h0 : +\t4\'h0; +end +endfunction + + +\treg [95:0] r_xa; +\treg [95:0] r_ya; + + +\talways @(posedge clk) +\tbegin +\t\tr_xa[ 3: 0] <= xa(pbit[ 0], xy_d[ 1: 0], xy_d[ 3: 2], pzw[ 2: 0]); +\t\tr_xa[ 7: 4] <= xa(pbit[ 1], xy_d[ 5: 4], xy_d[ 7: 6], pzw[ 5: 3]); +\t\tr_xa[11: 8] <= xa(pbit[ 2], xy_d[ 9: 8], xy_d[11:10], pzw[ 8: 6]); +\t\tr_xa[15: 12] <= xa(pbit[ 3], xy_d[13:12], xy_d[15:14], pzw[11: 9]); +\t\tr_xa[19: 16] <= xa(pbit[ 4], xy_d[17:16], xy_d[19:18], pzw[14:12]); +\t\tr_xa[23: 20] <= xa(pbit[ 5], xy_d[21:20], xy_d[23:22], pzw[17:15]); +\t\tr_xa[27: 24] <= xa(pbit[ 6], xy_d[25:24], xy_d[27:26], pzw[20:18]); +\t\tr_xa[31: 28] <= xa(pbit[ 7], xy_d[29:28], xy_d[31:30], pzw[23:21]); +\t\tr_xa[35: 32] <= xa(pbit[ 8], xy_d[33:32], xy_d[35:34], pzw[26:24]); +\t\tr_xa[39: 36] <= xa(pbit[ 9], xy_d[37:36], xy_d[39:38], pzw[29:27]); +\t\tr_xa[43: 40] <= xa(pbit[10], xy_d[41:40], xy_d[43:42], pzw[32:30]); +\t\tr_xa[47: 44] <= xa(pbit[11], xy_d[45:44], xy_d[47:46], pzw[35:33]); +\t\tr_xa[51: 48] <= xa(pbit[12], xy_d[49:48], xy_d[51:50], pzw[38:36]); +\t\tr_xa[55: 52] <= xa(pbit[13], xy_d[53:52], xy_d[55:54], pzw[41:39]); +\t\tr_xa[59: 56] <= xa(pbit[14], xy_d[57:56], xy_d[59:58], pzw[44:42]); +\t\tr_xa[63: 60] <= xa(pbit[15], xy_d[61:60], xy_d[63:62], pzw[47:45]); +\t\tr_xa[67: 64] <= xa(pbit[16], xy_d[65:64], xy_d[67:66], pzw[50:48]); +\t\tr_xa[71: 68] <= xa(pbit[17], xy_d[69:68], xy_d[71:70], pzw[53:51]); +\t\tr_xa[75: 72] <= xa(pbit[18], xy_d[73:72], xy_d[75:74], pzw[56:54]); +\t\tr_xa[79: 76] <= xa(pbit[19], xy_d[77:76], xy_d[79:78], pzw[59:57]); +\t\tr_xa[83: 80] <= xa(pbit[20], xy_d[81:80], xy_d[83:82], pzw[62:60]); +\t\tr_xa[87: 84] <= xa(pbit[21], xy_d[85:84], xy_d[87:86], pzw[65:63]); +\t\tr_xa[91: 88] <= xa(pbit[22], xy_d[89:88], xy_d[91:90], pzw[68:66]); +\t\tr_xa[95: 92] <= xa(pbit[23], xy_d[93:92], xy_d[95:94], pzw[71:69]); + +\t\tr_ya[ 3: 0] <= ya(pbit[ 0], xy_d[ 1: 0], xy_d[ 3: 2], pzw[ 2: 0]); +\t\tr_ya[ 7: 4] <= ya(pbit[ 1], xy_d[ 5: 4], xy_d[ 7: 6], pzw[ 5: 3]); +\t\tr_ya[11: 8] <= ya(pbit[ 2], xy_d[ 9: 8], xy_d[11:10], pzw[ 8: 6]); +\t\tr_ya[15: 12] <= ya(pbit[ 3], xy_d[13:12], xy_d[15:14], pzw[11: 9]); +\t\tr_ya[19: 16] <= ya(pbit[ 4], xy_d[17:16], xy_d[19:18], pzw[14:12]); +\t\tr_ya[23: 20] <= ya(pbit[ 5], xy_d[21:20], xy_d[23:22], pzw[17:15]); +\t\tr_ya[27: 24] <= ya(pbit[ 6], xy_d[25:24], xy_d[27:26], pzw[20:18]); +\t\tr_ya[31: 28] <= ya(pbit[ 7], xy_d[29:28], xy_d[31:30], pzw[23:21]); +\t\tr_ya[35: 32] <= ya(pbit[ 8], xy_d[33:32], xy_d[35:34], pzw[26:24]); +\t\tr_ya[39: 36] <= ya(pbit[ 9], xy_d[37:36], xy_d[39:38], pzw[29:27]); +\t\tr_ya[43: 40] <= ya(pbit[10], xy_d[41:40], xy_d[43:42], pzw[32:30]); +\t\tr_ya[47: 44] <= ya(pbit[11], xy_d[45:44], xy_d[47:46], pzw[35:33]); +\t\tr_ya[51: 48] <= ya(pbit[12], xy_d[49:48], xy_d[51:50], pzw[38:36]); +\t\tr_ya[55: 52] <= ya(pbit[13], xy_d[53:52], xy_d[55:54], pzw[41:39]); +\t\tr_ya[59: 56] <= ya(pbit[14], xy_d[57:56], xy_d[59:58], pzw[44:42]); +\t\tr_ya[63: 60] <= ya(pbit[15], xy_d[61:60], xy_d[63:62], pzw[47:45]); +\t\tr_ya[67: 64] <= ya(pbit[16], xy_d[65:64], xy_d[67:66], pzw[50:48]); +\t\tr_ya[71: 68] <= ya(pbit[17], xy_d[69:68], xy_d[71:70], pzw[53:51]); +\t\tr_ya[75: 72] <= ya(pbit[18], xy_d[73:72], xy_d[75:74], pzw[56:54]); +\t\tr_ya[79: 76] <= ya(pbit[19], xy_d[77:76], xy_d[79:78], pzw[59:57]); +\t\tr_ya[83: 80] <= ya(pbit[20], xy_d[81:80], xy_d[83:82], pzw[62:60]); +\t\tr_ya[87: 84] <= ya(pbit[21], xy_d[85:84], xy_d[87:86], pzw[65:63]); +\t\tr_ya[91: 88] <= ya(pbit[22], xy_d[89:88], xy_d[91:90], pzw[68:66]); +\t\tr_ya[95: 92] <= ya(pbit[23], xy_d[93:92], xy_d[95:94], pzw[71:69]); +\tend + +\tassign xas = r_xa; +\tassign yas = r_ya; + +endmodule +" +"/* + * Verify that the continuous assignments support a delay that is + * greater than 32 bits. The top delays are in seconds and the other + * delays are in ps. The second delays all require more than 32 bits + * to work correctly. They will use the /d version. + */ + +`timescale 1s/1s +module gt32b; + wire real rlval; + wire rval; + wire aval[1:0]; + wire [7:0] psval; + + assign #1 rlval = 1.0; + assign #2 rval = 1\'b1; + assign #3 aval[0] = 1\'b0; + assign #4 psval[1] = 1\'b1; + + initial begin + $timeformat(-12, 0, "" ps"", 16); + #1; + $display(""dl:gt32b- %t"", $realtime); + end + + always @(rlval) begin + $display(""rl:gt32b- %t"", $realtime); + end + + always @(rval) begin + $display(""rg:gt32b- %t"", $realtime); + end + + always @(aval[0]) begin + $display(""ar:gt32b- %t"", $realtime); + end + + always @(psval) begin + $display(""ps:gt32b- %t"", $realtime); + end +endmodule + +`timescale 1ps/1ps +module ls32b; + wire real rlval; + wire rval; + wire aval[1:0]; + wire [7:0] psval; + + assign #1 rlval = 1.0; + assign #2 rval = 1\'b1; + assign #3 aval[0] = 1\'b0; + assign #4 psval[1] = 1\'b1; + + initial begin + #1; + $display(""dl:ls32b- %t"", $realtime); + end + + always @(rlval) begin + $display(""rl:ls32b- %t"", $realtime); + end + + always @(rval) begin + $display(""rg:ls32b- %t"", $realtime); + end + + always @(aval[0]) begin + $display(""ar:ls32b- %t"", $realtime); + end + + always @(psval) begin + $display(""ps:ls32b- %t"", $realtime); + end +endmodule +" +"module test(); + +typedef enum logic [8:0] { ILLEGAL, IA, IB } inst_t; + +inst_t ipb_inst; + +typedef struct packed { + inst_t inst; + logic iw; +} ipb_data_t; + +ipb_data_t ipb_d; + +assign ipb_inst = ipb_d.inst; + +initial begin + ipb_d.inst = IA; + #1; + if (ipb_inst === IA) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module dut( + input wire [3:0] i, + output wire [3:0] o +); + +assign o = i; + +specify + (i[3:0] => o[3:0]) = (1, 1); +endspecify + +endmodule + +module top(); + +reg [3:0] i; +wire [3:0] o; + +dut dut(i, o); + +reg failed = 0; + +initial begin + $monitor($time,,i,,o); + #1 i = 4\'d1; + #0 if (o !== 4\'bx) failed = 1; + #1 i = 4\'d2; + #0 if (o !== 4\'d1) failed = 1; + #1; + #0 if (o !== 4\'d2) failed = 1; + #1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module test (); + parameter fuse_a_msb = 4; + parameter fuse_q_msb = (2**(fuse_a_msb+1))-1; + + initial begin + if (fuse_q_msb != \'h1f) begin +\t $display(""FAILED -- fuse_q_msb = %d"", fuse_q_msb); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule +" +"module check (input unsigned [22:0] a, c); + wire [22:0] int_AB; + + assign int_AB = ~a; + +always @(a, int_AB, c) begin + #1; + if (int_AB != c) begin + $display(""ERROR""); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [22:0] A); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; + for (i=0; i +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// \'wait on\' & \'wait until\' test + +module vhdl_wait_test; +logic [1:0] a, b; +vhdl_wait dut(a, b); + +always @(posedge b[0]) begin + $display(""wait 1 acknowledged""); + // complete ""wait 2"" + a[1] = 1\'b0; +end + +always @(posedge b[1]) begin + $display(""wait 2 acknowledged""); +end + +initial begin + // complete ""wait 1"" + a = 2\'b00; +end + +endmodule +" +"`timescale 1ns/10ps + +module top; +// Comment out this line and the $display below to get elaboration to fail. + integer max = 2 ** 2; + + initial begin + test_ok; +// test_fail; + $display(""Main: %3d"", max); + end + + // This works. + task test_ok; + integer max; + + begin + max = 2 ** 8; + $display(""OK: %3d"", max); + end + endtask + +/* + * This is invalid syntax! You can not do an assignment in a block + * level variable declaration (task, function, etc.). + // And this is failing! It appears to be looking in the wrong scope. + task test_fail; + integer max = 2 ** 8; + + begin + $display(""Fail: %3d"", max); + end + endtask + */ + +endmodule +" +"module top; + real rvar1, rvar2, rtmp; + wire real wrcon3, wrcon4, wrcon5, wrcon6; + + wire real wrcon1 = {2.0, 1.0}; + wire real wrcon2 = {rvar1, rvar2}; + + assign wrcon3 = {2.0, 1.0}; + assign wrcon4 = {rvar1, rvar2}; + + assign {wrcon5, wrcon6} = 1.0; + + initial begin + rtmp = {2.0, 1.0}; + rtmp = {rvar1, rvar2}; + + {rvar1, rvar2} = rtmp; + end +endmodule +" +"// Copyright (c) 2000 Stephen Williams (steve@icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + + // This tests DFF-like behavior. The clocked always block acts like a + // DFF, and if the -Fsynth flag to ivl is used, actually generates an + // LPM_FF device. + +module main () ; + + reg clk; + reg D, Q; + + always #10 clk = ~clk; + always @(posedge clk) Q = D; + + initial begin + clk = 0; + D = 0; + @(negedge clk) + if (Q !== 1\'b0) + begin +\t $display(""FAILED: %b !== %b"", Q, D); +\t $finish; + end + + D = 1; + @(negedge clk) + if (Q !== 1\'b1) + begin +\t $display(""FAILED: %b !== %b"", Q, D); +\t $finish; + end + + D = \'bx; + + @(negedge clk) + if (Q !== 1\'bx) + begin +\t $display(""FAILED: %b !== %b"", Q, D); +\t $finish; + end + + D = \'bz; + @(negedge clk) + if (Q !== 1\'bz) + begin +\t $display(""FAILED: %b !== %b"", Q, D); +\t $finish; + end + + $display(""PASSED""); + $finish; + end // initial begin + +endmodule +" +"module test(); +// wire r; +a ua ( .r ( !r )); +endmodule + +module a ( r ); +input r; +endmodule +" +" +module test_logic + #(parameter WID = 4) + (input wire [WID-1:0] A, + output q_and, q_or, q_xor, q_nand, q_nor, q_xnor); + + assign q_and = & A; + assign q_or = | A; + assign q_xor = ^ A; + assign q_nand= ~& A; + assign q_nor = ~| A; + assign q_xnor= ~^ A; + +endmodule // test_logic +" +"/*********************************************************************** + + Duplicate output declaration test case + Duplicate port declarations should generate an error + +***********************************************************************/ + +module port_test4 ( +\t\t a,\t\t// Input +\t\t b,\t\t// Output + ); + +input a; + +output b; +output b; + +assign b=a; + +endmodule +" +"/* + * In this example, the set and clr are both synchronous. This checks + * that this complex case is handled correctly. + */ +module main; + + + reg\t Q, clk, rst, set, clr; + (* ivl_synthesis_on *) + always@(posedge clk or posedge rst) + begin +\tif (rst) +\t Q <= 1\'b0; +\telse if (clr) +\t Q <= 1\'b0; +\telse if (set) +\t Q <= 1\'b1; +\telse +\t Q <= Q; + end + + (* ivl_synthesis_off *) + initial begin + clk = 0; + rst = 0; + set = 0; + clr = 0; + + #1 rst = 1; + #1 rst = 0; + + if (Q !== 0) begin +\t $display(""FAILED -- rst""); +\t $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin +\t $display(""FAILED -- 1 clk""); +\t $finish; + end + + #1 set = 1; + #1 ; + + if (Q !== 0) begin +\t $display(""FAILED -- 1 set (no clk)""); +\t $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 1) begin +\t $display(""FAILED -- 1 set""); +\t $finish; + end + + #1 clr = 1; + #1 ; + + if (Q !== 1) begin +\t $display(""FAILED -- 1 clr+set (no clk)""); +\t $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin +\t $display(""FAILED -- 1 clr+set""); +\t $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin +\t $display(""FAILED -- 2 clr+set""); +\t $finish; + end + + #1 set = 1; + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin +\t $display(""FAILED -- 1 set+clr""); +\t $finish; + end + + #1 clr = 0; + #1 clk = 1; + #1 clk = 0; + + if (Q !== 1) begin +\t $display(""FAILED -- 1 set-clr""); +\t $finish; + end + + $display(""PASSED""); + $finish; + end + +endmodule +" +"//////////////////////////////////////////////////////////////////////// +// Copyright 2003 University of Kentucky +// +// This file is released into the public domain +//////////////////////////////////////////////////////////////////////// + +// +// Top level module +// +module top(); +\tparameter tp = \'d1; + +\treg a; +\twire b; + +\tbot b1(b, a); + +\tinitial begin +\t\ta = 0; +\t\t$display(""tp = %d in top"", tp); +\tend +endmodule + + +// +// bottom level module +// + +`define div 0.100 + +module bot(a, b); +\tinput b; +\toutput a; + +\treal tp;\t// tp is overridden by tp parameter in top +\treal tp2; + +\tassign a = b; +\tinitial begin +\t\ttp = 1 / `div; +\t\ttp2 = 1 / `div; +\t\t$display(""tp = %f, tp2 = %f"", tp, tp2); +\t\tif (tp != 10.0) +\t\t\t$display(""tp != 10.0. (tp = %f)"", tp); +\t\telse +\t\t\t$display(""tp == 10, (expected)""); +\t\t#1 $display(""tp = %f, tp2 = %f"", tp, tp2); +\tend +endmodule +" +"package test_pkg; + + class uvm_object; + function new (); + print(""new uvm_object""); + endfunction : new + + virtual function void print (string str); + $display (str); + endfunction : print + endclass : uvm_object + + class uvm_report_object extends uvm_object; + function new (); + print(""new uvm_report_object""); + endfunction : new + endclass : uvm_report_object + +endpackage : test_pkg + +module m; + import test_pkg::*; + uvm_report_object r_0; + uvm_object u_0; + + initial begin : test + #100; + u_0 = new(); + r_0 = new(); + + u_0.print(""u_0""); + r_0.print(""r_0""); + + end : test + +endmodule : m +" +"`timescale 1 ps / 1 ps + +module example; + time delay; + initial begin +// delay = 64\'bx; + $display( ""%T %b"", $time, delay ); +// #(64\'bx) + #delay + $display( ""%T"", $time ); + end +endmodule +" +"/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + reg [7:0] x, y; + + initial begin + x = -4; + if (x !== 8\'hfc) begin +\t $display(""FAILED -- x = -4 --> %b"", x); +\t $finish; + end + + x = 4; + if (x !== 8\'h04) begin +\t $display(""FAILED""); +\t $finish; + end + + y = -x; + if (y !== 8\'hfc) begin +\t $display(""FAILED -- y = -%b --> %b"", x, y); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + + +endmodule // main +" +"module top; + reg pass; + reg in; + wire out, outb; + + lower_cell dutb(outb, in); + lower_no_cell dut(out, in); + + always @(outb) begin + if (outb !== ~in) begin + $display(""FAILED outb at time %t, expected %b, got %b"", $time, ~in, outb); + pass = 1\'b0; + end + end + + always @(out) begin + if (out !== in) begin + $display(""FAILED out at time %t, expected %b, got %b"", $time, in, out); + pass = 1\'b0; + end + end + + initial begin + pass = 1\'b1; + #1 in = 1\'b0; + #1 in = 1\'b1; + #1 in = 1\'b0; + + #1 if (pass) $display(""Verilog checking was OK.""); + $is_cell(dut); + $is_cell(dutb); + end +endmodule + +`celldefine +module lower_cell(output out, input in); + not(out, in); +endmodule +`endcelldefine + +module lower_no_cell(output out, input in); + buf(out, in); +endmodule +" +"/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + reg [7:0] a, b; + wire [8:0] res; + + has_ports test(res, a, b); + + initial begin + a = 0; + b = 0; + #1 $display(""has_ports (%b, %b, %b)"", res, a, b); + if (res !== (a + b)) begin +\t $display(""FAILED""); +\t $finish; + end + + a = 10; + #1 $display(""has_ports (%b, %b, %b)"", res, a, b); + if (res !== (a + b)) begin +\t $display(""FAILED""); +\t $finish; + end + + b = 11; + #1 $display(""has_ports (%b, %b, %b)"", res, a, b); + if (res !== (a + b)) begin +\t $display(""FAILED""); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule // main + +module has_ports (output reg [8:0] o, +\t\t input wire [7:0] a, +\t\t input wire [7:0] b); + + always @* o <= a + b; + +endmodule // has_ports +" +"module ts_pad ( + inout wire pad, + input wire oe, + input wire op +); + +assign pad = oe ? op : 1\'bz; + +endmodule + +module test(); + +wire [1:0] bus; + +reg oe1 = 1\'b0; +reg oe2 = 1\'b0; +reg oe3 = 1\'b0; +reg oe4 = 1\'b0; +reg oe5 = 1\'b0; +reg oe6 = 1\'b0; + +wire op1 = 1\'b0; +wire op2 = 1\'b1; +wire op3 = 1\'b1; +wire op4 = 1\'b0; +wire op5 = 1\'bx; +wire op6 = 1\'bx; + +ts_pad pad1(bus[0], oe1, op1); +ts_pad pad2(bus[1], oe2, op2); + +ts_pad pad3(bus[0], oe3, op3); +ts_pad pad4(bus[1], oe4, op4); + +bufif1(bus[0], op5, oe5); +bufif1(bus[1], op6, oe6); + +integer multi; +integer forced; +integer countD; +integer count0; +integer count1; +integer countX; + +reg failed = 0; + +task check_results; + +input integer expected_multi; +input integer expected_forced; +input integer expected_countD; +input integer expected_count0; +input integer expected_count1; +input integer expected_countX; + +begin + $write(""multi = %0d "", multi); + if (multi !== expected_multi) failed = 1; + if (expected_forced != -1) begin + $write(""forced = %0d "", forced); + if (forced !== expected_forced) failed = 1; + end + if (expected_countD != -1) begin + $write(""countD = %0d "", countD); + if (countD !== expected_countD) failed = 1; + end + if (expected_count0 != -1) begin + $write(""count0 = %0d "", count0); + if (count0 !== expected_count0) failed = 1; + end + if (expected_count1 != -1) begin + $write(""count1 = %0d "", count1); + if (count1 !== expected_count1) failed = 1; + end + if (expected_countX != -1) begin + $write(""countX = %0d "", countX); + if (countX !== expected_countX) failed = 1; + end + $write(""\ +""); +end + +endtask + +initial begin + #1; + multi = $countdrivers(bus[0], forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + multi = $countdrivers(bus[1], forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + $display(""""); + + oe1 = 1\'b1; + #1; + multi = $countdrivers(bus[0], forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(bus[1], forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + $display(""""); + + oe2 = 1\'b1; + #1; + multi = $countdrivers(bus[0], forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(bus[1], forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + $display(""""); + + oe3 = 1\'b1; + #1; + multi = $countdrivers(bus[0], forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(bus[1], forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + $display(""""); + + oe4 = 1\'b1; + #1; + multi = $countdrivers(bus[0], forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(bus[1], forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + $display(""""); + + oe5 = 1\'b1; + #1; + multi = $countdrivers(bus[0], forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(bus[1], forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + $display(""""); + + oe6 = 1\'b1; + #1; + multi = $countdrivers(bus[0], forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(bus[1], forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + $display(""""); + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module test; + +typedef enum reg { FALSE = 1\'b0, TRUE = 1\'b1 } boolean; + +boolean flag; + +initial begin + #1 $display(""%b"", flag); + if (flag === TRUE) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module foo; + + reg [2:0] cond; + reg\t test; + + initial begin + cond = 0; + test = cond ? 1\'b1 : 1\'b0; + + if (test !== 1\'b0) begin +\t $display(""FAILED -- cond=%b, test=%b"", cond, test); +\t $finish; + end + + cond = 1; + test = cond ? 1\'b1 : 1\'b0; + + if (test !== 1) begin +\t $display(""FAILED -- cond=%b, test=%b"", cond, test); +\t $finish; + end + + cond = 2; + test = cond ? 1\'b1 : 1\'b0; + + if (test !== 1) begin +\t $display(""FAILED -- cond=%b, test=%b"", cond, test); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule +" +"/* + * Copyright (c) 2000 Nadim Shaikli + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/*************************************************** +* +* Problem: Core dump on \'out of range\' error +* search for \'thing[9]\' +* +***************************************************/ + +module main; + + reg clk; + reg [3:0] sig; + reg [7:0] thing; + + // generate a clock + always + #10 clk = ~clk; + + initial + begin + $display (""\ +<< BEGIN >>""); + + case ( sig[3:0] ) + 4\'b0000: thing[0] = 1\'b1; + 4\'b0010: thing[2] = 1\'b1; + 4\'b0011: thing[9] = 1\'b1; + endcase // case( sig[3:0] ) + + $display (""<< END >>\ +""); + $finish; + end + + // Waves definition +// initial +// begin +// $dumpfile(""out.dump""); +// $dumpvars(0, main); +// end + +endmodule // main +" +"/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Test the display of very wide vectors in decimal. + */ +module test; + + reg signed [127:0] value; + + initial begin + value = 1; + while (value != 0) begin +\t $display(""value=%d"", value); +\t value = value << 1; + end + + value = -1; + while (value != 0) begin +\t $display(""value=%d"", value); +\t value = value << 1; + end + + end +endmodule // test +" +"// This test program shows how programs can be instantiated +// within another module. + +program test(input [7:0] sh1, input [7:0] sh2); + + final begin + if (sh1 !== \'h55) begin +\t $display(""FAILED -- shared=%b is not correct"", sh1); +\t $finish; + end + + if (sh2 !== \'haa) begin +\t $display(""FAILED -- sh2 not correct"", sh2); +\t $finish; + end + + $display(""PASSED""); + end + +endprogram :test + +module main; + + reg[7:0] shared = \'h55; + wire [7:0] not_shared = ~shared; + + test check(shared, not_shared); + +endmodule // main +" +" +module main; + + typedef enum logic [3:0] { WORD0, WORD1, WORD9=\'b1001, WORDC=\'b1100 } word_t; + + typedef union packed { + logic [3:0] bits; + word_t words; + } bits_t; + + bits_t foo; + + initial begin + foo.bits = \'b1001; + if (foo.bits !== \'b1001) begin +\t $display(""FAILED -- foo.bits=%b"", foo.bits); +\t $finish; + end + + if (foo.words !== WORD9) begin +\t $display(""FAILED -- foo.words=%b"", foo.words); +\t $finish; + end + + foo.words = WORDC; + if (foo.words !== WORDC) begin +\t $display(""FAILED -- foo.words=%b"", foo.words); +\t $finish; + end + if (foo.bits !== \'b1100) begin +\t $display(""FAILED -- foo.bits=%b"", foo.bits); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"module test; + + reg [1:0] bus; + reg [1:0] skewed_bus; + + integer delay0; initial delay0 = 5; + integer delay1; initial delay1 = 10; + + /* attempt to model skew across the bus using transport delays */ + + always @( bus[0] ) + begin + skewed_bus[0] <= #delay0 bus[0]; + end + + always @( bus[1] ) + begin + skewed_bus[1] <= #delay1 bus[1]; + end + + initial begin + #1 bus = 2\'b00; + #11 if (skewed_bus !== 2\'b00) begin +\t $display(""FAILED -- setup failed.""); +\t $finish; + end + + bus = 2\'b11; + + #4 if (skewed_bus !== 2\'b00) begin +\t $display(""FAILED -- changed far too soon""); +\t $finish; + end + + #2 if (skewed_bus !== 2\'b01) begin +\t $display(""FAILED -- partial change not right.""); +\t $finish; + end + + #5 if (skewed_bus !== 2\'b11) begin +\t $display(""FAILED -- final change not right""); +\t $finish; + end + + $display(""PASSED""); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate variable right shift in function + + +module main; + +reg globvar; + +reg [7:0] var1,var2,var3; +reg error; +reg [7:0] value; + +function [7:0] rshft; +input [7:0] var1,var2; +begin + rshft = var1 >> var2; +end +endfunction + +initial + begin + error = 0; + #1 ; + var1 = 8\'h80; + var2 = 8\'h7; + value = rshft(var1,var2); + #1; + if(value !== 8\'h1) + begin + error = 1; +\t$display (""FAILED - 80 >> 7 is %h"",value); + end + #1 ; + var1 = 8\'h80; + var2 = 8\'h6; + value = rshft(var1,var2); + #1; + if(value !== 8\'h2) + begin + error = 1; +\t$display (""FAILED - 80 >> 6 is %h"",value); + end + #1 ; + var1 = 8\'h80; + var2 = 8\'h5; + value = rshft(var1,var2); + #1; + if(value !== 8\'h4) + begin + error = 1; +\t$display (""FAILED - 80 >> 5 is %h"",value); + end + #1 ; + var1 = 8\'h80; + var2 = 8\'h4; + value = rshft(var1,var2); + #1; + if(value !== 8\'h8) + begin + error = 1; +\t$display (""FAILED - 80 >> 4 is %h"",value); + end + #1 ; + var1 = 8\'h80; + var2 = 8\'h3; + value = rshft(var1,var2); + #1; + if(value !== 8\'h10) + begin + error = 1; +\t$display (""FAILED - 80 >> 3 is %h"",value); + end + #1 ; + var1 = 8\'h80; + var2 = 8\'h2; + value = rshft(var1,var2); + #1; + if(value !== 8\'h20) + begin + error = 1; +\t$display (""FAILED - 80 >> 2 is %h"",value); + end + #1 ; + var1 = 8\'h80; + var2 = 8\'h1; + value = rshft(var1,var2); + #1; + if(value !== 8\'h40) + begin + error = 1; +\t$display (""FAILED - 80 >> 1 is %h"",value); + end + #1 ; + var1 = 8\'h80; + var2 = 8\'h0; + value = rshft(var1,var2); + #1; + if(value !== 8\'h80) + begin + error = 1; +\t$display (""FAILED - 80 >> 0 is %h"",value); + end + #1 ; + var1 = 8\'ha5; + var2 = 8\'h7; + value = rshft(var1,var2); + #1; + if(value !== 8\'h01) + begin + error = 1; +\t$display (""FAILED - a5 >> 7 is %h"",value); + end + #1 ; + var1 = 8\'ha5; + var2 = 8\'h1; + value = rshft(var1,var2); + #1; + if(value !== 8\'h52) + begin + error = 1; +\t$display (""FAILED - aa >> 1 is %h"",value); + end + if(error === 0) + $display(""PASSED""); + end + +endmodule // main +" +"module pr3064375; + +reg\t\tCLK; +reg\t\tRST; + +reg\t\tReg1; +reg\t\tReg2; + +initial begin + CLK = 0; + forever begin + #5 CLK = 1; + #5 CLK = 0; + end +end + +initial begin + RST = 1; + #20; + RST = 0; + #101; + $finish(0); +end + +always @(posedge CLK or posedge RST) begin + if (RST) + Reg1 <= 0; + else + Reg1 <= !Reg1; +end + +always @(negedge CLK or posedge RST) begin + if (RST) + Reg2 <= 0; + else + Reg2 <= Reg1; +end + +initial begin + $monitor(""CLK %b RST %b Reg1 %b Reg2 %b"", CLK, RST, Reg1, Reg2); +end + +endmodule +" +"module test(); + +wire a; + +supply0 b; +supply1 c; + +supply1 d; +supply0 e; + +wire f; +wire g; + +wire h; +wire i; + +supply1 j; +supply0 k; + +wire l; + +supply0 m; +supply1 n; + +assign d = 1\'b0; +assign e = 1\'b1; + +assign f = 1\'b0; +assign f = 1\'b1; + +assign g = 1\'b1; +assign g = 1\'b0; + +assign (strong1,strong0) h = 1\'b0; +assign ( weak1, weak0) h = 1\'b1; + +assign ( weak1, weak0) i = 1\'b0; +assign (strong1,strong0) i = 1\'b1; + +assign (supply1,supply0) j = 1\'b0; +assign (supply1,supply0) k = 1\'b1; + +wire [1:0] A = {1\'b1, a}; +wire [1:0] B = {1\'b1, b}; +wire [1:0] C = {1\'b1, c}; +wire [1:0] D = {1\'b1, d}; +wire [1:0] E = {1\'b1, e}; +wire [1:0] F = {1\'b1, f}; +wire [1:0] G = {1\'b1, g}; +wire [1:0] H = {1\'b1, h}; +wire [1:0] I = {1\'b1, i}; +wire [1:0] J = {1\'b1, j}; +wire [1:0] K = {1\'b1, k}; +wire [1:0] L = {1\'b1, l}; +wire [1:0] M = {1\'b1, m}; +wire [1:0] N = {1\'b1, n}; + +reg failed; + +initial begin + failed = 0; #1; + + $display(""A = %b, expect 1z"", A); if (A !== 2\'b1z) failed = 1; + $display(""B = %b, expect 10"", B); if (B !== 2\'b10) failed = 1; + $display(""C = %b, expect 11"", C); if (C !== 2\'b11) failed = 1; + $display(""D = %b, expect 11"", D); if (D !== 2\'b11) failed = 1; + $display(""E = %b, expect 10"", E); if (E !== 2\'b10) failed = 1; + $display(""F = %b, expect 1x"", F); if (F !== 2\'b1x) failed = 1; + $display(""G = %b, expect 1x"", G); if (G !== 2\'b1x) failed = 1; + $display(""H = %b, expect 10"", H); if (H !== 2\'b10) failed = 1; + $display(""I = %b, expect 11"", I); if (I !== 2\'b11) failed = 1; + $display(""J = %b, expect 1x"", J); if (J !== 2\'b1x) failed = 1; + $display(""K = %b, expect 1x"", K); if (K !== 2\'b1x) failed = 1; + force l = 1\'b0; #1; + $display(""L = %b, expect 10"", L); if (L !== 2\'b10) failed = 1; + force l = 1\'b1; #1; + $display(""L = %b, expect 11"", L); if (L !== 2\'b11) failed = 1; + force m = 1\'b1; #1; + $display(""M = %b, expect 11"", M); if (M !== 2\'b11) failed = 1; + force n = 1\'b0; #1; + $display(""N = %b, expect 10"", N); if (N !== 2\'b10) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module top_default; + initial begin + $printtimescale(top_default); + $printtimescale(top_timescale); + $printtimescale(top_resetall); + $printtimescale(top_timescale2); + $printtimescale(top_timescale3); + end +endmodule + +`resetall +`timescale 1ns/1ns +module top_timescale; + reg a; + initial a = 1'b1; +endmodule + +`resetall +`resetall +module top_resetall; + reg a; + initial a = 1'b0; +endmodule + +`resetall +`timescale 1ms/1ms +module top_timescale2; + reg a; + initial a = 1'b1; +endmodule + +`resetall +`timescale 1us/1us +module top_timescale3; + reg a; + initial a = 1'bz; +endmodule +" +"module test(); + +reg a, b; + +wire a1, a2, a3, a4, a5, a6, a7; + +assign (supply1, supply0) a1 = a; + +rtran t1(a1, a2); +rtran t2(a2, a3); +rtran t3(a3, a4); +rtran t4(a4, a5); +rtran t5(a5, a6); +rtran t6(a6, a7); + +wire a11, a12, a13, a14, a15, b11, b12, b13, b14, b15; +wire a21, a22, a23, a24, a25, b21, b22, b23, b24, b25; +wire a31, a32, a33, a34, a35, b31, b32, b33, b34, b35; +wire a41, a42, a43, a44, a45, b41, b42, b43, b44, b45; +wire a51, a52, a53, a54, a55, b51, b52, b53, b54, b55; + +assign (supply1, supply0) a11 = a, b11 = b; +assign (supply1, strong0) a12 = a, b12 = b; +assign (supply1, pull0) a13 = a, b13 = b; +assign (supply1, weak0) a14 = a, b14 = b; +assign (supply1, highz0) a15 = a, b15 = b; + +assign (strong1, supply0) a21 = a, b21 = b; +assign (strong1, strong0) a22 = a, b22 = b; +assign (strong1, pull0) a23 = a, b23 = b; +assign (strong1, weak0) a24 = a, b24 = b; +assign (strong1, highz0) a25 = a, b25 = b; + +assign ( pull1, supply0) a31 = a, b31 = b; +assign ( pull1, strong0) a32 = a, b32 = b; +assign ( pull1, pull0) a33 = a, b33 = b; +assign ( pull1, weak0) a34 = a, b34 = b; +assign ( pull1, highz0) a35 = a, b35 = b; + +assign ( weak1, supply0) a41 = a, b41 = b; +assign ( weak1, strong0) a42 = a, b42 = b; +assign ( weak1, pull0) a43 = a, b43 = b; +assign ( weak1, weak0) a44 = a, b44 = b; +assign ( weak1, highz0) a45 = a, b45 = b; + +assign ( highz1, supply0) a51 = a, b51 = b; +assign ( highz1, strong0) a52 = a, b52 = b; +assign ( highz1, pull0) a53 = a, b53 = b; +assign ( highz1, weak0) a54 = a, b54 = b; + +rtran t11(a11, b11); +rtran t12(a12, b12); +rtran t13(a13, b13); +rtran t14(a14, b14); +rtran t15(a15, b15); + +rtran t21(a21, b21); +rtran t22(a22, b22); +rtran t23(a23, b23); +rtran t24(a24, b24); +rtran t25(a25, b25); + +rtran t31(a31, b31); +rtran t32(a32, b32); +rtran t33(a33, b33); +rtran t34(a34, b34); +rtran t35(a35, b35); + +rtran t41(a41, b41); +rtran t42(a42, b42); +rtran t43(a43, b43); +rtran t44(a44, b44); +rtran t45(a45, b45); + +rtran t51(a51, b51); +rtran t52(a52, b52); +rtran t53(a53, b53); +rtran t54(a54, b54); +rtran t55(a55, b55); + +task display_strengths; + +input ta, tb; + +begin + a = ta; + b = tb; + #1; + $display(""a = %b b = %b"", a, b); + $display(""a1(%v) a2(%v) a3(%v) a4(%v) a5(%v) a6(%v) a7(%v)"", a1, a2, a3, a4, a5, a6, a7); + $display(""t11(%v %v) t12(%v %v) t13(%v %v) t14(%v %v) t15(%v %v)"", a11, b11, a12, b12, a13, b13, a14, b14, a15, b15); + $display(""t21(%v %v) t22(%v %v) t23(%v %v) t24(%v %v) t25(%v %v)"", a21, b21, a22, b22, a23, b23, a24, b24, a25, b25); + $display(""t31(%v %v) t32(%v %v) t33(%v %v) t34(%v %v) t35(%v %v)"", a31, b31, a32, b32, a33, b33, a34, b34, a35, b35); + $display(""t41(%v %v) t42(%v %v) t43(%v %v) t44(%v %v) t45(%v %v)"", a41, b41, a42, b42, a43, b43, a44, b44, a45, b45); + $display(""t51(%v %v) t52(%v %v) t53(%v %v) t54(%v %v) t55(%v %v)"", a51, b51, a52, b52, a53, b53, a54, b54, a55, b55); +end + +endtask + +initial begin + display_strengths(1\'bz, 1\'bz); + display_strengths(1\'bx, 1\'bz); + display_strengths(1\'b0, 1\'bz); + display_strengths(1\'b1, 1\'bz); + + display_strengths(1\'bz, 1\'bx); + display_strengths(1\'bx, 1\'bx); + display_strengths(1\'b0, 1\'bx); + display_strengths(1\'b1, 1\'bx); + + display_strengths(1\'bz, 1\'b0); + display_strengths(1\'bx, 1\'b0); + display_strengths(1\'b0, 1\'b0); + display_strengths(1\'b1, 1\'b0); + + display_strengths(1\'bz, 1\'b1); + display_strengths(1\'bx, 1\'b1); + display_strengths(1\'b0, 1\'b1); + display_strengths(1\'b1, 1\'b1); +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate continuous <= in assignment. +// + + +module main; + +reg globvar; + +reg [3:0] var1; +reg error; + +wire var2 = (var1 <= 4\'h02); + +initial + begin + error = 0; + var1 = 4\'h0 ; + #1 ; + if(var2 !== 1\'b1) + begin + $display(""FAILED continuous <= logical op (1)""); + error = 1; + end + #1 ; + var1 = 4\'h2; + #1 ; + if(var2 !== 1\'b1) + begin + $display(""FAILED continuos <= logical op (2)""); + error = 1; + end + #1 ; + var1 = 4\'h4; + #1 ; + if(var2 !== 1\'b0) + begin + $display(""FAILED continuos <= logical op (3)""); + error = 1; + end + if(error == 0) + $display(""PASSED""); + end + +endmodule // main +" +"module check (input signed [22:0] a, b, c); + wire signed [22:0] int_AB; + + assign int_AB = a / b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB != c) begin + $display(""ERROR""); + $finish; + end +end + +endmodule + +module stimulus (output reg signed [22:0] A, B); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; B= 1; + for (i=0; i>4;// 2 (<--- here) + output [c_w-1:0] a; + wire [c_w-1:0] a=\'h0; + + initial begin + $display(""p_w=%b, c_w=%b"", p_w, c_w); + + if (c_w !== 2) begin +\t$display(""FAILED -- c_w == %b"", c_w); +\t$finish; + end + + if ($bits(a) !== 2) begin +\t$display(""FAILED -- $bits(a) == %b"", $bits(a)); +\t$finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule + +module main; + wire [1:0] a; + port_test m (.a(a)); +endmodule +" +"module top; + // This will compile. + enum integer {IDLE, UNKNOWN=\'bx} en1; + // This is failing to compile. + enum integer {VAL, XX=32\'bx} en2; + + initial $display(""PASSED""); +endmodule +" +"// test_mis.v - Testbench for mis.bvrl +// 01-22-01 E. Brombaugh + +/* + * Copyright (c) 2001 Eric Brombaugh + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * The mis\'\' module was generated by the synopsis module compiler + * and is typical of the modules it generates. The testbench was hand + * coded. This file was merged into a single file using the Verilog + * preprocessor. + */ + +`timescale 1ns / 10 ps +module mis( y, a, b ); +input [3:0] a; +input [3:0] b; +output [12:0] y; +wire dpa_zero, dpa_one; +wire [5:0] const__1_24_; +wire [7:0] C0; +wire [6:0] const__2_33_; +wire [7:0] C1; +wire [12:0] y_1_; +assign dpa_zero= 1024\'h0; +assign dpa_one= 1024\'h1; +assign const__1_24_=- 1024\'h18; +assign const__2_33_=- 1024\'h21; + +/* mis.mcl:4 module mis (y, a, b); */ + +/* mis.mcl:5 input signed [3:0] a, b; */ + +/* mis.mcl:10 C0 = -24; */ + +assign C0= ((const__1_24_[4:0]-(const__1_24_[5]<<5))); + +/* mis.mcl:11 C1 = -33; */ + +assign C1= ((const__2_33_[5:0]-(const__2_33_[6]<<6))); + +/* mis.mcl:13 y = C0*a + C1*b; */ + +assign y_1_= ((C0[6:0]-(C0[7]<<7))*(a[2:0]-(a[3]<<3))+ + (C1[6:0]-(C1[7]<<7))*(b[2:0]-(b[3]<<3))); + +/* mis.mcl:6 output signed [12:0] y; */ + +assign y = y_1_[12:0]; + +/* mis.mcl:4 module mis (y, a, b); */ + +/* mis.mcl:13 y = C0*a + C1*b; */ + +/*User Defined Aliases */ +endmodule + +module test_mis; + reg [10:0] count; + + reg clk; + reg [3:0] a, b; + + wire [12:0] y; + + mis u1(y, a, b); + + initial + begin + count = 0; + clk = 0; + a = 0; + b = 0; + end + + always + #10 clk = ~clk; + + always @(posedge clk) + begin + a = count[3:0]; + b = count[7:4]; + + #10 + $display(""%h %h %h"", a, b, y); + + count = count + 1; + if(count == 0) + $finish(0); + end +endmodule +" +"/* I expected that p1=p2. But the generated output looks like: + +Icarus Verilog version 0.7 +Copyright 1998-2003 Stephen Williams +$Name: $ + + 0 p1=x p2=StX + 5 p1=1 p2=StX + 10 p1=0 p2=St0 + 15 p1=1 p2=St0 + 20 p1=0 p2=St0 + 25 p1=1 p2=St0 + 30 p1=0 p2=St0 + 35 p1=1 p2=St0 + 40 p1=0 p2=St0 + 45 p1=1 p2=St0 + 50 p1=0 p2=St0 + 55 p1=1 p2=St0 + 60 p1=0 p2=St0 + 65 p1=1 p2=St0 + 70 p1=0 p2=St0 + 75 p1=1 p2=St0 + 80 p1=0 p2=St0 + 85 p1=1 p2=St0 + 90 p1=0 p2=St0 + 95 p1=1 p2=St0 + + + +Model Technology ModelSim SE vsim 5.7c Simulator 2003.03 Mar 13 2003 + +# 0 p1=x p2=StX +# 5 p1=1 p2=StX +# 10 p1=0 p2=St0 +# 15 p1=1 p2=St0 +# 20 p1=0 p2=St0 +# 25 p1=1 p2=St0 +# 30 p1=0 p2=St0 +# 35 p1=1 p2=St0 +# 40 p1=0 p2=St0 +# 45 p1=1 p2=St0 +# 50 p1=0 p2=St0 +# 55 p1=1 p2=St0 +# 60 p1=0 p2=St0 +# 65 p1=1 p2=St0 +# 70 p1=0 p2=St0 +# 75 p1=1 p2=St0 +# 80 p1=0 p2=St0 +# 85 p1=1 p2=St0 +# 90 p1=0 p2=St0 +# 95 p1=1 p2=St0 +# +*/ +`timescale 1 ns / 1 ns + +module pulse; +reg p1,p2; + + + initial + begin + $monitor(""%t p1=%b p2=%v"",$time,p1,p2); + #101 $finish(0); + end + + + initial + repeat(10) + begin + #5 p1=1\'b1; + #5 p1=1\'b0; + end + + + initial + repeat(10) single_pulse(p2); + + + task single_pulse; + output p; + begin + #5 p=1\'b1; + #5 p=1\'b0; + end + endtask + +endmodule +" +"module test; + + parameter parm1 = 0; + parameter parm2 = parm1 == 0; + + initial begin +\t// if got here then we compiled +\tif (parm2) +\t $display(""PASSED""); +\telse +\t $display(""FAILED""); + end + +endmodule +" +"// pr1701921 + +module top; + + reg foo, bar; + wire blend; + + assign blend = foo; + assign blend = bar; + + initial begin + bar = 1; + // Bar explicitly has a 1 value, foo gets its initial x value. + // Together, they should drive to an x value. + #1 if (blend !== 1\'bx) begin +\t $display(""FAILED -- blend=%b (foo=%b, bar=%b)"", blend, foo, bar); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule +" +"module top; + localparam enum_start = 2\'d1; + + // This is an expression so the value just has to fit. + enum logic [3:0] { first = enum_start + 2\'d0, + second = enum_start + 2\'d1} my_enum; + + initial $display(""PASSED""); + +endmodule +" +"module test; + + reg [7:0] bus; + reg [7:0] skewed_bus; + + integer delay0; initial delay0 = 4; + integer delay1; initial delay1 = 8; + integer delay2; initial delay2 = 12; + integer delay3; initial delay3 = 16; + integer delay4; initial delay4 = 20; + integer delay5; initial delay5 = 24; + integer delay6; initial delay6 = 28; + integer delay7; initial delay7 = 32; + + /* model skew across the bus using transport delays */ + + always @( bus[0] ) + begin + skewed_bus[0] <= #delay0 bus[0]; + end + + always @( bus[1] ) + begin + skewed_bus[1] <= #delay1 bus[1]; + end + + always @( bus[2] ) + begin + skewed_bus[2] <= #delay2 bus[2]; + end + + always @( bus[3] ) + begin + skewed_bus[3] <= #delay3 bus[3]; + end + + always @( bus[4] ) + begin + skewed_bus[4] <= #delay4 bus[4]; + end + + always @( bus[5] ) + begin + skewed_bus[5] <= #delay5 bus[5]; + end + + always @( bus[6] ) + begin + skewed_bus[6] <= #delay6 bus[6]; + end + + always @( bus[7] ) + begin + skewed_bus[7] <= #delay7 bus[7]; + end + + + initial + begin + bus = {8{1\'b0}}; + #4; + bus = 8\'b00100100; + #4; + bus = 8\'b10000001; + #4; + bus = 8\'b00001001; + #4; + bus = 8\'b01100011; + #4; + bus = 8\'b00001101; + #4; + bus = 8\'b10001101; + #4; + bus = 8\'b01100101; + #4; + bus = 8\'b00010010; + #4; + bus = 8\'b00000001; + #4; + bus = 8\'b00001101; + #4; + bus = 8\'b01110110; + #4; + bus = 8\'b00111101; + #4; + bus = 8\'b11101101; + #4; + bus = 8\'b10001100; + #4; + bus = 8\'b11111001; + #4; + bus = 8\'b11000110; + #4; + bus = 8\'b11000101; + #4; + bus = 8\'b10101010; + #4; + bus = 8\'b11100101; + #4; + bus = 8\'b01110111; + #4; + bus = 8\'b00010010; + #4; + bus = 8\'b10001111; + #4; + bus = 8\'b11110010; + #4; + bus = 8\'b11001110; + #4; + bus = 8\'b11101000; + #4; + bus = 8\'b11000101; + #4; + bus = 8\'b01011100; + #4; + bus = 8\'b10111101; + #4; + bus = 8\'b00101101; + #4; + bus = 8\'b01100101; + #4; + bus = 8\'b01100011; + #4; + bus = 8\'b00001010; + #4; + bus = 8\'b10000000; + #4; + bus = 8\'b00100000; + #4; + bus = 8\'b10101010; + #4; + bus = 8\'b10011101; + #4; + bus = 8\'b10010110; + #4; + bus = 8\'b00010011; + #4; + bus = 8\'b00001101; + #4; + bus = 8\'b01010011; + #4; + bus = 8\'b01101011; + #4; + bus = 8\'b11010101; + #4; + bus = 8\'b00000010; + #4; + bus = 8\'b10101110; + #4; + bus = 8\'b00011101; + #4; + bus = 8\'b11001111; + #4; + bus = 8\'b00100011; + #4; + bus = 8\'b00001010; + #4; + bus = 8\'b11001010; + #4; + bus = 8\'b00111100; + #4; + bus = 8\'b11110010; + #4; + bus = 8\'b10001010; + #4; + bus = 8\'b01000001; + #4; + bus = 8\'b11011000; + #4; + bus = 8\'b01111000; + #4; + bus = 8\'b10001001; + #4; + bus = 8\'b11101011; + #4; + bus = 8\'b10110110; + #4; + bus = 8\'b11000110; + #4; + bus = 8\'b10101110; + #4; + bus = 8\'b10111100; + #4; + bus = 8\'b00101010; + #4; + bus = 8\'b00001011; + #4; + bus = 8\'b01110001; + #4; + bus = 8\'b10000101; + #4; + bus = 8\'b01001111; + #4; + bus = 8\'b00111011; + #4; + bus = 8\'b00111010; + #4; + bus = 8\'b01111110; + #4; + bus = 8\'b00010101; + #4; + bus = 8\'b11110001; + #4; + bus = 8\'b11011001; + #4; + bus = 8\'b01100010; + #4; + bus = 8\'b01001100; + #4; + bus = 8\'b10011111; + #4; + bus = 8\'b10001111; + #4; + bus = 8\'b11111000; + #4; + bus = 8\'b10110111; + #4; + bus = 8\'b10011111; + #4; + bus = 8\'b01011100; + #4; + bus = 8\'b01011011; + #4; + bus = 8\'b10001001; + #4; + bus = 8\'b01001001; + #4; + bus = 8\'b11010000; + #4; + bus = 8\'b11010111; + #4; + bus = 8\'b01010001; + #4; + bus = 8\'b10010110; + #4; + bus = 8\'b00001100; + #4; + bus = 8\'b11000010; + #4; + bus = 8\'b11001000; + #4; + bus = 8\'b01110111; + #4; + bus = 8\'b00111101; + #4; + bus = 8\'b00010010; + #4; + bus = 8\'b01111110; + #4; + bus = 8\'b01101101; + #4; + bus = 8\'b00111001; + #4; + bus = 8\'b00011111; + #4; + bus = 8\'b11010011; + #4; + bus = 8\'b10000101; + #4; + bus = 8\'b01111000; + #4; + bus = 8\'b01011011; + #4; + bus = 8\'b01001001; + #4; + bus = 8\'b00111111; + #4; + bus = 8\'b00101010; + #4; + bus = 8\'b01011000; + #4; + bus = 8\'b10000110; + #4; + bus = 8\'b10001110; + #4; + bus = 8\'b10011100; + #4; + bus = 8\'b11111010; + #4; + bus = 8\'b00100110; + #4; + bus = 8\'b01110011; + #4; + bus = 8\'b10100011; + #4; + bus = 8\'b00101111; + #4; + bus = 8\'b10110011; + #4; + bus = 8\'b01011111; + #4; + bus = 8\'b01000100; + #4; + bus = 8\'b11110111; + #4; + bus = 8\'b11001011; + #4; + bus = 8\'b11100110; + #4; + bus = 8\'b01011010; + #4; + bus = 8\'b00101001; + #4; + bus = 8\'b11101101; + #4; + bus = 8\'b11011010; + #4; + bus = 8\'b01100101; + #4; + bus = 8\'b10110101; + #4; + bus = 8\'b11011111; + #4; + bus = 8\'b01111001; + #4; + bus = 8\'b01000100; + end + + initial + begin + #2; + if (skewed_bus !== 8\'bxxxxxxxx) + begin + $write(""FAILED -- expected xxxxxxxx ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'bxxxxxxx0) + begin + $write(""FAILED -- expected xxxxxxx0 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'bxxxxxx00) + begin + $write(""FAILED -- expected xxxxxx00 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'bxxxxx001) + begin + $write(""FAILED -- expected xxxxx001 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'bxxxx0101) + begin + $write(""FAILED -- expected xxxx0101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'bxxx00001) + begin + $write(""FAILED -- expected xxx00001 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'bxx000011) + begin + $write(""FAILED -- expected xx000011 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'bx0101001) + begin + $write(""FAILED -- expected x0101001 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00000101) + begin + $write(""FAILED -- expected 00000101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00001100) + begin + $write(""FAILED -- expected 00001100 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10101111) + begin + $write(""FAILED -- expected 10101111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01000001) + begin + $write(""FAILED -- expected 01000001 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00000000) + begin + $write(""FAILED -- expected 00000000 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00110111) + begin + $write(""FAILED -- expected 00110111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11001101) + begin + $write(""FAILED -- expected 11001101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00000100) + begin + $write(""FAILED -- expected 00000100 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00011101) + begin + $write(""FAILED -- expected 00011101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00111100) + begin + $write(""FAILED -- expected 00111100 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01101011) + begin + $write(""FAILED -- expected 01101011 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00101100) + begin + $write(""FAILED -- expected 00101100 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01010111) + begin + $write(""FAILED -- expected 01010111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10100001) + begin + $write(""FAILED -- expected 10100001 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11001110) + begin + $write(""FAILED -- expected 11001110 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11000111) + begin + $write(""FAILED -- expected 11000111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11100010) + begin + $write(""FAILED -- expected 11100010 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10110110) + begin + $write(""FAILED -- expected 10110110 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11111010) + begin + $write(""FAILED -- expected 11111010 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11000101) + begin + $write(""FAILED -- expected 11000101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00011000) + begin + $write(""FAILED -- expected 00011000 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00101101) + begin + $write(""FAILED -- expected 00101101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11000101) + begin + $write(""FAILED -- expected 11000101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11101101) + begin + $write(""FAILED -- expected 11101101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11011101) + begin + $write(""FAILED -- expected 11011101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11011110) + begin + $write(""FAILED -- expected 11011110 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11100010) + begin + $write(""FAILED -- expected 11100010 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00100000) + begin + $write(""FAILED -- expected 00100000 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10101000) + begin + $write(""FAILED -- expected 10101000 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01100011) + begin + $write(""FAILED -- expected 01100011 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01000000) + begin + $write(""FAILED -- expected 01000000 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00001111) + begin + $write(""FAILED -- expected 00001111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00101111) + begin + $write(""FAILED -- expected 00101111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10110001) + begin + $write(""FAILED -- expected 10110001 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00010111) + begin + $write(""FAILED -- expected 00010111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10011011) + begin + $write(""FAILED -- expected 10011011 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10000000) + begin + $write(""FAILED -- expected 10000000 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10011110) + begin + $write(""FAILED -- expected 10011110 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00000011) + begin + $write(""FAILED -- expected 00000011 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01110101) + begin + $write(""FAILED -- expected 01110101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01001111) + begin + $write(""FAILED -- expected 01001111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01001110) + begin + $write(""FAILED -- expected 01001110 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10111010) + begin + $write(""FAILED -- expected 10111010 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00000010) + begin + $write(""FAILED -- expected 00000010 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10001000) + begin + $write(""FAILED -- expected 10001000 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01101110) + begin + $write(""FAILED -- expected 01101110 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10001011) + begin + $write(""FAILED -- expected 10001011 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00010000) + begin + $write(""FAILED -- expected 00010000 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01111000) + begin + $write(""FAILED -- expected 01111000 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10100001) + begin + $write(""FAILED -- expected 10100001 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01001001) + begin + $write(""FAILED -- expected 01001001 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10011010) + begin + $write(""FAILED -- expected 10011010 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11011010) + begin + $write(""FAILED -- expected 11011010 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01101110) + begin + $write(""FAILED -- expected 01101110 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11000110) + begin + $write(""FAILED -- expected 11000110 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00110100) + begin + $write(""FAILED -- expected 00110100 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11101111) + begin + $write(""FAILED -- expected 11101111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10001011) + begin + $write(""FAILED -- expected 10001011 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11111001) + begin + $write(""FAILED -- expected 11111001 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10101001) + begin + $write(""FAILED -- expected 10101001 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10100111) + begin + $write(""FAILED -- expected 10100111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10010110) + begin + $write(""FAILED -- expected 10010110 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00101010) + begin + $write(""FAILED -- expected 00101010 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01001011) + begin + $write(""FAILED -- expected 01001011 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00011101) + begin + $write(""FAILED -- expected 00011101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11111101) + begin + $write(""FAILED -- expected 11111101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00110000) + begin + $write(""FAILED -- expected 00110000 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00110010) + begin + $write(""FAILED -- expected 00110010 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01011001) + begin + $write(""FAILED -- expected 01011001 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00110111) + begin + $write(""FAILED -- expected 00110111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01001110) + begin + $write(""FAILED -- expected 01001110 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11101101) + begin + $write(""FAILED -- expected 11101101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11011011) + begin + $write(""FAILED -- expected 11011011 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01001110) + begin + $write(""FAILED -- expected 01001110 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00010101) + begin + $write(""FAILED -- expected 00010101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10111111) + begin + $write(""FAILED -- expected 10111111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11111001) + begin + $write(""FAILED -- expected 11111001 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10011000) + begin + $write(""FAILED -- expected 10011000 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10011001) + begin + $write(""FAILED -- expected 10011001 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11001011) + begin + $write(""FAILED -- expected 11001011 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01000100) + begin + $write(""FAILED -- expected 01000100 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00010010) + begin + $write(""FAILED -- expected 00010010 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11010100) + begin + $write(""FAILED -- expected 11010100 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01010110) + begin + $write(""FAILED -- expected 01010110 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11011001) + begin + $write(""FAILED -- expected 11011001 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11000011) + begin + $write(""FAILED -- expected 11000011 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00001100) + begin + $write(""FAILED -- expected 00001100 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10000110) + begin + $write(""FAILED -- expected 10000110 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01011011) + begin + $write(""FAILED -- expected 01011011 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11110101) + begin + $write(""FAILED -- expected 11110101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11111101) + begin + $write(""FAILED -- expected 11111101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00011011) + begin + $write(""FAILED -- expected 00011011 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00101111) + begin + $write(""FAILED -- expected 00101111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01111000) + begin + $write(""FAILED -- expected 01111000 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01110101) + begin + $write(""FAILED -- expected 01110101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00010011) + begin + $write(""FAILED -- expected 00010011 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00001001) + begin + $write(""FAILED -- expected 00001001 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01011010) + begin + $write(""FAILED -- expected 01011010 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10111110) + begin + $write(""FAILED -- expected 10111110 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11001000) + begin + $write(""FAILED -- expected 11001000 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01011010) + begin + $write(""FAILED -- expected 01011010 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01101110) + begin + $write(""FAILED -- expected 01101110 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00110100) + begin + $write(""FAILED -- expected 00110100 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00001110) + begin + $write(""FAILED -- expected 00001110 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01001011) + begin + $write(""FAILED -- expected 01001011 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00011111) + begin + $write(""FAILED -- expected 00011111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10010011) + begin + $write(""FAILED -- expected 10010011 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10100011) + begin + $write(""FAILED -- expected 10100011 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11110111) + begin + $write(""FAILED -- expected 11110111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10101010) + begin + $write(""FAILED -- expected 10101010 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01100101) + begin + $write(""FAILED -- expected 01100101 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00111111) + begin + $write(""FAILED -- expected 00111111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b10110110) + begin + $write(""FAILED -- expected 10110110 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b00000010) + begin + $write(""FAILED -- expected 00000010 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11011111) + begin + $write(""FAILED -- expected 11011111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01100001) + begin + $write(""FAILED -- expected 01100001 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b01001000) + begin + $write(""FAILED -- expected 01001000 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11111111) + begin + $write(""FAILED -- expected 11111111 ""); + $display(""received %b "", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8\'b11001001) + begin + $write(""FAILED -- expected 11001001 ""); + $display(""received %b "", skewed_bus); + $finish; + end + $display(""PASSED""); + end + +endmodule +" +"/* + * Copyright (c) 1998 Philips Semiconductors (Stefan.Thiede@sv.sc.philips.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +*/ +// 9/7/99 - SDW - Added a PASSED message - no functional checking needed + + +module test(); +wire [1:0] a; +wire [9:0] b; +wire [0:9] d; +a a1(.a(c)); +b b1(.a(a[0])); +c ci(.a({a, b})); +d d1(.a({d[0:9], a[1:0]}), .d(c)); +f f(a); +a a3(a[1]); +a a4({a[1]}); +g g({a,b}); +e e(); + +initial + $display(""PASSED""); +endmodule + +module a(a); +input a; +endmodule + + +module b(.a(b)); +input b; +endmodule + +module c(.a({b, c}), ); +input [10:0] b; +input c; +endmodule + +module d(.a({b, c}), d); +input [10:0] b; +input c, d; +endmodule + +module e(); +endmodule + +module f({a, b}); +input a, b; +endmodule +module g(a); +input [11:0] a; +endmodule +" +"module test (); + parameter t=0; + reg t_not, t_zero; + + generate + if (!t) begin + initial t_not = 1; + end + endgenerate + + generate + if (t==0) begin + initial t_zero = 1; + end + endgenerate + + initial begin +\t#1 if (t_not !== 1) begin +\t\t$display(""FAILED -- t_not=%b"", t_not); +\t\t$finish; +\tend +\tif (t_zero !== 1) begin +\t\t$display(""FAILED -- t_zero=%b"", t_zero); +\t\t$finish; +\tend +\t$display(""PASSED""); + end +endmodule +" +"module t(); + + reg passed = 1; + + task abc; + input [7:0] a; + + begin +\t if(a == 1) +\t $display(""OK""); +\t else +\t begin $display(""FAILURE""); passed = 0; end + end + endtask + + reg [7:0] b; + + initial + begin +\t#1 ; +\tabc(500 >> 8); +\tb = 500 >> 8; +\tabc(b); + +\tif (passed) +\t $display(""PASSED""); + end +endmodule +" +"`define VUG_PCREL(u, uch) ({ {(uch - 12 - 1 > 0 ? uch - 12 - 1 : 1){u[11]}}, \\ + u[10:0], 2\'b00 }) + +module t(); + +parameter uch = 16; +parameter u_hossz = 32; +parameter u_prefix = 3; + +reg [u_hossz - u_prefix - 1:0] v_utas; +reg [uch - 1:0] v_cim; +wire [uch - 1:0] v_ugras_ide; + +assign v_ugras_ide = v_cim + `VUG_PCREL(v_utas, uch); + +initial +begin +\tv_utas = \'h0fff; +\tv_cim = \'h7; +\t#1; + +\tif(v_ugras_ide !== \'h3) +\t\t$display(""FAILED""); +\telse +\t\t$display(""PASSED""); + +\t$finish; +end + +endmodule +" +"module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:0]; + +assign Array[0][0] = In[0]; +assign Array[0][7:1] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[N:0] = Array[0][7:1]; +end + +endmodule +" +"module top; + reg q, d; + event foo; + + always_comb begin + @foo q = d; + end + + initial $display(""Expected compile failure!""); + +endmodule +" +"module top; + reg foo; + always @* foo <= 0; + initial #1 $display(""foo is %b"", foo); +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Basic ifdef test with else, no define +// + + +module ifdef1; + +reg error ; + + +`ifdef NOCODE +initial + begin + #20; + error = 1; + #20; + end +`else +initial + begin + #20; + error = 0; + #20; + end +`endif + +initial + begin + #1; + error = 1; + #40; + if(error == 0) + $display(""PASSED""); + else + $display(""FAILED""); + end + +endmodule // main +" +"/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: deposit.v,v 1.4 2001/11/22 04:36:33 sib4 Exp $ + +// Test for vpi_put_value() to properly propagate in structural context. + +module deposit_test; + + reg ck; + + reg start; + initial start = 0; + +`ifdef RTL + + reg [3:0] cnt; + wire cnt_tc = &cnt; + + always @(posedge ck) + if (start | ~cnt_tc) + cnt <= cnt + 1; + +`else // !ifdef RTL + + wire [3:0] cnt; + wire [3:0] cnt_1; + wire [3:0] cnt_c; + wire cnt_tc; + wire ne, e; + + and (cnt_tc, cnt[0], cnt[1], cnt[2], cnt[3]); + not (ne, cnt_tc); + or (e, ne, start); + + had A0 (cnt[0], 1\'b1, cnt_c[0], cnt_1[0]); + had A1 (cnt[1], cnt_c[0], cnt_c[1], cnt_1[1]); + had A2 (cnt[2], cnt_c[1], cnt_c[2], cnt_1[2]); + had A3 (cnt[3], cnt_c[2], cnt_c[3], cnt_1[3]); + + dffe C0 (ck, e, cnt_1[0], cnt[0]); + dffe C1 (ck, e, cnt_1[1], cnt[1]); + dffe C2 (ck, e, cnt_1[2], cnt[2]); + dffe C3 (ck, e, cnt_1[3], cnt[3]); + +`endif // !ifdef RTL + + integer r0; initial r0 = 0; + integer r1; initial r1 = 0; + + always + begin +\t#5 ck <= 0; +\t#4; +\t$display(""%b %b %d %d"", cnt, cnt_tc, r0, r1); +\tif (cnt_tc === 1\'b0) r0 = r0 + 1; +\tif (cnt_tc === 1\'b1) r1 = r1 + 1; +\t#1 ck <= 1; + end + + initial + begin +\t// $dumpfile(""deposit.vcd""); +\t// $dumpvars(0, deposit_test); +\t#22; +`ifdef RTL +\tcnt <= 4\'b 1010; +`else +\t$deposit(C0.Q, 1\'b0); +\t$deposit(C1.Q, 1\'b1); +\t$deposit(C2.Q, 1\'b0); +\t$deposit(C3.Q, 1\'b1); +`endif +\t#1 if (cnt !== 4\'b1010) +\t $display(""FAILED""); +\t#99; +\t$display(""%d/%d"", r0, r1); +\tif (r0===5 && r1===5) +\t $display(""PASSED""); +\telse +\t $display(""FAILED""); +\t$finish; + end + +endmodule + +`ifdef RTL +`else + +module dffe (CK, E, D, Q); + input CK, E, D; + output Q; + wire qq; + UDP_dffe ff (qq, CK, E, D); + buf #1 (Q, qq); +endmodule + +primitive UDP_dffe (q, cp, e, d); + output q; + reg\t q; + input cp, e, d; + table + (01) 1 1 : ? : 1 ; + (01) 1 0 : ? : 0 ; + * 0 ? : ? : - ; + * ? 1 : 1 : - ; + * ? 0 : 0 : - ; + (1x) ? ? : ? : - ; + (?0) ? ? : ? : - ; + ? ? * : ? : - ; + ? * ? : ? : - ; + endtable +endprimitive + +module had (A, B, C, S); + input A, B; + output C, S; + xor s (S, A, B); + and c (C, A, B); +endmodule + +`endif // !ifdef RTL +" +"package ivl_uvm_pkg; + virtual class uvm_test; + task ok; + $display(""PASSED""); + endtask + endclass : uvm_test +endpackage : ivl_uvm_pkg + +package test_pkg; + import ivl_uvm_pkg::*; + class sanity_test extends uvm_test; + endclass : sanity_test +endpackage : test_pkg + +module m; + + import test_pkg::*; + + sanity_test obj; + + initial begin + obj = new; + obj.ok; + end + +endmodule : m +" +"module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:0]; + +assign Array[0][0] = In[0]; +assign Array[0][7:1] = In[N:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:1] = Array[0][7:1]; +end + +endmodule +" +"module test; + + parameter [39:0] foo = 5; + + initial begin + if ($bits(foo) != 40) begin +\t $display(""FAILED -- $bits(foo) == %d"", $bits(foo)); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // test +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate variable left shift in assign + + +module main; + +reg globvar; + +reg [7:0] var1,var2,var3; +reg error; +wire [7:0] value; +assign value = var1 << var2; + +initial + begin + error = 0; + #1 ; + var1 = 8\'h1; + var2 = 8\'h0; + #1; + if(value !== 8\'h1) + begin + error = 1; +\t$display (""FAILED - 1 << 0 is %h"",value); + end + #1 ; + var1 = 8\'h1; + var2 = 8\'h1; + #1; + if(value !== 8\'h2) + begin + error = 1; +\t$display (""FAILED - 1 << 1 is %h"",value); + end + #1 ; + var1 = 8\'h1; + var2 = 8\'h2; + #1; + if(value !== 8\'h4) + begin + error = 1; +\t$display (""FAILED - 1 << 2 is %h"",value); + end + #1 ; + var1 = 8\'h1; + var2 = 8\'h3; + #1; + if(value !== 8\'h8) + begin + error = 1; +\t$display (""FAILED - 1 << 3 is %h"",value); + end + #1 ; + var1 = 8\'h1; + var2 = 8\'h4; + #1; + if(value !== 8\'h10) + begin + error = 1; +\t$display (""FAILED - 1 << 4 is %h"",value); + end + #1 ; + var1 = 8\'h1; + var2 = 8\'h5; + #1; + if(value !== 8\'h20) + begin + error = 1; +\t$display (""FAILED - 1 << 5 is %h"",value); + end + #1 ; + var1 = 8\'h1; + var2 = 8\'h6; + #1; + if(value !== 8\'h40) + begin + error = 1; +\t$display (""FAILED - 1 << 6 is %h"",value); + end + #1 ; + var1 = 8\'h1; + var2 = 8\'h7; + #1; + if(value !== 8\'h80) + begin + error = 1; +\t$display (""FAILED - 1 << 6 is %h"",value); + end + #1 ; + var1 = 8\'ha5; + var2 = 8\'h7; + #1; + if(value !== 8\'h80) + begin + error = 1; +\t$display (""FAILED - a5 << 7 is %h"",value); + end + #1 ; + var1 = 8\'ha5; + var2 = 8\'h1; + #1; + if(value !== 8\'h4a) + begin + error = 1; +\t$display (""FAILED - aa << 1 is %h"",value); + end + if(error === 0) + $display(""PASSED""); + end + +endmodule // main +" +"module main; + + initial begin + # 32 $display(""PASSED""); + $finish; + end + + // This delay is \'h1_00000010. The idea here is if the delay is + // only treated as 32 bits anywhere in the processing, then the + // high bits are truncated, and it becomes 16, which is less then + // the 32 above and we fail. + initial begin + # 4294967312 $display(""FAILED -- time=%d"", $time); + $finish; + end +endmodule // main +" +"module test(); + +wire [7:0] value; +wire pass; + +assign value[3:0] = 4\'d2; + +assign pass = (value === 8\'bzzzz0010); + +initial begin + #2 $display(""%b %b"", value, pass); + if (pass === 1) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"// Eleven basic tests in here: +// 1. int must be initialised before any initial or always block +// 2. assignments to (unsigned) int with random numbers +// 3. assignments to (unsigned) int with random values including X and Z +// 4. converting unsigned integers to unsigned int +// 5. converting signed integers to unsigned int +// 6. converting integers including X and Z states to unsigned int +// 7. trying unsigned sums (procedural, function, task and module) +// 8. trying unsigned mults (procedural, function and task) +// 9. trying relational operators +// 10. smaller signed numbers to unsigned int (signed extension) +// 11. trying some concatenations from bytes, shortints to ints + +module mu_add (input int unsigned a, b, output int unsigned sc, ss); + assign sc = a + b; + always @(a, b) ss = a + b; +endmodule + +module main; + parameter N_REPS = 500; // repetition with random numbers + parameter XZ_REPS = 500; // repetition with \'x \'z values + parameter UMAX = \'hffff_ffff; + parameter MAX8 = 256; + parameter MAX16 = 65536; + parameter LEN = 32; + // variables used as golden references + reg unsigned [LEN-1:0] ar; // holds numbers + reg unsigned [LEN-1:0] ar_xz; // holds \'x and/or \'z in random positions + reg unsigned [LEN-1:0] ar_expected; + integer unsigned ui; + integer signed si; + reg signed [LEN/2-1:0] slice; + + // type assumed tested before + byte unsigned pt1, pt2; + shortint unsigned ps1, ps2; + + // types to be tested + int unsigned bu; // holds numbers + int unsigned bu_xz; // \'x and \'z are attempted on this + int unsigned bresult; // hold results from sums and mults + int unsigned mcaresult; // wired to a module instance + int unsigned mabresult; // also wired to a module instance + + + integer i; + + // continuous assigments + // type LHS type RHS + // --------- --------- + // int 4-value logic + assign bu = ar; + assign bu_xz = ar_xz; + + // module instantiation + mu_add duv (.a(bu), .b(bu_xz), .sc(mcaresult), .ss(mabresult) ); + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if (bu !== 32\'b0 || bu_xz !== 32\'b0 || bresult !== 32\'b0 || mcaresult !== 32\'b0 || mabresult !== 32\'b0) + begin + $display (""FAILED - time zero initialisation incorrect: %b %b"", bu, bu_xz); + $finish; + end + // driving int type with unsigned random numbers from a variable + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = {$random}; + #1; + if (bu !== ar) + begin + $display (""FAILED - incorrect assigment to int: %b"", bu); + $finish; + end + end + # 1; + // attempting to drive variables having \'x \'z values into type unsigned int + // \'x \'z injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + ar = {$random}; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0 + begin + $display (""FAILED - incorrect assigment to int (when \'x \'z): %b"", bu); + $finish; + end + end + // converting unsigned integers to unsigned int + // truncation expected (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ui = {$random}; + #1; + force bu = ui; + #1; + if (bu !== ui) + begin + $display (""FAILED - incorrect truncation from unsigned integer to int: %b"", bu); + $finish; + end + end + release bu; + // converting signed integers to unsigned ints + // truncation expected (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + si = $random; + #1; + force bu = si; + #1; + if (bu !== si) + begin + $display (""FAILED - incorrect truncation from signed integer to int: %b mismatchs %b"", bu, si); + $finish; + end + end + release bu; + // converting integers having \'x \'z values into type unsigned int + // \'x \'z injections (Section 4.3.2 of IEEE 1850 LRM) + // truncation and coercion to zero expected + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + si = $random; + ar_xz = xz_inject (si); + si = ar_xz; + ar_expected = xz_expected (ar_xz); + #1; + force bu_xz = si; + #1; + if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0 + begin + $display (""FAILED - incorrect conversion from integer (with \'x \'z) to int: %b mismatchs %b"", bu_xz, ar_expected); + $finish; + end + end + release bu_xz; + // trying unsigned sums + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = {$random}; + ar_xz = {$random}; + #1; + bresult = bu + bu_xz; + #1; + if ( bresult !== u_sum(ar, ar_xz) ) + begin + $display (""FAILED - incorrect addition of unsigned ints: %0d mismatchs %0d"", bresult, u_sum(ar, ar_xz)); + $finish; + end + // invoking shortint sum function + if ( fu_sum (bu, bu_xz) !== u_sum(ar, ar_xz) ) + begin + $display (""FAILED - incorrect addition of unsigned int in function""); + $finish; + end + // invoking byte sum task + tu_sum (bu, bu_xz, bresult); + if ( bresult !== u_sum(ar, ar_xz) ) + begin + $display (""FAILED - incorrect addition of unsigned int in task: %0d mismatchs %0d"", bresult, u_sum(ar, ar_xz)); + $finish; + end + // checking byte sum from module + if ( mcaresult !== u_sum(ar, ar_xz) || mabresult !== u_sum(ar, ar_xz)) + begin + $display (""FAILED - incorrect addition of unsigned int from module""); + $finish; + end + end + // trying unsigned mults + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = ({$random} % UMAX) << (LEN/2); + ar_xz = ({$random} % UMAX) << (LEN/2 - 1); + #1; + bresult = bu * bu_xz; // truncated multiplication + #1; + if ( bresult !== uh_mul(ar, ar_xz) ) + begin + $display (""FAILED - incorrect multiplication of unsigned ints (truncated)""); + $finish; + end + #1; + ps1 = {$random} % \'hffff; + ps2 = {$random} % \'hffff; + #1; + bresult = ps1 * ps2; // int = shortint x shortint + #1; + if ( bresult !== u_mul(ps1, ps2) ) + begin + $display (""FAILED - incorrect multiplication of unsigned input shorints""); + $finish; + end + // invoking shortint mult function (byte*byte) + if ( fu_mul (ps1, ps2) !== u_mul(ps1, ps2) ) + begin + $display (""FAILED - incorrect product of unsigned shortint for a function returning unsigned int""); + $finish; + end + // invoking shortint mult task (byte*byte) + tu_mul (ps1, ps2, bresult); + if ( bresult !== u_mul(ps1, ps2) ) + begin + $display (""FAILED - incorrect product of unsigned shortint in task returning unsigned int""); + $finish; + end + end + // trying relational operators + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = {$random}; + ar_xz = {$random}; + #1; + if ( (bu < bu_xz ) !== (ar < ar_xz) ) + begin + $display (""FAILED - incorrect \'less than\' on unsigned ints""); + $finish; + end + if ( (bu <= bu_xz ) !== (ar <= ar_xz) ) + begin + $display (""FAILED - incorrect \'less than or equal\' on unsigned ints""); + $finish; + end + if ( (bu > bu_xz ) !== (ar > ar_xz) ) + begin + $display (""FAILED - incorrect \'greater than\' on unsigned ints""); + $finish; + end + if ( (bu >= bu_xz ) !== (ar >= ar_xz) ) + begin + $display (""FAILED - incorrect \'greater than or equal\' than on unsigned ints""); + $finish; + end + if ( (bu == bu_xz ) !== (ar == ar_xz) ) + begin + $display (""FAILED - incorrect \'equal to\' on unsigned ints""); + $finish; + end + if ( (bu != bu_xz ) !== (ar != ar_xz) ) + begin + $display (""FAILED - incorrect \'not equal to\' on unsigned ints""); + $finish; + end + end + # 1; + // signed small numbers to unsigned int + for (i = 0; i < (1<= valb) begin +\t $display(""FAILED -- vala(%b) is >= valb(%b)"", vala, valb); +\t $finish; + end + + if (vala > valb) begin +\t $display(""FAILED -- vala(%b) is > valb(%b)"", vala, valb); +\t $finish; + end + + if (valb <= vala) begin +\t $display(""FAILED -- valb(%b) is <= vala(%b)"", valb, vala); +\t $finish; + end + + if (valb < vala) begin +\t $display(""FAILED -- valb(%b) is < vala(%b)"", valb, vala); +\t $finish; + end + + if (valc <= valb) begin +\t $display(""FAILED -- valc(%b) is not > valb(%b)"", valc, valb); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Tests size casting of complex expressions. + +module resize(output wire logic [4:0] result); + logic [6:0] a; + assign result = (5\'(a + 2)); + + initial begin + a = 7\'d39; + end +endmodule + +module resize_test(); + logic [4:0] result; + resize dut(result); + + initial begin + #1; + + if(result !== 5\'d9) begin + $display(""FAILED""); + $finish(); + end + + $display(""PASSED""); + end +endmodule +" +" +/* + * Sign extend input + * T can be 0 for <<, 1 for >>, 2 for <<< or 3 for >>>. + */ +module sign_ext + #(parameter WI = 4, WO = 6) + (input wire signed [WI-1:0] D, + output wire signed [WO-1:0] Q + /* */); + + assign Q = D; + +endmodule + +" +"module top; + reg a; + reg q, d; + reg clk; + event foo; + real rl; + int ar []; + int start = 0; + int stop = 1; + int step = 1; + int done = 0; + + task a_task; + real trl; + event tevt; + reg tvr; + $display(""user task""); + endtask + + always_ff @(posedge clk) begin: blk_name + event int1, int2; + real intrl; + q = d; + -> foo; + rl = 0.0; + rl <= 1.0; + ar = new [2]; + for (int idx = start; idx < stop; idx += step) $display(""For: %0d"", idx); + for (int idx = 0; done; idx = done + 1) $display(""Should never run!""); + for (int idx = 0; idx; done = done + 1) $display(""Should never run!""); + for (int idx = 0; idx; {done, idx} = done + 1) $display(""Should never run!""); + for (int idx = 0; idx; idx <<= 1) $display(""Should never run!""); + for (int idx = 0; idx; idx = idx << 1) $display(""Should never run!""); + $display(""array size: %0d"", ar.size()); + ar.delete(); + $display(""array size: %0d"", ar.size()); + a_task; + assign a = 1\'b0; + deassign a; + do $display(""do/while""); + while (a); + force a = 1\'b1; + release a; + while(a) begin + $display(""while""); + a = 1\'b0; + end + repeat(2) $display(""repeat""); + disable out_name; + forever begin + $display(""forever""); + disable blk_name; // This one should not generate a warning + end + end + + initial begin + #1 clk = 1\'b1; + #0 $display(""Expect compile warnings!\ +PASSED""); + end + + initial begin: out_name + #2 $display(""FAILED""); + end + +endmodule +" +"module top; + reg real [1:0] a; + + initial begin + a[0] = 0.3; + a[1] = 0.4; + $display(""FAILED""); + end +endmodule +" +"// Sample Code +module main( stb, a ); + + input stb; + output [1:0] a; + wire [1:0] b; + + buf (a[0], b[0]); + buf (a[1], b[1]); + + specify + (posedge stb => (a[0]:1'bx)) = 1.0; + (posedge stb => (a[1]:1'bx)) = 1.0; + endspecify + +endmodule // main +" +"module top; + reg a, b, c, d, e; + wand out; + + assign out = a; + assign out = b; + assign out = c; + assign out = d; + assign out = e; + + initial begin + a = 1\'b1; + b = 1\'b0; + c = 1\'b1; + d = 1\'b1; + e = 1\'b1; + #1; + if (out !== 1\'b0) $display(""FAILED: expected 1\'b1, got %b"", out); + else $display(""PASSED""); + end +endmodule +" +"module main; + + parameter N = 2**4; + + initial begin + if (N != 16) begin +\t $display(""FAILED -- N = %u (%h)"", N, N); +\t $finish; + end + + if (2**4 != 16) begin +\t $display(""FAILED -- 2**16 = %u"", 2**16); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"//--------------------------------------------------------------------------- +// +//--------------------------------------------------------------------------- + module xor_try; + + reg [1:0] inp_xor; // The two-bit inputs to the XOR + reg out_xor; // The XOR output + reg clk; + + initial begin clk = 1'b1; $sn; #160 $finish(0); end + always #50 clk = ~clk; + // The clock + + always @(posedge clk) out_xor = #1 (inp_xor[0] ^ inp_xor[1]); + // The actual operation + endmodule + +" +"module test ; + +wire a; +reg sel,in0, in1; +reg error; + +assign a = sel ? in1 : in0 ; + +initial + begin + error = 0; + #1; + sel = 0; + in0 = 0; + in1 = 0; + #1; + if(a !== 0) + begin + $display(""FAILED - (1) Mux error sel=0, in0=in0=0 yet out != 0""); + $display(""sel=%b,in0=%b,in1=%b,out=%b"", + sel,in0,in1,a); + error = 1; + end + #1; + in0 = 1; + #1; + if(a !== 1) + begin + $display(""FAILED - (2) Mux error sel=0, in0=1,in1=0 yet out != 1""); + $display(""sel=%b,in0=%b,in1=%b,out=%b"", + sel,in0,in1,a); + error = 1; + end + + #1; + sel = 1; + #1; + if(a !== 0) + begin + $display(""FAILED - (3) Mux error sel=1, in0=1,in1=0 yet out != 0""); + $display(""sel=%b,in0=%b,in1=%b,out=%b"", + sel,in0,in1,a); + error = 1; + end + #1; + in1 = 1; + #1; + if(a !== 1) + begin + $display(""FAILED - (5) Mux error sel=1, in0=1,in1=1 yet out != 1""); + $display(""sel=%b,in0=%b,in1=%b,out=%b"", + sel,in0,in1,a); + error = 1; + end + #1; + in0 = 0; + #1; + if(a !== 1) + begin + $display(""FAILED - (6) Mux error sel=1, in0=0,in1=1 yet out != 1""); + $display(""sel=%b,in0=%b,in1=%b,out=%b"", + sel,in0,in1,a); + error = 1; + end + #1; + in1 = 0; + sel = 1\'bx; + #1; + if(a !== 0) + begin + $display(""FAILED - (8) Mux error sel=X, in0=0,in1=0 yet out != 0""); + $display(""sel=%b,in0=%b,in1=%b,out=%b"", + sel,in0,in1,a); + error = 1; + end + #1; + in0 = 1; + in1 = 1; + sel = 1\'bx; + #1; + if(a !== 1) + begin + $display(""FAILED - (9) Mux error sel=X, in0=1,in1=1 yet out != 1""); + $display(""sel=%b,in0=%b,in1=%b,out=%b"", + sel,in0,in1,a); + error = 1; + end + if(error === 0) + $display(""PASSED""); + end + +endmodule +" +"module top; + reg a, enb, q; + reg pass; + + always_latch if (enb !== 1\'b1) q <= a !== 1\'bx; + + + initial begin + pass = 1\'b1; + #1; + if (q !== 1\'b0) begin + $display(""Expected q = 1\'b0 with the default 1\'bx input, got %b"", q); + pass = 1\'b0; + end + + a = 1\'b0; + #1; + if (q !== 1\'b1) begin + $display(""Expected q = 1\'b1 with an explicit 1\'b0 input, got %b"", q); + pass = 1\'b0; + end + + a = 1\'b1; + #1; + if (q !== 1\'b1) begin + $display(""Expected q = 1\'b1 with an explicit 1\'b1 input, got %b"", q); + pass = 1\'b0; + end + + a = 1\'bz; + #1; + if (q !== 1\'b1) begin + $display(""Expected q = 1\'b1 with an explicit 1\'bz input, got %b"", q); + pass = 1\'b0; + end + + a = 1\'bx; + #1; + if (q !== 1\'b0) begin + $display(""Expected q = 1\'b0 with an explicit 1\'bx input, got %b"", q); + pass = 1\'b0; + end + + enb = 1\'b1; + a = 1\'bz; + #1; + if (q !== 1\'b0) begin + $display(""Expected q = 1\'b0 with an enb = 1\'b1, got %b"", q); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end + +endmodule +" +"module testbench; + // This should give us a vector of [-1:0] (A == 0). + parameter A = $clog2(1); + wire [A-1:0] x; + wire [A-1:0] y = x; + + // Check to see that we got a two bit wide wire. + initial if ($bits(x) == 2) $display(""PASSED""); + else $display(""FAILED""); +endmodule +" +"// Catch problem where we assign to function params +module top(); + integer r; + + function integer fact; + input n; + integer n; + + for (fact = 1; n > 0; n = n - 1) begin + fact = fact * n; + end + endfunction // for + + initial begin + r = fact(5); + $display(""fact(5) = %d"", r); + if (r == 120) + $display(""PASSED""); + else + $display(""FAILED""); + end +endmodule // top +" +"// Copyright 2008, Martin Whitaker. +// This file may be freely copied for any purpose. + +module localparam_sign(); + +localparam\tP1\t= 16; +localparam\tP2\t= P1 * 2; + +submodule #(P2) submodule(); + +endmodule + +module submodule(); + +parameter\tP3\t= 1; + +initial begin + $display(""P3 = %0d"", P3); +end + +endmodule +" +"`begin_keywords ""1364-2005"" +module top(arg); + input [31:0] arg; + + wire [31:0] out_0; + wire [31:0] out_1; + reg [31:0] var; + + add dut_0 (var, var, out_0); + add dut_1 (arg, var, out_1); + +endmodule + +module add(in0, in1, out); + input [31:0] in0; + input [31:0] in1; + output reg [31:0] out; + + // This works if you explicitly specify the sensitivity list. + always @* out = in0 + in1; +endmodule +`end_keywords +" +"/* + * Copyright (c) 2000 Chris Lattner + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This isn\'t computationally complicated, but can trip up a vvm + * code generation error. + */ +module test; + reg [15:0] is[1:0]; + reg [4:0] i; + + initial begin + i = 0; + is[0] = i; // Notice the different widths. + if (is[0] !== 16\'d0) begin +\t $display(""FAILED -- is[0] --> %b"", is[0]); +\t $finish; + end + $display(""PASSED""); + end +endmodule +" +"module top; + reg q, en, d; + + always_latch begin + if (en) #0 q <= d; + end + + initial $display(""Expected compile failure!""); + +endmodule +" +"// Copyright 2007, Martin Whitaker. +// This code may be freely copied for any purpose. + +module duplicate_names(); + +localparam up = 1; + +generate + if (up) + begin:block1 + wire [2:0] count1; + count_up counter(count1); + end +endgenerate + +initial begin:block1 + reg [2:0] count2; + + #1 count2 = 4; + #1 count2 = 5; + #1 count2 = 6; + #1 count2 = 7; +end + +endmodule + +module count_up(output reg [2:0] count); + +initial begin + #1 count = 0; + #1 count = 1; + #1 count = 2; + #1 count = 3; +end + +endmodule +" +"module top; + // This should fail because XX4 is not given a constant. + enum {VAL4, XX4 = $time} en4; + + initial $display(""FAILED""); +endmodule +" +"package test_pkg; + + class uvm_phase; + function void print(string str); + $display(str); + endfunction + endclass : uvm_phase + + class uvm_component; + virtual function void build_phase(uvm_phase phase); + phase.print(""building""); + endfunction : build_phase + + virtual task run_phase(uvm_phase phase); + phase.print(""running""); + endtask : run_phase + + virtual task run_all(); + uvm_phase p0; + + p0 = new(); + + this.build_phase(p0); + this.run_phase(p0); + endtask : run_all + + endclass : uvm_component + +endpackage : test_pkg + +module m; + import test_pkg::*; + uvm_component u0; + + initial begin : test + u0 = new(); + u0.run_all(); + end : test + +endmodule : m +" +"/* + * This tests the synthesis of a very sparse case statement. The + * combinational case statement below specifies only two of 256 + * possible selections, with all the remaining left to the default. + * What\'s more, all the inputs to the MUX are constant, giving + * even further opportunity for optimization. + */ +module main; + + reg [7:0] val; + reg [7:0] out; + + (* ivl_combinational *) + always @ (val) begin + case (val) + 8\'h2a: out = 8\'h40 ; + 8\'h1f: out = 8\'h20 ; + default: out = 8\'h04 ; + endcase + end + + integer idx; + (* ivl_synthesis_off *) initial begin + for (idx = 0 ; idx < 256 ; idx = idx + 1) begin +\t val <= idx; +\t #1 ; +\t if (val == 8\'h2a) begin +\t if (out !== 8\'h40) begin +\t $display(""FAILED -- val=%h, out=%h (%b)"", val, out, out); +\t $finish; +\t end +\t end else if (val == 8\'h1f) begin +\t if (out !== 8\'h20) begin +\t $display(""FAILED -- val=%h, out=%h (%b)"", val, out, out); +\t $finish; +\t end +\t end else if (out !== 8\'h04) begin +\t $display(""FAILED -- val=%h, out=%h (%b)"", val, out, out); +\t $finish; +\t end + end + $display(""PASSED""); + end + +endmodule // main +" +"/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This sample tests that the supply0 and supply1 nets take on + * the proper initial value. This adds to the supply1 test some + * constant drivers that could tickle constant propagation bugs. + */ + +module test; + + supply0 gnd; + supply1 vdd; + + // These should drop away as meaningless. + assign gnd = 1; + assign vdd = 0; + + initial begin #1 + if (gnd !== 0) begin +\t $display(""FAILED -- gnd == %b"", gnd); +\t $finish; + end + + if (vdd !== 1) begin +\t $display(""FAILED -- vdd == %b"", vdd); +\t $finish; + end + + $display(""PASSED""); + end +endmodule +" +"module ge2(output wire out, input wire [1:0] A, input wire [1:0] B); + + assign out = A >= B; + +endmodule // ge2 +" +"module check (input signed [22:0] a, b, +\t\t input signed [45:0] c); + wire signed [45:0] int_AB; + + assign int_AB = a * b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB !== c) begin + $display(""ERROR: mismatch for inputs %d * %d"", a, b); +\t $display(""VHDL = %d; Verilog = %d"", c, int_AB); + $finish; + end +end + +endmodule + +module stimulus (output reg signed [22:0] A, B); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; B= 0; + for (i=0; i foo; + rl = 0.0; + rl <= 1.0; + ar = new [2]; + for (int idx = start; idx < stop; idx += step) $display(""For: %0d"", idx); + for (int idx = 0; done; idx = done + 1) $display(""Should never run!""); + for (int idx = 0; idx; done = done + 1) $display(""Should never run!""); + for (int idx = 0; idx; {done, idx} = done + 1) $display(""Should never run!""); + for (int idx = 0; idx; idx <<= 1) $display(""Should never run!""); + for (int idx = 0; idx; idx = idx << 1) $display(""Should never run!""); + $display(""array size: %0d"", ar.size()); + ar.delete(); + $display(""array size: %0d"", ar.size()); + a_task; + assign a = 1\'b0; + deassign a; + do $display(""do/while""); + while (a); + force a = 1\'b1; + release a; + while(a) begin + $display(""while""); + a = 1\'b0; + end + repeat(2) $display(""repeat""); + disable out_name; + forever begin + $display(""forever""); + disable blk_name; // This one should not generate a warning + end + end + + initial #1 $display(""Expect compile warnings!\ +PASSED""); + + initial begin: out_name + #2 $display(""FAILED""); + end + +endmodule +" +"/* testcase */ + +/** +generate this input file: +$ cat t.in +1073741824 +2147483648 +4294967296 +$ + +expected output in t.out: +$ cat t.out +# x = 1073741824 +# x = 2147483648 +# x = 4294967296 + 0 +1073741824 +2147483648 +4294967296 + +Icarus Verilog output in t.out: +$ cat t.out +# x = 1073741824 +# x = 2147483648 +# x = 4294967296 + 0 +1073741824 +6442450944 + 0 +*/ + +module testbench; +\tparameter WIDTH = 33; +\treg clk; +\treg [WIDTH-1:0] in; +\treg [WIDTH-1:0] test_val1; +\treg [WIDTH-1:0] test_val2; +\treg [WIDTH-1:0] test_val3; +\tinteger infile, outfile, count; + +\tinitial begin +\t\tclk = 0; +\t\tin = 0; +\t\ttest_val1 = 1 << 30; +\t\ttest_val2 = 1 << 31; +\t\ttest_val3 = 1 << 32; +\t\tinfile = $fopen(""ivltests/pr2029336.in"", ""r""); +\t\toutfile = $fopen(""work/pr2029336.out"", ""w""); +\t\t$fwrite(outfile, ""# x = %d\ +"", test_val1); // $fwrite() seems to be ok... +\t\t$fwrite(outfile, ""# x = %d\ +"", test_val2); // $fwrite() seems to be ok... +\t\t$fwrite(outfile, ""# x = %d\ +"", test_val3); // $fwrite() seems to be ok... +\tend + +\talways @(negedge clk) begin +\t\t$fwrite(outfile, ""%d\ +"", in); +\t\tcount = $fscanf(infile, ""%d\ +"", in); // $fscanf() seems buggy... +\t\tif (count != 1) begin +\t\t\t$fclose(infile); +\t\t\t$fclose(outfile); +\t\t\t$finish; +\t\tend +\tend + +\talways #1 +\t\tclk = ~clk; + +endmodule +" +"module test(); + +parameter y = 1; +parameter a = 0; + +parameter x = y ? a : b; + +endmodule +" +"module main; + + reg [7:0] period; + + reg\t drive; + wire trace; + + // This is the main point of the test. Non-constant delay expressions + // should work here. + assign #(period) trace = drive; + + initial begin + period = 8; + // Initially, set up a period=8 and get the trace to start + // following the drive. + #1 drive <= 1; + #9 if (trace !== drive) begin +\t $display(""FAILED -- time=%0t, drive=%b, trace=%b"", +\t\t $time, drive, trace); +\t $finish; + end + + // The drive should NOT change the trace before the period. + drive <= 0; + + #7 if (trace !== 1\'b1) begin +\t $display(""FAILED -- time=%0t, drive=%b, trace=%b"", +\t\t $time, drive, trace); +\t $finish; + end + #2 if (trace !== drive) begin +\t $display(""FAILED -- time=%0t, drive=%b, trace=%b"", +\t\t $time, drive, trace); +\t $finish; + end + + // Change the period. + period = 6; + + // Now check that the new delay is taken. + #1 drive <= 1; + + #5 if (trace !== 1\'b0) begin +\t $display(""FAILED -- time=%0t, drive=%b, trace=%b"", +\t\t $time, drive, trace); +\t $finish; + end + + #2 if (trace !== drive) begin +\t $display(""FAILED -- time=%0t, drive=%b, trace=%b"", +\t\t $time, drive, trace); +\t $finish; + end + + $display(""PASSED""); + $finish; + end + +endmodule // main +" +" +/* + * Generate a combinational adder of any width. The width parameter can + * be any integer value >0. The A and B inputs have WID bits, and the Q + * output has WID+1 bits to include the overflow. + */ +module addN + #(parameter WID = 4) + (input wire [WID-1:0] A, + input wire [WID-1:0] B, + output wire [WID:0] Q + /* */); + + wire [WID-1:0]\tCout; + + /* The least significant slice has no Cin */ + add1 U0 (.A(A[0]), .B(B[0]), .Cin(1\'b0), .Q(Q[0]), .Cout(Cout[0])); + + /* Generate all the remaining slices */ + genvar i; + for (i = 1 ; i < WID ; i = i+1) begin : U + add1 Un (.A(A[i]), .B(B[i]), .Cin(Cout[i-1]), .Q(Q[i]), .Cout(Cout[i])); + end + + assign Q[WID] = Cout[WID-1]; + +endmodule // add + +/* + * This is a single-bit combinational adder used by the addH module + * above. + */ +module add1(input A, input B, input Cin, output Q, output Cout); + + assign Q = A ^ B ^ Cin; + assign Cout = A&B | A&Cin | B&Cin; + +endmodule // hadd + +`ifdef TEST_BENCH +module main; + + parameter WID = 4; + reg [WID-1:0] A, B; + wire [WID:0] Q; + + addN #(.WID(WID)) usum (.A(A), .B(B), .Q(Q)); + + int\t\t adx; + int\t\t bdx; + initial begin + for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin +\t for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin +\t A <= adx[WID-1:0]; +\t B <= bdx[WID-1:0]; +\t #1 if (Q !== (adx+bdx)) begin +\t $display(""FAILED -- A=%b, B=%b, Q=%b"", A, B, Q); +\t $finish; +\t end +\t end + end + $display(""PASSED""); + end + +endmodule // main +`endif +" +" +module cmpN + #(parameter WID = 4) + (input wire [WID-1:0] A, + input wire [WID-1:0] B, + output reg QE, QN, QGT, QGE + /* */); + + always @(A, B) + if (A > B) + QGT = 1; + else + QGT = 0; + + always @(A, B) + if (A >= B) + QGE = 1; + else + QGE = 0; + + always @(A, B) + if (A == B) + QE = 1; + else + QE = 0; + + always @(A, B) + if (A != B) + QN = 1; + else + QN = 0; + + +/* + always @(A, B) + if (A > B) begin +\t QE = 0; +\t QN = 1; +\t QGT = 1; +\t QGE = 1; + end else if (A == B) begin +\t QE = 1; +\t QN = 0; +\t QGT = 0; +\t QGE = 1; + end else begin +\t QE = 0; +\t QN = 1; +\t QGT = 0; +\t QGE = 0; + end +*/ +endmodule // add +" +"// Check the various variable array selects (large to small). +module top; + reg passed; + + wire [1:0] a [4:1]; + wire [0:0] s0 = 0; + wire [1:0] s1 = 0; + wire [2:0] s2 = 0; + reg [1:0] ar [4:1]; + + wire [1:0] c [0:-3]; + wire [0:0] s3 = 0; + wire [1:0] s4 = 0; + reg [1:0] cr [0:-3]; + + wire [1:0] res_a0 = a[s0]; + wire [1:0] res_a1 = a[s1]; + wire [1:0] res_a2 = a[s2]; + + wire [1:0] res_c3 = c[s3]; + wire [1:0] res_c4 = c[s4]; + + reg res_a [4:1]; + reg res_c [0:-3]; + + assign a[1] = 2\'d0; + assign a[2] = 2\'b1; + assign a[3] = 2\'d2; + assign a[4] = 2\'d3; + + assign c[-3] = 2\'d0; + assign c[-2] = 2\'b1; + assign c[-1] = 2\'d2; + assign c[0] = 2\'d3; + + initial begin + #1; + passed = 1\'b1; + + ar[1] = 2\'d0; + ar[2] = 2\'b1; + ar[3] = 2\'d2; + ar[4] = 2\'d3; + + cr[-3] = 2\'d0; + cr[-2] = 2\'b1; + cr[-1] = 2\'d2; + cr[0] = 2\'d3; + + // Check procedural R-value variable bit selects of a net. + + $display(""a[s0]: %b"", a[s0]); + if (a[s0] !== 2\'bxx) begin + $display(""Failed a[s0], expected 2\'bxx, got %b"", a[s0]); + passed = 1\'b0; + end + + $display(""a[s1]: %b"", a[s1]); + if (a[s1] !== 2\'bxx) begin + $display(""Failed a[s1], expected 2\'bxx, got %b"", a[s1]); + passed = 1\'b0; + end + + $display(""a[s2]: %b"", a[s2]); + if (a[s2] !== 2\'bxx) begin + $display(""Failed a[s2], expected 2\'bxx, got %b"", a[s2]); + passed = 1\'b0; + end + + $display(""c[s3]: %b"", c[s3]); + if (c[s3] !== 2\'b11) begin + $display(""Failed c[s3], expected 2\'b11, got %b"", c[s3]); + passed = 1\'b0; + end + + $display(""c[s4]: %b"", c[s4]); + if (c[s4] !== 2\'b11) begin + $display(""Failed c[s4], expected 2\'b11, got %b"", c[s4]); + passed = 1\'b0; + end + + // Check procedural R-value variable bit selects of a reg. + + $display(""ar[s0]: %b"", ar[s0]); + if (ar[s0] !== 2\'bxx) begin + $display(""Failed ar[s0], expected 2\'bxx, got %b"", ar[s0]); + passed = 1\'b0; + end + + $display(""ar[s1]: %b"", ar[s1]); + if (ar[s1] !== 2\'bxx) begin + $display(""Failed ar[s1], expected 2\'bxx, got %b"", ar[s1]); + passed = 1\'b0; + end + + $display(""ar[s2]: %b"", ar[s2]); + if (ar[s2] !== 2\'bxx) begin + $display(""Failed ar[s2], expected 2\'bxx, got %b"", ar[s2]); + passed = 1\'b0; + end + + $display(""cr[s3]: %b"", cr[s3]); + if (cr[s3] !== 2\'b11) begin + $display(""Failed cr[s3], expected 2\'b11, got %b"", cr[s3]); + passed = 1\'b0; + end + + $display(""cr[s4]: %b"", cr[s4]); + if (cr[s4] !== 2\'b11) begin + $display(""Failed cr[s4], expected 2\'b11, got %b"", cr[s4]); + passed = 1\'b0; + end + + // Check continuous assignment R-value variable bit selects. + + if (res_a0 !== 2\'bxx) begin + $display(""Failed res_a0, expected 2\'bxx, got %b"", res_a0); + passed = 1\'b0; + end + + if (res_a1 !== 2\'bxx) begin + $display(""Failed res_a1, expected 2\'bxx, got %b"", res_a1); + passed = 1\'b0; + end + + if (res_a2 !== 2\'bxx) begin + $display(""Failed res_a2, expected 2\'bxx, got %b"", res_a2); + passed = 1\'b0; + end + + if (res_c3 !== 2\'b11) begin + $display(""Failed res_c3, expected 2\'b11, got %b"", res_c3); + passed = 1\'b0; + end + + if (res_c4 !== 2\'b11) begin + $display(""Failed res_c4, expected 2\'b11, got %b"", res_c4); + passed = 1\'b0; + end + + // Check procedural L-value variable bit selects. + + res_a[1] = 1\'bx; + res_a[2] = 1\'bx; + res_a[3] = 1\'bx; + res_a[4] = 1\'bx; + res_a[s0] = 1\'b0; + if (res_a[1] !== 1\'bx) begin + $display(""Failed res_a[s0], expected 1\'bx for [1], got %b"", res_a[1]); + passed = 1\'b0; + end + if (res_a[2] !== 1\'bx) begin + $display(""Failed res_a[s0], expected 1\'bx for [2], got %b"", res_a[2]); + passed = 1\'b0; + end + if (res_a[3] !== 1\'bx) begin + $display(""Failed res_a[s0], expected 1\'bx for [3], got %b"", res_a[3]); + passed = 1\'b0; + end + if (res_a[4] !== 1\'bx) begin + $display(""Failed res_a[s0], expected 1\'bx for [4], got %b"", res_a[4]); + passed = 1\'b0; + end + + res_a[1] = 1\'bx; + res_a[2] = 1\'bx; + res_a[3] = 1\'bx; + res_a[4] = 1\'bx; + res_a[s1] = 1\'b0; + if (res_a[1] !== 1\'bx) begin + $display(""Failed res_a[s1], expected 1\'bx for [1], got %b"", res_a[1]); + passed = 1\'b0; + end + if (res_a[2] !== 1\'bx) begin + $display(""Failed res_a[s1], expected 1\'bx for [2], got %b"", res_a[2]); + passed = 1\'b0; + end + if (res_a[3] !== 1\'bx) begin + $display(""Failed res_a[s1], expected 1\'bx for [3], got %b"", res_a[3]); + passed = 1\'b0; + end + if (res_a[4] !== 1\'bx) begin + $display(""Failed res_a[s1], expected 1\'bx for [4], got %b"", res_a[4]); + passed = 1\'b0; + end + + res_a[1] = 1\'bx; + res_a[2] = 1\'bx; + res_a[3] = 1\'bx; + res_a[4] = 1\'bx; + res_a[s2] = 1\'b0; + if (res_a[1] !== 1\'bx) begin + $display(""Failed res_a[s2], expected 1\'bx for [1], got %b"", res_a[1]); + passed = 1\'b0; + end + if (res_a[2] !== 1\'bx) begin + $display(""Failed res_a[s2], expected 1\'bx for [2], got %b"", res_a[2]); + passed = 1\'b0; + end + if (res_a[3] !== 1\'bx) begin + $display(""Failed res_a[s2], expected 1\'bx for [3], got %b"", res_a[3]); + passed = 1\'b0; + end + if (res_a[4] !== 1\'bx) begin + $display(""Failed res_a[s2], expected 1\'bx for [4], got %b"", res_a[4]); + passed = 1\'b0; + end + + res_c[-3] = 1\'bx; + res_c[-2] = 1\'bx; + res_c[-1] = 1\'bx; + res_c[0] = 1\'bx; + res_c[s3] = 1\'b0; + if (res_c[-3] !== 1\'bx) begin + $display(""Failed res_c[s3], expected 1\'bx for [-3], got %b"", res_c[-3]); + passed = 1\'b0; + end + if (res_c[-2] !== 1\'bx) begin + $display(""Failed res_c[s3], expected 1\'bx for [-2], got %b"", res_c[-2]); + passed = 1\'b0; + end + if (res_c[-1] !== 1\'bx) begin + $display(""Failed res_c[s3], expected 1\'bx for [-1], got %b"", res_c[-1]); + passed = 1\'b0; + end + if (res_c[0] !== 1\'b0) begin + $display(""Failed res_c[s3], expected 1\'b0 for [0], got %b"", res_c[0]); + passed = 1\'b0; + end + + res_c[-3] = 1\'bx; + res_c[-2] = 1\'bx; + res_c[-1] = 1\'bx; + res_c[0] = 1\'bx; + res_c[s4] = 1\'b0; + if (res_c[-3] !== 1\'bx) begin + $display(""Failed res_c[s4], expected 1\'bx for [-3], got %b"", res_c[-3]); + passed = 1\'b0; + end + if (res_c[-2] !== 1\'bx) begin + $display(""Failed res_c[s4], expected 1\'bx for [-2], got %b"", res_c[-2]); + passed = 1\'b0; + end + if (res_c[-1] !== 1\'bx) begin + $display(""Failed res_c[s4], expected 1\'bx for [-1], got %b"", res_c[-1]); + passed = 1\'b0; + end + if (res_c[0] !== 1\'b0) begin + $display(""Failed res_c[s4], expected 1\'b0 for [0], got %b"", res_c[0]); + passed = 1\'b0; + end + + if (passed) $display(""Compare tests passed""); + end +endmodule +" +"`define OPT1_DISPLAY $display(""opt1""); +`define OPT2_DISPLAY $display(""opt2""); + +`define INDIRECT_OPT(OPTN) ```OPTN``_DISPLAY + + +module t; + + initial begin + `INDIRECT_OPT(OPT1) + `INDIRECT_OPT(OPT2) + end +endmodule +" +"module top; + reg passed; + // These should be OK + enum {zdef1_[0:1]} zdef1; + enum {zdef2_[1:0]} zdef2; + enum {zdefb_[0:0]} zdef3; + enum {zvalb_[0:0] = 1} zval1; + + initial begin + passed = 1\'b1; + + if (zdef1_0 !== 0) begin + $display(""FAILED: expected zdef1_0 to be 0, got %0d"", zdef1_0); + passed = 1\'b0; + end + if (zdef1_1 !== 1) begin + $display(""FAILED: expected zdef1_1 to be 1, got %0d"", zdef1_1); + passed = 1\'b0; + end + + if (zdef2_1 !== 0) begin + $display(""FAILED: expected zdef2_1 to be 0, got %0d"", zdef2_1); + passed = 1\'b0; + end + if (zdef2_0 !== 1) begin + $display(""FAILED: expected zdef2_0 to be 1, got %0d"", zdef2_0); + passed = 1\'b0; + end + + if (zdefb_0 !== 0) begin + $display(""FAILED: expected zdefb_0 to be 0, got %0d"", zdefb_0); + passed = 1\'b0; + end + + if (zvalb_0 !== 1) begin + $display(""FAILED: expected zvalb_0 to be 1, got %0d"", zvalb_0); + passed = 1\'b0; + end + + if (passed) $display(""PASSED""); + end +endmodule +" +"// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for NOW() system function. + +module now_test; +logic gen_report; +now_entity dut(gen_report); + +initial begin + gen_report = 0; + #5; + gen_report = 1; + #5; + gen_report = 0; + #5; + gen_report = 1; + #5; + gen_report = 0; + #5; + gen_report = 1; +end +endmodule +" +"module test(); +reg [13:0] a; +reg b; +reg c; + +always @(a or b) +begin + + case ({1\'b0,~b,a[3:0]}) + 6\'b00_0000 : begin + c = 1\'b1; + end + default : begin + c = 1\'b0; + end + endcase +end + +initial begin + #1 /* Wait for the always block above to get settled. */; + a = 0; + b = 0; + #1 if (c !== 0) begin + $display(""FAILED - a=%b, b=%b, c=%b"", a, b, c); + $finish; + end + + b = 1; + #1 if (c !== 1) begin + $display(""FAILED - a=%b, b=%b, c=%b"", a, b, c); + $finish; + end + + $display(""PASSED""); +end // initial begin + +endmodule +" +"module main; + + wire out; + reg [1:0] A, B; + + ge2 dut(.out(out), .A(A), .B(B)); + + initial begin + A = 0; + B = 0; + #1 $display(""%b >= %b: %b"", A, B, out); + + B = 1; + #1 $display(""%b >= %b: %b"", A, B, out); + + B = 2; + #1 $display(""%b >= %b: %b"", A, B, out); + + B = 3; + #1 $display(""%b >= %b: %b"", A, B, out); + + A = 1; + B = 0; + #1 $display(""%b >= %b: %b"", A, B, out); + + B = 1; + #1 $display(""%b >= %b: %b"", A, B, out); + + B = 2; + #1 $display(""%b >= %b: %b"", A, B, out); + + B = 3; + #1 $display(""%b >= %b: %b"", A, B, out); + + A = 2; + B = 0; + #1 $display(""%b >= %b: %b"", A, B, out); + + B = 1; + #1 $display(""%b >= %b: %b"", A, B, out); + + B = 2; + #1 $display(""%b >= %b: %b"", A, B, out); + + B = 3; + #1 $display(""%b >= %b: %b"", A, B, out); + + A = 3; + B = 0; + #1 $display(""%b >= %b: %b"", A, B, out); + + B = 1; + #1 $display(""%b >= %b: %b"", A, B, out); + + B = 2; + #1 $display(""%b >= %b: %b"", A, B, out); + + B = 3; + #1 $display(""%b >= %b: %b"", A, B, out); + + end // initial begin +endmodule // main +" +"`timescale 1ns/1ns + +module lfsr_test(); + parameter SIZE = 4; + reg clk, reset, ena; + wire [SIZE-1:0] out; + + initial + begin //{ + clk = 0; + reset = 0; + ena = 1\'bz; + #15 reset = 0; + #20 reset = 1; + end //} + + initial + begin //{ +\t //$dumpfile(""lfsr_test.vcd""); // Change filename as appropriate. +\t //$dumpvars( 0, lfsr_test); +\t $monitor(""out=%b"", out); + end //} + + always clk = #10 ~clk; + + lfsr_counter LF( clk, reset, out ); + + initial #1000 $finish(0); +endmodule // gray_code + + + + +module lfsr_counter( clk, reset, out ); + `define W 4 + parameter WIDTH = `W; + parameter TAP = `W\'b1001; + integer N; + + output [WIDTH-1:0] out; + input clk, reset; + + wire [WIDTH-1:0] gc; + reg [WIDTH-1:0] lfsr, next_lfsr; + reg\t\t fb_lsb, fb; + + always @(posedge clk or negedge reset ) + begin //{ + if( reset == 1\'b0 ) +\tlfsr[WIDTH-1:0] <= `W\'b0; + else +\tlfsr[WIDTH-1:0] <= next_lfsr[WIDTH-1:0]; + end //} + + always @( lfsr ) + begin //{ + fb_lsb = ~| lfsr[WIDTH-2:0]; + fb = lfsr[WIDTH-1] ^ fb_lsb; + for( N=WIDTH; N>=0; N=N-1 ) +\tif( TAP[N] == 1 ) +\t next_lfsr[N] = lfsr[N-1] ^ fb; +\telse +\t next_lfsr[N] = lfsr[N-1]; + next_lfsr[0] = fb; + end //} + assign out[WIDTH-1:0] = {1\'b0, lfsr[WIDTH-1:1]}; //(1) + //assign out[WIDTH-1:0] = lfsr[WIDTH-1:0]; //(2) + //assign gc[WIDTH-1:0] = out[WIDTH-1:0] ^ {1\'b0, out[WIDTH-1:1]}; +//(3) + +endmodule // gray_counter +" +"// Copyright 2007, Martin Whitaker. +// This code may be freely copied for any purpose. +module generate_memory(); + +generate + genvar\tb; + + for (b = 0; b < 4; b = b + 1) begin: Byte + reg [7:0] Data[0:3]; + end +endgenerate + +integer\t\ti; + +initial begin + for (i = 0; i < 4; i = i + 1) begin + Byte[0].Data[i] = i*16 + 1; + Byte[1].Data[i] = i*16 + 2; + Byte[2].Data[i] = i*16 + 3; + Byte[3].Data[i] = i*16 + 4; + end + for (i = 0; i < 4; i = i + 1) begin + $display(""%h"", Byte[0].Data[i]); + $display(""%h"", Byte[1].Data[i]); + $display(""%h"", Byte[2].Data[i]); + $display(""%h"", Byte[3].Data[i]); + end +end + +endmodule +" +"module top; + reg q1, q2, q3, q4, q5, q6, q7, d; + reg clk; + reg [5:4] rst; + integer i; + + // The compiler should warn that clk is missing an edge keyword. + always_ff @(clk) begin + q1 <= d; + end + + // The compiler should warn that rst is missing an edge keyword. + always_ff @(posedge clk or rst[4]) begin + if (rst[4]) + q2 <= 1\'b0; + else + q2 <= d; + end + + // The compiler should warn that rst is missing an edge keyword. + always_ff @(posedge clk or rst[i]) begin + if (rst[i]) + q3 <= 1\'b0; + else + q3 <= d; + end + + // The compiler should warn that rst is missing an edge keyword. + always_ff @(posedge clk or !rst) begin + if (!rst) + q4 <= 1\'b0; + else + q4 <= d; + end + + // The compiler should warn that rst is missing an edge keyword. + always_ff @(posedge clk or ~rst[4]) begin + if (~rst[4]) + q5 <= 1\'b0; + else + q5 <= d; + end + + // The compiler should warn that rst is missing an edge keyword. + always_ff @(posedge clk or &rst) begin + if (&rst) + q6 <= 1\'b0; + else + q6 <= d; + end + + // The compiler should warn that rst is not a single bit. + always_ff @(posedge clk or posedge rst) begin + if (rst) + q7 <= 1\'b0; + else + q7 <= d; + end + + initial begin + $display(""Expect compile warnings!\ +PASSED""); + end + +endmodule +" +"/* + * 23.2.2.3 Rules for determining port kind, data type, and direction says + * + * For output ports, the default port kind depends on how the data type is + * specified: + * - If the data type is omitted or declared with the implicit_data_type + * syntax, the port kind shall default to a net of default net type. + * - If the data type is declared with the explicit data_type syntax, the port + * kind shall default to variable. + */ + +typedef enum { A, B } E; + +module main; + E in; + wire E out; + + M foo (in, out); + + initial begin + in = A; + #1 if (out !== A) begin +\t $display(""FAIL: in=%0d, out=%0d"", in, out); +\t $finish; + end + + in = B; + #1 if (out !== B) begin +\t $display(""FAIL: in=%0d, out=%0d"", in, out); +\t $finish; + end + + $display(""PASSED""); + $finish; + end +endmodule // main + +module M (input E ei, +\t output E eo); + + always_comb eo = ei; + +endmodule // M +" +"module test(); + +task t(integer a, b); + $display(a,,b); +endtask + +initial t(0, 1); + +endmodule +" +"module top; + reg pass; + reg signed [63:0] error; + + initial begin + pass = 1\'b1; + error = 0; + error = error + 64\'h40000000; + error = error + 64\'h80000000; + if (error !== 64\'hc0000000) begin + $display(""FAILED immediate add, got %h"", error); + pass = 1\'b0; + end + + error = error + -64\'sh40000000; + error = error + -64\'sh80000000; + if (error !== 64\'h00000000) begin + $display(""FAILED immediate add, got %h"", error); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module testbench(); + reg [3:0] a, b; + + initial begin + a = 1; + b = 2; + #1; + a = a + b; + b = a + b; + if (a !== 3) + begin + $display(""FAILED -- a !== 3""); + $finish; + end + if (b !== 5) + begin + $display(""FAILED -- b !== 5""); + $finish; + end + #2; + $display(""PASSED""); + end // initial begin + + initial begin + #2; + if (a !== 3) + begin + $display(""FAILED -- a (signal) !== 3""); + $finish; + end + if (b !== 5) + begin + $display(""FAILED -- b (signal) !== 5""); + $finish; + end + end + +endmodule // testbench +" +" +module main; + + reg [1:0] D0, D1; + reg\t sel; + wire [1:0] Q; + + test_mux DUT(.\\S[1] (1\'b0), .\\S[0] (sel), +\t\t.\\D0[1] (D0[1]), .\\D0[0] (D0[0]), +\t\t.\\D1[1] (D1[1]), .\\D1[0] (D1[0]), +\t\t.\\Q[1] (Q[1]), .\\Q[0] (Q[0])); + + initial begin + D0 = \'b01; + D1 = \'b10; + sel = 0; + #1 ; + if (Q !== D0) begin +\t $display(""FAILED -- D0=%b, D1=%b, S=%b, Q=%b"", D0, D1, sel, Q); +\t $finish; + end + + sel = 1; + #1 ; + if (Q !== D1) begin +\t $display(""FAILED -- D0=%b, D1=%b, S=%b, Q=%b"", D0, D1, sel, Q); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +" +module main; + + localparam AMAX = 7; + localparam SHIFT = 4; + int foo [AMAX:0]; + int unsigned foo_u [AMAX:0]; + int idx; + + initial begin + for (idx = 0 ; idx <= AMAX ; idx = idx+1) begin +\t foo[idx] = idx - SHIFT; +\t foo_u[idx] = idx; + end + + for (idx = 0 ; idx <= AMAX ; idx = idx+1) begin +\t if (idx < SHIFT && foo[idx] > 0) begin +\t $display(""FAIL -- foo[%0d] = %0d (not signed?)"", idx, foo[idx]); +\t $finish; +\t end +\t if (foo[idx] != (idx-SHIFT)) begin +\t $display(""FAIL -- foo[%0d] = %0d"", idx, foo[idx]); +\t $finish; +\t end +\t if (foo_u[idx] != idx) begin +\t $display(""FAIL -- foo_u[%0d] = %0d"", idx, foo[idx]); +\t $finish; +\t end + end + + $display(""PASSED""); + $finish; + end // initial begin + +endmodule // main +" +"module bar; + parameter P = 1; +endmodule + +module baz; + parameter P = 1; + parameter Q = 2; +endmodule + +module foo; + bar #345 bar1(); + bar #(456) bar2(); + baz baz1(); + baz #(888,999) baz2(); + + initial + $display(""PASSED""); +endmodule +" +"module test; + +event i1, i2, i3; + +integer countA, countB; + +always @(i1 or i2) begin + $display(""%0t: A"", $time); + countA = countA + 1; +end + +always @(i2 or i3) begin + $display(""%0t: B"", $time); + countB = countB + 1; +end + +initial begin + countA = 0; + countB = 0; + #1 ->i1; + #1 ->i2; + #1 ->i3; + #1; + if (countA === 2 && countB === 2) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module test; + reg blah [63:0]; + initial blah = 0; // This should generate an error message. +endmodule +" +"module main; + + wire [15:0] out; + reg [16:0] in; + reg [15:0] mask; + + mask dut (.\\output (out), .\\input (in[15:0]), .mask(mask)); + + wire [15:0] out_ref = in[15:0] & mask; + initial begin + for (in = 0 ; in[16] == 0 ; in = in+1) begin +\t mask = $random; +\t #1 if (out !== out_ref) begin +\t $display(""FAILED: in=%b, out=%b, mask=%b, out_ref=%b"", in, out, mask, out_ref); +\t $finish; +\t end + end + + $display(""PASSED""); + end + +endmodule // main +" +"module bug(); + localparam signed [31:0] n1 = 32\'h8000_0000; + localparam signed [31:0] d1 = 32\'hFFFF_FFFF; + localparam signed [31:0] q1 = n1 / d1; + localparam signed [31:0] m1 = n1 % d1; + + localparam signed [63:0] n2 = 64\'h8000_0000_0000_0000; + localparam signed [63:0] d2 = 64\'hFFFF_FFFF_FFFF_FFFF; + localparam signed [63:0] q2 = n2 / d2; + localparam signed [63:0] m2 = n2 % d2; + + initial begin + $display(""32 bit quotient = 0x%08h;"", q1); + $display(""32 bit modulus = 0x%08h;"", m1); + $display(""64 bit quotient = 0x%016h;"", q2); + $display(""64 bit modulus = 0x%016h;"", m2); + if ((q1 === 32\'h8000_0000) && (q2 === 64\'h8000_0000_0000_0000) + && (m1 === 32\'h0000_0000) && (m2 === 64\'h0000_0000_0000_0000)) + $display(""PASSED""); + else + $display(""FAILED""); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate case/endcase - no default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 or val2) + case (val1 & val2 ) + 3\'b000: result = 0; + 3\'b001: result = 1 ; + 3\'b010: result = 2; + endcase + +initial + begin + error = 0; + + val1 = 3\'b0; + val2 = 3\'b0; + #1 if(result !==0) + begin + $display(""FAILED case 3.8A - case (expr) lab1: ""); + error = 1; + end + + val1 = 3\'b001; + val2 = 3\'b011; + #1 if(result !==1) + begin + $display(""FAILED case 3.8A - case (expr) lab2: ""); + error = 1; + end + + + val1 = 3\'b111;\t// Should get no-action - expr = 3\'b011 + #1 if(result !==1) + begin + $display(""FAILED case 3.8A - case (expr) lab1: ""); + error = 1; + end + + if(error == 0) + $display(""PASSED""); + end + +endmodule // main +" +"module stimulus (output reg A, B); + + + initial begin + {A, B} = 2\'b00; + #10 {A, B} = 2\'b01; + #10 {A, B} = 2\'b10; + #10 {A, B} = 2\'b11; + end + +endmodule + +module scoreboard (input Y, A, B); + +function truth_table (input a, b); + reg [1:0] gate_operand; + reg gate_output; + begin + gate_operand[1:0] = {a, b}; + case (gate_operand) + 2\'b00: gate_output = 1; + 2\'b01: gate_output = 1; + 2\'b10: gate_output = 1; + 2\'b11: gate_output = 0; + endcase + + truth_table = gate_output; + end +endfunction + + +reg Y_t; + +always @(A or B) begin + Y_t = truth_table (A, B); + #1; + //$display (""a = %b, b = %b, Y_s = %b, Y = %b"", A, B, Y_s, Y); + if (Y_t !== Y) begin + $display(""FAILED! - mismatch found for inputs %b and %b in NAND operation"", A, B); + $finish; + end +end + +endmodule + +module test; + stimulus stim (A, B); + nand_gate duv (.a_i(A), .b_i(B), .c_o(Y) ); + scoreboard mon (Y, A, B); + + initial begin + #100; + $display(""PASSED""); + $finish; + end + +endmodule +" +"module automatic_error(); + +task automatic auto_task; + +reg local; + +local = 1; + +endtask + +initial auto_task.local = 0; + +endmodule +" +"// pr1639060 + +module top; + real value; + + initial begin + value = 10.0; + // value = -10.0; + print; + end + + task print; + + real tmp; + + begin + if (value < 0.0) tmp = value + 10.0; + else tmp = value; + $display(""1. The result is %5.1f"", tmp); + + // This line fails! + tmp = (value < 0.0) ? value+10.0 : value; + $display(""2. The result is %5.1f"", tmp); + end + endtask +endmodule +" +"/* + * This demonstrates that strings can be used as + * constructed formats in $display et al. + */ +module main; + + string foo; + string bar; + + initial begin + bar = ""PAS""; + foo = {bar, ""SED""}; + if (foo != ""PASSED"") begin +\t $display(""FAILED (1)""); +\t $finish; + end + + foo = ""PAS""; + bar = ""SED""; + + $display({foo,bar}); + $finish; + end +endmodule // main +" +"module copy(input [1:0] out, output [1:0] in); + +assign out = in; + +endmodule + +module top(); + +reg [2:0] r; +wire [1:0] i1; +wire [1:0] i2; +wire [1:0] i3; +wire [0:0] o1; +wire [1:0] o2; +wire [2:0] o3; + +assign i1 = r; +assign i2 = r; +assign i3 = r; + +copy copy1(o1, i1); +copy copy2(o2, i2); +copy copy3(o3, i3); + +reg failed; + +initial begin + failed = 0; + for (r = 0; r < 4; r = r + 1) begin + #1 $display(""%b : %b %b : %b %b : %b %b"", r[1:0], i1, o1, i2, o2, i3, o3); + if (o1 !== r[0]) failed = 1; + if (o2 !== r[1:0]) failed = 1; + if (o3 !== {1\'bz, r[1:0]}) failed = 1; + end + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"// Check assignment operations in constant functions. +module constfunc7(); + +function real i_to_r(input signed [3:0] value); + i_to_r = value + 0.5; +endfunction + +function signed [3:0] r_to_i(input real value); + r_to_i = value; +endfunction + +function real u_to_r(input [3:0] value); + u_to_r = value + 0.5; +endfunction + +function [3:0] r_to_u(input real value); + r_to_u = value; +endfunction + +function [3:0] i_to_u(input signed [3:0] value); + i_to_u = value; +endfunction + +function signed [3:0] u_to_i(input [3:0] value); + u_to_i = value; +endfunction + +function [5:0] si_to_lu(input signed [3:0] value); + si_to_lu = value; +endfunction + +function signed [5:0] su_to_li(input [3:0] value); + su_to_li = value; +endfunction + +function [3:0] li_to_su(input signed [5:0] value); + li_to_su = value; +endfunction + +function signed [3:0] lu_to_si(input [5:0] value); + lu_to_si = value; +endfunction + +localparam i_to_r_res1 = i_to_r(-9); +localparam i_to_r_res2 = i_to_r(-8); +localparam i_to_r_res3 = i_to_r( 7); +localparam i_to_r_res4 = i_to_r( 8); + +localparam r_to_i_res1 = r_to_i(-8.5); +localparam r_to_i_res2 = r_to_i(-7.5); +localparam r_to_i_res3 = r_to_i( 6.5); +localparam r_to_i_res4 = r_to_i( 7.5); + +localparam u_to_r_res1 = u_to_r(-1); +localparam u_to_r_res2 = u_to_r( 1); +localparam u_to_r_res3 = u_to_r(15); +localparam u_to_r_res4 = u_to_r(17); + +localparam r_to_u_res1 = r_to_u(-0.5); +localparam r_to_u_res2 = r_to_u( 0.5); +localparam r_to_u_res3 = r_to_u(14.5); +localparam r_to_u_res4 = r_to_u(16.5); + +localparam i_to_u_res1 = i_to_u(-9); +localparam i_to_u_res2 = i_to_u(-8); +localparam i_to_u_res3 = i_to_u( 7); +localparam i_to_u_res4 = i_to_u( 8); + +localparam u_to_i_res1 = u_to_i(-1); +localparam u_to_i_res2 = u_to_i( 1); +localparam u_to_i_res3 = u_to_i(15); +localparam u_to_i_res4 = u_to_i(17); + +localparam si_to_lu_res1 = si_to_lu(-9); +localparam si_to_lu_res2 = si_to_lu(-8); +localparam si_to_lu_res3 = si_to_lu( 7); +localparam si_to_lu_res4 = si_to_lu( 8); + +localparam su_to_li_res1 = su_to_li(-1); +localparam su_to_li_res2 = su_to_li( 1); +localparam su_to_li_res3 = su_to_li(15); +localparam su_to_li_res4 = su_to_li(17); + +localparam li_to_su_res1 = li_to_su(-9); +localparam li_to_su_res2 = li_to_su(-8); +localparam li_to_su_res3 = li_to_su( 7); +localparam li_to_su_res4 = li_to_su( 8); + +localparam lu_to_si_res1 = lu_to_si(-1); +localparam lu_to_si_res2 = lu_to_si( 1); +localparam lu_to_si_res3 = lu_to_si(15); +localparam lu_to_si_res4 = lu_to_si(17); + +reg failed; + +initial begin + failed = 0; + + $display(""%0g"", i_to_r_res1); if (i_to_r_res1 != 7.5) failed = 1; + $display(""%0g"", i_to_r_res2); if (i_to_r_res2 != -7.5) failed = 1; + $display(""%0g"", i_to_r_res3); if (i_to_r_res3 != 7.5) failed = 1; + $display(""%0g"", i_to_r_res4); if (i_to_r_res4 != -7.5) failed = 1; + $display(""""); + $display(""%0d"", r_to_i_res1); if (r_to_i_res1 !== 7) failed = 1; + $display(""%0d"", r_to_i_res2); if (r_to_i_res2 !== -8) failed = 1; + $display(""%0d"", r_to_i_res3); if (r_to_i_res3 !== 7) failed = 1; + $display(""%0d"", r_to_i_res4); if (r_to_i_res4 !== -8) failed = 1; + $display(""""); + $display(""%0g"", u_to_r_res1); if (u_to_r_res1 != 15.5) failed = 1; + $display(""%0g"", u_to_r_res2); if (u_to_r_res2 != 1.5) failed = 1; + $display(""%0g"", u_to_r_res3); if (u_to_r_res3 != 15.5) failed = 1; + $display(""%0g"", u_to_r_res4); if (u_to_r_res4 != 1.5) failed = 1; + $display(""""); + $display(""%0d"", r_to_u_res1); if (r_to_u_res1 !== 15) failed = 1; + $display(""%0d"", r_to_u_res2); if (r_to_u_res2 !== 1) failed = 1; + $display(""%0d"", r_to_u_res3); if (r_to_u_res3 !== 15) failed = 1; + $display(""%0d"", r_to_u_res4); if (r_to_u_res4 !== 1) failed = 1; + $display(""""); + $display(""%0d"", i_to_u_res1); if (i_to_u_res1 !== 7) failed = 1; + $display(""%0d"", i_to_u_res2); if (i_to_u_res2 !== 8) failed = 1; + $display(""%0d"", i_to_u_res3); if (i_to_u_res3 !== 7) failed = 1; + $display(""%0d"", i_to_u_res4); if (i_to_u_res4 !== 8) failed = 1; + $display(""""); + $display(""%0d"", u_to_i_res1); if (u_to_i_res1 !== -1) failed = 1; + $display(""%0d"", u_to_i_res2); if (u_to_i_res2 !== 1) failed = 1; + $display(""%0d"", u_to_i_res3); if (u_to_i_res3 !== -1) failed = 1; + $display(""%0d"", u_to_i_res4); if (u_to_i_res4 !== 1) failed = 1; + $display(""""); + $display(""%0d"", si_to_lu_res1); if (si_to_lu_res1 !== 7) failed = 1; + $display(""%0d"", si_to_lu_res2); if (si_to_lu_res2 !== 56) failed = 1; + $display(""%0d"", si_to_lu_res3); if (si_to_lu_res3 !== 7) failed = 1; + $display(""%0d"", si_to_lu_res4); if (si_to_lu_res4 !== 56) failed = 1; + $display(""""); + $display(""%0d"", su_to_li_res1); if (su_to_li_res1 !== 15) failed = 1; + $display(""%0d"", su_to_li_res2); if (su_to_li_res2 !== 1) failed = 1; + $display(""%0d"", su_to_li_res3); if (su_to_li_res3 !== 15) failed = 1; + $display(""%0d"", su_to_li_res4); if (su_to_li_res4 !== 1) failed = 1; + $display(""""); + $display(""%0d"", li_to_su_res1); if (li_to_su_res1 !== 7) failed = 1; + $display(""%0d"", li_to_su_res2); if (li_to_su_res2 !== 8) failed = 1; + $display(""%0d"", li_to_su_res3); if (li_to_su_res3 !== 7) failed = 1; + $display(""%0d"", li_to_su_res4); if (li_to_su_res4 !== 8) failed = 1; + $display(""""); + $display(""%0d"", lu_to_si_res1); if (lu_to_si_res1 !== -1) failed = 1; + $display(""%0d"", lu_to_si_res2); if (lu_to_si_res2 !== 1) failed = 1; + $display(""%0d"", lu_to_si_res3); if (lu_to_si_res3 !== -1) failed = 1; + $display(""%0d"", lu_to_si_res4); if (lu_to_si_res4 !== 1) failed = 1; + $display(""""); + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"/* + * Copyright (c) 2000 Mark Schellhorn + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/**************************************************************************** + + The following code illustrates an apparent bug in the VCS v5.2 simulator. + The check for whether or not the memory[0] array element was set correctly + fails; yet the $display statement immediately after the check shows the + memory[0] element actually has been set correctly. + + I\'ve noted that if the $display and the check are reversed, the $display + is incorrect but the check passes. + + This appears to be a problem with the simulator\'s internal scheduler. + +***************************************************************************/ + + +module bug_test; + +reg [1:0] temp; + +initial begin + + /********** First test. */ + + $display(""Running first test.\ +""); + + // Try setting memory array in other module using hierarchical + // references & concatenation. + temp = 2\'h3; + top.memory.memory[0] = {2\'h0,temp}; + top.memory.memory[0] = {top.memory.memory[0],temp}; + + // Check that setting was made correctly + if (top.memory.memory[0] != {2{temp}}) begin + $display(""ERROR! top.memory.memory[0] failed to get""); + $display(""set correctly!""); + end else begin + $display(""PASS! top.memory.memory[0] set correctly.""); + end + + // Display the value that was checked + $display(""top.memory.memory[0] = %h"",top.memory.memory[0]); + + + + /********** Second test. */ + + $display(""\ +Running second test.\ +""); + + // Try setting memory array in other module using hierarchical + // references & concatenation. + temp = 2\'h3; + top.memory.memory[1] = {2\'h0,temp}; + top.memory.memory[1] = {top.memory.memory[1],temp}; + + // Display the value that will be checked + $display(""top.memory.memory[1] = %h"",top.memory.memory[1]); + + // Check that setting was made correctly + if (top.memory.memory[1] != {2{temp}}) begin + $display(""ERROR! top.memory.memory[1] failed to get""); + $display(""set correctly!""); + end else begin + $display(""PASS! top.memory.memory[1] set correctly.""); + end + + // Display the value that was checked + $display(""top.memory.memory[1] = %h"",top.memory.memory[1]); + + $finish(0); + +end + +endmodule + +// Module containing a memory array +module memory; + +reg [3:0] memory [0:1]; + +endmodule + +// Module to instantiate test and memory modules +module top; + + bug_test bug_test(); + memory memory(); + +endmodule +" +"package foobar; + +class aclass; + bit tested = 0; + + task test; + begin + $display(""Testing classes in packages""); + tested = 1; + end + endtask +endclass + aclass bar = new; +endpackage + +module test; + import foobar::*; + initial begin + bar.test; + if (bar.tested) + $display(""PASSED""); + else + $display(""FAILED""); + end +endmodule +" +"/* PR1645518 */ + +module testBench; + wire w1, w2, w3, w4, w5; + binaryToESeg d (w1, w2, w3, w4, w5); + test_bToESeg t (w1, w2, w3, w4, w5); +endmodule + +module binaryToESeg + (input A, B, C, D, + output eSeg); + nand #1 + g1 (p1, C, ~D), + g2 (p2, A, B), + g3 (p3, ~B, ~D), + g4 (p4, A, C), + g5 (eSeg, p1, p2, p3, p4); +endmodule // binaryToESeg + +module test_bToESeg + (output reg A, B, C, D, input eSeg); + initial // two slashes introduce a single line comment + begin + $monitor ($time,, +\t\t""A = %b B = %b C = %b D = %b, eSeg = %b"", +\t\tA, B, C, D, eSeg); + //waveform for simulating the nand lip lop + #10 A = 0; B = 0; C = 0; D = 0; + #10 D = 1; + #10 C = 1; D = 0; + #10 $finish(0); + end +endmodule +" +"class testclass; + task start(); + top.dut.signal = 1; + endtask +endclass + +module dut(); + logic signal = 0; + + initial begin + $display(signal); + @(signal); + $display(signal); + if (signal === 1) + $display(""PASSED""); + else + $display(""FAILED""); + $finish; + end +endmodule + +module top(); + testclass tc; + + initial begin + #1 tc.start(); + end + + dut dut(); +endmodule +" +"module test(); +wire [1:0] b; + +assign b[0] = 0; + +a a(~b[0]); + +endmodule + +module a(b); +input b; +initial #1 if (b) $display(""PASSED""); else $display(""FAILED""); +endmodule +" +"`celldefine +//`timescale 1ns / 1ps + +// Description : 2 input XOR + +module XOR20 (input A, input B, output Q); + + xor (Q,B,A); + + specify + (A => Q) = (1,1); + (B => Q) = (1,1); + endspecify + +endmodule + +`endcelldefine + +module tb; + + reg a, b; + wire q; + XOR20 dut(.A(a), .B(b), .Q(q)); + + initial begin + $monitor($time,, ""A=%b, B=%b, Q=%b"", a, b, q); + $dump_specify(dut); + + #10 ; + a = 1; + b = 1; + #10 ; + b = 0; + #10 $finish(0); + end + +endmodule // tb +" +"/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This module checks integer initialization syntax. + */ +module main; + + integer i = 8; + time t = 0; + + + initial begin + #1 if (i !== 8) begin + $display(""FAILED -- i == %b"", i); + $finish; + end + + if (t !== 0) begin + $display(""FAILED -- t == %b"", t); + $finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"package test_pkg; + +// Need to add enumerations to packages. + typedef enum logic[4:0] { + + EXC_A = 0, + EXC_B = 1, + EXC_C = 2 + } exc_code_t; + +// Need to search up the parent scope searching for the enum definition. + function logic func1(exc_code_t c); + logic rVal; + case(c) + EXC_C : rVal = 1; + default: rVal = 0; + endcase + return(rVal); + endfunction + +endpackage + +module a(); + + import test_pkg::func1; + import test_pkg::exc_code_t; + + exc_code_t exc_code; + logic result; + + initial begin + +// Need to compare the base enumeration definition to check compatibility. + exc_code = test_pkg::EXC_C; + + result = func1(exc_code); + + if(result==1\'b1) begin + $display(""PASSED""); + $finish; + end + + $display(""FAILED""); + $finish; + + end + +endmodule +" +"// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Tests accessing individual characters in a string + +module string_index(); + +initial begin + int i; + string str = ""that is a test string""; + + for(i = 0; i < $size(str); ++i) + begin + if(str[i] == ""t"") + str[i] = ""w""; + end + + if(str != ""whaw is a wesw swring"") + begin + $display(""FAILED""); + $finish(); + end + + $display(""PASSED""); +end + +endmodule + +" +"`timescale 1ns/10ps + +module top; + initial begin + $timeformat(-6, 0, "" uS"", 8); + #10 $display(""The time is %t"", $time); + #1000 $display(""The time is %t"", $time); + end +endmodule +" +"module top; + reg [2:-1] vec; + integer idx; + + initial begin + idx = 'bx; + assign vec[idx] = 1'b1; + deassign vec[idx]; + end +endmodule +" +"typedef struct packed { + union packed { + logic[2:0] a; + logic[2:0] b; + } u; +} s1; + +module top(); + +s1 source; +logic result; + +logic failed = 0; + +initial begin + source.u.a = 3\'b000; + result = | source.u.b; + if (result !== 1\'b0) failed = 1; + source.u.a = 3\'b001; + result = | source.u.b; + if (result !== 1\'b1) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate Modulus operator + +module top; + +reg [7:0] a,b; +wire [7:0] wa,wb; +reg [7:0] result; +wire [7:0] wresult; +reg [15:0] work; +reg error; + +assign wa = a; +assign wresult = work % a; + +always @ (work or wa) + result = work % a; + +initial + begin + error = 0; + /* Try mod div by 0 */ + #1; + a = 0; + work = 16\'d1235; + #1; + if(wresult !== 8\'hxx) + begin + $display(""FAILED - wire 1235 mod 0: wresult = %h"",wresult); + error =1; + end + if(result !== 8\'hxx) + begin + $display(""FAILED - reg 1235 mod 0: result = %h"",result); + error =1; + end + #1; + a = 8\'d10; + #1; + if(wresult !== 8\'h05) + begin + $display(""FAILED - wire 1235 mod 10: wresult = %h"",wresult); + error =1; + end + if(result !== 8\'h05) + begin + $display(""FAILED - reg 1235 mod 10: result = %h"",result); + error =1; + end + + #1; + a = 8\'b0000_x001; + #1; + if(wresult !== 8\'bxxxx_xxxx) + begin + $display(""FAILED - wire 1235 mod 10: wresult = %h"",wresult); + error =1; + end + if(result !== 8\'bxxxx_xxxx) + begin + $display(""FAILED - reg 1235 mod 10: result = %h"",result); + error =1; + end + + + if(error == 0) + $display(""PASSED""); + + end + +endmodule +" +"// pr1750870 + +module test (FUSE_Q); + + parameter fuse_a_msb = 4; + + parameter fuse_q_msb = (2**(fuse_a_msb+1))-1; + + input [fuse_q_msb:0] FUSE_Q; + + initial begin + $display(""fuse_q_msb = %d"", fuse_q_msb); + if ($bits(FUSE_Q) != 32) begin +\t $display(""FAILED -- $bits(FUSE_Q) = %d"", $bits(FUSE_Q)); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule +" +"/* + * Check that errors are caught. + */ + +timeunit 100us/1us; + +// Repeated declarations must match the initial declarations. +timeunit 1ms/1ns; + +// A local time unit/precision is OK, but a repeat must match. +module check_tup_d_e; + timeunit 10us/10us; + timeunit 1us/1us; + timeunit 1us; + timeprecision 1us; +endmodule + +// A repeat time unit/precision is only allowed if an initial one is given. +module check_tup_m_e; + integer foo; + timeunit 10us/10us; +endmodule + +// A local time unit is OK and a repeat is OK, but this is not a prec decl. +module check_tu_d_e; + timeunit 10us; + timeunit 10us/1us; +endmodule + +// A local time prec is OK and a repeat is OK, but this is not a unit decl. +module check_tp_d_e; + timeprecision 1us; + timeunit 10us/1us; +endmodule + +/* Check some invalid values */ + +// Only a power of 10 is allowed. +timeunit 200s/200s; +// Too many zeros (only allow 0 - 2). +timeunit 1000s/1000s; +// This actually trips as an invalid scale of '2s'. +timeunit 12s/12s; +// This needs to be checked. The base time_literal supports this, but +// for now timeunit/precision code does not. +timeunit 1_0s/1_0s; +" +"\r +\r +module test();\r + typedef struct packed {\r + logic [31:0] sub_local;\r + } row_entry_t; \r +\r + typedef struct packed {\r + logic [31:0] row_local;\r + row_entry_t sub;\r + row_entry_t [1:0] sub_list;\r + } row_t; \r + \r + row_t main;\r +\r + initial begin\r + main.row_local = 32\'hCAFE;\t\r + main.sub.sub_local = 32\'h00000001;\r + main.sub_list[0].sub_local = 32\'hACE;\r + main.sub_list[1].sub_local = 32\'hECA;\r + $display(""main=0x%08X"", main);\r + if (main !== 128\'h0000cafe0000000100000eca00000ace) begin\r +\t $display(""FAILED -- main != 128\'h0000cafe0000000100000eca00000ace"");\r +\t $finish;\r + end\r + $display(""main.row_local=0x%08X"", main.row_local); \r + $display(""main.sub=0x%08X"", main.sub); \r + //$display(""0x%08X"", main.sub.sub_local); \r + //$display(""0x%08X"", main.sub_list[0].sub_local); \r + $display(""PASSED"");\r + $finish();\r + end\r +\r +endmodule\r +" +"// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for basic loops in VHDL. + +module vhdl_loop_test; +logic start; +int counter; +vhdl_loop dut(start, counter); + +initial begin + for(int i = 0; i < 5; ++i) begin + if(counter !== i) begin + $display(""FAILED""); + $finish(); + end + + #10; + end + + $display(""PASSED""); + $finish(); +end +endmodule +" +"module top; + reg pass; + reg [3:0] value; + reg [3:0] in; + + initial begin + pass = 1\'b1; + value = 4\'b1001; + if (value !== 4\'b1001) begin + $display(""Failed: initial value, expected 4\'b1001, got %b"", value); + pass = 1\'b0; + end + + in = 4\'bzx10; + // This should work since it is really the whole value. + force value[0 +: 4] = in; + if (value !== 4\'bzx10) begin + $display(""Failed: force value, expected 4\'bzx10, got %b"", value); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW: Module instantiation with non-ordered port assignment +// +// D: Same as sdw_inst1 except using .net(net) port convention. +// + +module test_mod (reset,clka,out); +input reset; +input clka; +output out; + +reg out; + +always @(posedge clka or posedge reset) + if(reset) + out = 0; + else + out = ~out; + +endmodule + +module main(); + +reg reset,clk_0,clk_1; +wire out_0,out_1; + +test_mod module_1 (.reset(reset),.clka(clk_0),.out(out_0)); +test_mod module_2 (.reset(reset),.clka(clk_1),.out(out_1)); + +initial + begin + clk_0 = 0; + clk_1 = 0; + #1 reset = 1; + # 2; + $display(""time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\ +"",$time,reset,clk_0, + clk_1,out_0,out_1); + // Validate that both out_0 and out_1 are reset + if(out_0) + begin + $display(""FAILED - out_0 not reset\ +""); + $finish ; + end + + if(out_1) + begin + $display(""FAILED - out_1 not reset\ +""); + $finish ; + end + reset = 0; + $display(""time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\ +"",$time,reset,clk_0, + clk_1,out_0,out_1); + # 2; + clk_0 = 1; + # 2; // Wait so we don\'t worry about races. + $display(""time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\ +"",$time,reset,clk_0, + clk_1,out_0,out_1); + if(!out_0) + begin + $display(""FAILED - out_0 didn\'t set on clk_0\ +""); + $finish ; + end + + if(out_1) + begin + $display(""FAILED - out_1 set on wrong clk!\ +""); + $finish ; + end + + clk_1 = 1; + # 2; // Wait so we don\'t worry about races. + $display(""time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\ +"",$time,reset,clk_0, + clk_1,out_0,out_1); + if(!out_1) + begin + $display(""FAILED - out_1 didn\'t set on clk_1\ +""); + $finish ; + end + + if(!out_0) + begin + $display(""FAILED - out_0 changed due to clk_0\ +""); + $finish ; + end + + + $display(""PASSED\ +""); + $finish ; + end +endmodule +" +"/* + * Copyright (c) 2001 Ted Bullen + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// This code is released to Steve Williams for the Icarus Verilog compiler +// It can be used as desired ! + + +// DEFINES +`define NRBITS 4\t// Number of bits in each operand + +// TOP MODULE +module testFunction(); + + // SIGNAL DECLARATIONS + reg\t\t\t\tclock; + reg [`NRBITS-1:0]\t\ta_in; + integer\t\t\ta_integer; + integer\t\t\tmyint; + reg [`NRBITS:0]\t\tcycle_count;\t// Counts valid clock cycles + + // Initialize inputs + initial begin +\t clock = 1; +\t cycle_count = 0; + # (16*200+15) $display(""PASSED""); + $finish; + end + + // Generate the clock + always #100 clock = ~clock; + + // Simulate + always @(negedge clock) begin +\t cycle_count = cycle_count + 1; + +\t // Create inputs between 0 and all 1s +\t a_in = cycle_count[`NRBITS-1:0]; +\t myint = a_in; +\t $display(""a_in = %d, myint = %d"", a_in, myint); + +\t // Convert the unsigned numbers to signed numbers +\t a_integer = short_to_int(a_in); + + +\t if (myint !== a_integer) +\t\t begin +\t\t\t$display(""ERROR ! %d !== %d"", myint, a_integer); +\t\t\t$stop; +\t\t end + end + + // Function\tto convert a reg of `NRBITS + // bits to a signed integer + function integer short_to_int; + +\t input [`NRBITS-1:0]\tx; +\t begin +\t\t short_to_int = x; +\t\t $display(""\\tshort_to_int(%b) = %b"", x, short_to_int); +\t end + endfunction +endmodule +" +"// based on PR#1022 + +module foo; + wire [-1:0] fred; + assign fred = 1; + + initial begin + #1 if (fred[0] !== 1) begin +\t $display(""FAILED -- fred[0] = %b"", fred[0]); +\t $finish; + end + + if (fred[-1] !== 0) begin +\t $display(""FAILED -- fred[-1] = %b"", fred[-1]); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule +" +"`begin_keywords ""1364-2005"" +module top; + reg svar; + reg sarr [1:0]; + reg sout, stmp; + wire wsarr [1:0]; + wire wsbslv, wspslv, wsuplv, wsdolv; + wire wsbstr, wspstr, wsuptr, wsdotr; + + wire wsbs = svar[0]; + wire wsps = svar[0:0]; + wire wsup = svar[0+:1]; + wire wsdo = svar[0-:1]; + + wire wsabs = sarr[0][0]; + wire wsaps = sarr[0][0:0]; + wire wsaup = sarr[0][0+:1]; + wire wsado = sarr[0][0-:1]; + + assign wsbslv[0] = svar; + assign wspslv[0:0] = svar; + assign wsuplv[0+:1] = svar; + assign wsdolv[0-:1] = svar; + + assign wsarr[0][0] = svar; + assign wsarr[0][0:0] = svar; + assign wsarr[0][0+:1] = svar; + assign wsarr[0][0-:1] = svar; + + tran(wsbstr[0], wsarr[1]); + tran(wspstr[0:0], wsarr[1]); + tran(wsuptr[0+:1], wsarr[1]); + tran(wsdotr[0-:1], wsarr[1]); + + submod1 s1 (wsbstr[0], wspstr[0:0], wsuptr[0+:1], wsdotr[0-:1]); + submod2 s2 (wsbstr[0], wspstr[0:0], wsuptr[0+:1], wsdotr[0-:1]); + submod3 s3 (wsbstr[0], wspstr[0:0], wsuptr[0+:1], wsdotr[0-:1]); + + task stask; + input a; + reg local; + begin + local = a[0]; + local = a[0:0]; + local = a[0+:1]; + local = a[0-:1]; + end + endtask + + initial begin + stmp = svar[0]; + stmp = svar[0:0]; + stmp = svar[0+:1]; + stmp = svar[0-:1]; + + stmp = sarr[0][0]; + stmp = sarr[0][0:0]; + stmp = sarr[0][0+:1]; + stmp = sarr[0][0-:1]; + + sout[0] = 1\'b0; + sout[0:0] = 1\'b0; + sout[0+:1] = 1\'b0; + sout[0-:1] = 1\'b0; + + sarr[0][0] = 1\'b0; + sarr[0][0:0] = 1\'b0; + sarr[0][0+:1] = 1\'b0; + sarr[0][0-:1] = 1\'b0; + end +endmodule + +module submod1(arg1, arg2, arg3, arg4); + input arg1, arg2, arg3, arg4; + wire arg1, arg2, arg3, arg4; + + initial $display(""In submod1 with %b, %b, %b, %b"", arg1, arg2, arg3, arg4); +endmodule + +module submod2(arg1, arg2, arg3, arg4); + output arg1, arg2, arg3, arg4; + wire arg1, arg2, arg3, arg4; + + initial $display(""In submod2 with %b, %b, %b, %b"", arg1, arg2, arg3, arg4); +endmodule + +module submod3(arg1, arg2, arg3, arg4); + inout arg1, arg2, arg3, arg4; + wire arg1, arg2, arg3, arg4; + + initial $display(""In submod3 with %b, %b, %b, %b"", arg1, arg2, arg3, arg4); +endmodule +`end_keywords +" +"module bar; + reg [24:1] original = 24\'h123456; + reg [8:1] second, minus_indexed, plus_indexed; + + integer tmp; + initial begin + second = original[16:9]; + minus_indexed = original[16 -:8]; + plus_indexed = original[9 +:8]; + $display (""Orig = %h, Second = %h, Minus Indexed = %h, Plus Indexed = %h"", +\t\toriginal, second, minus_indexed, plus_indexed); + + tmp = 9; + second = original[16:9]; + minus_indexed = original[tmp+7 -:8]; + plus_indexed = original[tmp +:8]; + $display (""Orig = %h, Second = %h, Minus Indexed = %h, Plus Indexed = %h"", +\t\toriginal, second, minus_indexed, plus_indexed); + end + endmodule +" +"module test; + function integer fn (input integer a, b, input integer c); + fn = ((a > b) ? a : b) + c; + endfunction + + initial begin + if (fn(2, 4, 3) != 7) $display(""Failed""); + else $display(""PASSED""); + end +endmodule +" +"/* + * This test deminstrates a complication in the handling of a vector + * as a unit, instead of breaking it out. The problem is with the + * legal inout expression that takes one bit of the vector. That + * leads to a driver to the input of a part select, and also the + * other way around. Yikes. + */ +module main; + + reg [1:0] drv = 2\'b0z; + wire [1:0] a = drv; + reg\t en; + + bi dut0(a[0], en); + + initial begin + en <= 0; + + #1 $display(""drv=%b en=%b, a=%b (should be 0z)"", drv, en, a); + if (a !== 2\'b0z) begin +\t $display(""FAILED""); +\t $finish; + end + + en <= 1; + + #1 $display(""drv=%b en=%b, a=%b (should be 01)"", drv, en, a); + if (a !== 2\'b01) begin +\t $display(""FAILED""); +\t $finish; + end + + $display(""PASSED""); + $finish; + end + +endmodule // main + +module bi (inout a, input en); + + reg val = 1; + assign a = en? val : 1\'bz; + +endmodule // bi +" +"module top; + reg [31:0] mem [3:0]; + + initial begin + mem[1] = {32{1\'b1}}; + mem[1][15] = 1\'b0; + + if (mem[1] !== 32\'hffff7fff) $display(""Failed, got %h"", mem[1]); + else $display(""PASSED""); + end +endmodule +" +"module pr2974294; + +reg [7:0] array[1:0]; +wire [7:0] word; +reg fail; + +assign word = array[0]; + +initial begin + fail = 0; + #0 $display(""%b"", word); + if (word !== 8\'bx) fail = 1; + #1 $display(""%b"", word); + if (word !== 8\'bx) fail = 1; + array[0] = 8\'d0; + #0 $display(""%b"", word); + if (word !== 8\'d0) fail = 1; + if (fail) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"/* + * Copyright (c) 2001 Stephen Rowland + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module dummy; + +reg [7:0] decode_vec; +wire [7:0] data1; +wire [7:0] data2; + +// icarus cant handle this statement +assign data1 = (decode_vec[8\'h02>>1] ) ? 8\'h55 : 8\'h00; + +assign data2 = (decode_vec[8\'h01 ] ) ? 8\'h55 : 8\'h00; + +initial +begin +#0; +$monitor(""%h %h %h"", decode_vec, data1, data2); +decode_vec = 8\'h02; +#10; +decode_vec = 8\'h80; +#10; +decode_vec = 8\'h02; +#10; +$finish(0); +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate continuous <= in assignment. +// + + +module main; + +reg globvar; + +reg [3:0] var1; +reg error; + +wire var2 = (var1 == 4\'h02); + +initial + begin + error = 0; + var1 = 4\'h0 ; + #1 ; + if(var2 != 1\'b0) + begin + $display(""FAILED continuous <= logical op (1)""); + error = 1; + end + #1 ; + var1 = 4\'h2; + #1 ; + if(var2 != 1\'b1) + begin + $display(""FAILED continuos <= logical op (2)""); + error = 1; + end + #1 ; + var1 = 4\'h4; + #1 ; + if(var2 != 1\'b0) + begin + $display(""FAILED continuos <= logical op (3)""); + error = 1; + end + if(error == 0) + $display(""PASSED""); + end + +endmodule // main +" +"/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: ldelay4.v,v 1.3 2007/12/06 02:31:10 stevewilliams Exp $ + +// Test for delays in structural logic. Differential clock receiver UDP. + +module test; + + wire q, e; + reg a, b; + drec #1 rec(q, a, b); + edet det (e, q); + + reg\terror; + initial + begin +\terror = 0; +\t#2; +\tforever @(e) +\t if (e !== 1\'bx) begin // Fail on anything other then x. +\t error = 1; +\t $display(""%0d: FAILED: e=%b"", $time, e); +\t end + end + + always @(q) + $display(""%d: q=%b"", $time, q); + + initial + begin +//\t$dumpvars; +\ta = 0; +\tb = 1; +\t#3; +\ta = 1; +\tb = 0; +\t#2; +\ta = 0; +\tb = 1; +\t#3; +\tif (!error) +\t $display(""PASSED""); + end +endmodule + +// differential receiver + +primitive drec (q, a, b); + output q; + input a, b; + table + 1 0 : 1 ; + 0 1 : 0 ; + endtable +endprimitive + +// flag any edges to or from \'bx + +primitive edet (q, i); + output q; + input i; + reg\t q; + table + (?x) : ? : 1; + (x?) : ? : 0; + endtable +endprimitive +" +"module test(); + +task accumulate1(input integer value, output integer result); + static int acc = 1; + acc = acc + value; + result = acc; +endtask + +task automatic accumulate2(input integer value, output integer result); + int acc = 1; + acc = acc + value; + result = acc; +endtask + +integer value; + +reg failed = 0; + +initial begin + accumulate1(2, value); + $display(""%d"", value); + if (value !== 3) failed = 1; + + accumulate1(3, value); + $display(""%d"", value); + if (value !== 6) failed = 1; + + accumulate2(2, value); + $display(""%d"", value); + if (value !== 3) failed = 1; + + accumulate2(3, value); + $display(""%d"", value); + if (value !== 4) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"// This tests system functions operationg on packed arrays +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test (); + + // parameters for array sizes + localparam WA = 4; + localparam WB = 6; + localparam WC = 8; + + function int wdt (input int i); + wdt = 2 + 2*i; + endfunction + + // 2D packed arrays + logic [WA-1:0] [WB-1:0] [WC-1:0] abg; // big endian array + logic [0:WA-1] [0:WB-1] [0:WC-1] alt; // little endian array + + // error counter + bit err = 0; + + // indexing variable + int i; + + initial begin + // big endian + + // full array + if ($dimensions(abg) != 3) begin $display(""FAILED -- $dimensions(abg) = %0d"", $dimensions(abg)); err=1; end; + if ($bits (abg) != WA*WB*WC) begin $display(""FAILED -- $bits (abg) = %0d"", $bits (abg)); err=1; end; + for (i=1; i<=3; i=i+1) begin + if ($left (abg , i) != wdt(i )-1) begin $display(""FAILED -- $left (abg , %0d) = %0d"", i, $left (abg , i)); err=1; end; + if ($right (abg , i) != 0 ) begin $display(""FAILED -- $right (abg , %0d) = %0d"", i, $right (abg , i)); err=1; end; + if ($low (abg , i) != 0 ) begin $display(""FAILED -- $low (abg , %0d) = %0d"", i, $low (abg , i)); err=1; end; + if ($high (abg , i) != wdt(i )-1) begin $display(""FAILED -- $high (abg , %0d) = %0d"", i, $high (abg , i)); err=1; end; + if ($increment(abg , i) != 1 ) begin $display(""FAILED -- $increment(abg , %0d) = %0d"", i, $increment(abg , i)); err=1; end; + if ($size (abg , i) != wdt(i ) ) begin $display(""FAILED -- $size (abg , %0d) = %0d"", i, $size (abg , i)); err=1; end; + end + // half array + if ($dimensions(abg[1:0]) != 3) begin $display(""FAILED -- $dimensions(abg[1:0]) = %0d"", $dimensions(abg[1:0])); err=1; end; + if ($bits (abg[1:0]) != 2*WB*WC) begin $display(""FAILED -- $bits (abg[1:0]) = %0d"", $bits (abg[1:0])); err=1; end; + for (i=1; i<=3; i=i+1) begin + if ($left (abg[1:0], i) != wdt(i )-1) begin $display(""FAILED -- $left (abg[1:0], %0d) = %0d"", i, $left (abg[1:0], i)); err=1; end; + if ($right (abg[1:0], i) != 0 ) begin $display(""FAILED -- $right (abg[1:0], %0d) = %0d"", i, $right (abg[1:0], i)); err=1; end; + if ($low (abg[1:0], i) != 0 ) begin $display(""FAILED -- $low (abg[1:0], %0d) = %0d"", i, $low (abg[1:0], i)); err=1; end; + if ($high (abg[1:0], i) != wdt(i )-1) begin $display(""FAILED -- $high (abg[1:0], %0d) = %0d"", i, $high (abg[1:0], i)); err=1; end; + if ($increment(abg[1:0], i) != 1 ) begin $display(""FAILED -- $increment(abg[1:0], %0d) = %0d"", i, $increment(abg[1:0], i)); err=1; end; + if ($size (abg[1:0], i) != wdt(i ) ) begin $display(""FAILED -- $size (abg[1:0], %0d) = %0d"", i, $size (abg[1:0], i)); err=1; end; + end + // single array element + if ($dimensions(abg[0]) != 2) begin $display(""FAILED -- $dimensions(abg[0]) = %0d"", $dimensions(abg[0])); err=1; end; + if ($bits (abg[0]) != WB*WC) begin $display(""FAILED -- $bits (abg[0]) = %0d"", $bits (abg[0])); err=1; end; + for (i=1; i<=2; i=i+1) begin + if ($left (abg[0] , i) != wdt(i+1)-1) begin $display(""FAILED -- $left (abg[0] , %0d) = %0d"", i, $left (abg[0] , i)); err=1; end; + if ($right (abg[0] , i) != 0 ) begin $display(""FAILED -- $right (abg[0] , %0d) = %0d"", i, $right (abg[0] , i)); err=1; end; + if ($low (abg[0] , i) != 0 ) begin $display(""FAILED -- $low (abg[0] , %0d) = %0d"", i, $low (abg[0] , i)); err=1; end; + if ($high (abg[0] , i) != wdt(i+1)-1) begin $display(""FAILED -- $high (abg[0] , %0d) = %0d"", i, $high (abg[0] , i)); err=1; end; + if ($increment(abg[0] , i) != 1 ) begin $display(""FAILED -- $increment(abg[0] , %0d) = %0d"", i, $increment(abg[0] , i)); err=1; end; + if ($size (abg[0] , i) != wdt(i+1) ) begin $display(""FAILED -- $size (abg[0] , %0d) = %0d"", i, $size (abg[0] , i)); err=1; end; + end + + // little endian + + // full array + if ($dimensions(alt) != 3) begin $display(""FAILED -- $dimensions(alt) = %0d"", $dimensions(alt)); err=1; end; + if ($bits (alt) != WA*WB*WC) begin $display(""FAILED -- $bits (alt) = %0d"", $bits (alt)); err=1; end; + for (i=1; i<=3; i=i+1) begin + if ($left (alt , i) != 0 ) begin $display(""FAILED -- $left (alt , %0d) = %0d"", i, $left (alt , i)); err=1; end; + if ($right (alt , i) != wdt(i )-1) begin $display(""FAILED -- $right (alt , %0d) = %0d"", i, $right (alt , i)); err=1; end; + if ($low (alt , i) != 0 ) begin $display(""FAILED -- $low (alt , %0d) = %0d"", i, $low (alt , i)); err=1; end; + if ($high (alt , i) != wdt(i )-1) begin $display(""FAILED -- $high (alt , %0d) = %0d"", i, $high (alt , i)); err=1; end; + if ($increment(alt , i) != -1 ) begin $display(""FAILED -- $increment(alt , %0d) = %0d"", i, $increment(alt , i)); err=1; end; + if ($size (alt , i) != wdt(i ) ) begin $display(""FAILED -- $size (alt , %0d) = %0d"", i, $size (alt , i)); err=1; end; + end + // half array + if ($dimensions(alt[0:1]) != 3) begin $display(""FAILED -- $dimensions(alt[0:1]) = %0d"", $dimensions(alt[0:1])); err=1; end; + if ($bits (alt[0:1]) != 2*WB*WC) begin $display(""FAILED -- $bits (alt[0:1]) = %0d"", $bits (alt[0:1])); err=1; end; + for (i=1; i<=3; i=i+1) begin + if ($left (alt[0:1], i) != 0 ) begin $display(""FAILED -- $left (alt[0:1], %0d) = %0d"", i, $left (alt[0:1], i)); err=1; end; + if ($right (alt[0:1], i) != wdt(i )-1) begin $display(""FAILED -- $right (alt[0:1], %0d) = %0d"", i, $right (alt[0:1], i)); err=1; end; + if ($low (alt[0:1], i) != 0 ) begin $display(""FAILED -- $low (alt[0:1], %0d) = %0d"", i, $low (alt[0:1], i)); err=1; end; + if ($high (alt[0:1], i) != wdt(i )-1) begin $display(""FAILED -- $high (alt[0:1], %0d) = %0d"", i, $high (alt[0:1], i)); err=1; end; + if ($increment(alt[0:1], i) != -1 ) begin $display(""FAILED -- $increment(alt[0:1], %0d) = %0d"", i, $increment(alt[0:1], i)); err=1; end; + if ($size (alt[0:1], i) != wdt(i ) ) begin $display(""FAILED -- $size (alt[0:1], %0d) = %0d"", i, $size (alt[0:1], i)); err=1; end; + end + // single array element + if ($dimensions(alt[0]) != 2) begin $display(""FAILED -- $dimensions(alt) = %0d"", $dimensions(alt)); err=1; end; + if ($bits (alt[0]) != WB*WC) begin $display(""FAILED -- $bits (alt) = %0d"", $bits (alt)); err=1; end; + for (i=1; i<=2; i=i+1) begin + if ($left (alt[0] , i) != 0 ) begin $display(""FAILED -- $left (alt[0] , %0d) = %0d"", i, $left (alt[0] , i)); err=1; end; + if ($right (alt[0] , i) != wdt(i+1)-1) begin $display(""FAILED -- $right (alt[0] , %0d) = %0d"", i, $right (alt[0] , i)); err=1; end; + if ($low (alt[0] , i) != 0 ) begin $display(""FAILED -- $low (alt[0] , %0d) = %0d"", i, $low (alt[0] , i)); err=1; end; + if ($high (alt[0] , i) != wdt(i+1)-1) begin $display(""FAILED -- $high (alt[0] , %0d) = %0d"", i, $high (alt[0] , i)); err=1; end; + if ($increment(alt[0] , i) != -1 ) begin $display(""FAILED -- $increment(alt[0] , %0d) = %0d"", i, $increment(alt[0] , i)); err=1; end; + if ($size (alt[0] , i) != wdt(i+1) ) begin $display(""FAILED -- $size (alt[0] , %0d) = %0d"", i, $size (alt[0] , i)); err=1; end; + end + + if (!err) $display(""PASSED""); + end + +endmodule // test +" +"module test; + reg fail = 1\'b0; + reg [3:0] bus = 4\'b0; + wire [3:0] val = bus; // to check the propagated value is correct + + initial begin + // Check the initial value. + #1 if (val !== 4\'b0) begin + $display(""FAILED: initial value, got %b, expected 0000."", val); + fail = 1; + end + + // Check a bit force and verify a normal bit assign does nothing. + #1 force bus[0] = 1\'b1; + bus[0] = 1\'bz; + #1 if (val !== 4\'b0001) begin + $display(""FAILED: force of bus[0], got %b, expected 0001."", val); + fail = 1\'b1; + end + + // Check a part force + #1 force bus[3:2] = 2\'b11; + #1 if (val !== 4\'b1101) begin + $display(""FAILED: force of bus[3:2], got %b, expected 1101."", val); + fail = 1\'b1; + end + + // Check that we can change an unforced bit. + #1 bus[1] = 1\'bz; + #1 if (val !== 4\'b11z1) begin + $display(""FAILED: assignment of bus[1], got %b, expected 11z1."", val); + fail = 1\'b1; + end + #1 bus[1] = 1\'b0; + + // Check a bit release. + #1 release bus[0]; + bus = 4\'b000z; + #1 if (val !== 4\'b110z) begin + $display(""FAILED: release of bus[0], got %b, expected 110z."", val); + fail = 1\'b1; + end + + // Check a part release. + #1 release bus[3:2]; + bus[3] = 1\'b0; + #1 if (val !== 4\'b010z) begin + $display(""FAILED: release of bus[3:2], got %b, expected 010z."", val); + fail = 1\'b1; + end + + // Check a force from the upper thread bits (>=8). + #1 force bus[2:1] = 2\'bx1; + #1 if (val !== 4\'b0x1z) begin + $display(""FAILED: force of bus[2:1], got %b, expected 0x1z."", val); + fail = 1\'b1; + end + + if (!fail) $display(""PASSED""); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate that an array of modules in supported. +// + +module my_and (out,a,b); +input a,b; +output out; + +and u0 (out,a,b); + +endmodule + +module main; + +reg globvar; + +wire [15:0] out; +reg [15:0] a,b, rslt; +reg error; + +// The test gate goes HERE! + +my_and foo [0:15] (out,a,b); + +always @(a or b) + rslt = a & b; + +initial + begin // { + error = 0; + # 1; + for(a = 16\'h1; a != 16\'hffff; a = (a << 1) | 1) + begin // { + for(b = 16\'hffff; b !== 16\'h0; b = b >> 1) + begin // { + #1 ; + if(out !== rslt) + begin // { + $display(""FAILED - GA And a=%h,b=%h,expct=%h - rcvd=%h"", + a,b,rslt,out); + error = 1; + end // } + end // } + end // } + if( error == 0) + $display(""PASSED""); + end // } +endmodule // main +" +"/* + * Copyright (c) 2000 Guy Hutchison (ghutchis@pacbell.net) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +//`define DEBUG + +`define BUG_FIX + +module drive_strength; + + // strength values (append 1/0 to each): + // supply -> strong -> pull -> weak -> highz + +/* + * Strength Value Table + * 1--> supply | strong | pull | weak | highz + * supply x | 0 | 0 | 0 | 0 + * strong 1 | x | 0 | 0 | 0 + * pull 1 | 1 | x | 0 | 0 + * weak 1 | 1 | 1 | x | 0 + * highz 1 | 1 | 1 | 1 | z + */ + + wire su1su0, su1st0, su1pu0, su1we0, su1hz0; + wire st1su0, st1st0, st1pu0, st1we0, st1hz0; + wire pu1su0, pu1st0, pu1pu0, pu1we0, pu1hz0; + wire we1su0, we1st0, we1pu0, we1we0, we1hz0; + wire hz1su0, hz1st0, hz1pu0, hz1we0, hz1hz0; + + /* supply assignments */ + assign (supply1, supply0) su1su0 = 1\'b1; + assign (supply1, supply0) su1st0 = 1\'b1; + assign (supply1, supply0) su1pu0 = 1\'b1; + assign (supply1, supply0) su1we0 = 1\'b1; + assign (supply1, supply0) su1hz0 = 1\'b1; + + /* strong assignments */ + assign (strong1, strong0) st1su0 = 1\'b1; + assign (strong1, strong0) st1st0 = 1\'b1; + assign (strong1, strong0) st1pu0 = 1\'b1; + assign (strong1, strong0) st1we0 = 1\'b1; + assign (strong1, strong0) st1hz0 = 1\'b1; + + /* pull assignments */ + assign (pull1, pull0) pu1su0 = 1\'b1; + assign (pull1, pull0) pu1st0 = 1\'b1; + assign (pull1, pull0) pu1pu0 = 1\'b1; + assign (pull1, pull0) pu1we0 = 1\'b1; + assign (pull1, pull0) pu1hz0 = 1\'b1; + + /* weak assignments */ + assign (weak1, weak0) we1su0 = 1\'b1; + assign (weak1, weak0) we1st0 = 1\'b1; + assign (weak1, weak0) we1pu0 = 1\'b1; + assign (weak1, weak0) we1we0 = 1\'b1; + assign (weak1, weak0) we1hz0 = 1\'b1; + + /* highz assignments */ + assign (highz1, strong0) hz1su0 = 1\'b1; + assign (highz1, strong0) hz1st0 = 1\'b1; + assign (highz1, strong0) hz1pu0 = 1\'b1; + assign (highz1, strong0) hz1we0 = 1\'b1; + assign (highz1, strong0) hz1hz0 = 1\'b1; + + /* supply assignments */ + assign (supply1, supply0) su1su0 = 1\'b0; + assign (supply1, supply0) st1su0 = 1\'b0; + assign (supply1, supply0) pu1su0 = 1\'b0; + assign (supply1, supply0) we1su0 = 1\'b0; + assign (supply1, supply0) hz1su0 = 1\'b0; + + /* strong assignments */ + assign (strong1, strong0) su1st0 = 1\'b0; + assign (strong1, strong0) st1st0 = 1\'b0; + assign (strong1, strong0) pu1st0 = 1\'b0; + assign (strong1, strong0) we1st0 = 1\'b0; + assign (strong1, strong0) hz1st0 = 1\'b0; + + /* pull assignments */ + assign (pull1, pull0) su1pu0 = 1\'b0; + assign (pull1, pull0) st1pu0 = 1\'b0; + assign (pull1, pull0) pu1pu0 = 1\'b0; + assign (pull1, pull0) we1pu0 = 1\'b0; + assign (pull1, pull0) hz1pu0 = 1\'b0; + + /* weak assignments */ + assign (weak1, weak0) su1we0 = 1\'b0; + assign (weak1, weak0) st1we0 = 1\'b0; + assign (weak1, weak0) pu1we0 = 1\'b0; + assign (weak1, weak0) we1we0 = 1\'b0; + assign (weak1, weak0) hz1we0 = 1\'b0; + + /* highz assignments */ + assign (strong1, highz0) su1hz0 = 1\'b0; + assign (strong1, highz0) st1hz0 = 1\'b0; + assign (strong1, highz0) pu1hz0 = 1\'b0; + assign (strong1, highz0) we1hz0 = 1\'b0; + assign (strong1, highz0) hz1hz0 = 1\'b0; + + initial + begin +`ifdef DEBUG + $dumpfile (""verilog.dump""); + $dumpvars (0, drive_strength); +`endif + + /* check all values for 1/x/0 */ + #1;\t// Give things a chance to evaluate!!! + if ((su1su0 !== 1\'bx) || +\t (su1st0 !== 1\'b1) || +\t (su1pu0 !== 1\'b1) || +\t (su1we0 !== 1\'b1) || +\t (su1hz0 !== 1\'b1) || + (st1su0 !== 1\'b0) || +\t (st1st0 !== 1\'bx) || +\t (st1pu0 !== 1\'b1) || +\t (st1we0 !== 1\'b1) || +\t (st1hz0 !== 1\'b1) || + (pu1su0 !== 1\'b0) || +\t (pu1st0 !== 1\'b0) || +\t (pu1pu0 !== 1\'bx) || +\t (pu1we0 !== 1\'b1) || +\t (pu1hz0 !== 1\'b1) || + (we1su0 !== 1\'b0) || +\t (we1st0 !== 1\'b0) || +\t (we1pu0 !== 1\'b0) || +\t (we1we0 !== 1\'bx) || +\t (we1hz0 !== 1\'b1) || + (hz1su0 !== 1\'b0) || +\t (hz1st0 !== 1\'b0) || +\t (hz1pu0 !== 1\'b0) || +\t (hz1we0 !== 1\'b0) || +\t (hz1hz0 !== 1\'bz)) +\t$display (""FAILED - drive_strength""); + else +\t$display (""PASSED""); + + #10; + $finish; + end // initial begin + +`ifdef BUG_FIX + reg bug_fix; + + initial + begin + bug_fix = 0; + #2; + bug_fix = 1; + #2; + bug_fix = 0; + end +`endif // ifdef BUG_FIX + +endmodule +" +"module top; + reg passed; + reg pevt; + reg evt; + reg pedge; + reg nedge; + + initial begin + passed = 1\'b1; + + #1; // Check X to 0 + {pedge, nedge} = 2\'b01; + evt = 1\'b0; + + #1; // Check 0 to X + pevt = evt; + {pedge, nedge} = 2\'b10; + evt = 1\'bx; + + #1; // Check X to 1 + pevt = evt; + {pedge, nedge} = 2\'b10; + evt = 1\'b1; + + #1; // Check 1 to X + pevt = evt; + {pedge, nedge} = 2\'b01; + evt = 1\'bx; + + #1; // Check X to Z + pevt = evt; + {pedge, nedge} = 2\'b00; + evt = 1\'bz; + + #1; // Check Z to X + pevt = evt; + {pedge, nedge} = 2\'b00; + evt = 1\'bx; + + #1; // Check X to Z (again) + pevt = evt; + {pedge, nedge} = 2\'b00; + evt = 1\'bz; + + #1; // Check Z to 0 + pevt = evt; + {pedge, nedge} = 2\'b01; + evt = 1\'b0; + + #1; // Check 0 to Z + pevt = evt; + {pedge, nedge} = 2\'b10; + evt = 1\'bz; + + #1; // Check Z to 1 + pevt = evt; + {pedge, nedge} = 2\'b10; + evt = 1\'b1; + + #1; // Check 1 to Z + pevt = evt; + {pedge, nedge} = 2\'b01; + evt = 1\'bz; + + #1; // Check Z to 1 (again) + pevt = evt; + {pedge, nedge} = 2\'b10; + evt = 1\'b1; + + #1; // Check 1 to 0 + pevt = evt; + {pedge, nedge} = 2\'b01; + evt = 1\'b0; + + #1; // Check 0 to 1 + pevt = evt; + {pedge, nedge} = 2\'b10; + evt = 1\'b1; + + #1; + + if (passed) $display(""PASSED""); + end + + always @(posedge evt) begin + if (!pedge) begin + $display(""Error: posedge detected for %b -> %b"", pevt, evt); + passed = 1\'b0; + end + end + + always @(negedge evt) begin + if (!nedge) begin + $display(""Error: negedge detected for %b -> %b"", pevt, evt); + passed = 1\'b0; + end + end + + always @(edge evt) begin + if (!nedge && !pedge) begin + $display(""Error: edge detected for %b -> %b"", pevt, evt); + passed = 1\'b0; + end + end + + always @(evt) + $display(""Checking the %b -> %b event"", pevt, evt); +endmodule +" +"module top; + reg signed [63:0] a = 64\'h12345678abcdabcd; + reg signed [63:0] b = 64\'h1234; + + initial + if (a/b !== 64\'h10004c017806b) + $display(""FAILED: expected 64\'h10004c017896b, got 64\'h%h"", a/b); + else $display(""PASSED""); +endmodule +" +"/* + * Copyright (c) 2000 Yasuhisa Kato + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// Modified my stevew@home.com to be self-checking per the comments. + +module main; + + reg clk ; + initial begin clk = 0 ; forever #5 clk = ~clk ; end + initial #20 $finish; + + wire w, ww, wr, w1, wwr, ww1, wr1, wwro, ww1o, wr1o ; + reg r, rw ; + reg error; + + // z <- (z) = z + assign ww = w ; // z <- (z) = z + assign wr = r ; // x <- (z) = x + assign w1 = \'b1 ; // 1 <- (z) = 1 + assign wwr = w & r ; // x <- z & x + assign ww1 = w & \'b1 ; // x <- z & 1 + assign wr1 = r & \'b1 ; // x <- x & 1 + + assign wwro= w | r ; // x <- z | x + assign ww1o= w | \'b1 ; // 1 <- z | 1 + assign wr1o= r | \'b1 ; // 1 <- x | 1 + + always @(posedge clk) + rw <= w ; // x <- (x) = z + + always @(posedge clk) + begin + #1; + $display(""%b %b %b %b %b %b %b : %b %b %b : %b %b"", + w, ww, wr, w1, wwr, ww1, wr1, wwro, ww1o, wr1o, r, rw ); + end + +initial + begin + error = 0; + #19; + if(ww !== 1\'bz) begin + error = 1; + $display(""FAILED - ww s/b z, is %h"",ww); + end + if(wr !== 1\'bx) begin + error = 1; + $display(""FAILED - wr s/b x, is %h"",wr); + end + if(w1 !== 1\'b1) begin + error = 1; + $display(""FAILED - wr s/b 1, is %h"",wr); + end + if(wwr !== 1\'bx) begin + error = 1; + $display(""FAILED - wwr s/b x, is %h"",wwr); + end + if(ww1 !== 1\'bx) begin + error = 1; + $display(""FAILED - ww1 s/b x, is %h"",ww1); + end + if(wr1 !== 1\'bx) begin + error = 1; + $display(""FAILED - wr1 s/b x, is %h"",wr1); + end + if(wwro !== 1\'bx) begin + error = 1; + $display(""FAILED - wwro s/b 1, is %h"",wwro); + end + if(wr1o !== 1\'b1) begin + error = 1; + $display(""FAILED - wr1o s/b 1, is %h"",wr1o); + end + if(r !== 1\'bx) begin + error = 1; + $display(""FAILED - r s/b x, is %h"",r); + end + if(r !== 1\'bx) begin + error = 1; + $display(""FAILED - r s/b x, is %h"",r); + end + if(rw !== 1\'bz) begin + error = 1; + $display(""FAILED - rw s/b z, is %h"",r); + end + if(error === 0) + $display(""PASSED""); + $finish(0); + end + +endmodule + +// *Initial Value Test* + +// expected output - This according to XL +// z z x 1 x x x : x 1 1 : x x +// z z x 1 x x x : x 1 1 : x z + +// ivl current result +// z z x 1 x z x : x 1 1 : x x +// z z x 1 x z x : x 1 1 : x z +" +"module foo(clk, rst, inp_a, inp_b, out); + input wire clk; + input wire rst; + input wire [7:0] inp_a; + input wire [7:0] inp_b; + output reg [7:0] out; + + function [7:0] do_add; + input [7:0] inp_a; + input [7:0] inp_b; + + do_add = inp_a + inp_b; + endfunction + + always @(posedge clk) + if (rst) out <= 0; + else out <= do_add (* combinational_adder *) (inp_a, inp_b); + + initial begin + $display(""PASSED""); + end + +endmodule + +" +"/* + * Copyright (c) 2002 Stephen Rowland + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module dummy7; + +`define ADDR1 16\'h0011 +`define ADDR2 16\'h0022 + +`define ADDR81 8\'h11 +`define ADDR82 8\'h22 + +reg [7:0] data1; +reg [7:0] data2; +reg [7:0] data3; +reg [7:0] data4; +reg [7:0] addr; +reg [15:0] addr16; + +// use mod operator to convert literal to 8 bits - this works in verilogXL +always @ (addr) +case (addr) +`ADDR1 %256 : data1 = 8\'h11; +`ADDR2 %256 : data1 = 8\'h22; +default : data1 = 8\'h00; +endcase + +// icarus like this +always @ (addr) +case (addr) +`ADDR1 : data2 = 8\'h11; +`ADDR2 : data2 = 8\'h22; +default : data2 = 8\'h00; +endcase + + +always @ (addr16) +case (addr16) +`ADDR1 : data3 = 8\'h11; +`ADDR2 : data3 = 8\'h22; +default : data3 = 8\'h00; +endcase + +always @ (addr) +case (addr) +`ADDR81 : data4 = 8\'h11; +`ADDR82 : data4 = 8\'h22; +default : data4 = 8\'h00; +endcase + + +initial +begin +addr = 8\'h00; +addr16 = 16\'h0000; +#10; +$display(""should be 00 -- data1=%h data2=%h data3=%h data4=%h\ +"",data1,data2,data3,data4); + +addr = 8\'h11; +addr16 = 16\'h0011; +#10; +$display(""should be 11 -- data1=%h data2=%h data3=%h data4=%h\ +"",data1,data2,data3,data4); + +addr = 8\'h22; +addr16 = 16\'h0022; +#10; +$display(""should be 22 -- data1=%h data2=%h data3=%h data4=%h\ +"",data1,data2,data3,data4); + + +$finish(0); +end +endmodule +" +"module test ( + input CL, + input CSB +); + + reg a; + + specify specparam + tps = 0.0; + $setup(posedge CSB, edge[01,0x,x1,1x] CL, tps, a); + endspecify + +endmodule +" +"/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * SDW: Verify expression using bit-wise and in a parameter declaration + */ +module test; + +parameter A0 = & 4\'b1111; + +initial + begin + if(A0 !== 1\'b1) + $display(""FAILED - bit-wise and in an expression .""); + else + $display(""PASSED""); + end + +endmodule +" +"module part1 ( +\\6A_A , +\\6Y_A , +VCC , +GND , +\\6A_B , +\\6Y_B , +\\6A_C , +\\6Y_C , +\\6A_D , +\\6Y_D , +\\6A_E , +// note: there is not a space character before the nl below +\\6Y_E + ) ; + +input \\6A_A ; +output \\6Y_A ; +input VCC ; +input GND ; +input \\6A_B ; +output \\6Y_B ; +input \\6A_C ; +output \\6Y_C ; +input \\6A_D ; +output \\6Y_D ; +input \\6A_E ; +output \\6Y_E ; + +assign \\6Y_A = ~\\6A_A ; +assign \\6Y_B = ~\\6A_B ; +assign \\6Y_C = ~\\6A_C ; +assign \\6Y_D = ~\\6A_D ; +assign \\6Y_E = ~\\6A_E ; + +endmodule +" +"module bug(); + +reg [0:1][0:15][0:7] array; + +reg failed = 0; + +integer i; + +reg [3:0] index; + +initial begin + i = $bits(array); + $display(""width 0 = %0d"", i); + if (i !== 256) failed = 1; + + i = $bits(array[0]); + $display(""width 1 = %0d"", i); + if (i !== 128) failed = 1; + + i = $bits(array[0][0]); + $display(""width 2 = %0d"", i); + if (i !== 8) failed = 1; + + for (i = 0; i < 16; i++) begin + index = i[3:0]; + array[0][index] = {4\'d0, index}; + array[1][index] = {4\'d1, index}; + end + $display(""%h"", array); + if (array !== 256\'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f) + failed = 1; + for (i = 0; i < 16; i++) begin + index = i[3:0]; + $display(""%h : %h %h"", index, array[0][index], array[1][index]); + if (array[0][index] !== {4\'d0, index}) failed = 1; + if (array[1][index] !== {4\'d1, index}) failed = 1; + end + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"// Use the default timescale. +module top; + initial begin + $printtimescale(top); + $printtimescale(other); + $printtimescale(other2); + end +endmodule + +`timescale 1ms/1ms + +// Use the given timescale. +module other; +endmodule + +`resetall + +// Use the default timescale. +module other2; +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate 3.1.2E always reg_lvalue <= # (mintypmax_expression) constant ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + begin + # 3; /* Wait till here to verify didn\'t see 2ns delay! */ + if(value1 !== 4\'hx) +\t$display(""FAILED - always reg_lvalue <= # (mintypmax_expression) constant \ +""); + #12 ; + if(value1 != 4\'h5) +\t$display(""FAILED - always reg_lvalue <= # (mintypmax_expression) constant \ +""); + else + begin + $display(""PASSED\ +""); + $finish ; + end + end + +always value1 <= # (2:10:17) 4\'h5 ; + +endmodule +" +"/* + * What matters here is the size of the display, which should reflect + * the size of 20, which is written with an _ character. Weird, but + * legal. + */ + +module underscore_in_size; +initial +\t$display ( ""%d %d %d %d"", 2_0\'b0, 2_0\'d0, 2_0\'o0, 2_0\'h0 ); +endmodule +" +"// Released under GPL2.0 +// (c) 2002 Tom Verbeure + +module main; + +\tinteger myInt; +\treg [39:0] myReg40; +\treg [0:39] myReg40r; +\treg [0:38] myReg39r; +\treg [13:0] myReg14; +\treg [7:0] myReg8; +\treg [31:0] myReg32; + +\tinitial begin +\t\t$display(""============================ myReg14 = -10""); +\t\tmyReg14 = -10; + +\t\t$display("">|16374|""); +\t\t$display(""*|%d|"", myReg14); +\t\t$display(""*|%0d|"", myReg14); +\t\t$display(""*|"",myReg14,""|""); + +\t\t$display(""============================ myReg14 = 65""); +\t\tmyReg14 = 65; + +\t\t$display("">| 65|""); +\t\t$display(""*|%d|"", myReg14); +\t\t$display(""*|"",myReg14,""|""); +\t\t$display("">|65|""); +\t\t$display(""*|%0d|"", myReg14); + +\t\t$display("">|0041|""); +\t\t$display(""*|%h|"", myReg14); +\t\t$display("">|41|""); +\t\t$display(""*|%0h|"", myReg14); + +\t\t$display("">|00101|""); +\t\t$display(""*|%o|"", myReg14); +\t\t$display("">|101|""); +\t\t$display(""*|%0o|"", myReg14); + +\t\t$display("">|00000001000001|""); +\t\t$display(""*|%b|"", myReg14); +\t\t$display("">|1000001|""); +\t\t$display(""*|%0b|"", myReg14); + +\t\t$display("">| A|""); +\t\t$display(""*|%s|"", myReg14); +\t\t$display("">|A|""); +\t\t$display(""*|%0s|"", myReg14); + +\t\t$display(""============================ myInt = -10""); +\t\tmyInt = -10; +\t\t$display("">| -10|""); +\t\t$display(""*|%d|"", myInt); +\t\t$display(""*|"",myInt,""|""); +\t\t$display("">|-10|""); +\t\t$display(""*|%0d|"", myInt); + +\t\t$display("">|fffffff6|""); +\t\t$display(""*|%h|"", myInt); +\t\t$display(""*|%0h|"", myInt); + +\t\t$display("">|37777777766|""); +\t\t$display(""*|%o|"", myInt); +\t\t$display(""*|%0o|"", myInt); + +\t\t$display("">|11111111111111111111111111110110|""); +\t\t$display(""*|%b|"", myInt); +\t\t$display(""*|%0b|"", myInt); + +\t\t$display(""============================ myReg32 = -10""); +\t\tmyReg32 = -10; +\t\t$display("">|4294967286|""); +\t\t$display(""*|%d|"", myReg32); +\t\t$display(""*|%0d|"", myReg32); +\t\t$display(""*|"",myReg32,""|""); + +\t\t$display("">|fffffff6|""); +\t\t$display(""*|%h|"", myReg32); +\t\t$display(""*|%0h|"", myReg32); + +\t\t$display("">|37777777766|""); +\t\t$display(""*|%o|"", myReg32); +\t\t$display(""*|%0o|"", myReg32); + +\t\t$display(""============================ myInt = 65""); +\t\tmyInt = 65; +\t\t$display("">| 65|""); +\t\t$display(""*|%d|"", myInt); +\t\t$display(""*|"",myInt,""|""); +\t\t$display("">|65|""); +\t\t$display(""*|%0d|"", myInt); + +\t\t$display("">|00000041|""); +\t\t$display(""*|%h|"", myInt); +\t\t$display("">|41|""); +\t\t$display(""*|%0h|"", myInt); + +\t\t$display("">|00000000101|""); +\t\t$display(""*|%o|"", myInt); +\t\t$display("">|101|""); +\t\t$display(""*|%0o|"", myInt); + +\t\t$display("">|00000000000000000000000001000001|""); +\t\t$display(""*|%b|"", myInt); +\t\t$display("">|1000001|""); +\t\t$display(""*|%0b|"", myInt); + +\t\t$display(""*| A|""); +\t\t$display("">|%s|"", myInt); +\t\t$display(""*|A|""); +\t\t$display("">|%0s|"", myInt); + +\t\t$display(""============================ Print \\"" A\\""""); +\t\t$display(""*| A|""); +\t\t$display("">|%s|"", "" A""); +\t\t$display("">|%0s|"", "" A""); + +\t\t$display(""============================ Print $time""); +\t\t$display(""*| 0|""); +\t\t$display("">|%t|"", $time); +\t\t$display(""*|0|""); +\t\t$display("">|%0t|"", $time); + +\tend +endmodule +" +"module test; + wire [5:0] a; + reg [3:0] b; + assign a[1:0] = {{2\'b0},b}; + + initial begin + b = 4\'b0110; + #1 if (a !== 6\'bzzzz10) begin +\t $display(""FAILED -- a=%b"", a); +\t $finish; + end + $display(""PASSED""); + end + +endmodule +" +"module top(); + +reg CLK; +reg [3:0] D; +reg EN; +reg [3:0] Q; + +always @(posedge CLK) begin + if (EN) begin + Q[1] <= D[1]; + Q[2] <= ~D[2]; + Q[3] <= D[3]; + end +end + +reg failed; + +(* ivl_synthesis_off *) +initial begin + failed = 0; + $monitor(""%b %b %b %b"", CLK, EN, D, Q); + CLK = 0; + EN = 0; + D = 4\'b0000; + #1 CLK = 1; + #1 CLK = 0; + if (Q !== 4\'bxxxx) failed = 1; + EN = 1; + #1 CLK = 1; + #1 CLK = 0; + if (Q !== 4\'b010x) failed = 1; + EN = 0; + D = 4\'b1111; + #1 CLK = 1; + #1 CLK = 0; + if (Q !== 4\'b010x) failed = 1; + EN = 1; + #1 CLK = 1; + #1 CLK = 0; + if (Q !== 4\'b101x) failed = 1; + #1; + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"//--------------------------------------------------------------------------- +// +//--------------------------------------------------------------------------- + module xor_try; + + (* ivl_do_not_elide *) reg unused; + initial $sn; + endmodule + +" +"module check (input unsigned [0:22] a, b, c); + wire [0:22] int_AB; + + assign int_AB = a & b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB != c) begin + $display(""ERROR""); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [0:22] A, B); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; B= 0; + for (i=0; i + +module main ; + +reg [3:0] value1 ; +event event_ident ; + +initial +begin + # 5 -> event_ident ; +end + +initial + begin + if(value1 !== 4\'bxxxx) +\t$display(""FAILED - always reg_lvalue = @ event_identifier constant\ +""); + #10 ; + if(value1 != 4\'h5) +\t$display(""FAILED - always reg_lvalue = @ event_identifier constant\ +""); + else + begin + $display(""PASSED\ +""); + $finish ; + end + end + +always value1 = @ event_ident 4\'h5; + + +endmodule +" +"module test; + reg [4:0] i; + reg [7:0] j, k, l; + + initial + main; + task main; + begin +\t i = 5\'h14; +\t j = $signed(i); // works +\t k = $signed(5\'h14); // doesn\'t work +\t l = 5\'sh14; // works + +\t $display(""i, j, k, l: \'%b\', \'%b\', \'%b\', \'%b\'"", i, j, k, l); + end + endtask +endmodule +" +"/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test was inspired by PR#539. We check that the calculated bit + * select of a net in a continuous assignment gets bits in the right + * order and position. The trick here is that the bits are numbered + * from MSB to LSB. + */ + +module main; + + reg [0:63] target0 = 64\'h0040200000000000; + reg [1:64] target1 = 64\'h0040200000000000; + reg [6:0] idx; + + wire mux0 = target0[idx]; + wire mux1 = target1[idx+1]; + + initial begin + $display( ""Using constant indices:"" ); + $display( "" %b=v[ 9]"", target0[ 9] ); + if (target0[9] !== 1\'b1) begin +\t $display(""FAILED -- target0[9] != 1""); +\t $finish; + end + + $display( "" %b=v[18]"", target0[18] ); + if (target0[18] !== 1\'b1) begin +\t $display(""FAILED -- target0[18] != 1""); +\t $finish; + end + + $display( "" %b=v[45]"", target0[45] ); + if (target0[45] !== 1\'b0) begin +\t $display(""FAILED -- target0[45] != 0""); +\t $finish; + end + + $display( "" %b=v[54]"", target0[54] ); + if (target0[54] !== 1\'b0) begin +\t $display(""FAILED -- target0[54] != 0""); +\t $finish; + end + + $display( ""Using calcuated indices:"" ); + for (idx = 0 ; idx < 64 ; idx = idx + 1) begin +\t #1 $display(""target0[%2d]=%b, mux0=%b"", idx, target0[idx], mux0); +\t $display(""target1[%2d]=%b, mux1=%b"", idx+1, target1[idx+1], mux1); + +\t if (target0[idx] !== mux0) begin +\t $display(""FAILED -- target0[idx] != mux0""); +\t $finish; +\t end + +\t if (target1[idx+1] !== mux1) begin +\t $display(""FAILED -- target1[idx+1] != mux1""); +\t $finish; +\t end + end + + $display(""PASSED""); + end + +endmodule // main +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate and gate vector +// + + +module main; + +reg globvar; + +wire [15:0] out; +reg [15:0] a,b, rslt; +reg error; + +// The test gate goes HERE! + +and foo [15:0] (out,a,b); + +always @(a or b) + rslt = a & b; + +initial + begin // { + error = 0; + # 1; + for(a = 16\'h1; a != 16\'hffff; a = (a << 1) | 1) + begin // { + for(b = 16\'hffff; b !== 16\'h0; b = b >> 1) + begin // { + #1 ; + if(out !== rslt) + begin // { + $display(""FAILED - GA And a=%h,b=%h,expct=%h - rcvd=%h"", + a,b,rslt,out); + error = 1; + end // } + end // } + end // } + if( error == 0) + $display(""PASSED""); + end // } +endmodule // main +" +"// Regression test for GitHub issue 22 + +module bug(); + +reg [1:0] a; +reg [2:0] b; +wire [3:0] y; + +assign y = {a >> {22{b}}, a << (0 <<< b)}; + +initial begin + b = 7; + a = 3; + #1 $display(""%b"", y); + if (y === 4\'b0011) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"`timescale 1us/100ns + +module top; + reg pass = 1\'b1; + + real ra = 1.0; + wire real rufunc; + + assign #10 rufunc = rl_func(ra); + + initial begin + #1 if (rufunc == 2.0) begin + pass = 1\'b0; + $display(""Real: user function value (%f) not delayed."", rufunc); + end + #8 if (rufunc == 2.0) begin + pass = 1\'b0; + $display(""Real: user function value (%f) not delayed."", rufunc); + end + #2; + if (rufunc != 2.0) begin + pass = 1\'b0; + $display(""Real: user function value not delayed correctly.""); + end + if (pass) $display(""PASSED""); + end + + function real rl_func; + input real in; + rl_func = in * 2.0; + endfunction + +endmodule +" +"module t; + final $display(""Final in %m""); +endmodule + +module t2; + final $display(""Final in %m""); +endmodule +" +"module test(); + +function [31:0] pre_inc(input [31:0] x); +begin + ++x[23:8]; + pre_inc = x; +end +endfunction + +function [31:0] pre_dec(input [31:0] x); +begin + --x[23:8]; + pre_dec = x; +end +endfunction + +function [31:0] post_inc(input [31:0] x); +begin + x[23:8]++; + post_inc = x; +end +endfunction + +function [31:0] post_dec(input [31:0] x); +begin + x[23:8]--; + post_dec = x; +end +endfunction + +localparam pre_inc_5 = pre_inc({8\'h55, 16\'d5, 8\'haa}); +localparam pre_dec_5 = pre_dec({8\'h55, 16\'d5, 8\'haa}); + +localparam post_inc_5 = post_inc({8\'h55, 16\'d5, 8\'haa}); +localparam post_dec_5 = post_dec({8\'h55, 16\'d5, 8\'haa}); + +function [31:0] add2(input [31:0] x); +begin + x[23:8] += 2; + add2 = x; +end +endfunction + +function [31:0] sub2(input [31:0] x); +begin + x[23:8] -= 2; + sub2 = x; +end +endfunction + +function [31:0] mul2(input [31:0] x); +begin + x[23:8] *= 2; + mul2 = x; +end +endfunction + +function [31:0] div2(input [31:0] x); +begin + x[23:8] /= 2; + div2 = x; +end +endfunction + +function [31:0] mod2(input [31:0] x); +begin + x[23:8] %= 2; + mod2 = x; +end +endfunction + +function [31:0] and6(input [31:0] x); +begin + x[23:8] &= 16\'h6666; + and6 = x; +end +endfunction + +function [31:0] or6(input [31:0] x); +begin + x[23:8] |= 16\'h6666; + or6 = x; +end +endfunction + +function [31:0] xor6(input [31:0] x); +begin + x[23:8] ^= 16\'h6666; + xor6 = x; +end +endfunction + +function [31:0] lsl2(input [31:0] x); +begin + x[23:8] <<= 2; + lsl2 = x; +end +endfunction + +function [31:0] lsr2(input [31:0] x); +begin + x[23:8] >>= 2; + lsr2 = x; +end +endfunction + +function [31:0] asl2(input [31:0] x); +begin + x[23:8] <<<= 2; + asl2 = x; +end +endfunction + +function [31:0] asr2(input [31:0] x); +begin + x[23:8] >>>= 2; + asr2 = x; +end +endfunction + +localparam add2_5 = add2({8\'h55, 16\'d5, 8\'haa}); +localparam sub2_5 = sub2({8\'h55, 16\'d5, 8\'haa}); +localparam mul2_5 = mul2({8\'h55, 16\'d5, 8\'haa}); +localparam div2_5 = div2({8\'h55, 16\'d5, 8\'haa}); +localparam mod2_5 = mod2({8\'h55, 16\'d5, 8\'haa}); + +localparam and6_f = and6(32\'h55ffffaa); +localparam or6_0 = or6(32\'h550000aa); +localparam xor6_f = xor6(32\'h55ffffaa); + +localparam lsl2_p25 = lsl2({8\'h55, 16\'sd25, 8\'haa}); +localparam lsr2_m25 = lsr2({8\'h55, -16\'sd25, 8\'haa}); +localparam asl2_m25 = asl2({8\'h55, -16\'sd25, 8\'haa}); +localparam asr2_m25 = asr2({8\'h55, -16\'sd25, 8\'haa}); + +function [31:0] add3(input [31:0] x); +begin + add3 = x; + add3[23:8] += 3; +end +endfunction + +function [31:0] sub3(input [31:0] x); +begin + sub3 = x; + sub3[23:8] -= 3; +end +endfunction + +function [31:0] mul3(input [31:0] x); +begin + mul3 = x; + mul3[23:8] *= 3; +end +endfunction + +function [31:0] div3(input [31:0] x); +begin + div3 = x; + div3[23:8] /= 3; +end +endfunction + +function [31:0] mod3(input [31:0] x); +begin + mod3 = x; + mod3[23:8] %= 3; +end +endfunction + +function [31:0] and9(input [31:0] x); +begin + and9 = x; + and9[23:8] &= 16\'h9999; +end +endfunction + +function [31:0] or9(input [31:0] x); +begin + or9 = x; + or9[23:8] |= 16\'h9999; +end +endfunction + +function [31:0] xor9(input [31:0] x); +begin + xor9 = x; + xor9[23:8] ^= 16\'h9999; +end +endfunction + +function [31:0] lsl3(input [31:0] x); +begin + lsl3 = x; + lsl3[23:8] <<= 3; +end +endfunction + +function [31:0] lsr3(input [31:0] x); +begin + lsr3 = x; + lsr3[23:8] >>= 3; +end +endfunction + +function [31:0] asl3(input [31:0] x); +begin + asl3 = x; + asl3[23:8] <<<= 3; +end +endfunction + +function [31:0] asr3(input [31:0] x); +begin + asr3 = x; + asr3[23:8] >>>= 3; +end +endfunction + +localparam add3_5 = add3({8\'h55, 16\'d5, 8\'haa}); +localparam sub3_5 = sub3({8\'h55, 16\'d5, 8\'haa}); +localparam mul3_5 = mul3({8\'h55, 16\'d5, 8\'haa}); +localparam div3_5 = div3({8\'h55, 16\'d5, 8\'haa}); +localparam mod3_5 = mod3({8\'h55, 16\'d5, 8\'haa}); + +localparam and9_f = and9(32\'h55ffffaa); +localparam or9_0 = or9(32\'h550000aa); +localparam xor9_f = xor9(32\'h55ffffaa); + +localparam lsl3_p25 = lsl3({8\'h55, 16\'sd25, 8\'haa}); +localparam lsr3_m25 = lsr3({8\'h55, -16\'sd25, 8\'haa}); +localparam asl3_m25 = asl3({8\'h55, -16\'sd25, 8\'haa}); +localparam asr3_m25 = asr3({8\'h55, -16\'sd25, 8\'haa}); + +reg failed = 0; + +initial begin + $display(""pre_inc_5 = %0h"", pre_inc_5); + if (pre_inc_5 !== pre_inc({8\'h55, 16\'d5, 8\'haa})) failed = 1; + if (pre_inc_5 !== 32\'h550006aa) failed = 1; + + $display(""pre_dec_5 = %0h"", pre_dec_5); + if (pre_dec_5 !== pre_dec({8\'h55, 16\'d5, 8\'haa})) failed = 1; + if (pre_dec_5 !== 32\'h550004aa) failed = 1; + + $display(""post_inc_5 = %0h"", post_inc_5); + if (post_inc_5 !== post_inc({8\'h55, 16\'d5, 8\'haa})) failed = 1; + if (post_inc_5 !== 32\'h550006aa) failed = 1; + + $display(""post_dec_5 = %0h"", post_dec_5); + if (post_dec_5 !== post_dec({8\'h55, 16\'d5, 8\'haa})) failed = 1; + if (post_dec_5 !== 32\'h550004aa) failed = 1; + + $display(""add2_5 = %0h"", add2_5); + if (add2_5 !== add2({8\'h55, 16\'d5, 8\'haa})) failed = 1; + if (add2_5 !== 32\'h550007aa) failed = 1; + + $display(""sub2_5 = %0h"", sub2_5); + if (sub2_5 !== sub2({8\'h55, 16\'d5, 8\'haa})) failed = 1; + if (sub2_5 !== 32\'h550003aa) failed = 1; + + $display(""mul2_5 = %0h"", mul2_5); + if (mul2_5 !== mul2({8\'h55, 16\'d5, 8\'haa})) failed = 1; + if (mul2_5 !== 32\'h55000aaa) failed = 1; + + $display(""div2_5 = %0h"", div2_5); + if (div2_5 !== div2({8\'h55, 16\'d5, 8\'haa})) failed = 1; + if (div2_5 !== 32\'h550002aa) failed = 1; + + $display(""mod2_5 = %0h"", mod2_5); + if (mod2_5 !== mod2({8\'h55, 16\'d5, 8\'haa})) failed = 1; + if (mod2_5 !== 32\'h550001aa) failed = 1; + + $display(""and6_f = %h"", and6_f); + if (and6_f !== and6(32\'h55ffffaa)) failed = 1; + if (and6_f !== 32\'h556666aa) failed = 1; + + $display("" or6_0 = %h"", or6_0); + if (or6_0 !== or6(32\'h550000aa)) failed = 1; + if (or6_0 !== 32\'h556666aa) failed = 1; + + $display(""xor6_f = %h"", xor6_f); + if (xor6_f !== xor6(32\'h55ffffaa)) failed = 1; + if (xor6_f !== 32\'h559999aa) failed = 1; + + $display(""lsl2_p25 = %0h"", lsl2_p25); + if (lsl2_p25 !== lsl2({8\'h55, 16\'sd25, 8\'haa})) failed = 1; + if (lsl2_p25 !== 32\'h550064aa) failed = 1; + + $display(""lsr2_m25 = %0h"", lsr2_m25); + if (lsr2_m25 !== lsr2({8\'h55, -16\'sd25, 8\'haa})) failed = 1; + if (lsr2_m25 !== 32\'h553ff9aa) failed = 1; + + $display(""asl2_m25 = %0h"", asl2_m25); + if (asl2_m25 !== asl2({8\'h55, -16\'sd25, 8\'haa})) failed = 1; + if (asl2_m25 !== 32\'h55ff9caa) failed = 1; + + $display(""asr2_m25 = %0h"", asr2_m25); + if (asr2_m25 !== asr2({8\'h55, -16\'sd25, 8\'haa})) failed = 1; + if (asr2_m25 !== 32\'h553ff9aa) failed = 1; + + $display(""add3_5 = %0h"", add3_5); + if (add3_5 !== add3({8\'h55, 16\'d5, 8\'haa})) failed = 1; + if (add3_5 !== 32\'h550008aa) failed = 1; + + $display(""sub3_5 = %0h"", sub3_5); + if (sub3_5 !== sub3({8\'h55, 16\'d5, 8\'haa})) failed = 1; + if (sub3_5 !== 32\'h550002aa) failed = 1; + + $display(""mul3_5 = %0h"", mul3_5); + if (mul3_5 !== mul3({8\'h55, 16\'d5, 8\'haa})) failed = 1; + if (mul3_5 !== 32\'h55000faa) failed = 1; + + $display(""div3_5 = %0h"", div3_5); + if (div3_5 !== div3({8\'h55, 16\'d5, 8\'haa})) failed = 1; + if (div3_5 !== 32\'h550001aa) failed = 1; + + $display(""mod3_5 = %0h"", mod3_5); + if (mod3_5 !== mod3({8\'h55, 16\'d5, 8\'haa})) failed = 1; + if (mod3_5 !== 32\'h550002aa) failed = 1; + + $display(""and9_f = %h"", and9_f); + if (and9_f !== and9(32\'h55ffffaa)) failed = 1; + if (and9_f !== 32\'h559999aa) failed = 1; + + $display("" or9_0 = %h"", or9_0); + if (or9_0 !== or9(32\'h550000aa)) failed = 1; + if (or9_0 !== 32\'h559999aa) failed = 1; + + $display(""xor9_f = %h"", xor9_f); + if (xor9_f !== xor9(32\'h55ffffaa)) failed = 1; + if (xor9_f !== 32\'h556666aa) failed = 1; + + $display(""lsl3_p25 = %0h"", lsl3_p25); + if (lsl3_p25 !== lsl3({8\'h55, 16\'sd25, 8\'haa})) failed = 1; + if (lsl3_p25 !== 32\'h5500c8aa) failed = 1; + + $display(""lsr3_m25 = %0h"", lsr3_m25); + if (lsr3_m25 !== lsr3({8\'h55, -16\'sd25, 8\'haa})) failed = 1; + if (lsr3_m25 !== 32\'h551ffcaa) failed = 1; + + $display(""asl3_m25 = %0h"", asl3_m25); + if (asl3_m25 !== asl3({8\'h55, -16\'sd25, 8\'haa})) failed = 1; + if (asl3_m25 !== 32\'h55ff38aa) failed = 1; + + $display(""asr3_m25 = %0h"", asr3_m25); + if (asr3_m25 !== asr3({8\'h55, -16\'sd25, 8\'haa})) failed = 1; + if (asr3_m25 !== 32\'h551ffcaa) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"// Check non-constant port default value is rejected +// in constant context. + +module test(); + +integer a; +integer b; + +function integer k(integer i, integer j = a+b); + k = i + j; +endfunction + +localparam integer result = k(3); + +endmodule +" +"module top; + initial fork : named_begin + $display(""FAILED""); + join : wrong_name +endmodule +" +"// Check behaviour with out-of-range and undefined array indices +// on LHS of blocking procedural assignment. + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + +reg array1[2:1]; +reg array2[1:0]; + +`ifndef VLOG95 +real array3[2:1]; +real array4[1:0]; +`endif + +integer index; + +reg failed; + +initial begin + failed = 0; + + array1[1] = 1\'b0; + array1[2] = 1\'b0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array1[0] = 1\'b1; // Constant out of bounds select may be an error +`endif + $display(""array = %b %b"", array1[2], array1[1]); + if ((array1[1] !== 1\'b0) || (array1[2] !== 1\'b0)) failed = 1; + + array1[1] = 1\'b0; + array1[2] = 1\'b0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array1[3] = 1\'b1; // Constant out of bounds select may be an error +`endif + $display(""array = %b %b"", array1[2], array1[1]); + if ((array1[1] !== 1\'b0) || (array1[2] !== 1\'b0)) failed = 1; + + array2[0] = 1\'b0; + array2[1] = 1\'b0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array2[\'bx] = 1\'b1; // Constant undefined out of bounds select may be an error +`endif + $display(""array = %b %b"", array2[1], array2[0]); + if ((array2[0] !== 1\'b0) || (array2[1] !== 1\'b0)) failed = 1; + + index = 0; + array1[1] = 1\'b0; + array1[2] = 1\'b0; + array1[index] = 1\'b1; + $display(""array = %b %b"", array1[2], array1[1]); + if ((array1[1] !== 1\'b0) || (array1[2] !== 1\'b0)) failed = 1; + + index = 3; + array1[1] = 1\'b0; + array1[2] = 1\'b0; + array1[index] = 1\'b1; + $display(""array = %b %b"", array1[2], array1[1]); + if ((array1[1] !== 1\'b0) || (array1[2] !== 1\'b0)) failed = 1; + + index = \'bx; + array2[0] = 1\'b0; + array2[1] = 1\'b0; + array2[index] = 1\'b1; + $display(""array = %b %b"", array2[1], array2[0]); + if ((array2[0] !== 1\'b0) || (array2[1] !== 1\'b0)) failed = 1; + +`ifndef VLOG95 + array3[1] = 0.0; + array3[2] = 0.0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array3[0] = 1.0; // Constant out of bounds select may be an error +`endif + $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + + array3[1] = 0.0; + array3[2] = 0.0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array3[3] = 1.0; // Constant out of bounds select may be an error +`endif + $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + + array4[0] = 0.0; + array4[1] = 0.0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array4[\'bx] = 1.0; // Constant undefined out of bounds select may be an error +`endif + $display(""array = %0g %0g"", array4[1], array4[0]); + if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1; + + index = 0; + array3[1] = 0.0; + array3[2] = 0.0; + array3[index] = 1.0; + $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + + index = 3; + array3[1] = 0.0; + array3[2] = 0.0; + array3[index] = 1.0; + $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + + index = \'bx; + array4[0] = 0.0; + array4[1] = 0.0; + array4[index] = 1.0; + $display(""array = %0g %0g"", array4[1], array4[0]); + if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1; +`endif + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module bug; + +wire [7:0] r1; +wire [7:0] r2; +wire [7:0] r3; +wire [7:0] r4; +wire [7:0] r5; +wire [7:0] r6; +wire [7:0] r7; + +wire [7:0] r; + +function [7:0] fn; + +input [7:0] a; +input [7:0] b; +input [7:0] c; +input [7:0] d; +input [7:0] e; +input [7:0] f; +input [7:0] g; +input [7:0] h; + +begin + fn = a + b + c + d + e + f + g + h; +end + +endfunction + +assign {r1, r2, r3, r4, r5, r6, r7} = 56\'d257; + +assign r = fn(r1, r2, r3, r4, r5, r6, r7, 8\'d0); + +initial begin + #1 $display(""r=%0d"", r); + if (r !== 8\'d2) begin + $display(""FAILED""); + $finish; + end + $display(""PASSED""); +end + +endmodule +" +"module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4\'d2; + +assign value2 = value1 | 8\'d1; + +initial begin + #2 $display(""%b %b"", value1, value2); + if (value2 === 8\'bxxxx0011) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Bit select of a net (a wire) using the index of a for loop. + */ + +module main; + + // Make a vector of bits, an array of functors in practice, and + // create a net that hooks to that array backwards. + reg [5:1] vect = 5\'b10100; + wire [5:1] tmp = { vect[1], vect[2], vect[3], vect[4], vect[5] }; + + reg [2:0] idx; + initial begin + #1 $display(""vect=%b, tmp=%b"", vect, tmp); + + for (idx = 1 ; idx <= 5 ; idx = idx + 1) begin +\t $display(""idx=%d: vect=%b, tmp=%b"", idx, vect[idx], tmp[idx]); +\t if (tmp[idx] !== vect[6-idx]) begin +\t $display(""FAILED""); +\t $finish; +\t end + end + + $display(""PASSED""); + end + +endmodule // main +" +"module pr0; + reg r; + initial r = ( 1\'b1 ? 1\'b0 : 1\'b0) ? 1\'b0 : 1\'b0; + initial begin + #1 if (r !== 1\'b0) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""PASSED""); + end +endmodule +" +"module test(); + +wire [3:0] foo; +wire [5:0] bar; + +assign foo[2:1] = 2\'b10; +assign bar[4:1] = foo; + +initial begin + if (bar === 6\'bzz10zz) + $display(""PASSED""); + else + $display(""PASSED""); +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate casez/endcase w/ default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 ) + casez (val1) + 5\'b0000z: result = 0; + 5\'b001z0: result = 1 ; + 5\'b01zz0: result = 2; + default: result = 4; + endcase + +initial + begin + error = 0; + + val1 = 5\'b0000z ; + if(result !=0) + begin + $display(""FAILED casez 3.10D - case (expr) lab1: ""); + error = 1; + end + + val1 = 5\'b001z0; + if(result !=1) + begin + $display(""FAILED casez 3.10D - case (expr) lab2: ""); + error = 1; + end + + val1 = 5\'b1zzzz;\t// Should get no-action - expr = 3\'b011 + if(result !=4) + begin + $display(""FAILED casez 3.10D - case (expr) lab1: ""); + error = 1; + end + + if(error == 0) + $display(""PASSED""); + end + +endmodule // main +" +"`begin_keywords ""1364-2005"" +module top; + reg [31:0] var; + + initial begin + $monitor(var); + var = 0; + repeat (60) begin + #1 var = $urandom_range(0,16); + end + end +endmodule +`end_keywords +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - always block with @(value) and (posedge OR negedge) +// +// D: New test used to validate always @(value), and +// D: always @(val1 or val2), and always @(posedge val1 or negedge val2) +// D: statements. +// +// + +module main (); +reg working; +reg reset; +reg clock ; +reg test_var; + +initial\t// Used to generate timing of events + begin + clock = 0; + reset = 0; + + // Nothing sent yet... + + #5 ; + $display(""time=%d, c=%b, r=%b, reg=%b"",$time,clock,reset,test_var); + reset = 1;\t// 5 ns + + #5 ; + $display(""time=%d, c=%b, r=%b, reg=%b"",$time,clock,reset,test_var); + reset = 0;\t// 10ns + + #5 ; + $display(""time=%d, c=%b, r=%b, reg=%b"",$time,clock,reset,test_var); + clock = 1;\t// 15 ns + + #5 ; + $display(""time=%d, c=%b, r=%b, reg=%b"",$time,clock,reset,test_var); + clock = 0; // 20 ns + + #5 ;\t// 25 ns + $display(""time=%d, c=%b, r=%b, reg=%b"",$time,clock,reset,test_var); + end + +// +// This is the statement being verified... +// +// This LOOKS like a race between the posedge and the reset value +// but is a standard method for reseting f/f\'s. +// + +always @(posedge clock or posedge reset) + if(reset) + test_var = 0; + else + test_var = ~test_var; + +initial // This is the validation block + begin + # 3;\t// 3 ns Check always @(val) + if(test_var != 1\'bx) + begin + $display(""FAILED - initial condition of reg variable not x\ +""); + $finish ; + end + # 5;\t// 8 ns Check posedge of always @(posedge val or negedge) + if(test_var == 1\'bx) + begin + $display(""FAILED - Reset didn\'t reset var \ +""); + $finish ; + end + if(test_var == 1\'b1) + begin + $display(""FAILED - Reset set it to 1?? \ +""); + $finish ; + end + + # 5;\t// 12 ns + if(test_var == 1\'bx) + begin + $display(""FAILED - Reset didn\'t reset var \ +""); + $finish ; + end + if(test_var == 1\'b1) + begin + $display(""FAILED - Reset set it to 1?? \ +""); + $finish ; + end + # 5;\t// 17 ns - have received the clock by now + if(test_var == 1\'bx) + begin + $display(""FAILED - The clock caused an x??\ +""); + $finish ; + end + if(test_var == 1\'b0) + begin + $display(""FAILED - The clock didn\'t have any effect?? \ +""); + $finish ; + end + # 30; + + $display(""PASSED\ +""); + $finish; + end + +endmodule +" +"/* + * Copyright (c) 1998 Purdea Andrei (purdeaandrei@yahoo.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This demonstrates proper handling of leading zeroes, and the %0b format. + */ +module main(); + +initial + begin + $display(""|%b|"", 10\'b11); + $display(""|%0b|"", 10\'b11); + $display(""|%b|"", 10\'b0); + $display(""|%0b|"", 10\'b0); + $finish(0); + end + +endmodule +" +"/* + * blocksyn1.v + * This tests synthesis where statements in a block override previous + * statements in a block and also uses other previous statements in the + * block. Note in this example that the flag assignment is completely + * overruled by the conditional that is directly after it. + */ +module main; + + reg [1:0] out; + reg\t flag; + reg [1:0] sel; + + (* ivl_synthesis_on, ivl_combinational *) + always @* + begin +\tout = 2\'b00; +\tcase (sel) +\t 2\'b00: out = 2\'b11; +\t 2\'b01: out = 2\'b10; +\t 2\'b10: out = 2\'b01; +\tendcase // case(sel) + +\t// This flag is overridded by the true clause, so the +\t// synthesizer should move the first assignment to the +\t// else clause of the if. +\tflag = 1\'b0; +\tif (out == 2\'b00) +\t flag = 1\'b1; + end + + reg [2:0] idx; + reg\t test; + + (* ivl_synthesis_off *) + initial begin + for (idx = 0 ; idx < 7 ; idx = idx + 1) begin +\t sel = idx[1:0]; +\t #1 if (out !== ~sel) begin +\t $display(""FAILED -- sel=%b, out=%b, flag=%b"", sel, out, flag); +\t $finish; +\t end + +\t test = (out == 2\'b00)? 1\'b1 : 1\'b0; + +\t if (test !== flag) begin +\t $display(""FAILED -- test=%b, sel=%b, out=%b, flag=%b"", +\t\t test, sel, out, flag); +\t $finish; +\t end + end // for (idx = 0 ; idx < 7 ; idx = idx + 1) + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +" +/* + * This is a post-wynthesis test for the blif01a.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif01a.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter WID = 4; + reg [WID-1:0] A, B; + wire [WID:0] Q; + + addN usum(.\\A[3] (A[3]), .\\A[2] (A[2]), .\\A[1] (A[1]), .\\A[0] (A[0]), +\t .\\B[3] (B[3]), .\\B[2] (B[2]), .\\B[1] (B[1]), .\\B[0] (B[0]), +\t .\\Q[4] (Q[4]), .\\Q[3] (Q[3]), .\\Q[2] (Q[2]), .\\Q[1] (Q[1]), .\\Q[0] (Q[0])); + + int\t\t adx; + int\t\t bdx; + initial begin + for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin +\t for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin +\t A <= adx[WID-1:0]; +\t B <= bdx[WID-1:0]; +\t #1 if (Q !== (adx+bdx)) begin +\t $display(""FAILED -- A=%b, B=%b, Q=%b"", A, B, Q); +\t $finish; +\t end +\t end + end + $display(""PASSED""); + end + +endmodule // main +" +"/* + * This program tests that enumeration value first/last/num + * methods work properly. + */ +module main; + + enum byte { RED, ORANGE, YELLOW, GREEN, BLUE, VIOLET, +\t BLACK = 10, WHITE = \'d11 +\t} color1; + + + initial begin + color1 = RED; + $display(""color1.first == %0d"", color1.first); + $display(""color1.last == %0d"", color1.last); + $display(""color1.num == %0d"", color1.num); + + if (color1.first !== RED) begin +\t $display(""FAILED""); +\t $finish; + end + + if (color1.last !== WHITE) begin +\t $display(""FAILED""); +\t $finish; + end + + if (color1.num !== 8) begin +\t $display(""FAILED""); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate variable left shift in always block + + +module main; + +reg globvar; + +reg [7:0] var1,var2,var3; +reg error; +wire [7:0] value; +assign value = var1 << var2; + +initial + begin + error = 0; + #1 ; + var1 = 8\'h1; + var2 = 8\'h0; + #2; + if(value !== 8\'h1) + begin + error = 1; +\t$display (""FAILED - 1 << 0 is %h"",value); + end + #1 ; + var1 = 8\'h1; + var2 = 8\'h1; + #2; + if(value !== 8\'h2) + begin + error = 1; +\t$display (""FAILED - 1 << 1 is %h"",value); + end + #1 ; + var1 = 8\'h1; + var2 = 8\'h2; + #2; + if(value !== 8\'h4) + begin + error = 1; +\t$display (""FAILED - 1 << 2 is %h"",value); + end + #1 ; + var1 = 8\'h1; + var2 = 8\'h3; + #2; + if(value !== 8\'h8) + begin + error = 1; +\t$display (""FAILED - 1 << 3 is %h"",value); + end + #1 ; + var1 = 8\'h1; + var2 = 8\'h4; + #2; + if(value !== 8\'h10) + begin + error = 1; +\t$display (""FAILED - 1 << 4 is %h"",value); + end + #1 ; + var1 = 8\'h1; + var2 = 8\'h5; + #2; + if(value !== 8\'h20) + begin + error = 1; +\t$display (""FAILED - 1 << 5 is %h"",value); + end + #1 ; + var1 = 8\'h1; + var2 = 8\'h6; + #2; + if(value !== 8\'h40) + begin + error = 1; +\t$display (""FAILED - 1 << 6 is %h"",value); + end + #1 ; + var1 = 8\'h1; + var2 = 8\'h7; + #2; + if(value !== 8\'h80) + begin + error = 1; +\t$display (""FAILED - 1 << 6 is %h"",value); + end + #1 ; + var1 = 8\'ha5; + var2 = 8\'h7; + #2; + if(value !== 8\'h80) + begin + error = 1; +\t$display (""FAILED - a5 << 7 is %h"",value); + end + #1 ; + var1 = 8\'ha5; + var2 = 8\'h1; + #2; + if(value !== 8\'h4a) + begin + error = 1; +\t$display (""FAILED - aa << 1 is %h"",value); + end + if(error === 0) + $display(""PASSED""); + end + +endmodule // main +" +"// Regression test for GitHub issue 7 : Undef propagation in power operator. + +module bug(); + +reg [3:0] a; +reg [3:0] y; + +reg failed = 0; + +initial begin + a = 4\'d1 / 4\'d0; + y = 4\'d2 ** a; + $display(""%b"", a); + $display(""%b"", y); + if (y !== 4\'bxxxx) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module automatic_events(); + +reg [5:1] any; + +integer k; + +initial begin + any = 5\'b00000; + #200; + for (k = 1; k <= 5; k = k + 1) begin + #10 any[k] = 1; + #10 any[k] = 0; + end +end + +task automatic report_events; + +input integer n; + +begin:task_body + reg [5:1] pos; + reg [5:1] neg; + + #n; + pos = 5\'b00000; + neg = 5\'b00000; + fork:task_threads + integer i; + integer j; + + for (i = 1; i <= 5; i = i + 1) begin + #10 neg[i] = 1; + #10 pos[i] = 1; + #10 neg[i] = 0; + #10 pos[i] = 0; + end + for (j = 1; j <= 20; j = j + 1) begin + @( any[1] or posedge pos[1] or negedge neg[1] + or any[2] or posedge pos[2] or negedge neg[2] + or any[3] or posedge pos[3] or negedge neg[3] + or any[4] or posedge pos[4] or negedge neg[4] + or any[5] or posedge pos[5] or negedge neg[5] ); + #n $display(""task %0d triggered: %b %b %b %4d"", n, any, pos, neg, $time); + end + join +end + +endtask + +initial begin + fork + report_events(1); + report_events(2); + join + $finish(0); +end + +endmodule +" +"module test(); + +reg [3:0] count; +reg carry; + +reg failed = 0; + +integer i; + +initial begin + {carry, count} = 0; + for (i = 0; i < 32; i += 1) begin + $display(""%b %b"", carry, count); + if (count !== i[3:0]) failed = 1; + if (carry !== i[4]) failed = 1; + {carry, count} += 1; + end + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module main; + + parameter WIDTH = 8; + parameter ITERATIONS = 1000; + + reg [WIDTH-1:0] src0, src1, ref_dst; + reg clk; + wire [WIDTH-1:0] dst; + + test #(.width(WIDTH)) test0 (.dst(dst), .src0(src0), .src1(src1), .clk(clk)); + + integer\t idx; + initial begin + clk = 0; + for (idx = 0 ; idx < ITERATIONS ; idx = idx+1) begin +\t src0 = $random; +\t src1 = $random; +\t ref_dst = src0 ^ src1; +\t #1 clk = 1; +\t #1 if (dst !== ref_dst) begin +\t $display(""FAILED: src0=%b, src1=%b dst=%b, ref=%b"", +\t\t src0, src1, dst, ref_dst); +\t $finish; +\t end +\t clk = 0; + end + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"// Copyright (c) 2002 Michael Ruff (mruff at chiaro.com) +//\t\t Michael Runyan (mrunyan at chiaro.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module test; + + reg [7:0]\tr_poke_1, r_poke_2, r_poke_3, r_poke_4, r_poke_5; + reg [7:0]\tr_peek_1, r_peek_2, r_peek_3, r_peek_4, r_peek_5; + + task f_copy; + begin +\t// twizzle copy +\tr_peek_1 = r_poke_2; +\tr_peek_2 = r_poke_3; +\tr_peek_3 = r_poke_4; +\tr_peek_4 = r_poke_5; +\tr_peek_5 = r_poke_1; + end + endtask + + task f_dump; +\tinteger i; + begin +\t$display(""Verilog compare r_poke <=> r_peek""); +\t$display ("" \'b_%b <=> \'b_%b%s"", +\t r_poke_1, r_peek_5, r_poke_1 !== r_peek_5 ? "" - ERROR"" : """"); +\t$display ("" \'b_%b <=> \'b_%b%s"", +\t r_poke_2, r_peek_1, r_poke_2 !== r_peek_1 ? "" - ERROR"" : """"); +\t$display ("" \'b_%b <=> \'b_%b%s"", +\t r_poke_3, r_peek_2, r_poke_3 !== r_peek_2 ? "" - ERROR"" : """"); +\t$display ("" \'b_%b <=> \'b_%b%s"", +\t r_poke_4, r_peek_3, r_poke_4 !== r_peek_3 ? "" - ERROR"" : """"); +\t$display ("" \'b_%b <=> \'b_%b%s"", +\t r_poke_5, r_peek_4, r_poke_5 !== r_peek_4 ? "" - ERROR"" : """"); + end + endtask + + initial begin +\t#0; +\t$regpoke; +\t#10; +\tf_copy; +\t#10; +\t$regpeek; +\t#10; +\tf_dump; + end + +endmodule +" +"module all; + reg pass; + + task automatic check; + input sig; + input val; + input [32*8:1] name; + begin + if (sig !== val) begin + $display(""FAILED \\""%0s\\"", expected %b, got %b"", name, val, sig); + pass = 1\'b0; + end + end + endtask + + initial begin + pass = 1\'b1; + #100; + if (pass) $display(""PASSED""); + end +endmodule + +/* Check the wire net type. */ +`default_nettype wire +module top_wire; + reg in0, in1; + + assign tmp = in0; + assign tmp = in1; + + initial begin + in0 = 1\'b0; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""wire(0,0)""); + in0 = 1\'b0; in1 = 1\'b1; + #1 all.check(tmp, 1\'bx, ""wire(0,1)""); + in0 = 1\'b0; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""wire(0,x)""); + in0 = 1\'b0; in1 = 1\'bz; + #1 all.check(tmp, 1\'b0, ""wire(0,z)""); + + in0 = 1\'b1; in1 = 1\'b0; + #1 all.check(tmp, 1\'bx, ""wire(1,0)""); + in0 = 1\'b1; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""wire(1,1)""); + in0 = 1\'b1; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""wire(1,x)""); + in0 = 1\'b1; in1 = 1\'bz; + #1 all.check(tmp, 1\'b1, ""wire(1,z)""); + + in0 = 1\'bx; in1 = 1\'b0; + #1 all.check(tmp, 1\'bx, ""wire(x,0)""); + in0 = 1\'bx; in1 = 1\'b1; + #1 all.check(tmp, 1\'bx, ""wire(x,1)""); + in0 = 1\'bx; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""wire(x,x)""); + in0 = 1\'bx; in1 = 1\'bz; + #1 all.check(tmp, 1\'bx, ""wire(x,z)""); + + in0 = 1\'bz; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""wire(z,0)""); + in0 = 1\'bz; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""wire(z,1)""); + in0 = 1\'bz; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""wire(z,x)""); + in0 = 1\'bz; in1 = 1\'bz; + #1 all.check(tmp, 1\'bz, ""wire(z,z)""); + end +endmodule + +/* Check the tri net type (should be identical to wire). */ +`default_nettype tri +module top_tri; + reg in0, in1; + + assign tmp = in0; + assign tmp = in1; + + initial begin + in0 = 1\'b0; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""tri(0,0)""); + in0 = 1\'b0; in1 = 1\'b1; + #1 all.check(tmp, 1\'bx, ""tri(0,1)""); + in0 = 1\'b0; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""tri(0,x)""); + in0 = 1\'b0; in1 = 1\'bz; + #1 all.check(tmp, 1\'b0, ""tri(0,z)""); + + in0 = 1\'b1; in1 = 1\'b0; + #1 all.check(tmp, 1\'bx, ""tri(1,0)""); + in0 = 1\'b1; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""tri(1,1)""); + in0 = 1\'b1; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""tri(1,x)""); + in0 = 1\'b1; in1 = 1\'bz; + #1 all.check(tmp, 1\'b1, ""tri(1,z)""); + + in0 = 1\'bx; in1 = 1\'b0; + #1 all.check(tmp, 1\'bx, ""tri(x,0)""); + in0 = 1\'bx; in1 = 1\'b1; + #1 all.check(tmp, 1\'bx, ""tri(x,1)""); + in0 = 1\'bx; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""tri(x,x)""); + in0 = 1\'bx; in1 = 1\'bz; + #1 all.check(tmp, 1\'bx, ""tri(x,z)""); + + in0 = 1\'bz; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""tri(z,0)""); + in0 = 1\'bz; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""tri(z,1)""); + in0 = 1\'bz; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""tri(z,x)""); + in0 = 1\'bz; in1 = 1\'bz; + #1 all.check(tmp, 1\'bz, ""tri(z,z)""); + end +endmodule + +/* Check the tri0 net type (should be the same as tri except z,z is 0). */ +`default_nettype tri0 +module top_tri0; + reg in0, in1; + + assign tmp = in0; + assign tmp = in1; + + initial begin + in0 = 1\'b0; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""tri0(0,0)""); + in0 = 1\'b0; in1 = 1\'b1; + #1 all.check(tmp, 1\'bx, ""tri0(0,1)""); + in0 = 1\'b0; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""tri0(0,x)""); + in0 = 1\'b0; in1 = 1\'bz; + #1 all.check(tmp, 1\'b0, ""tri0(0,z)""); + + in0 = 1\'b1; in1 = 1\'b0; + #1 all.check(tmp, 1\'bx, ""tri0(1,0)""); + in0 = 1\'b1; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""tri0(1,1)""); + in0 = 1\'b1; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""tri0(1,x)""); + in0 = 1\'b1; in1 = 1\'bz; + #1 all.check(tmp, 1\'b1, ""tri0(1,z)""); + + in0 = 1\'bx; in1 = 1\'b0; + #1 all.check(tmp, 1\'bx, ""tri0(x,0)""); + in0 = 1\'bx; in1 = 1\'b1; + #1 all.check(tmp, 1\'bx, ""tri0(x,1)""); + in0 = 1\'bx; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""tri0(x,x)""); + in0 = 1\'bx; in1 = 1\'bz; + #1 all.check(tmp, 1\'bx, ""tri0(x,z)""); + + in0 = 1\'bz; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""tri0(z,0)""); + in0 = 1\'bz; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""tri0(z,1)""); + in0 = 1\'bz; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""tri0(z,x)""); + in0 = 1\'bz; in1 = 1\'bz; + #1 all.check(tmp, 1\'b0, ""tri0(z,z)""); + end +endmodule + +/* Check the tri1 net type (should be the same as tri except z,z is 1). */ +`default_nettype tri1 +module top_tri1; + reg in0, in1; + + assign tmp = in0; + assign tmp = in1; + + initial begin + in0 = 1\'b0; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""tri1(0,0)""); + in0 = 1\'b0; in1 = 1\'b1; + #1 all.check(tmp, 1\'bx, ""tri1(0,1)""); + in0 = 1\'b0; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""tri1(0,x)""); + in0 = 1\'b0; in1 = 1\'bz; + #1 all.check(tmp, 1\'b0, ""tri1(0,z)""); + + in0 = 1\'b1; in1 = 1\'b0; + #1 all.check(tmp, 1\'bx, ""tri1(1,0)""); + in0 = 1\'b1; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""tri1(1,1)""); + in0 = 1\'b1; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""tri1(1,x)""); + in0 = 1\'b1; in1 = 1\'bz; + #1 all.check(tmp, 1\'b1, ""tri1(1,z)""); + + in0 = 1\'bx; in1 = 1\'b0; + #1 all.check(tmp, 1\'bx, ""tri1(x,0)""); + in0 = 1\'bx; in1 = 1\'b1; + #1 all.check(tmp, 1\'bx, ""tri1(x,1)""); + in0 = 1\'bx; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""tri1(x,x)""); + in0 = 1\'bx; in1 = 1\'bz; + #1 all.check(tmp, 1\'bx, ""tri1(x,z)""); + + in0 = 1\'bz; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""tri1(z,0)""); + in0 = 1\'bz; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""tri1(z,1)""); + in0 = 1\'bz; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""tri1(z,x)""); + in0 = 1\'bz; in1 = 1\'bz; + #1 all.check(tmp, 1\'b1, ""tri1(z,z)""); + end +endmodule + +/* Check the wand net type. */ +`default_nettype wand +module top_wand; + reg in0, in1; + + assign tmp = in0; + assign tmp = in1; + + initial begin + in0 = 1\'b0; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""wand(0,0)""); + in0 = 1\'b0; in1 = 1\'b1; + #1 all.check(tmp, 1\'b0, ""wand(0,1)""); + in0 = 1\'b0; in1 = 1\'bx; + #1 all.check(tmp, 1\'b0, ""wand(0,x)""); + in0 = 1\'b0; in1 = 1\'bz; + #1 all.check(tmp, 1\'b0, ""wand(0,z)""); + + in0 = 1\'b1; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""wand(1,0)""); + in0 = 1\'b1; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""wand(1,1)""); + in0 = 1\'b1; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""wand(1,x)""); + in0 = 1\'b1; in1 = 1\'bz; + #1 all.check(tmp, 1\'b1, ""wand(1,z)""); + + in0 = 1\'bx; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""wand(x,0)""); + in0 = 1\'bx; in1 = 1\'b1; + #1 all.check(tmp, 1\'bx, ""wand(x,1)""); + in0 = 1\'bx; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""wand(x,x)""); + in0 = 1\'bx; in1 = 1\'bz; + #1 all.check(tmp, 1\'bx, ""wand(x,z)""); + + in0 = 1\'bz; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""wand(z,0)""); + in0 = 1\'bz; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""wand(z,1)""); + in0 = 1\'bz; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""wand(z,x)""); + in0 = 1\'bz; in1 = 1\'bz; + #1 all.check(tmp, 1\'bz, ""wand(z,z)""); + end +endmodule + +/* Check the triand net type (should be the same as wand). */ +`default_nettype triand +module top_triand; + reg in0, in1; + + assign tmp = in0; + assign tmp = in1; + + initial begin + in0 = 1\'b0; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""triand(0,0)""); + in0 = 1\'b0; in1 = 1\'b1; + #1 all.check(tmp, 1\'b0, ""triand(0,1)""); + in0 = 1\'b0; in1 = 1\'bx; + #1 all.check(tmp, 1\'b0, ""triand(0,x)""); + in0 = 1\'b0; in1 = 1\'bz; + #1 all.check(tmp, 1\'b0, ""triand(0,z)""); + + in0 = 1\'b1; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""triand(1,0)""); + in0 = 1\'b1; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""triand(1,1)""); + in0 = 1\'b1; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""triand(1,x)""); + in0 = 1\'b1; in1 = 1\'bz; + #1 all.check(tmp, 1\'b1, ""triand(1,z)""); + + in0 = 1\'bx; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""triand(x,0)""); + in0 = 1\'bx; in1 = 1\'b1; + #1 all.check(tmp, 1\'bx, ""triand(x,1)""); + in0 = 1\'bx; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""triand(x,x)""); + in0 = 1\'bx; in1 = 1\'bz; + #1 all.check(tmp, 1\'bx, ""triand(x,z)""); + + in0 = 1\'bz; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""triand(z,0)""); + in0 = 1\'bz; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""triand(z,1)""); + in0 = 1\'bz; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""triand(z,x)""); + in0 = 1\'bz; in1 = 1\'bz; + #1 all.check(tmp, 1\'bz, ""triand(z,z)""); + end +endmodule + +/* Check the wor net type. */ +`default_nettype wor +module top_wor; + reg in0, in1; + + assign tmp = in0; + assign tmp = in1; + + initial begin + in0 = 1\'b0; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""wor(0,0)""); + in0 = 1\'b0; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""wor(0,1)""); + in0 = 1\'b0; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""wor(0,x)""); + in0 = 1\'b0; in1 = 1\'bz; + #1 all.check(tmp, 1\'b0, ""wor(0,z)""); + + in0 = 1\'b1; in1 = 1\'b0; + #1 all.check(tmp, 1\'b1, ""wor(1,0)""); + in0 = 1\'b1; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""wor(1,1)""); + in0 = 1\'b1; in1 = 1\'bx; + #1 all.check(tmp, 1\'b1, ""wor(1,x)""); + in0 = 1\'b1; in1 = 1\'bz; + #1 all.check(tmp, 1\'b1, ""wor(1,z)""); + + in0 = 1\'bx; in1 = 1\'b0; + #1 all.check(tmp, 1\'bx, ""wor(x,0)""); + in0 = 1\'bx; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""wor(x,1)""); + in0 = 1\'bx; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""wor(x,x)""); + in0 = 1\'bx; in1 = 1\'bz; + #1 all.check(tmp, 1\'bx, ""wor(x,z)""); + + in0 = 1\'bz; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""wor(z,0)""); + in0 = 1\'bz; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""wor(z,1)""); + in0 = 1\'bz; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""wor(z,x)""); + in0 = 1\'bz; in1 = 1\'bz; + #1 all.check(tmp, 1\'bz, ""wor(z,z)""); + end +endmodule + +/* Check the trior net type (should be the same as wor). */ +`default_nettype trior +module top_trior; + reg in0, in1; + + assign tmp = in0; + assign tmp = in1; + + initial begin + in0 = 1\'b0; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""trior(0,0)""); + in0 = 1\'b0; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""trior(0,1)""); + in0 = 1\'b0; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""trior(0,x)""); + in0 = 1\'b0; in1 = 1\'bz; + #1 all.check(tmp, 1\'b0, ""trior(0,z)""); + + in0 = 1\'b1; in1 = 1\'b0; + #1 all.check(tmp, 1\'b1, ""trior(1,0)""); + in0 = 1\'b1; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""trior(1,1)""); + in0 = 1\'b1; in1 = 1\'bx; + #1 all.check(tmp, 1\'b1, ""trior(1,x)""); + in0 = 1\'b1; in1 = 1\'bz; + #1 all.check(tmp, 1\'b1, ""trior(1,z)""); + + in0 = 1\'bx; in1 = 1\'b0; + #1 all.check(tmp, 1\'bx, ""trior(x,0)""); + in0 = 1\'bx; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""trior(x,1)""); + in0 = 1\'bx; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""trior(x,x)""); + in0 = 1\'bx; in1 = 1\'bz; + #1 all.check(tmp, 1\'bx, ""trior(x,z)""); + + in0 = 1\'bz; in1 = 1\'b0; + #1 all.check(tmp, 1\'b0, ""trior(z,0)""); + in0 = 1\'bz; in1 = 1\'b1; + #1 all.check(tmp, 1\'b1, ""trior(z,1)""); + in0 = 1\'bz; in1 = 1\'bx; + #1 all.check(tmp, 1\'bx, ""trior(z,x)""); + in0 = 1\'bz; in1 = 1\'bz; + #1 all.check(tmp, 1\'bz, ""trior(z,z)""); + end +endmodule +" +"`begin_keywords ""1364-2005"" +/* + * This is a general recreation of the VHDL ieee.math_real package. + */ + +// Constants for use below and for general reference +// TODO: Bring it out to 12 (or more???) places beyond the decimal? +`define MATH_E 2.7182818284 +`define MATH_1_OVER_E 0.3678794411 +`define MATH_PI 3.1415926536 +`define MATH_2_PI 6.2831853071 +`define MATH_1_OVER_PI 0.3183098861 +`define MATH_PI_OVER_2 1.5707963267 +`define MATH_PI_OVER_3 1.0471975511 +`define MATH_PI_OVER_4 0.7853981633 +`define MATH_3_PI_OVER_2 4.7123889803 +`define MATH_LOG_OF_2 0.6931471805 +`define MATH_LOG_OF_10 2.3025850929 +`define MATH_LOG2_OF_E 1.4426950408 +`define MATH_LOG10_OF_E 0.4342944819 +`define MATH_SQRT_2 1.4142135623 +`define MATH_1_OVER_SQRT_2 0.7071067811 +`define MATH_SQRT_PI 1.7724538509 +`define MATH_DEG_TO_RAD 0.0174532925 +`define MATH_RAD_TO_DEG 57.2957795130 + +// The number of iterations to do for the Taylor series approximations +`define EXPLOG_ITERATIONS 50 +`define COS_ITERATIONS 13 + +module math ; + + /* Conversion Routines */ + + // Return the sign of a particular number. + function real sign ; + input real x ; + begin + sign = x < 0.0 ? 1.0 : 0.0 ; + end + endfunction + + // Return the trunc function of a number + function real trunc ; + input real x ; + begin + trunc = x - mod(x,1.0) ; + end + endfunction + + // Return the ceiling function of a number. + function real ceil ; + input real x ; + real retval ; + begin + retval = mod(x,1.0) ; + if( retval != 0.0 && x > 0.0 ) retval = x+1.0 ; + else retval = x ; + ceil = trunc(retval) ; + end + endfunction + + // Return the floor function of a number + function real floor ; + input real x ; + real retval ; + begin + retval = mod(x,1.0) ; + if( retval != 0.0 && x < 0.0 ) retval = x - 1.0 ; + else retval = x ; + floor = trunc(retval) ; + end + endfunction + + // Return the round function of a number + function real round ; + input real x ; + real retval ; + begin + retval = x > 0.0 ? x + 0.5 : x - 0.5 ; + round = trunc(retval) ; + end + endfunction + + // Return the fractional remainder of (x mod m) + function real mod ; + input real x ; + input real m ; + real retval ; + begin + retval = x ; + if( retval > m ) begin + while( retval > m ) begin + retval = retval - m ; + end + end + else begin + while( retval < -m ) begin + retval = retval + m ; + end + end + mod = retval ; + end + endfunction + + // Return the max between two real numbers + function real realmax ; + input real x ; + input real y ; + begin + realmax = x > y ? x : y ; + end + endfunction + + // Return the min between two real numbers + function real realmin ; + input real x ; + input real y ; + begin + realmin = x > y ? y : x ; + end + endfunction + + /* Random Numbers */ + + // Generate Gaussian distributed variables + function real gaussian ; + input real mean ; + input real var ; + real u1, u2, v1, v2, s ; + begin + s = 1.0 ; + while( s >= 1.0 ) begin + // Two random numbers between 0 and 1 + u1 = $random/pow(2.0,32) ; + u2 = $random/pow(2.0,32) ; + // Adjust to be between -1,1 + v1 = 2.0*u1-1.0 ; + v2 = 2.0*u2-1.0 ; + // Polar mag squared + s = v1*v1 + v2*v2 ; + end + gaussian = mean + sqrt(-2.0*log(s)/s) * v1 * sqrt(var) ; + // gaussian2 = mean + sqrt(-2*log(s)/s)*v2 * sqrt(var) ; + end + endfunction + + /* Roots and Log Functions */ + + // Return the square root of a number + function real sqrt ; + input real x ; + real retval ; + begin + // if( x == 0.0 ) retval = 0.0 ; + // else retval = powr(x,0.5) ; + // sqrt = retval ; + sqrt = (x == 0.0) ? 0.0 : powr(x,0.5) ; + end + endfunction + + // Return the cube root of a number + function real cbrt ; + input real x ; + real retval ; + begin + // if( x == 0.0 ) retval = 0.0 ; + // else retval = powr(x,1.0/3.0) ; + // cbrt = retval ; + cbrt = (x == 0.0) ? 0.0 : powr(x,1.0/3.0) ; + end + endfunction + + // Return the absolute value of a real value + function real abs ; + input real x ; + begin + abs = (x > 0.0) ? x : -x ; + end + endfunction + + // Return a real value raised to an integer power + function real pow ; + input real b ; + input integer x ; + integer i ; + integer absx ; + real retval ; + begin + retval = 1.0 ; + absx = abs(x) ; + for( i = 0 ; i < absx ; i = i+1 ) begin + retval = b*retval ; + end + pow = x < 0 ? (1.0/retval) : retval ; + end + endfunction + + // Return a real value raised to a real power + function real powr ; + input real b ; + input real x ; + begin + powr = exp(x*log(b)) ; + end + endfunction + + // Return the evaluation of e^x where e is the natural logarithm base + // NOTE: This is the Taylor series expansion of e^x + function real exp ; + input real x ; + real retval ; + integer i ; + real nm1_fact ; + real powm1 ; + begin + nm1_fact = 1.0 ; + powm1 = 1.0 ; + retval = 1.0 ; + for( i = 1 ; i < `EXPLOG_ITERATIONS ; i = i + 1 ) begin + powm1 = x*powm1 ; + nm1_fact = nm1_fact * i ; + retval = retval + powm1/nm1_fact ; + end + exp = retval ; + end + endfunction + + // Return the evaluation log(x) + function real log ; + input real x ; + integer i ; + real whole ; + real xm1oxp1 ; + real retval ; + real newx ; + begin + retval = 0.0 ; + whole = 0.0 ; + newx = x ; + while( newx > `MATH_E ) begin + whole = whole + 1.0 ; + newx = newx / `MATH_E ; + end + newx = x/pow(`MATH_E,whole) ; + xm1oxp1 = (newx-1.0)/(newx+1.0) ; + for( i = 0 ; i < `EXPLOG_ITERATIONS ; i = i + 1 ) begin + retval = retval + pow(xm1oxp1,2*i+1)/(2.0*i+1.0) ; + end + log = whole+2.0*retval ; + end + endfunction + + // Return the evaluation ln(x) (same as log(x)) + function real ln ; + input real x ; + begin + ln = log(x) ; + end + endfunction + + // Return the evaluation log_2(x) + function real log2 ; + input real x ; + begin + log2 = log(x)/`MATH_LOG_OF_2 ; + end + endfunction + + function real log10 ; + input real x ; + begin + log10 = log(x)/`MATH_LOG_OF_10 ; + end + endfunction + + function real log_base ; + input real x ; + input real b ; + begin + log_base = log(x)/log(b) ; + end + endfunction + + /* Trigonometric Functions */ + + // Internal function to reduce a value to be between [-pi:pi] + function real reduce ; + input real x ; + real retval ; + begin + retval = x ; + if( x > `MATH_PI ) begin + while( retval >= `MATH_PI ) begin + retval = retval - `MATH_PI ; + end + end + else begin + while( retval <= -`MATH_PI ) begin + retval = retval + `MATH_PI ; + end + end + reduce = retval ; + end + endfunction + + // Return the cos of a number in radians + function real cos ; + input real x ; + integer i ; + integer sign ; + real newx ; + real retval ; + real xsqnm1 ; + real twonm1fact ; + begin + newx = reduce(x) ; + xsqnm1 = 1.0 ; + twonm1fact = 1.0 ; + retval = 1.0 ; + for( i = 1 ; i < `COS_ITERATIONS ; i = i + 1 ) begin + sign = -2*(i % 2)+1 ; + xsqnm1 = xsqnm1*newx*newx ; + twonm1fact = twonm1fact * (2.0*i) * (2.0*i-1.0) ; + retval = retval + sign*(xsqnm1/twonm1fact) ; + end + cos = retval ; + end + endfunction + + // Return the sin of a number in radians + function real sin ; + input real x ; + begin + sin = cos(x - `MATH_PI_OVER_2) ; + end + endfunction + + // Return the tan of a number in radians + function real tan ; + input real x ; + begin + tan = sin(x) / cos(x) ; + end + endfunction + + // Return the arcsin in radians of a number + function real arcsin ; + input real x ; + begin + arcsin = 2.0*arctan(x/(1.0+sqrt(1.0-x*x))) ; + end + endfunction + + // Return the arccos in radians of a number + function real arccos ; + input real x ; + begin + arccos = `MATH_PI_OVER_2-arcsin(x) ; + end + endfunction + + // Return the arctan in radians of a number + // TODO: Make sure this REALLY does work as it is supposed to! + function real arctan ; + input real x ; + real retval ; + real y ; + real newx ; + real twoiotwoip1 ; + integer i ; + integer mult ; + begin + retval = 1.0 ; + twoiotwoip1 = 1.0 ; + mult = 1 ; + newx = abs(x) ; + while( newx > 1.0 ) begin + mult = mult*2 ; + newx = newx/(1.0+sqrt(1.0+newx*newx)) ; + end + y = 1.0 ; + for( i = 1 ; i < 2*`COS_ITERATIONS ; i = i + 1 ) begin + y = y*((newx*newx)/(1+newx*newx)) ; + twoiotwoip1 = twoiotwoip1 * (2.0*i)/(2.0*i+1.0) ; + retval = retval + twoiotwoip1*y ; + end + retval = retval * (newx/(1+newx*newx)) ; + retval = retval * mult ; + + arctan = (x > 0.0) ? retval : -retval ; + end + endfunction + + // Return the arctan in radians of a ratio x/y + // TODO: Test to make sure this works as it is supposed to! + function real arctan_xy ; + input real x ; + input real y ; + real retval ; + begin + retval = 0.0 ; + if( x < 0.0 ) retval = `MATH_PI - arctan(-abs(y)/x) ; + else if( x > 0.0 ) retval = arctan(abs(y)/x) ; + else if( x == 0.0 ) retval = `MATH_PI_OVER_2 ; + arctan_xy = (y < 0.0) ? -retval : retval ; + end + endfunction + + /* Hyperbolic Functions */ + + // Return the sinh of a number + function real sinh ; + input real x ; + begin + sinh = (exp(x) - exp(-x))/2.0 ; + end + endfunction + + // Return the cosh of a number + function real cosh ; + input real x ; + begin + cosh = (exp(x) + exp(-x))/2.0 ; + end + endfunction + + // Return the tanh of a number + function real tanh ; + input real x ; + real e2x ; + begin + e2x = exp(2.0*x) ; + tanh = (e2x+1.0)/(e2x-1.0) ; + end + endfunction + + // Return the arcsinh of a number + function real arcsinh ; + input real x ; + begin + arcsinh = log(x+sqrt(x*x+1.0)) ; + end + endfunction + + // Return the arccosh of a number + function real arccosh ; + input real x ; + begin + arccosh = ln(x+sqrt(x*x-1.0)) ; + end + endfunction + + // Return the arctanh of a number + function real arctanh ; + input real x ; + begin + arctanh = 0.5*ln((1.0+x)/(1.0-x)) ; + end + endfunction + + initial begin + $display( ""cos(MATH_PI_OVER_3): %f"", cos(`MATH_PI_OVER_3) ) ; + $display( ""sin(MATH_PI_OVER_3): %f"", sin(`MATH_PI_OVER_3) ) ; + $display( ""sign(-10): %f"", sign(-10) ) ; + $display( ""realmax(MATH_PI,MATH_E): %f"", realmax(`MATH_PI,`MATH_E) ) ; + $display( ""realmin(MATH_PI,MATH_E): %f"", realmin(`MATH_PI,`MATH_E) ) ; + $display( ""mod(MATH_PI,MATH_E): %f"", mod(`MATH_PI,`MATH_E) ) ; + $display( ""ceil(-MATH_PI): %f"", ceil(-`MATH_PI) ) ; + $display( ""ceil(4.0): %f"", ceil(4.0) ) ; + $display( ""ceil(3.99999999999999): %f"", ceil(3.99999999999999) ) ; + $display( ""pow(MATH_PI,2): %f"", pow(`MATH_PI,2) ) ; + $display( ""gaussian(1.0,1.0): %f"", gaussian(1.0,1.0) ) ; + $display( ""round(MATH_PI): %f"", round(`MATH_PI) ) ; + $display( ""trunc(-MATH_PI): %f"", trunc(-`MATH_PI) ) ; + $display( ""ceil(-MATH_PI): %f"", ceil(-`MATH_PI) ) ; + $display( ""floor(MATH_PI): %f"", floor(`MATH_PI) ) ; + $display( ""round(e): %f"", round(`MATH_E)) ; + $display( ""ceil(-e): %f"", ceil(-`MATH_E)) ; + $display( ""exp(MATH_PI): %f"", exp(`MATH_PI) ) ; + $display( ""log2(MATH_PI): %f"", log2(`MATH_PI) ) ; + $display( ""log_base(pow(2,32),2): %f"", log_base(pow(2,32),2) ) ; + $display( ""ln(0.1): %f"", log(0.1) ) ; + $display( ""cbrt(7): %f"", cbrt(7) ) ; + $display( ""cos(%s): %f"", ``MATH_2_PI, cos(20*`MATH_2_PI) ) ; + $display( ""sin(-%s): %f"", ``MATH_2_PI, sin(-50*`MATH_2_PI) ) ; + $display( ""sinh(%s): %f"", ``MATH_E, sinh(`MATH_E) ) ; + $display( ""cosh(%s): %f"", ``MATH_2_PI, cosh(`MATH_2_PI) ) ; + $display( ""arctan_xy(-4,3): %f"", arctan_xy(-4,3) ) ; + $display( ""arctan(MATH_PI): %f"", arctan(`MATH_PI) ) ; + $display( ""arctan(-MATH_E/2): %f"", arctan(-`MATH_E/2) ) ; + $display( ""arctan(MATH_PI_OVER_2): %f"", arctan(`MATH_PI_OVER_2) ) ; + $display( ""arctan(1/7) = %f"", arctan(1.0/7.0) ) ; + $display( ""arctan(3/79) = %f"", arctan(3.0/79.0) ) ; + $display( ""pi/4 ?= %f"", 5*arctan(1.0/7.0)+2*arctan(3.0/79.0) ) ; + $display( ""arcsin(1.0): %f"", arcsin(1.0) ) ; + $display( ""cos(pi/2): %f"", cos(`MATH_PI_OVER_2)) ; + $display( ""arccos(cos(pi/2)): %f"", arccos(cos(`MATH_PI_OVER_2)) ) ; + end + +endmodule +`end_keywords +" +"module top(); + +reg foo; + +tri [1:0] a; +tri [1:0] b; +tri [3:0] c; + +assign a[0] = foo; + +tran t1(a[0], a[1]); +tran t2(b[0], b[1]); + +tran t3[1:0](a, c[1:0]); +tran t4[1:0](b, c[3:2]); + +tran t5(c[1], c[3]); + +initial begin + foo = 1\'b1; + #1 $display(""%b %b %b"", a, b, c); + if ((a === 2\'b11) && (b === 2\'b11) && (c === 4\'b1111)) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module top; + integer res; + initial begin + $hello; + $check_sys_task; + res = $check_sys_func; + $hello; + end +endmodule +" +"module top; + integer i = 0; + + generate + for(i=0; i<4; i=i+1) begin:U + reg [1:0] a = i; + end + endgenerate + + initial $display(""FAILED""); +endmodule +" +"module top; + reg q, clk, d; + reg pass; + + always_ff @(posedge clk) begin + q <= d; + end + + initial begin + pass = 1\'b1; + + #1; + if (q !== 1\'bx) begin + $display(""FAILED: initally expected 1\'bx, got %b"", q); + pass = 1\'b0; + end + + d = 1\'b0; + clk = 1\'b1; + #1; + if (q !== 1\'b0) begin + $display(""FAILED: clock in a 0 expected 1\'b0, got %b"", q); + pass = 1\'b0; + end + + d = 1\'b1; + clk = 1\'b0; + #1; + if (q !== 1\'b0) begin + $display(""FAILED: no clock change expected 1\'b0, got %b"", q); + pass = 1\'b0; + end + + clk = 1\'b1; + #1; + if (q !== 1\'b1) begin + $display(""FAILED: clock in a 1 expected 1\'b1, got %b"", q); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module bug; + +function real sin; +\tinput x; +\treal x; +\tsin = 1.570794*x; +endfunction + +real ax, ay; +initial begin +\tax = 2.0; +\tay = sin(ax); +\t$display(""sin(%g) is not really %g"", ax, ay); +end +endmodule +" +"/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This module tests the basic behavior of a tri0 register. We use a ?: + * to turn on/off the driver to the tri0 net and watch its value. + * A tri0 net should pull to 0 when undriven, and follow the driver + * otherwise. + */ +module main; + + reg enable, val; + tri0 t0 = (~enable) ? 1\'bz : val; + + initial begin + enable = 0; + val = 0; + + #1 if (t0 !== 1\'b0) begin +\t $display(""FAILED -- undriven t0 == %b"", t0); +\t $finish; + end + + enable = 1; + + #1 if (t0 !== 1\'b0) begin +\t $display(""FAILED -- driven-0 t0 == %b"", t0); +\t $finish; + end + + val = 1; + + #1 if (t0 !== 1\'b1) begin +\t $display(""FAILED -- driven-1 t0 == %b"", t0); +\t $finish; + end + + $display(""PASSED""); + end // initial begin +endmodule // main +" +"module bittest; + +reg signed [5:0] m; +reg signed [7:0] n; +reg signed [18:0] p; +reg signed [8:0] s; +reg b; +reg signed c; +reg d; + +always @(m, n, c) begin + p <= m * n; // m and n are signed, so do signed multiply + s <= m + b; // b is UNsigned, so do unsigned pad and add. + d <= c == 1; // c and the literal 1 are signed, so do signed compare. +end + +initial begin + #10; + m <= -25; + n <= 29; + b <= 1; + c <= 1; + #10; + $display(""p=%d s=%d d=%d"", p, s, d); + if (s !== 9\'d40) begin + $display(""FAILED -- s=\'b%b"", s); + $finish; + end + if (p !== -19\'d725) begin + $display(""FAILED == p=\'b%b"", p); + $finish; + end + if (d !== 0) begin + $display(""FAILED == d=\'b%b"", d); + $finish; + end + $display(""PASSED""); +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate task w/ simple input and output + + +module main; + +reg globvar; +reg in1; +reg error; + +task my_task ; + input in1; + output out1; + out1 = in1; +endtask + +initial + begin + error = 0; + my_task(1\'b1,globvar); + if(~globvar) + begin + $display(""FAILED - task 3.14C task didn\'t correctly affect global var(1)""); + error = 1; + end + + in1 = 0; + my_task(!in1,globvar); + if(~globvar) + begin + $display(""FAILED - task 3.14C task didn\'t correctly affect global var(2)""); + error = 1; + end + if(error == 0) + $display(""PASSED""); + end + +endmodule // main +" +"/* Extracted from PR#820. */ + +module main(); + wire clk; + wire reset; + reg [3:0] waddr, raddr; + reg [7:0] wdata; + wire [7:0] rdata; + + clk_reset_gen cg(clk, reset); + + ram_rw #(8,4) r(clk, waddr, wdata, 1\'b1, raddr, rdata); + + initial begin + waddr = 4\'d0; + raddr = 4\'d14; + wdata = 0; + #3001; + $finish(0); + end + + always @(posedge clk) begin + waddr <= #1 waddr + 1; + raddr <= #1 raddr + 1; + wdata <= #1 wdata + 3; + end + + always @(posedge clk) + $display($time,,""waddr wdata %d %d raddr rdata %d %d"",waddr,wdata,raddr,rdata); + +endmodule + +module ram_rw(clk,waddr,wdata,we,raddr,rdata); + parameter WDATA = 8; + parameter WADDR = 11; + + input clk; + + input [(WADDR-1):0] waddr; + input [(WDATA-1):0] wdata; + input we; + + input [(WADDR-1):0] raddr; + output [(WDATA-1):0] rdata; + +//local + reg [(WDATA-1):0] mem[0:((1< Q) = (1,1); + (B => Q) = (1,1); + endspecify + +endmodule + +`endcelldefine + +module tb; + + reg a, b; + wire q; + XOR20 dut(.A(a), .B(b), .Q(q)); + + initial begin + $monitor($time,, ""A=%b, B=%b, Q=%b"", a, b, q); + $sdf_annotate(""ivltests/sdf7.sdf""); + + #10 ; + a = 1; + b = 1; + #10 ; + b = 0; + #10 ; + b = 1; + #10 ; + a = 0; + #10 $finish(0); + end + +endmodule // tb +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate the ? operator - use [var] as bit selector also + + +module main; + +reg globvar; + +reg [3:0] bvec,var1,var2,var3; +reg cond, a,b,out1,out2; +reg error; + +initial + begin + error = 0; + bvec = 4\'bzx10 ; + for(var1 = 0; var1 <= 3; var1 = var1 + 1) + for(var2 = 0; var2 <= 3; var2 = var2 + 1) + for(var3 = 0; var3 <= 3; var3 = var3 + 1) + begin +\t // Tried both bvec[var1] and bvec[var1:var1] + // but believe these HAVE to be a constant expression? + if(var1 == 4\'h0) + cond = bvec[0]; + else + if(var1 == 4\'h1) + cond = bvec[1]; + else + if(var1 == 4\'h2) + cond = bvec[2]; + else + cond = bvec[3]; + + if (var2 == 4\'h0) + a = bvec[0]; + else + if (var2 == 4\'h1) + a = bvec[1]; + else + if (var2 == 4\'h2) + a = bvec[2]; + else + a = bvec[3]; + + if (var3 == 4\'h0) + a = bvec[0]; + else + if (var3 == 4\'h1) + a = bvec[1]; + else + if (var3 == 4\'h2) + a = bvec[2]; + else + a = bvec[3]; + + out1 = cond ? a: b ; + if(cond) out2 = a ; + else out2 = b; + if(out1 != out2) + begin + $display(""FAILED - qmark1 - %b %b %b %b %b"", + cond,a,b,out1,out2); + error = 1; + end + end + if(error == 0) + $display(""PASSED""); + end + +endmodule // main +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Basic ifdef test +// + + +module ifdef1; + +reg error ; + +`ifdef NOCODE +initial + begin + #20; + error = 1; + #20; + end +`endif + +initial + begin + #1; + error = 0; + #40; + if(error == 0) + $display(""PASSED""); + else + $display(""FAILED""); + end + +endmodule // main +" +"// Test implicit casts during continuous assignments. + +`ifdef __ICARUS__ + `define SUPPORT_REAL_NETS_IN_IVTEST + `define SUPPORT_TWO_STATE_NETS_IN_IVTEST +`endif + +module implicit_cast(); + +real src_r; + +bit unsigned [7:0] src_u2; +bit signed [7:0] src_s2; + +logic unsigned [7:0] src_u4; +logic signed [7:0] src_s4; + +logic unsigned [7:0] src_ux; +logic signed [7:0] src_sx; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +wire real dst1_r; +wire real dst2_r; +wire real dst3_r; +wire real dst4_r; +wire real dst5_r; +wire real dst6_r; +wire real dst7_r; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +wire bit unsigned [3:0] dst1_u2s; +wire bit unsigned [3:0] dst2_u2s; +wire bit unsigned [3:0] dst3_u2s; +wire bit unsigned [3:0] dst4_u2s; +wire bit unsigned [3:0] dst5_u2s; +wire bit unsigned [3:0] dst6_u2s; +wire bit unsigned [3:0] dst7_u2s; + +wire bit signed [3:0] dst1_s2s; +wire bit signed [3:0] dst2_s2s; +wire bit signed [3:0] dst3_s2s; +wire bit signed [3:0] dst4_s2s; +wire bit signed [3:0] dst5_s2s; +wire bit signed [3:0] dst6_s2s; +wire bit signed [3:0] dst7_s2s; + +wire bit unsigned [11:0] dst1_u2l; +wire bit unsigned [11:0] dst2_u2l; +wire bit unsigned [11:0] dst3_u2l; +wire bit unsigned [11:0] dst4_u2l; +wire bit unsigned [11:0] dst5_u2l; +wire bit unsigned [11:0] dst6_u2l; +wire bit unsigned [11:0] dst7_u2l; + +wire bit signed [11:0] dst1_s2l; +wire bit signed [11:0] dst2_s2l; +wire bit signed [11:0] dst3_s2l; +wire bit signed [11:0] dst4_s2l; +wire bit signed [11:0] dst5_s2l; +wire bit signed [11:0] dst6_s2l; +wire bit signed [11:0] dst7_s2l; +`endif + +wire logic unsigned [3:0] dst1_u4s; +wire logic unsigned [3:0] dst2_u4s; +wire logic unsigned [3:0] dst3_u4s; +wire logic unsigned [3:0] dst4_u4s; +wire logic unsigned [3:0] dst5_u4s; +wire logic unsigned [3:0] dst6_u4s; +wire logic unsigned [3:0] dst7_u4s; + +wire logic signed [3:0] dst1_s4s; +wire logic signed [3:0] dst2_s4s; +wire logic signed [3:0] dst3_s4s; +wire logic signed [3:0] dst4_s4s; +wire logic signed [3:0] dst5_s4s; +wire logic signed [3:0] dst6_s4s; +wire logic signed [3:0] dst7_s4s; + +wire logic unsigned [11:0] dst1_u4l; +wire logic unsigned [11:0] dst2_u4l; +wire logic unsigned [11:0] dst3_u4l; +wire logic unsigned [11:0] dst4_u4l; +wire logic unsigned [11:0] dst5_u4l; +wire logic unsigned [11:0] dst6_u4l; +wire logic unsigned [11:0] dst7_u4l; + +wire logic signed [11:0] dst1_s4l; +wire logic signed [11:0] dst2_s4l; +wire logic signed [11:0] dst3_s4l; +wire logic signed [11:0] dst4_s4l; +wire logic signed [11:0] dst5_s4l; +wire logic signed [11:0] dst6_s4l; +wire logic signed [11:0] dst7_s4l; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +assign dst1_r = src_r; +assign dst2_r = src_u4; +assign dst3_r = src_s4; +assign dst4_r = src_u2; +assign dst5_r = src_s2; +assign dst6_r = src_ux; +assign dst7_r = src_sx; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +assign dst1_u2s = src_r; +assign dst2_u2s = src_u4; +assign dst3_u2s = src_s4; +assign dst4_u2s = src_u2; +assign dst5_u2s = src_s2; +assign dst6_u2s = src_ux; +assign dst7_u2s = src_sx; + +assign dst1_s2s = src_r; +assign dst2_s2s = src_u4; +assign dst3_s2s = src_s4; +assign dst4_s2s = src_u2; +assign dst5_s2s = src_s2; +assign dst6_s2s = src_ux; +assign dst7_s2s = src_sx; + +assign dst1_u2l = src_r; +assign dst2_u2l = src_u4; +assign dst3_u2l = src_s4; +assign dst4_u2l = src_u2; +assign dst5_u2l = src_s2; +assign dst6_u2l = src_ux; +assign dst7_u2l = src_sx; + +assign dst1_s2l = src_r; +assign dst2_s2l = src_u4; +assign dst3_s2l = src_s4; +assign dst4_s2l = src_u2; +assign dst5_s2l = src_s2; +assign dst6_s2l = src_ux; +assign dst7_s2l = src_sx; +`endif + +assign dst1_u4s = src_r; +assign dst2_u4s = src_u4; +assign dst3_u4s = src_s4; +assign dst4_u4s = src_u2; +assign dst5_u4s = src_s2; +assign dst6_u4s = src_ux; +assign dst7_u4s = src_sx; + +assign dst1_s4s = src_r; +assign dst2_s4s = src_u4; +assign dst3_s4s = src_s4; +assign dst4_s4s = src_u2; +assign dst5_s4s = src_s2; +assign dst6_s4s = src_ux; +assign dst7_s4s = src_sx; + +assign dst1_u4l = src_r; +assign dst2_u4l = src_u4; +assign dst3_u4l = src_s4; +assign dst4_u4l = src_u2; +assign dst5_u4l = src_s2; +assign dst6_u4l = src_ux; +assign dst7_u4l = src_sx; + +assign dst1_s4l = src_r; +assign dst2_s4l = src_u4; +assign dst3_s4l = src_s4; +assign dst4_s4l = src_u2; +assign dst5_s4l = src_s2; +assign dst6_s4l = src_ux; +assign dst7_s4l = src_sx; + +bit failed; + +initial begin + failed = 0; + + src_r = -7; + src_u2 = 7; + src_s2 = -7; + src_u4 = 7; + src_s4 = -7; + src_ux = 8\'bx0z00111; + src_sx = 8\'bx0z00111; + + #1; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST + $display(""cast to real""); + $display(""%g"", dst1_r); if (dst1_r != -7.0) failed = 1; + $display(""%g"", dst2_r); if (dst2_r != 7.0) failed = 1; + $display(""%g"", dst3_r); if (dst3_r != -7.0) failed = 1; + $display(""%g"", dst4_r); if (dst4_r != 7.0) failed = 1; + $display(""%g"", dst5_r); if (dst5_r != -7.0) failed = 1; + $display(""%g"", dst6_r); if (dst6_r != 7.0) failed = 1; + $display(""%g"", dst7_r); if (dst7_r != 7.0) failed = 1; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST + $display(""cast to small unsigned bit""); + $display(""%d"", dst1_u2s); if (dst1_u2s !== 4\'d9) failed = 1; + $display(""%d"", dst2_u2s); if (dst2_u2s !== 4\'d7) failed = 1; + $display(""%d"", dst3_u2s); if (dst3_u2s !== 4\'d9) failed = 1; + $display(""%d"", dst4_u2s); if (dst4_u2s !== 4\'d7) failed = 1; + $display(""%d"", dst5_u2s); if (dst5_u2s !== 4\'d9) failed = 1; + $display(""%d"", dst6_u2s); if (dst6_u2s !== 4\'d7) failed = 1; + $display(""%d"", dst7_u2s); if (dst7_u2s !== 4\'d7) failed = 1; + + $display(""cast to small signed bit""); + $display(""%d"", dst1_s2s); if (dst1_s2s !== -4\'sd7) failed = 1; + $display(""%d"", dst2_s2s); if (dst2_s2s !== 4\'sd7) failed = 1; + $display(""%d"", dst3_s2s); if (dst3_s2s !== -4\'sd7) failed = 1; + $display(""%d"", dst4_s2s); if (dst4_s2s !== 4\'sd7) failed = 1; + $display(""%d"", dst5_s2s); if (dst5_s2s !== -4\'sd7) failed = 1; + $display(""%d"", dst6_s2s); if (dst6_s2s !== 4\'sd7) failed = 1; + $display(""%d"", dst7_s2s); if (dst7_s2s !== 4\'sd7) failed = 1; + + $display(""cast to large unsigned bit""); + $display(""%d"", dst1_u2l); if (dst1_u2l !== 12\'d4089) failed = 1; + $display(""%d"", dst2_u2l); if (dst2_u2l !== 12\'d7) failed = 1; + $display(""%d"", dst3_u2l); if (dst3_u2l !== 12\'d4089) failed = 1; + $display(""%d"", dst4_u2l); if (dst4_u2l !== 12\'d7) failed = 1; + $display(""%d"", dst5_u2l); if (dst5_u2l !== 12\'d4089) failed = 1; + $display(""%b"", dst6_u2l); if (dst6_u2l !== 12\'b000000000111) failed = 1; + $display(""%b"", dst7_u2l); if (dst7_u2l !== 12\'b000000000111) failed = 1; + + $display(""cast to large signed bit""); + $display(""%d"", dst1_s2l); if (dst1_s2l !== -12\'sd7) failed = 1; + $display(""%d"", dst2_s2l); if (dst2_s2l !== 12\'sd7) failed = 1; + $display(""%d"", dst3_s2l); if (dst3_s2l !== -12\'sd7) failed = 1; + $display(""%d"", dst4_s2l); if (dst4_s2l !== 12\'sd7) failed = 1; + $display(""%d"", dst5_s2l); if (dst5_s2l !== -12\'sd7) failed = 1; + $display(""%b"", dst6_s2l); if (dst6_s2l !== 12\'b000000000111) failed = 1; + $display(""%b"", dst7_s2l); if (dst7_s2l !== 12\'b000000000111) failed = 1; +`endif + + $display(""cast to small unsigned logic""); + $display(""%d"", dst1_u4s); if (dst1_u4s !== 4\'d9) failed = 1; + $display(""%d"", dst2_u4s); if (dst2_u4s !== 4\'d7) failed = 1; + $display(""%d"", dst3_u4s); if (dst3_u4s !== 4\'d9) failed = 1; + $display(""%d"", dst4_u4s); if (dst4_u4s !== 4\'d7) failed = 1; + $display(""%d"", dst5_u4s); if (dst5_u4s !== 4\'d9) failed = 1; + $display(""%d"", dst6_u4s); if (dst6_u4s !== 4\'d7) failed = 1; + $display(""%d"", dst7_u4s); if (dst7_u4s !== 4\'d7) failed = 1; + + $display(""cast to small signed logic""); + $display(""%d"", dst1_s4s); if (dst1_s4s !== -4\'sd7) failed = 1; + $display(""%d"", dst2_s4s); if (dst2_s4s !== 4\'sd7) failed = 1; + $display(""%d"", dst3_s4s); if (dst3_s4s !== -4\'sd7) failed = 1; + $display(""%d"", dst4_s4s); if (dst4_s4s !== 4\'sd7) failed = 1; + $display(""%d"", dst5_s4s); if (dst5_s4s !== -4\'sd7) failed = 1; + $display(""%d"", dst6_s4s); if (dst6_s4s !== 4\'sd7) failed = 1; + $display(""%d"", dst7_s4s); if (dst7_s4s !== 4\'sd7) failed = 1; + + $display(""cast to large unsigned logic""); + $display(""%d"", dst1_u4l); if (dst1_u4l !== 12\'d4089) failed = 1; + $display(""%d"", dst2_u4l); if (dst2_u4l !== 12\'d7) failed = 1; + $display(""%d"", dst3_u4l); if (dst3_u4l !== 12\'d4089) failed = 1; + $display(""%d"", dst4_u4l); if (dst4_u4l !== 12\'d7) failed = 1; + $display(""%d"", dst5_u4l); if (dst5_u4l !== 12\'d4089) failed = 1; + $display(""%b"", dst6_u4l); if (dst6_u4l !== 12\'b0000x0z00111) failed = 1; + $display(""%b"", dst7_u4l); if (dst7_u4l !== 12\'bxxxxx0z00111) failed = 1; + + $display(""cast to large signed logic""); + $display(""%d"", dst1_s4l); if (dst1_s4l !== -12\'sd7) failed = 1; + $display(""%d"", dst2_s4l); if (dst2_s4l !== 12\'sd7) failed = 1; + $display(""%d"", dst3_s4l); if (dst3_s4l !== -12\'sd7) failed = 1; + $display(""%d"", dst4_s4l); if (dst4_s4l !== 12\'sd7) failed = 1; + $display(""%d"", dst5_s4l); if (dst5_s4l !== -12\'sd7) failed = 1; + $display(""%b"", dst6_s4l); if (dst6_s4l !== 12\'b0000x0z00111) failed = 1; + $display(""%b"", dst7_s4l); if (dst7_s4l !== 12\'bxxxxx0z00111) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"// Here are two examples of $strobe failing. It appears that thread data +// is being cleaned up too soon for the $strobe to access it. +module test; + reg[4:0] j; + reg [5:0] in [1:0]; + wire [5:0] out; + + assign out = in[j]; // This uses the current j. + + initial begin + in[1] = 6\'b110001; + + j = 1; + #1; // Need some delay for the calculations to run. + $display(""out: %b, in[%0d] %b:"", out, j, in[j]); + $display(""out[3:0]: %b, in[%0d] %b:"", out[j*1-1 +: 4], j, in[j]); + + // in[j] is what is failing. + $strobe(""out: %b, in[%0d] %b:"", out, j, in[j]); + + // out[j... is what is failing. + $strobe(""out[3:0]: %b, in[%0d] %b:"", out[j*1-1 +: 4], j, in[j]); +// #1; // Adding this will work around the bug. + end + +endmodule +" +" +/* + * This tests a trivial class. This tests that properties can be + * given types, and that the types behave properly. + */ +program main; + + // Trivial example of a class + class foo_t ; + longint signed a; + longint unsigned b; + endclass : foo_t // foo_t + + foo_t obj; + + initial begin + obj = new; + + // This is the most trivial assignment of class properties. + obj.a = 68\'hf_ffffffff_ffffffff; + obj.b = 68\'hf_ffffffff_ffffffff; + + if (obj.a != -1 || obj.b != 64\'hffffffff_ffffffff) begin +\t $display(""FAILED -- assign to object: obj.a=%0d, obj.b=%0d"", obj.a, obj.b); +\t $finish; + end + + obj.a = obj.a + 1; + obj.b = obj.b + 1; + if (obj.a != 0 || obj.b != 0) begin +\t $display(""FAILED -- increment properties: obj.a=%0d, obj.b=%0d"", obj.a, obj.b); +\t $finish; + end + + $display(""PASSED""); + $finish; + end +endprogram // main +" +"module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4\'d2; + +buf buffer[7:0](value2, value1); + +initial begin + #2 $display(""%b %b"", value1, value2); + if (value2 === 8\'bxxxx0010) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate NAND gate vector +// + + +module main; + +reg globvar; + +wire [15:0] out; +reg [15:0] a,b, rslt; +reg error; + +// The test gate goes HERE! + +nand foo [15:0] (out,a,b); + +always @(a or b) + rslt = ~(a & b); + +initial + begin // { + error = 0; + # 1; + for(a = 16\'h1; a != 16\'hffff; a = (a << 1) | 1) + begin // { + for(b = 16\'hffff; b !== 16\'h0; b = b >> 1) + begin // { + #1 ; + if(out !== rslt) + begin // { + $display(""FAILED - GA NAND a=%h,b=%h,expct=%h - rcvd=%h"", + a,b,rslt,out); + error = 1; + end // } + end // } + end // } + if( error == 0) + $display(""PASSED""); + end // } +endmodule // main +" +"// +// Copyright (c) 2002 Stephen Williams (steve@icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +/* + * This function captures the correctness of a non-constant delay + * that is internal to a non-blocking assignment. + */ + +module main; + + reg [7:0] delay = 0; + reg\t step; + + initial begin + delay = 2; + step = 0; + step <= #(delay) 1; + + #1 if (step !== 0) begin +\t $display(""FAILED -- step=%b at time=1"", step); +\t $finish; + end + + #2 if (step !== 1) begin +\t $display(""FAILED == step=%b at time=3"", step); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"module x; + + parameter bar0_low = 5\'d16; // Register Space + reg [31:bar0_low] base_address0; + + reg [31:0]\t ad_in_d; + wire [0:5]\t hit_bar; + + wire\t\t a = |bar0_low; + wire [31:0]\t e = ad_in_d[31:bar0_low]; + wire\t\t b = (base_address0==e); + wire\t\t d = b; + + assign\t hit_bar[0] = a ? d : 0; + + initial begin + if ($bits(base_address0) != 16) begin +\t $display(""FAILED -- $bits(base_address0) = %0d"", $bits(base_address0)); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule +" +"module main; + + reg [1:0] src; + wire [3:0] dst, dst2, dst3; + + foo_entity dut (.data_o(dst), .data_o2(dst2), .data_o3(dst3), .data_i(src)); + + initial begin + src = 2\'b00; + #1 if (dst != 4\'b0001 || dst2 != 4\'bxxxx || dst3 != 4\'bxxx) begin +\t $display(""FAILED""); +\t $finish; + end + + src = 2\'b01; + #1 if (dst != 4\'b0010 || dst2 != 4\'b0101 || dst3 != 4\'b0011) begin +\t $display(""FAILED""); +\t $finish; + end + + src = 2\'b10; + #1 if (dst != 4\'b0100 || dst2 != 4\'b0101 || dst3 != 4\'b1100) begin +\t $display(""FAILED""); +\t $finish; + end + + src = 2\'b11; + #1 if (dst != 4\'b1000 || dst2 != 4\'b0101 || dst3 != 4\'b1100) begin +\t $display(""FAILED""); +\t $finish; + end + + $display(""PASSED""); + end +endmodule // main +" +"// Check that packed arrays of all sorts get elaborated without an error and +// that the resulting type has the right packed width. + +module test; + +typedef bit bit2; +typedef logic [1:0] vector; + +bit2 [1:0] b; +vector [2:0] l; + +typedef enum logic [7:0] { + A +} E; + +typedef E [1:0] EP; +typedef EP [2:0] EPP; + +E e; +EP ep1; +E [1:0] ep2; +EP [2:0] epp1; +EPP epp2; +EPP [3:0] eppp; + +typedef struct packed { + longint x; +} S1; + +typedef struct packed { + time t; + integer i; + + logic [1:0] x; + bit [3:0] y; + int z; + shortint w; + + E e; + EP ep; + + S1 s; +} S2; + +localparam S_SIZE = 64 + 32 + 2 + 4 + 32 + 16 + 8 + 8*2 + 64; + +typedef S2 [3:0] SP; +typedef SP [9:0] SPP; + +S2 s; +SP sp1; +S2 [3:0] sp2; +SP [9:0] spp1; +SPP spp2; +SPP [1:0] sppp; + +bit failed = 1\'b0; + +initial begin + // Packed arrays of basic types + failed |= $bits(b) !== 2; + failed |= $bits(l) !== 2 * 3; + + // Packed arrays of enums + failed |= $bits(e) !== 8; + failed |= $bits(ep1) !== $bits(e) * 2; + failed |= $bits(ep2) !== $bits(ep1); + failed |= $bits(epp1) !== $bits(ep1) * 3; + failed |= $bits(epp2) !== $bits(epp1); + failed |= $bits(eppp) !== $bits(epp1) * 4; + + // Packed arrays of structs + failed |= $bits(s) !== S_SIZE; + failed |= $bits(sp1) != $bits(s) * 4; + failed |= $bits(sp2) != $bits(sp1); + failed |= $bits(spp1) != $bits(sp1) * 10; + failed |= $bits(spp1) != $bits(spp2); + failed |= $bits(sppp) != $bits(spp1) * 2; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"`timescale 1 s / 1 fs + +module main; + + reg a; + + initial begin + a = 1\'b0; + #10 ; + $display(""simtime=%d (%h)"", $simtime, $simtime); + a = 1\'b1; + end + + initial begin + #100 $finish(0); + end + +endmodule // main +" +"// This test program is mostly about the parser parsing the attribute +// attached to the main.dut.Q reg below. + +module main; + + reg CK; + always begin + #10 CK = 0; + #10 CK = 1; + end + + reg [3:0] D; + wire [3:0] Q; + test dut (.Q(Q), .D(D), .CK(CK)); + + initial begin + D = 0; + @(posedge CK) #1 $display(""Q=%b, D=%b"", Q, D); + if (Q !== D) begin +\t $display(""FAILED""); +\t $finish; + end + + $display(""PASSED""); + $finish; + end + +endmodule // main + +module test (Q, D, CK); + + output [3:0] Q; + input [3:0]\tD; + input\tCK; + + (* REGISTER_DUPLICATION = ""no"" *) + reg [3:0]\tQ; + always @(posedge CK) + Q <= D; + +endmodule // test +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always wait (expression ) reg_lvalue = constant ; + + +module main ; + +reg [3:0] value1,value2,value3; + +always wait (value1 == 4\'h3) begin + value2 = 3 ; + #1 ; + end + +initial + begin + value1 = 0; + value2 = 0; + value3 = 0; + #2 ; + if(value2 != 0) + begin + $display(""FAILED - 3.1.8A always wait (expr) reg_lval = const (1);""); + value3 = 1; + end + value1 = 1; + #2 ; + if(value2 != 0) + begin + $display(""FAILED - 3.1.8A always wait (expr) reg_lval = const (2);""); + value3 = 1; + end + value1 = 2; + #2 ; + if(value2 != 0) + begin + $display(""FAILED - 3.1.8A always wait (expr) reg_lval = const (3);""); + value3 = 1; + end + value1 = 4\'h3; + #2; + if(value2 != 3) + begin + $display(""FAILED - 3.1.8A always wait (expr) reg_lval = const (4);""); + value3 = 1; + end + #10; + if(value3 == 0) + $display(""PASSED""); + $finish ; + end + +endmodule +" +"package my_package; + +parameter p1 = 1; +localparam p2 = p1 + \'bx; + +typedef logic [1:0] word; + +word v = 2\'bx; + +event e; + +function word f(word g); + f = g + 2\'bx; +endfunction + +task h(word i); + v = v + i + 2\'bx; + $display(v); +endtask + +endpackage + +module test(); + +import my_package::*; + +parameter p1 = 3; +localparam p2 = p1 + 2; + +typedef logic [7:0] word; + +word v = 0; + +event e; + +word my_v = 0; + +initial begin + #1 ->my_package::e; +end + +initial begin + @(my_package::e); + my_v = p1; + #1 ->e; +end + +initial begin + @e v = my_v; + h(f(1)); + if (p2 === 5 && $bits(v) === 8 && v === 5) + $display(""PASSED""); + else + $display(""FAILED""); +end + +function word f(word g); + f = g + 1; +endfunction + +task h(word i); + v = v + i; + $display(v); +endtask + +endmodule +" +"module test(); + +reg illegal[0]; + +endmodule +" +"module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4\'d2; + +assign (weak1,weak0) value2 = value1; + +initial begin + #2 $display(""%b %b"", value1, value2); + if (value2 === 8\'bzzzz0010) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module top; + reg [79:0] data = 0; + + initial begin + data = data + 80\'h12345678901234567890; + if (data !== 80\'h12345678901234567890) $display(""FAILED""); + else $display(""PASSED""); + end +endmodule +" +"module br993a(); + +reg clk; +reg a; +reg b; +reg [1:0] q; + +(* ivl_synthesis_on *) +always @(posedge clk) begin + q <= 0; + if (a) q <= 1; + if (b) q <= 2; +end +(* ivl_synthesis_off *) + +reg failed; +initial begin + clk = 0; + + a = 0; + b = 0; + #1 clk = 1; + #1 clk = 0; + $display(""%d"", q); + if (q !== 2\'d0) failed = 1; + + a = 1; + b = 0; + #1 clk = 1; + #1 clk = 0; + $display(""%d"", q); + if (q !== 2\'d1) failed = 1; + + a = 1; + b = 1; + #1 clk = 1; + #1 clk = 0; + $display(""%d"", q); + if (q !== 2\'d2) failed = 1; + + a = 0; + b = 1; + #1 clk = 1; + #1 clk = 0; + $display(""%d"", q); + if (q !== 2\'d2) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module top; + reg clk; + reg pass = 1\'b1; + + generate + genvar n; + for (n=0; n<4; n=n+1) begin : loop + reg [n:0] r; + always @(clk) r = n; + end + endgenerate + + initial begin + clk = 0; + #1; + + if (loop[0].r !== 0) begin + $display(""Failed generate instance 0""); + pass = 1\'b0; + end + + if (loop[1].r !== 1) begin + $display(""Failed generate instance 1""); + pass = 1\'b0; + end + + if (loop[2].r !== 2) begin + $display(""Failed generate instance 2""); + pass = 1\'b0; + end + + if (loop[3].r !== 3) begin + $display(""Failed generate instance 3""); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"// Regression test for br962 - based on test case provided in bug report +module qtest; + parameter width = 32; + parameter depth = 32; + + reg [width-1:0] values[$]; + reg [$clog2(depth)+width-1:0] sum1; + reg [$clog2(depth)+width-1:0] sum2; + + task new_sample; + input [width-1:0] data; + int i; + begin + reg [width-1:0] popped; + if (values.size >= depth) +\tbegin : foo +\t popped = values.pop_back(); +\t sum1 = sum1 - popped; +\tend + sum1 = sum1 + data; + values.push_front(data); + sum2 = 0; + for (i = 0; i < values.size; i++) begin + sum2 = sum2 + values[i]; + end + $display(""sum1 = %d sum2 = %d"", sum1, sum2); + if (sum1 !== sum2) begin + $display(""FAILED""); + $finish; + end + end + endtask + + initial begin + sum1 = 0; + repeat (2*depth) new_sample({$random}); + $display(""PASSED""); + end + +endmodule +" +"module top; + initial begin + #1 $info(""This is the $info message.""); + #1 $warning(""This is the $warning message.""); + #1 $error(""This is the $error message.""); + #1 $display(""Check that the messages are correct.""); + end +endmodule +" +"module test(); + +task t(input integer a, integer b); + $display(a,,b); +endtask + +initial t(0, 1); + +endmodule +" +"`timescale 1us/100ns + +module top; + reg pass = 1\'b1; + + real ra = 1.0, rb = 2.0; + wire real rpow; + + /* Real Power. */ + assign #1 rpow = ra ** rb; + + initial begin + #0.9; + if (rpow == 1.0) begin + pass = 1\'b0; + $display(""Real: power value not delayed.""); + end + + #0.1; + #0; + if (rpow != 1.0) begin + pass = 1\'b0; + $display(""Real: power value not correct, expected 1.0 got %g."", rpow); + end + + #1 ra = 2.0; + #2; + if (rpow != 4.0) begin + pass = 1\'b0; + $display(""Real: power value not correct, expected 4.0 got %g."", rpow); + end + + #1 ra = 0.0; + #2; + if (rpow != 0.0) begin + pass = 1\'b0; + $display(""Real: power value not correct, expected 0.0 got %g."", rpow); + end + + #1 ra = 10.0; + #2; + if (rpow != 100.0) begin + pass = 1\'b0; + $display(""Real: power value not correct, expected 100.0 got %g."", rpow); + end + + #1 ra = 0.0; rb = -1.0; + #2; + $display(""0.0 ** -1.0 = %g"", rpow); + + #1 ra = -1.0; rb = 2.5; + #2; + $display(""-1.0 ** 2.5 = %g"", rpow); + + if (pass) $display(""PASSED""); + end +endmodule +" +"// Check behaviour with out-of-range and undefined array indices +// on LHS of procedural continuous (reg) assignment. + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + +reg [1:0] array1[2:1]; +reg [1:0] array2[1:0]; + +reg [1:0] var1; + +`ifndef VLOG95 +real array3[2:1]; +real array4[1:0]; + +real var2; +`endif + +reg failed; + +initial begin + failed = 0; + + array1[1] = 2\'d0; + array1[2] = 2\'d0; + + array2[0] = 2\'d0; + array2[1] = 2\'d0; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign array1[0] = 2\'d1; + #1 $display(""array = %h %h"", array1[2], array1[1]); + if ((array1[1] !== 2\'d0) || (array1[2] !== 2\'d0)) failed = 1; + deassign array1[0]; +`endif + + assign array1[1] = 2\'d1; + #1 $display(""array = %h %h"", array1[2], array1[1]); + if ((array1[1] !== 2\'d1) || (array1[2] !== 2\'d0)) failed = 1; + deassign array1[1]; + + assign array1[2] = var1; + var1 = 2\'d1; + #1 $display(""array = %h %h"", array1[2], array1[1]); + if ((array1[1] !== 2\'d0) || (array1[2] !== 2\'d1)) failed = 1; + var1 = 2\'d2; + #1 $display(""array = %h %h"", array1[2], array1[1]); + if ((array1[1] !== 2\'d0) || (array1[2] !== 2\'d2)) failed = 1; + deassign array1[2]; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign array1[3] = var1; + #1 $display(""array = %h %h"", array1[2], array1[1]); + if ((array1[1] !== 2\'d0) || (array1[2] !== 2\'d0)) failed = 1; + deassign array1[3]; + + assign array2[\'bx] = 2\'d1; + #1 $display(""array = %h %h"", array2[1], array2[0]); + if ((array2[0] !== 2\'d0) || (array2[1] !== 2\'d0)) failed = 1; + deassign array2[\'bx]; +`endif + +`ifndef VLOG95 + array3[1] = 0.0; + array3[2] = 0.0; + + array4[0] = 0.0; + array4[1] = 0.0; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign array3[0] = 1.0; + #1 $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + deassign array3[0]; +`endif + + assign array3[1] = 1.0; + #1 $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 1.0) || (array3[2] != 0.0)) failed = 1; + deassign array3[1]; + + assign array3[2] = var2; + var2 = 1.0; + #1 $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 1.0)) failed = 1; + var2 = 2.0; + #1 $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 2.0)) failed = 1; + deassign array3[2]; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign array3[3] = var2; + #1 $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + deassign array3[3]; + + assign array4[\'bx] = 1.0; + #1 $display(""array = %0g %0g"", array4[1], array4[0]); + if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1; + deassign array4[\'bx]; +`endif +`endif + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"// pr1855504 + +module mul_test(); + + reg [15:0] prod; + reg [7:0] op2; + reg [15:0] op1; + + + initial begin + op1 = 16\'h0DA0; + op2 = 8\'h0A; + prod = 16\'h0000; + end + + always begin + prod <= op1[7:0] * op2; + #5 $display(""op1 = %h, op2 = %h, prod = %h"", op1, op2, prod); + #5 $finish(0); + end + +endmodule // mul_test +" +"// pr1742910 + +module checktest(); + + parameter sum = 1\'h1 + 1\'h1; + + initial begin +`ifdef __ICARUS_UNSIZED__ + if (sum !== 2) begin +`else + if (sum !== 0) begin +`endif +\t $display(""FAILED -- sum = %d"", sum); +\t $finish; + end + $display(""PASSED""); + $finish; + end + +endmodule +" +"/* + * This is a simple test for the for...join_any syntax. There is a + * fork statement to start a bunch of threads. We wait for none of + * them and instead watch them progress with the master thread. + */ +module main; + + int flag; + initial begin + flag = 0; + fork +\t # 10 flag = 10; +\t # 20 flag = 20; +\t # 30 flag = 30; + join_any + + #5 if (flag != 10) begin +\t $display(""FAILED -- flag=%d (s.b. 10)"", flag); +\t $finish; + end + + #10 if (flag != 20) begin +\t $display(""FAILED -- flag=%d (s.b. 20)"", flag); +\t $finish; + end + + #10 if (flag != 30) begin +\t $display(""FAILED -- flag=%d (s.b. 30)"", flag); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule +" +"module inner (); + initial + a.dump; +endmodule + +module outer (); + inner i (); + + generate + begin : a + task dump; + begin + $display (""PASSED""); + end + endtask + end + endgenerate +endmodule +" +"module main; + reg pass = 1\'b1; + + reg v1 = 1\'b0; + reg v2 = 1\'b0; + reg v3 = 1\'b0; + reg v4 = 1\'b0; + reg v5 = 1\'b0; + reg v6 = 1\'b0; + reg v7 = 1\'b0; + reg v8 = 1\'b0; + reg v9 = 1\'b0; + reg v10 = 1\'b0; + reg v11 = 1\'b0; + reg v12 = 1\'b0; + reg cond = 1\'b1; + reg [1:0] cval = 2\'b00; + + always #1 v1 = 1\'b1; + + always v2 = #1 1\'b1; + + always if (1\'b1) #1 v3 = 1\'b1; + + // This will pass since the else is optimized away! + always if (1\'b1) #1 v4 = 1\'b1; else v4 = 1\'b0; + + always if (cond) #1 v5 = 1\'b1; else #1 v5 = 1\'b0; + + always begin #1 v6 = 1\'b1; end // 1 + + always begin #1; v7 = 1\'b1; end // 2 + + always begin #0; #1 v8 = 1\'b1; end // 3 + + always begin if (cond) #1 v9 = 1\'b0; else v9 = 1\'b0; #1 v9 = 1\'b1; end // 4 + + always repeat(1) #1 v10 = 1\'b1; + + always case(cval) + 2\'b00: #1 v11 = 1\'b1; + 2\'b01: #1 v11 = 1\'bx; + default: #1 v11 = 1\'bz; + endcase + + always definite_delay; + + task definite_delay; + #1 v12 = 1\'b1; + endtask + + initial begin + #3; + if (v1 != 1\'b1) begin + $display(""Failed delayed assignment.""); + pass = 1\'b0; + end + + if (v2 != 1\'b1) begin + $display(""Failed intra-assignment delay.""); + pass = 1\'b0; + end + + if (v3 != 1\'b1) begin + $display(""Failed simple if statement.""); + pass = 1\'b0; + end + + if (v4 != 1\'b1) begin + $display(""Failed constant if/else statement.""); + pass = 1\'b0; + end + + if (v5 != 1\'b1) begin + $display(""Failed if/else statement.""); + pass = 1\'b0; + end + + if (v6 != 1\'b1) begin + $display(""Failed block (1).""); + pass = 1\'b0; + end + + if (v7 != 1\'b1) begin + $display(""Failed block (2).""); + pass = 1\'b0; + end + + if (v8 != 1\'b1) begin + $display(""Failed block (3).""); + pass = 1\'b0; + end + + if (v9 != 1\'b1) begin + $display(""Failed block (4).""); + pass = 1\'b0; + end + + if (v10 != 1\'b1) begin + $display(""Failed repeat.""); + pass = 1\'b0; + end + + if (v11 != 1\'b1) begin + $display(""Failed case.""); + pass = 1\'b0; + end + + if (v12 != 1\'b1) begin + $display(""Failed task.""); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + $finish; + end +endmodule +" +"module bts ( z , a , e); + inout z ; wire z ; + input a ; wire a ; + input e ; wire e ; + + assign #4 z= ( (e==1\'b1)? a : 1\'bz ); +endmodule + +module test(); + reg [1:0] aa; + wire [1:0] zz; + reg [1:0] ee; + + bts sub1 (.z(zz[1]), .a(aa[1]), .e(ee[1])); + bts sub0 (.z(zz[0]), .a(aa[0]), .e(ee[0])); + + + initial begin +// $dumpvars; + ee=2\'b00; + aa=2\'b00; #100; + if (zz !== 2\'bzz) begin + $display(""FAILED -- (1) All disabled, expected HiZ, got %b"", zz); + $finish; + end + aa=2\'b11; #100; + if (zz !== 2\'bzz) begin + $display(""FAILED -- (2) All disabled, expected HiZ, got %b"", zz); + $finish; + end + aa=2\'b00; #100; + if (zz !== 2\'bzz) begin + $display(""FAILED -- (3) All disabled, expected HiZ, got %b"", zz); + $finish; + end + aa=2\'b11; #100; + if (zz !== 2\'bzz) begin + $display(""FAILED -- (4) All disabled, expected HiZ, got %b"", zz); + $finish; + end + + ee=2\'b11; + aa=2\'b00; #100; + if (zz !== 2\'b00) begin + $display(""FAILED -- (5) All enabled, expected 00, got %b"", zz); + $finish; + end + aa=2\'b11; #100; + if (zz !== 2\'b11) begin + $display(""FAILED -- (6) All enabled, expected 11, got %b"", zz); + $finish; + end + aa=2\'b00; #100; + if (zz !== 2\'b00) begin + $display(""FAILED -- (7) All enabled, expected 00, got %b"", zz); + $finish; + end + aa=2\'b11; #100; + if (zz !== 2\'b11) begin + $display(""FAILED -- (8) All enabled, expected 11, got %b"", zz); + $finish; + end + + $display(""PASSED""); + end +endmodule +" +"// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for selected assignments. + +module vhdl_selected_test; +logic [1:0] sel; +logic [3:0] in; +logic out; +vhdl_selected dut(sel, in, out); + +initial begin + in = 4\'b1010; + + sel = 1\'b00; + #1; + if(out !== 1\'b0) begin + $display(""FAILED 1""); + $finish(); + end + + sel = 1\'b01; + #1; + if(out !== 1\'b1) begin + $display(""FAILED 2""); + $finish(); + end + + sel = 1\'b10; + #1; + if(out !== 1\'b0) begin + $display(""FAILED 3""); + $finish(); + end + + sel = 1\'b11; + #1; + if(out !== 1\'b1) begin + $display(""FAILED 4""); + $finish(); + end + + $display(""PASSED""); +end +endmodule +" +"module top; + parameter rval = 1.23456; + real rlv = 1.23456; + + initial begin + $display(""Real :%g: has a width of %0d."", rlv, $bits(rlv)); + $display(""Parameter real :%g: has a width of %0d."", rval, $bits(rval)); + $display(""Real constant :%g: has a width of %0d."", 1.23456, + $bits(1.23456)); + end +endmodule +" +"// Regression test for GitHub issue 14 : Bug in processing 1\'b1 >= |1\'bx. + +module bug(); + +wire y = 1\'b1 >= 1\'bx; + +initial begin + #0 $display(""%b"", y); + if (y !== 1\'bx) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module main; + + // Declare word1 as a VARIABLE + struct packed { + logic [7:0] high; + logic [7:0] low; + } word1; + + // Declare word2 as a VARIABLE + struct packed { + logic [7:0] high; + logic [7:0] low; + } word2; + + always @(word1) begin + word2.high = word1.high; + word2.low = word1.low; + end + + initial begin + word1 = 16\'haa_55; + if (word1.high !== 8\'haa || word1.low !== 8\'h55) begin +\t $display(""FAILED: word1 = %h, word1.high = %h, word1.low = %h"", +\t\t word1, word1.high, word1.low); +\t $finish; + end + + #1 /* Make sure word2 assign propagates */; + + if (word2.high !== 8\'haa || word2.low !== 8\'h55) begin +\t $display(""FAILED: word2 = %h, word2.high = %h, word2.low = %h"", +\t\t word1, word2.high, word2.low); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"module top; + localparam wid = 7; + localparam vec_wid = $clog2(wid+1)-1; + reg pass; + reg [vec_wid:0] mem [wid:0]; + reg [wid:0] sel; + wor [vec_wid:0] out; + integer lp; + genvar i; + + for (i = 0; i <= wid; i = i + 1) assign out = sel[i] ? mem[i] : {wid{1\'b0}}; + + initial begin + pass = 1\'b1; + + for (lp = 0; lp <= wid; lp = lp + 1) begin + mem[lp] = lp; + end + + for (lp = 0; lp <= wid; lp = lp + 1) begin + sel = 2**lp; + #1; + if (out !== mem[lp]) begin + $display(""FAILED: mem[%0d] %b != %b (%b)"", lp, mem[lp], out, sel); + pass = 1\'b0; + end else $display(""OK: mem[%0d] %b (%b)"", lp, out, sel); + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module modname; +`define macro1(arg1) $display(`""arg1`""); +`define macro2(arg1=d1, arg2) $display(`""arg1 arg2`""); + initial begin + `macro1(1) + + `macro2(1,2) + end +endmodule +" +"`timescale 1us/100ns + +module top; + reg pass = 1\'b1; + + reg [3:0] ia = 4\'d1, ib = 4\'d2; + wire signed [3:0] icon; + + assign #1 icon = {ib[1:0], ia[0]}; // Should give 5 after a delay. + + initial begin + #0.9; + if (icon !== 4\'bx) begin + pass = 1\'b0; + $display(""concatenation value not delayed, expected 4\'bx got %b."", icon); + end + + #0.1; + #0; + if (icon !== 4\'d5) begin + pass = 1\'b0; + $display(""concatenation value not correct, expected 4\'d5 got %d."", icon); + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"/* Copyright (C) 2000 Stephen G. Tell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ +/* fdisplay2 - test $fopen and $fdisplay system tasks */ + +module fdisplay2; + + integer fp, dfp; + reg [7:0] a; + + initial begin + fp = $fopen(""work/fdisplay2.out""); + if(fp != 2 && fp != 4 && fp != 8 && fp != 16 && fp != 32 && fp != 64) + begin +\t $display(""FAILED fopen fp=%d"", fp); +\t $finish; + end + + $fwrite(fp, ""hello, world\ +""); + a = 8\'hac; + + //$fdisplay(1|fp, ""a = %h; x: %b\ +"", a, a^8\'h0f); + dfp = 1|fp; + $fdisplay(dfp, ""a = \'h%h = \'b%b"", a, a); + + $finish; + end // initial begin + +endmodule +" +"module top; + event my_event; + + // The following two line should be an error + // You can not take the edge of a named event. + always @(posedge my_event) $display(""Posedge event.""); + always @(negedge my_event) $display(""Negedge event.""); + // This should work correctly. + always @(my_event) $display(""Any event edge.""); + + initial begin + #1 ->my_event; + #1 $display(""FAILED""); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue = @ (event_expression) boolean_expr +// + +module main ; + +reg [3:0] value1 ; +reg event_var ; + +initial +begin + # 2 ; + value1 = 5\'h 0 ; + # 3 ; + event_var = 1\'b0 ; + # 2 ; + value1 = 5\'h 0 ; + # 3 ; + event_var = 1\'b1 ; + #5 ; +end + +initial + begin\t\t\t// Should be xxxx at initial time + if(value1 !== 4\'bxxxx) +\t$display(""FAILED - always reg_lvalue = @ (event_expression) boolean_expr\ +""); + # 6 ; + if(value1 != 4\'h1)\t// Time 5 should see a change of 0 to 1 +\t$display(""FAILED - always reg_lvalue = @ (event_expression) boolean_expr\ +""); + # 5 ; + if(value1 != 4\'h1)\t// Time 5 should see a change of 0 to 1 +\t$display(""FAILED - always reg_lvalue = @ (event_expression) boolean_expr\ +""); + begin + $display(""PASSED\ +""); + $finish ; + end + end + +always value1 = @ (event_var) 1\'b1 && 1\'b1 ; + + +endmodule +" +"module test; + reg [19:0] x1; + initial + main; + task main; + begin +\t x1 = 20\'habcde; +\t $display(""x1: %h; x2: %h"", x1, (x1 - x1 - 1)); + end + endtask +endmodule // test +" +"module top; + reg [79:0] str; + + initial begin + $readmempath(str); + str = ""test""; + str[7:0] = \'d2; + $readmempath(str); + end +endmodule +" +"`timescale 1ns/10ps + +module TBUF_X2 (A, EN, Z); + input A; + input EN; + output Z; + + bufif1(Z, A, EN); + + specify + (A => Z) = (0.1, 0.2); + (EN => Z) = (0.3, 0.4); + endspecify +endmodule + +module ckt (out, in, en); + output out; + input in, en; + + TBUF_X2 dut (.A ( in ) , .EN ( en ) , .Z ( out ) ) ; +endmodule + +module top; + wire out; + reg in, en; + + ckt dut(out, in, en); + + initial begin + $monitor($realtime,,out,""="",in,,en); + $sdf_annotate(""ivltests/br960c.sdf"", dut); + in = 1\'b0; + en = 1\'b0; + $display(""Max (X->Z)""); + // X -> Z = max(enable)) + #10; + en = 1\'b1; + $display(""Z->0""); + #10; + en = 1\'b0; + $display(""0->Z""); + #5; + in = 1\'b1; + #5; + en = 1\'b1; + $display(""Z->1""); + #10; + en = 1\'b0; + $display(""1->Z""); + #10; + end +endmodule +" +"//// +//// The following was written to illustrate a bug in iverilog. +//// In particular, this little lovely produces a 202 MB vvp file. +//// + +module ExplodedArrays1; + + reg [7:0] data [0:25600-1]; + + integer idx; + initial begin + for (idx = 0 ; idx < 25600 ; idx = idx+1) + data[idx] = idx[7:0]; + + for (idx = 0 ; idx < 256 ; idx = idx+ 1) begin +\t if (data[idx] !== idx) begin +\t $display(""FAILED -- data[%d] = %d (%h)"", idx, data[idx], data[idx]); +\t $finish; +\t end + end + + $display(""PASSED""); + end // initial begin + +endmodule +" +"module top; + task automatic worker(int delay); + #delay $display(""worker finished at %0d."", delay); + endtask + + initial begin + fork + worker(10); + worker(5); + join_any + $display(""fork has joined (any)""); + if ($time != 5) begin + $display(""FAILED -- time=%0t"", $time); + $finish; + end + $display(""PASSED""); + end +endmodule +" +"module top; + parameter seeq1 = 6\'sb111000 === 4\'sb1000; + parameter seeqx = 6\'sbxxx000 === 4\'sbx000; + parameter seeqz = 6\'sbzzz000 === 4\'sbz000; + parameter seq1 = 6\'sb111000 == 4\'sb1000; + parameter seqx = 6\'sbxxx000 == 4\'sbx000; + parameter seqz = 6\'sbzzz000 == 4\'sbz000; + reg pass; + + initial begin + pass = 1\'b1; + + if (seeq1 !== 1\'b1) begin + $display(""FAILED: signed === (1), got %b"", seeq1); + pass = 1\'b0; + end + + if (seeqx !== 1\'b1) begin + $display(""FAILED: signed === (x), got %b"", seeqx); + pass = 1\'b0; + end + + if (seeqz !== 1\'b1) begin + $display(""FAILED: signed === (z), got %b"", seeqz); + pass = 1\'b0; + end + + if (seq1 !== 1\'b1) begin + $display(""FAILED: signed == (1), got %b"", seq1); + pass = 1\'b0; + end + + if (seqx !== 1\'bx) begin + $display(""FAILED: signed == (x), got %b"", seqx); + pass = 1\'b0; + end + + if (seqz !== 1\'bx) begin + $display(""FAILED: signed == (z), got %b"", seqz); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW - Validate always with OR, posedge constructs. +// +// D: New test used to validate always @(value), and +// D: always @(val1 or val2), and always @(posedge val1 or negedge val2) +// D: statements. +// +// + +module main (); +reg working; +reg val1, val2, val3, val4, val5; +reg clock ; +reg test_var; + +initial\t// Used to generate timing of events + begin + val2 = 0; + val3 = 0; + val4 = 1; + # 1; + test_var = 1; + # 1; + val1 = 1;\t\t// Cause a change in val1 -> test_var to 0. + # 2 ;\t\t// 4ns + test_var = 1; + # 1 ;\t\t// 5ns + val2 = 1;\t\t// Cause posedge on val2 -> test_var to 0 + # 2;\t\t// 7ns + test_var = 1; + # 1;\t\t// 8ns + val4 = 0;\t\t// Cause negedge on val4 -> test_var to 0 + # 2;\t\t// 10ns + test_var = 1; + # 1;\t\t// 11 ns + val3 = 1;\t\t// Cause val3 change for always @(a or b) + # 2;\t\t// 13 ns + test_var = 1; + # 1;\t\t// 14 ns + val5 = 1;\t\t// Cause val5 cahnge for always @(a or b) + # 2;\t\t// 16 ns + end + +always @(val1)\t// Val1 changing clears test_var + test_var = 0; + +always @(posedge val2 or negedge val4) + test_var = 0; + +always @(val3 or val5) + test_var = 0; + + +initial // This is the validation block + begin + # 3;\t// 3 ns Check always @(val) + if(test_var) + begin + $display(""FAILED - always @(val) wrong \ +""); + $finish ; + end + # 3;\t// 6 ns Check posedge of always @(posedge val or negedge) + if(test_var) + begin + $display(""FAILED - posedge of always @(posedge or negedge) wrong \ +""); + $finish ; + end + # 3;\t// 9 ns Check negedge of always @(posedge val or negedge) + if(test_var) + begin + $display(""FAILED - negedge of always @(posedge or negedge) wrong \ +""); + $finish ; + end + # 3;\t// 12 ns Check a of always @(a or b) + if(test_var) + begin + $display(""FAILED - a of always @(a or b) wrong \ +""); + $finish ; + end + # 3;\t// 15 ns Check b of always @(a or b) + if(test_var) + begin + $display(""FAILED - b of always @(a or b) wrong \ +""); + $finish ; + end + + $display(""PASSED\ +""); + $finish; + end + +always @ (posedge clock) + working = 1; + +always @ (negedge clock) + working = 1; + +endmodule +" +"module top; + initial fork : named_fork + $display(""PASSED""); + join : named_fork +endmodule +" +"module main; + + reg [6:0] bar; + wire [31:0] foo = {{25{1\'b0}}, bar}; + + initial begin + bar = 7\'b1111111; + #1 if (foo !== 32\'h00_00_00_7f) begin +\t $display(""FAILED -- foo=%h"", foo); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"module test(); + +wire a; + +tri0 b; +tri1 c; + +tri1 d; +tri0 e; + +wire f; +wire g; + +wire h; +wire i; + +tri1 j; +tri0 k; + +wire l; + +tri0 m; +tri1 n; + +assign d = 1\'b0; +assign e = 1\'b1; + +assign f = 1\'b0; +assign f = 1\'b1; + +assign g = 1\'b1; +assign g = 1\'b0; + +assign (strong1,strong0) h = 1\'b0; +assign ( weak1, weak0) h = 1\'b1; + +assign ( weak1, weak0) i = 1\'b0; +assign (strong1,strong0) i = 1\'b1; + +assign (pull1,pull0) j = 1\'b0; +assign (pull1,pull0) k = 1\'b1; + +wire [1:0] A = {1\'b1, a}; +wire [1:0] B = {1\'b1, b}; +wire [1:0] C = {1\'b1, c}; +wire [1:0] D = {1\'b1, d}; +wire [1:0] E = {1\'b1, e}; +wire [1:0] F = {1\'b1, f}; +wire [1:0] G = {1\'b1, g}; +wire [1:0] H = {1\'b1, h}; +wire [1:0] I = {1\'b1, i}; +wire [1:0] J = {1\'b1, j}; +wire [1:0] K = {1\'b1, k}; +wire [1:0] L = {1\'b1, l}; +wire [1:0] M = {1\'b1, m}; +wire [1:0] N = {1\'b1, n}; + +reg failed; + +initial begin + failed = 0; #1; + + $display(""A = %b, expect 1z"", A); if (A !== 2\'b1z) failed = 1; + $display(""B = %b, expect 10"", B); if (B !== 2\'b10) failed = 1; + $display(""C = %b, expect 11"", C); if (C !== 2\'b11) failed = 1; + $display(""D = %b, expect 10"", D); if (D !== 2\'b10) failed = 1; + $display(""E = %b, expect 11"", E); if (E !== 2\'b11) failed = 1; + $display(""F = %b, expect 1x"", F); if (F !== 2\'b1x) failed = 1; + $display(""G = %b, expect 1x"", G); if (G !== 2\'b1x) failed = 1; + $display(""H = %b, expect 10"", H); if (H !== 2\'b10) failed = 1; + $display(""I = %b, expect 11"", I); if (I !== 2\'b11) failed = 1; + $display(""J = %b, expect 1x"", J); if (J !== 2\'b1x) failed = 1; + $display(""K = %b, expect 1x"", K); if (K !== 2\'b1x) failed = 1; + force l = 1\'b0; #1; + $display(""L = %b, expect 10"", L); if (L !== 2\'b10) failed = 1; + force l = 1\'b1; #1; + $display(""L = %b, expect 11"", L); if (L !== 2\'b11) failed = 1; + force m = 1\'b1; #1; + $display(""M = %b, expect 11"", M); if (M !== 2\'b11) failed = 1; + force n = 1\'b0; #1; + $display(""N = %b, expect 10"", N); if (N !== 2\'b10) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"timeunit 100ps / 10ps; + +package testpackage; + task delay(output [63:0] t); + begin + $printtimescale(top); + $printtimescale; + #5ns t = $time; + end + endtask +endpackage + +module top(); + +timeunit 1ns / 1ps; + +import testpackage::delay; + +reg [63:0] t1; +reg [63:0] t2; + +initial begin + $printtimescale; + delay(t1); + t2 = $time; + $display(""%0d %0d"", t1, t2); + if ((t1 === 50) && (t2 === 5)) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module test(); + +reg [] illegal; + +endmodule +" +"// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +module br987_test; +logic clk, trig, data_o; +bug5 dut(clk, trig, data_o); + +initial begin + trig = 1; + clk = 0; + #1 clk = ~clk; + #1 clk = ~clk; + $display(""PASSED""); +end + +endmodule +" +"module test; + parameter j=0; + + reg [3:0] in [7:0]; + wire [3:0] out [7:0]; + + assign out[(j+1)*4 - 1 : j*4] = in[j]; +// assign out[j] = in[j]; // This is what was probably wanted. + + initial $display(""out[0]: %b"", out[0]); + +endmodule +" +"// +// Copyright (c) 1999 Peter Monta (pmonta@imedia.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module main; + reg [3:0] a; + wire b; + + assign b = !a; + + initial begin + a = 4\'d1; + #1; + if (b!==0) begin + $display(""FAILED""); + $finish; + end + a = 4\'d0; + #1; + if (b!==1) begin + $display(""FAILED""); + $finish; + end + $display(""PASSED""); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate task with internal delay + + +module main; + +reg var1,var2; +reg in1; +reg error; + +task my_task ; + input in1; + output out1; + out1 = #10 in1; +endtask + +initial + begin + var1 = 0; + error = 0; + fork + my_task(1\'b1,var1); + begin + if(var1 != 1\'b0) + begin + $display(""FAILED - task3.14F Task with internal delay(1)""); + error = 1; + end + #20; + if(var1 != 1\'b1) + begin + $display(""FAILED - task3.14F Task with internal delay(2)""); + error = 1; + end + end + join + if(error == 0) + $display(""PASSED""); + end + +endmodule // main +" +"module test; + reg pass; + reg [8*40:1] str; + integer s; + reg [31:0] su; + integer res; + + initial begin + pass = 1\'b1; + s = 2000; + su = 2000; + + res = s + (1 << 3) - 1; + if (res !== 2007) begin + $display(""FAILED first term << (s), expected 2007, got %d"", res); + pass = 1\'b0; + end + res = su + (1 << 3) - 1; + if (res !== 2007) begin + $display(""FAILED first term << (su), expected 2007, got %d"", res); + pass = 1\'b0; + end + + res = s + (16 >> 1) - 1; + if (res !== 2007) begin + $display(""FAILED first term >> (s), expected 2007, got %d"", res); + pass = 1\'b0; + end + res = su + (16 >> 1) - 1; + if (res !== 2007) begin + $display(""FAILED first term >> (su), expected 2007, got %d"", res); + pass = 1\'b0; + end + + res = (s + (1 << 3) - 1) * 16000; + if (res !== 32112000) begin + $display(""FAILED second term << (s), expected 32112000, got %d"", res); + pass = 1\'b0; + end + res = (su + (1 << 3) - 1) * 16000; + if (res !== 32112000) begin + $display(""FAILED second term << (su), expected 32112000, got %d"", res); + pass = 1\'b0; + end + + res = (s + (16 >> 1) - 1) * 16000; + if (res !== 32112000) begin + $display(""FAILED second term >> (s), expected 32112000, got %d"", res); + pass = 1\'b0; + end + res = (su + (16 >> 1) - 1) * 16000; + if (res !== 32112000) begin + $display(""FAILED second term >> (su), expected 32112000, got %d"", res); + pass = 1\'b0; + end + + $sformat(str, ""%0d"", s + (1 << 3) - 1); + if (str[8*4:1] !== ""2007"" || str[8*40:8*4+1] !== 0) begin + $display(""FAILED first string << (s), expected \\""2007\\"", got %s"", str); + pass = 1\'b0; + end + $sformat(str, ""%0d"", su + (1 << 3) - 1); + if (str[8*4:1] !== ""2007"" || str[8*40:8*4+1] !== 0) begin + $display(""FAILED first string << (su), expected \\""2007\\"", got %s"", str); + pass = 1\'b0; + end + + $sformat(str, ""%0d"", s + (16 >> 1) - 1); + if (str[8*4:1] !== ""2007"" || str[8*40:8*4+1] !== 0) begin + $display(""FAILED first string >> (s), expected \\""2007\\"", got %s"", str); + pass = 1\'b0; + end + $sformat(str, ""%0d"", su + (16 >> 1) - 1); + if (str[8*4:1] !== ""2007"" || str[8*40:8*4+1] !== 0) begin + $display(""FAILED first string >> (su), expected \\""2007\\"", got %s"", str); + pass = 1\'b0; + end + + $sformat(str, ""%0d"", (s + (1 << 3) - 1) * 16000); + if (str[8*8:1] !== ""32112000"" || str[8*40:8*8+1] !== 0) begin + $display(""FAILED second string << (s), expected \\""32112000\\"", got %s"", + str); + pass = 1\'b0; + end + $sformat(str, ""%0d"", (su + (1 << 3) - 1) * 16000); + if (str[8*8:1] !== ""32112000"" || str[8*40:8*8+1] !== 0) begin + $display(""FAILED second string << (su), expected \\""32112000\\"", got %s"", + str); + pass = 1\'b0; + end + + $sformat(str, ""%0d"", (s + (16 >> 1) - 1) * 16000); + if (str[8*8:1] !== ""32112000"" || str[8*40:8*8+1] !== 0) begin + $display(""FAILED second string >> (s), expected \\""32112000\\"", got %s"", + str); + pass = 1\'b0; + end + $sformat(str, ""%0d"", (su + (16 >> 1) -1) * 16000); + if (str[8*8:1] !== ""32112000"" || str[8*40:8*8+1] !== 0) begin + $display(""FAILED second string >> (su), expected \\""32112000\\"", got %s"", + str); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module bug(); + +reg [3:0] flags = 4\'b0000; + +generate + genvar i; + + for (i = 1; i < 4; i = i + 1) begin:loop + localparam j = i; + + if (j > 0) begin + initial #1 flags[j] = 1\'b1; + end + end +endgenerate + +initial begin + #2 $display(""flags = %b"", flags); + if (flags === 4\'b1110) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module bug(); + +reg [2:1][16:1][8:1] array; + +reg failed = 0; + +integer i; + +reg [3:0] index; + +initial begin + i = $bits(array); + $display(""width 0 = %0d"", i); + if (i !== 256) failed = 1; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + i = $bits(array[0]); +`else + i = $bits(array[1]); +`endif + $display(""width 1 = %0d"", i); + if (i !== 128) failed = 1; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + i = $bits(array[0][0]); +`else + i = $bits(array[1][1]); +`endif + $display(""width 2 = %0d"", i); + if (i !== 8) failed = 1; + + for (i = 0; i < 16; i++) begin + index = i[3:0]; + array[1][5\'d1+index] = {4\'d0, index}; + array[2][5\'d1+index] = {4\'d1, index}; + end + $display(""%h"", array); + if (array !== 256\'h1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09080706050403020100) + failed = 1; + for (i = 0; i < 16; i++) begin + index = i[3:0]; + $display(""%h : %h %h"", index, array[1][5\'d1+index], array[2][5\'d1+index]); + if (array[1][5\'d1+index] !== {4\'d0, index}) failed = 1; + if (array[2][5\'d1+index] !== {4\'d1, index}) failed = 1; + end + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module main; + + wire eq1, eq2, eq5; + wire ne1, ne2, ne5; + + reg [7:0] x, y; + + eqne dut(.eq1(eq1), .eq2(eq2), .eq5(eq5), +\t .ne1(ne1), .ne2(ne2), .ne5(ne5), +\t .x(x), .y(y)); + + initial begin + for (x = 0 ; x < \'h20 ; x = x+1) +\tfor (y = 0 ; y < \'h20 ; y = y+1) begin +\t #1 $display(""x=%h, y=%h: "", x, y, +\t\t ""eq1=%b, eq2=%b, eq5=%b, "", eq1, eq2, eq5, +\t\t ""ne1=%b, ne2=%b, ne5=%b"", ne1, ne2, ne5); +\t if (eq1 !== (x[0] == y[0])) begin +\t $display(""FAILED""); +\t $finish; +\t end + +\t if (eq2 !== (x[1:0] == y[1:0])) begin +\t $display(""FAILED""); +\t $finish; +\t end + +\t if (eq5 !== (x[4:0] == y[4:0])) begin +\t $display(""FAILED""); +\t $finish; +\t end + +\t if (ne1 !== (x[0] != y[0])) begin +\t $display(""FAILED""); +\t $finish; +\t end + +\t if (ne2 !== (x[1:0] != y[1:0])) begin +\t $display(""FAILED""); +\t $finish; +\t end + +\t if (ne5 !== (x[4:0] != y[4:0])) begin +\t $display(""FAILED""); +\t $finish; +\t end +\tend + + $display(""PASSED""); + end + +endmodule // main +" +"module main; + parameter [15:0] a = 16\'h8421; + reg [3:0] b, c; + reg pass; + + always @* begin + b = a[c+:4]; +// $display($time, "" c: %d, b: %h"", c, b); + end + + initial begin + pass = 1\'b1; + c = 0; + #1 if (b !== 4\'d1) begin + $display(""FAILED: c = 0, expected 1, got %0d"", b); + pass = 1\'b0; + end + + #9 c = 4; + #1 if (b !== 4\'d2) begin + $display(""FAILED: c = 4, expected 2, got %0d"", b); + pass = 1\'b0; + end + + #9 c = 8; + #1 if (b !== 4\'d4) begin + $display(""FAILED: c = 8, expected 4, got %0d"", b); + pass = 1\'b0; + end + + #9 c = 12; + #1 if (b !== 4\'d8) begin + $display(""FAILED: c = 12, expected 8, got %0d"", b); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"// +// Copyright (c) 2001 Ed Schwartz (schwartz@r11.ricoh.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Verify PR142 - Added something to print PASSED.. + +module testit; + + reg clk; + reg [2:0] cnt; + + always + begin + # 50 clk = ~clk; + end // always begin + + task idle; + input [15:0] waitcnt; + + begin: idletask + // begin + integer i; + for (i=0; i < waitcnt; i = i + 1) + begin + @ (posedge clk); + + end // for (i=0; i < waitcnt; i = i + 1) + + end + endtask // idle + + initial begin + clk = 0; + cnt = 0; + $display (""One""); + cnt = cnt + 1; + idle(3); + cnt = cnt + 1; + $display (""Two""); + if(cnt === 2) + $display(""PASSED""); + else + $display(""FAILED""); + $finish; + end + +endmodule +" +"module test4; + reg r; +endmodule + +module test3; + test4 test4(); +endmodule + +module test2; + initial begin +\t$dumpvars(1, test3.test4); + end + test3 test3(); +endmodule + +module test; + initial begin +\t$dumpfile(""work/dumpfile.vcd""); +\t$dumpvars(1, test2.test3); +\t$display(""PASSED""); + end + test2 test2(); +endmodule +" +"/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: ldelay3.v,v 1.2 2007/12/06 02:31:10 stevewilliams Exp $ + +// Test for delays in structural logic. timescale + +`timescale 1ns/100ps + +module test; + + wire q; + reg a, b; + gate gg (q, a, b); + + task ok; + input qq; + reg error; + begin +\t if (q !== qq) +\t begin +\t error = 1; +\t $display(""%0d: FAILED: q=%b, expect %b"", $time, q, qq); +\t end + end + endtask + + initial + begin +\tok.error = 0; +//\t$dumpvars; +\ta <= 0; +\tb <= 1; +\t#5.5 ok(1\'b x); +\t#0.1 ok(1\'b 0); +\ta <= 1; +\t#5.5 ok(1\'b 0); +\t#0.1 ok(1\'b 1); +\ta <= 0; +\t#3 ok(1\'b 1); +\ta <= 1; +\t#1 ok(1\'b 1); +\t#1 ok(1\'b 1); +\t#1 ok(1\'b 1); +\t#1 ok(1\'b 1); +\t#1 ok(1\'b 1); +\t#1 ok(1\'b 1); +\t#1 ok(1\'b 1); +\tif (!ok.error) +\t $display(""PASSED""); + end + +endmodule + +`timescale 1ps/1ps + +module gate(q, a, b); + output q; + input a, b; + + and #5555 (q, a, b); +endmodule +" +" + +`define FOO(val=42, text=""42"") do_foo(val, text) + +module main; + + int ref_val; + string ref_text; + task do_foo(int val, string text); + if (val!=ref_val || text!=ref_text) begin +\t $display(""FAILED -- val=%d (expect %d), text=%0s, (expect %0s)"", +\t\t val, ref_val, text, ref_text); +\t $finish; + end + endtask // do_foo + + initial begin + ref_val = 42; + ref_text = ""42""; + `FOO(,); + + ref_val = 42; + ref_text = ""41""; + `FOO(,""41""); + + ref_val = 41; + ref_text = ""42""; + `FOO(41,); + + ref_val = 41; + ref_text = ""41""; + `FOO(41,""41""); + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"// pr1946411 + +module test(); + localparam integer a = 99; + + initial begin + if (a !== 99) begin +\t $display(""FAILED -- a = %d"", a); +\t $finish; + end + $display(""PASSED\ +""); + end + +endmodule +" +"module top; + wire [1:0] out; + reg [1:0] in1, in2; + + initial begin + $monitor($time,,""out=%d"", out); + in1 = 2\'d1; + in2 = 2\'d2; + #1 force out = in1; + #1 force out = in2; + #1 release out; + end +endmodule +" +"`begin_keywords ""1364-2005"" +/* + * This tests the synthesis of a case statement that has an empty case. + */ +module main; + + reg bit, foo; + + // Combinational device that sends 1 or 0 to foo, to follow bit. + always @* + begin +\tfoo = 0; +\tcase (bit) +\t 1\'b0: ; +\t 1\'b1: foo = 1; +\tendcase // case(bit) + end + + (* ivl_synthesis_off *) + initial begin + bit = 0; + + # 6 $display(""bit=%b, foo=%b"", bit, foo); + if (bit !== 0 || foo !== 0) begin +\t $display(""FAILED""); +\t $finish; + end + + bit <= 1; + #10 $display(""bit=%b, foo=%b"", bit, foo); + if (bit !== 1 || foo !== 1) begin +\t $display(""FAILED""); +\t $finish; + end + + $display(""PASSED""); + $finish; + end + +endmodule // main +`end_keywords +" +"module test; + + reg cp; + reg\td; + wire q; + + dff ff(q, cp, d); + + always begin #5 cp=0; #5 cp=1; end + + always + begin +\t@(negedge cp) +\t d <= ~d; + +\t@(posedge cp) +\t if (q !== \'bx && d === q) +\t begin +\t $display(""FAILED, d=%b, q=%b"", d, q); +\t #1 $finish; +\t end + end + + initial + begin +\t#1 d <= 1; +\t#22; +\t$display(""PASSED""); +\t$finish; + end + + initial $monitor($time,,cp,,d,,q); + +endmodule + +primitive dff(q, cp, d); + output q; + input cp, d; + reg\t q; + + table + // (cp) d : q : q ; + ? * : ? : - ; + (?0) ? : ? : - ; + (1x) ? : ? : - ; + (x1) 0 : 0 : 0 ; + (x1) 1 : 1 : 1 ; + (0x) 0 : 0 : 0 ; + (0x) 1 : 1 : 1 ; + (01) 0 : ? : 0 ; + (01) 1 : ? : 1 ; + endtable + +endprimitive +" +"/*************************************************************** +** Author: Oswaldo Cadenas (oswaldo.cadenas@gmail.com) +** Date: September 26 2011 +** +** Test: Intended to test parametric counter in timebase.vhd +** the counter has parameters: N for counter length and + VALUE to flag when the count reaches this value +** +** Four counter instances are created here: +** duv1 with counter default parameters for N and VALUE +** duv2 with N1, V1 for parameter N, VALUE respectively +** duv3 with N2, V2 for parameters N, VALUE respectively +** duv4 with N2 replacing N and VALUE left as default +** +** The test for a long time making sure each of the four counter flags TICK become one +**************************************************************************************/ + +module test; + parameter integer T = 25; + parameter integer N1 = 8; + parameter integer N2 = 17; + parameter integer V1 = 200; + parameter integer V2 = 17\'h16C8A; + + bit clk = 0, reset = 0; + wire [11:0] count1; + wire [N1-1:0] count2; + wire [N2-1:0] count3; + wire [N2-1:0] count4; + + wire tick1, tick2, tick3, tick4; + reg tick1_reg, tick2_reg, tick3_reg, tick4_reg; + + initial forever #(T) clk = !clk; + + + initial begin + @(negedge clk); + reset = 1\'b1; + repeat(6) @(negedge clk); + reset = 1\'b0; + end + + // duv1 switch + always @(posedge clk, posedge reset) +\tif (reset) tick1_reg <= 1\'b0; +\telse if (tick1) tick1_reg <= 1\'b1; + + // duv2 switch + always @(posedge clk, posedge reset) +\tif (reset) tick2_reg <= 1\'b0; +\telse if (tick2) tick2_reg <= 1\'b1; + + // duv3 switch + always @(posedge clk, posedge reset) +\tif (reset) tick3_reg <= 1\'b0; +\telse if (tick3) tick3_reg <= 1\'b1; + + // duv4 switch + always @(posedge clk, posedge reset) +\tif (reset) tick4_reg <= 1\'b0; +\telse if (tick4) tick4_reg <= 1\'b1; + + initial begin + #(V2*2*T + 1000); + if (tick1_reg != 1 || tick2_reg != 1 || tick3_reg != 1 || tick4_reg != 1) begin + $display (""Counting FAILED""); + $finish; + end + else begin + $display (""PASSED""); + #20; + $finish; + end +end + + timebase duv1 (.clock(clk), .reset(reset), .enable(1\'b1), .tick(tick1), .count_value(count1) ); // default parameters + timebase #(.n(N1), .value(V1)) + duv2 (.clock(clk), .reset(reset), .enable(1\'b1), .tick(tick2), .count_value(count2) ); // N1, V1 parameters + timebase #(N2, V2) + duv3 (.clock(clk), .reset(reset), .enable(1\'b1), .tick(tick3), .count_value(count3) ); // N2, V2 parameters + timebase #(.n(N2)) + duv4 (.clock(clk), .reset(reset), .enable(1\'b1), .tick(tick4), .count_value(count4) ); // only one parameter modified + +endmodule +" +"module dut(input [3:0] DataI, output [3:0] DataO); + +wire [3:0] DataI; +reg [3:0] DataO; + +always @* DataO = DataI; + +endmodule + +module top(); + +reg [3:0] DataI; +wire [3:0] DataO; + +dut dut(DataI, DataO); + +initial begin + DataI = 5; + #1; + if (DataO === 5) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module automatic_task(); + +task automatic fill_array; + +input [7:0] value; + +reg [7:0] array[3:0]; + +integer i; + +fork + begin + #10 array[0] = value; + #10 array[1] = array[0]; + #10 array[2] = array[1]; + #10 array[3] = array[2]; + end + begin + @(array[0]) $display(array[0], array[1], array[2], array[3]); + @(array[1]) $display(array[0], array[1], array[2], array[3]); + @(array[2]) $display(array[0], array[1], array[2], array[3]); + @(array[3]) $display(array[0], array[1], array[2], array[3]); + end +join + +endtask + +initial #1 fill_array(1); +initial #2 fill_array(2); + +endmodule +" +"// Module to test the messages for out of bound R-value part selects. + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + reg big_param; + reg [1:0] part; + integer idx; + + parameter pvar0 = 0; + parameter pvar1 = 1; + parameter pvar2 = -1; + parameter pvar3 = 4\'b0001; + parameter [4:1] pvar4 = 4\'b0001; + parameter [1:4] pvar5 = 4\'b0001; + reg [4:1] rvar = 4\'b1000; + reg [1:4] rvar2 = 4\'b1000; + reg [4:1] ravar [2:1]; + reg [1:4] ravar2 [2:1]; + wire [4:1] wvar = 4\'b1010; + wire [1:4] wvar2 = 4\'b1010; + wire [4:1] wavar [2:1]; + wire [1:4] wavar2 [2:1]; + + assign wavar[1] = 4\'b0111; + assign wavar[2] = 4\'b1110; + assign wavar2[1] = 4\'b0111; + assign wavar2[2] = 4\'b1110; + + initial begin + pass = 1\'b1; + ravar[1] = 4\'b0111; + ravar[2] = 4\'b1110; + ravar2[1] = 4\'b0111; + ravar2[2] = 4\'b1110; + #1; + + // Icarus supports an unlimited size for unsized parameters. The + // following checks the 33rd bit to see if it is 1\'bx. If so we + // assume that the simulator only support 32 bit, otherwise we + // modify our after check for unsized parameters to work (pass) + // with a larger constant. + big_param = 1\'b1; + idx = 32; + if (pvar0[idx] === 1\'bx) big_param = 1\'b0; + + // Check a parameter with default size equal to 0. + part = pvar0[31:30]; // At end + if (part !== 2\'b00) begin + $display(""Failed at end part select of a parameter (0), got %b"", part); + pass = 1\'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = pvar0[33:32]; // May be after all + if (part !== (big_param ? 2\'b00: 2\'bxx)) begin + $display(""Failed after part select of a parameter (0), got %b"", part); + pass = 1\'b0; + end + part = pvar0[32:31]; // May be partial after + if (part !== (big_param ? 2\'b00 : 2\'bx0)) begin + $display(""Failed partial after part select of a parameter (0), got %b"", + part); + pass = 1\'b0; + end + part = pvar0[-1:-2]; // Before all + if (part !== 2\'bxx) begin + $display(""Failed before part select of a parameter (0), got %b"", part); + pass = 1\'b0; + end + part = pvar0[0:-1]; // Partial before + if (part !== 2\'b0x) begin + $display(""Failed partial before part select of a parameter (0), got %b"", + part); + pass = 1\'b0; + end + part = pvar0[1\'bx:1]; // Undefined 1st + if (part !== 2\'bxx) begin + $display(""Failed undefined 1st part select of a parameter (0), got %b"", + part); + pass = 1\'b0; + end + part = pvar0[1:1\'bx]; // Undefined 2nd + if (part !== 2\'bxx) begin + $display(""Failed undefined 2nd part select of a parameter (0), got %b"", + part); + pass = 1\'b0; + end + part = pvar0[1\'bz:1]; // High-Z 1st + if (part !== 2\'bxx) begin + $display(""Failed high-Z 1st part select of a parameter (0), got %b"", + part); + pass = 1\'b0; + end + part = pvar0[1:1\'bz]; // High-Z 2nd + if (part !== 2\'bxx) begin + $display(""Failed high-Z 2nd part select of a parameter (0), got %b"", + part); + pass = 1\'b0; + end +`endif + + // Check a parameter with default size equal to 1. + part = pvar1[31:30]; // At end + if (part !== 2\'b00) begin + $display(""Failed at end part select of a parameter (1), got %b"", part); + pass = 1\'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = pvar1[33:32]; // May be after all + if (part !== (big_param ? 2\'b00: 2\'bxx)) begin + $display(""Failed after part select of a parameter (1), got %b"", part); + pass = 1\'b0; + end + part = pvar1[32:31]; // May be partial after + if (part !== (big_param ? 2\'b00 : 2\'bx0)) begin + $display(""Failed partial after part select of a parameter (1), got %b"", + part); + pass = 1\'b0; + end + part = pvar1[-1:-2]; // Before all + if (part !== 2\'bxx) begin + $display(""Failed before part select of a parameter (1), got %b"", part); + pass = 1\'b0; + end + part = pvar1[0:-1]; // Partial before + if (part !== 2\'b1x) begin + $display(""Failed partial before part select of a parameter (1), got %b"", + part); + pass = 1\'b0; + end + part = pvar1[1\'bx:1]; // Undefined 1st + if (part !== 2\'bxx) begin + $display(""Failed undefined 1st part select of a parameter (1), got %b"", + part); + pass = 1\'b0; + end + part = pvar1[1:1\'bx]; // Undefined 2nd + if (part !== 2\'bxx) begin + $display(""Failed undefined 2nd part select of a parameter (1), got %b"", + part); + pass = 1\'b0; + end + part = pvar1[1\'bz:1]; // High-Z 1st + if (part !== 2\'bxx) begin + $display(""Failed high-Z 1st part select of a parameter (1), got %b"", + part); + pass = 1\'b0; + end + part = pvar1[1:1\'bz]; // High-Z 2nd + if (part !== 2\'bxx) begin + $display(""Failed high-Z 2nd part select of a parameter (1), got %b"", + part); + pass = 1\'b0; + end +`endif + + // Check a parameter with default size equal to -1. + part = pvar2[31:30]; // At end + if (part !== 2\'b11) begin + $display(""Failed at end part select of a parameter (2), got %b"", part); + pass = 1\'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = pvar2[33:32]; // May be after all + if (part !== (big_param ? 2\'b11: 2\'bxx)) begin + $display(""Failed after part select of a parameter (2), got %b"", part); + pass = 1\'b0; + end + part = pvar2[32:31]; // May be partial after + if (part !== (big_param ? 2\'b11 : 2\'bx1)) begin + $display(""Failed partial after part select of a parameter (2), got %b"", + part); + pass = 1\'b0; + end + part = pvar2[-1:-2]; // Before all + if (part !== 2\'bxx) begin + $display(""Failed before part select of a parameter (2), got %b"", part); + pass = 1\'b0; + end + part = pvar2[0:-1]; // Partial before + if (part !== 2\'b1x) begin + $display(""Failed partial before part select of a parameter (2), got %b"", + part); + pass = 1\'b0; + end + part = pvar2[1\'bx:1]; // Undefined 1st + if (part !== 2\'bxx) begin + $display(""Failed undefined 1st part select of a parameter (2), got %b"", + part); + pass = 1\'b0; + end + part = pvar2[1:1\'bx]; // Undefined 2nd + if (part !== 2\'bxx) begin + $display(""Failed undefined 2nd part select of a parameter (2), got %b"", + part); + pass = 1\'b0; + end + part = pvar2[1\'bz:1]; // High-Z 1st + if (part !== 2\'bxx) begin + $display(""Failed high-Z 1st part select of a parameter (2), got %b"", + part); + pass = 1\'b0; + end + part = pvar2[1:1\'bz]; // High-Z 2nd + if (part !== 2\'bxx) begin + $display(""Failed high-Z 2nd part select of a parameter (2), got %b"", + part); + pass = 1\'b0; + end +`endif + + // Check a parameter with size four from the value. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = pvar3[5:4]; // After all + if (part !== 2\'bxx) begin + $display(""Failed after part select of a parameter (3), got %b"", part); + pass = 1\'b0; + end + part = pvar3[4:3]; // Partial after + if (part !== 2\'bx0) begin + $display(""Failed partial after part select of a parameter (3), got %b"", + part); + pass = 1\'b0; + end + part = pvar3[-1:-2]; // Before all + if (part !== 2\'bxx) begin + $display(""Failed before part select of a parameter (3), got %b"", part); + pass = 1\'b0; + end + part = pvar3[0:-1]; // Partial before + if (part !== 2\'b1x) begin + $display(""Failed partial before part select of a parameter (3), got %b"", + part); + pass = 1\'b0; + end + part = pvar3[1\'bx:1]; // Undefined 1st + if (part !== 2\'bxx) begin + $display(""Failed undefined 1st part select of a parameter (3), got %b"", + part); + pass = 1\'b0; + end + part = pvar3[1:1\'bx]; // Undefined 2nd + if (part !== 2\'bxx) begin + $display(""Failed undefined 2nd part select of a parameter (3), got %b"", + part); + pass = 1\'b0; + end + part = pvar3[1\'bz:1]; // High-Z 1st + if (part !== 2\'bxx) begin + $display(""Failed high-Z 1st part select of a parameter (3), got %b"", + part); + pass = 1\'b0; + end + part = pvar3[1:1\'bz]; // High-Z 2nd + if (part !== 2\'bxx) begin + $display(""Failed high-Z 2nd part select of a parameter (3), got %b"", + part); + pass = 1\'b0; + end +`endif + + // Check a parameter with size four from the range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = pvar4[6:5]; // After all + if (part !== 2\'bxx) begin + $display(""Failed after part select of a parameter (4), got %b"", part); + pass = 1\'b0; + end + part = pvar4[5:4]; // Partial after + if (part !== 2\'bx0) begin + $display(""Failed partial after part select of a parameter (4), got %b"", + part); + pass = 1\'b0; + end + part = pvar4[0:-1]; // Before all + if (part !== 2\'bxx) begin + $display(""Failed before part select of a parameter (4), got %b"", part); + pass = 1\'b0; + end + part = pvar4[1:0]; // Partial before + if (part !== 2\'b1x) begin + $display(""Failed partial before part select of a parameter (4), got %b"", + part); + pass = 1\'b0; + end + part = pvar4[1\'bx:1]; // Undefined 1st + if (part !== 2\'bxx) begin + $display(""Failed undefined 1st part select of a parameter (4), got %b"", + part); + pass = 1\'b0; + end + part = pvar4[1:1\'bx]; // Undefined 2nd + if (part !== 2\'bxx) begin + $display(""Failed undefined 2nd part select of a parameter (4), got %b"", + part); + pass = 1\'b0; + end + part = pvar4[1\'bz:1]; // High-Z 1st + if (part !== 2\'bxx) begin + $display(""Failed high-Z 1st part select of a parameter (4), got %b"", + part); + pass = 1\'b0; + end + part = pvar4[1:1\'bz]; // High-Z 2nd + if (part !== 2\'bxx) begin + $display(""Failed high-Z 2nd part select of a parameter (4), got %b"", + part); + pass = 1\'b0; + end +`endif + + // Check a parameter with size four from the range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = pvar5[-1:0]; // After all + if (part !== 2\'bxx) begin + $display(""Failed after part select of a parameter (5), got %b"", part); + pass = 1\'b0; + end + part = pvar5[0:1]; // Partial after + if (part !== 2\'bx0) begin + $display(""Failed partial after part select of a parameter (5), got %b"", + part); + pass = 1\'b0; + end + part = pvar5[5:6]; // Before all + if (part !== 2\'bxx) begin + $display(""Failed before part select of a parameter (5), got %b"", part); + pass = 1\'b0; + end + part = pvar5[4:5]; // Partial before + if (part !== 2\'b1x) begin + $display(""Failed partial before part select of a parameter (5), got %b"", + part); + pass = 1\'b0; + end + part = pvar5[1\'bx:1]; // Undefined 1st + if (part !== 2\'bxx) begin + $display(""Failed undefined 1st part select of a parameter (5), got %b"", + part); + pass = 1\'b0; + end + part = pvar5[1:1\'bx]; // Undefined 2nd + if (part !== 2\'bxx) begin + $display(""Failed undefined 2nd part select of a parameter (5), got %b"", + part); + pass = 1\'b0; + end + part = pvar5[1\'bz:1]; // High-Z 1st + if (part !== 2\'bxx) begin + $display(""Failed high-Z 1st part select of a parameter (5), got %b"", + part); + pass = 1\'b0; + end + part = pvar5[1:1\'bz]; // High-Z 2nd + if (part !== 2\'bxx) begin + $display(""Failed high-Z 2nd part select of a parameter (5), got %b"", + part); + pass = 1\'b0; + end +`endif + + + // Check a register with range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = rvar[6:5]; // After all + if (part !== 2\'bxx) begin + $display(""Failed after part select of a register, got %b"", part); + pass = 1\'b0; + end + part = rvar[5:4]; // Partial after + if (part !== 2\'bx1) begin + $display(""Failed partial after part select of a register, got %b"", part); + pass = 1\'b0; + end + part = rvar[0:-1]; // Before all + if (part !== 2\'bxx) begin + $display(""Failed before part select of a register, got %b"", part); + pass = 1\'b0; + end + part = rvar[1:0]; // Partial before + if (part !== 2\'b0x) begin + $display(""Failed partial before part select of a register, got %b"", part); + pass = 1\'b0; + end + part = rvar[1\'bx:1]; // Undefined 1st + if (part !== 2\'bxx) begin + $display(""Failed undefined 1st part select of a register, got %b"", part); + pass = 1\'b0; + end + part = rvar[1:1\'bx]; // Undefined 2nd + if (part !== 2\'bxx) begin + $display(""Failed undefined 2nd part select of a register, got %b"", part); + pass = 1\'b0; + end + part = rvar[1\'bz:1]; // High-Z 1st + if (part !== 2\'bxx) begin + $display(""Failed high-Z 1st part select of a register, got %b"", part); + pass = 1\'b0; + end + part = rvar[1:1\'bz]; // High-Z 2nd + if (part !== 2\'bxx) begin + $display(""Failed high-Z 2nd part select of a register, got %b"", part); + pass = 1\'b0; + end +`endif + + // Check a register with range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = rvar2[-1:0]; // After all + if (part !== 2\'bxx) begin + $display(""Failed after part select of a register (2), got %b"", part); + pass = 1\'b0; + end + part = rvar2[0:1]; // Partial after + if (part !== 2\'bx1) begin + $display(""Failed partial after part select of a register (2), got %b"", + part); + pass = 1\'b0; + end + part = rvar2[5:6]; // Before all + if (part !== 2\'bxx) begin + $display(""Failed before part select of a register (2), got %b"", part); + pass = 1\'b0; + end + part = rvar2[4:5]; // Partial before + if (part !== 2\'b0x) begin + $display(""Failed partial before part select of a register (2), got %b"", + part); + pass = 1\'b0; + end + part = rvar2[1\'bx:1]; // Undefined 1st + if (part !== 2\'bxx) begin + $display(""Failed undefined 1st part select of a register (2), got %b"", + part); + pass = 1\'b0; + end + part = rvar2[1:1\'bx]; // Undefined 2nd + if (part !== 2\'bxx) begin + $display(""Failed undefined 2nd part select of a register (2), got %b"", + part); + pass = 1\'b0; + end + part = rvar2[1\'bz:1]; // High-Z 1st + if (part !== 2\'bxx) begin + $display(""Failed high-Z 1st part select of a register (2), got %b"", part); + pass = 1\'b0; + end + part = rvar2[1:1\'bz]; // High-Z 2nd + if (part !== 2\'bxx) begin + $display(""Failed high-Z 2nd part select of a register (2), got %b"", part); + pass = 1\'b0; + end +`endif + + + // Check an array word with range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = ravar[1][6:5]; // After all + if (part !== 2\'bxx) begin + $display(""Failed after part select of an array word, got %b"", part); + pass = 1\'b0; + end + part = ravar[1][5:4]; // Partial after + if (part !== 2\'bx0) begin + $display(""Failed partial after part select of an array word, got %b"", + part); + pass = 1\'b0; + end + part = ravar[1][0:-1]; // Before all + if (part !== 2\'bxx) begin + $display(""Failed before part select of an array word, got %b"", part); + pass = 1\'b0; + end + part = ravar[1][1:0]; // Partial before + if (part !== 2\'b1x) begin + $display(""Failed partial before part select of an array word, got %b"", + part); + pass = 1\'b0; + end + part = ravar[1][1\'bx:1]; // Undefined 1st + if (part !== 2\'bxx) begin + $display(""Failed undefined 1st part select of an array word, got %b"", + part); + pass = 1\'b0; + end + part = ravar[1][1:1\'bx]; // Undefined 2nd + if (part !== 2\'bxx) begin + $display(""Failed undefined 2nd part select of an array word, got %b"", + part); + pass = 1\'b0; + end + part = ravar[1][1\'bz:1]; // High-Z 1st + if (part !== 2\'bxx) begin + $display(""Failed high-Z 1st part select of an array word, got %b"", part); + pass = 1\'b0; + end + part = ravar[1][1:1\'bz]; // High-Z 2nd + if (part !== 2\'bxx) begin + $display(""Failed high-Z 2nd part select of an array word, got %b"", part); + pass = 1\'b0; + end +`endif + + // Check an array word with range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = ravar2[1][-1:0]; // After all + if (part !== 2\'bxx) begin + $display(""Failed after part select of an array word (2), got %b"", part); + pass = 1\'b0; + end + part = ravar2[1][0:1]; // Partial after + if (part !== 2\'bx0) begin + $display(""Failed partial after part select of an array word (2), got %b"", + part); + pass = 1\'b0; + end + part = ravar2[1][5:6]; // Before all + if (part !== 2\'bxx) begin + $display(""Failed before part select of an array word (2), got %b"", part); + pass = 1\'b0; + end + part = ravar2[1][4:5]; // Partial before + if (part !== 2\'b1x) begin + $display(""Failed partial before part select of an array word (2), got %b"", + part); + pass = 1\'b0; + end + part = ravar2[1][1\'bx:1]; // Undefined 1st + if (part !== 2\'bxx) begin + $display(""Failed undefined 1st part select of an array word (2), got %b"", + part); + pass = 1\'b0; + end + part = ravar2[1][1:1\'bx]; // Undefined 2nd + if (part !== 2\'bxx) begin + $display(""Failed undefined 2nd part select of an array word (2), got %b"", + part); + pass = 1\'b0; + end + part = ravar2[1][1\'bz:1]; // High-Z 1st + if (part !== 2\'bxx) begin + $display(""Failed high-Z 1st part select of an array word (2), got %b"", + part); + pass = 1\'b0; + end + part = ravar2[1][1:1\'bz]; // High-Z 2nd + if (part !== 2\'bxx) begin + $display(""Failed high-Z 2nd part select of an array word (2), got %b"", + part); + pass = 1\'b0; + end +`endif + + + // Check a wire with range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = wvar[6:5]; // After all + if (part !== 2\'bxx) begin + $display(""Failed after part select of a wire, got %b"", part); + pass = 1\'b0; + end + part = wvar[5:4]; // Partial after + if (part !== 2\'bx1) begin + $display(""Failed partial after part select of a wire, got %b"", part); + pass = 1\'b0; + end + part = wvar[0:-1]; // Before all + if (part !== 2\'bxx) begin + $display(""Failed before part select of a wire, got %b"", part); + pass = 1\'b0; + end + part = wvar[1:0]; // Partial before + if (part !== 2\'b0x) begin + $display(""Failed partial before part select of a wire, got %b"", part); + pass = 1\'b0; + end + part = wvar[1\'bx:1]; // Undefined 1st + if (part !== 2\'bxx) begin + $display(""Failed undefined 1st part select of a wire, got %b"", part); + pass = 1\'b0; + end + part = wvar[1:1\'bx]; // Undefined 2nd + if (part !== 2\'bxx) begin + $display(""Failed undefined 2nd part select of a wire, got %b"", part); + pass = 1\'b0; + end + part = wvar[1\'bz:1]; // High-Z 1st + if (part !== 2\'bxx) begin + $display(""Failed high-Z 1st part select of a wire, got %b"", part); + pass = 1\'b0; + end + part = wvar[1:1\'bz]; // High-Z 2nd + if (part !== 2\'bxx) begin + $display(""Failed high-Z 2nd part select of a wire, got %b"", part); + pass = 1\'b0; + end +`endif + + // Check a wire with range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = wvar2[-1:0]; // After all + if (part !== 2\'bxx) begin + $display(""Failed after part select of a wire (2), got %b"", part); + pass = 1\'b0; + end + part = wvar2[0:1]; // Partial after + if (part !== 2\'bx1) begin + $display(""Failed partial after part select of a wire (2), got %b"", part); + pass = 1\'b0; + end + part = wvar2[5:6]; // Before all + if (part !== 2\'bxx) begin + $display(""Failed before part select of a wire (2), got %b"", part); + pass = 1\'b0; + end + part = wvar2[4:5]; // Partial before + if (part !== 2\'b0x) begin + $display(""Failed partial before part select of a wire (2), got %b"", part); + pass = 1\'b0; + end + part = wvar2[1\'bx:1]; // Undefined 1st + if (part !== 2\'bxx) begin + $display(""Failed undefined 1st part select of a wire (2), got %b"", part); + pass = 1\'b0; + end + part = wvar2[1:1\'bx]; // Undefined 2nd + if (part !== 2\'bxx) begin + $display(""Failed undefined 2nd part select of a wire (2), got %b"", part); + pass = 1\'b0; + end + part = wvar2[1\'bz:1]; // High-Z 1st + if (part !== 2\'bxx) begin + $display(""Failed high-Z 1st part select of a wire (2), got %b"", part); + pass = 1\'b0; + end + part = wvar2[1:1\'bz]; // High-Z 2nd + if (part !== 2\'bxx) begin + $display(""Failed high-Z 2nd part select of a wire (2), got %b"", part); + pass = 1\'b0; + end +`endif + + + // Check a wire array word with range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = wavar[1][6:5]; // After all + if (part !== 2\'bxx) begin + $display(""Failed after part select of a wire array word, got %b"", part); + pass = 1\'b0; + end + part = wavar[1][5:4]; // Partial after + if (part !== 2\'bx0) begin + $display(""Failed partial after part select of a wire array word, got %b"", + part); + pass = 1\'b0; + end + part = wavar[1][0:-1]; // Before all + if (part !== 2\'bxx) begin + $display(""Failed before part select of a wire array word, got %b"", part); + pass = 1\'b0; + end + part = wavar[1][1:0]; // Partial before + if (part !== 2\'b1x) begin + $display(""Failed partial before part select of a wire array word, got %b"", + part); + pass = 1\'b0; + end + part = wavar[1][1\'bx:1]; // Undefined 1st + if (part !== 2\'bxx) begin + $display(""Failed undefined 1st part select of a wire array word, got %b"", + part); + pass = 1\'b0; + end + part = wavar[1][1:1\'bx]; // Undefined 2nd + if (part !== 2\'bxx) begin + $display(""Failed undefined 2nd part select of a wire array word, got %b"", + part); + pass = 1\'b0; + end + part = wavar[1][1\'bz:1]; // High-Z 1st + if (part !== 2\'bxx) begin + $display(""Failed high-Z 1st part select of a wire array word, got %b"", + part); + pass = 1\'b0; + end + part = wavar[1][1:1\'bz]; // High-Z 2nd + if (part !== 2\'bxx) begin + $display(""Failed high-Z 2nd part select of a wire array word, got %b"", + part); + pass = 1\'b0; + end +`endif + + // Check a wire array word with range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = wavar2[1][-1:0]; // After all + if (part !== 2\'bxx) begin + $display(""Failed after part select of a wire array word (2), got %b"", + part); + pass = 1\'b0; + end + part = wavar2[1][0:1]; // Partial after + if (part !== 2\'bx0) begin + $display(""Failed partial after part select of a wire array word (2),"", + "" got %b"", part); + pass = 1\'b0; + end + part = wavar2[1][5:6]; // Before all + if (part !== 2\'bxx) begin + $display(""Failed before part select of a wire array word (2), got %b"", + part); + pass = 1\'b0; + end + part = wavar2[1][4:5]; // Partial before + if (part !== 2\'b1x) begin + $display(""Failed partial before part select of a wire array word (2),"", + "" got %b"", part); + pass = 1\'b0; + end + part = wavar2[1][1\'bx:1]; // Undefined 1st + if (part !== 2\'bxx) begin + $display(""Failed undefined 1st part select of a wire array word (2),"", + "" got %b"", part); + pass = 1\'b0; + end + part = wavar2[1][1:1\'bx]; // Undefined 2nd + if (part !== 2\'bxx) begin + $display(""Failed undefined 2nd part select of a wire array word (2),"", + "" got %b"", part); + pass = 1\'b0; + end + part = wavar2[1][1\'bz:1]; // High-Z 1st + if (part !== 2\'bxx) begin + $display(""Failed high-Z 1st part select of a wire array word (2), got %b"", + part); + pass = 1\'b0; + end + part = wavar2[1][1:1\'bz]; // High-Z 2nd + if (part !== 2\'bxx) begin + $display(""Failed high-Z 2nd part select of a wire array word (2), got %b"", + part); + pass = 1\'b0; + end +`endif + + if (pass) $display(""PASSED""); + end +endmodule +" +"// Regression test for GitHub issue 8 : Signedness handling in binary +// bitwise operations of constants. + +module bug(); + +localparam value1 = 4\'sb1010 | 4\'sb0000; +localparam value2 = 4\'sb1010 + 4\'sb0000; +localparam value3 = ~4\'sb0101; +localparam value4 = -4\'sb0101; + +reg signed [4:0] result; + +reg failed = 0; + +initial begin + result = value1; + $display(""%b"", result); + if (result !== 5\'b11010) failed = 1; + result = value2; + $display(""%b"", result); + if (result !== 5\'b11010) failed = 1; + result = value3; + $display(""%b"", result); + if (result !== 5\'b11010) failed = 1; + result = value4; + $display(""%b"", result); + if (result !== 5\'b11011) failed = 1; + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module test_unknown_in_always_star; +reg [2:0] x; +always @* x = {unknown, 1'b0}; +endmodule +" +"// tests using array elements as indices/selects in an array lval select +`timescale 1ns/100ps +module tb; + +reg [7:0] a[7:0]; +real r[7:0]; +wire [2:0] idx[7:0]; + +genvar g; +for (g = 0; g < 8; g=g+1) + assign idx[g] = g; + +reg pass; +integer i; +initial begin + pass = 1\'b1; + + // zero everything out + for (i = 0; i < 8; i = i + 1) begin + a[i] = 8\'h0; + r[i] = 0.0; + end + + // test using one in a part select + a[1][idx[1]*4 +: 4] = 4\'ha; + if (a[1] != 8\'ha0) begin + $display(""FAILED part select, expected a0, got %x"", a[1]); + pass = 1\'b0; + end + + // test using one in an index + a[idx[2]] = 8\'hbc; + if (a[2] != 8\'hbc) begin + $display(""FAILED word index, expected bc, got %x"", a[2]); + pass = 1\'b0; + end + + // and now both... + a[idx[3]][idx[0]*4 +: 4] = 4\'hd; + if (a[3] != 8\'h0d) begin + $display(""FAILED word index and part select, expected 0d, got %x"", a[3]); + pass = 1\'b0; + end + + // non-blocking, in part select + a[4][idx[1]*4 +: 4] <= 4\'he; + if (a[4] != 8\'h00) begin + $display(""FAILED NB assign with part select 1, expected 00, got %x"", a[4]); + pass = 1\'b0; + end + #0.1; + if (a[4] != 8\'he0) begin + $display(""FAILED NB assign with part select 2, expected e0, got %x"", a[4]); + pass = 1\'b0; + end + + // non-blocking, in index + a[idx[5]] <= 8\'h12; + if (a[5] != 8\'h00) begin + $display(""FAILED NB assign with word index 1, expected 00, got %x"", a[4]); + pass = 1\'b0; + end + #0.1; + if (a[5] != 8\'h12) begin + $display(""FAILED NB assign with word index 2, expected 12, got %x"", a[4]); + pass = 1\'b0; + end + + // non-blocking, index and part select + a[idx[6]][idx[0]*4 +: 4] <= 4\'h3; + if (a[6] != 8\'h00) begin + $display(""FAILED NB assign with both 1, expected 00, got %x"", a[4]); + pass = 1\'b0; + end + #0.1; + if (a[6] != 8\'h03) begin + $display(""FAILED NB assign with both 2, expected 03, got %x"", a[4]); + pass = 1\'b0; + end + + // NB, both, with a delay + a[idx[7]][idx[1]*4 +: 4] <= #(idx[1]) 4\'h4; + #0.1; + if (a[7] != 8\'h00) begin + $display(""FAILED NB assign with both and delay 1, expected 00, got %x"", a[4]); + pass = 1\'b0; + end + #1.1; + if (a[7] != 8\'h40) begin + $display(""FAILED NB assign with both and delay 2, expected 40, got %x"", a[4]); + pass = 1\'b0; + end + + // real array index + r[idx[0]] = 1.1; + if (r[0] != 1.1) begin + $display(""FAILED real word, expected 1.0, got %f"", r[0]); + pass = 1\'b0; + end + + // NB to real array + r[idx[1]] <= 2.2; + if (r[1] != 0.0) begin + $display(""FAILED NB assign real word 1, expected 0.0 got %f"", r[1]); + pass = 1\'b0; + end + #0.1; + if (r[1] != 2.2) begin + $display(""FAILED NB assign real word 2, expected 2.2 got %f"", r[1]); + pass = 1\'b0; + end + + // NB to real array with delay + r[idx[2]] <= #(idx[2]) 3.3; + #1.1; + if (r[2] != 0.0) begin + $display(""FAILED NB assign with delay to real word 1, expected 0.0 got %f"", r[1]); + pass = 1\'b0; + end + #1.0; + if (r[2] != 3.3) begin + $display(""FAILED NB assign with delay to real word 2, expected 3.3 got %f"", r[1]); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); +end +endmodule +" +"/* + * This example is a distillation of the essence of PR#993. + * Or at least the essence that led to a bug report. + */ + +module main; + + integer length; + wire [31:0] length_bits = ((length * 8 )/11)+(((length * 8 )%11) != 0); + + reg [31:0] length_bits2; + + initial begin + for (length = 1 ; length < 56 ; length = length + 1) begin +\t length_bits2 = ((length * 8 )/11)+(((length * 8 )%11) != 0); + +\t #1 $display(""length=%3d, length_bits=%3d (%3d)"", +\t\t length, length_bits, length_bits2); + +\t if (length_bits != length_bits2) begin +\t $display(""FAILED - Expressions have different results.""); +\t $finish; +\t end + end // for (length = 1 ; length < 56 ; length = length + 1) + + $finish(0); + end + +endmodule // main +" +"module example; + + reg [3:0] mem [0:7]; + reg [3:0] addr; + wire [3:0] m0 = mem[0]; + wire [3:0] m1 = mem[1]; + wire [3:0] m2 = mem[2]; + wire [3:0] m3 = mem[3]; + wire [3:0] m4 = mem[4]; + wire [3:0] m5 = mem[5]; + wire [3:0] m6 = mem[6]; + wire [3:0] m7 = mem[7]; + wire [3:0] maddr = mem[addr]; + + initial begin + $write( "" "" ); + $display( +""time addr maddr m0 m1 m2 m3 m4 m5 m6 m7"" ); + $write( "" "" ); + $display( +""---- ---- ----- ---- ---- ---- ---- ---- ---- ---- ----"" ); + $monitor( ""%T %b %b %b %b %b %b %b %b %b %b"", + $time, addr, maddr, + m0, m1, m2, m3, m4, m5, m6, m7 ); + mem[0] = 8; + mem[1] = 1; + mem[2] = 2; + mem[3] = 3; + mem[4] = 4; + mem[5] = 5; + mem[6] = 6; + mem[7] = 7; + addr = 0; // 0 + #100 addr = 1; // 100 + #100 addr = 2; // 200 + #100 addr = 3; // 300 + #100 addr = 4; // 400 + #100 addr = 5; // 500 + #100 addr = 6; // 600 + #100 addr = 7; // 700 + #100 addr = 8; // 800 + #100 addr = 4\'b001x; // 900 + #100 addr = 4\'b01x0; // 1000 + #100 addr = 4\'b0x01; // 1100 + #100 addr = 0; // 1200 + #100 mem[addr] <= 9; // 1300 + #100 addr = 3; // 1400 + #100 mem[addr] <= 10; // 1500 + #100 addr = 6; // 1600 + #100 mem[addr] <= 11; // 1700 + #100 addr = 8; // 1800 + #100 mem[addr] <= 12; // 1900 + #100 addr = 4\'b010x; // 2000 + #100 mem[addr] <= 13; // 2100 + #100 addr = 4\'b00x1; // 2200 + #100 mem[addr] <= 14; // 2300 + #100 addr = 4\'b0x10; // 2400 + #100 mem[addr] <= 15; // 2500 + #100 addr = 4\'bxxxx; // 2600 + #100 mem[addr] <= 0; // 2700 + #100 $display( ""Finish at time %T"", $time ); + end + +endmodule +" +"/* + * Test case showing the failure of the \'less than or equal\' operator (note + * that the \'greather than or equal\' comparison also fails) on two signed + * values. The \'foo\' module defines inputs \'a\' and \'b\' as signed inputs, + * then performs a LTE comparison of those two values in order to select the + * smaller of the two as the result (via a mux). The generated output for + * this test (via the display call) for icarus and a well known commercial + * Verilog simulator are shown here. It is my belief that the commercial + * simulator results reflect the correct behavior for a simulator. + * Specifically, with signed numbers the value 32\'h7fffffff represents the + * maximum positive value while 32\'h80000000 represents the minimum negative + * value. Thus for Less Than or Equal comparison any negative value (ie + * 32\'h80000000) should evaluate to less than any positive value + * (ie 32\'h7fffffff). Note the difference in the last 4 comparisons between + * the icarus results and the commercial results. The commercial results show + * that the 32\'h8000000? values are less than the 32\'h7ffffff? values as is + * expected. + * + * icarus commercial simulator + * 7ffffff5 7ffffffa = 7ffffff5 # 7ffffff5 7ffffffa = 7ffffff5 + * 7ffffff6 7ffffffb = 7ffffff6 # 7ffffff6 7ffffffb = 7ffffff6 + * 7ffffff7 7ffffffc = 7ffffff7 # 7ffffff7 7ffffffc = 7ffffff7 + * 7ffffff8 7ffffffd = 7ffffff8 # 7ffffff8 7ffffffd = 7ffffff8 + * 7ffffff9 7ffffffe = 7ffffff9 # 7ffffff9 7ffffffe = 7ffffff9 + * 7ffffffa 7fffffff = 7ffffffa # 7ffffffa 7fffffff = 7ffffffa + * 7ffffffb 80000000 = 7ffffffb # 7ffffffb 80000000 = 80000000 + * 7ffffffc 80000001 = 7ffffffc # 7ffffffc 80000001 = 80000001 + * 7ffffffd 80000002 = 7ffffffd # 7ffffffd 80000002 = 80000002 + * 7ffffffe 80000003 = 7ffffffe # 7ffffffe 80000003 = 80000003 + * + * iverilog -version: + * Icarus Verilog version 0.7 ($Name: $) + * + * Compilation + * iverilog -o iverilog.out + * vvp iverilog.out + */ +module test (); + reg clk; + reg [31:0] a_dat; + reg [31:0] b_dat; + wire [31:0] result; + + initial begin +\t clk <= 0; +\t a_dat <= 32\'h7fffFFF5; +\t b_dat <= 32\'h7fffFFFA; +\t #500 $finish(0); + end + always #25 clk <= ~clk; + + always @(posedge clk) +\t begin +\t\ta_dat <= a_dat + 1; +\t\tb_dat <= b_dat + 1; +\t\t$display(""%x %x = %x"", a_dat, b_dat, result); +\t end + + foo foo_test(.a(a_dat), .b(b_dat), .RESULT(result)); + +endmodule // test + +module foo(a, b, RESULT); + input\tsigned [31:0]\ta; + input\tsigned [31:0]\tb; + output [31:0] RESULT; + wire\t\t\t lessThanEqualTo; + wire [31:0]\t\t mux; + assign\t\t lessThanEqualTo=a<=b; + assign\t\t mux=(lessThanEqualTo)?a:b; + assign\t\t RESULT=mux; +endmodule // foo +" +"`celldefine +//`timescale 1ns / 1ps + +// Description : 2 input XOR + +module XOR20 (input A, input B, output Q); + + xor (Q,B,A); + + initial $sdf_annotate(""ivltests/sdf3.sdf""); + + specify + (A => Q) = (1,1); + (B => Q) = (1,1); + endspecify + +endmodule + +`endcelldefine + +module tb; + + reg a, b; + wire q; + XOR20 dut(.A(a), .B(b), .Q(q)); + + initial begin + $monitor($time,, ""A=%b, B=%b, Q=%b"", a, b, q); + + #10 ; + a = 1; + b = 1; + #10 ; + b = 0; + #10 $finish(0); + end + +endmodule // tb +" +"/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +module main; + test tt(); + defparam foo = 3; /* This should generate a warning. */ + defparam tt.foo = 4; +endmodule // main + +module test; + parameter foo = 10; + reg [foo-1:0] bar; + + initial begin + if ($bits(bar) != 4) begin +\t $display(""FAILED -- $bits(bar) = %d"", $bits(bar)); +\t $finish; + end + $display(""PASSED""); + end + +endmodule // test +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate continuous << in assignment..dependent on always << working +// + + +module main; + +reg globvar; + +reg [3:0] var1,var2,var3; +wire [3:0] var3a; +reg error; + +assign var3a = var1 << var2; + +always @( var1 or var2) + var3 = var1 << var2 ; + +initial +begin +error = 0; +for ( var1 = 4\'b0; var1 != 4\'hf; var1 = var1 + 1) + for ( var2 = 4\'b0; var2 != 4\'hf; var2 = var2 + 1) + begin + #1 ; + if(var3 != var3a) + begin + $display(""FAILED continous << 1=%h,2=%h,3=%h,3a=%h"", + var1,var2,var3,var3a); + error = 1; + end + #1; + end +if(error == 0) + $display(""PASSED""); +end + +endmodule // main +" +"/* + * Copyright (c) 2001 Juergen Urban + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module sensitivity_list (); +parameter ii = 4; +reg CLK; +reg A; +reg [ii-1:0] B,C; +initial +begin + #30; + C <= {ii{1\'b0}}; + #60; + $finish(0); +end + +always +begin + CLK = 1\'b0; + #10; + CLK = 1\'b1; + #10; + $display ($time); +end + +always @(A or C) begin + A = 1\'b0; + $display (""combinatorial process "", A, "" time:"",$time); + A = 1\'b1; + $display (""combinatorial process "", A, "" time:"",$time); + B = A+C; + end +endmodule +" +"`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + wire [2:0] arr [0:7]; + reg rarr [0:7]; + integer i; + + initial begin + pass = 1\'b1; + #1; + for (i = 0; i <=7 ; i = i + 1) begin + if (arr[i] !== i) begin + $display(""FAILED: index %1d, expected %1d, got %1d"", i, i, arr[i]); + pass = 1\'b0; + end + end + + if (pass) $display(""PASSED""); + end + + // This should display a warning and just ignore the whole statement. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign arr[20] = \'b0; + assign arr[-1] = \'b0; +`endif + + + genvar m; + generate + // This like above should warn when 8 <= m <= 15. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + for (m=0; m<=15; m=m+1) begin: arr_loop +`else + for (m=0; m<=7; m=m+1) begin: arr_loop +`endif + assign arr[m] = m; + end + endgenerate +endmodule +" +"module main; + + reg signed [5:0] GAIN = 2; + reg signed [23:0] iir = -8; + + wire signed [23:0] iir_s1 = iir >>> 2; + wire signed [23:0] iir_s2 = iir >>> GAIN; + + initial begin + #1 /* Wait for inputs values to settle. */ ; + + if (iir_s1 !== -24\'sd2) begin +\t $display(""FAILED -- s1 = %d (%h)"", iir_s1, iir_s1); +\t $finish; + end + + if (iir_s2 !== -24\'sd2) begin +\t $display(""FAILED -- s2 = %d (%h)"", iir_s2, iir_s2); +\t $finish; + end + + $display(""PASSED""); + end +endmodule // main +" +"/* + * This test runs the random number generator to make sure + * it follows the standard algorithm. It is based on the bug + * report from PR#995. + */ + +module pr995 (); + integer seed; + integer i; + integer result; + + initial begin + seed = 1; + $display (""Start sequence: seed=%h"", seed); + + result=$random(seed); + $display (""seed=%h result=%h"", seed, result); + + for (i=0; i<30; i=i+1) begin +\t result=$random(seed); +\t $display (""seed=%h result=%h"", seed, result); + end + + seed = 2; + $display (""Start sequence: seed=%h"", seed); + + result=$random(seed); + $display (""seed=%h result=%h"", seed, result); + + for (i=0; i<30; i=i+1) begin +\t result=$random(seed); +\t $display (""seed=%h result=%h"", seed, result); + end + + seed = 1; + $display (""Start sequence: seed=%h"", seed); + + result=$random(seed); + $display (""seed=%h result=%h"", seed, result); + + for (i=0; i<30; i=i+1) begin +\t result=$random(seed); +\t $display (""seed=%h result=%h"", seed, result); + end + end +endmodule // rand +" +"/*************************************************************** +** Author: Oswaldo Cadenas (oswaldo.cadenas@gmail.com) +** Date: September 27 2011 +** +** Test: Intended to test the vhd code in enumsystem.vhd +** +** A stimulus modules generates a count 0,1,.., 7, 1 and an enable signal +** A scoreboard forces a check according to the operation found in enumsystem.vhd +** +** The test runs for sometime making sure relevant input conditions are met throughout +**************************************************************************************/ + +module stim (input clk, reset, output reg [2:0] count, output reg en); + + always @(posedge clk) begin + if (reset) count <= 3\'b0; + else count <= count + 1; +end + + +initial begin + en = 1; + repeat (100) @(posedge clk); + en = 0; +end + +endmodule + +module scoreboard (input [2:0] count, input reset, en, input [0:3] y); + +initial begin + @(posedge reset); + @(negedge reset); // waiting for reset to become inactive + mycheck(); +end + +task mycheck; + forever begin + #1; + if (en == 0) begin + if (y !== 4\'b0000) begin + $display (""ERROR""); + $finish; + end + end + else begin + #2; + case (count) + 0: if (y !== 4\'b1000) begin + $display(""ERROR""); + $finish; + end + 1: if (y !== 4\'b0100) begin + $display(""ERROR""); + $finish; + end + 2: if (y !== 4\'b0010) begin + $display(""ERROR""); + $finish; + end + 3: if (y !== 4\'b0001) begin + $display(""ERROR""); + $finish; + end + default: if (y !== 4\'b1111 && en == 1) begin + $display(""ERROR here, en = %d"", en); + $finish; + end + endcase + end // else +end // always +endtask + +endmodule + + +module test; +parameter T = 10; +parameter S = 2*10*150; + +bit clk = 0, reset = 0; +wire en; +wire [2:0] count; +wire [0:3] y; + + +initial forever #(T) clk = !clk; + + initial begin + @(negedge clk); + reset = 1\'b1; + repeat(6) @(negedge clk); + reset = 1\'b0; + end + +stim stim (.clk(clk), .reset(reset), .en(en), .count(count) ); +enumsystem duv (.clk(clk), .reset(reset), .en(en), .y(y) ); +scoreboard check (.en(en), .reset(reset), .count(count), .y(y) ); + +initial begin + #S; + $display(""PASSED""); + $finish; +end + + +endmodule +" +"module main; + + reg [2:0] Q; + reg\t clk, clr, up; + + (*ivl_synthesis_off *) + initial begin + clk = 0; + up = 0; + clr = 1; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin +\t $display(""FAILED""); +\t $finish; + end + + up = 1; + clr = 0; + + #1 clk = 1; + #1 clk = 0; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 3\'b010) begin +\t $display(""FAILED""); +\t $finish; + end + + up = 0; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 3\'b010) begin +\t $display(""FAILED""); +\t $finish; + end + + clr = 1; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin +\t $display(""FAILED""); +\t $finish; + end + + $display(""PASSED""); + $finish; + end + + /* + * This statement models a snythesizable UP counter. The up + * count is enabled by the up signal. The clr is an asynchronous + * clear input. + * + * NOTE: This is bad style. Bad, bad style. It comes from a + * customer\'s customer, so I try to support it, but I\'ll moan + * about it. Much better (and clearer) is: + * + * if (clr) + * Q <= 0; + * else + * Q <= Q+1; + */ + (* ivl_synthesis_on *) + always @(posedge clk, posedge clr) begin + if (up) +\tQ = Q + 1; + if (clr) +\tQ = 0; + end + +endmodule // main +" +"module top; + reg clk = 0; + reg [1:0] in = 2'b00; + wire [1:0] out; + + test t1 (clk, out, in); +endmodule + +module test(clk, a, b); +input clk; +output a; +input [1:0] b; + +reg [1:0] a; + +always @(posedge clk) begin + a <= b; +end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW - Int type declaration/validation +// +// D: Assign a 16 bit vector to an int and observe the 0 extension. +// D: Assign a 32 bit vector to an int and observer same value. +// D: Add -1 + 1. Add 0 and -1...and observer correct values. + +module main(); + +reg [15:0] a; +reg [31:0] b; + +integer result; +integer int_a; +integer int_b; + +initial // Excitation block + begin + a = 0; + b = 0; + result = 0; + # 5;\t\t\t// Assign a shorter value + a = 16\'h1234;\t// should see 0 extension in result + result = a; + + # 5;\t\t\t// Assign a 32 bit vector + b = 32\'h12345678 ; + result = b; + + # 5;\t\t\t// Validate sum basic integer arithmetic + int_a = -1 ;\t\t// pun intended! + int_b = 1; + result = int_a + int_b; + + # 5; + int_a = 0; + int_b = -1; + result = int_a + int_b; + + end + +initial // Validation block + begin + #1 ; + #5 ; + if(result != 32\'h00001234) + begin + $display(""FAILED - Bit extend wrong\ +""); + $finish ; + end + + #5 ; + if(result != 32\'h12345678) + begin + $display(""FAILED - 32 bit assign wrong\ +""); + $finish ; + end + + #5 ; + if(result != 32\'h00000000) + begin + $display(""FAILED - -1 + 1 = %h\ +"",result); + $finish ; + end + + #5 ; + if(result != 32\'hffffffff) + begin + $display(""FAILED - 0 - 1 = %h\ +"",result); + $finish ; + end + $display(""PASSED\ +""); + $finish ; + end + +endmodule +" +"module top(); + reg pass = 1\'b1; + reg [31:0] in = \'bx; + reg signed [31:0] sin = \'bx; + wire [63:0] res; + wire signed [63:0] sres; + + lower lwr(res, in); + slower slwr(sres, sin); + + initial begin + #1; + if (res !== {32\'b0, 32\'bx}) begin + $display(""FAILED: unsigned output (%b)"", res); + pass = 1\'b0; + end + + if (lwr.lout !== {32\'b0, 32\'bx}) begin + $display(""FAILED: unsigned input (%b)"", lwr.lout); + pass = 1\'b0; + end + + if (sres !== 64\'bx) begin + $display(""FAILED: signed output (%b)"", sres); + pass = 1\'b0; + end + + if (slwr.lout !== 64\'bx) begin + $display(""FAILED: signed input (%b)"", slwr.lout); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule + +module lower(lrtn, lin); + output [31:0] lrtn; + input [63:0] lin; + + wire [63:0] lout = lin; + + assign lrtn = lout[31:0]; +endmodule + +module slower(lrtn, lin); + output signed [31:0] lrtn; + input signed[63:0] lin; + + wire signed [63:0] lout = lin; + + assign lrtn = lout[31:0]; +endmodule +" +"module test(); + + string str1 = ""abcd""; + string str2 = ""efgh""; + + typedef bit [31:0] vector; + + vector data[1:0]; + + initial begin + data[0] = vector\'(str1); + data[1] = vector\'(str2); + $display(""%s %s"", data[0], data[1]); + if (data[0] === ""abcd"" && data[1] === ""efgh"") + $display(""PASSED""); + else + $display(""FAILED""); + end + +endmodule +" +"module function_test(); + +function [3:0] Copy; + +input [3:0] Value; + +Copy = Value; + +endfunction + +reg [3:0] Value1; +reg [3:0] Value2; + +event Start; + +always @Start begin + Value1 = Copy(1); +end + +always @Start begin + Value2 = Copy(2); +end + +initial begin + ->Start; + #1 $display(""%d %d"", Value1, Value2); +end + +endmodule +" +"module main; + + parameter COND = 1; + parameter SEL = 0; + parameter VAL0 = 0; + parameter VAL1 = 1; + parameter VAL2 = 2; + + wire [3:0] foo; + if (COND) begin + case (SEL) + 0: assign foo = VAL0; + 1: assign foo = VAL1; + 2: assign foo = VAL2; + endcase // case (SEL) + end else begin + assign foo = \'bx; + end + + initial begin + #1 $display(""foo = %b"", foo); + if (foo !== VAL0) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""PASSED""); + $finish; + end + +endmodule // main +" +"module top; + reg pass; + wire [1:0] out; + reg [1:0] drive_val; + reg [1:0] oe_n; + reg [2:0] pull_vec; + reg [1:0] base; + + bufif0 bufs[1:0] (out, drive_val, oe_n); + assign (pull0, pull1) out = pull_vec[base+:2]; + + initial begin + pass = 1\'b1; + base = 2\'b00; + pull_vec = 3\'b000; + oe_n = 2\'b00; + + // Drive is selected. + drive_val = 2\'b00; + #1; + if (out !== drive_val) begin + $display(""Failed to drive 2\'b00, got %b"", out); + pass = 1\'b0; + end + + drive_val = 1\'b1; + #1; + if (out !== drive_val) begin + $display(""Failed to drive 2\'b11, got %b"", out); + pass = 1\'b0; + end + + // The pull is selected (low). + oe_n = 2\'b11; + drive_val = 2\'b00; + #1; + if (out !== pull_vec[1:0]) begin + $display(""Failed pull #1, expected 2\'b00, got %b"", out); + pass = 1\'b0; + end + + drive_val = 1\'b1; + #1; + if (out !== pull_vec[1:0]) begin + $display(""Failed pull #2, expected 2\'b00, got %b"", out); + pass = 1\'b0; + end + + // The pull is selected (high). + pull_vec = 3\'b111; + drive_val = 2\'b00; + #1; + if (out !== pull_vec[1:0]) begin + $display(""Failed pull #3, expected 2\'b11, got %b"", out); + pass = 1\'b0; + end + + drive_val = 2\'b11; + if (out !== pull_vec[1:0]) begin + $display(""Failed pull #4, expected 2\'b11, got %b"", out); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"`begin_keywords ""1364-2005"" +module test(); + +reg signed [15:0] a; +reg signed [7:0] b; +reg signed [31:0] expect; +reg signed [31:0] actual; + +reg signed [127:0] long_x; +real real_x; + +initial begin + for (a = -32768; a < 32767; a = a + 1) begin:outer_loop + long_x = 1; + for (b = 0; b < 127; b = b + 1) begin:inner_loop + real_x = $itor(a) ** $itor(b); + if (real_x < 0.0) real_x = -real_x; + if (real_x >= 2.0**128.0) disable outer_loop; + expect = long_x; + actual = a ** b; + if (actual !== expect) begin + $display(""FAILED : %0d ** %0d = %0d not %0d"", a, b, expect, actual); + $finish; + end + long_x = long_x * a; + end + end + $display(""PASSED""); +end + +endmodule +`end_keywords +" +"/* + * Verification test for increment/decrement operators + * + * Author: Prasad Joshi + */ + +module main; +logic la; +logic lb; + +int ia; +int ib; + +bit ba; +bit bb; + +real ra; +real rb; +real rc; + +\tinitial begin + +\t\t/* logic tests */ +\t\tla = 0; +\t\t#1 + +\t\tlb = ++la; +\t\t#1 +\t\tif (la != lb) begin +\t\t\t$display(""FAILED""); +\t\t\t$finish; +\t\tend + +\t\tib = 15; +\t\t#1 +\t\tia = ++ib; +\t\t#1 +\t\tif (ia != ib) begin +\t\t\t$display(""FAILED""); +\t\t\t$finish; +\t\tend + +\t\tia = 15; +\t\t#1 +\t\tib = ia++; +\t\t#1 +\t\tif (ia != 16 || ib != 15) begin +\t\t\t$display(""FAILED""); +\t\t\t$finish; +\t\tend + +\t\tib = --ia; +\t\tif (ib != ia) begin +\t\t\t$display(""FAILED""); +\t\t\t$finish; +\t\tend + +\t\t/* bit test */ +\t\tba = 0; +\t\t#1 +\t\tfor (ia = 0; ia < 10; ia = ia + 1) begin +\t\t\tbb = --ba; +\t\t\t#1 +\t\t\tif (bb != ba && !(bb == 1 || bb == 0)) begin +\t\t\t\t$display(""FAILED""); +\t\t\t\t$finish; +\t\t\tend +\t\tend + +\t\t/* real decrement test */ +\t\tia = 15; +\t\tra = --ia; +\t\tif (ra != ia) begin +\t\t\t$display(""FAILED""); +\t\t\t$finish; +\t\tend + +\t\trb = 19.99; +\t\trc = rb - 2; +\t\tra = --rb; +\t\tif (ra != rb) begin +\t\t\t$display(""FAILED""); +\t\t\t$finish; +\t\tend + +\t\tra = rb--; +\t\tif (ra == rb || rc != rb) begin +\t\t\t$display(""FAILED""); +\t\t\t$finish; +\t\tend + +\t\t/* real increment test */ +\t\tia = 15; +\t\tra = ++ia; +\t\tif (ra != ia) begin +\t\t\t$display(""FAILED""); +\t\t\t$finish; +\t\tend + +\t\trb = 19.99; +\t\trc = rb + 2; +\t\tra = ++rb; +\t\tif (ra != rb) begin +\t\t\t$display(""FAILED""); +\t\t\t$finish; +\t\tend + +\t\tra = rb++; +\t\tif (ra == rb || rc != rb) begin +\t\t\t$display(""FAILED""); +\t\t\t$finish; +\t\tend + +\t\t$display(""PASSED""); +\tend +endmodule +" +"module top; + real zero, mzero, inf, minf; + + initial begin + zero = 0.0; + mzero = -1.0 * zero; + inf = 1/0.0; + minf = -1 * inf; + + $display(""+0=%f, -0=%f, inf=%f and minf=%f."", zero, mzero, inf, minf); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW - Verify task basic function with no values passed. +// +// D: Task validation. Notice that there are no values passed to this task. +// +// + +module main(); + +reg [3:0] global_reg; + +task dec_glob; +begin + global_reg = global_reg -1; +end +endtask + +initial +begin + global_reg = 2; + dec_glob; + + if(global_reg != 1) + begin + $display(""FAILED - task didn\'t modify global_reg\ +""); + $finish ; + end + $display(""PASSED\ +""); + $finish ; +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate variable right shift in always + + +module main; + +reg globvar; + +reg [7:0] var1,var2,var3; +reg error; +reg [7:0] value; + +always @(var1 or var2) + value = var1 >> var2; + +initial + begin + error = 0; + #1 ; + var1 = 8\'h80; + var2 = 8\'h7; + #1; + if(value !== 8\'h1) + begin + error = 1; +\t$display (""FAILED - 80 >> 7 is %h"",value); + end + #1 ; + var1 = 8\'h80; + var2 = 8\'h6; + #1; + if(value !== 8\'h2) + begin + error = 1; +\t$display (""FAILED - 80 >> 6 is %h"",value); + end + #1 ; + var1 = 8\'h80; + var2 = 8\'h5; + #1; + if(value !== 8\'h4) + begin + error = 1; +\t$display (""FAILED - 80 >> 5 is %h"",value); + end + #1 ; + var1 = 8\'h80; + var2 = 8\'h4; + #1; + if(value !== 8\'h8) + begin + error = 1; +\t$display (""FAILED - 80 >> 4 is %h"",value); + end + #1 ; + var1 = 8\'h80; + var2 = 8\'h3; + #1; + if(value !== 8\'h10) + begin + error = 1; +\t$display (""FAILED - 80 >> 3 is %h"",value); + end + #1 ; + var1 = 8\'h80; + var2 = 8\'h2; + #1; + if(value !== 8\'h20) + begin + error = 1; +\t$display (""FAILED - 80 >> 2 is %h"",value); + end + #1 ; + var1 = 8\'h80; + var2 = 8\'h1; + #1; + if(value !== 8\'h40) + begin + error = 1; +\t$display (""FAILED - 80 >> 1 is %h"",value); + end + #1 ; + var1 = 8\'h80; + var2 = 8\'h0; + #1; + if(value !== 8\'h80) + begin + error = 1; +\t$display (""FAILED - 80 >> 0 is %h"",value); + end + #1 ; + var1 = 8\'ha5; + var2 = 8\'h7; + #1; + if(value !== 8\'h01) + begin + error = 1; +\t$display (""FAILED - a5 >> 7 is %h"",value); + end + #1 ; + var1 = 8\'ha5; + var2 = 8\'h1; + #1; + if(value !== 8\'h52) + begin + error = 1; +\t$display (""FAILED - aa >> 1 is %h"",value); + end + if(error === 0) + $display(""PASSED""); + end + +endmodule // main +" +"// +// Copyright (c) 2002 Steven Wilson (steve@ka6s.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Synth of basic expression assign with add +// +// +module adder (q,a,b ); +input a,b; +output [1:0] q; + +assign q = {1\'b0,a} +{1\'b0,b}; + +endmodule + +module test ; + +reg d; + +wire [1:0] q; + +adder u_add (.q(q),.a(d),.b(d)); + +(* ivl_synthesis_off *) +initial + begin +// $dumpfile(""test.vcd""); +// $dumpvars(0,test); + d = 0; + # 1; + if (q !== 2\'b0) + begin + $display(""FAILED - Q isn\'t 0 ""); +\t $finish; + end + #1 ; + d = 1; + # 1; + if (q !== 2\'b10) + begin + $display(""FAILED - Q isn\'t 2 ""); +\t $finish; + end + $display(""PASSED""); + + end +endmodule +" +"module top; + wire real vo; + + rcvr U1(vo); + drvr U2(vo); +endmodule + +module rcvr(vo); + input vo; + wire real vo; + + always @(vo) + $display(""Real value is %f at %g"", vo, $time); +endmodule + +module drvr(vo); + output vo; + reg real vo; + + initial begin + vo = 3.3; + #1000 vo = 4.5776; + #1000 vo = -4; + end +endmodule +" +"module tb; + + reg [1:0] i; + reg [3:0] x[0:2]; + + initial begin + x[1] = 1; + i = 1; + x[i++] += 2; + if (x[1] != 3) $display(""FAILED: got %b"", x[1]); + else $display(""PASSED""); + end +endmodule // tb +" +"module top; + // Does this have to be signed? + wire signed [7:0] out; + + // Either of these will not expand correctly. +// assign out = 'sh1f; + assign out = 5'sh1f; + + initial #1 $displayb(out); +endmodule +" +"/* + * part select in continuous assignment. + */ + +`timescale 1ns/1ns + +module main; + reg [3:0] src; + wire foo = src[3:1] == 3\'b101; + + integer idx; + initial + begin +\tfor (idx = 0 ; idx < 16 ; idx = idx+1) begin +\t src = idx; +\t #1 if (foo !== (src[3:1] == 3\'b101)) begin +\t $display(""FAILED -- src=%b, foo=%b"", src, foo); +\t $finish; +\t end +\tend +\t$display(""PASSED""); + end // initial begin +endmodule +" +"// Three basic tests in here: +// 1. bit must be initialised before any initial or always block +// 2. assignments to (unsigned) bits with random numbers +// 3. assignments to (unsigned) bits with random values including X and Z + + +module ibit_test; + parameter TRIALS = 100; + parameter MAX = 32768; + + reg unsigned [14:0] ar; // should it be ""reg unsigned [7:0] aw""? + reg unsigned [14:0] ar_xz; // same as above here? + reg unsigned [14:0] ar_expected; // and here + bit unsigned [14:0] bu; + bit unsigned [14:0] bu_xz; + + integer i; + + assign bu = ar; + assign bu_xz = ar_xz; + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if (bu !== 15\'b0 | bu_xz != 15\'b0) + begin + $display (""FAILED - time zero initialisation incorrect: %b %b"", bu, bu_xz); + $finish; + end + // random numbers + for (i = 0; i< TRIALS; i = i+1) + begin + #1; + ar = {$random} % MAX; + #1; + if (bu !== ar) + begin + $display (""FAILED - incorrect assigment to bits: %b"", bu); + $finish; + end + end + # 1; + // with \'x injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< TRIALS; i = i+1) + begin + #1; + ar = {$random} % MAX; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0 + begin + $display (""FAILED - incorrect assigment to bits (when \'x): %b"", bu); + $finish; + end + end + # 1; + $display(""PASSED""); + end + + // this returns X and Z states into bit random positions for a value + function [15:0] xz_inject (input reg unsigned [15:0] value); // should it be ""input unsigned [15:0]"" instead? + integer i, temp; + begin + temp = {$random} % MAX; + for (i=0; i<15; i=i+1) + begin + if (temp[i] == 1\'b1) + begin + temp = $random % MAX; + if (temp <= 0) + value[i] = 1\'bx; // \'x noise + else + value[i] = 1\'bz; // \'z noise + end + end + xz_inject = value; + end + endfunction + + // this function returns bit positions with either X or Z to 0 for an input value + function [15:0] xz_expected (input reg unsigned [15:0] value_xz); // should it be ""input unsigned [15:0] instead? + integer i; + begin + for (i=0; i<15; i=i+1) + begin + if (value_xz[i] === 1\'bx || value_xz[i] === 1\'bz ) + value_xz[i] = 1\'b0; // forced to zero + end + xz_expected = value_xz; + end + endfunction + + +endmodule +" +"// Incomplete case statements in asynchronous logic are dangerous in +// synthesisable code, as in real hardware the inferred latch will be +// sensitive to glitches as the case select value changes. Check that +// the compiler outputs a warning for this. +module mux( + +input wire [2:0] sel, +input wire [2:0] i1, +input wire [2:0] i2, +input wire [2:0] i3, +input wire [2:0] i4, +output reg [2:0] o + +); + +(* ivl_synthesis_on *) +always @* begin + case (sel) + 0 : o = 0; + 1 : o = i1; + 2 : o = i2; + 3 : o = i3; + 4 : o = i4; + endcase +end +(* ivl_synthesis_off *) + +initial $display(""PASSED""); + +endmodule +" +"// pr1662508.v + +`timescale 1ns / 1ns + +module ram( +\tinput clk, +\tinput we, +\tinput [9:0] addr, +\tinput [15:0] data, +\toutput [15:0] read_bus +); + +reg [15:0] ram[31:0]; +assign read_bus = ram[addr[3:0]]; +always @(posedge clk) if (we) +\tram[addr[3:0]] <= data; +endmodule + + +module ram_test; + +reg clk; +reg fail=0; +integer cc; +initial begin +\tfor (cc = 0; cc < 33; cc=cc+1) begin +\t\tclk = 0; #5; +\t\tclk = 1; #5; +\tend +\tif (fail) $display(""FAIL""); +\telse $display(""PASSED""); +end + +reg we=0; +reg [9:0] addr=0; +reg [15:0] data=0; + +always @(posedge clk) begin +\taddr <= cc; +\tdata <= cc*cc; +\twe <= cc<16; +end + +wire [15:0] read_bus; +ram ram(clk, we, addr, data, read_bus); + +always @(negedge clk) if (~we) begin +\t$display(""%d %d"", addr, read_bus); +\tif (read_bus !== addr[3:0]*addr[3:0]) fail=1; +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always @ (event_expression) ; +// D: + +module main ; + +reg [3:0] value1 ; + +initial +\tbegin + # 10 ; + value1 = 4\'h5; + # 10 ; + $display(""PASSED\ +""); +\t $finish; + end + +always @ (value1) ; + +endmodule +" +"module test(); + +localparam [7:0] dly1 = 4; +wire [7:0] dly2 = 3; +reg [7:0] dly3 = 2; + +reg i; +wire [6:1] o; + +assign #(dly1, dly2, dly3) o[1] = i; +assign #(dly2, dly3, dly1) o[2] = i; +assign #(dly3, dly1, dly2) o[3] = i; +assign #(dly2-1, dly2-2, dly2-3) o[4] = i; +assign #(dly3+1, dly3+2, dly3+3) o[5] = i; +assign #(4, 3, 2) o[6] = i; + +function check(input o1, input o2, input o3, input o4, input o5, input o6); + +begin + check = (o[1] == o1) && (o[2] == o2) && (o[3] == o3) + && (o[4] == o4) && (o[5] == o5) && (o[6] == o6); +end + +endfunction + +reg failed = 0; + +initial begin + #1 $monitor($time,,i,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]); + + i = 1\'b1; + #0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx)) failed = 1; + #1; #0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx)) failed = 1; + #1; #0 if (!check(1\'bx, 1\'bx, 1\'b1, 1\'b1, 1\'bx, 1\'bx)) failed = 1; + #1; #0 if (!check(1\'bx, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'bx)) failed = 1; + #1; #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1)) failed = 1; + + i = 1\'b0; + #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1)) failed = 1; + #1; #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b0, 1\'b1, 1\'b1)) failed = 1; + #1; #0 if (!check(1\'b1, 1\'b0, 1\'b1, 1\'b0, 1\'b1, 1\'b1)) failed = 1; + #1; #0 if (!check(1\'b0, 1\'b0, 1\'b1, 1\'b0, 1\'b1, 1\'b0)) failed = 1; + #1; #0 if (!check(1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0)) failed = 1; + + i = 1\'bx; + #0 if (!check(1\'b0, 1\'b0, 1\'b0, 1\'bx, 1\'b0, 1\'b0)) failed = 1; + #1; #0 if (!check(1\'b0, 1\'b0, 1\'b0, 1\'bx, 1\'b0, 1\'b0)) failed = 1; + #1; #0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'b0, 1\'bx)) failed = 1; + #1; #0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx)) failed = 1; + + i = 1\'bz; + #0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bz, 1\'bx, 1\'bx)) failed = 1; + #1; #0 if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bz, 1\'bx, 1\'bx)) failed = 1; + #1; #0 if (!check(1\'bz, 1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx)) failed = 1; + #1; #0 if (!check(1\'bz, 1\'bx, 1\'bx, 1\'bz, 1\'bx, 1\'bz)) failed = 1; + #1; #0 if (!check(1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bx, 1\'bz)) failed = 1; + #1; #0 if (!check(1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bz)) failed = 1; + + #1; + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"/* + * This program tests the synthesis of small memories, including + * aysnchronous read w/ synchronous write. + */ +module main; + + reg [3:0] mem [1:0], D; + reg\t rst, clk, wr, wadr, radr; + + /* + * This implements the synchronous write port to the memory. + */ + (* ivl_synthesis_on *) + always @(posedge clk) + if (rst) begin +\tmem[0] <= 0; +\tmem[1] <= 0; + end else if (wr) begin +\tmem[wadr] <= D; + end + + /* This is the asynchronous read port from the memory. */ + wire [3:0] Q = mem[radr]; + + (* ivl_synthesis_off *) + initial begin + rst = 0; + clk = 0; + wadr = 0; + radr = 0; + wr = 0; + + #1 clk = 1; + #1 clk = 0; + + // Make sure reset works. + rst = 1; + + #1 clk = 1; + #1 clk = 0; + + #1 if (mem[0] !== 0 || mem[1] !== 0) begin +\t $display(""FAILED -- Reset 1: mem[0]=%b, mem[1]=%b"", mem[0], mem[1]); +\t $finish; + end + + radr = 0; + #1 if (Q !== mem[radr]) begin +\t $display(""FAILED -- mem[%b] = %b, Q=%b"", radr, mem[radr], Q); +\t $finish; + end + + radr = 1; + #1 if (Q !== mem[radr]) begin +\t $display(""FAILED -- mem[%b] = %b, Q=%b"", radr, mem[radr], Q); +\t $finish; + end + + rst = 0; + #1 clk = 1; + #1 clk = 0; + + // Make sure memory remembers value. + if (mem[0] !== 0 || mem[1] !== 0) begin +\t $display(""FAILED -- Reset 2: mem[0]=%b, mem[1]=%b"", mem[0], mem[1]); +\t $finish; + end + + D = 7; + wr = 1; + #1 clk = 1; + #1 clk = 0; + + // Make sure write works. + if (mem[0] !== 7 || mem[1] !== 0) begin +\t $display(""FAILED -- write D=%b: mem[0]=%b, mem[1]=%b"", +\t\t D, mem[0], mem[1]); +\t $finish; + end + + D = 2; + wadr = 1; + #1 clk = 1; + #1 clk = 0; + + // Make sure write works. + if (mem[0] !== 7 || mem[1] !== 2) begin +\t $display(""FAILED -- write D=%b: mem[0]=%b, mem[1]=%b"", +\t\t D, mem[0], mem[1]); +\t $finish; + end + + radr = 0; + #1 if (Q !== mem[radr]) begin +\t $display(""FAILED -- mem[%b] = %b, Q=%b"", radr, mem[radr], Q); +\t $finish; + end + + wr = 0; + D = 5; + + // Make sure memory remembers written values. + if (mem[0] !== 7 || mem[1] !== 2) begin +\t $display(""FAILED -- write D=%b: mem[0]=%b, mem[1]=%b"", +\t\t D, mem[0], mem[1]); +\t $finish; + end + + $display(""PASSED""); + $finish; + end + +endmodule // main +" +"module top; + reg [15:0] out_16; + reg [31:0] in_32, in_32x, ck_32, ck_32x, out_32, out_32x; + reg [63:0] out_64; + integer res, fd; + reg passed; + + initial begin + passed = 1\'b1; + + // Check that a normal 32 bit %u works as expected. + fd = $fopen(""work/test_fscanf.bin"", ""wb""); + in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32\'b00001000_00100000_10100000_10001110; + $fwrite(fd, ""%u"", in_32); + $fclose(fd); + fd = $fopen(""work/test_fscanf.bin"", ""rb""); + res = $fscanf(fd, ""%u"", out_32); + if (res !== 1) begin + $display(""FAILED: $fscanf() #1 returned %d"", res); + passed = 1\'b0; + end else if (ck_32 !== out_32) begin + $display(""FAILED: #1 %b !== %b"", ck_32, out_32); + passed = 1\'b0; + end + res = $fscanf(fd, ""%u"", out_32); + if (res !== -1) begin + $display(""FAILED: $fscanf() #1 EOF returned %d (%b)"", res, out_32); + passed = 1\'b0; + end + $fclose(fd); + + // Check that a normal 32/64 bit %u works as expected. Do the write as + // two 32 bit values to make sure the word order is correct. + fd = $fopen(""work/test_fscanf.bin"", ""wb""); + in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32\'b00001000_00100000_10100000_10001110; + $fwrite(fd, ""%u"", in_32); + in_32x = 32\'b0001000x_0010000x_0011000x_0100000x; + ck_32x = 32\'b00010000_00100000_00110000_01000000; + $fwrite(fd, ""%u"", in_32x); + $fclose(fd); + fd = $fopen(""work/test_fscanf.bin"", ""rb""); + res = $fscanf(fd, ""%u"", out_64); + if (res !== 1) $display(""FAILED: $fscanf() #2a returned %d"", res); + else if ({ck_32x,ck_32} !== out_64) begin + $display(""FAILED: #2a %b !== %b"", {ck_32x,ck_32}, out_64); + passed = 1\'b0; + end + res = $fscanf(fd, ""%u"", out_32); + if (res !== -1) begin + $display(""FAILED: $fscanf() #2a EOF returned %d (%b)"", res, out_32); + passed = 1\'b0; + end + $fclose(fd); + + // Check that a normal 64/64 bit %u works as expected. + fd = $fopen(""work/test_fscanf.bin"", ""wb""); + in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32\'b00001000_00100000_10100000_10001110; + in_32x = 32\'b0001000x_0010000x_0011000x_0100000x; + ck_32x = 32\'b00010000_00100000_00110000_01000000; + $fwrite(fd, ""%u"", {in_32x,in_32}); + $fclose(fd); + fd = $fopen(""work/test_fscanf.bin"", ""rb""); + res = $fscanf(fd, ""%u"", out_64); + if (res !== 1) $display(""FAILED: $fscanf() #2b returned %d"", res); + else if ({ck_32x,ck_32} !== out_64) begin + $display(""FAILED: #2b %b !== %b"", {ck_32x,ck_32}, out_64); + passed = 1\'b0; + end + res = $fscanf(fd, ""%u"", out_32); + if (res !== -1) begin + $display(""FAILED: $fscanf() #2b EOF returned %d (%b)"", res, out_32); + passed = 1\'b0; + end + $fclose(fd); + + // Check that a normal 64/32 bit %u works as expected. + fd = $fopen(""work/test_fscanf.bin"", ""wb""); + in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32\'b00001000_00100000_10100000_10001110; + in_32x = 32\'b0001000x_0010000x_0011000x_0100000x; + ck_32x = 32\'b00010000_00100000_00110000_01000000; + $fwrite(fd, ""%u"", {in_32x,in_32}); + $fclose(fd); + fd = $fopen(""work/test_fscanf.bin"", ""rb""); + res = $fscanf(fd, ""%u%u"", out_32,out_32x); + if (res !== 2) $display(""FAILED: $fscanf() #2c returned %d"", res); + else if ({ck_32x,ck_32} !== {out_32x, out_32}) begin + $display(""FAILED: #2c %b !== %b"", {ck_32x,ck_32}, {out_32x,out_32}); + passed = 1\'b0; + end + res = $fscanf(fd, ""%u"", out_32); + if (res !== -1) begin + $display(""FAILED: $fscanf() #2c EOF returned %d (%b)"", res, out_32); + passed = 1\'b0; + end + $fclose(fd); + + // Check that a 16 bit %u works as expected. + fd = $fopen(""work/test_fscanf.bin"", ""wb""); + in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32\'b00001000_00100000_10100000_10001110; + $fwrite(fd, ""%u"", in_32); + $fclose(fd); + fd = $fopen(""work/test_fscanf.bin"", ""rb""); + res = $fscanf(fd, ""%u"", out_16); + if (res !== 1) begin + $display(""FAILED: $fscanf() #3 returned %d"", res); + passed = 1\'b0; + end else if (ck_32[15:0] !== out_16) begin + $display(""FAILED: #3 %b !== %b"", ck_32[15:0], out_16); + passed = 1\'b0; + end + res = $fscanf(fd, ""%u"", out_32); + if (res !== -1) begin + $display(""FAILED: $fscanf() #3 EOF returned %d (%b)"", res, out_32); + passed = 1\'b0; + end + $fclose(fd); + + // Check that a 16 bit %u works as expected even with a 32 bit variable. + // All 32 bits are read but we truncate and zero fill the result. + fd = $fopen(""work/test_fscanf.bin"", ""wb""); + in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32\'b00001000_00100000_10100000_10001110; + $fwrite(fd, ""%u"", in_32); + $fclose(fd); + fd = $fopen(""work/test_fscanf.bin"", ""rb""); + res = $fscanf(fd, ""%16u"", out_32); + if (res !== 1) begin + $display(""FAILED: $fscanf() #4 returned %d"", res); + passed = 1\'b0; + end else if (ck_32[15:0] !== out_32) begin + $display(""FAILED: #4 %b !== %b"", ck_32[15:0], out_32); + passed = 1\'b0; + end + res = $fscanf(fd, ""%u"", out_32); + if (res !== -1) begin + $display(""FAILED: $fscanf() #4 EOF returned %d (%b)"", res, out_32); + passed = 1\'b0; + end + $fclose(fd); + + // Check that a 32 bit %u works with a 64 bit variable when sized. + fd = $fopen(""work/test_fscanf.bin"", ""wb""); + in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32\'b00001000_00100000_10100000_10001110; + $fwrite(fd, ""%u"", in_32); + $fclose(fd); + fd = $fopen(""work/test_fscanf.bin"", ""rb""); + res = $fscanf(fd, ""%32u"", out_64); + if (res !== 1) begin + $display(""FAILED: $fscanf() #5 returned %d"", res); + passed = 1\'b0; + end else if (ck_32 !== out_64) begin + $display(""FAILED: #5 %b !== %b"", ck_32, out_64); + passed = 1\'b0; + end + res = $fscanf(fd, ""%u"", out_32); + if (res !== -1) begin + $display(""FAILED: $fscanf() #5 EOF returned %d (%b)"", res, out_32); + passed = 1\'b0; + end + $fclose(fd); + + // Check that by default one element is suppressed. + fd = $fopen(""work/test_fscanf.bin"", ""wb""); + in_32x = 32\'b0001000x_0010000x_0011000x_0100000x; + $fwrite(fd, ""%u"", in_32x); + in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32\'b00001000_00100000_10100000_10001110; + $fwrite(fd, ""%u"", in_32); + $fclose(fd); + fd = $fopen(""work/test_fscanf.bin"", ""rb""); + res = $fscanf(fd, ""%*u%u"", out_32); + if (res !== 1) begin + $display(""FAILED: $fscanf() #6 returned %d"", res); + passed = 1\'b0; + end else if (ck_32 !== out_32) begin + $display(""FAILED: #6 %b !== %b"", ck_32, out_32); + passed = 1\'b0; + end + res = $fscanf(fd, ""%u"", out_32); + if (res !== -1) begin + $display(""FAILED: $fscanf() #6 EOF returned %d (%b)"", res, out_32); + passed = 1\'b0; + end + $fclose(fd); + + // Check that multiple elements can be suppressed (exact count). + fd = $fopen(""work/test_fscanf.bin"", ""wb""); + in_32x = 32\'b0001000x_0010000x_0011000x_0100000x; + $fwrite(fd, ""%u%u"", in_32x, in_32x); + in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32\'b00001000_00100000_10100000_10001110; + $fwrite(fd, ""%u"", in_32); + $fclose(fd); + fd = $fopen(""work/test_fscanf.bin"", ""rb""); + res = $fscanf(fd, ""%*64u%u"", out_32); + if (res !== 1) begin + $display(""FAILED: $fscanf() #7 returned %d"", res); + passed = 1\'b0; + end else if (ck_32 !== out_32) begin + $display(""FAILED: #7 %b !== %b"", ck_32, out_32); + passed = 1\'b0; + end + res = $fscanf(fd, ""%u"", out_32); + if (res !== -1) begin + $display(""FAILED: $fscanf() #7 EOF returned %d (%b)"", res, out_32); + passed = 1\'b0; + end + $fclose(fd); + + // Check that multiple elements can be suppressed (minimum count). + fd = $fopen(""work/test_fscanf.bin"", ""wb""); + in_32x = 32\'b0001000x_0010000x_0011000x_0100000x; + $fwrite(fd, ""%u%u"", in_32x, in_32x); + in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32\'b00001000_00100000_10100000_10001110; + $fwrite(fd, ""%u"", in_32); + $fclose(fd); + fd = $fopen(""work/test_fscanf.bin"", ""rb""); + res = $fscanf(fd, ""%*33u%u"", out_32); + if (res !== 1) begin + $display(""FAILED: $fscanf() #8 returned %d"", res); + passed = 1\'b0; + end else if (ck_32 !== out_32) begin + $display(""FAILED: #8 %b !== %b"", ck_32, out_32); + passed = 1\'b0; + end + res = $fscanf(fd, ""%u"", out_32); + if (res !== -1) begin + $display(""FAILED: $fscanf() #8 EOF returned %d (%b)"", res, out_32); + passed = 1\'b0; + end + $fclose(fd); + + if (passed) $display(""PASSED""); + end +endmodule +" +"// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for 'image attribute in VHDL. + +module image_attr_test; +logic start_test; +image_attr_entity dut(start_test); + +initial begin + start_test = 1'b0; + #1 start_test = 1'b1; +end +endmodule +" +"// Invalid packed dimensions +// This should generate a error message and not crash during elaboration + +typedef logic [] T1; +typedef logic [0] T2; +typedef logic [-1] T3; +typedef logic [$] T4; + +module test ( + input [] port_a, + input [0] port_b, + output [-1] port_c, + output [$] port_d +); +\tlogic [$] a; +\tT1 b; +\tT1 [$] c; + +\tlogic [0] d; +\tT2 e; +\tT2 [0] f; + +\tlogic [-1] g; +\tT3 h; +\tT3 [-1] i; + +\tlogic [$] j; +\tT4 k; +\tT4 [$] l; +endmodule +" +"/* + * See PR#810 in the test suite. + */ + +`timescale 1 ns / 1 ps + +module RR64X1_4LA1 (); + +parameter I_AADR_01_DOA_01_T2 = 1.167000; +parameter I_AADR_10_DOA_01_T2 = 1.176000; +parameter taaa_d1 = ( I_AADR_01_DOA_01_T2 > I_AADR_10_DOA_01_T2 ) +? I_AADR_01_DOA_01_T2 : I_AADR_10_DOA_01_T2; +parameter I_AADR_01_DOA_10_T2 = 1.276000; +parameter I_AADR_10_DOA_10_T2 = 1.267000; +parameter taaa_d0 = ( I_AADR_01_DOA_10_T2 > I_AADR_10_DOA_10_T2 ) +? I_AADR_01_DOA_10_T2 : I_AADR_10_DOA_10_T2; +parameter taaa = ( taaa_d1 > taaa_d0 ) ? taaa_d1 : taaa_d0; + + initial begin + if (taaa_d1 != I_AADR_10_DOA_01_T2) begin +\t $display(""FAILED -- taaa_d1=%f"", taaa_d1); +\t $finish; + end + + if (taaa_d0 != I_AADR_01_DOA_10_T2) begin +\t $display(""FAILED -- taaa_d0=%f"", taaa_d0); +\t $finish; + end + + if (taaa != taaa_d0) begin +\t $display(""FAILED -- taaa=%f"", taaa); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule +" +"module top; + reg [80*8:1] simp_str, info_str; + real ver, subver; + initial begin + ver = $simparam(""simulatorVersion""); + subver = $simparam(""simulatorSubversion""); + // For 0.9 only use one digit after the decimal point. + if (ver < 1.0) $swrite(simp_str, ""%0.1f.%0.0f"", ver, subver); + // For the rest, 10 and above, use no digits after the decimal point. + else $swrite(simp_str, ""%0.0f.%0.0f"", ver, subver); + $get_version(info_str); + if (simp_str !== info_str) begin + $display(""FAILED""); + $display(""$simparam version: \'%0s\'"", simp_str); + $display(""vpi_get_vlog_info version: \'%0s\'"", info_str); + end else $display(""The two versions matched!""); + end +endmodule +" +"primitive passthrough (o, i); + input i; + output o; + table + // i : o + 1 : 1; + 0 : 0; + ? : 0; + endtable +endprimitive + +module test; + reg i; + wire o1, o1b, o2, o2b; + + initial begin + i = 1\'b0; + #1; + if ((o1 !== 1\'b0) && (o1b !== 1\'b1) && + (o2 !== 1\'b0) && (o2b !== 1\'b1)) $display(""FAILED""); + else $display(""PASSED""); + end + + passthrough (o1, i); + passthrough (o1b, !i); + passthrough (o2, i); + passthrough (o2b, ~i); +endmodule +" +"module top; + initial begin: b_label + $display(""FAILED""); + end: b_label_f + + initial fork:fj_label + join:fj_label_f + + initial fork:fja_label + join_any:fja_label_f + + initial fork:fjn_label + join_none:fjn_label_f + + task t_label; + endtask: t_label_f + + task twa_label(input arg); + endtask: twa_label_f + + function fn_label; + input arg; + endfunction: fn_label_f + + function fa_label(input in); + endfunction: fa_label_f + +endmodule:top_f + +macromodule extra; + parameter add_inv = 1; + reg a; + wire y, yb; + pbuf dut(y, a); + + if (add_inv) begin: g_label + pinv dut2(yb, y); + end: g_label_f + +endmodule: extra_f + +package pkg; +endpackage: pkg_f + +program pgm; + class foo; + endclass: foo_f +endprogram: pgm_f + +primitive pbuf (out, in); + output out; + input in; + table + 0 : 0; + 1 : 1; + endtable +endprimitive: pbuf + +primitive pinv (output out, input in); + table + 0 : 1; + 1 : 0; + endtable +endprimitive: pinv_f +" +"`define msg(x,y) `""x: `\\`""y`\\`""`"" + +module test(); + +initial begin + $display(`msg(left side,right side)); +end + +endmodule +" +"module RegisterArrayBug01; + + reg [15:0] rf[0:7]; + wire [3:0] rf_0_slice0 = rf[0][3:0]; + + wire [15:0] rf_0 = rf[0]; + + initial begin + $monitor($time,, ""rf and slice: %h %h"", rf_0, rf_0_slice0); + + rf[0] = 16\'hffff; + #10 rf[0] = 16\'h0000; + #10 rf[0] = 16\'hbeef; + #10 $finish(0); + end + +endmodule + +/* Program fails to compile with result: + elab_net.cc:1738: failed assertion `msb_ == 0\' + */ +" +"module top; + reg signed [7:0] neg = -2; + reg signed [7:0] m1 = -1; + reg signed [7:0] zero = 0; + reg signed [7:0] one = 1; + reg signed [7:0] pos = 2; + reg signed [7:0] pose = 2; + reg signed [7:0] poso = 3; + reg signed [7:0] res; + + wire signed [7:0] neg_pose = neg**pose; + wire signed [7:0] neg_poso = neg**poso; + wire signed [7:0] m1_pose = m1**pose; + wire signed [7:0] m1_poso = m1**poso; + wire signed [7:0] zero_pos = zero**pos; + wire signed [7:0] one_pos = one**pos; + wire signed [7:0] pos_pos = pos**pos; + + wire signed [7:0] neg_zero = neg**zero; + wire signed [7:0] m1_zero = m1**zero; + wire signed [7:0] zero_zero = zero**zero; + wire signed [7:0] one_zero = one**zero; + wire signed [7:0] pos_zero = pos**zero; + + wire signed [7:0] neg_neg = neg**m1; + wire signed [7:0] m1_nege = m1**neg; + wire signed [7:0] m1_nego = m1**m1; + wire signed [7:0] zero_neg = zero**m1; + wire signed [7:0] one_neg = one**m1; + wire signed [7:0] pos_neg = pos**m1; + + reg pass; + + initial begin + pass = 1\'b1; + + #1; + + /* Positive exponent. */ + if (neg_pose !== 4) begin + $display(""Failed neg**pos even, got %d"", neg_pose); + pass = 1\'b0; + end + if (neg_poso !== -8) begin + $display(""Failed neg**pos odd, got %d"", neg_poso); + pass = 1\'b0; + end + if (m1_pose !== 1) begin + $display(""Failed -1**pos even, got %d"", m1_pose); + pass = 1\'b0; + end + if (m1_poso !== -1) begin + $display(""Failed -1**pos odd, got %d"", m1_poso); + pass = 1\'b0; + end + if (zero_pos !== 0) begin + $display(""Failed 0**pos, got %d"", zero_pos); + pass = 1\'b0; + end + if (one_pos !== 1) begin + $display(""Failed 1**pos, got %d"", one_pos); + pass = 1\'b0; + end + if (pos_pos !== 4) begin + $display(""Failed 1**pos, got %d"", pos_pos); + pass = 1\'b0; + end + + /* Zero exponent. */ + if (neg_zero !== 1) begin + $display(""Failed neg**0, got %d"", neg_zero); + pass = 1\'b0; + end + if (m1_zero !== 1) begin + $display(""Failed -1**0, got %d"", m1_zero); + pass = 1\'b0; + end + if (zero_zero !== 1) begin + $display(""Failed 0**0, got %d"", zero_zero); + pass = 1\'b0; + end + if (one_zero !== 1) begin + $display(""Failed 1**0, got %d"", one_zero); + pass = 1\'b0; + end + if (pos_zero !== 1) begin + $display(""Failed pos**0, got %d"", pos_zero); + pass = 1\'b0; + end + + /* Negative exponent. */ + if (neg_neg !== 0) begin + $display(""Failed neg**neg got %d"", neg_neg); + pass = 1\'b0; + end + if (m1_nege !== 1) begin + $display(""Failed -1**neg (even) got %d"", m1_nege); + pass = 1\'b0; + end + if (m1_nego !== -1) begin + $display(""Failed -1**neg (odd) got %d"", m1_nego); + pass = 1\'b0; + end + if (zero_neg !== \'sbx) begin + $display(""Failed 0**neg (odd) got %d"", zero_neg); + pass = 1\'b0; + end + if (one_neg !== 1) begin + $display(""Failed 1**neg got %d"", one_neg); + pass = 1\'b0; + end + if (pos_neg !== 0) begin + $display(""Failed pos**neg got %d"", pos_neg); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"localparam num1 = 101, str1 = ""unit1""; +localparam num2 = 102, str2 = ""unit1""; +localparam num3 = 103, str3 = ""unit1""; + +class c1; + + const int num2 = 100; const string str2 = ""c1""; + + task display; + begin + $display(""%d from %s"", num1, str1); + $display(""%d from %s"", num2, str2); + end + endtask + +endclass + + +module m1(); + + localparam num2 = 112, str2 = ""m1""; + + c1 obj; + + initial begin + #1; + obj = new; + obj.display; + $display(""%d from %s"", num1, str1); + $display(""%d from %s"", num2, str2); + $display(""%d from %s"", num3, str3); + $display(""%d from %s"", m2.num4, m2.str4); + end + +/* This should not change the result, but Icarus ignores the order in + which variables are declared and used. + localparam num3 = 113, str3 = ""m1""; +*/ + +endmodule + + +module m2(); + + localparam num1 = 121, str1 = ""m2""; + localparam num2 = 122, str2 = ""m2""; + localparam num3 = 123, str3 = ""m2""; + localparam num4 = 124, str4 = ""m2""; + + m1 m1inst(); + +endmodule +" +"module main; + + time period; + reg\tdrive; + + // This is the main point of the test. Non-constant delay expressions + // should work here. + wire #(period/3) trace = drive; + + initial begin + period = 8*3; + // Initially, set up a period=8 and get the trace to start + // following the drive. + #1 drive <= 1; + #9 if (trace !== drive) begin +\t $display(""FAILED -- time=%0t, drive=%b, trace=%b"", +\t\t $time, drive, trace); +\t $finish; + end + + // The drive should NOT change the trace before the period. + drive <= 0; + + #7 if (trace !== 1\'b1) begin +\t $display(""FAILED -- time=%0t, drive=%b, trace=%b"", +\t\t $time, drive, trace); +\t $finish; + end + #2 if (trace !== drive) begin +\t $display(""FAILED -- time=%0t, drive=%b, trace=%b"", +\t\t $time, drive, trace); +\t $finish; + end + + // Change the period. + period = 6*3; + + // Now check that the new delay is taken. + #1 drive <= 1; + + #5 if (trace !== 1\'b0) begin +\t $display(""FAILED -- time=%0t, drive=%b, trace=%b"", +\t\t $time, drive, trace); +\t $finish; + end + + #2 if (trace !== drive) begin +\t $display(""FAILED -- time=%0t, drive=%b, trace=%b"", +\t\t $time, drive, trace); +\t $finish; + end + + $display(""PASSED""); + $finish; + end + +endmodule // main +" +"module main; + + int unsigned foo, bar = 10; + int signed foos, bars = 10; + + int unsigned wire_sum; + int\t\twire_sums; + + assign wire_sum = foo + bar; + assign wire_sums = foos + bars; + + function int unsigned sum(input int unsigned a, b); + sum = a + b; + endfunction + + function int unsigned sums(input int signed a, b); + sums = a + b; + endfunction + + initial begin + foo = 9; + $display(""%0d * %0d = %0d"", foo, bar, foo * bar); + $display(""sum(%0d,%0d) = %0d"", foo, bar, sum(foo,bar)); + + if (foo !== 9 || bar !== 10) begin +\t $display(""FAILED""); +\t $finish; + end + + if (foo*bar !== 90) begin +\t $display(""FAILED""); +\t $finish; + end + + if (sum(foo,bar) !== 19) begin +\t $display(""FAILED""); +\t $finish; + end + + foos = -7; + $display(""%0d * %0d = %0d"", foos, bars, foos * bars); + $display(""sums(%0d,%0d) = %0d"", foos, bars, sums(foos,bars)); + + if (foos !== -7 || bars !== 10) begin +\t $display(""FAILED""); +\t $finish; + end + + if (foos*bars !== -70) begin +\t $display(""FAILED""); +\t $finish; + end + + if (sums(foos,bars) !== 3) begin +\t $display(""FAILED""); +\t $finish; + end + + #0; // allow CAs to propagate + $display(""wire_sum = %0d"", wire_sum); + $display(""wire_sums = %0d"", wire_sums); + + if (wire_sum !== 19) begin +\t $display(""FAILED""); +\t $finish; + end + + if (wire_sums !== 3) begin +\t $display(""FAILED""); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"module top; + +reg [3:0][3:0] array; + +reg failed = 0; + +initial begin + array = 16\'h4321; + + $display(""%h"", array[ 0+:2]); if (array[ 0+:2] !== 8\'h21) failed = 1; + $display(""%h"", array[ 1+:2]); if (array[ 1+:2] !== 8\'h32) failed = 1; + $display(""%h"", array[ 2+:2]); if (array[ 2+:2] !== 8\'h43) failed = 1; + + $display(""%h"", array[ 1-:2]); if (array[ 1-:2] !== 8\'h21) failed = 1; + $display(""%h"", array[ 2-:2]); if (array[ 2-:2] !== 8\'h32) failed = 1; + $display(""%h"", array[ 3-:2]); if (array[ 3-:2] !== 8\'h43) failed = 1; + + $display(""%h"", array[ 1:0 ]); if (array[ 1:0 ] !== 8\'h21) failed = 1; + $display(""%h"", array[ 2:1 ]); if (array[ 2:1 ] !== 8\'h32) failed = 1; + $display(""%h"", array[ 3:2 ]); if (array[ 3:2 ] !== 8\'h43) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always if ( boolean_expr ) statement ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial +\tbegin + value1 = 0; + # 5 ; + if(value1 != 4\'d4) + $display(""FAILED - always 3.1.5D always if ( bool_expr) statement \ +""); + else + $display(""PASSED""); +\t $finish; + end + +always if( 1\'b1 && 1\'b1 ) begin + # 1; + value1 = value1 + 1; + end + +endmodule +" +"module test(); + +string str; + +always @(str) begin + $display(""str = %s"", str); +end + +task automatic test_task(input integer delay, input string str1, input string str2); + +string str; + +fork + begin + @(str) $display(""str%0d = %s"", delay, str); + @(str) $display(""str%0d = %s"", delay, str); + end + begin + #delay; + #2 str = str1; + #2 str = str1; + #2 str = str2; + end +join + +endtask + +initial begin + #1 str = ""hello""; + #1 str = ""hello""; + #1 str = ""world""; + fork + test_task(1, ""hello1"", ""world1""); + test_task(2, ""hello2"", ""world2""); + join + fork + test_task(1, ""world1"", ""hello1""); + test_task(2, ""world2"", ""hello2""); + join + #1 $finish(0); +end + +endmodule +" +"/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + reg a; + reg b; + wire q = a & b; + + initial begin + a = 1; + b = 0; + #1; + if (q !== 0) begin +\t $display(""FAILED -- q did not start out right: %b"", q); +\t $finish; + end + + b = 1; + if (q !== 0) begin +\t // Since b takes the new value with a blocking assignment, +\t // it is up to the & gate to schedule the q change, and not +\t // actually push the change through. +\t $display(""FAILED -- q changed too soon? %b"", q); +\t $finish; + end + + if (b !== 1) begin +\t $display(""FAILED -- b value did not stick: %b"", b); +\t $finish; + end + + // The #0 delay lets the scheduler execute the change to the + // q value, so that we can read the correct value out. + #0 if (q !== 1) begin +\t $display(""FAILED -- q did not change when it should: %b"", q); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"/* + * From IEEE 1800-2012 + * + * 5.8 Time literals + * + * Time is written in integer or fixed-point format, followed without a space by a + * time unit ( fs ps ns us ms s ). + * For example: + * 2.1ns + * 40ps + * The time literal is interpreted as a realtime value scaled to the current time + * unit and rounded to the current time precision. + */ + +module same; + timeunit 1ps; + timeprecision 1ps; + + function logic check_time; + realtime result; + + check_time = 1\'b1; + + result = 1ns; + if (result != 1000.0) begin + $display(""Failed-same: Expected 1ns to be rounded to 1000.0, got %f"", result); + check_time = 1\'b0; + end + + result = 1ps; + if (result != 1.0) begin + $display(""Failed-same: Expected 1ps to be rounded to 1.0, got %f"", result); + check_time = 1\'b0; + end + + result = 0.5ps; + if (result != 1.0) begin + $display(""Failed-same: Expected 0.5ps to be rounded to 1.0, got %f"", result); + check_time = 1\'b0; + end + + result = 0.499ps; + if (result != 0.0) begin + $display(""Failed-same: Expected 0.49ps to be rounded to 0.0, got %f"", result); + check_time = 1\'b0; + end + endfunction +endmodule + +module max; + timeunit 100s; + timeprecision 1fs; + + function logic check_time; + realtime result; + + check_time = 1\'b1; + + result = 1s; + if (result != 1e-2) begin + $display(""Failed-max: Expected 1s to be rounded to 1.0e-2, got %f"", result); + check_time = 1\'b0; + end + + result = 0.5fs; + if (result != 1e-17) begin + $display(""Failed-max: Expected 0.5fs to be rounded to 1.0e-17, got %f"", result); + check_time = 1\'b0; + end + + result = 0.499fs; + if (result != 0.0) begin + $display(""Failed-max: Expected 0.49fs to be rounded to 0.0, got %f"", result); + check_time = 1\'b0; + end + endfunction +endmodule + +module top; + timeunit 1ns; + timeprecision 1ps; + + realtime result; + logic passed; + + initial begin + passed = 1\'b1; + + result = 1ns; + if (result != 1.0) begin + $display(""Failed: Expected 1ns to be rounded to 1.0, got %f"", result); + passed = 1\'b0; + end + + result = 1ps; + if (result != 0.001) begin + $display(""Failed: Expected 1ps to be rounded to 0.001, got %f"", result); + passed = 1\'b0; + end + + result = 1.23456789ps; + if (result != 0.001) begin + $display(""Failed: Expected 1.23456789ps to be rounded to 0.001, got %f"", result); + passed = 1\'b0; + end + + result = 0.5ps; + if (result != 0.001) begin + $display(""Failed: Expected 0.5ps to be rounded to 0.001, got %f"", result); + passed = 1\'b0; + end + + result = 0.499ps; + if (result != 0.0) begin + $display(""Failed: Expected 0.49ps to be rounded to 0.0, got %f"", result); + passed = 1\'b0; + end + + passed &= same.check_time(); + passed &= max.check_time(); + + if (passed) $display(""PASSED""); + end +endmodule +" +" +/* + * This is a post-wynthesis test for the blif01a.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif01a.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter WID = 4; + reg [WID-1:0] A, B; + wire [WID:0] Q; + + addN usum(.\\A[3] (A[3]), .\\A[2] (A[2]), .\\A[1] (A[1]), .\\A[0] (A[0]), +\t .\\B[3] (B[3]), .\\B[2] (B[2]), .\\B[1] (B[1]), .\\B[0] (B[0]), +\t .\\Q[4] (Q[4]), .\\Q[3] (Q[3]), .\\Q[2] (Q[2]), .\\Q[1] (Q[1]), .\\Q[0] (Q[0])); + + int\t\t adx; + int\t\t bdx; + initial begin + for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin +\t for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin +\t A <= adx[WID-1:0]; +\t B <= bdx[WID-1:0]; +\t #1 if (Q !== (adx+bdx)) begin +\t $display(""FAILED -- A=%b, B=%b, Q=%b"", A, B, Q); +\t $finish; +\t end +\t end + end + $display(""PASSED""); + end + +endmodule // main +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - always force reg_lvalue = constant ; +// D: No dependancy + +module main ; + +reg [3:0] value1 ; + +initial + begin + #15; + if(value1 != 4\'h5) + $display(""FAILED - 3.1.3D always force reg_lvalue = constant;\ +""); + else +\tbegin + $display(""PASSED\ +""); +\t $finish; + end + end + +always force value1 = 4\'h5; + +endmodule +" +"//--------------------------------------------------------------------------- +// +//--------------------------------------------------------------------------- + module xor_try; + + reg [1:0] inp_xor; // The two-bit inputs to the XOR + reg out_xor; // The XOR output + reg clk; + + initial begin clk = 1'b1; #10 $sn; #160 $finish(0); end + always #50 clk = ~clk; + // The clock + + always @(posedge clk) out_xor = #1 (inp_xor[0] ^ inp_xor[1]); + // The actual operation + endmodule + +" +"module dff (q, d, cp, sdn, cdn); + output q; + input cp; + input d; + input sdn; + input cdn; + + reg q; + + always @(posedge cp or negedge sdn or negedge cdn) begin + if (~sdn) q <= 1; + else if (~cdn) q <= 0; + else q <= d; + end + + specify + if (sdn && cdn) (posedge cp => (q +: d)) = (1, 1); + (negedge cdn => (q +: 1\'b0)) = (1, 1); + (negedge sdn => (q -: 1\'b1)) = (1, 1); + endspecify +endmodule + +module test; + reg d, clk, set, clr; + + dff dut(q, d, clk, ~set, ~clr); + + initial begin + d=0; clk=0; set=0; clr=0; + $monitor($time,, ""d=%b, clk=%b, set=%b, clr=%b, q=%b"", + d, clk, set, clr, q); + $sdf_annotate(""ivltests/sdf6.sdf""); + #10 d = 1; + #10 set = 1; + #10 set = 0; + #10 clr = 1; + #10 clr = 0; + #10 clk = 1; + #10 d = 0; + end +endmodule +" +" +/* + * This tests a trivial class. This tests that properties can be + * given types, and that the types behave properly. + */ +program main; + + // Trivial example of a class + class foo_t ; + string a; + string b; + endclass : foo_t // foo_t + + foo_t obj; + + initial begin + obj = new; + + // Absent any other constructor, strings get initialized as nil. + if (obj.a != """" || obj.b != """") begin +\t $display(""FAILED -- String property not initialized.""); +\t $finish; + end + + // This is the most trivial assignment of class properties. + obj.a = ""Hello""; + obj.b = ""World""; + + $display(""obj = {%0s, %0s}"", obj.a, obj.b); + if (obj.a != ""Hello"" || obj.b != ""World"") begin +\t $display(""FAILED -- assign to object: obj.a=%0s, obj.b=%0s"", obj.a, obj.b); +\t $finish; + end + + $display(""PASSED""); + $finish; + end +endprogram // main +" +"module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4\'d2; + +assign value2 = value1 + 0.0; + +initial begin + // value1 gets cast to real, so \'z\' bits are converted to \'0\'. + #2 $display(""%b %b"", value1, value2); + if (value2 === 8\'b00000010) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"/* + * Copyright (c) 2000 Intrinsity, Inc. + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module test_notif1 ( ); + +reg gnd, vdd, x, z; + +wire t0, t1, t2, t3, t4, t5, t6, t7, + t8, t9, ta, tb, tc, td, te, tf; + +reg failed; + +wire StH, StL; + +assign (strong1, highz0) StH = 1\'bx; +assign (highz1, strong0) StL = 1\'bx; + +notif1 b0 ( t0, gnd, gnd); +notif1 b1 ( t1, gnd, vdd); +notif1 b2 ( t2, gnd, x); +notif1 b3 ( t3, gnd, z); + +notif1 b4 ( t4, vdd, gnd); +notif1 b5 ( t5, vdd, vdd); +notif1 b6 ( t6, vdd, x); +notif1 b7 ( t7, vdd, z); + +notif1 b8 ( t8, x, gnd); +notif1 b9 ( t9, x, vdd); +notif1 ba ( ta, x, x); +notif1 bb ( tb, x, z); + +notif1 bc ( tc, z, gnd); +notif1 bd ( td, z, vdd); +notif1 be ( te, z, x); +notif1 bf ( tf, z, z); + +initial begin + + // + // work around initial state assignment bug + failed = 0; + assign gnd = 1\'b1; + assign vdd = 1\'b0; + assign x = 1\'b1; + assign z = 1\'b1; + #10; + + assign gnd = 1\'b0; + assign vdd = 1\'b1; + assign x = 1\'bx; + assign z = 1\'bz; + #10; + + if (t0 !== z) + begin + failed = 1; + $display (""FAILED: notif1 s:%d g:%d d:%d expected:z"", gnd, gnd, t0 ); + end + + if (t1 !== 1) + begin + failed = 1; + $display (""FAILED: notif1 s:%d g:%d d:%d expected:1"", gnd, vdd, t1 ); + end + if (t2 !== StH) + begin + failed = 1; + $display (""FAILED: notif1 s:%d g:%d d:%d expected:StH"", gnd, x, t2 ); + end + if (t3 !== StH) + begin + failed = 1; + $display (""FAILED: notif1 s:%d g:%d d:%d expected:StH"", gnd, z, t3 ); + end + + if (t4 !== 1\'bz) + begin + failed = 1; + $display (""FAILED: notif1 s:%d g:%d d:%d expected:z"", vdd, gnd, t4 ); + end + if (t5 !== 0) + begin + failed = 1; + $display (""FAILED: notif1 s:%d g:%d d:%d expected:0"", vdd, vdd, t5 ); + end + if (t6 !== StL) + begin + failed = 1; + $display (""FAILED: notif1 s:%d g:%d d:%d expected:StL"", vdd, x, t6 ); + end + if (t7 !== StL) + begin + failed = 1; + $display (""FAILED: notif1 s:%d g:%d d:%d expected:StL"", vdd, z, t7 ); + end + + if (t8 !== 1\'bz) + begin + failed = 1; + $display (""FAILED: notif1 s:%d g:%d d:%d expected:z"", x, gnd, t8 ); + end + if (t9 !== 1\'bx) + begin + failed = 1; + $display (""FAILED: notif1 s:%d g:%d d:%d expected:x"", x, vdd, t9 ); + end + if (ta !== 1\'bx) + begin + failed = 1; + $display (""FAILED: notif1 s:%d g:%d d:%d expected:x"", x, x, ta ); + end + if (tb !== 1\'bx) + begin + failed = 1; + $display (""FAILED: notif1 s:%d g:%d d:%d expected:x"", x, z, tb ); + end + + if (tc !== 1\'bz) + begin + failed = 1; + $display (""FAILED: notif1 s:%d g:%d d:%d expected:z"", z, gnd, tc ); + end + if (td !== 1\'bx) + begin + failed = 1; + $display (""FAILED: notif1 s:%d g:%d d:%d expected:x"", z, vdd, td ); + end + if (te !== 1\'bx) + begin + failed = 1; + $display (""FAILED: notif1 s:%d g:%d d:%d expected:x"", z, x, te ); + end + if (tf !== 1\'bx) + begin + failed = 1; + $display (""FAILED: notif1 s:%d g:%d d:%d expected:x"", z, z, tf ); + end + + if (failed == 0) + $display (""PASSED""); +end +endmodule +" +"/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + wire no, po; + reg\td, c; + + nmos n (no, d, c); + pmos p (po, d, c); + + initial begin + c = 0; + d = 0; + + #1 if (no !== 1\'bz) begin +\t $display(""FAILED -- n (%b, %b, %b)"", no, d, c); +\t $finish; + end + + if (po !== 1\'b0) begin +\t $display(""FAILED -- p (%b, %b, %b)"", po, d, c); +\t $finish; + end + + d = 1; + + #1 if (no !== 1\'bz) begin +\t $display(""FAILED -- n (%b, %b, %b)"", no, d, c); +\t $finish; + end + + if (po !== 1\'b1) begin +\t $display(""FAILED -- p (%b, %b, %b)"", po, d, c); +\t $finish; + end + + c = 1; + + #1 if (no !== 1\'b1) begin +\t $display(""FAILED -- n (%b, %b, %b)"", no, d, c); +\t $finish; + end + + if (po !== 1\'bz) begin +\t $display(""FAILED -- p (%b, %b, %b)"", po, d, c); +\t $finish; + end + + d = 0; + + #1 if (no !== 1\'b0) begin +\t $display(""FAILED -- n (%b, %b, %b)"", no, d, c); +\t $finish; + end + + if (po !== 1\'bz) begin +\t $display(""FAILED -- p (%b, %b, %b)"", po, d, c); +\t $finish; + end + + $display(""PASSED""); + + end + +endmodule // main +" +"// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for or_reduce/and_reduce functions. + +module vhdl_reduce_test; +logic [4:0] inp; +logic and_reduced, or_reduced; + +vhdl_reduce test(inp, and_reduced, or_reduced); + +initial begin + inp = 5\'b00000; + #1 if(and_reduced !== 1\'b0 || or_reduced !== 1\'b0) begin + $display(""FAILED 1""); + $finish(); + end + + inp = 5\'b00010; + #1 if(and_reduced !== 1\'b0 || or_reduced !== 1\'b1) begin + $display(""FAILED 2""); + $finish(); + end + + inp = 5\'b11111; + #1 if(and_reduced !== 1\'b1 || or_reduced !== 1\'b1) begin + $display(""FAILED 3""); + $finish(); + end + + inp = 5\'bzz1xx; + #1 if(and_reduced !== 1\'bx || or_reduced !== 1\'b1) begin + $display(and_reduced); + $display(or_reduced); + $display(""FAILED 4""); + $finish(); + end + + inp = 5\'bzz0xx; + #1 if(and_reduced !== 1\'b0 || or_reduced !== 1\'bx) begin + $display(and_reduced); + $display(or_reduced); + $display(""FAILED 5""); + $finish(); + end + + inp = 5\'bzzzxx; + #1 if(and_reduced !== 1\'bx || or_reduced !== 1\'bx) begin + $display(and_reduced); + $display(or_reduced); + $display(""FAILED 6""); + $finish(); + end + + $display(""PASSED""); +end +endmodule +" +"//--------------------------------------------------------------------------- +// +//--------------------------------------------------------------------------- + module xor_try; + + reg [1:0] inp_xor; // The two-bit inputs to the XOR + reg out_xor; // The XOR output + reg clk; + + initial begin clk = 1'b1; #10 $sn; #160 $finish(0); end + always #50 clk = ~clk; + // The clock + + always @(posedge clk) out_xor = #1 (inp_xor[0] ^ inp_xor[1]); + // The actual operation + endmodule + +" +"module main; + + reg foo_reg; + byte foo_byte; + int foo_int; + shortint foo_shortint; + longint foo_longint; + + initial begin + if ($bits(foo_reg) != 1) begin +\t $display(""FAILED""); +\t $finish; + end + if ($bits(foo_byte) != 8) begin +\t $display(""FAILED""); +\t $finish; + end + if ($bits(foo_int) != 32) begin +\t $display(""FAILED""); +\t $finish; + end + if ($bits(foo_shortint) != 16) begin +\t $display(""FAILED""); +\t $finish; + end + if ($bits(foo_longint) != 64) begin +\t $display(""FAILED""); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always # delay_value reg_lvalue = boolean_expr ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; +reg err ; + +initial +\tbegin + err = 0; + # 1; + if(value1 !== 4\'bxxxx) + begin + $display(""FAILED - 3.1.4C - initial value not xxxx;\ +""); + err = 1; + end + #10 ; + if(value1 != 4\'h5) + begin + $display(""FAILED - 3.1.4C - always # delay_value reg_lvalue = boolean_expr\ +""); + err = 1; + end + #10 ; + if(value1 != 4\'hA) + begin + $display(""FAILED - 3.1.4C - always # delay_value reg_lvalue = boolean_expr\ +""); + err = 1; + end + + if (err == 0) + $display(""PASSED\ +""); + + $finish; + + end + +always # 10 value1 = ~value1; + +endmodule +" +"module tern; + +reg [13:0] fdbk_err_wide; + +// arithmetic saturation from 14 bits down to 13 bits, and drop lsb +wire [11:0] fdbk_err = ((fdbk_err_wide[13:12]==2\'b00) | (fdbk_err_wide[13:12]==2\'b11)) ? + fdbk_err_wide[12:1] : {fdbk_err_wide[13],{11{~fdbk_err_wide[13]}}}; + +initial begin +\t#10; +\t$display(fdbk_err_wide, fdbk_err); +\t// 2008-03-04 snapshot prints x x, 2008-04-02 git prints x z +\t// 01eb298228d0adce9d62818e21d47fb274af9060 is first ""bad"" commit +\t#10; +\tfdbk_err_wide = 42; +\t#10; +\t$display(fdbk_err_wide, fdbk_err); +\t// everybody agrees this is 42 21 +\t#10; +\tfdbk_err_wide = 14\'bxxxxxxxxxxxxxx; +\t#10; +\t// everybody agrees this is x x +\t$display(fdbk_err_wide, fdbk_err); +\t#10; +\t$finish(0); +end + +endmodule +" +"`begin_keywords ""1364-2005"" +module automatic_error(); + +reg global; + +task automatic auto_task; + +begin:block + reg local; + + global <= @(local) 0; +end + +endtask + +endmodule +`end_keywords +" +"// This file extends the original bug test case to explore all the +// forms of a signed right shift that are treated as special cases. +module test; + reg pass; + reg [8*40:1] str; + integer s; + + initial begin + pass = 1\'b1; + s = 1; + + $sformat(str, ""%0d"", ((0 >> 1) + 1) * -1); + if (str[8*2:1] !== ""-1"" || str[8*40:8*2+1] !== 0) begin + $display(""FAILED 1st test, expected \\""-1\\"", got %s"", str); + pass = 1\'b0; + end + + $sformat(str, ""%0d"", ((2 >> 1) + 1) * -1); + if (str[8*2:1] !== ""-2"" || str[8*40:8*2+1] !== 0) begin + $display(""FAILED 2nd test, expected \\""-2\\"", got %s"", str); + pass = 1\'b0; + end + + $sformat(str, ""%0d"", ((2 >> s) + 1) * -1); + if (str[8*2:1] !== ""-2"" || str[8*40:8*2+1] !== 0) begin + $display(""FAILED 3rd test, expected \\""-2\\"", got %s"", str); + pass = 1\'b0; + end + + $sformat(str, ""%0d"", ((s >> 1) + 1) * -1); + if (str[8*2:1] !== ""-1"" || str[8*40:8*2+1] !== 0) begin + $display(""FAILED 4th test, expected \\""-1\\"", got %s"", str); + pass = 1\'b0; + end + + $sformat(str, ""%0d"", ((s >> 0) + 1) * -1); + if (str[8*2:1] !== ""-2"" || str[8*40:8*2+1] !== 0) begin + $display(""FAILED 5th test, expected \\""-2\\"", got %s"", str); + pass = 1\'b0; + end + + $sformat(str, ""%0d"", ((s >> 64) + 1) * -1); + if (str[8*2:1] !== ""-1"" || str[8*40:8*2+1] !== 0) begin + $display(""FAILED 6th test, expected \\""-1\\"", got %s"", str); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"`begin_keywords ""1364-2005"" +module automatic_error(); + +task automatic auto_task; + +integer local; + +begin + local = 1; + $fstrobe(1, ""%0d"", local); +end + +endtask + +initial auto_task; + +endmodule +`end_keywords +" +"// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test casting integers to real + +module cast_real(); + int i; + logic [3:0] l; + logic signed [3:0] sl; + real a, b, c, d, e; + +initial begin + // Initalization using an integer variable + i = 5; + a = real\'(i); + + // ..and logic + l = 4\'b1010; + b = real\'(l); + + sl = 4\'b1010; + c = real\'(sl); + + // Initialization using an integer constant + d = real\'(11); + e = real\'(-7); + + if (a != 5.0) + begin + $display(""FAILED #1 a = %f"", a); + $finish(); + end + + if (b != 10.0) + begin + $display(""FAILED #2 b = %f"", b); + $finish(); + end + + if (c != -6.0) + begin + $display(""FAILED #3 c = %f"", c); + $finish(); + end + + if (d != 11.0) + begin + $display(""FAILED #4 d = %f"", d); + $finish(); + end + + if (e != -7.0) + begin + $display(""FAILED #5 e = %f"", e); + $finish(); + end + + $display(""PASSED""); +end +endmodule +" +"module param_width(); + +parameter a = 3\'d4; +parameter b = 3\'d5; +parameter c = 3\'d4; +parameter d = 3\'d5; + +parameter [3:0] sum1 = a + b; +parameter sum2 = a + b; +parameter [3:0] sum3 = c + d; +parameter sum4 = c + d; + +defparam c = 2\'d2; +defparam d = 2\'d3; + +initial begin + $display(""%b"", sum1); + $display(""%b"", sum2); + $display(""%b"", sum3); + $display(""%b"", sum4); +end + +endmodule +" +"module main; + + reg [4:0] val; + + ornor4 dut (.O_OR(o_or), .O_NOR(o_nor), +\t .I0(val[0]), .I1(val[1]), .I2(val[2]), .I3(val[3])); + + initial begin + for (val = 0 ; val[4] == 0 ; val = val+1) begin +\t #1 if (o_or !== |val[3:0]) begin +\t $display(""FAILED -- |%b --> %b"", val[3:0], o_or); +\t $finish; +\t end + +\t if (o_nor !== ~|val[3:0]) begin +\t $display(""FAILED -- ~|%b --> %b"", val[3:0], o_nor); +\t $finish; +\t end + end // for (val = 0 ; val[4] == 0 ; val = val+1) + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"module bufifab (output Out0, output Out1, input I, input E); + + bufif0 (Out0, I, E); + bufif1 (Out1, I, E); + +endmodule +" +"/* + * Based on PR#1008 + */ + +`timescale 1 ps / 1 ps + +module star; + +reg a; +reg b; + +initial begin + $monitor(""b = %b"", b); + #1; + a = 1; + #2; + a = 0; + #2; + a = 1; +end + +/* This generated the error: + :0: internal error: NetProc::nex_output not implemented + Before CVS 20040630 */ +always @* begin + b = #1 ~a; +end + +endmodule // star +" +"// test that if the port doesn't exist, an error is thrown +module m(input a, output b); +assign b = a; +endmodule + +module top; +reg a; +wire b; +wire c; +m foo(.a, .b, .c); +endmodule +" +"// Based on https://github.com/YosysHQ/yosys/blob/master/tests/various/const_func.v +// +// ISC License +// +// Copyright (C) 2012 - 2020 Claire Wolf +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED ""AS IS"" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +module Example(outA, outB, outC, outD); + parameter OUTPUT = ""FOO""; + output wire [23:0] outA; + output wire [23:0] outB; + output reg outC, outD; + function automatic [23:0] flip; + input [23:0] inp; + flip = ~inp; + endfunction + + generate + if (flip(OUTPUT) == flip(""BAR"")) + assign outA = OUTPUT; + else + assign outA = 0; + + case (flip(OUTPUT)) + flip(""FOO""): assign outB = OUTPUT; + flip(""BAR""): assign outB = 0; + flip(""BAZ""): assign outB = ""HI""; + endcase + + genvar i; + initial outC = 0; + for (i = 0; i != flip(flip(OUTPUT[15:8])); i = i + 1) + if (i + 1 == flip(flip(""O""))) + initial #1 outC = 1; + endgenerate + + integer j; + initial begin + outD = 1; + for (j = 0; j != flip(flip(OUTPUT[15:8])); j = j + 1) + if (j + 1 == flip(flip(""O""))) + outD = 0; + end +endmodule + +module top(out); + wire [23:0] a1, a2, a3, a4; + wire [23:0] b1, b2, b3, b4; + wire c1, c2, c3, c4; + wire d1, d2, d3, d4; + Example e1(a1, b1, c1, d1); + Example #(""FOO"") e2(a2, b2, c2, d2); + Example #(""BAR"") e3(a3, b3, c3, d3); + Example #(""BAZ"") e4(a4, b4, c4, d4); + + output wire [24 * 8 - 1 + 4 :0] out; + assign out = { + a1, a2, a3, a4, + b1, b2, b3, b4, + c1, c2, c3, c4, + d1, d2, d3, d4}; + + initial begin + #2; + $display(""%h %h %h %h"", a1, a2, a3, a4); + $display(""%h %h %h %h"", b1, b2, b3, b4); + $display(c1,,c2,,c3,,c4); + $display(d1,,d2,,d3,,d4); + if((a1 === 0) + && (a2 === 0) + && (a3 === ""BAR"") + && (a4 === 0) + && (b1 === ""FOO"") + && (b2 === ""FOO"") + && (b3 === 0) + && (b4 === ""HI"") + && (c1 === 1) + && (c2 === 1) + && (c3 === 0) + && (c4 === 0) + && (d1 === 0) + && (d2 === 0) + && (d3 === 1) + && (d4 === 1)) + $display(""PASSED""); + else + $display(""FAILED""); + end +endmodule +" +"// This program is about testing that the value ranges parse and work for +// integer parameters. +module test(input wire in); + + parameter integer foo = 0 from [-10 : 10] exclude [1:2); + parameter integer bar = 0 from (-inf:0]; + + initial begin + $display(""foo = %d"", foo); + $display(""PASSED""); + $finish; + end + +endmodule // test + +module main; + + reg rrr = 0; + test #(.foo(2), .bar(-5)) dut (rrr); + +endmodule // main +" +"// +// Copyright (c) 1999 Paul Bain (pdbain@adm.org) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - PR122 - Const define without length specification causes error. + +`timescale 1ns/1ns +module main( +clk, +dat +); + +parameter dat_width =32; +input clk; +output [dat_width-1:0] dat; +reg [dat_width-1:0] dat; +reg [32-1:0] exp_dat; +reg error; + +initial + begin + exp_dat = 0; + dat = 0; + end + +initial + begin + dat = #1 \'h00010203; + exp_dat = #1 \'h0010203; + error = 0; + #10; + for (exp_dat = 0; exp_dat != 4\'hf; exp_dat = exp_dat + 1) + begin + dat = exp_dat; + #1 + if(dat !== exp_dat) + begin + $display(""ERROR: dat = %h, exp_dat = %h"",dat,exp_dat); +\t error = 1; + end + else + $display(""Okay: dat = %h, exp_dat = %h"",dat,exp_dat); + end + if(error === 0) + $display(""PASSED""); + else + $display(""FAILED""); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always #1 disable task_identifier ; + +module main ; + + +reg [3:0] value1 ; + +task foo ; + value1 = #2 1; +endtask + +initial + begin + value1 = 1\'b0; + #5; + foo ; + #4 ; + if(value1 === 1\'b0) + $display(""PASSED""); + else + $display(""FAILED - always3.1.9C always #2 disable foo""); + $finish ; + end + +always #6 disable foo ; + +endmodule +" +"module test (d, en, g, s, a); + + input [31:2] d; + input en; + output g, s, a; + + reg g, s, a; + reg [31:21] r14; + reg [2:0] r18; + + always @(d or r18 or r14 or en) begin + casex ({d[31:12],r18[2:0],en}) + {20\'b1111_1111_0011_????_????, 3\'b???, 1\'b1} : s = 1\'b1; + {20\'b1111_1111_0010_????_????, 3\'b???, 1\'b1} : g = 1\'b1; + {{r14[31:21], 9\'b0_01??_????}, 3\'b???, 1\'b?} : a = 1\'b1; + {{r14[31:21], 9\'b1_????_????}, 3\'b???, 1\'b?} : a = 1\'b1; + endcase + end + + // Other tests check functionality so if this compiles it is fine. + initial $display(""PASSED""); + +endmodule +" +"/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test checks that the upwards search for a name stops at a + * module boundary. In this example, the q variable in the instance + * ""inst"" of the test module should be an implicit wire, even though + * it is placed into the containing main scope that has a wire q in it. + */ + +module test(p); + output p; + + wire q = 1; + assign p = q; + +endmodule // test + +module main; + + wire q = 0; + wire sig; + test inst(sig); + + initial begin + #1 if (q !== 1\'b0) begin +\t $display(""FAILED -- main.q == %b"", q); +\t $finish; + end + + if (sig !== 1\'b1) begin +\t $display(""FAILED -- main.test.q == %b"", sig); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"/* + * This test reflects the problem reported in PR#1115. + */ +module test; + + reg[7:0] addr [0:2], pixel; + + wire match0 = addr[0] == pixel; + + initial begin + pixel = 1; + addr[0] = 1; + addr[1] = 2; + addr[2] = 3; + #1 if (match0 !== 1\'b1) begin +\t $display(""FAILED -- match0 is %b"", match0); +\t $finish; + end + + $display(""PASSED""); + $finish; + end // initial begin + +endmodule +" +"/* + * Check declarations and repeat declarations in nested modules. + */ +timeunit 100us/1us; + +// Both a local time unit and precision are OK. +module check_tup_nest; + timeunit 10us / 10us; + module nested; + timeunit 100us / 1us; + timeunit 100us / 1us; + endmodule + timeunit 10us / 10us; +endmodule + +module check2(); + +initial begin + $printtimescale(check_tup_nest); + $printtimescale(check_tup_nest.nested); +end + +endmodule +" +" +/* + * This is a post-wynthesis test for the blif01a.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif01a.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter WID = 4; + reg [WID-1:0] A, B; + wire [WID:0] Q; + + subN usum(.\\A[3] (A[3]), .\\A[2] (A[2]), .\\A[1] (A[1]), .\\A[0] (A[0]), +\t .\\B[3] (B[3]), .\\B[2] (B[2]), .\\B[1] (B[1]), .\\B[0] (B[0]), +\t .\\Q[4] (Q[4]), .\\Q[3] (Q[3]), .\\Q[2] (Q[2]), .\\Q[1] (Q[1]), .\\Q[0] (Q[0])); + + int\t\t adx; + int\t\t bdx; + initial begin + for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin +\t for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin +\t A <= adx[WID-1:0]; +\t B <= bdx[WID-1:0]; +\t #1 if (Q !== (adx[WID-1:0]-bdx[WID-1:0])) begin +\t $display(""FAILED -- A=%b, B=%b, Q=%b"", A, B, Q); +\t $finish; +\t end +\t end + end + $display(""PASSED""); + end + +endmodule // main +" +"/* + * Copyright (c) 1999 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// This example describes a 16x1 RAM that can be synthesized into +// a CLB ram in a Xilinx FPGA. + +module ram16x1 (q, d, a, we, wclk); + output q; + input d; + input [3:0] a; + input we; + input wclk; + + reg mem[15:0]; + + assign q = mem[a]; + always @(posedge wclk) if (we) mem[a] = d; + +endmodule /* ram16x1 */ + +module main; + wire q; + reg d; + reg [3:0] a; + reg we, wclk; + + ram16x1 r1 (q, d, a, we, wclk); + + initial begin + wclk = 0; + we = 1; + for (a = 0 ; a < 4\'hf ; a = a + 1) begin +\t d = a[0]; +\t #1 wclk = 1; +\t #1 wclk = 0; +\t $display(""r1[%h] == %b"", a, q); + end + + for (a = 0 ; a < 4\'hf ; a = a + 1) +\t #1 if (q !== a[0]) begin +\t $display(""FAILED -- mem[%h] !== %b"", a, a[0]); +\t $finish; +\t end + + $display(""PASSED""); + end +endmodule /* main */ +" +"/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: task_scope.v,v 1.1 2001/06/19 13:52:13 ka6s Exp $ +// $Log: task_scope.v,v $ +// Revision 1.1 2001/06/19 13:52:13 ka6s +// Added 4 tests from Stephan Boettcher +// + +// Test for task scope lookup in VVP + +module test; + + wire w; + + jobs j(w); + + task ini; + begin +\t j.set(1\'bz); + end + endtask + + initial + begin +\tini; +\t#1; +\tj.set(1\'b1); +\t#1; +\tif (w===1) +\t $display(""PASSED""); +\telse +\t $display(""FAILED""); + end + +endmodule // test + +module jobs (out); + + output out; + reg\t out; + + task set; + input val; + begin +\t #1 out = val; + end + endtask + +endmodule // jobs +" +"/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test was inspired by PR#539. We check that the calculated bit + * select of a net in a continuous assignment gets bits in the right + * order and position. The trick here is that the bits are numbered + * from MSB to LSB. + */ + +module main; + + reg [63:0] target0 = 64\'h0040_2000_0000_0000; + reg [64:1] target1 = 64\'h0040_2000_0000_0000; + reg [6:0] idx; + + wire mux0 = target0[idx]; + wire mux1 = target1[idx+1]; + + initial begin + $display( ""Using constant indices:"" ); + $display( "" %b=v[45]"", target0[45] ); + if (target0[45] !== 1\'b1) begin +\t $display(""FAILED -- target0[45] != 1""); +\t $finish; + end + + $display( "" %b=v[54]"", target0[54] ); + if (target0[54] !== 1\'b1) begin +\t $display(""FAILED -- target0[54] != 1""); +\t $finish; + end + + $display( "" %b=v[18]"", target0[18] ); + if (target0[18] !== 1\'b0) begin +\t $display(""FAILED -- target0[18] != 0""); +\t $finish; + end + + $display( "" %b=v[ 9]"", target0[9] ); + if (target0[9] !== 1\'b0) begin +\t $display(""FAILED -- target0[ 9] != 0""); +\t $finish; + end + + $display( ""Using calcuated indices:"" ); + for (idx = 0 ; idx < 64 ; idx = idx + 1) begin +\t #1 $display(""target0[%2d]=%b, mux0=%b"", idx, target0[idx], mux0); +\t $display(""target1[%2d]=%b, mux1=%b"", idx+1, target1[idx+1], mux1); + +\t if (target0[idx] !== mux0) begin +\t $display(""FAILED -- target0[idx] != mux0""); +\t $finish; +\t end + +\t if (target1[idx+1] !== mux1) begin +\t $display(""FAILED -- target1[idx+1] != mux1""); +\t $finish; +\t end + end + + $display(""PASSED""); + end + +endmodule // main +" +"// This will not generate a RE if these are calling the correct warning. +module top; + integer res; + + initial begin + // $countdrivers is now implemented + res = $getpattern; + $input; + $key; + $nokey; + $list; + $log; + $nolog; + $save; + $restart; + $incsave; + res = $scale; + $scope; + $showscopes; + $showvars; + $sreadmemb; + $sreadmemh; + $display(""PASSED""); + end +endmodule +" +"`timescale 1ns/1ps + +module top; + reg pass; + reg ina, inb; + wire out; + + my_or dut(out, ina, inb); + + initial begin + pass = 1\'b1; + ina = 1\'b0; + inb = 1\'b0; + #0.399 + if (out !== 1\'bx && out !== 1\'bz) begin + $display(""FAILED: gate had incorrect delay, expected x/z, got %b."", out); + pass = 1\'b0; + end + #0.002 + if (out !== 1\'b0) begin + $display(""FAILED: gate had incorrect delay, expected 0, got %b."", out); + pass = 1\'b0; + end + + // Check inertial delays. + ina = 1\'b1; + #0.399 + ina = 1\'b0; + #0.002 + if (out !== 1\'b0) begin + $display(""FAILED: inertial delay, expected 0, got %b."", out); + pass = 1\'b0; + end + + // Check that this change is relative to the first edge. + ina = 1\'b1; + #0.200; + inb = 1\'b1; + #0.201; + if (out !== 1\'b1) begin + $display(""FAILED: double edge delay, expected 1, got %b."", out); + pass = 1\'b0; + #0.200; + if (out === 1\'b1) begin + $display(""FAILED: double edge delay was off second edge.""); + end + end + + if (pass) $display(""PASSED""); + end +endmodule + +module my_or(out, ina, inb); + output out; + input ina, inb; + + or(out, ina, inb); + + specify + (ina, inb *> out) = 0.4; + endspecify +endmodule +" +"`timescale 1ns/10ps +module top; + reg pass; + reg [60*8-1:0] str, cmp; + reg [7:0] bval; + reg [15:0] oval, hval; + integer dval; + time tval; + real rval; + + initial begin + pass = 1\'b1; + + // Check the %b conversion. + bval = 8\'b01101001; + cmp = ""1101001""; + $sformat(str, ""%0b"", bval); + if (str != cmp) begin + $display(""FAILED: %%0b, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""0000000001101001""; + $sformat(str, ""%016b"", bval); + if (str != cmp) begin + $display(""FAILED: %%016b, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""1101001 ""; + $sformat(str, ""%-016b"", bval); + if (str != cmp) begin + $display(""FAILED: %%-016b, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + // Check the %o conversion. + oval = 16\'o01234; + cmp = ""1234""; + $sformat(str, ""%0o"", oval); + if (str != cmp) begin + $display(""FAILED: %%0o, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""00001234""; + $sformat(str, ""%08o"", oval); + if (str != cmp) begin + $display(""FAILED: %%08o, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""1234 ""; + $sformat(str, ""%-08o"", oval); + if (str != cmp) begin + $display(""FAILED: %%-08o, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + // Check the %h conversion. + hval = 16\'h0abc; + cmp = ""abc""; + $sformat(str, ""%0h"", hval); + if (str != cmp) begin + $display(""FAILED: %%0h, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""00000abc""; + $sformat(str, ""%08h"", hval); + if (str != cmp) begin + $display(""FAILED: %%08h, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""abc ""; + $sformat(str, ""%-08h"", hval); + if (str != cmp) begin + $display(""FAILED: %%-08h, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + // Check the %c conversion. + bval = ""c""; + cmp = ""c""; + $sformat(str, ""%0c"", bval); + if (str != cmp) begin + $display(""FAILED: %%0c, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""000c""; + $sformat(str, ""%04c"", bval); + if (str != cmp) begin + $display(""FAILED: %%04c, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + // Check the %d conversion. + dval = 123; + cmp = ""00000123""; + $sformat(str, ""%08d"", dval); + if (str != cmp) begin + $display(""FAILED: %%08d, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""+0000123""; + $sformat(str, ""%+08d"", dval); + if (str != cmp) begin + $display(""FAILED: %%+08d, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = "" 123""; + $sformat(str, ""%d"", dval); + if (str != cmp) begin + $display(""FAILED: %%d, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""123 ""; + $sformat(str, ""%-08d"", dval); + if (str != cmp) begin + $display(""FAILED: %%-08d, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""123""; + $sformat(str, ""%0d"", dval); + if (str != cmp) begin + $display(""FAILED: %%0d, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + dval = -123; + cmp = ""-0000123""; + $sformat(str, ""%08d"", dval); + if (str != cmp) begin + $display(""FAILED: %%08d, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + $sformat(str, ""%+08d"", dval); + if (str != cmp) begin + $display(""FAILED: %%+08d, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = "" -123""; + $sformat(str, ""%d"", dval); + if (str != cmp) begin + $display(""FAILED: %%d, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + // Check the %t conversion. + tval = 100_000; + cmp = ""0010000000""; + $sformat(str, ""%010t"", tval); + if (str != cmp) begin + $display(""FAILED: %%010t, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = "" 10000000""; // Default width is 20. + $sformat(str, ""%t"", tval); + if (str != cmp) begin + $display(""FAILED: %%t, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""10000000 ""; + $sformat(str, ""%-010t"", tval); + if (str != cmp) begin + $display(""FAILED: %%-010t, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""10000000""; + $sformat(str, ""%0t"", tval); + if (str != cmp) begin + $display(""FAILED: %%0t, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + rval=100_000.25; + cmp = ""0010000025""; + $sformat(str, ""%010t"", rval); + if (str != cmp) begin + $display(""FAILED: %%010t (real), expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = "" 10000025""; // Default width is 20. + $sformat(str, ""%t"", rval); + if (str != cmp) begin + $display(""FAILED: %%t (real), expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""10000025 ""; + $sformat(str, ""%-010t"", rval); + if (str != cmp) begin + $display(""FAILED: %%-010t (real), expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""10000025""; + $sformat(str, ""%0t"", rval); + if (str != cmp) begin + $display(""FAILED: %%0t (real), expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + // Display in ns with 10ps resolution. + $timeformat(-9, 2, "" ns"", 15); + + cmp = ""000100000.00 ns""; + $sformat(str, ""%015t"", tval); + if (str != cmp) begin + $display(""FAILED: %%015t (w/$tf), expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = "" 100000.00 ns""; + $sformat(str, ""%t"", tval); + if (str != cmp) begin + $display(""FAILED: %%t (w/$tf), expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""100000.00 ns ""; + $sformat(str, ""%-015t"", tval); + if (str != cmp) begin + $display(""FAILED: %%-015t (w/$tf), expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""100000.00 ns""; + $sformat(str, ""%-0t"", tval); + if (str != cmp) begin + $display(""FAILED: %%-0t (w/$tf), expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""000100000.25 ns""; + $sformat(str, ""%015t"", rval); + if (str != cmp) begin + $display(""FAILED: %%015t (w/$tf, rl), expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = "" 100000.25 ns""; + $sformat(str, ""%t"", rval); + if (str != cmp) begin + $display(""FAILED: %%t (w/$tf, rl), expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""100000.25 ns ""; + $sformat(str, ""%-015t"", rval); + if (str != cmp) begin + $display(""FAILED: %%-015t (w/$tf, rl), expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""100000.25 ns""; + $sformat(str, ""%-0t"", rval); + if (str != cmp) begin + $display(""FAILED: %%-0t (w/$tf, rl), expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + // Check the real conversions (%e, %f, %g). If one works they all + // they all work (uses system conversion). + + rval = 1.25; + cmp = ""000000001.250000""; + $sformat(str, ""%016.6f"", rval); + if (str != cmp) begin + $display(""FAILED: %%016.6f, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""+00000001.250000""; + $sformat(str, ""%+016.6f"", rval); + if (str != cmp) begin + $display(""FAILED: %%+016.6f, expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + rval = -1.25; + cmp = ""-00000001.250000""; + $sformat(str, ""%016.6f"", rval); + if (str != cmp) begin + $display(""FAILED: %%016.6f (negative), expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + cmp = ""-00000001.250000""; + $sformat(str, ""%+016.6f"", rval); + if (str != cmp) begin + $display(""FAILED: %%+016.6f (negative), expected %0s, got %0s"", cmp, str); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"`timescale 1ns/1ps + +module top; + realtime rtime; + time itime; + + initial begin + repeat (5) begin + rtime = $realtime; + itime = $time; + $display(""%4t %.2f %2d, %4t %0.2f %2d, %4t %.2f, %4t %0.2f, %4t %.2f,"", + $time, $time, $time, itime, itime, itime, + $realtime, $realtime, rtime, rtime, rtm($realtime), + rtm($realtime),, $time,, $realtime); + #0.6; + end + end + + function real rtm; + input real rin; + rtm = rin; + endfunction +endmodule +" +"module top; + reg pass; + reg [7:0] idx; + reg [7:0] mem [0:7]; + + initial begin + pass = 1\'b1; + + // Neither no_dir or no_dir2 should exist and vsim should be a file. + $readmempath(""/tmp:/no_dir:no_dir2:vsim:ivltests""); + + $readmemh(""pr2509349.txt"", mem); + + for (idx = 0; idx < 8; idx = idx + 1) begin + if (mem[idx] !== idx) begin + $display(""Failed mem[%0d], expected %d, got %d"", idx, idx, mem[idx]); + pass = 1\'b0; + end + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"/* + * This test program should cause the message ""Hello, World"" to + * display twice. The first when the always thread runs and gets + * stuck in the wait, and the second when the block is disabled, + * and the alwas thread starts it over again. + */ + +module main; + + always begin :restartable + $display(""Test thread runs.""); + wait (0); + $display(""FAILED: Should never get here.""); + end + + initial begin + #10 disable restartable; + #10 $finish(0); + end + +endmodule // main +" +"// This tests literal values, from verilog 2001 and SystemVerilog +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test (); + + // logic vector + logic unsigned [15:0] luv; // logic unsigned vector + logic signed [15:0] lsv; // logic signed vector + + // error counter + bit err = 0; + + initial begin + // unsized literals without base + luv = \'0; if (luv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- luv = \'b%b != \'0"", luv); err=1; end + luv = \'1; if (luv !== 16\'b1111_1111_1111_1111) begin $display(""FAILED -- luv = \'b%b != \'1"", luv); err=1; end + luv = \'x; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- luv = \'b%b != \'x"", luv); err=1; end + luv = \'z; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- luv = \'b%b != \'z"", luv); err=1; end + + // unsized binary literals single character + luv = \'b0; if (luv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- luv = \'b%b != \'b0"", luv); err=1; end + luv = \'b1; if (luv !== 16\'b0000_0000_0000_0001) begin $display(""FAILED -- luv = \'b%b != \'b1"", luv); err=1; end + luv = \'bx; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- luv = \'b%b != \'bx"", luv); err=1; end + luv = \'bz; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- luv = \'b%b != \'bz"", luv); err=1; end + // unsized binary literals two characters + luv = \'b00; if (luv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- luv = \'b%b != \'b00"", luv); err=1; end + luv = \'b11; if (luv !== 16\'b0000_0000_0000_0011) begin $display(""FAILED -- luv = \'b%b != \'b11"", luv); err=1; end + luv = \'bxx; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- luv = \'b%b != \'bxx"", luv); err=1; end + luv = \'bzz; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- luv = \'b%b != \'bzz"", luv); err=1; end + luv = \'b1x; if (luv !== 16\'b0000_0000_0000_001x) begin $display(""FAILED -- luv = \'b%b != \'b1x"", luv); err=1; end + luv = \'b1z; if (luv !== 16\'b0000_0000_0000_001z) begin $display(""FAILED -- luv = \'b%b != \'b1z"", luv); err=1; end + luv = \'bx1; if (luv !== 16\'bxxxx_xxxx_xxxx_xxx1) begin $display(""FAILED -- luv = \'b%b != \'bx1"", luv); err=1; end + luv = \'bz1; if (luv !== 16\'bzzzz_zzzz_zzzz_zzz1) begin $display(""FAILED -- luv = \'b%b != \'bz1"", luv); err=1; end + + // unsized binary literals single character + luv = \'o0; if (luv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- luv = \'b%b != \'o0"", luv); err=1; end + luv = \'o5; if (luv !== 16\'b0000_0000_0000_0101) begin $display(""FAILED -- luv = \'b%b != \'o5"", luv); err=1; end + luv = \'ox; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- luv = \'b%b != \'ox"", luv); err=1; end + luv = \'oz; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- luv = \'b%b != \'oz"", luv); err=1; end + // unsized binary literals two characters + luv = \'o00; if (luv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- luv = \'b%b != \'o00"", luv); err=1; end + luv = \'o55; if (luv !== 16\'b0000_0000_0010_1101) begin $display(""FAILED -- luv = \'b%b != \'o55"", luv); err=1; end + luv = \'oxx; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- luv = \'b%b != \'oxx"", luv); err=1; end + luv = \'ozz; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- luv = \'b%b != \'ozz"", luv); err=1; end + luv = \'o5x; if (luv !== 16\'b0000_0000_0010_1xxx) begin $display(""FAILED -- luv = \'b%b != \'o5x"", luv); err=1; end + luv = \'o5z; if (luv !== 16\'b0000_0000_0010_1zzz) begin $display(""FAILED -- luv = \'b%b != \'o5z"", luv); err=1; end + luv = \'ox5; if (luv !== 16\'bxxxx_xxxx_xxxx_x101) begin $display(""FAILED -- luv = \'b%b != \'ox5"", luv); err=1; end + luv = \'oz5; if (luv !== 16\'bzzzz_zzzz_zzzz_z101) begin $display(""FAILED -- luv = \'b%b != \'oz5"", luv); err=1; end + + // unsized binary literals single character + luv = \'h0; if (luv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- luv = \'b%b != \'h0"", luv); err=1; end + luv = \'h9; if (luv !== 16\'b0000_0000_0000_1001) begin $display(""FAILED -- luv = \'b%b != \'h9"", luv); err=1; end + luv = \'hx; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- luv = \'b%b != \'hx"", luv); err=1; end + luv = \'hz; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- luv = \'b%b != \'hz"", luv); err=1; end + // unsized binary literals two characters + luv = \'h00; if (luv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- luv = \'b%b != \'h00"", luv); err=1; end + luv = \'h99; if (luv !== 16\'b0000_0000_1001_1001) begin $display(""FAILED -- luv = \'b%b != \'h99"", luv); err=1; end + luv = \'hxx; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- luv = \'b%b != \'hxx"", luv); err=1; end + luv = \'hzz; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- luv = \'b%b != \'hzz"", luv); err=1; end + luv = \'h9x; if (luv !== 16\'b0000_0000_1001_xxxx) begin $display(""FAILED -- luv = \'b%b != \'h9x"", luv); err=1; end + luv = \'h9z; if (luv !== 16\'b0000_0000_1001_zzzz) begin $display(""FAILED -- luv = \'b%b != \'h9z"", luv); err=1; end + luv = \'hx9; if (luv !== 16\'bxxxx_xxxx_xxxx_1001) begin $display(""FAILED -- luv = \'b%b != \'hx9"", luv); err=1; end + luv = \'hz9; if (luv !== 16\'bzzzz_zzzz_zzzz_1001) begin $display(""FAILED -- luv = \'b%b != \'hz9"", luv); err=1; end + + // unsized binary literals single character + luv = \'d0; if (luv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- luv = \'b%b != \'d0"", luv); err=1; end + luv = \'d9; if (luv !== 16\'b0000_0000_0000_1001) begin $display(""FAILED -- luv = \'b%b != \'d9"", luv); err=1; end + luv = \'dx; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- luv = \'b%b != \'dx"", luv); err=1; end + luv = \'dz; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- luv = \'b%b != \'dz"", luv); err=1; end + // unsized binary literals two characters + luv = \'d00; if (luv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- luv = \'b%b != \'d00"", luv); err=1; end + luv = \'d99; if (luv !== 16\'b0000_0000_0110_0011) begin $display(""FAILED -- luv = \'b%b != \'d99"", luv); err=1; end +// luv = \'dxx; if (luv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- luv = \'b%b != \'dxx"", luv); err=1; end +// luv = \'dzz; if (luv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- luv = \'b%b != \'dzz"", luv); err=1; end + + + // unsized binary literals single character + luv = 15\'b0; if (luv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- luv = \'b%b != 15\'b0"", luv); err=1; end + luv = 15\'b1; if (luv !== 16\'b0000_0000_0000_0001) begin $display(""FAILED -- luv = \'b%b != 15\'b1"", luv); err=1; end + luv = 15\'bx; if (luv !== 16\'b0xxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- luv = \'b%b != 15\'bx"", luv); err=1; end + luv = 15\'bz; if (luv !== 16\'b0zzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- luv = \'b%b != 15\'bz"", luv); err=1; end + // unsized binary literals two characters + luv = 15\'b00; if (luv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- luv = \'b%b != 15\'b00"", luv); err=1; end + luv = 15\'b11; if (luv !== 16\'b0000_0000_0000_0011) begin $display(""FAILED -- luv = \'b%b != 15\'b11"", luv); err=1; end + luv = 15\'bxx; if (luv !== 16\'b0xxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- luv = \'b%b != 15\'bxx"", luv); err=1; end + luv = 15\'bzz; if (luv !== 16\'b0zzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- luv = \'b%b != 15\'bzz"", luv); err=1; end + luv = 15\'b1x; if (luv !== 16\'b0000_0000_0000_001x) begin $display(""FAILED -- luv = \'b%b != 15\'b1x"", luv); err=1; end + luv = 15\'b1z; if (luv !== 16\'b0000_0000_0000_001z) begin $display(""FAILED -- luv = \'b%b != 15\'b1z"", luv); err=1; end + luv = 15\'bx1; if (luv !== 16\'b0xxx_xxxx_xxxx_xxx1) begin $display(""FAILED -- luv = \'b%b != 15\'bx1"", luv); err=1; end + luv = 15\'bz1; if (luv !== 16\'b0zzz_zzzz_zzzz_zzz1) begin $display(""FAILED -- luv = \'b%b != 15\'bz1"", luv); err=1; end + + // unsized binary literals single character + luv = 15\'o0; if (luv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- luv = \'b%b != 15\'o0"", luv); err=1; end + luv = 15\'o5; if (luv !== 16\'b0000_0000_0000_0101) begin $display(""FAILED -- luv = \'b%b != 15\'o5"", luv); err=1; end + luv = 15\'ox; if (luv !== 16\'b0xxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- luv = \'b%b != 15\'ox"", luv); err=1; end + luv = 15\'oz; if (luv !== 16\'b0zzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- luv = \'b%b != 15\'oz"", luv); err=1; end + // unsized binary literals two characters + luv = 15\'o00; if (luv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- luv = \'b%b != 15\'o00"", luv); err=1; end + luv = 15\'o55; if (luv !== 16\'b0000_0000_0010_1101) begin $display(""FAILED -- luv = \'b%b != 15\'o55"", luv); err=1; end + luv = 15\'oxx; if (luv !== 16\'b0xxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- luv = \'b%b != 15\'oxx"", luv); err=1; end + luv = 15\'ozz; if (luv !== 16\'b0zzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- luv = \'b%b != 15\'ozz"", luv); err=1; end + luv = 15\'o5x; if (luv !== 16\'b0000_0000_0010_1xxx) begin $display(""FAILED -- luv = \'b%b != 15\'o5x"", luv); err=1; end + luv = 15\'o5z; if (luv !== 16\'b0000_0000_0010_1zzz) begin $display(""FAILED -- luv = \'b%b != 15\'o5z"", luv); err=1; end + luv = 15\'ox5; if (luv !== 16\'b0xxx_xxxx_xxxx_x101) begin $display(""FAILED -- luv = \'b%b != 15\'ox5"", luv); err=1; end + luv = 15\'oz5; if (luv !== 16\'b0zzz_zzzz_zzzz_z101) begin $display(""FAILED -- luv = \'b%b != 15\'oz5"", luv); err=1; end + + // unsized binary literals single character + luv = 15\'h0; if (luv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- luv = \'b%b != 15\'h0"", luv); err=1; end + luv = 15\'h9; if (luv !== 16\'b0000_0000_0000_1001) begin $display(""FAILED -- luv = \'b%b != 15\'h9"", luv); err=1; end + luv = 15\'hx; if (luv !== 16\'b0xxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- luv = \'b%b != 15\'hx"", luv); err=1; end + luv = 15\'hz; if (luv !== 16\'b0zzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- luv = \'b%b != 15\'hz"", luv); err=1; end + // unsized binary literals two characters + luv = 15\'h00; if (luv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- luv = \'b%b != 15\'h00"", luv); err=1; end + luv = 15\'h99; if (luv !== 16\'b0000_0000_1001_1001) begin $display(""FAILED -- luv = \'b%b != 15\'h99"", luv); err=1; end + luv = 15\'hxx; if (luv !== 16\'b0xxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- luv = \'b%b != 15\'hxx"", luv); err=1; end + luv = 15\'hzz; if (luv !== 16\'b0zzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- luv = \'b%b != 15\'hzz"", luv); err=1; end + luv = 15\'h9x; if (luv !== 16\'b0000_0000_1001_xxxx) begin $display(""FAILED -- luv = \'b%b != 15\'h9x"", luv); err=1; end + luv = 15\'h9z; if (luv !== 16\'b0000_0000_1001_zzzz) begin $display(""FAILED -- luv = \'b%b != 15\'h9z"", luv); err=1; end + luv = 15\'hx9; if (luv !== 16\'b0xxx_xxxx_xxxx_1001) begin $display(""FAILED -- luv = \'b%b != 15\'hx9"", luv); err=1; end + luv = 15\'hz9; if (luv !== 16\'b0zzz_zzzz_zzzz_1001) begin $display(""FAILED -- luv = \'b%b != 15\'hz9"", luv); err=1; end + + // unsized binary literals single character + luv = 15\'d0; if (luv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- luv = \'b%b != 15\'d0"", luv); err=1; end + luv = 15\'d9; if (luv !== 16\'b0000_0000_0000_1001) begin $display(""FAILED -- luv = \'b%b != 15\'d9"", luv); err=1; end + luv = 15\'dx; if (luv !== 16\'b0xxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- luv = \'b%b != 15\'dx"", luv); err=1; end + luv = 15\'dz; if (luv !== 16\'b0zzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- luv = \'b%b != 15\'dz"", luv); err=1; end + // unsized binary literals two characters + luv = 15\'d00; if (luv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- luv = \'b%b != 15\'d00"", luv); err=1; end + luv = 15\'d99; if (luv !== 16\'b0000_0000_0110_0011) begin $display(""FAILED -- luv = \'b%b != 15\'d99"", luv); err=1; end +// luv = 15\'dxx; if (luv !== 16\'b0xxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- luv = \'b%b != 15\'dxx"", luv); err=1; end +// luv = 15\'dzz; if (luv !== 16\'b0zzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- luv = \'b%b != 15\'dzz"", luv); err=1; end + + + + + // unsized binary literals single character + lsv = \'sb0; if (lsv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- lsv = \'b%b != \'sb0"", lsv); err=1; end + lsv = \'sb1; if (lsv !== 16\'b0000_0000_0000_0001) begin $display(""FAILED -- lsv = \'b%b != \'sb1"", lsv); err=1; end + lsv = \'sbx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- lsv = \'b%b != \'sbx"", lsv); err=1; end + lsv = \'sbz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- lsv = \'b%b != \'sbz"", lsv); err=1; end + // unsized binary literals two characters + lsv = \'sb00; if (lsv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- lsv = \'b%b != \'sb00"", lsv); err=1; end + lsv = \'sb11; if (lsv !== 16\'b0000_0000_0000_0011) begin $display(""FAILED -- lsv = \'b%b != \'sb11"", lsv); err=1; end + lsv = \'sbxx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- lsv = \'b%b != \'sbxx"", lsv); err=1; end + lsv = \'sbzz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- lsv = \'b%b != \'sbzz"", lsv); err=1; end + lsv = \'sb1x; if (lsv !== 16\'b0000_0000_0000_001x) begin $display(""FAILED -- lsv = \'b%b != \'sb1x"", lsv); err=1; end + lsv = \'sb1z; if (lsv !== 16\'b0000_0000_0000_001z) begin $display(""FAILED -- lsv = \'b%b != \'sb1z"", lsv); err=1; end + lsv = \'sbx1; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxx1) begin $display(""FAILED -- lsv = \'b%b != \'sbx1"", lsv); err=1; end + lsv = \'sbz1; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzz1) begin $display(""FAILED -- lsv = \'b%b != \'sbz1"", lsv); err=1; end + + // unsized binary literals single character + lsv = \'so0; if (lsv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- lsv = \'b%b != \'so0"", lsv); err=1; end + lsv = \'so5; if (lsv !== 16\'b0000_0000_0000_0101) begin $display(""FAILED -- lsv = \'b%b != \'so5"", lsv); err=1; end + lsv = \'sox; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- lsv = \'b%b != \'sox"", lsv); err=1; end + lsv = \'soz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- lsv = \'b%b != \'soz"", lsv); err=1; end + // unsized binary literals two characters + lsv = \'so00; if (lsv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- lsv = \'b%b != \'so00"", lsv); err=1; end + lsv = \'so55; if (lsv !== 16\'b0000_0000_0010_1101) begin $display(""FAILED -- lsv = \'b%b != \'so55"", lsv); err=1; end + lsv = \'soxx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- lsv = \'b%b != \'soxx"", lsv); err=1; end + lsv = \'sozz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- lsv = \'b%b != \'sozz"", lsv); err=1; end + lsv = \'so5x; if (lsv !== 16\'b0000_0000_0010_1xxx) begin $display(""FAILED -- lsv = \'b%b != \'so5x"", lsv); err=1; end + lsv = \'so5z; if (lsv !== 16\'b0000_0000_0010_1zzz) begin $display(""FAILED -- lsv = \'b%b != \'so5z"", lsv); err=1; end + lsv = \'sox5; if (lsv !== 16\'bxxxx_xxxx_xxxx_x101) begin $display(""FAILED -- lsv = \'b%b != \'sox5"", lsv); err=1; end + lsv = \'soz5; if (lsv !== 16\'bzzzz_zzzz_zzzz_z101) begin $display(""FAILED -- lsv = \'b%b != \'soz5"", lsv); err=1; end + + // unsized binary literals single character + lsv = \'sh0; if (lsv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- lsv = \'b%b != \'sh0"", lsv); err=1; end + lsv = \'sh9; if (lsv !== 16\'b0000_0000_0000_1001) begin $display(""FAILED -- lsv = \'b%b != \'sh9"", lsv); err=1; end + lsv = \'shx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- lsv = \'b%b != \'shx"", lsv); err=1; end + lsv = \'shz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- lsv = \'b%b != \'shz"", lsv); err=1; end + // unsized binary literals two characters + lsv = \'sh00; if (lsv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- lsv = \'b%b != \'sh00"", lsv); err=1; end + lsv = \'sh99; if (lsv !== 16\'b0000_0000_1001_1001) begin $display(""FAILED -- lsv = \'b%b != \'sh99"", lsv); err=1; end + lsv = \'shxx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- lsv = \'b%b != \'shxx"", lsv); err=1; end + lsv = \'shzz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- lsv = \'b%b != \'shzz"", lsv); err=1; end + lsv = \'sh9x; if (lsv !== 16\'b0000_0000_1001_xxxx) begin $display(""FAILED -- lsv = \'b%b != \'sh9x"", lsv); err=1; end + lsv = \'sh9z; if (lsv !== 16\'b0000_0000_1001_zzzz) begin $display(""FAILED -- lsv = \'b%b != \'sh9z"", lsv); err=1; end + lsv = \'shx9; if (lsv !== 16\'bxxxx_xxxx_xxxx_1001) begin $display(""FAILED -- lsv = \'b%b != \'shx9"", lsv); err=1; end + lsv = \'shz9; if (lsv !== 16\'bzzzz_zzzz_zzzz_1001) begin $display(""FAILED -- lsv = \'b%b != \'shz9"", lsv); err=1; end + + // unsized binary literals single character + lsv = \'sd0; if (lsv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- lsv = \'b%b != \'sd0"", lsv); err=1; end + lsv = \'sd9; if (lsv !== 16\'b0000_0000_0000_1001) begin $display(""FAILED -- lsv = \'b%b != \'sd9"", lsv); err=1; end + lsv = \'sdx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- lsv = \'b%b != \'sdx"", lsv); err=1; end + lsv = \'sdz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- lsv = \'b%b != \'sdz"", lsv); err=1; end + // unsized binary literals two characters + lsv = \'sd00; if (lsv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- lsv = \'b%b != \'sd00"", lsv); err=1; end + lsv = \'sd99; if (lsv !== 16\'b0000_0000_0110_0011) begin $display(""FAILED -- lsv = \'b%b != \'sd99"", lsv); err=1; end +// lsv = \'sdxx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- lsv = \'b%b != \'sdxx"", lsv); err=1; end +// lsv = \'sdzz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- lsv = \'b%b != \'sdzz"", lsv); err=1; end + + + // unsized binary literals single character + lsv = 15\'sb0; if (lsv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- lsv = \'b%b != 15\'sb0"", lsv); err=1; end + lsv = 15\'sb1; if (lsv !== 16\'b0000_0000_0000_0001) begin $display(""FAILED -- lsv = \'b%b != 15\'sb1"", lsv); err=1; end + lsv = 15\'sbx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- lsv = \'b%b != 15\'sbx"", lsv); err=1; end + lsv = 15\'sbz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- lsv = \'b%b != 15\'sbz"", lsv); err=1; end + // unsized binary literals two characters + lsv = 15\'sb00; if (lsv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- lsv = \'b%b != 15\'sb00"", lsv); err=1; end + lsv = 15\'sb11; if (lsv !== 16\'b0000_0000_0000_0011) begin $display(""FAILED -- lsv = \'b%b != 15\'sb11"", lsv); err=1; end + lsv = 15\'sbxx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- lsv = \'b%b != 15\'sbxx"", lsv); err=1; end + lsv = 15\'sbzz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- lsv = \'b%b != 15\'sbzz"", lsv); err=1; end + lsv = 15\'sb1x; if (lsv !== 16\'b0000_0000_0000_001x) begin $display(""FAILED -- lsv = \'b%b != 15\'sb1x"", lsv); err=1; end + lsv = 15\'sb1z; if (lsv !== 16\'b0000_0000_0000_001z) begin $display(""FAILED -- lsv = \'b%b != 15\'sb1z"", lsv); err=1; end + lsv = 15\'sbx1; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxx1) begin $display(""FAILED -- lsv = \'b%b != 15\'sbx1"", lsv); err=1; end + lsv = 15\'sbz1; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzz1) begin $display(""FAILED -- lsv = \'b%b != 15\'sbz1"", lsv); err=1; end + + // unsized binary literals single character + lsv = 15\'so0; if (lsv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- lsv = \'b%b != 15\'so0"", lsv); err=1; end + lsv = 15\'so5; if (lsv !== 16\'b0000_0000_0000_0101) begin $display(""FAILED -- lsv = \'b%b != 15\'so5"", lsv); err=1; end + lsv = 15\'sox; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- lsv = \'b%b != 15\'sox"", lsv); err=1; end + lsv = 15\'soz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- lsv = \'b%b != 15\'soz"", lsv); err=1; end + // unsized binary literals two characters + lsv = 15\'so00; if (lsv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- lsv = \'b%b != 15\'so00"", lsv); err=1; end + lsv = 15\'so55; if (lsv !== 16\'b0000_0000_0010_1101) begin $display(""FAILED -- lsv = \'b%b != 15\'so55"", lsv); err=1; end + lsv = 15\'soxx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- lsv = \'b%b != 15\'soxx"", lsv); err=1; end + lsv = 15\'sozz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- lsv = \'b%b != 15\'sozz"", lsv); err=1; end + lsv = 15\'so5x; if (lsv !== 16\'b0000_0000_0010_1xxx) begin $display(""FAILED -- lsv = \'b%b != 15\'so5x"", lsv); err=1; end + lsv = 15\'so5z; if (lsv !== 16\'b0000_0000_0010_1zzz) begin $display(""FAILED -- lsv = \'b%b != 15\'so5z"", lsv); err=1; end + lsv = 15\'sox5; if (lsv !== 16\'bxxxx_xxxx_xxxx_x101) begin $display(""FAILED -- lsv = \'b%b != 15\'sox5"", lsv); err=1; end + lsv = 15\'soz5; if (lsv !== 16\'bzzzz_zzzz_zzzz_z101) begin $display(""FAILED -- lsv = \'b%b != 15\'soz5"", lsv); err=1; end + + // unsized binary literals single character + lsv = 15\'sh0; if (lsv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- lsv = \'b%b != 15\'sh0"", lsv); err=1; end + lsv = 15\'sh9; if (lsv !== 16\'b0000_0000_0000_1001) begin $display(""FAILED -- lsv = \'b%b != 15\'sh9"", lsv); err=1; end + lsv = 15\'shx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- lsv = \'b%b != 15\'shx"", lsv); err=1; end + lsv = 15\'shz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- lsv = \'b%b != 15\'shz"", lsv); err=1; end + // unsized binary literals two characters + lsv = 15\'sh00; if (lsv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- lsv = \'b%b != 15\'sh00"", lsv); err=1; end + lsv = 15\'sh99; if (lsv !== 16\'b0000_0000_1001_1001) begin $display(""FAILED -- lsv = \'b%b != 15\'sh99"", lsv); err=1; end + lsv = 15\'shxx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- lsv = \'b%b != 15\'shxx"", lsv); err=1; end + lsv = 15\'shzz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- lsv = \'b%b != 15\'shzz"", lsv); err=1; end + lsv = 15\'sh9x; if (lsv !== 16\'b0000_0000_1001_xxxx) begin $display(""FAILED -- lsv = \'b%b != 15\'sh9x"", lsv); err=1; end + lsv = 15\'sh9z; if (lsv !== 16\'b0000_0000_1001_zzzz) begin $display(""FAILED -- lsv = \'b%b != 15\'sh9z"", lsv); err=1; end + lsv = 15\'shx9; if (lsv !== 16\'bxxxx_xxxx_xxxx_1001) begin $display(""FAILED -- lsv = \'b%b != 15\'shx9"", lsv); err=1; end + lsv = 15\'shz9; if (lsv !== 16\'bzzzz_zzzz_zzzz_1001) begin $display(""FAILED -- lsv = \'b%b != 15\'shz9"", lsv); err=1; end + + // unsized binary literals single character + lsv = 15\'sd0; if (lsv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- lsv = \'b%b != 15\'sd0"", lsv); err=1; end + lsv = 15\'sd9; if (lsv !== 16\'b0000_0000_0000_1001) begin $display(""FAILED -- lsv = \'b%b != 15\'sd9"", lsv); err=1; end + lsv = 15\'sdx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- lsv = \'b%b != 15\'sdx"", lsv); err=1; end + lsv = 15\'sdz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- lsv = \'b%b != 15\'sdz"", lsv); err=1; end + // unsized binary literals two characters + lsv = 15\'sd00; if (lsv !== 16\'b0000_0000_0000_0000) begin $display(""FAILED -- lsv = \'b%b != 15\'sd00"", lsv); err=1; end + lsv = 15\'sd99; if (lsv !== 16\'b0000_0000_0110_0011) begin $display(""FAILED -- lsv = \'b%b != 15\'sd99"", lsv); err=1; end +// lsv = 15\'sdxx; if (lsv !== 16\'bxxxx_xxxx_xxxx_xxxx) begin $display(""FAILED -- lsv = \'b%b != 15\'sdxx"", lsv); err=1; end +// lsv = 15\'sdzz; if (lsv !== 16\'bzzzz_zzzz_zzzz_zzzz) begin $display(""FAILED -- lsv = \'b%b != 15\'sdzz"", lsv); err=1; end + + if (!err) $display(""PASSED""); + end + +endmodule // test +" +"// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test string escaping in VHDL. + +module vhdl_string_test; +logic start; +vhdl_string dut(start); +// nothing else is needed here +endmodule +" +"module top; + +wire [2:0] value = 2; + +shim shim( + .bit0(value[0]), + .bit1(value[1]), + .bit2(value[2]) +); + +endmodule + +module shim( + inout wire bit0, + inout wire bit1, + inout wire bit2 +); + +wire [2:0] value = {bit2, bit1, bit0}; + +initial begin + #1 $display(value); + if (value === 2) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"`timescale 1ns/1ps +module top; +`timescale 1us/1ns +endmodule +" +"module top; + integer in; + + initial begin + in = 2; + if ($clog2(in) != 1) $display(""FAILED""); + else $display(""PASSED""); + end +endmodule +" +"module top; + reg passed = 1\'b1; + reg [7:0] in; + + lwr dut(in); + + initial begin + #1 in = 8\'d1; + #1 in = 8\'d2; + + #1 if (passed) $display(""PASSED""); + end +endmodule + +module lwr(input [7:0] xin); + wire [7:0] x1 = {xin,{0{1\'b0}}}; + + always @(x1) if (x1 != $time) begin + $display(""Failed at time %2d, expected %2d, got %2d"", $time, $time, x1); + top.passed = 1\'b0; + end +endmodule +" +"package p; + + localparam a = 1, b = 2; + + typedef logic [b:a] vector_t; + +endpackage + +module a(); + + localparam a = 1, b = 4; + + import p::*; + + vector_t v; + + initial begin:blk + v = ~0; + $display(""%b"", v); + if (v === 2\'b11) + $display(""PASSED""); + else + $display(""FAILED""); + end + +endmodule +" +"module test; + reg [15:0] r; + integer i, i2; + real r1, r2; + initial begin +\ti = $mytest(r, i2, r1, r2); + +\tif (i !== 69 || r !== 11 || i2 !== 22 || r1 != 3.3 || r2 != 4.4) begin +\t $display(""i = %0d, r = %0d, i2 = %0d, r1 = %f, r2 = %f"", +\t\ti, r, i2, r1, r2); +\t $display(""FAILED""); +\tend else +\t $display(""PASSED""); + end +endmodule +" +"/* + * Modified to add ""endtask : "" syntax. This modification tests + * the SystemVerilog extension to the syntax. -- Stephen Williams + */ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: task_scope.v,v 1.1 2001/06/19 13:52:13 ka6s Exp $ +// $Log: task_scope.v,v $ +// Revision 1.1 2001/06/19 13:52:13 ka6s +// Added 4 tests from Stephan Boettcher +// + +// Test for task scope lookup in VVP + +module test; + + wire w; + + jobs j(w); + + task ini; + begin +\t j.set(1\'bz); + end + endtask : ini + + initial + begin +\tini; +\t#1; +\tj.set(1\'b1); +\t#1; +\tif (w===1) +\t $display(""PASSED""); +\telse +\t $display(""FAILED""); + end + +endmodule // test + +module jobs (out); + + output out; + reg\t out; + + task set; + input val; + begin +\t #1 out = val; + end + endtask : set + +endmodule // jobs +" +"module main; + + parameter CACHE_RAM = 128; + parameter ADR_WIDTH = 7; + + reg [31:0] buff[0:CACHE_RAM], data_o, data_i; + + reg [ADR_WIDTH-1:0] addr; + reg\t clk, rst, wr; + + (* ivl_synthesis_on *) + always @(posedge clk) + if (wr) buff[addr] <= data_i; + + (* ivl_synthesis_on *) + always @(posedge clk or posedge rst) + begin +\tif (rst) +\t data_o <= 32\'h0; +\telse if (wr) +\t data_o <= data_i; +\telse +\t data_o <= buff[addr]; + end + + (* ivl_synthesis_off *) + initial begin + clk = 0; + rst = 0; + wr = 1; + for (addr = 0 ; addr < 64 ; addr = addr+1) begin +\t data_i <= addr; +\t #1 clk = 1; +\t #1 clk = 0; +\t if (data_o !== data_i) begin +\t $display(""FAILED -- write addr=0x%h, data_o=%h"", addr, data_o); +\t $finish; +\t end + end + + wr = 0; + data_i = 32\'hx; + for (addr = 0 ; addr < 64 ; addr = addr+1) begin +\t #1 clk = 1; +\t #1 clk = 0; +\t if (data_o !== addr) begin +\t $display(""FAILED -- read addr=0x%h, data_o=%h"", addr, data_o); +\t $finish; +\t end + end + + $display(""PASSED""); + end + +endmodule // main +" +"module test(); + +struct packed { + logic [15:0] value; +} data; + +initial begin + data.value[7:0] = 8\'h55; + data.value[15:8] = 8\'haa; + if (data !== 16\'haa55) begin + $display(""FAILED -- data=%h"", data); + $finish; + end + $display(""PASSED""); +end + +endmodule +" +" +module main; + typedef struct packed { + logic [1:0] hig; + logic [1:0] low; + } word_as_nibbles; + + typedef union packed { + logic [3:0] bits; + word_as_nibbles words; + } bits_t; + + bits_t foo; + + initial begin + foo.bits = \'b1001; + if (foo.bits != \'b1001) begin +\t $display(""FAILED -- foo.bits=%b"", foo.bits); +\t $finish; + end + + if (foo.words != \'b1001) begin +\t $display(""FAILED -- foo.words=%b"", foo.words); +\t $finish; + end + + //foo.words.low = \'b00; + //foo.words.hig = \'b11; + foo.words = \'b1100; + if (foo.words != \'b1100) begin +\t $display(""FAILED -- foo.words=%b"", foo.words); +\t $finish; + end + if (foo.bits != \'b1100) begin +\t $display(""FAILED -- foo.bits=%b"", foo.bits); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"module top; + wire [3:0] array [1:0]; + integer sel; + + assign array[0] = 4\'h0; + assign array[1] = 4\'h1; + + initial begin + #1; + $display("" %h %h"", array[0], array[1]); + // This is only a problem for a wire (net array)! + sel = 0; + $display("" %h %h"", array[sel], array[sel+1]); + $display(""PASSED""); + end +endmodule +" +"module top; + // This should fail because XX5 is given an undefined constant (2-state). + enum {VAL5, XX5 = \'bx} en5; + + initial $display(""FAILED""); +endmodule +" +"module test; + initial begin +\t$display(""Error: \\""FloatTest.bsv\\"", line 234, column 24: (R0001)\ + Mutually exclusive rules (from the ME sets [RL_action_l234c24] and\ + [RL_action_l235c24, RL_action_l236c24, RL_action_l237c24, RL_action_l238c24,\ + RL_action_l239c24, RL_action_l240c24, RL_action_l241c24, RL_action_l242c24,\ + RL_action_l243c24, RL_action_l244c24, RL_action_l245c24, RL_action_l246c24,\ + RL_action_l247c24, RL_action_l248c24, RL_action_l249c24, RL_action_l250c24,\ + RL_action_l251c24, RL_action_l252c24, RL_action_l253c24, RL_action_l255c24,\ + RL_action_l256c24, RL_action_l257c24, RL_action_l258c24, RL_action_l259c24,\ + RL_action_l260c24, RL_action_l261c24, RL_action_l262c24, RL_action_l263c24,\ + RL_action_l264c24, RL_action_l265c24, RL_action_l266c24, RL_action_l267c24,\ + RL_action_l268c24, RL_action_l269c24, RL_action_l270c24, RL_action_l271c24,\ + RL_action_l272c24, RL_action_l273c24, RL_action_l274c24, RL_action_l276c24,\ + RL_action_l277c24, RL_action_l278c24, RL_action_l279c24, RL_action_l280c24,\ + RL_action_l281c24, RL_action_l282c24, RL_action_l283c24, RL_action_l284c24,\ + RL_action_l285c24, RL_action_l286c24, RL_action_l287c24, RL_action_l288c24,\ + RL_action_l289c24, RL_action_l290c24, RL_action_l291c24, RL_action_l292c24,\ + RL_action_l293c24, RL_action_l294c24, RL_action_l295c24, RL_action_l297c24,\ + RL_action_l298c24, RL_action_l299c24, RL_action_l300c24, RL_action_l301c24,\ + RL_action_l302c24, RL_action_l303c24, RL_action_l304c24, RL_action_l305c24,\ + RL_action_l306c24, RL_action_l307c24, RL_action_l308c24, RL_action_l309c24,\ + RL_action_l310c24, RL_action_l311c24, RL_action_l312c24, RL_action_l313c24,\ + RL_action_l314c24, RL_action_l315c24, RL_action_l316c24, RL_action_l318c24,\ + RL_action_l319c24, RL_action_l320c24, RL_action_l321c24, RL_action_l322c24,\ + RL_action_l323c24, RL_action_l324c24, RL_action_l326c24, RL_action_l327c24,\ + RL_action_l328c24, RL_action_l329c24, RL_action_l330c24, RL_action_l331c24,\ + RL_action_l332c24, RL_action_l333c24, RL_action_l334c24, RL_action_l335c24,\ + RL_action_l336c24, RL_action_l337c24, RL_action_l338c24, RL_action_l339c24,\ + RL_action_l340c24, RL_action_l341c24, RL_action_l342c24, RL_action_l343c24,\ + RL_action_l344c24, RL_action_l345c24, RL_action_l348c18, RL_action_l353c22,\ + RL_action_l354c22, RL_action_l355c22, RL_action_l356c22, RL_action_l357c22,\ + RL_action_l358c22, RL_action_l359c22, RL_action_l360c22, RL_action_l361c22,\ + RL_action_l362c22, RL_action_l363c22, RL_action_l364c22, RL_action_l365c22,\ + RL_action_l366c22, RL_action_l367c22, RL_action_l368c22, RL_action_l369c22,\ + RL_action_l370c22, RL_action_l371c22, RL_action_l372c22, RL_action_l374c22,\ + RL_action_l376c22, RL_action_l377c22, RL_action_l378c22, RL_action_l379c22,\ + RL_action_l381c22, RL_action_l383c22, RL_action_l384c22, RL_action_l386c22,\ + RL_action_l387c22, RL_action_l390c18, RL_action_l395c23, RL_action_l396c23,\ + RL_action_l398c23, RL_action_l399c23, RL_action_l400c23, RL_action_l401c23,\ + RL_action_l402c23, RL_action_l403c23, RL_action_l404c23, RL_action_l405c23,\ + RL_action_l406c23, RL_action_l407c23, RL_action_l408c23, RL_action_l409c23,\ + RL_action_l410c23, RL_action_l411c23, RL_action_l412c23, RL_action_l413c23,\ + RL_action_l414c23, RL_action_l415c23, RL_action_l416c23, RL_action_l417c23,\ + RL_action_l419c23, RL_action_l420c23, RL_action_l421c23, RL_action_l422c23,\ + RL_action_l423c23, RL_action_l424c23, RL_action_l425c23, RL_action_l426c23,\ + RL_action_l427c23, RL_action_l428c23, RL_action_l429c23, RL_action_l430c23,\ + RL_action_l431c23, RL_action_l432c23, RL_action_l433c23, RL_action_l434c23,\ + RL_action_l435c23, RL_action_l436c23, RL_action_l437c23, RL_action_l438c23,\ + RL_action_l441c18, RL_action_l446c28, RL_action_l447c28, RL_action_l448c28,\ + RL_action_l449c28, RL_action_l450c28, RL_action_l451c28, RL_action_l452c28,\ + RL_action_l453c28, RL_action_l455c28, RL_action_l456c28, RL_action_l457c28,\ + RL_action_l458c28, RL_action_l459c28, RL_action_l460c28, RL_action_l461c28,\ + RL_action_l462c28, RL_action_l463c28, RL_action_l464c28, RL_action_l465c28,\ + RL_action_l466c28, RL_action_l467c28, RL_action_l468c28, RL_action_l469c28,\ + RL_action_l470c28, RL_action_l471c28, RL_action_l472c28, RL_action_l473c28,\ + RL_action_l474c28, RL_action_l475c28, RL_action_l476c28, RL_action_l478c28,\ + RL_action_l479c28, RL_action_l481c28, RL_action_l484c18, RL_action_l489c21,\ + RL_action_l490c21, RL_action_l491c21, RL_action_l492c21, RL_action_l493c21,\ + RL_action_l494c21, RL_action_l495c21, RL_action_l496c21, RL_action_l497c21,\ + RL_action_l498c21, RL_action_l499c21, RL_action_l500c21, RL_action_l501c21,\ + RL_action_l502c21, RL_action_l503c21, RL_action_l504c21, RL_action_l505c21,\ + RL_action_l506c21, RL_action_l507c21, RL_action_l508c21, RL_action_l509c21,\ + RL_action_l510c21, RL_action_l512c21, RL_action_l513c21, RL_action_l514c21,\ + RL_action_l515c21, RL_action_l516c21, RL_action_l517c21, RL_action_l518c21,\ + RL_action_l519c21, RL_action_l520c21, RL_action_l521c21, RL_action_l522c21,\ + RL_action_l523c21, RL_action_l524c21, RL_action_l525c21, RL_action_l526c21,\ + RL_action_l527c21, RL_action_l528c21, RL_action_l529c21, RL_action_l530c21,\ + RL_action_l531c21, RL_action_l533c26, RL_action_l534c26, RL_action_l535c26,\ + RL_action_l536c26, RL_action_l537c26, RL_action_l538c26, RL_action_l539c26,\ + RL_action_l540c26, RL_action_l542c26, RL_action_l543c26, RL_action_l544c26,\ + RL_action_l545c26, RL_action_l546c26, RL_action_l547c26, RL_action_l548c26,\ + RL_action_l549c26, RL_action_l550c26, RL_action_l551c26, RL_action_l552c26,\ + RL_action_l553c26, RL_action_l554c26, RL_action_l555c26, RL_action_l556c26,\ + RL_action_l557c26, RL_action_l558c26, RL_action_l559c26, RL_action_l560c26,\ + RL_action_l561c26, RL_action_l562c26, RL_action_l563c26, RL_action_l565c26,\ + RL_action_l566c26, RL_action_l568c26, RL_action_l570c21, RL_action_l572c21,\ + RL_action_l574c26, RL_action_l576c26, RL_action_l577c26, RL_action_l579c26,\ + RL_action_l582c18, RL_action_l587c28, RL_action_l588c28, RL_action_l589c28,\ + RL_action_l590c28, RL_action_l591c28, RL_action_l592c28, RL_action_l593c28,\ + RL_action_l594c28, RL_action_l595c28, RL_action_l596c28, RL_action_l597c28,\ + RL_action_l598c28, RL_action_l599c28, RL_action_l600c28, RL_action_l601c28,\ + RL_action_l602c28, RL_action_l603c28, RL_action_l604c28, RL_action_l605c28,\ + RL_action_l606c28, RL_action_l607c28, RL_action_l609c28, RL_action_l610c28,\ + RL_action_l611c28, RL_action_l613c28, RL_action_l614c28, RL_action_l615c28,\ + RL_action_l616c28, RL_action_l617c28, RL_action_l618c28, RL_action_l619c28,\ + RL_action_l621c28, RL_action_l622c28, RL_action_l623c28, RL_action_l624c28,\ + RL_action_l625c28, RL_action_l626c28, RL_action_l627c28, RL_action_l628c28,\ + RL_action_l629c28, RL_action_l630c28, RL_action_l631c28, RL_action_l632c28,\ + RL_action_l633c28, RL_action_l634c28, RL_action_l635c28, RL_action_l636c28,\ + RL_action_l637c28, RL_action_l638c28, RL_action_l639c28, RL_action_l645c18,\ + RL_action_l647c7] ) fired in the same clock cycle.\ +PASSED""); + end +endmodule +" +"module top; + reg pass; + reg [7:0] in; + reg [1:0] res; + integer lp; + + initial begin + pass = 1\'b1; + in = 8\'b11100100; + lp = 3; + + // lp[1:0] is being sign extended and that fails when the value mod 4 + // is either 2 or 3! A bit/part select is always unsigned unless we use + // The $signed function to cast it to signed! + res = in[lp[1:0]*2 +: 2]; + if (res !== 2\'b11) begin + $display(""Failed expected 2\'b11, got %b (%b:%d)"", res, in, lp[1:0]*2); + pass = 1\'b0; + end + + // This should give -2 for the index. + res = in[$signed(lp[1:0])*2 +: 2]; + if (res !== 2\'bxx) begin + $display(""Failed expected 2\'bxx, got %b (%b:%d)"", res, in, + $signed(lp[1:0])*2); + pass = 1\'b0; + end + + lp = 6; + // The same as above, but not at the start of the signal. + res = in[lp[2:1]*2 +: 2]; + if (res !== 2\'b11) begin + $display(""Failed expected 2\'b11, got %b (%b:%d)"", res, in, lp[2:1]*2); + pass = 1\'b0; + end + res = in[$signed(lp[2:1])*2 +: 2]; + if (res !== 2\'bxx) begin + $display(""Failed expected 2\'bxx, got %b (%b:%d)"", res, in, + $signed(lp[2:1])*2); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"/* + * Copyright (c) 2000 Steve Wilson (stevew@home.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This checks bit select from/to vectors with odd bit arrangements. + */ +module test; + + reg [4:1] a; + reg [1:4] b; + integer i; + + initial begin + a = 4\'b1100; + for (i = 1 ; i <= 4 ; i = i + 1) +\tb[i] = a[i]; + + $display(""a=%b, b=%b"", a, b); + if (b !== 4\'b0011) begin +\t $display(""FAILED -- b == %b"", b); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule +" +"module sub(); + +task task1; + +input [1023:0] a; +input [1023:0] b; + +begin + if (a + b > 1026'd2) $display(1); +end + +endtask + +initial task1(1, 2); + +endmodule + +module top(); + +generate + genvar i; + + for (i = 0; i < 256; i = i + 1) begin:block + sub sub(); + end +endgenerate + +endmodule +" +"// This file extends the original bug test case to explore all the +// forms of a signed left shift that are treated as special cases. +module test; + reg pass; + reg [8*40:1] str; + integer s; + + initial begin + pass = 1\'b1; + s = 1; + + $sformat(str, ""%0d"", ((0 << 1) + 1) * -1); + if (str[8*2:1] !== ""-1"" || str[8*40:8*2+1] !== 0) begin + $display(""FAILED 1st test, expected \\""-1\\"", got %s"", str); + pass = 1\'b0; + end + + $sformat(str, ""%0d"", ((1 << 1) + 1) * -1); + if (str[8*2:1] !== ""-3"" || str[8*40:8*2+1] !== 0) begin + $display(""FAILED 2nd test, expected \\""-3\\"", got %s"", str); + pass = 1\'b0; + end + + $sformat(str, ""%0d"", ((1 << s) + 1) * -1); + if (str[8*2:1] !== ""-3"" || str[8*40:8*2+1] !== 0) begin + $display(""FAILED 3rd test, expected \\""-3\\"", got %s"", str); + pass = 1\'b0; + end + + $sformat(str, ""%0d"", ((s << 1) + 1) * -1); + if (str[8*2:1] !== ""-3"" || str[8*40:8*2+1] !== 0) begin + $display(""FAILED 4th test, expected \\""-3\\"", got %s"", str); + pass = 1\'b0; + end + + $sformat(str, ""%0d"", ((s << 0) + 1) * -1); + if (str[8*2:1] !== ""-2"" || str[8*40:8*2+1] !== 0) begin + $display(""FAILED 5th test, expected \\""-2\\"", got %s"", str); + pass = 1\'b0; + end + + $sformat(str, ""%0d"", ((s << 64) + 1\'sd1) * -1\'sd1); + if (str[8*2:1] !== ""-1"" || str[8*40:8*2+1] !== 0) begin + $display(""FAILED 6th test, expected \\""-1\\"", got %s"", str); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"// pr1831724 + +module test; + reg [15:0] tmp1, tmp2; + initial + begin +\ttmp1 = 9\'bxxx000000; +\ttmp2 = {9\'bxxx000000}; +\t$display(""tmp1: \'%b\'; tmp2: \'%b\'"", tmp1, tmp2); + end +endmodule +" +"`timescale 1 ns / 1 ns +module short(inout [7:0] p, input en); +\tassign p = en ? 8\'h55 : 8\'hzz; +endmodule + +module long(inout [15:0] p, input en); +\tassign p = en ? 16\'haaaa : 16\'hzzzz; +endmodule + +module main; +\twire [15:0] bus; +\treg l_en, s_en; +\tinteger fails=0; +\tlong l(.p(bus), .en(l_en)); +\tshort s(.p(bus[7:0]), .en(s_en)); +\tinitial begin +\t\t// $dumpfile(""tri.vcd""); +\t\t// $dumpvars(3,main); +\t\tl_en = 0; +\t\ts_en = 0; +\t\t#10; +\t\tl_en = 1; +\t\t#10; +\t\t$display(""s.p = %4x"", s.p); +\t\tif (s.p !== 8\'haa) fails=1; +\t\t#10; +\t\tl_en = 0; +\t\ts_en = 1; +\t\t#10; +\t\t$display(""l.p = %4x"", l.p); +\t\tif (l.p !== 16\'hzz55) fails=2; +\t\t#10; +\t\ts_en = 0; +\t\t#10; +\t\tif (fails == 0) $display(""PASSED""); +\t\telse $display(""FAILED "",fails); +\tend +endmodule +" +"/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module test(); + + reg [7:0] test; + wire [7:0] neg_test = -test; + + initial begin + for (test = 0 ; test < 255 ; test = test + 1) begin +\t #1 if (neg_test !== (-test)) begin +\t $display(""FAILED -- %b !== -%b"", neg_test, test); +\t $finish; +\t end + end + + $display(""PASSED""); + end + +endmodule +" +"parameter num1 = 201, str1 = ""unit2""; +parameter num2 = 202, str2 = ""unit2""; +parameter num3 = 203, str3 = ""unit2""; + +module m3(); + + parameter num2 = 232, str2 = ""m3""; + + initial begin + #2; // allow m1 to go first + m2.m1inst.obj.display; + $display(""%d from %s"", num1, str1); + $display(""%d from %s"", num2, str2); + $display(""%d from %s"", num3, str3); + $display(""%d from %s"", m4.num4, m4.str4); + end + +/* This should not change the result, but Icarus ignores the order in + which variables are declared and used. + parameter num = 113, str3 = ""m3""; +*/ + +endmodule + + +module m4(); + + parameter num1 = 241, str1 = ""m4""; + parameter num2 = 242, str2 = ""m4""; + parameter num3 = 243, str3 = ""m4""; + parameter num4 = 244, str4 = ""m4""; + + m3 m3inst(); + +endmodule +" +"module forBug(); + integer i; + integer j; + + initial + begin +\t// This loop sets i=4 .. -1 which is an error +\tfor (i=4; i>-1; i=i-1) +\t $display(""i=%d"",i); + +\t// This loop sets j=4 .. 0 which is correct. +\tfor (j=4; j>=0; j=j-1) +\t $display(""j=%d"",j); + end +endmodule // forBug +" +"/* + * This test is based on PR#913 in the test suite. The + * idea is to wait for the start integer to become true. + */ +module test(); + integer start; + + initial + #900000 begin $display(""FAILED""); $stop; end + + initial + #100000 start = 1; + + initial + begin +\twait (start) $display(""PASSED""); +\t$finish; + end +endmodule // test +" +"/* + * Copyright (c) 1998-2000 Andrei Purdea (andrei@purdea.ro) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// The below test is expected to fail with a combilation error. +module main; + function void bla(); + return 10; + endfunction +endmodule +" +"module top; + initial begin + // This will fail at run time. + $fdisplay(32\'h8000_000f, ""write to invalid FD""); + end +endmodule +" +"module top; + reg pass; + reg [7:0] a, b; + wire [15:0] ruu, rsu, rus, rss; + reg signed [15:0] res; + integer i; + + assign ruu = a % b; + assign rsu = $signed(a) % b; + assign rus = a % $signed(b); + assign rss = $signed(a) % $signed(b); + + initial begin + pass = 1\'b1; + + // Run 1000 random vectors + for (i = 0; i < 1000; i = i + 1) begin + // Random vectors + a = $random; + b = $random; + #1; + + // Check unsigned % unsigned. + if (ruu !== a%b) begin + $display(""FAILED: u%%u (%b%%%b) gave %b, expected %b"", a, b, ruu, a%b); + pass = 1\'b0; + end + // Check signed % unsigned division. + if (rsu !== a%b) begin + $display(""FAILED: s%%u (%b%%%b) gave %b, expected %b"", a, b, rsu, a%b); + pass = 1\'b0; + end + // Check unsigned % signed division. + if (rus !== a%b) begin + $display(""FAILED: u%%s (%b%%%b) gave %b, expected %b"", a, b, rus, a%b); + pass = 1\'b0; + end + // Check signed % signed division. + res = $signed(a)%$signed(b); + if (rss !== res) begin + $display(""FAILED: s%%s (%b%%%b) gave %b, expected %b"", a, b, rss, res); + pass = 1\'b0; + end + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module check (input unsigned [22:0] a, b, c); + wire [22:0] int_AB; + + assign int_AB = a & b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB != c) begin + $display(""ERROR""); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [22:0] A, B); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; B= 0; + for (i=0; i 4) $display(""FAILED""); else $display(""PASSED""); + end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate release statement +// +// D: This code verifies the release statement. +// D: It depends on the force statement being +// D: functional! (Kinda have to - no way to +// D: release if you haven\'t forced the issue. +// D: It is intended to be self checking. +// +// By: Steve Wilson +// + +module main (); + +reg working; +reg timer; + +initial + working = 1; + +initial + begin + #5 ; + force working = 0; + end + +initial + begin + #10; + release working;\t// This releases the force + #2 ; + working = 1;\t// This allows a new value onto the reg. + end + +initial + begin + #20; + if(!working) + $display(""FAILED\ +""); + else + $display(""PASSED\ +""); + end + +endmodule +" +"// Check that a SystemVerilog do/while loop works correctly. +module top; + int i; + + initial begin + i = 0; + do begin + i += 1; + $display(""The value of i is %0d"", i); + end while (i < 2); + $display(""PASSED""); + end +endmodule +" +"module main; + + reg [2:0] Q; + reg\t clk, clr, up, down; + reg\t flag; + + (*ivl_synthesis_off *) + initial begin + clk = 0; + up = 0; + down = 0; + clr = 1; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin +\t $display(""FAILED""); +\t $finish; + end + if (flag !== 0) begin +\t $display(""FAILED""); +\t $finish; + end + + up = 1; + clr = 0; + + #1 clk = 1; + #1 clk = 0; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 3\'b010) begin +\t $display(""FAILED""); +\t $finish; + end + if (flag !== 0) begin +\t $display(""FAILED""); +\t $finish; + end + + up = 0; + down = 1; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 3\'b001) begin +\t $display(""FAILED""); +\t $finish; + end + if (flag !== 0) begin +\t $display(""FAILED""); +\t $finish; + end + + down = 0; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 3\'b001) begin +\t $display(""FAILED""); +\t $finish; + end + + if (flag !== 1) begin +\t $display(""FAILED""); +\t $finish; + end + + $display(""PASSED""); + $finish; + end + + /* + * This statement models a snythesizable UP/DOWN counter. The up + * and down cases are enabled by up and down signals. If both + * signals are absent, the synthesizer should take the implicit + * case that Q <= Q; + */ + (* ivl_synthesis_on *) + always @(posedge clk, posedge clr) + if (clr) begin +\tQ <= 0; +\tflag <= 0; + end else begin +\tif (up) +\t Q <= Q + 1; +\telse if (down) +\t Q <= Q - 1; +\telse +\t flag <= 1; + end + +endmodule // main +" +"/* + * Check that errors are caught. + */ + +timeunit 100us; +timeprecision 1us; + +// Repeated declarations must match the initial declarations. +timeunit 1ms; +timeprecision 1ns; + +// A local time unit is OK, but a repeat must match. +module check_tu_d_e; + timeunit 10us; + timeunit 1us; +endmodule + +// A local time precision is OK, but a repeat must match. +module check_tp_d_e; + timeprecision 10us; + timeprecision 1us; +endmodule + +// A repeat time unit is only allowed if an initial one is given. +module check_tu_m_e; + integer foo; + timeunit 10us; +endmodule + +// A repeat time precision is only allowed if an initial one is given. +module check_tp_m_e; + integer foo; + timeprecision 10us; +endmodule + +// A local time unit is OK and a repeat is OK, but this is not a prec decl. +module check_tup_d_e; + timeunit 10us; + timeunit 10us; + timeprecision 1us; +endmodule + +// A local time prec is OK and a repeat is OK, but this is not a unit decl. +module check_tpu_d_e; + timeprecision 1us; + timeprecision 1us; + timeunit 10us; +endmodule + +/* Check some invalid values */ + +// Only a power of 10 is allowed. +timeunit 200s; +timeprecision 200s; +// Too many zeros (only allow 0 - 2). +timeunit 1000s; +timeprecision 1000s; +// This actually trips as an invalid scale of '2s'. +timeunit 12s; +timeprecision 12s; +// This needs to be checked. The base time_literal supports this, but +// for now timeunit/precision code does not. +timeunit 1_0s; +timeprecision 1_0s; +" +" +module main; + + typedef enum { RED, ORANGE, YELLOW, GREEN, BLUE, VIOLET } rainbow_t; + rainbow_t color; + string\ttmp; + + initial begin + color = color.first(); + tmp = color.name(); + $display(""first color is %s (%0d)"", tmp, color); + if (color.name() != ""RED"") begin +\t $display(""FAILED -- color.name() != RED""); +\t $finish; + end + if (color.first() != RED) begin +\t $display(""FAILED -- color.first() != RED""); +\t $finish; + end + + while (color != color.last()) begin +\t color = color.next(); +\t $display(""Next color is %s (%0d)"", color.name(), color); + end + + $display(""Last color is %s (%0d)."", color.name(), color); + if (color.name() != ""VIOLET"") begin +\t $display(""FAILED -- color.name() != VIOLET""); +\t $finish; + end + if (color.last() != VIOLET) begin +\t $display(""FAILED -- color.last() != VIOLET""); +\t $finish; + end + + $display(""PASSED""); + $finish(0); + end + +endmodule // main +" +"`timescale 100 ps / 10 ps + +(* ivl_synthesis_cell *) +module LD (Q, D, G); + + output Q; + reg\t q_out; + + input D, G; + + buf b1 (Q, q_out); + + always @(D or G) if (G) q_out <= D; + +endmodule +" +"module tb(); + +typedef enum logic [1:0] { + IDLE = 0, + RESET = 1, + START = 2, + WAITFOR = 3 +} stateType; + +stateType state; + +string workingString = ""WORKING""; + +initial begin + $display(""DIRECT ASSIGNED STRING is "", workingString); + #10; + state = IDLE; +end + +string state_txt; + +always @* begin + case(state) + IDLE : state_txt = ""IDLE""; + RESET : state_txt = ""RST""; + START : state_txt = ""STRT""; + WAITFOR : state_txt = ""WAIT""; + endcase + $display(""Controller\'s new state is %s"",state_txt); +end + +endmodule +" +"// Taken from GitHub issue 11 : Syntax error on operator attributes. + +module test(input [3:0] a, b, output [3:0] y1, y2, y3); + +assign y1 = - (* foo = ""bar"" *) a; +assign y2 = a + (* foobar = 42 *) b; +assign y3 = a == b ? (* foobar *) y1 : y2; + +endmodule +" +"module top; + wire [63:0] vo; + + rcvr U1(vo); + drvr U2(vo); +endmodule + +module rcvr(input wire [63:0] vo); + + always @(vo) + $display(""Real value is %f at %g"", $bitstoreal(vo), $time); +endmodule + +module drvr(output wire [63:0] vo); + real vint; + + assign vo = $realtobits(vint); + + initial begin + vint = 3.3; + #1000 vint = 4.5776; + #1000 vint = -4; + end +endmodule +" +"// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test while loops in VHDL. + +module vhdl_while_test; +logic start; +int out; +vhdl_while dut(start, out); + +initial begin + start = 1; + #1; + + if(out !== 10) begin + $display(""FAILED""); + $finish(); + end + + $display(""PASSED""); +end +endmodule + +" +"module test(); + +wire [7:0] value1; +reg [7:0] value2; + +reg en; + +assign value1[3:0] = 4\'b1010; + +always @* begin + if (en) + value2 <= value1; +end + +(* ivl_synthesis_off *) +initial begin + #1 en = 0; + #1 en = 1; + #1 en = 0; + $display(""%b %b"", value1, value2); + if (value2 === 8\'bzzzz1010) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +" +typedef union packed { + logic [3:0] bits; + struct packed { logic [1:0] hig; logic [1:0] low; } words; +} bits_t; + +module main; + + bits_t foo; + + initial begin + + if ($bits(foo) !== 4) begin +\t $display(""FAILED -- $bits(foo)=%0d"", $bits(foo)); +\t $finish; + end + + if ($bits(bits_t) !== 4) begin +\t $display(""FAILED -- $bits(bits_t)=%0d"", $bits(bits_t)); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program is designed to test non-constant bit selects in the + * concatenated l-value of procedural assignment. + */ +module main; + + reg [3:0] vec; + reg\t a; + integer i; + + initial begin + vec = 4\'b0000; + a = 0; + + if (vec !== 4\'b0000) begin +\t $display(""FAILED -- initialized vec to %b"", vec); +\t $finish; + end + + for (i = 0 ; i < 4 ; i = i + 1) begin +\t #1 { a, vec[i] } <= 2\'b11; + end + + #1 if (vec !== 4\'b1111) begin +\t $display(""FAILED == vec (%b) is not 1111"", vec); +\t $finish; + end + + if (a !== 1\'b1) begin +\t $display(""FAILED -- a (%b) is not 1"", a); +\t $finish; + end + + $display(""PASSED""); + end // initial begin +endmodule // main +" +"// Copyright (c) 2001 Stephen Williams (steve@icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + + +/* + * This module implements what essentially amounts to an array of DFF + * devices with output enable. This test checks the operation of the + * pmos and nmos devices. + */ +module grayGap (ad, clk, read, write); + + output [31:0] ad; + input\t clk, read, write; + + reg [15:0] regff; + + rpmos ad_drv [31:0] (ad, {16\'b0, regff}, read); + + always @(posedge clk) + if (write) regff = ad[15:0]; + + +endmodule + + +module main; + + wire [31:0] ad; + reg\t clk, read, write; + + reg [31:0] ad_val; + reg ad_en; + + rnmos ad_drv[31:0] (ad, ad_val, ad_en); + + grayGap test (ad, clk, read, write); + + always #10 clk = ~clk; + + initial begin + clk = 1; + read = 1; + write = 0; + $monitor($time, ""ad=%b"", ad); + + // Set up to write a value into the grayGap register. + @(negedge clk) +\tad_val = 32\'haaaa_aaaa; + read = 1; + write = 1; + ad_en = 1; + + // The posedge has passed, now set up to read that value + // out. Turn all the drivers off for a moment, to see that the + // line becomes tri-state... + @(negedge clk) +\tad_en = 0; + write = 0; + + // Now read the value. + #1 read = 0; + + #1 $display(""Wrote %h, got %h"", ad_val, ad); + + if (ad !== 32\'b0000_0000_0000_0000_1010_1010_1010_1010) begin +\t $display(""FAILED -- ad is %b"", ad); +\t $finish; + end + + #2 read = 1; + + $display(""PASSED""); + $finish; + end + +endmodule // main +" +"module bug04_integerDiv; + +reg passed; + +reg signed[31:0] reg0; +reg signed[31:0] reg1; +reg signed[31:0] rquot; +wire signed[31:0] dividend=reg0; +wire signed[31:0] divisor=reg1; +wire signed[31:0] quotient; + +assign quotient= dividend/divisor; + +initial begin +\tpassed = 1\'b1; +\treg0=32\'h76c3625e; +\treg1=32\'hffffffff; +\t//BUG here: quotient==32\'hxxxxxxxx, should be 32\'h893c9da2 +\t#1 if (quotient !== 32\'h893c9da2) begin +\t\t$display(""Failed: CA division, expected 32\'h893c9da2, got %h"", +\t\t quotient); +\t\tpassed = 1\'b0; +\tend + +\trquot = reg0/reg1; +\tif (rquot !== 32\'h893c9da2) begin +\t\t$display(""Failed: division, expected 32\'h893c9da2, got %h"", +\t\t rquot); +\t\tpassed = 1\'b0; +\tend + +\tif (passed) $display(""PASSED""); +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always repeat (expression) statement ; + +module main ; + +reg [3:0] value1,value2,value3; + +initial +\tbegin + value1 = 0;\t\t// Time 0 assignemnt + value2 = 0; + #6 ; + if(value1 != 4\'h1) + begin + $display(""FAILED - 3.1.7B always forever (1) ""); + value2 = 1; + end + #5 ; + if(value1 != 4\'h2) + begin + $display(""FAILED - 3.1.7B always forever (2) ""); + value2 = 1; + end + #5 ; + if(value1 != 4\'h3) + begin + $display(""FAILED - 3.1.7B always forever (3) ""); + value2 = 1; + end + if(value2 == 0) + $display(""PASSED""); +\t $finish; + end + +always repeat(3) begin + #5 ; + value1 = value1 + 1; + end + + +endmodule +" +"// +// Copyright (c) 2000 Steve Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// force3.17A - Template 1 - force reg_lvalue = constant. +// + +module test ; + +reg [3:0] val1; +reg [3:0] val2; + +initial + begin + val2 = 0; + #50 ; + if(val2 !== 4\'b1010) + $display(""FAILED""); + else + $display(""PASSED""); + end + +initial + begin + #20; + force val2 = 4\'b1010; + end +endmodule +" +"// Check a local timeprecision that is too large. +`resetall +module ltp_large; + timeunit 1ns/10ns; +endmodule +" +"/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * test the signedness of wires. + */ +module main; + + reg signed [7:0] val_rs = -5; + wire [7:0] val_w = val_rs + 1; + wire signed [7:0] val_ws = val_rs + 1; + + initial begin + #1 /* Let assignments settle. */ +\t$display(""val_w=%d, val_ws=%d"", val_w, val_ws); + + if (val_w !== 8\'d252) begin +\t $display(""FAILED -- val_w is wrong: %b"", val_w); +\t $finish; + end + + if (val_ws !== -8\'sd4) begin +\t $display(""FAILED == val_ws is wrong: %b"", val_ws); +\t $finish; + end + + if (val_ws > 0) begin +\t $display(""FAILED -- signed test of val_ws failed""); +\t $finish; + end + + if (val_w < 0) begin +\t $display(""FAILED -- signed test of val_w failed""); +\t $finish; + end + + $display(""PASSED""); + end +endmodule // main +" +"module top; + + // A join_any will always take the shortest path + always fork + #2; + #1; + join_none + + initial begin + $display(""FAILED""); + #1; + $finish; + end + +endmodule +" +"module stimulus (output reg A, B); + + initial begin + // both inputs are x + #0 {A, B} = 2\'bxx; + // both inputs are z + #10 {A, B} = 2\'bzz; + // one input is a zero + #10 {A, B} = 2\'b0x; + #10 {A, B} = 2\'bx0; + #10 {A, B} = 2\'b0z; + #10 {A, B} = 2\'bz0; + // one input is a one + #10 {A, B} = 2\'b1x; + #10 {A, B} = 2\'bx1; + #10 {A, B} = 2\'b1z; + #10 {A, B} = 2\'bz1; + // one input x, other z + #10 {A, B} = 2\'bxz; + #10 {A, B} = 2\'bzx; + // normal bit operands + #10 {A, B} = 2\'b00; + #10 {A, B} = 2\'b01; + #10 {A, B} = 2\'b10; + #10 {A, B} = 2\'b11; + end + +endmodule + +module scoreboard (input Y, A, B); + +function truth_table (input a, b); + reg [1:0] gate_operand; + reg gate_output; + begin + gate_operand[1:0] = {a, b}; + case (gate_operand) + // both inputs are x + 2\'bxx: gate_output = 1\'bx; + // both inputs are z + 2\'bzz: gate_output = 1\'bx; + // output should be zero (one input is a one) + 2\'b1x: gate_output = 0; + 2\'bx1: gate_output = 0; + 2\'b1z: gate_output = 0; + 2\'bz1: gate_output = 0; + // output is x (one input is a zero) + 2\'b0x: gate_output = 1\'bx; + 2\'bx0: gate_output = 1\'bx; + 2\'b0z: gate_output = 1\'bx; + 2\'bz0: gate_output = 1\'bx; + // inputs x, z + 2\'bxz: gate_output = 1\'bx; + 2\'bzx: gate_output = 1\'bx; + // normal operation on bit + 2\'b00: gate_output = 1; + 2\'b01: gate_output = 0; + 2\'b10: gate_output = 0; + 2\'b11: gate_output = 0; + endcase + + truth_table = gate_output; + end +endfunction + + +reg Y_t; + +always @(A or B) begin + Y_t = truth_table (A, B); + #1; + //$display (""a = %b, b = %b, Y_s = %b, Y = %b"", A, B, Y_s, Y); + if (Y_t !== Y) begin + $display(""FAILED! - mismatch found for inputs %b and %b in NOR operation"", A, B); + $finish; + end +end + +endmodule + +module test; + stimulus stim (A, B); + nor_gate duv (.a_i(A), .b_i(B), .c_o(Y) ); + scoreboard mon (Y, A, B); + + initial begin + #200; + $display(""PASSED""); + $finish; + end + +endmodule +" +"module top; + reg [1:0] a, b, c, d, e; + reg passed; + + initial begin + a = 2\'b00; + b = 2\'b00; + c = 2\'b00; + d = 2\'b00; + e = 2\'b00; + passed =1\'b1; + #2; + // Check that only the first process has run so far. + if (a !== 2\'b01) begin + $display(""First process in named fork has not run: %b"", a); + passed = 1\'b0; + end + if (b !== 2\'b01) begin + $display(""First process in named block has not run: %b"", b); + passed = 1\'b0; + end + if (c !== 2\'b01) begin + $display(""First process in parent ending has not run: %b"", c); + passed = 1\'b0; + end + if (d !== 2\'b01) begin + $display(""First process in parent alive has not run: %b"", d); + passed = 1\'b0; + end + if (e !== 2\'b01) begin + $display(""First process in parent ending (disable) has not run: %b"", e); + passed = 1\'b0; + end + // This external lexical disable should disable the second process even + // though the parent has already ended. + disable top.be_name; + #2; + // Check that the second process only runs for the parent ending + // and alive cases. + if (a !== 2\'b01) begin + $display(""Second process in named fork ran: %b"", a); + passed = 1\'b0; + end + if (b !== 2\'b01) begin + $display(""Second process in named block ran: %b"", b); + passed = 1\'b0; + end + if (c !== 2\'b11) begin + $display(""Second process in parent ending has not run: %b"", c); + passed = 1\'b0; + end + if (d !== 2\'b11) begin + $display(""Second process in parent alive has not run: %b"", d); + passed = 1\'b0; + end + if (e !== 2\'b01) begin + $display(""Second process in parent ending (disable) ran: %b"", e); + passed = 1\'b0; + end + + if (passed) $display(""PASSED""); + end + + // Verify that disabling a named fork kills any detached processes. + initial begin + fork: fa_name + #1 a[0] = 1\'b1; + #3 a[1] = 1\'b1; + join_any + disable fa_name; + end + + // Verify that disabling a named block kills any detached processes. + initial begin: bb_name + fork + #1 b[0] = 1\'b1; + #3 b[1] = 1\'b1; + join_any + disable bb_name; + end + + // Verify that a detached process survives the parent ending. + initial begin + fork + #1 c[0] = 1\'b1; + #3 c[1] = 1\'b1; + join_any + end + + // Verify that a detached process runs if the parent is still alive. + initial begin + fork + #1 d[0] = 1\'b1; + #3 d[1] = 1\'b1; + join_any + #4; + end + + // Verify that a detached process survives the parent ending, but can + // still be disabled lexically by disabling the block that started it. + initial begin: be_name + fork + #1 e[0] = 1\'b1; + #3 e[1] = 1\'b1; + join_any + end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue <= @ event_identifier constant +// D: There is a dependency here between this and event keyword and -> + +module main ; + +reg [3:0] value1 ; +event event_ident ; + +initial +begin + # 5 -> event_ident ; +end + +initial + begin + if(value1 !== 4\'bxxxx) +\t$display(""FAILED - always reg_lvalue <= @ event_identifier constant\ +""); + #10 ; + if(value1 != 4\'h5) +\t$display(""FAILED - always reg_lvalue <= @ event_identifier constant\ +""); + else + begin + $display(""PASSED\ +""); + $finish ; + end + end + +always value1 <= @ event_ident 4\'h5; + + +endmodule +" +"module octal(); + +reg [5:0] var1; +reg [4:0] var2; + +initial begin + var1 = 6\'o00; $displayo($signed(var1)); + var1 = 6\'o01; $displayo($signed(var1)); + var1 = 6\'o02; $displayo($signed(var1)); + var1 = 6\'o03; $displayo($signed(var1)); + var1 = 6\'o04; $displayo($signed(var1)); + var1 = 6\'o05; $displayo($signed(var1)); + var1 = 6\'o06; $displayo($signed(var1)); + var1 = 6\'o07; $displayo($signed(var1)); + var1 = 6\'o10; $displayo($signed(var1)); + var1 = 6\'o20; $displayo($signed(var1)); + var1 = 6\'o30; $displayo($signed(var1)); + var1 = 6\'o40; $displayo($signed(var1)); + var1 = 6\'o50; $displayo($signed(var1)); + var1 = 6\'o60; $displayo($signed(var1)); + var1 = 6\'o70; $displayo($signed(var1)); + var1 = 6\'o17; $displayo($signed(var1)); + var1 = 6\'o26; $displayo($signed(var1)); + var1 = 6\'o35; $displayo($signed(var1)); + var1 = 6\'o44; $displayo($signed(var1)); + var1 = 6\'o53; $displayo($signed(var1)); + var1 = 6\'o62; $displayo($signed(var1)); + var1 = 6\'o71; $displayo($signed(var1)); + $display(""""); + var2 = 6\'o00; $displayo($signed(var2)); + var2 = 6\'o01; $displayo($signed(var2)); + var2 = 6\'o02; $displayo($signed(var2)); + var2 = 6\'o03; $displayo($signed(var2)); + var2 = 6\'o04; $displayo($signed(var2)); + var2 = 6\'o05; $displayo($signed(var2)); + var2 = 6\'o06; $displayo($signed(var2)); + var2 = 6\'o07; $displayo($signed(var2)); + var2 = 6\'o10; $displayo($signed(var2)); + var2 = 6\'o20; $displayo($signed(var2)); + var2 = 6\'o30; $displayo($signed(var2)); + var2 = 6\'o17; $displayo($signed(var2)); + var2 = 6\'o26; $displayo($signed(var2)); + var2 = 6\'o35; $displayo($signed(var2)); +end + +endmodule +" +"// Copyright 2008, Martin Whitaker +// This file may be freely copied for any purpose + +module shift(); + +reg [5:0] S; +wire [63:0] Y; + +assign Y = 1 << S; + +initial begin + S = 32; + #1 $display(""1 << %0d = %b"", S, Y); +end + +endmodule +" +"module bug; + + reg [31:0] a; + integer i; + + initial + begin +\ti=4; +\ta=0; +\ta[i*4+:2] = 2\'b11; + +\t$display(""%h"",a); +\tif (a !== 32\'h00030000) begin +\t $display(""FAILED""); +\t $finish; +\tend + +\t$display(""PASSED""); + end +endmodule +" +"module top; + initial begin : named_begin + $display(""PASSED""); + end : named_begin +endmodule +" +"module top; + reg pass = 1\'b1; + + generate + genvar n; + for (n=0; n<4; n=n+1) begin : loop + reg [2:0] r = n; // This fails. +// wire [2:0] r = n; // This works. + end + endgenerate + + initial begin + #1; + + if (loop[0].r !== 0) begin + $display(""Failed generate instance 0""); + pass = 1\'b0; + end + + if (loop[1].r !== 1) begin + $display(""Failed generate instance 1""); + pass = 1\'b0; + end + + if (loop[2].r !== 2) begin + $display(""Failed generate instance 2""); + pass = 1\'b0; + end + + if (loop[3].r !== 3) begin + $display(""Failed generate instance 3""); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"`begin_keywords ""1364-2005"" +module top; + reg [20*8-1:0] var; + integer fp, code; + initial begin + fp = $fopenr(""read""); + if (fp != 0) $display(""Read of empty file failed.""); + + fp = $fopenw(""work/test.txt""); + $fdisplay(fp, ""From the write.""); + $fclose(fp); + + fp = $fopena(""work/test.txt""); + $fdisplay(fp, ""From the append.""); + $fclose(fp); + + fp = $fopenr(""work/test.txt""); + code = $fgets(var, fp); + $display(""%0s"", var[20*8-1:8]); + code = $fgets(var, fp); + $display(""%0s"", var[20*8-1:8]); + $fclose(fp); + end +endmodule +`end_keywords +" +"// Copyright (c) 2015 CERN +// @author Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for port inout mode. + +module vhdl_inout_test; +logic a, b, c; +vhdl_inout dut(a, b, c); + +initial begin + b <= 1\'b0; + #1; + if(a !== 1\'b1 || c !== 1\'b0) begin + $display(""FAILED 1""); + $finish(); + end + + b <= 1\'b1; + #1; + if(a !== 1\'b0 || c !== 1\'b1) begin + $display(""FAILED 2""); + $finish(); + end + + $display(""PASSED""); +end +endmodule +" +"module main; + + reg [3:0] value; + reg [2:0] addr; + + wire test_bit = value[addr] == 1; + + initial begin + value = \'b0110; + + for (addr = 0 ; addr < 4 ; addr = addr+1) begin +\t #1 if (test_bit !== value[addr]) begin +\t $display(""FAILED -- value[%d]=%b, test_bit=%b"", +\t\t addr, value[addr], test_bit); +\t $finish; +\t end + end + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"module main; + wire [1:0] a2, b2; + wire [2:0] a3, b3; + + target #(.WA(2), .WB(2)) u1 (a2, b2); + target #(.WA(3), .WB(3)) u2 (a3, b3); + + initial begin + $display(""u1.WA=%d, $bits(u1.A)=%d"", u1.WA, $bits(u1.A)); + $display(""u1.WB=%d, $bits(u1.A)=%d"", u1.WB, $bits(u1.B)); + + if ($bits(u1.A) != 2) begin +\t $display(""FAILED -- $bits(u1.A) = %d"", $bits(u1.A)); +\t $finish; + end + + if ($bits(u2.A) != 3) begin +\t $display(""FAILED -- $bits(u2.A) = %d"", $bits(u2.A)); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main + +module target + #(parameter WA = 4, WB = 4) + (input [WA-1:0] A, output [WB-1:0] B); + + assign B = A; + +endmodule // target +" +"// We want to print a warning if we find a delay that comes from the +// default timescale (1s) and then one from a given timescale. +// Basically we want to have either the case of no timescales or +// timescales for all delays. +module wo_time(out, in); + output out; + input in; + + buf(out, in); + + specify + (in => out) = 1; + endspecify +endmodule + +module top; + reg in; + wire out_wo, out_w; + + wo_time wo(out_wo, in); + w_time w(out_w, in); + + initial begin + in = 1\'b1; + #2 $finish(0); + end + + always @(out_wo) $display(""The time in wo_time is: %e"", $abstime); + always @(out_w) $display(""The time in w_time is: %e"", $abstime); +endmodule + +`timescale 1ns/1ns +module w_time(out, in); + output out; + input in; + + buf(out, in); + + specify + (in => out) = 1; + endspecify +endmodule +" +"module top; + reg [1:0] q; + wire [4:0] icim[1:0]; + integer j; + + always @(q) begin + /* + * The following line had the muli problem, the other line has a + * different problem. + */ + icim[0] <= #1 0 + 8 * (0 >> q); + icim[1] <= #1 1 + 8 * (1 >> q); + end + + initial begin + q = 2\'d1; + #2; + if (icim[0] !== 0) begin +\t $display(""FAILED""); +\t $finish; + end + if (icim[1] !== 1) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""PASSED""); + end + +endmodule +" +" +program main; + + function real sum_array(real array[]); + int idx; + sum_array = 0.0; + for (idx = 0 ; idx < array.size() ; idx = idx+1) +\tsum_array = sum_array + array[idx]; + endfunction // sum_array + + real obj[]; + real foo; + initial begin + foo = sum_array(\'{}); + if (foo != 0.0) begin +\t $display(""FAILED -- sum of empty array returns %0d"", foo); +\t $finish; + end + + obj = new[3]; + obj = \'{1,2,3}; + foo = sum_array(obj); + if (foo != 6.0) begin +\t $display(""FAILED -- sum of \'{%f,%f,%f} is %0d"", obj[0], obj[1], obj[2], foo); +\t $finish; + end + + obj = new[3] (\'{4,5,6}); + foo = sum_array(obj); + if (foo != 15.0) begin +\t $display(""FAILED -- sum of \'{4,5,6} is %0d"", foo); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endprogram // main +" +"// This tests system functions available for packed structures +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test; + + typedef struct packed { + logic [7:0] high; + logic [7:0] low; + } word_t; + + // Declare word0 as a VARIABLE + word_t word0; + + // error counter + bit err = 0; + + initial begin + if ($bits(word0 ) !== 16) begin $display(""FAILED -- $bits(word0 ) = %d"", $bits(word0 )); err=1; end + if ($bits(word0.high) !== 8) begin $display(""FAILED -- $bits(word0.high) = %d"", $bits(word0.high)); err=1; end + if ($bits(word0.low ) !== 8) begin $display(""FAILED -- $bits(word0.low ) = %d"", $bits(word0.low )); err=1; end + + if (!err) $display(""PASSED""); + end + +endmodule // test +" +"module bug(); + +reg d; +reg [31:0] x; +reg [31:0] y; +reg [31:0] z; + +initial begin + d = 1; + x = 32\'hffffffff << {d, 64\'d0}; + y = 32\'hffffffff >> {d, 64\'d0}; + z = 32\'hffffffff >>> {d, 64\'d0}; + $display(""%h"", x); + $display(""%h"", y); + $display(""%h"", z); + if (x === 32\'d0 && y === 32\'d0 && z === 32\'d0) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"/* + * Author: Oswaldo Cadenas + * + * The test checks the module reg ouput type accepts default + * initialization value. If no default value is given to reg output + * type then this test fails. + */ + +module clkgen(output reg clk = 0); + +initial begin + #100; + disable checking; + disable gen; + $display (""PASSED""); + $finish; +end + +initial begin + fork + gen; + checking; + join +end + +task gen; + forever #10 clk = ~clk; +endtask + +task checking; + forever begin + #1; + if (clk === 1\'bx ) begin + $display (""FAILED!""); +\t $finish; + end + end +endtask + +endmodule +" +"module mux( + +input wire [1:0] sel, +input wire [2:0] i0, +input wire [2:0] i1, +input wire [2:0] i2, +input wire [2:0] i3, +input wire [2:0] i4, +output reg [2:0] o + +); + +always @* begin + case (sel) + 0 : o = i0; + 1 : o = i1; + 2 : o = i2; + 3 : o = i3; + 2 : o = i4; + endcase +end + +endmodule + +module test(); + +reg [1:0] sel; +wire [2:0] out; + +mux mux(sel, 3\'d0, 3\'d1, 3\'d2, 3\'d3, 3\'d4, out); + +reg failed; + +(* ivl_synthesis_off *) +initial begin + failed = 0; + sel = 0; + repeat (4) begin + #1 $display(""%d : %b"", sel, out); + if (out !== sel) failed = 1; + sel = sel + 1; + end + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module test; + +reg [31:0] vec; + +initial begin + vec = 0; // make sure vec is not pruned + $test; +end + +endmodule +" +"task a_task (input int id); + $display(""This is task %0d."", id); +endtask + +// This should print the following: +// This is task 2. +// This is task 1. +module top; + initial begin + a_task(2); + a_task(1); + end +endmodule +" +"/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This sample demonstrates the post 20030904 Icarus Verilog feature + * where combinational blocks with time-0 races against the rest of + * the design can be resolved. + * + * The always @(foo) threads should be detected by the compiler as + * combinational, and should be pushed to the front of the time-0 + * scheduling queue. This causes the threads to enter the wait early + * so that it can detect the change from x to 1 for its value. + * + * The program HAS a time-0 race according to the IEEE1364 standard, + * but Icarus Verilog as an extension resolves this race intentionally + * as described. + */ + +module main; + + reg foo, bar; + reg foo_ok = 0, bar_ok = 0; + + initial foo = 1; + + always @(foo) begin + if (foo !== 1\'b1) begin +\t $display(""FAILED --(foo = %b)"", foo); +\t $finish; + end + foo_ok = 1; + end + + always @(bar) begin + if (bar !== 1\'b1) begin +\t $display(""FAILED --(bar = %b)"", bar); +\t $finish; + end + bar_ok = 1; + end + + initial bar = 1; + + initial begin + #1 if (foo_ok !== 1) begin +\t $display(""FAILED -- foo lost the race""); +\t $finish; + end + + if (bar_ok !== 1) begin +\t $display(""FAILED -- bar lost the race""); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"module test(); + +integer f; + +initial begin + f = $fopen(""work/br_gh209.dat""); + $fwrite(f, ""%c%c%c%c"", 8\'h00, 8\'h01, 8\'h02, 8\'h03); +end + +endmodule +" +"// Invalid packed dimensions +// This should generate a error message and not crash during elaboration + +typedef logic [] T1; +typedef logic [0] T2; +typedef logic [-1] T3; +typedef logic [$] T4; + +class C; +\tlogic [$] a; +\tT1 b; +\tT1 [$] c; + +\tlogic [0] d; +\tT2 e; +\tT2 [0] f; + +\tlogic [-1] g; +\tT3 h; +\tT3 [-1] i; + +\tlogic [$] j; +\tT4 k; +\tT4 [$] l; +endclass + +module test; +endmodule +" +"module main; + + real foo; + + initial begin + foo = 1.0; + if (foo != 1.0) begin +\t $display(""FAILED: Simple assign works not. foo=%f"", foo); +\t $finish; + end + + foo <= 1.5; + if (foo != 1.0) begin +\t $display(""FAILED: nb assign works too fast. foo=%f"", foo); +\t $finish; + end + + #1 if (foo != 1.5) begin +\t $display(""FAILED: nb assign works not. foo=%f"", foo); +\t $finish; + end + + $display(""PASSED""); + $finish; + end // initial begin + +endmodule // main +" +" +// This program should emit: +// m_argv[0] = str0 +// LARGE: 4 +// LARGE: 4 (2) +// m_argv[1] = str1 +// LARGE: 4 +// LARGE: 4 (2) +// + +module m; + + string m_argv [$]; + + function int size_function(input string val); + size_function = val.len(); + endfunction // size_function + + initial begin + m_argv.push_back (""str0""); + m_argv.push_back (""str1""); + + foreach (m_argv[i]) begin +\t $display(""m_argv[%0d] = %s"", i, m_argv[i]); +\t if(m_argv[i].len() >= 2) begin + $display (""LARGE: %0d"", m_argv[i].len()); +\t end else begin +\t $display(""FAILED: m_argv[i].len() == %0d"", m_argv[i].len()); +\t end +\t if(size_function(m_argv[i]) >= 2) begin + $display (""LARGE: %0d (2)"", size_function(m_argv[i])); +\t end else begin +\t $display(""FAILED: size_function(m_argv[i]) == %0d"", size_function(m_argv[i])); +\t end + end + end +endmodule : m +" +"module top; + parameter WIDTH = dut.WIDTH; + + test dut(); +endmodule + +module test; + parameter WIDTH = 8; +endmodule +" +" +// This tests the basic support for default arguments to task/function +// ports. The default port syntax gives SystemVerilog a limited form +// of variable argument lists. + +program main; + + function int increment(int val, int step = 1, int flag = 1); + increment = val + step*flag; + endfunction // increment + + initial begin + + if (increment(5) !== 6) begin +\t $display(""FAILED -- increment(5) --> %0d"", increment(5)); +\t $finish; + end + + if (increment(5,2) !== 7) begin +\t $display(""FAILED -- increment(5,2) --> %0d"", increment(5,2)); +\t $finish; + end + + if (increment(5,,3) !== 8) begin +\t $display(""FAILED -- increment(5,,3) --> %0d"", increment(5,,3)); +\t $finish; + end + $display(""PASSED""); + end + +endprogram // main +" +"module main; +\treal x; + +\tinitial +\t\tbegin +\t\t\tx = 1.0; + +\t\t\t$display(""Hello, World""); +\t\t\t$display(""Positive x is %f"", x); +\t\t\t$display(""-1.0 * x is %f"", -1.0 * x); +\t\t\t$display(""0.0 - x is %f"", 0.0 - x); +\t\t\t$display(""-x is %f"", -x); + +\t\t\t$finish(0); +\t\tend +endmodule +" +"module bug(); + +integer i; +integer j; + +reg [7:0] Value; + +initial begin + for (i = 0; i < 2; i = i + 1) begin + for (j = 0; j < 2; j = j + 1) begin + Value = i * 256 + j * 128; + $display(Value); + end + end +end + +endmodule +" +"// This test program shows how programs can be contained by +// modules, and can access variables in the context. +module main; + + reg[7:0] shared; + wire [7:0] not_shared = ~shared; + +program test1; + initial shared <= \'h55; +endprogram :test1 + +program test2; + reg [7:0] tmp; + final begin + if (shared !== \'h55) begin +\t $display(""FAILED -- shared=%b is not correct"", shared); +\t $finish; + end + + tmp = ~shared; + if (not_shared !== \'haa || not_shared !== tmp) begin +\t $display(""FAILED -- not_shared is not correct"", not_shared); +\t $finish; + end + + $display(""PASSED""); + end + +endprogram :test2 + +endmodule // main +" +"/* + * Copyright (c) 2000 Chris Lattner + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module test; + reg [3:0] val, y; + + initial begin + val = 2; + y = !val; + if (y !== 4\'b0000) begin + $display(""FAILED -- !%b --> %b"", val, y); + $finish; + end + + $display(""PASSED""); + end +endmodule +" +"/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + * $Log: mem1.v,v $ + * Revision 1.2 2001/01/29 17:26:06 ka6s + * Check in fixes contributed by Paul Campbell (Thanks Paul) + * + */ + +`define CLK 10 + +module main; + reg [31:0] counter; + integer i; + reg [23:0] testvec [15:0]; + reg clk; + wire [23:0] data; + reg write; + + + initial + begin + write = 0; + counter = 0; + clk = 0; + + $readmemb(""ivltests/mem1.dat"", testvec, 0); + + for (i = 0; i < 16; i = i + 1) + begin + $write(""mem[%d] = %x\ +"", i, testvec[i]); + end + end + + always + begin + #`CLK clk = ~clk; + end + + assign data = (write) ? testvec[counter] : 24\'bz; + + always @ (posedge clk) + begin + begin + write = 1; + #1 ; + $write(""%d %x\ +"", counter, data); + write = 0; + counter = counter + 1; + if (counter == 16) + $finish(0); + end + end + +endmodule +" +"// +// Copyright (c) 2003 Steve Williams +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +`timescale 1ns / 1ps + +module main; + + task test; + $display(""time within task: %t"", $time); + endtask // test + + initial begin + $timeformat(-9, 3, ""ns"", 6); + #1 $display(""time within module: %t"", $time); + test; + end + +endmodule +" +"// +// Copyright (c) 2002 Stephen Williams (steve at icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +module main; + + reg [3:0] val_drv = 4\'b0101; + wire [3:0] val; + + buf val_buf[3:0] (val, val_drv); + + initial begin + #50 if (val !== val_drv) begin +\t $display(""FAILED -- initial val %b !== %b"", val, val_drv); +\t $finish; + end + + force val = 4\'b1010; + #1 if (val !== 4\'b1010) begin +\t $display(""FAILED -- force 1010 failed, val=%b"", val); +\t $finish; + end + + // Use force to ""lift"" the driver. + force val = 4\'bzzzz; + + if (val !== 4\'bzzzz) begin +\t $display(""FAILED -- force z failed, val=%b"", val); +\t $finish; + end + + release val; + #1 if (val !== 4\'b0101) begin +\t $display(""FAILED -- unforced val = %b"", val); +\t $finish; + end + + val_drv = 4\'b1010; + #1 if (val !== 4\'b1010) begin +\t $display(""FAILED -- val_drv=%b, val=%b"", val_drv, val); +\t $finish; + end + + $display(""PASSED""); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always 3.1.2A always reg_lvalue <= constant ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + if(value1 != 4\'h5) +\t$display(""FAILED - 3.1.2A always reg_lvalue = constant\ +""); + else +\tbegin + $display(""PASSED\ +""); +\t $finish; + end + +always value1 <= 4\'h5 ; + +endmodule +" +"module test; + reg[2:0] a, b, c, d; + + initial begin + $monitor($time, "" a=%b; b=%b; c=%b; d=%b"", a, b, c, d); + a = 1; + b = 2; + c = 3; + d = 4; + #1; + swap(a, b); + #1; + swap(c, d); + #1; + if (a === 2 && b ===1 && c === 4 && d === 3) + $display(""PASSED""); + else + $display(""FAILED""); + end + + task swap(inout reg[2:0] x, y); + reg[2:0] temp; + begin + temp = x; + x = y; + y = temp; +// $display(""temp: %b; x: %b; y: %b"", temp, x, y); + end + endtask +endmodule // test +" +"module top; + +reg [3:0][3:0] array1; +reg [3:0][3:0] array2; +reg [3:0][3:0] array3; +reg [3:0][3:0] array4; +reg [3:0][3:0] array5; +reg [3:0][3:0] array6; + +reg failed = 0; + +initial begin + array1[0+:2] = 8\'h21; + array1[2+:2] = 8\'h43; + + array2[1+:2] = 8\'h32; + + array3[1-:2] = 8\'h21; + array3[3-:2] = 8\'h43; + + array4[2-:2] = 8\'h32; + + array5[1:0] = 8\'h21; + array5[3:2] = 8\'h43; + + array6[2:1] = 8\'h32; + + $display(""%h"", array1); + if (array1 !== 16\'h4321) failed = 1; + $display(""%h"", array2); + if (array2 !== 16\'hx32x) failed = 1; + $display(""%h"", array3); + if (array3 !== 16\'h4321) failed = 1; + $display(""%h"", array4); + if (array4 !== 16\'hx32x) failed = 1; + $display(""%h"", array5); + if (array5 !== 16\'h4321) failed = 1; + $display(""%h"", array6); + if (array6 !== 16\'hx32x) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"`timescale 1 ns / 1 ps +module test; + initial begin +\t#12.3456; +\t$display(""$time = %0t"", $time); +\t$test(test); +\t#34.5678; +\t$display(""$time = %0t"", $time); +\t$test(test); + end +endmodule + +`timescale 1 ps / 1 ps +module test2; + initial begin +\t#56.7890; +\t$display(""$time = %0t"", $time); +\t$test(test2); +\t#78.9012; +\t$display(""$time = %0t"", $time); +\t$test(test2); + end +endmodule +" +"nature Voltage; + units = ""V""; + access = V; + idt_nature = Flux; + abstol = 1e-6; +endnature + +discipline voltage; + potential Voltage; +enddiscipline + +nature Flux; + units = ""Wb""; + access = Phi; + ddt_nature = Voltage; + abstol = 1e-9; +endnature + +`timescale 1s/1s +module main; + + real value; + voltage in, out; + analog V(out) <+ transition(value, 0, 4); + + initial begin + value = 0.0; + #10 if (V(out) != value) begin +\t $display(""FAILED -- value=%g, res=%g"", value, V(out)); +\t $finish; + end + + // Halfway through the rise time, the output should have + // half the input. + value = 2.0; + //#2 if (V(out) != value/2) begin + #2 if (abs(V(out) - value/2) > 1e-6) begin +\t $display(""FAILED -- value=%g, value/2=%g, res=%f"", value, value/2, V(out)); +\t $finish; + end + + // After the full transition time, the output should match + // the input. + #2 if (V(out) != value) begin +\t $display(""FAILED -- value=%g, res=%f"", value, V(out)); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + reg [2:-1] vec; + integer idx; + + initial begin + pass = 1\'b1; + + idx = \'bx; + + vec = 4\'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1\'bx] <= 1\'b1; +`endif + #1 if (vec !== 4\'bxxx) begin + $display(""Failed vec[1\'bx], expected 4\'bxxxx, got %b"", vec); + pass = 1\'b0; + end + + vec = 4\'bxxxx; + vec[idx] <= 1\'b1; + #1 if (vec !== 4\'bxxxx) begin + $display(""Failed vec[1\'bx], expected 4\'bxxxx, got %b"", vec); + pass = 1\'b0; + end + + vec = 4\'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1\'bx:0] <= 1\'b1; +`endif + #1 if (vec !== 4\'bxxxx) begin + $display(""Failed vec[1\'bx:0], expected 4\'bxxxx, got %b"", vec); + pass = 1\'b0; + end + + vec = 4\'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[0:1\'bx] <= 1\'b1; +`endif + #1 if (vec !== 4\'bxxxx) begin + $display(""Failed vec[0:1\'bx], expected 4\'bxxxx, got %b"", vec); + pass = 1\'b0; + end + + vec = 4\'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1\'bx:1\'bx] <= 1\'b1; +`endif + #1 if (vec !== 4\'bxxxx) begin + $display(""Failed vec[1\'bx:1\'bx], expected 4\'bxxxx, got %b"", vec); + pass = 1\'b0; + end + + vec = 4\'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1\'bx+:1] <= 1\'b1; +`endif + #1 if (vec !== 4\'bxxxx) begin + $display(""Failed vec[1\'bx+:1], expected 4\'bxxxx, got %b"", vec); + pass = 1\'b0; + end + + vec = 4\'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1\'bx+:2] <= 2\'b01; +`endif + #1 if (vec !== 4\'bxxxx) begin + $display(""Failed vec[1\'bx+:2], expected 4\'bxxxx, got %b"", vec); + pass = 1\'b0; + end + + vec = 4\'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1\'bx-:1] <= 1\'b1; +`endif + #1 if (vec !== 4\'bxxxx) begin + $display(""Failed vec[1\'bx-:1], expected 4\'bxxxx, got %b"", vec); + pass = 1\'b0; + end + + vec = 4\'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1\'bx-:2] <= 2\'b01; +`endif + #1 if (vec !== 4\'bxxxx) begin + $display(""Failed vec[1\'bx-:2], expected 4\'bxxxx, got %b"", vec); + pass = 1\'b0; + end + + vec = 4\'bxxxx; + vec[idx+:1] <= 1\'b1; + #1 if (vec !== 4\'bxxxx) begin + $display(""Failed vec[idx+:1], expected 4\'bxxxx, got %b"", vec); + pass = 1\'b0; + end + + vec = 4\'bxxxx; + vec[idx+:2] <= 2\'b01; + #1 if (vec !== 4\'bxxxx) begin + $display(""Failed vec[idx+:2], expected 4\'bxxxx, got %b"", vec); + pass = 1\'b0; + end + + vec = 4\'bxxxx; + vec[idx-:1] <= 1\'b1; + #1 if (vec !== 4\'bxxxx) begin + $display(""Failed vec[idx-:1], expected 4\'bxxxx, got %b"", vec); + pass = 1\'b0; + end + + vec = 4\'bxxxx; + vec[idx-:2] <= 2\'b01; + #1 if (vec !== 4\'bxxxx) begin + $display(""Failed vec[idx-:2], expected 4\'bxxxx, got %b"", vec); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module top; + reg [47:0] out1, out2, out3, out4, out5; + integer i; + + initial begin + for (i=-1 ; i<2; i=i+1) begin + // i is signed so should it be sign extended? + out1 = 48\'d16 + i; + // I would have expected this to be the same as (i+0) below! + out2 = 48\'d16 + (i); + // All the rest of these are sign extended? + out3 = 48\'d16 + (i+0); + out4 = 48\'sd16 + i; + out5 = 48\'d16 + (i-1); + $display(""16 + %2d = %10d, %10d, %2d, %2d, -1 = %2d"", + i, out1, out2, out3, out4, out5); + end + end +endmodule +" +"// + // Copyright (c) 1999 Stephen Williams +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always case ( reg_value) case_item1; case_item2; case_item3; endcase +// D: + + + // time value1 value2 + // xxxx xxxx + // 1 0000 + // 2 0000 + // 3 0001 + // 4 0001 + // 5 0010 + // 6 0010 + +module main ; + +reg [3:0] value1,value2,value3; + +initial begin + #1 ; + #2 if (value2 != 0) begin + $display(""FAILED == at time 3, %b != 0"", value2); + $finish; + end + #2 if (value2 != 1) begin + $display(""FAILED == at time 5, %b != 1"", value2); + $finish; + end + #2 if (value2 != 2) begin + $display(""FAILED == at time 7, %b != 2"", value2); + $finish; + end + $display(""PASSED""); + $finish; +end + +initial begin + #1 value1 = 4\'b0000; + #2 value1 = 4\'b0001; + #2 value1 = 4\'b0010; +end + +always case (value1) +\t 4\'b0000 : begin +\t value2 = 4\'b0000 ; +\t #2 ; +\t end +\t 4\'b0001 : begin +\t value2 = 4\'b0001 ; +\t #2 ; +\t end +\t 4\'b0010 : begin +\t value2 = 4\'b0010 ; +\t #2 ; +\t end +\t 4\'bxxxx : #2 ; + +\t default : begin +\t $display(""FAILED -- unexpected value1===%b"", value1); +\t $finish; +\t end + +\tendcase + + +endmodule +" +"// Check the various variable indexed up selects (LSB > MSB). +module top; + parameter [-4:-1] ap = 4\'he; + parameter [-4:-1] bp = 4\'h1; + parameter [1:4] cp = 4\'he; + parameter [1:4] dp = 4\'h1; + + reg passed; + + wire [-4:-1] a = 4\'he; + wire [-4:-1] b = 4\'h1; + wire signed [0:0] s0 = -1; + wire signed [1:0] s1 = -1; + wire signed [2:0] s2 = -1; + reg [-4:-1] ar = 4\'he; + reg [-4:-1] br = 4\'h1; + + wire [1:4] c = 4\'he; + wire [1:4] d = 4\'h1; + wire [0:0] s3 = 0; + wire [1:0] s4 = 0; + reg [1:4] cr = 4\'he; + reg [1:4] dr = 4\'h1; + + wire [1:0] res_a0 = a[s0+:2]; + wire [1:0] res_b0 = b[s0+:2]; + wire [1:0] res_a1 = a[s1+:2]; + wire [1:0] res_b1 = b[s1+:2]; + wire [1:0] res_a2 = a[s2+:2]; + wire [1:0] res_b2 = b[s2+:2]; + + wire [1:0] res_c3 = c[s3+:2]; + wire [1:0] res_d3 = d[s3+:2]; + wire [1:0] res_c4 = c[s4+:2]; + wire [1:0] res_d4 = d[s4+:2]; + + reg [-4:-1] res_ab; + reg [1:4] res_cd; + + initial begin + #1; + passed = 1\'b1; + + // Check procedural R-value variable index up selects of a net. + + $display(""a[s0+:2]: %b"", a[s0+:2]); + if (a[s0+:2] !== 2\'b0x) begin + $display(""Failed a[s0+:2], expected 2\'b0x, got %b"", a[s0+:2]); + passed = 1\'b0; + end + + $display(""b[s0+:2]: %b"", b[s0+:2]); + if (b[s0+:2] !== 2\'b1x) begin + $display(""Failed b[s0+:2], expected 2\'b1x, got %b"", b[s0+:2]); + passed = 1\'b0; + end + + $display(""a[s1+:2]: %b"", a[s1+:2]); + if (a[s1+:2] !== 2\'b0x) begin + $display(""Failed a[s1+:2], expected 2\'b0x, got %b"", a[s1+:2]); + passed = 1\'b0; + end + + $display(""b[s1+:2]: %b"", b[s1+:2]); + if (b[s1+:2] !== 2\'b1x) begin + $display(""Failed b[s1+:2], expected 2\'b1x, got %b"", b[s1+:2]); + passed = 1\'b0; + end + + $display(""a[s2+:2]: %b"", a[s2+:2]); + if (a[s2+:2] !== 2\'b0x) begin + $display(""Failed a[s2+:2], expected 2\'b0x, got %b"", a[s2+:2]); + passed = 1\'b0; + end + + $display(""b[s2+:2]: %b"", b[s2+:2]); + if (b[s2+:2] !== 2\'b1x) begin + $display(""Failed b[s2+:2], expected 2\'b1x, got %b"", b[s2+:2]); + passed = 1\'b0; + end + + $display(""c[s3+:2]: %b"", c[s3+:2]); + if (c[s3+:2] !== 2\'bx1) begin + $display(""Failed c[s3+:2], expected 2\'bx1, got %b"", c[s3+:2]); + passed = 1\'b0; + end + + $display(""d[s3+:2]: %b"", d[s3+:2]); + if (d[s3+:2] !== 2\'bx0) begin + $display(""Failed d[s3+:2], expected 2\'bx0, got %b"", d[s3+:2]); + passed = 1\'b0; + end + + $display(""c[s4+:2]: %b"", c[s4+:2]); + if (c[s4+:2] !== 2\'bx1) begin + $display(""Failed c[s4+:2], expected 2\'bx1, got %b"", c[s4+:2]); + passed = 1\'b0; + end + + $display(""d[s4+:2]: %b"", d[s4+:2]); + if (d[s4+:2] !== 2\'bx0) begin + $display(""Failed d[s4+:2], expected 2\'bx0, got %b"", d[s4+:2]); + passed = 1\'b0; + end + + // Check procedural R-value variable index up selects of a parameter. + + $display(""ap[s0+:2]: %b"", ap[s0+:2]); + if (ap[s0+:2] !== 2\'b0x) begin + $display(""Failed ap[s0+:2], expected 2\'b0x, got %b"", ap[s0+:2]); + passed = 1\'b0; + end + + $display(""bp[s0+:2]: %b"", bp[s0+:2]); + if (bp[s0+:2] !== 2\'b1x) begin + $display(""Failed bp[s0+:2], expected 2\'b1x, got %b"", bp[s0+:2]); + passed = 1\'b0; + end + + $display(""ap[s1+:2]: %b"", ap[s1+:2]); + if (ap[s1+:2] !== 2\'b0x) begin + $display(""Failed ap[s1+:2], expected 2\'b0x, got %b"", ap[s1+:2]); + passed = 1\'b0; + end + + $display(""bp[s1+:2]: %b"", bp[s1+:2]); + if (bp[s1+:2] !== 2\'b1x) begin + $display(""Failed bp[s1+:2], expected 2\'b1x, got %b"", bp[s1+:2]); + passed = 1\'b0; + end + + $display(""ap[s2+:2]: %b"", ap[s2+:2]); + if (ap[s2+:2] !== 2\'b0x) begin + $display(""Failed ap[s2+:2], expected 2\'b0x, got %b"", ap[s2+:2]); + passed = 1\'b0; + end + + $display(""bp[s2+:2]: %b"", bp[s2+:2]); + if (bp[s2+:2] !== 2\'b1x) begin + $display(""Failed bp[s2+:2], expected 2\'b1x, got %b"", bp[s2+:2]); + passed = 1\'b0; + end + + $display(""cp[s3+:2]: %b"", cp[s3+:2]); + if (cp[s3+:2] !== 2\'bx1) begin + $display(""Failed cp[s3+:2], expected 2\'bx1, got %b"", cp[s3+:2]); + passed = 1\'b0; + end + + $display(""dp[s3+:2]: %b"", dp[s3+:2]); + if (dp[s3+:2] !== 2\'bx0) begin + $display(""Failed dp[s3+:2], expected 2\'bx0, got %b"", dp[s3+:2]); + passed = 1\'b0; + end + + $display(""cp[s4+:2]: %b"", cp[s4+:2]); + if (cp[s4+:2] !== 2\'bx1) begin + $display(""Failed cp[s4+:2], expected 2\'bx1, got %b"", cp[s4+:2]); + passed = 1\'b0; + end + + $display(""dp[s4+:2]: %b"", dp[s4+:2]); + if (dp[s4+:2] !== 2\'bx0) begin + $display(""Failed dp[s4+:2], expected 2\'bx0, got %b"", dp[s4+:2]); + passed = 1\'b0; + end + + // Check procedural R-value variable index up selects of a reg. + + $display(""ar[s0+:2]: %b"", ar[s0+:2]); + if (ar[s0+:2] !== 2\'b0x) begin + $display(""Failed ar[s0+:2], expected 2\'b0x, got %b"", ar[s0+:2]); + passed = 1\'b0; + end + + $display(""br[s0+:2]: %b"", br[s0+:2]); + if (br[s0+:2] !== 2\'b1x) begin + $display(""Failed br[s0+:2], expected 2\'b1x, got %b"", br[s0+:2]); + passed = 1\'b0; + end + + $display(""ar[s1+:2]: %b"", ar[s1+:2]); + if (ar[s1+:2] !== 2\'b0x) begin + $display(""Failed ar[s1+:2], expected 2\'b0x, got %b"", ar[s1+:2]); + passed = 1\'b0; + end + + $display(""br[s1+:2]: %b"", br[s1+:2]); + if (br[s1+:2] !== 2\'b1x) begin + $display(""Failed br[s1+:2], expected 2\'b1x, got %b"", br[s1+:2]); + passed = 1\'b0; + end + + $display(""ar[s2+:2]: %b"", ar[s2+:2]); + if (ar[s2+:2] !== 2\'b0x) begin + $display(""Failed ar[s2+:2], expected 2\'b0x, got %b"", ar[s2+:2]); + passed = 1\'b0; + end + + $display(""br[s2+:2]: %b"", br[s2+:2]); + if (br[s2+:2] !== 2\'b1x) begin + $display(""Failed br[s2+:2], expected 2\'b1x, got %b"", br[s2+:2]); + passed = 1\'b0; + end + + $display(""cr[s3+:2]: %b"", cr[s3+:2]); + if (cr[s3+:2] !== 2\'bx1) begin + $display(""Failed cr[s3+:2], expected 2\'bx1, got %b"", cr[s3+:2]); + passed = 1\'b0; + end + + $display(""dr[s3+:2]: %b"", dr[s3+:2]); + if (dr[s3+:2] !== 2\'bx0) begin + $display(""Failed dr[s3+:2], expected 2\'bx0, got %b"", dr[s3+:2]); + passed = 1\'b0; + end + + $display(""cr[s4+:2]: %b"", cr[s4+:2]); + if (cr[s4+:2] !== 2\'bx1) begin + $display(""Failed cr[s4+:2], expected 2\'bx1, got %b"", cr[s4+:2]); + passed = 1\'b0; + end + + $display(""dr[s4+:2]: %b"", dr[s4+:2]); + if (dr[s4+:2] !== 2\'bx0) begin + $display(""Failed dr[s4+:2], expected 2\'bx0, got %b"", dr[s4+:2]); + passed = 1\'b0; + end + + // Check continuous assignment R-value variable index up selects. + + if (res_a0 !== 2\'b0x) begin + $display(""Failed res_a0, expected 2\'b0x, got %b"", res_a0); + passed = 1\'b0; + end + + if (res_b0 !== 2\'b1x) begin + $display(""Failed res_b0, expected 2\'b1x, got %b"", res_b0); + passed = 1\'b0; + end + + if (res_a1 !== 2\'b0x) begin + $display(""Failed res_a1, expected 2\'b0x, got %b"", res_a1); + passed = 1\'b0; + end + + if (res_b1 !== 2\'b1x) begin + $display(""Failed res_b1, expected 2\'b1x, got %b"", res_b1); + passed = 1\'b0; + end + + if (res_a2 !== 2\'b0x) begin + $display(""Failed res_a2, expected 2\'b0x, got %b"", res_a2); + passed = 1\'b0; + end + + if (res_b2 !== 2\'b1x) begin + $display(""Failed res_b2, expected 2\'b1x, got %b"", res_b2); + passed = 1\'b0; + end + + if (res_c3 !== 2\'bx1) begin + $display(""Failed res_c3, expected 2\'bx1, got %b"", res_c3); + passed = 1\'b0; + end + + if (res_d3 !== 2\'bx0) begin + $display(""Failed res_d3, expected 2\'bx0, got %b"", res_d3); + passed = 1\'b0; + end + + if (res_c4 !== 2\'bx1) begin + $display(""Failed res_c4, expected 2\'bx1, got %b"", res_c4); + passed = 1\'b0; + end + + if (res_d4 !== 2\'bx0) begin + $display(""Failed res_d4, expected 2\'bx0, got %b"", res_d4); + passed = 1\'b0; + end + + // Check procedural L-value variable index up selects. + + res_ab = 4\'bxxxx; + res_ab[s0+:2] = 2\'b00; + if (res_ab !== 4\'bxxx0) begin + $display(""Failed res_ab[s0], expected 4\'bxxx0, got %b"", res_ab); + passed = 1\'b0; + end + + res_ab = 4\'bxxxx; + res_ab[s1+:2] = 2\'b00; + if (res_ab !== 4\'bxxx0) begin + $display(""Failed res_ab[s1], expected 4\'bxxx0, got %b"", res_ab); + passed = 1\'b0; + end + + res_ab = 4\'bxxxx; + res_ab[s2+:2] = 2\'b00; + if (res_ab !== 4\'bxxx0) begin + $display(""Failed res_ab[s2], expected 4\'bxxx0, got %b"", res_ab); + passed = 1\'b0; + end + + res_cd = 4\'bxxxx; + res_cd[s3+:2] = 2\'b00; + if (res_cd !== 4\'b0xxx) begin + $display(""Failed res_cd[s3], expected 4\'b0xxx, got %b"", res_cd); + passed = 1\'b0; + end + + res_cd = 4\'bxxxx; + res_cd[s4+:2] = 2\'b00; + if (res_cd !== 4\'b0xxx) begin + $display(""Failed res_cd[s4], expected 4\'b0xxx, got %b"", res_cd); + passed = 1\'b0; + end + + if (passed) $display(""Compare tests passed""); + end +endmodule +" +"/* Copyright (C) 2000 Stephen G. Tell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ +/* fdisplay1 - test $fwrite and $fdisplay system tasks without using $fopen + * + * NB: this may need a little tweaking, as I\'m not sure that all verilogs + * have the predefined $fdisplay descriptors 2 and 3 matching what + * vpi_mcd_printf provides. + */ + +module fdisplay1; + + integer fp; + reg [7:0] a; + + initial begin + + $display(""message to stdout (from $display)\ +""); + $fwrite(1, ""another message (via fwrite) ""); + $fdisplay(1,""to stdout\ + (via fdisplay)""); + #5 + + a = 8\'h5a; + $fwrite(1, ""a = %b at %0t\ +"", a, $time); + + $finish(0); + + end // initial begin + +endmodule +" +"`begin_keywords ""1364-2005"" +// +// Copyright (c) 1999 Thomas Coonan (tcoonan@mindspring.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// Behavioral Verilog for CRC16 and CRC32 for use in a testbench. +// +// The specific polynomials and conventions regarding bit-ordering etc. +// are specific to the Cable Modem DOCSIS protocol, but the general scheme +// should be reusable for other types of CRCs with some fiddling. +// +// This CRC code works for a specific type of network protocol, and it +// must do certain byte swappings, etc. You may need to play with it +// for your protocol. Also, make sure the polynomials are what you +// really want. This is obviously, not synthesizable - I just used this +// in a testbench at one point. +// +// These tasks are crude and rely on some global parameters. They should +// also read from a file, yada yada yada. It is probably better to do this +// with a PLI call, but here it is anyway.. +// +// The test case includes a golden DOCSIS (Cable Modem) test message that +// was captured in a lab. +// +// tom coonan, 1999. +// +module test_gencrc; + +// *** Buffer for the Golden Message *** +reg [7:0]\ttest_packet[0:54]; + +// *** Global parameter block for the CRC32 calculator. +// +parameter\tCRC32_POLY = 32\'h04C11DB7; +reg [ 7:0]\tcrc32_packet[0:255]; +integer\t\tcrc32_length; +reg [31:0]\tcrc32_result; + +// *** Global parameter block for the CRC16 calculator. +// +parameter\tCRC16_POLY = 16\'h1020; +reg [ 7:0]\tcrc16_packet[0:255]; +integer\t\tcrc16_length; +reg [15:0]\tcrc16_result; + +`define TEST_GENCRC +`ifdef TEST_GENCRC +// Call the main test task and then quit. +// +initial begin + main_test; + $finish; +end +`endif + +// **************************************************************** +// * +// * GOLDEN MESSAGE +// * +// * The golden message is a DOCSIS frame that was captured off +// * the Broadcom reference design. It is a MAP message. It +// * includes a HCS (crc 16) and a CRC32. +// * +// * +// **************************************************************** +// +task initialize_test_packet; + begin + test_packet[00] = 8\'hC2;\t// FC. HCS coverage starts here. + test_packet[01] = 8\'h00;\t// MACPARAM + test_packet[02] = 8\'h00;\t// MAC LEN + test_packet[03] = 8\'h30;\t// MAC LEN. HCS Coverage includes this byte and ends here. + test_packet[04] = 8\'hF2;\t// CRC16 (also known as HCS) + test_packet[05] = 8\'hCF;\t// CRC16 cont.. + test_packet[06] = 8\'h01;\t// Start of the IEEE payload. CRC32 covererage starts here. This is the DA field + test_packet[07] = 8\'hE0;\t// DA field cont.. + test_packet[08] = 8\'h2F;\t// DA field cont.. + test_packet[09] = 8\'h00;\t// DA field cont.. + test_packet[10] = 8\'h00;\t// DA field cont.. + test_packet[11] = 8\'h01;\t// DA field cont.. + test_packet[12] = 8\'h00;\t// SA field + test_packet[13] = 8\'h80;\t// SA field cont.. + test_packet[14] = 8\'h42;\t// SA field cont.. + test_packet[15] = 8\'h42;\t// SA field cont.. + test_packet[16] = 8\'h20;\t// SA field cont.. + test_packet[17] = 8\'h9E;\t// SA field cont.. + test_packet[18] = 8\'h00;\t// IEEE LEN field + test_packet[19] = 8\'h1E;\t// IEEE LEN field cont. + test_packet[20] = 8\'h00;\t// LLC field. + test_packet[21] = 8\'h00;\t// LLC field cont... + test_packet[22] = 8\'h03;\t// LLC field cont... + test_packet[23] = 8\'h01;\t// LLC field cont... + test_packet[24] = 8\'h03;\t// LLC field cont... This is also the TYPE, which indicates MAP. + test_packet[25] = 8\'h00;\t// LLC field cont... + test_packet[26] = 8\'h01;\t// Start of MAP message payload. + test_packet[27] = 8\'h01;\t// MAP message payload.. + test_packet[28] = 8\'h02;\t// MAP message payload.. + test_packet[29] = 8\'h00;\t// MAP message payload.. + test_packet[30] = 8\'h00;\t// MAP message payload.. + test_packet[31] = 8\'h18;\t// MAP message payload.. + test_packet[32] = 8\'hAA;\t// MAP message payload.. + test_packet[33] = 8\'h58;\t// MAP message payload.. + test_packet[34] = 8\'h00;\t// MAP message payload.. + test_packet[35] = 8\'h18;\t// MAP message payload.. + test_packet[36] = 8\'hA8;\t// MAP message payload.. + test_packet[37] = 8\'hA0;\t// MAP message payload.. + test_packet[38] = 8\'h02;\t// MAP message payload.. + test_packet[39] = 8\'h03;\t// MAP message payload.. + test_packet[40] = 8\'h03;\t// MAP message payload.. + test_packet[41] = 8\'h08;\t// MAP message payload.. + test_packet[42] = 8\'hFF;\t// MAP message payload.. + test_packet[43] = 8\'hFC;\t// MAP message payload.. + test_packet[44] = 8\'h40;\t// MAP message payload.. + test_packet[45] = 8\'h00;\t// MAP message payload.. + test_packet[46] = 8\'h00;\t// MAP message payload.. + test_packet[47] = 8\'h01;\t// MAP message payload.. + test_packet[48] = 8\'hC0;\t// MAP message payload.. + test_packet[49] = 8\'h14;\t// Last byte of MAP payload, last byte covered by CRC32. + test_packet[50] = 8\'hDD;\t// CRC32 Starts here + test_packet[51] = 8\'hBF;\t// CRC32 cont.. + test_packet[52] = 8\'hC1;\t// CRC32 cont.. + test_packet[53] = 8\'h2E;\t// Last byte of CRC32, last byte of DOCSIS. + end +endtask + +// ************************************************************************* +// * +// * Main test task. +// * +// * Use our primary ""golden packet"". Copy into the generic global +// * variables that the low-level \'gencrc16\' and \'gencrc32\' tasks use. +// * Comare against the expected values and report SUCCESS or FAILURE. +// * +// ************************************************************************* +// +task main_test; + integer\ti, j; + integer\tnum_errors; + reg [15:0]\tcrc16_expected; + reg [31:0]\tcrc32_expected; + begin + + num_errors = 0; + + // Initialize the Golden Message! + // + initialize_test_packet; + + // **** TEST CRC16 + // + // + // Copy golden test_packet into the main crc16 buffer.. + for (i=0; i<4; i=i+1) begin + crc16_packet[i] = test_packet[i]; + end + crc16_expected = {test_packet[4], test_packet[5]}; + crc16_length = 4; // Must tell test function the length + gencrc16; // Call main test function + if (crc16_result !== crc16_expected) + begin + num_errors = num_errors + 1; + $display (""FAILED - Actual crc16_result = %h, Expected = %h"", + crc16_result, crc16_expected); + end + + // **** TEST CRC16 + // + j = 0; + for (i=6; i<50; i=i+1) begin + crc32_packet[j] = test_packet[i]; + j = j + 1; + end + crc32_expected = {test_packet[50], test_packet[51], test_packet[52], test_packet[53]}; + crc32_length = 44; + gencrc32; + if (crc32_result !== crc32_expected) + begin + $display (""FAILED - Actual crc32_result = %h, Expected = %h"", + crc32_result, crc32_expected); + num_errors = num_errors + 1; + end + + if(num_errors == 0) + $display(""PASSED""); +end + +endtask + + +// **************************************************************** +// * +// * Main working CRC tasks are: gencrc16, gencrc32. +// * +// * These tasks rely on some globals (see front of program). +// * +// **************************************************************** + + +// Generate a (DOCSIS) CRC16. +// +// Uses the GLOBAL variables: +// +// Globals referenced: +// parameter\tCRC16_POLY = 16\'h1020; +// reg [ 7:0]\tcrc16_packet[0:255]; +// integer\tcrc16_length; +// +// Globals modified: +// reg [15:0]\tcrc16_result; +// +task gencrc16; + integer\tbyte, bit; + reg\t\tmsb; + reg [7:0]\tcurrent_byte; + reg [15:0]\ttemp; + begin + crc16_result = 16\'hffff; + for (byte = 0; byte < crc16_length; byte = byte + 1) begin + current_byte = crc16_packet[byte]; + for (bit = 0; bit < 8; bit = bit + 1) begin + msb = crc16_result[15]; + crc16_result = crc16_result << 1; + if (msb != current_byte[bit]) begin + crc16_result = crc16_result ^ CRC16_POLY; + crc16_result[0] = 1; + end + end + end + + // Last step is to ""mirror"" every bit, swap the 2 bytes, and then complement each bit. + // + // Mirror: + for (bit = 0; bit < 16; bit = bit + 1) + temp[15-bit] = crc16_result[bit]; + + // Swap and Complement: + crc16_result = ~{temp[7:0], temp[15:8]}; + end +endtask + + +// Generate a (DOCSIS) CRC32. +// +// Uses the GLOBAL variables: +// +// Globals referenced: +// parameter\tCRC32_POLY = 32\'h04C11DB7; +// reg [ 7:0]\tcrc32_packet[0:255]; +// integer\tcrc32_length; +// +// Globals modified: +// reg [31:0]\tcrc32_result; +// + +task gencrc32; + integer\tbyte, bit; + reg\t\tmsb; + reg [7:0]\tcurrent_byte; + reg [31:0]\ttemp; + begin + crc32_result = 32\'hffffffff; + for (byte = 0; byte < crc32_length; byte = byte + 1) begin + current_byte = crc32_packet[byte]; + for (bit = 0; bit < 8; bit = bit + 1) begin + msb = crc32_result[31]; + crc32_result = crc32_result << 1; + if (msb != current_byte[bit]) begin + crc32_result = crc32_result ^ CRC32_POLY; + crc32_result[0] = 1; + end + end + end + + // Last step is to ""mirror"" every bit, swap the 4 bytes, and then complement each bit. + // + // Mirror: + for (bit = 0; bit < 32; bit = bit + 1) + temp[31-bit] = crc32_result[bit]; + + // Swap and Complement: + crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]}; + end +endtask + +endmodule +`end_keywords +" +"/* + * This program tests that enumeration value first/last/next + * methods work properly. The .next method requires some run-time + * support for enumeration. + */ +module main; + + enum { RED, GREEN = 2, BLUE } color1; + + initial begin + color1 = RED; + $display(""color1.first == %0d"", color1.first); + $display(""color1.last == %0d"", color1.last); + $display(""color1.num == %0d"", color1.num); + $display(""color1.next == %0d"", color1.next); + + color1 = color1.next; + if (color1 != GREEN || color1 !== 2) begin +\t $display(""FAILED -- should be %0d, got %0d"", GREEN, color1); +\t $finish; + end + + color1 = color1.next; + if (color1 != BLUE || color1 !== 3 || color1 != color1.last) begin +\t $display(""FAILED -- should be %0d, got %0d"", BLUE, color1); +\t $finish; + end + + color1 = color1.prev; + if (color1 != GREEN || color1 !== 2) begin +\t $display(""FAILED -- should be %0d, got %0d"", GREEN, color1); +\t $finish; + end + + color1 = color1.prev; + if (color1 != RED || color1 !== 0 || color1 != color1.first) begin +\t $display(""FAILED -- should be %0d, got %0d"", RED, color1); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"module main; + + reg clk; + + localparam integer TEST = 100; + print #(""PASSED"", TEST) foo (clk); + + initial begin + clk = 0; + #1 clk = 1; + #1 $finish; + end + +endmodule // main + +module print (input wire clk); + + parameter message = """"; + parameter number = 0; + + always @(posedge clk) begin + if (number !== 100) begin +\t $display(""FAILED -- number=%d\ +"", number); +\t $finish; + end + $display(""%s"", message); + end + +endmodule // print +" +" +module test_mux + (input wire [1:0] D0, D1, + input wire [1:0] S, + output reg [1:0] Q); + + always @(*) begin + if (S[1]==1'b0) +\tcase (S[0]) +\t 1'b0: Q = D0; +\t 1'b1: Q = D1; +\tendcase // case (S[0]) + else +\tQ = 2'b0; + end + +endmodule // test_mux +" +"module dut; + +function y(input x); + y = x; +endfunction + +reg a, b; +reg c, d; + +always @* begin + c = y(a); + d = y(b); +end + +endmodule + +module tb; + +dut dut(); + +initial begin + #1 dut.a = 0; + #1 dut.b = 1; + #1 $display(dut.a,,dut.b,,dut.c,,dut.d); + if (dut.c === 0 && dut.d === 1) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + * $Id: timer_tb.v,v 1.1 2003/04/01 05:55:24 stevewilliams Exp $ + */ + +`timescale 1us / 1us + +module main; + + wire rdy; + reg\treset, clk; + + timer dut(.rdy(rdy), .clk(clk), .reset(reset)); + + always begin + #5 clk = 1; + #5 clk = 0; + end + + initial begin + $dumpvars(0, main); + #7 reset = 1; + #1 if (rdy !== 0) begin +\t $display(""FAILED: reset did not clear rdy. rdy=%b"", rdy); +\t $finish; + end + #6 reset = 0; + end + + always @(posedge clk) + if (rdy === 1) begin +\t$display(""rdy=%b at time=%0d"", rdy, $time); +\tif ($time != 175) begin +\t $display(""FAILED: timer ran out incorrectly.""); +\t $finish; +\tend + +\t$display(""PASSED""); +\t$finish; + end + +endmodule // main +" +"/* + * The base vpi_get() is not returning the correct result for + * a signed value. There are obviously other problems as well. + */ +module top; + reg [7:0] rval; + reg signed [7:0] base; // This fails (no sign extension?). +// reg signed [31:0] base; // This works on a 32 bit machine. +// integer base; // And this works + + initial begin + rval = 8\'b10100101; + for (base = 0; base > -8; base = base -1) begin + $displayb(""%3d %b "", base, rval[base +: 8], rval[base +: 8]); + end + $display; + for (base = 0; base > -8; base = base -1) begin + $displayb(""%3d %b "", base+1, rval[base+1 +: 8], rval[base+1 +: 8]); + end + end +endmodule +" +"`timescale 1 ps/1 ps + +// extracted from altera_mf.v +module bug2011429; + reg pass = 1\'b1; + reg [7:0] vco_tap; + reg vco_c0_last_value; + integer c_ph_val[0:5]; + + always @(vco_tap[c_ph_val[0]]) + vco_c0_last_value = vco_tap[c_ph_val[0]]; + + initial begin + vco_tap = 8\'b10101010; + c_ph_val[0] = 0; + #1; + if (vco_c0_last_value != 1\'b0) begin + $display(""FAILED initial value, got %b"", vco_c0_last_value); + pass = 1\'b0; + end + + vco_tap = vco_tap >> 1; + #1; + if (vco_c0_last_value != 1\'b1) begin + $display(""FAILED shifted value, got %b"", vco_c0_last_value); + pass = 1\'b0; + end + + c_ph_val[0] = 1; + #1; + if (vco_c0_last_value != 1\'b0) begin + $display(""FAILED index change, got %b"", vco_c0_last_value); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program demonstrates a tricky aspect of the Verilog syntax. + * The problem is with the repeat statement. In fact, there is a + * question as to whether it is a repeat statement at all, or an + * event statement with a repeat modifier. These are the possibilities: + * + * procedural_timing_control_statement ::= + * delay_or_event_control statement_or_null + * + * delay_or_event_control ::= + * event_control + * | repeat ( expression ) event_control + * + * If this interpretation is used, then ``repeat (5) @(posedge clk)\'\' + * should be taken as a delay_or_event_control and the thread will + * block until the 5th clk posedge. + * + * loop_statement ::= + * repeat ( expression ) statement + * + * If *this* interpretation is used, then ``repeat (5)\'\' is the loop + * head is used and the statement in the example is executed 5 times. + * + * These two interpretations both appear to be perfectly valid. However, + * real tools use the loop_statement, so the standard must be considered + * broken and this interpretation used. + */ + +module main; + + reg clk = 1; + always #5 clk = ~clk; + + initial #1 + repeat (5) @(posedge clk) begin +\t if ($time !== 10) begin +\t $display(""FAILED -- $time = %t"", $time); +\t $finish; +\t end + +\t $display(""PASSED""); +\t $finish; + end + +endmodule // main +" +"// Copyright (c) 2015 CERN +// @author Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for variable initialization. + +module vhdl_var_init_test; +logic init; +logic [7:0] slv; +bit b; +int i; +vhdl_var_init dut(init, slv, b, i); + +initial begin + init = 0; + #1 init = 1; + #1; + + if(slv !== 8\'b01000010) begin + $display(""FAILED 1""); + $finish(); + end + + if(b !== false) begin + $display(""FAILED 2""); + $finish(); + end + + if(i !== 42) begin + $display(""FAILED 3""); + $finish(); + end + + $display(""PASSED""); +end + +endmodule +" +"// Check the various variable indexed down selects (LSB > MSB). +module top; + parameter [-4:-1] ap = 4\'he; + parameter [-4:-1] bp = 4\'h1; + parameter [1:4] cp = 4\'he; + parameter [1:4] dp = 4\'h1; + + reg passed; + + wire [-4:-1] a = 4\'he; + wire [-4:-1] b = 4\'h1; + wire [0:0] s0 = 0; + wire [1:0] s1 = 0; + wire [2:0] s2 = 0; + reg [-4:-1] ar = 4\'he; + reg [-4:-1] br = 4\'h1; + + wire [1:4] c = 4\'he; + wire [1:4] d = 4\'h1; + wire [0:0] s3 = 1; + wire [1:0] s4 = 1; + reg [1:4] cr = 4\'he; + reg [1:4] dr = 4\'h1; + + wire [1:0] res_a0 = a[s0-:2]; + wire [1:0] res_b0 = b[s0-:2]; + wire [1:0] res_a1 = a[s1-:2]; + wire [1:0] res_b1 = b[s1-:2]; + wire [1:0] res_a2 = a[s2-:2]; + wire [1:0] res_b2 = b[s2-:2]; + + wire [1:0] res_c3 = c[s3-:2]; + wire [1:0] res_d3 = d[s3-:2]; + wire [1:0] res_c4 = c[s4-:2]; + wire [1:0] res_d4 = d[s4-:2]; + + reg [-4:-1] res_ab; + reg [1:4] res_cd; + + initial begin + #1; + passed = 1\'b1; + + // Check procedural R-value variable index down selects of a net. + + $display(""a[s0-:2]: %b"", a[s1-:2]); + if (a[s0-:2] !== 2\'b0x) begin + $display(""Failed a[s0-:2], expected 2\'b0x, got %b"", a[s0-:2]); + passed = 1\'b0; + end + + $display(""b[s0-:2]: %b"", b[s1-:2]); + if (b[s0-:2] !== 2\'b1x) begin + $display(""Failed b[s0-:2], expected 2\'b1x, got %b"", b[s0-:2]); + passed = 1\'b0; + end + + $display(""a[s1-:2]: %b"", a[s1-:2]); + if (a[s1-:2] !== 2\'b0x) begin + $display(""Failed a[s1-:2], expected 2\'b0x, got %b"", a[s1-:2]); + passed = 1\'b0; + end + + $display(""b[s1-:2]: %b"", b[s1-:2]); + if (b[s1-:2] !== 2\'b1x) begin + $display(""Failed b[s1-:2], expected 2\'b1x, got %b"", b[s1-:2]); + passed = 1\'b0; + end + + $display(""a[s2-:2]: %b"", a[s2-:2]); + if (a[s2-:2] !== 2\'b0x) begin + $display(""Failed a[s2-:2], expected 2\'b0x, got %b"", a[s2-:2]); + passed = 1\'b0; + end + + $display(""b[s2-:2]: %b"", b[s2-:2]); + if (b[s2-:2] !== 2\'b1x) begin + $display(""Failed b[s2-:2], expected 2\'b1x, got %b"", b[s2-:2]); + passed = 1\'b0; + end + + $display(""c[s3-:2]: %b"", c[s3-:2]); + if (c[s3-:2] !== 2\'bx1) begin + $display(""Failed c[s3-:2], expected 2\'bx1, got %b"", c[s3-:2]); + passed = 1\'b0; + end + + $display(""d[s3-:2]: %b"", d[s3-:2]); + if (d[s3-:2] !== 2\'bx0) begin + $display(""Failed d[s3-:2], expected 2\'bx0, got %b"", d[s3-:2]); + passed = 1\'b0; + end + + $display(""c[s4-:2]: %b"", c[s4-:2]); + if (c[s4-:2] !== 2\'bx1) begin + $display(""Failed c[s4-:2], expected 2\'bx1, got %b"", c[s4-:2]); + passed = 1\'b0; + end + + $display(""d[s4-:2]: %b"", d[s4-:2]); + if (d[s4-:2] !== 2\'bx0) begin + $display(""Failed d[s4-:2], expected 2\'bx0, got %b"", d[s4-:2]); + passed = 1\'b0; + end + + // Check procedural R-value variable index down selects of a parameter. + + $display(""ap[s0-:2]: %b"", ap[s0-:2]); + if (ap[s0-:2] !== 2\'b0x) begin + $display(""Failed ap[s0-:2], expected 2\'b0x, got %b"", ap[s0-:2]); + passed = 1\'b0; + end + + $display(""bp[s0-:2]: %b"", bp[s0-:2]); + if (bp[s0-:2] !== 2\'b1x) begin + $display(""Failed bp[s0-:2], expected 2\'b1x, got %b"", bp[s0-:2]); + passed = 1\'b0; + end + + $display(""ap[s1-:2]: %b"", ap[s1-:2]); + if (ap[s1-:2] !== 2\'b0x) begin + $display(""Failed ap[s1-:2], expected 2\'b0x, got %b"", ap[s1-:2]); + passed = 1\'b0; + end + + $display(""bp[s1-:2]: %b"", bp[s1-:2]); + if (bp[s1-:2] !== 2\'b1x) begin + $display(""Failed bp[s1-:2], expected 2\'b1x, got %b"", bp[s1-:2]); + passed = 1\'b0; + end + + $display(""ap[s2-:2]: %b"", ap[s2-:2]); + if (ap[s2-:2] !== 2\'b0x) begin + $display(""Failed ap[s2-:2], expected 2\'b0x, got %b"", ap[s2-:2]); + passed = 1\'b0; + end + + $display(""bp[s2-:2]: %b"", bp[s2-:2]); + if (bp[s2-:2] !== 2\'b1x) begin + $display(""Failed bp[s2-:2], expected 2\'b1x, got %b"", bp[s2-:2]); + passed = 1\'b0; + end + + $display(""cp[s3-:2]: %b"", cp[s3-:2]); + if (cp[s3-:2] !== 2\'bx1) begin + $display(""Failed cp[s3-:2], expected 2\'bx1, got %b"", cp[s3-:2]); + passed = 1\'b0; + end + + $display(""dp[s3-:2]: %b"", dp[s3-:2]); + if (dp[s3-:2] !== 2\'bx0) begin + $display(""Failed dp[s3-:2], expected 2\'bx0, got %b"", dp[s3-:2]); + passed = 1\'b0; + end + + $display(""cp[s4-:2]: %b"", cp[s4-:2]); + if (cp[s4-:2] !== 2\'bx1) begin + $display(""Failed cp[s4-:2], expected 2\'bx1, got %b"", cp[s4-:2]); + passed = 1\'b0; + end + + $display(""dp[s4-:2]: %b"", dp[s4-:2]); + if (dp[s4-:2] !== 2\'bx0) begin + $display(""Failed dp[s4-:2], expected 2\'bx0, got %b"", dp[s4-:2]); + passed = 1\'b0; + end + + // Check procedural R-value variable index down selects of a reg. + + $display(""ar[s0-:2]: %b"", ar[s0-:2]); + if (ar[s0-:2] !== 2\'b0x) begin + $display(""Failed ar[s0-:2], expected 2\'b0x, got %b"", ar[s0-:2]); + passed = 1\'b0; + end + + $display(""br[s0-:2]: %b"", br[s0-:2]); + if (br[s0-:2] !== 2\'b1x) begin + $display(""Failed br[s0-:2], expected 2\'b1x, got %b"", br[s0-:2]); + passed = 1\'b0; + end + + $display(""ar[s1-:2]: %b"", ar[s1-:2]); + if (ar[s1-:2] !== 2\'b0x) begin + $display(""Failed ar[s1-:2], expected 2\'b0x, got %b"", ar[s1-:2]); + passed = 1\'b0; + end + + $display(""br[s1-:2]: %b"", br[s1-:2]); + if (br[s1-:2] !== 2\'b1x) begin + $display(""Failed br[s1-:2], expected 2\'b1x, got %b"", br[s1-:2]); + passed = 1\'b0; + end + + $display(""ar[s2-:2]: %b"", ar[s2-:2]); + if (ar[s2-:2] !== 2\'b0x) begin + $display(""Failed ar[s2-:2], expected 2\'b0x, got %b"", ar[s2-:2]); + passed = 1\'b0; + end + + $display(""br[s2-:2]: %b"", br[s2-:2]); + if (br[s2-:2] !== 2\'b1x) begin + $display(""Failed br[s2-:2], expected 2\'b1x, got %b"", br[s2-:2]); + passed = 1\'b0; + end + + $display(""cr[s3-:2]: %b"", cr[s3-:2]); + if (cr[s3-:2] !== 2\'bx1) begin + $display(""Failed cr[s3-:2], expected 2\'bx1, got %b"", cr[s3-:2]); + passed = 1\'b0; + end + + $display(""dr[s3-:2]: %b"", dr[s3-:2]); + if (dr[s3-:2] !== 2\'bx0) begin + $display(""Failed dr[s3-:2], expected 2\'bx0, got %b"", dr[s3-:2]); + passed = 1\'b0; + end + + $display(""cr[s4-:2]: %b"", cr[s4-:2]); + if (cr[s4-:2] !== 2\'bx1) begin + $display(""Failed cr[s4-:2], expected 2\'bx1, got %b"", cr[s4-:2]); + passed = 1\'b0; + end + + $display(""dr[s4-:2]: %b"", dr[s4-:2]); + if (dr[s4-:2] !== 2\'bx0) begin + $display(""Failed dr[s4-:2], expected 2\'bx0, got %b"", dr[s4-:2]); + passed = 1\'b0; + end + + // Check continuous assignment R-value variable index down selects. + + if (res_a0 !== 2\'b0x) begin + $display(""Failed res_a0, expected 2\'b0x, got %b"", res_a0); + passed = 1\'b0; + end + + if (res_b0 !== 2\'b1x) begin + $display(""Failed res_b0, expected 2\'b1x, got %b"", res_b0); + passed = 1\'b0; + end + + if (res_a1 !== 2\'b0x) begin + $display(""Failed res_a1, expected 2\'b0x, got %b"", res_a1); + passed = 1\'b0; + end + + if (res_b1 !== 2\'b1x) begin + $display(""Failed res_b1, expected 2\'b1x, got %b"", res_b1); + passed = 1\'b0; + end + + if (res_a2 !== 2\'b0x) begin + $display(""Failed res_a2, expected 2\'b0x, got %b"", res_a2); + passed = 1\'b0; + end + + if (res_b2 !== 2\'b1x) begin + $display(""Failed res_b2, expected 2\'b1x, got %b"", res_b2); + passed = 1\'b0; + end + + if (res_c3 !== 2\'bx1) begin + $display(""Failed res_c3, expected 2\'bx1, got %b"", res_c3); + passed = 1\'b0; + end + + if (res_d3 !== 2\'bx0) begin + $display(""Failed res_d3, expected 2\'bx0, got %b"", res_d3); + passed = 1\'b0; + end + + if (res_c4 !== 2\'bx1) begin + $display(""Failed res_c4, expected 2\'bx1, got %b"", res_c4); + passed = 1\'b0; + end + + if (res_d4 !== 2\'bx0) begin + $display(""Failed res_d4, expected 2\'bx0, got %b"", res_d4); + passed = 1\'b0; + end + + // Check procedural L-value variable index down selects. + + res_ab = 4\'bxxxx; + res_ab[s0-:2] = 2\'b00; + if (res_ab !== 4\'bxxx0) begin + $display(""Failed res_ab[s0], expected 4\'bxxx0, got %b"", res_ab); + passed = 1\'b0; + end + + res_ab = 4\'bxxxx; + res_ab[s1-:2] = 2\'b00; + if (res_ab !== 4\'bxxx0) begin + $display(""Failed res_ab[s1], expected 4\'bxxx0, got %b"", res_ab); + passed = 1\'b0; + end + + res_ab = 4\'bxxxx; + res_ab[s2-:2] = 2\'b00; + if (res_ab !== 4\'bxxx0) begin + $display(""Failed res_ab[s2], expected 4\'bxxx0, got %b"", res_ab); + passed = 1\'b0; + end + + res_cd = 4\'bxxxx; + res_cd[s3-:2] = 2\'b00; + if (res_cd !== 4\'b0xxx) begin + $display(""Failed res_cd[s3], expected 4\'b0xxx, got %b"", res_cd); + passed = 1\'b0; + end + + res_cd = 4\'bxxxx; + res_cd[s4-:2] = 2\'b00; + if (res_cd !== 4\'b0xxx) begin + $display(""Failed res_cd[s4], expected 4\'b0xxx, got %b"", res_cd); + passed = 1\'b0; + end + + if (passed) $display(""Compare tests passed""); + end +endmodule +" +"module top; + reg pass, pass_f1, pass_f2, pass_f3, pass_f4, pass_f5; + reg [8*30:1] res; + + initial begin + pass = 1\'b1; + + // Verify that the initial scope is correct. + $swrite(res, ""%m""); + if (res != ""top"") begin + $display(""Failed initial, got \\""%0s\\"""", res); + pass = 1\'b0; + end + + // Test %m in a named begin. + begin : my_begin + $swrite(res, ""%m""); + if (res != ""top.my_begin"") begin + $display(""Failed named begin (1st), got \\""%0s\\"""", res); + pass = 1\'b0; + end + + begin : my_begin_begin + // Test %m in a nested named begin. + $swrite(res, ""%m""); + if (res != ""top.my_begin.my_begin_begin"") begin + $display(""Failed nested named begin, got \\""%0s\\"""", res); + pass = 1\'b0; + end + end + + $swrite(res, ""%m""); + if (res != ""top.my_begin"") begin + $display(""Failed named begin (2nd), got \\""%0s\\"""", res); + pass = 1\'b0; + end + + // Test a named fork inside a named begin. + pass_f1 = 1\'b1; + pass_f2 = 1\'b1; + fork : my_begin_fork + begin + $swrite(res, ""%m""); + if (res != ""top.my_begin.my_begin_fork"") begin + $display(""Failed after named begin/fork (1), got \\""%0s\\"""", res); + pass_f1 = 1\'b0; + end + end + begin + $swrite(res, ""%m""); + if (res != ""top.my_begin.my_begin_fork"") begin + $display(""Failed after named begin/fork (2), got \\""%0s\\"""", res); + pass_f2 = 1\'b0; + end + end + join + + pass = pass & pass_f1 & pass_f2; + + $swrite(res, ""%m""); + if (res != ""top.my_begin"") begin + $display(""Failed named begin (3rd), got \\""%0s\\"""", res); + pass = 1\'b0; + end + end + + // Verify that the scope is back to normal. + $swrite(res, ""%m""); + if (res != ""top"") begin + $display(""Failed after named begin, got \\""%0s\\"""", res); + pass = 1\'b0; + end + + // Test %m in a named fork. + pass_f1 = 1\'b1; + pass_f2 = 1\'b1; + pass_f3 = 1\'b1; + pass_f4 = 1\'b1; + pass_f5 = 1\'b1; + fork : my_fork + begin + $swrite(res, ""%m""); + if (res != ""top.my_fork"") begin + $display(""Failed after named fork (1), got \\""%0s\\"""", res); + pass_f1 = 1\'b0; + end + end + // Test a %m in a nested named begin. + begin : my_fork_begin + $swrite(res, ""%m""); + if (res != ""top.my_fork.my_fork_begin"") begin + $display(""Failed after named fork/begin, got \\""%0s\\"""", res); + pass_f4 = 1\'b0; + end + end + begin + $swrite(res, ""%m""); + if (res != ""top.my_fork"") begin + $display(""Failed after named fork (2), got \\""%0s\\"""", res); + pass_f2 = 1\'b0; + end + end + fork : my_fork_fork + begin + $swrite(res, ""%m""); + if (res != ""top.my_fork.my_fork_fork"") begin + $display(""Failed after named fork/fork, got \\""%0s\\"""", res); + pass_f2 = 1\'b0; + end + end + join + begin + $swrite(res, ""%m""); + if (res != ""top.my_fork"") begin + $display(""Failed after named fork (3), got \\""%0s\\"""", res); + pass_f3 = 1\'b0; + end + end + join + + pass = pass & pass_f1 & pass_f2 & pass_f3; + + // Verify that the scope is back to normal. + $swrite(res, ""%m""); + if (res != ""top"") begin + $display(""Failed final, got \\""%0s\\"""", res); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module main; + + // The declaration assignment within a task it not allowed + // in Verilog, but it is allowed in SystemVerilog. + task foo (input integer x, output integer y); + integer step = 3; + y = x + step; + endtask // foo + + integer\t a, b; + initial begin + a = 3; + foo(a, b); + if (b !== 6) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""PASSED""); + end + +endmodule // main +" +"module top; + reg [1:0] in; + subm sm [1:0](in); + + initial begin + // This should trigger instance 0. + in[0] = 0; + #1 in[0] = 1; + // This should trigger instance 1. + in[1] = 0; + #1 in[1] = 1; + end +endmodule + +module subm(input wire in); + always @(posedge in) $display(""In %m at %0t"", $time); +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Force stmt validation +// +// D: This code verifies the force statement +// D: It is intended to be self checking. +// + +module main (); + +reg working; +reg timer; + +initial +begin + timer = 1; + # 5; + timer = 0; + # 5 ; + timer = 1; + # 5 ; +end + + +initial + begin + working = 1; + #2 ; // Validate that force occurs + force timer = 0; + if( timer == 1) working = 0; + #10 ; // Validate that force stays in effect + if( timer == 1) working = 0; + end + +initial + begin + #20; + if(!working) + $display(""FAILED\ +""); + else + $display(""PASSED\ +""); + end + +endmodule +" +"module main; + + wire logic [3:0][7:0] foo; + + genvar idx; + for (idx = 0 ; idx <= 3 ; idx = idx+1) begin: test + test dut (.sum(foo[idx]), .a(idx)); + end + + logic [7:0] tmp; + initial begin + #0; // avoid time-zero race + for (tmp = 0 ; tmp <= 3 ; tmp = tmp+1) begin +\t //if ($bits(foo[tmp]) !== 8) begin +\t // $display(""FAILED -- $bits = %d"", $bits(foo[tmp])); +\t // $finish; +\t //end +\t if (foo[tmp] !== (tmp+8\'d5)) begin +\t $display(""FAILED -- foo[%d] = %b"", tmp, foo[tmp]); +\t $finish; +\t end + end + $display(""PASSED""); + end + +endmodule // main + +module test (output logic[7:0] sum, input logic [7:0]a); + + assign sum = a + 8\'d5; + +endmodule // test +" +"module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + always @(posedge clk) + if (rst) out <= 1\'d0; + else out <= ~inp; + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output wire out; + + (* my_module_instance = 99 *) + bar bar_instance (clk, rst, inp, out); + + initial begin + $display(""PASSED""); + end + +endmodule + +" +"module test(); + wire b; + a a( .b_buf(b), + .b (b)); +endmodule // test + + +module a(output b_buf, input b); + assign b_buf = 1'b0; +endmodule // a +" +"module top; + int mbx[$]; + + initial begin + $display(""mbx.size() == %0d"", mbx.size()); + wait(mbx.size()); + $display(""mbx.size() == %0d"", mbx.size()); + $display(""PASSED""); + end + + initial begin + #100 $display (""Push an item""); + mbx.push_back(1); + end +endmodule + +" +"module top; + // This should be valid. The Icarus compiler keeps these as negatives, but + // the run time doesn\'t support negative values. + enum bit signed [7:0] {rn = -1, yn = -2, gn = -3} nl; + integer val; + + initial begin + nl = rn; + $display(""First: %d"", nl); + nl = nl.next; + $display(""Second: %d"", nl); + nl = nl.next; + $display(""Third: %d"", nl); + nl = nl.next; + $display(""Wrapped: %d"", nl); + nl = nl.prev; + $display(""Wrapped: %d"", nl); + val = nl; + $display(""As integer: %d"", val); + end + + // This should be a signed value! + initial #1 $display(""Compile: "", rn); + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Initial readmemh function - length of data = array size. +// +// + +module main (); + +reg [7:0] array [0:7]; +reg error ; +reg [3:0] count; + +initial + begin + error = 0; + $readmemh(""ivltests/readmemh1a.dat"",array); + + for(count = 0; count <= 7; count = count + 1) + begin + if(array[count[2:0]] !== count) + begin + error = 1; + $display(""FAILED - array[count] == %h, s/b %h"", + array[count],count); + end + end + + if(error == 0) + $display(""PASSED\ +""); + $finish ; + end +endmodule +" +"/* + * This is derived from PR#938 in the test suite. + */ +`timescale 1ns/100ps + +module test; + + wire out; + reg A, B, select; + + prim_mux2 mux (out, B, A, select); + + reg [3:0] cnt; + initial begin + $display(""A B S out""); + for (cnt = 0 ; cnt <= \'b0111 ; cnt = cnt + 1) begin +\t A <= cnt[0]; +\t B <= cnt[1]; +\t select <= cnt[2]; + +\t #1 $display(""%b %b %b --> %b"", A, B, select, out); + end + end + +endmodule + + +primitive prim_mux2( output out, input in1, input in0, input select); + +table + +//in1 in0 select : out + 0 0 1 : 0; + 1 1 ? : 1; + 0 ? 1 : 0; + 1 ? 1 : 1; + ? 0 0 : 0; + ? 1 0 : 1; +endtable + +endprimitive +" +"module top; + + initial begin + $display(""Output a slash \\\\.""); + $display(""Output a double slash \\\\\\\\.""); + end +endmodule +" +"module test; + logic [7:0] i, x[], y[], z[]; + + + initial begin + x = new [4]; + + for (i = 0; i < 4; i = i + 1) x[i] = 1 + i; + y = x; + z = new [4](x); + for (i = 0; i < 4; i = i + 1) y[i] = 4 - i; + for (i = 0; i < 4; i = i + 1) z[i] = 8 - i; + // Expected output: + // 1 2 3 4 + // 4 3 2 1 + // 8 7 6 5 + $display(x[0],,x[1],,x[2],,x[3]); + $display(y[0],,y[1],,y[2],,y[3]); + $display(z[0],,z[1],,z[2],,z[3]); + end + +endmodule +" +"// +// Copyright (c) 1999 Peter Monta (pmonta@imedia.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// 9/7/99 - SDW - Modified by instantiating Peter\'s module into a +// self-checking structure. Moved bar=result inside +// begin clause in function. +// +// SDW - Validate function contains a register + +module main (); + +reg [1:0] val1; +reg\t val2; +reg\t error; + +function bar; + input [1:0] arg; + reg result; + begin + result = |arg; + bar = result; + end +endfunction + +initial + begin + error = 0; + val2 = bar(2\'b01); + if(val2 != 1) + begin + $display(""FAILED function 3.11F - register within a function(1)""); + error = 1; + end + val1 = 2\'b11 ; + val2 = bar(val1) ; + if(val2 != 1) + begin + $display(""FAILED function 3.11F - register within a function(2)""); + error = 1; + end + val2 = bar(2\'b00); + if(val2 != 0) + begin + $display(""FAILED function 3.11F - register within a function(2)""); + error = 1; + end + if(error == 0) + $display(""PASSED""); + end + +endmodule // main +" +"//**************************************************************************** +// +// MODULE : parameter_multiply_test +// +// DESCRIPTION : Test module to demonstrate parameter multiplication bug. +// +// AUTHOR : Brendan J Simon (brendan.simon@bigpond.com) +// +// DATE : Tuesday 6th January 2001. +// +// NOTES : It seems that Icarus Verilog 0.4 does not evaluate +// parameter multiplication properly. +// The code compiles OK, but gives a runtime error of: +// vpi_const.c:35: vpip_bits_to_dec_str: Assertion `nbits <= +// 8*sizeof(val)\' failed. +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: multiply in parameter +//**************************************************************************** + +module parameter_multiply_test; + +parameter foo_size = 4 * 8; + +reg [31:0] testv; +initial begin + testv = foo_size; + if(testv !== 32) + begin + $write(""foo_size = %d\ +"", testv); +\t $display(""FAILED""); + end + else + begin + $write(""foo_size = %d\ +"", testv); +\t $display(""PASSED""); + end + $finish; +end + + +endmodule + +//**************************************************************************** +// EOF : parameter_multiply_test +//**************************************************************************** +" +"module test ( +input\t\tclk_dma, +input\t\trst_dma_n, + +input\t\twr_valid, +input\t\twr_trans, +input\t\twr_flush, + +output\t\twr_ready); + +wire buf_wr_wstrb; + +assign buf_wr_wstrb = wr_ready && wr_valid; +assign wr_ready = wr_flush ; + +endmodule +" +"module top; + parameter weq1 = 2\'b01 ==? 2\'b01; + parameter weq2 = 2\'b01 ==? 2\'b00; + parameter weq3 = 2\'b0x ==? 2\'b00; + parameter weq4 = 2\'b00 ==? 2\'b0x; + parameter weq5 = 2\'b01 ==? 2\'b0x; + parameter weq6 = 2\'b0z ==? 2\'b0x; + parameter weq7 = 2\'b0x ==? 2\'b0x; + parameter weq8 = 2\'b00 ==? 2\'b0z; + parameter weq9 = 2\'b01 ==? 2\'b0z; + parameter weqa = 2\'b0z ==? 2\'b0z; + parameter weqb = 2\'b0x ==? 2\'b0z; + parameter weqc = 2\'bx0 ==? 2\'b00; + parameter weqd = 2\'bx1 ==? 2\'b00; + parameter weqe = 2\'b1x ==? 2\'b00; + parameter weqf = 3\'b100 ==? 2\'b00; + parameter wneq1 = 2\'b01 !=? 2\'b01; + parameter wneq2 = 2\'b01 !=? 2\'b00; + parameter wneq3 = 2\'b0x !=? 2\'b00; + parameter wneq4 = 2\'b00 !=? 2\'b0x; + parameter wneq5 = 2\'b01 !=? 2\'b0x; + parameter wneq6 = 2\'b0z !=? 2\'b0x; + parameter wneq7 = 2\'b0x !=? 2\'b0x; + parameter wneq8 = 2\'b00 !=? 2\'b0z; + parameter wneq9 = 2\'b01 !=? 2\'b0z; + parameter wneqa = 2\'b0z !=? 2\'b0z; + parameter wneqb = 2\'b0x !=? 2\'b0z; + parameter wneqc = 2\'bx0 !=? 2\'b00; + parameter wneqd = 2\'bx1 !=? 2\'b00; + parameter wneqe = 2\'b1x !=? 2\'b00; + parameter wneqf = 3\'b100 !=? 2\'b00; + + reg pass; + + initial begin + pass = 1\'b1; + + if (weq1 !== 1\'b1) begin + $display(""Failed: parameter 2\'b01 ==? 2\'b01 returned 1\'b%b not 1\'b1"", weq1); + pass = 1\'b0; + end + + if (weq2 !== 1\'b0) begin + $display(""Failed: parameter 2\'b01 ==? 2\'b00 returned 1\'b%b not 1\'b0"", weq2); + pass = 1\'b0; + end + + if (weq3 !== 1\'bx) begin + $display(""Failed: parameter 2\'b0x ==? 2\'b00 returned 1\'b%b not 1\'bx"", weq3); + pass = 1\'b0; + end + + if (weq4 !== 1\'b1) begin + $display(""Failed: parameter 2\'b00 ==? 2\'b0x returned 1\'b%b not 1\'b1"", weq4); + pass = 1\'b0; + end + + if (weq5 !== 1\'b1) begin + $display(""Failed: parameter 2\'b01 ==? 2\'b0x returned 1\'b%b not 1\'b1"", weq5); + pass = 1\'b0; + end + + if (weq6 !== 1\'b1) begin + $display(""Failed: parameter 2\'b0x ==? 2\'b0x returned 1\'b%b not 1\'b1"", weq6); + pass = 1\'b0; + end + + if (weq7 !== 1\'b1) begin + $display(""Failed: parameter 2\'b0z ==? 2\'b0x returned 1\'b%b not 1\'b1"", weq7); + pass = 1\'b0; + end + + if (weq8 !== 1\'b1) begin + $display(""Failed: parameter 2\'b00 ==? 2\'b0z returned 1\'b%b not 1\'b1"", weq8); + pass = 1\'b0; + end + + if (weq9 !== 1\'b1) begin + $display(""Failed: parameter 2\'b01 ==? 2\'b0z returned 1\'b%b not 1\'b1"", weq9); + pass = 1\'b0; + end + + if (weqa !== 1\'b1) begin + $display(""Failed: parameter 2\'b0x ==? 2\'b0z returned 1\'b%b not 1\'b1"", weqa); + pass = 1\'b0; + end + + if (weqb !== 1\'b1) begin + $display(""Failed: parameter 2\'b0z ==? 2\'b0z returned 1\'b%b not 1\'b1"", weqb); + pass = 1\'b0; + end + + if (weqc !== 1\'bx) begin + $display(""Failed: parameter 2\'bx0 ==? 2\'b00 returned 1\'b%b not 1\'bx"", weqc); + pass = 1\'b0; + end + + if (weqd !== 1\'b0) begin + $display(""Failed: parameter 2\'bx1 ==? 2\'b00 returned 1\'b%b not 1\'b0"", weqd); + pass = 1\'b0; + end + + if (weqe !== 1\'b0) begin + $display(""Failed: parameter 2\'b1x ==? 2\'b00 returned 1\'b%b not 1\'b0"", weqe); + pass = 1\'b0; + end + + if (weqf !== 1\'b0) begin + $display(""Failed: parameter 3\'b100 ==? 2\'b00 returned 1\'b%b not 1\'b0"", weqf); + pass = 1\'b0; + end + + if (wneq1 !== 1\'b0) begin + $display(""Failed: parameter 2\'b01 !=? 2\'b01 returned 1\'b%b not 1\'b0"", wneq1); + pass = 1\'b0; + end + + if (wneq2 !== 1\'b1) begin + $display(""Failed: parameter 2\'b01 !=? 2\'b00 returned 1\'b%b not 1\'b1"", wneq2); + pass = 1\'b0; + end + + if (wneq3 !== 1\'bx) begin + $display(""Failed: parameter 2\'b0x !=? 2\'b00 returned 1\'b%b not 1\'bx"", wneq3); + pass = 1\'b0; + end + + if (wneq4 !== 1\'b0) begin + $display(""Failed: parameter 2\'b00 !=? 2\'b0x returned 1\'b%b not 1\'b0"", wneq4); + pass = 1\'b0; + end + + if (wneq5 !== 1\'b0) begin + $display(""Failed: parameter 2\'b01 !=? 2\'b0x returned 1\'b%b not 1\'b0"", wneq5); + pass = 1\'b0; + end + + if (wneq6 !== 1\'b0) begin + $display(""Failed: parameter 2\'b0x !=? 2\'b0x returned 1\'b%b not 1\'b0"", wneq6); + pass = 1\'b0; + end + + if (wneq7 !== 1\'b0) begin + $display(""Failed: parameter 2\'b0z !=? 2\'b0x returned 1\'b%b not 1\'b0"", wneq7); + pass = 1\'b0; + end + + if (wneq8 !== 1\'b0) begin + $display(""Failed: parameter 2\'b00 !=? 2\'b0z returned 1\'b%b not 1\'b0"", wneq8); + pass = 1\'b0; + end + + if (wneq9 !== 1\'b0) begin + $display(""Failed: parameter 2\'b01 !=? 2\'b0z returned 1\'b%b not 1\'b0"", wneq9); + pass = 1\'b0; + end + + if (wneqa !== 1\'b0) begin + $display(""Failed: parameter 2\'b0x !=? 2\'b0z returned 1\'b%b not 1\'b0"", wneqa); + pass = 1\'b0; + end + + if (wneqb !== 1\'b0) begin + $display(""Failed: parameter 2\'b0z !=? 2\'b0z returned 1\'b%b not 1\'b0"", wneqb); + pass = 1\'b0; + end + + if (wneqc !== 1\'bx) begin + $display(""Failed: parameter 2\'bx0 !=? 2\'b00 returned 1\'b%b not 1\'bx"", wneqc); + pass = 1\'b0; + end + + if (wneqd !== 1\'b1) begin + $display(""Failed: parameter 2\'bx1 !=? 2\'b00 returned 1\'b%b not 1\'b1"", wneqd); + pass = 1\'b0; + end + + if (wneqe !== 1\'b1) begin + $display(""Failed: parameter 2\'b1x !=? 2\'b00 returned 1\'b%b not 1\'b1"", wneqe); + pass = 1\'b0; + end + + if (wneqf !== 1\'b1) begin + $display(""Failed: parameter 3\'b100 !=? 2\'b00 returned 1\'b%b not 1\'b1"", wneqf); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Test some multiply values for an 18*18-->36 multiply. + */ + +module main; + + wire [35:0] p; + reg [17:0] a, b; + reg\t clk, ce, reset; + + parameter MAX_TRIALS = 1000; + integer idx; + + MULT18X18S dut (p, a, b, clk, ce, reset); + + initial begin + clk <= 0; + ce <= 1; + reset <= 1; + a <= 0; + b <= 0; + #5 clk <= 1; + #5 clk <= 0; + + if (p !== 36\'h0) begin +\t $display(""FAILED -- reset p=%h"", p); +\t $finish; + end + + reset <= 0; + + /* A magical value I know failed at one time. */ + a <= 18\'h3ff82; + b <= 18\'h04000; + + #5 clk <= 1; + #5 clk <= 0; + + if (p !== 36\'hfffe08000) begin +\t $display(""FAILED -- %h * %h --> %h"", a, b, p); +\t $finish; + end + + for (idx = 0 ; idx < MAX_TRIALS ; idx = idx + 1) begin +\t a <= $random; +\t b <= $random; + +\t #5 clk <= 1; +\t #5 clk <= 0; + +\t if ($signed(p) !== ($signed(a) * $signed(b))) begin +\t $display(""FAILED == %h * %h --> %h"", a, b, p); +\t $finish; +\t end + end // for (idx = 0 ; idx < `MAX_TRIALS ; idx = idx + 1) + + $display(""PASSED""); + end // initial begin + +endmodule // main + +module MULT18X18S (output reg [35:0] P, +\t\t input [17:0] A, +\t\t input [17:0] B, +\t\t input C, CE, R); + + wire [35:0] a_in = { {18{A[17]}}, A[17:0] }; + wire [35:0] b_in = { {18{B[17]}}, B[17:0] }; + wire [35:0] p_in; + reg [35:0] p_out; + + assign p_in = a_in * b_in; + + always @(posedge C) + if (R) + P <= 36\'b0; + else if (CE) + P <= p_in; + + +endmodule +" +"// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test a case when two variables with the same name are used in two +// different processes. + +module vhdl_process_scope_test; +vhdl_process_scope dut(); + +initial begin + #0; + // the test takes place in the dut processes + $display(""PASSED""); +end +endmodule + +" +"module test; + + reg [63:0] out; + reg [5:0] in; + + integer i = 0; + + reg failed = 0; + + initial begin + for (i = 0; i < 64; i = i + 1) begin + in = i; + out = 2 ** in; + $display(""%d: %b"", i, out); + if (out !== 64\'d1 << i) + failed = 1; + end + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); + end +endmodule +" +"// pr1645277 + + module test; + initial main; + + task main; + integer foo; + begin +\t foo = 0; +\t while(foo < 5) begin: inner +\t foo = foo + 1; +\t end +\t $write(""expected %d; got %d\ +"", 5, foo); + end + endtask + endmodule +" +"/* + * 1364-2001 19.2 ""When the `default_nettype is set to none, all nets must be + * explicitly declared. If a net is not explicitly declared, an error is + * generated."" + */ + +module ok; +reg a; +assign b=a; +endmodule + +`default_nettype none + +module bad; +reg a; +assign b=a; +endmodule +" +"module top; + reg y, a, b, flip, hidden; + reg pass; + + function f_and (input i1, i2); + reg partial; + begin + partial = i1 & i2; + f_and = partial | hidden; + end + endfunction + + reg intr; + always_comb begin + intr = flip; + y = f_and(a, b) ^ intr; + end + + initial begin + pass = 1\'b1; + + flip = 1\'b0; + hidden = 1\'b0; + a = 1\'b0; + b = 1\'b0; + #1; + if (y !== 1\'b0) begin + $display(""FAILED: a=1\'b0, b=1\'b0, hidden=1\'b0, expected 1\'b0, got %b"", y); + pass = 1\'b0; + end + + a = 1\'b0; + b = 1\'b1; + #1; + if (y !== 1\'b0) begin + $display(""FAILED: a=1\'b0, b=1\'b1, hidden=1\'b0, expected 1\'b0, got %b"", y); + pass = 1\'b0; + end + + a = 1\'b1; + b = 1\'b0; + #1; + if (y !== 1\'b0) begin + $display(""FAILED: a=1\'b1, b=1\'b0, hidden=1\'b0, expected 1\'b0, got %b"", y); + pass = 1\'b0; + end + + a = 1\'b1; + b = 1\'b1; + #1; + if (y !== 1\'b1) begin + $display(""FAILED: a=1\'b1, b=1\'b1, hidden=1\'b0, expected 1\'b1, got %b"", y); + pass = 1\'b0; + end + + hidden = 1\'b0; + a = 1\'b0; + b = 1\'b0; + #1; + if (y !== 1\'b0) begin + $display(""FAILED: a=1\'b0, b=1\'b0, hidden=1\'b0, expected 1\'b0, got %b"", y); + pass = 1\'b0; + end + + hidden = 1\'b1; + a = 1\'b0; + b = 1\'b0; + #1; + if (y !== 1\'b1) begin + $display(""FAILED: a=1\'b0, b=1\'b0, hidden=1\'b1, expected 1\'b1, got %b"", y); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module top; + parameter wid = 9; + + reg [31:0] rpass; + reg [31:0] rfail; + + initial begin + rpass = {(wid-8){ 8'b0}}; // This will pass + rfail = {(wid-16){8'b0}}; // and this will fail. + end +endmodule +" +"module top; + reg passed; + + reg signed[31:0] m_one, m_two, zero, one, two; + + // Both argument positive. + reg signed[31:0] rem; + wire signed[31:0] wrem = one % two; + + // First argument negative. + reg signed[31:0] rem1n; + wire signed[31:0] wrem1n = m_one % two; + + // Second argument negative. + reg signed[31:0] rem2n; + wire signed[31:0] wrem2n = one % m_two; + + // Both arguments negative. + reg signed[31:0] rembn; + wire signed[31:0] wrembn = m_one % m_two; + + // Divide by zero. + reg signed[31:0] remd0; + wire signed[31:0] wremd0 = one % zero; + + initial begin + passed = 1\'b1; + m_one = 32\'hffffffff; + m_two = 32\'hfffffffe; + zero = 32\'h00000000; + one = 32\'h00000001; + two = 32\'h00000002; + + #1; + // Both positive. + if (wrem !== 32\'h00000001) begin + $display(""Failed: CA remainder, expected 32\'h00...01, got %h"", + wrem); + passed = 1\'b0; + end + + rem = one % two; + if (rem !== 32\'h00000001) begin + $display(""Failed: remainder, expected 32\'h00...01, got %h"", + rem); + passed = 1\'b0; + end + + // First negative. + if (wrem1n !== 32\'hffffffff) begin + $display(""Failed: CA remainder (1n), expected 32\'hff...ff, got %h"", + wrem1n); + passed = 1\'b0; + end + + rem1n = m_one % two; + if (rem1n !== 32\'hffffffff) begin + $display(""Failed: remainder (1n), expected 32\'hff...ff, got %h"", + rem1n); + passed = 1\'b0; + end + + // Second negative. + if (wrem2n !== 32\'h00000001) begin + $display(""Failed: CA remainder (2n), expected 32\'h00...01, got %h"", + wrem2n); + passed = 1\'b0; + end + + rem2n = one % m_two; + if (rem2n !== 32\'h00000001) begin + $display(""Failed: remainder (2n), expected 32\'h00...01, got %h"", + rem2n); + passed = 1\'b0; + end + + // Both negative. + if (wrembn !== 32\'hffffffff) begin + $display(""Failed: CA remainder (bn), expected 32\'hff...ff, got %h"", + wrembn); + passed = 1\'b0; + end + + rembn = m_one % m_two; + if (rembn !== 32\'hffffffff) begin + $display(""Failed: remainder (bn), expected 32\'hff...ff, got %h"", + rembn); + passed = 1\'b0; + end + + // Divide by zero. + if (wremd0 !== 32\'hxxxxxxxx) begin + $display(""Failed: CA remainder (d0), expected 32\'hxx...xx, got %h"", + wremd0); + passed = 1\'b0; + end + + remd0 = one % zero; + if (remd0 !== 32\'hxxxxxxxx) begin + $display(""Failed: remainder (d0), expected 32\'hxx...xx, got %h"", + remd0); + passed = 1\'b0; + end + + if (passed) $display(""PASSED""); + end +endmodule +" +"module main; + + parameter use_wid = 4; + + reg [use_wid-1:0] d; + wire [use_wid-1:0] q; + reg\t\t clk; + + B #(.wid(use_wid)) dut (.Q(q), .D(d), .C(clk)); + + initial begin + clk = 0; + d = 4\'b0000; + + #1 clk = 1; + #1 clk = 0; + + if (q !== 4\'b0000) begin +\t $display(""FAILED -- d=%b, q=%b"", d, q); +\t $finish; + end + + d = 4\'b1111; + #1 clk = 1; + #1 clk = 0; + + if (q !== 4\'b1111) begin +\t $display(""FAILED -- d=%b, q=%b"", d, q); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main + +/* + * although the wid paramter is default to 3 in this module, the point + * of this test is to have the instantiating module (main) give a + * different value and have that value properly handlued in all the + * situations of this module. + */ +module B + #(parameter wid = 3) + (output [wid-1:0] Q, + input [wid-1:0] D, + input C); + + // the override from main will cause this to be a width of 4. + prim U [wid-1:0] (Q, D, C); + //prim U [wid-1:0] (.Q(Q), .D(D), .C(C)); + +endmodule // B + +module prim(output reg Q, input D, C); + + always @(posedge C) + Q <= D; + +endmodule // prim +" +"/* talu - a verilog test, + * illustrating problems I had in fragments of an ALU from an 8-bit micro + */ + +module talu; + reg error; + + reg [7:0] a; + reg [7:0] b; + reg cin; + reg [1:0] op; + + wire cout; + wire [7:0] aluout; + + alu alu_m(a, b, cin, op, aluout, cout); + + initial begin + error = 0; + + // add + op=\'b00; cin=\'b0; a=\'h0; b=\'h0; + #2 if({cout, aluout} != 9\'h000) begin +\t $display($time, "" FAILED %b %b %h %h %b %h"", op, cin, a, b, cout, aluout); +\t error = 1; + end + + // add1 + op=\'b01; cin=\'b0; a=\'h01; b=\'h01; + #2 if({cout, aluout} != 9\'h103) begin +\t $display($time, "" FAILED %b %b %h %h %b %h"", op, cin, a, b, cout, aluout); +\t error = 1; + end + + // and + op=\'b10; cin=\'b0; a=\'h16; b=\'h0F; + #2 if({cout, aluout} != 9\'h006) begin +\t $display($time, "" FAILED %b %b %h %h %b %h"", op, cin, a, b, cout, aluout); +\t error = 1; + end + op=\'b10; cin=\'b0; a=\'h28; b=\'hF7; + #2 if({cout, aluout} != 9\'h020) begin +\t $display($time, "" FAILED %b %b %h %h %b %h"", op, cin, a, b, cout, aluout); +\t error = 1; + end + + // genbit + op=\'b11; cin=\'b0; a=\'h00; b=\'h03; + #2 if({cout, aluout} != 9\'h008) begin +\t $display($time, "" FAILED %b %b %h %h %b %h"", op, cin, a, b, cout, aluout); +\t error = 1; + end + op=\'b11; cin=\'b0; a=\'h00; b=\'h00; + #2 if({cout, aluout} != 9\'h001) begin +\t $display($time, "" FAILED %b %b %h %h %b %h"", op, cin, a, b, cout, aluout); +\t error = 1; + end + /* tests are incomplete - doesn\'t compile yet on ivl */ + + + if(error == 0) +\t $display(""PASSED""); + $finish; + + end + +endmodule + +/* + * fragments of an ALU from an 8-bit micro + */ + +module alu(Aval, Bval, cin, op, ALUout, cout); + input [7:0]\tAval; + input [7:0]\tBval; + input\tcin; + input [1:0]\top; + output\tcout; + output [7:0]\tALUout; + + reg\t\tcout; + reg [7:0]\tALUout; + + always @(Aval or Bval or cin or op) begin + case(op) +\t2\'b00 : {cout, ALUout} = Aval + Bval; +\t2\'b10 : {cout, ALUout} = {1\'b0, Aval & Bval}; + +// C++ compilation troubles with both of these: +\t2\'b01 : {cout, ALUout} = 9\'h100 ^ (Aval + Bval + 9\'h001); +\t2\'b11 : {cout, ALUout} = {1\'b0, 8\'b1 << Bval}; + +//\t2\'b01 : {cout, ALUout} = 9\'h000; +//\t2\'b11 : {cout, ALUout} = 9\'h000; + endcase + end // always @ (Aval or Bval or cin or op) + +endmodule + +/* Copyright (C) 1999 Stephen G. Tell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ +" +" + +module test + (output reg [1:0] foo, + input wire [1:0] addr, + input wire\t in0, in1, + input wire\t en0, en1 + /* */); + + localparam foo_default = 2\'b00; + always @* + begin +\tfoo = foo_default; +\tcase (addr) +\t 0: if (en0) foo[0] = in0; +\t 1: if (en1) foo[1] = in1; +\t 2: foo = {in1, in0}; +\t default: foo = 0; +\tendcase + end + +endmodule // test + +module main; + + wire [1:0] foo; + reg [1:0] addr; + reg\t in0, in1; + reg\t en0, en1; + + test dut(.foo(foo), .addr(addr), .in0(in0), .in1(in1), .en0(en0), .en1(en1)); + + initial begin + in0 = 1; + in1 = 1; + en0 = 1; + en1 = 1; + + addr = 3; + #1 if (foo !== 2\'b00) begin +\t $display(""FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b"", +\t\t foo, in1, in0, en1, en0, addr); +\t $finish; + end + + addr = 0; + #1 if (foo !== 2\'b01) begin +\t $display(""FAILED -- foo=%b, in=%b%b, addr=%b"", foo, in1, in0, addr); +\t $finish; + end + + addr = 1; + #1 if (foo !== 2\'b10) begin +\t $display(""FAILED -- foo=%b, in=%b%b, addr=%b"", foo, in1, in0, addr); +\t $finish; + end + + addr = 2; + #1 if (foo !== 2\'b11) begin +\t $display(""FAILED -- foo=%b, in=%b%b, addr=%b"", foo, in1, in0, addr); +\t $finish; + end + + en0 = 0; + en1 = 0; + + addr = 3; + #1 if (foo !== 2\'b00) begin +\t $display(""FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b"", +\t\t foo, in1, in0, en1, en0, addr); +\t $finish; + end + + addr = 0; + #1 if (foo !== 2\'b00) begin +\t $display(""FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b"", +\t\t foo, in1, in0, en1, en0, addr); +\t $finish; + end + + addr = 1; + #1 if (foo !== 2\'b00) begin +\t $display(""FAILED -- foo=%b, in=%b%b, addr=%b"", foo, in1, in0, addr); +\t $finish; + end + + addr = 2; + #1 if (foo !== 2\'b11) begin +\t $display(""FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b"", +\t\t foo, in1, in0, en1, en0, addr); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"module bug; + +reg [4:0] a = 5\'b01010; + +reg failed = 0; + +initial begin + foreach (a[i]) begin + $display(""Value of a[%0d]=%0d"", i, a[i]); + if (a[i] !== i[0]) failed = 1; + end + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"/* + * Copyright (c) 2001 Uwe Bonnes + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +`define ADC_DATA_OFFSET 5 +`define ADC_CHANELS 8*48 +//`define ADC_CHANELS 348 + +module mymod (out1,out2,state,reset); + + input [8:0] state; + input reset; + output out1,out2; + assign out1 = (state > `ADC_DATA_OFFSET) ? 1 : 0; + assign out2 = (state > `ADC_CHANELS + `ADC_DATA_OFFSET +1)|| (reset); + +endmodule // mymod + +module t; + reg [8:0] state; + reg reset; + wire out1,out2; + + mymod m1 (out1,out2,state,reset); + + initial + begin + //$timeformat(-9,0,""ns"",5); + $display("" TIME:state:out1:out2""); + $monitor(""%7t:%5d:%3d:%3d"",$time,state,out1,out2); + state =0; + reset = 0; + #10 + reset=1; + #20 + reset=0; + #5110 + $finish(0); + end + always + begin + #10 + if (reset) + state = 0; + else + state=state+1; + end +endmodule // t +" +"module test; + + +reg clock; +initial begin +clock = 0; +forever #5 clock = !clock; +end + +wire [0:31] read_data1 [0:7]; +reg [0:31] read_data2 [0:7]; + + +assign read_data1[0] = 0; +assign read_data1[1] = 1; +assign read_data1[2] = 2; +assign read_data1[3] = 3; +assign read_data1[4] = 4; +assign read_data1[5] = 5; +assign read_data1[6] = 6; +assign read_data1[7] = 7; + + +always @(posedge clock) begin: we +reg [3:0] x; +for (x=0; x<8; x=x+1) begin +read_data2[x[2:0]] <= read_data1[x[2:0]]; +end +end + +always @(posedge clock) begin: wg +integer i; +#1 for (i=0; i<8; i=i+1) begin +$write(""%x "", read_data2[i]); +end +$display; +end + +initial begin +#20; +$finish(0); +end + + +endmodule // test +" +"module task_time_arg; + reg pass; + integer result; + + task test_it1; + realtime tmp; + begin + tmp = $realtime; + go_busy(tmp); + end + endtask + + task test_it2; + go_busy($realtime); + endtask + + task go_busy; + input delay; + integer delay; + result = delay; + endtask // go_busy + + initial begin + pass = 1\'b1; + #6 + test_it1; + if (result !== 6) begin + $display(""Failed: testit1, expected 6, got %d"", result); + pass = 1\'b0; + end + + #1 + test_it2; + if (result !== 7) begin + $display(""Failed: testit2, expected 7, got %d"", result); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end + +endmodule +" +"/********************************************************************** + * $my_pow example -- Verilog HDL test bench. + * + * Verilog test bench to test the $my_pow PLI application. + * + * For the book, ""The Verilog PLI Handbook"" by Stuart Sutherland + * Copyright 1999 & 2001, Kluwer Academic Publishers, Norwell, MA, USA + * Contact: www.wkap.il + * Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA + * Contact: www.sutherland-hdl.com + *********************************************************************/ +`timescale 1ns / 1ns +module test; + reg [32:0] result; + reg a, b; + + buf i1 (c,a); + initial + begin + $display(""Start simulation pow_test.v""); + a = 1; + b = 0; + /* Test $my_pow with invalid arguments */ + /* These invalid calls will need to be commented out to use */ + /* the valid calls to $my_pow in simulation */ +// #1 result = $my_pow; +// #1 result = $my_pow(); +// #1 result = $my_pow(1); +// #1 result = $my_pow(2,i1); +// #1 result = $my_pow(1,2,3); + + /* Test $my_pow with valid values */ + #1 $display(""$my_pow(2,3) returns %d"", $my_pow(2,3)); + #1 result = $my_pow(a,b); + #1 $display(""$my_pow(a,b) returns %d (a=%d b=%d)"", result, a, b); +// #1 $stop; + #1 $finish(0); + end + +endmodule +/*********************************************************************/ +" +"module top; + reg [4:0]cntr; + wire done; + wire allone; + + // A delayed comparison is only 1 bit wide. If this does not crash + // the run time then the compiler is producing correct code. + assign #1 done = cntr == \'d7; + // The same for a reduction. + assign #1 allone = &cntr; + + initial $display(""PASSED""); +endmodule +" +"/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program tests the ability to take bit and part selects + * of parameters. This is actually not legal in Verilog, but + * Icarus Verilog supports it anyhow, as do many (most?) other + * Verilog compilers. + */ + +module main; + + parameter vec = 16\'b0000_1001_0111_1010; + + initial begin + if (vec[0] !== 0) begin +\t $display(""FAILED -- %b[0] !== 0"", vec); +\t $finish; + end + + if (vec[1] !== 1) begin +\t $display(""FAILED -- %b[1] !== 1"", vec); +\t $finish; + end + + if (vec[3:1] !== 3\'b101) begin +\t $display(""FAILED -- %b[3:1] !== b101"", vec); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule +" +"module bug(); + +function signed [31:0] fpreal( + input real in +); + +real m; +real r; + +begin + m = 1 << 16; + r = in * m; + fpreal = $rtoi(r); +end + +endfunction + +function signed [31:0] fpdiv( + input signed [31:0] a, + input signed [31:0] b +); + +reg signed [47:0] r; + +begin + r = a << 16; + fpdiv = r / b; +end + +endfunction + +function signed [31:0] fpmul( + input signed [31:0] a, + input signed [31:0] b +); + +reg signed [47:0] r; + +begin + r = a * b; + fpmul = r >>> 16; +end + +endfunction + +function signed [31:0] fppow( + input signed [31:0] a, + input real b +); + +real ar; +real r; + +begin + ar = $itor(a) / (1 << 16); + r = ar ** b; + fppow = fpreal(r); +end + +endfunction + +wire signed [31:0] a = 1 << 16; +wire signed [31:0] b = 4 << 16; + +wire signed [31:0] c = fpdiv(a, b); +wire signed [31:0] d = fppow(c, 2.0); + +initial begin + #1 $display(""(%0f / %0f)**2.0 = %0f"", a / 65536.0, b / 65536.0, d / 65536.0); + if (d === 32\'h0000_1000) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign (strong1,weak0) value1[3:0] = 4\'b1010; + +cmos buffer[7:0](value2, value1, 1\'b1, 1\'b0); + +assign (strong1,weak0) value2 = 8\'b00110011; + +initial begin + #2 $display(""%b %b"", value1, value2); + if (value2 === 8\'b00111011) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module negvalue; + + reg[7:0]reg1; + + initial begin + reg1 <= -13 +21 ; + #1 + reg1 <= 0 -13 +21 ; + end + + always@(reg1)begin + $display(""%d (should be 8)"",reg1); + end + +endmodule +" +" +module main; + + localparam width = 8; + + reg clk; + reg [1:0] addr; + logic [width-1:0] data [0:3]; + + reg [width-1:0] Q; + + // Does SystemVerilog support continuous assignment + // of unpacked arrays? I think it does, but the LRM + // is really not clear on this. + wire [width-1:0] data_x[0:3]; + assign data_x = data; + always @(posedge clk) + Q <= data_x[addr]; + + reg [2:0]\t idx; + initial begin + clk = 0; + data[0] = 0; + data[1] = 1; + data[2] = 2; + data[3] = 3; + addr = 0; + + for (idx = 0 ; idx < 4 ; idx += 1) begin +\t clk = 0; +\t #1 addr = idx[1:0]; +\t #1 clk = 1; +\t #1 if (Q !== data[addr]) begin +\t $display(""FAILED -- data[%0d]==%h, Q==%h"", addr, data[addr], Q); +\t $finish; +\t end + end + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"/* + * Copyright (c) 1999 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +primitive BUFG ( O, I ); + output O; + input I; + table + 0 : 0 ; + 1 : 1 ; + endtable +endprimitive + +module main; + wire out; + reg in; + + BUFG bg(out, in); + + initial begin + in = 0; + #1 if (out != 0) begin +\t $display(""FAILED -- %b != 0"", out); +\t $finish; + end + in = 1; + #1 if (out != 1) begin +\t $display(""FAILED -- %b != 1"", out); +\t $finish; + end + $display(""PASSED""); + end +endmodule +" +"/* + * Copyright (c) 2000 Peter monta (pmonta@pacbell.net) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module main; + + function [3:0] foo; + input [3:0] x; + begin + foo = ~x + 1; + end + endfunction + + reg [3:0] x; + wire [3:0] y; + + assign y = foo(x); + + initial begin + x = 4\'b0110; + #1; + if (y==4\'b1010) + $display(""PASSED""); + else + $display(""FAILED""); + end + +endmodule +" +"`timescale 100 ps / 10 ps + +module test; + reg cdn, cp, d; + wire qr, qp; + + initial begin + $timeformat(-9, 2, "" ns"", 9); + $monitor(""%t - cdn=%b, cp=%b, d=%b, qr=%b, qp=%b"",$time,cdn,cp,d,qr,qp); + // Reset the FF. + cp = 0; d = 1; + #100 cdn = 0; + #100 cdn = 1; + // Toggle in some data. + #100 cp = 1; + #100 cp = 0; d = 0; + #100 cp = 1; + #100 cp = 0; d = 1; + #100 cp = 1; + end + + dff_rtl dutr(qr, d, cp, cdn); // This one works fine. + dff_prm dutp(qp, d, cp, cdn); // This one has no delay. +endmodule + +// The RTL version appears to work fine. +module dff_rtl (q, d, cp, cdn); + output q; + input d; + input cp; + input cdn; + + reg qi; + + always @(posedge cp or negedge cdn) begin + if (~cdn) qi <= 1\'b0; + else qi <= d; + end + buf (q, qi); + + specify + specparam tpd_cp_q_lh = 6; + specparam tpd_cp_q_hl = 7; + specparam tpd_cdn_q_lh = 0; + specparam tpd_cdn_q_hl = 3; + + if (cdn) (posedge cp => (q +: d)) = (tpd_cp_q_lh, tpd_cp_q_hl); + (negedge cdn => (q +: 1\'b0)) = (tpd_cdn_q_lh, tpd_cdn_q_hl); + endspecify +endmodule + +// The primitive version has no delay. +module dff_prm (q, d, cp, cdn); + output q; + input d, cp, cdn; + + UDP_DFF G3(q, d, cp, cdn); + + specify + specparam tpd_cp_q_lh = 6; + specparam tpd_cp_q_hl = 7; + specparam tpd_cdn_q_lh = 0; + specparam tpd_cdn_q_hl = 3; + + if (cdn) (posedge cp => (q +: d)) = (tpd_cp_q_lh, tpd_cp_q_hl); + (negedge cdn => (q +: 1\'b0)) = (tpd_cdn_q_lh, tpd_cdn_q_hl); + endspecify + +endmodule + +// This is overly simplistic, but it works for this example. +primitive UDP_DFF(q, d, cp, cdn); + output q; + reg q; + input d, cp, cdn; + + table + // d cp cdn q0 q + * ? ? : ? : - ; + ? n ? : ? : - ; + 0 r 1 : ? : 0 ; + 1 r 1 : ? : 1 ; + ? ? 0 : ? : 0 ; + ? ? p : ? : - ; + endtable +endprimitive +" +"module dut; + +integer id; + +endmodule + +module test; + +dut inst[4]; + +integer i; + +reg failed = 0; + +initial begin + inst[0].id = 0; + inst[1].id = 1; + inst[2].id = 2; + inst[3].id = 3; + + if (inst[0].id !== 0) failed = 1; + if (inst[1].id !== 1) failed = 1; + if (inst[2].id !== 2) failed = 1; + if (inst[3].id !== 3) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module top; + // The array code does not currently work because we need &APV<>! + // Both &PV<> and &APV<> (when implemented) need to have bit + // specific value change callbacks to function correctly. + reg [7:0] array [1:0]; + reg [7:0] bs, ps; + integer idx; + + initial begin + bs = 8\'b0; + ps = 8\'b0; + array[0] = 8\'b0; + $monitor($time,"" BS = "", bs[1], "", PS = "", ps[2:1], "", AR = "", array[0][1]); + + // This should only trigger the $monitor when bit 1 changes. + for (idx = 0; idx < 8 ; idx = idx + 1) begin + #1 bs[idx] = 1\'b1; + end + + // This should only trigger the $monitor when bit 1 or 2 changes. + for (idx = 0; idx < 8 ; idx = idx + 1) begin + #1 ps[idx] = 1\'b1; + end + + // This should only trigger the $monitor when bit 1 of array[0] changes.. + for (idx = 0; idx < 8 ; idx = idx + 1) begin + #1 array[0][idx] = 1\'b1; + end + end +endmodule +" +"`begin_keywords ""1364-2005"" +`timescale 1ns / 1ns + +module gentest; + +reg [7:0] a=0, b=0; +wire co; +wire [7:0] result; + +adder work(a, b, 1\'b0, result, co); + +integer cc; +initial begin +\tfor (cc=0; cc<10; cc=cc+1) begin +\t\ta=a+1; +\t\t#10; +\t\t$display(""%d %d %d"", a, b, result); +\t\tb=result; +\tend +\tif (b==55) $display(""PASSED""); +\telse $display(""FAIL""); +end + +endmodule + +module adder(a, b, ci, out, co); +parameter SIZE=8; +input [SIZE-1:0] a; +input [SIZE-1:0] b; +input ci; +output [SIZE-1:0] out; +output co; + +wire [SIZE:0] c; +assign c[0] = ci; +assign co = c[SIZE]; +`ifdef NOGENERATE +\tadd1 bit0(a[0], b[0], c[0], out[0], c[0+1]); +\tadd1 bit1(a[1], b[1], c[1], out[1], c[1+1]); +\tadd1 bit2(a[2], b[2], c[2], out[2], c[2+1]); +\tadd1 bit3(a[3], b[3], c[3], out[3], c[3+1]); +\tadd1 bit4(a[4], b[4], c[4], out[4], c[4+1]); +\tadd1 bit5(a[5], b[5], c[5], out[5], c[5+1]); +\tadd1 bit6(a[6], b[6], c[6], out[6], c[6+1]); +\tadd1 bit7(a[7], b[7], c[7], out[7], c[7+1]); +`else +genvar i; +generate for(i=0; i 1) ? factorial(n - 1) * n : n; +end + +endfunction + +reg [15:0] r1; +reg [15:0] r2; +reg [15:0] r3; + +initial begin + fork + r1 = factorial(3); + r2 = factorial(4); + r3 = factorial(5); + join + $display(""factorial 3 = %0d"", r1); + $display(""factorial 4 = %0d"", r2); + $display(""factorial 5 = %0d"", r3); +end + +wire [15:0] r4; +wire [15:0] r5; +wire [15:0] r6; + +assign r4 = factorial(6); +assign r5 = factorial(7); +assign r6 = factorial(8); + +initial begin + #1; + $display(""factorial 6 = %0d"", r4); + $display(""factorial 7 = %0d"", r5); + $display(""factorial 8 = %0d"", r6); +end + +endmodule +" +" +module DFF + (output reg Q0, + output reg [1:0] Q1, + input wire D0, + input wire [1:0] D1, + input wire CLK, + input wire RST + /* */); + + always @(posedge CLK or posedge RST) + if (RST) begin +\tQ0 <= 0; +\tQ1 <= 0; + end else begin +\tQ0 <= D0; +\tQ1 <= D1; + end + +endmodule // dut + +module main; + + wire q0; + wire [1:0] q1; + reg\t d0, clk, rst; + reg [1:0] d1; + + DFF dut (.Q0(q0), .Q1(q1), .D0(d0), .D1(d1), .CLK(clk), .RST(rst)); + + initial begin + clk <= 1; + d0 <= 0; + d1 <= 2; + + #1 rst <= 1; + #1 if (q0 !== 1\'b0 || q1 !== 1\'b0) begin +\t $display(""FAILED -- RST=%b, Q0=%b, Q1=%b"", rst, q0, q1); +\t $finish; + end + + #1 rst <= 0; + #1 if (q0 !== 1\'b0 || q1 !== 1\'b0) begin +\t $display(""FAILED -- RST=%b, Q0=%b, Q1=%b"", rst, q0, q1); +\t $finish; + end + + #1 clk <= 0; + #1 clk <= 1; + #1 if (q0 !== d0 || q1 !== d1) begin +\t $display(""FAILED -- Q0=%b Q1=%b, D0=%b D1=%b"", q0, q1, d0, d1); +\t $finish; + end + + $display(""PASSED""); + $finish; + end + +endmodule // main +" +"package pkg1; + +typedef enum logic [1:0] { + R0 = 2\'b00, + R1 = 2\'b01, + R2 = 2\'b10, + R3 = 2\'b11 +} reg_t; + +endpackage + +module dut(input pkg1::reg_t r1, output pkg1::reg_t r3); + +import pkg1::*; + +reg_t r2; + +always_comb + r2 = r1; + +always_comb + r3 = r2; + +endmodule + + +module test(); + +import pkg1::*; + +reg_t v1; +reg_t v2; + +dut dut(v1, v2); + +reg failed = 0; + +initial begin + v1 = R0; + #1 $display(""%h %h"", v1, v2); + if (v2 !== R0) failed = 1; + v1 = R1; + #1 $display(""%h %h"", v1, v2); + if (v2 !== R1) failed = 1; + v1 = R2; + #1 $display(""%h %h"", v1, v2); + if (v2 !== R2) failed = 1; + v1 = R3; + #1 $display(""%h %h"", v1, v2); + if (v2 !== R3) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"/* + * integer3gt - a verilog test for integer greater-than conditional > + * + * Copyright (C) 1999 Stephen G. Tell + * Portions inspired by qmark.v by Steven Wilson (stevew@home.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ + +module integer3gt; + + integer a; + integer b; + reg\t error; + + initial begin + error = 0; + + a = 1; + if(a > 2) begin +\t $display(""FAILED 1 > 2""); +\t error = 1; + end // if (a < 2) + + a = 2; + if(a > 2) begin +\t $display(""FAILED 2 > 2""); +\t error = 1; + end + + a = 3; + if(a > 2) begin +\t b = 1; + end else begin +\t $display(""FAILED 3 > 2""); +\t error = 1; + end + + + b = 0; + for(a = 10; a > 5; a = a - 1) begin +\t b = b + a; + end + + if(b != 40) begin +\t $display(""FAILED forloop b=%d expected 40"", b); +\t error = 1; + end + + if(error == 0) +\t $display(""PASSED""); + $finish; + + end // initial begin + +endmodule +" +"/* pr1612693.v */ + +module test (); + reg [9:0] col; + wire [9:0] xsize; + // The setup for this expression caused an assertion at run time + // according to pr1612693. + wire vschg = (col == (xsize>>1)); + + initial begin + #1 $display(""PASSED""); + end + +endmodule +" +"/********************************************************************** + * $pow example -- Verilog HDL test bench. + * + * Verilog test bench to test the $pow PLI application. + * + * For the book, ""The Verilog PLI Handbook"" by Stuart Sutherland + * Copyright 1999 & 2001, Kluwer Academic Publishers, Norwell, MA, USA + * Contact: www.wkap.il + * Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA + * Contact: www.sutherland-hdl.com + *********************************************************************/ +`timescale 1ns / 1ns +module test; + + reg [31:0] result; + reg a, b; + + initial + begin + $display(""Start simulation pow_test.v""); + a = 1; + b = 0; + + /* Test $pow with valid values */ + #1 $display(""$pow(2,3) returns %d"", $pow(2,3)); + #1 result = $pow(a,b); + #1 $display(""$pow(a,b) returns %d (a=%d b=%d)"", result, a, b); + #1 $finish(0); + end + +endmodule +/*********************************************************************/ +" +"module stimulus (output reg A); + + initial begin + // input is x + #0 A = 1\'bx; + // input is z + #10 A = 1\'bz; + // one input is a zero + #10 A = 1\'b0; + // one input is a one + #10 A = 1\'b1; + end + +endmodule + +module scoreboard (input Y, A); + +function truth_table (input a); + reg gate_operand; + reg gate_output; + begin + gate_operand = a; + case (gate_operand) + // input is x + 1\'bx: gate_output = 1\'bx; + // inputs is z + 1\'bz: gate_output = 1\'bx; + // normal operation on bit + 1\'b0: gate_output = 1; + 1\'b1: gate_output = 0; + endcase + + truth_table = gate_output; + end +endfunction + + +reg Y_t; + +always @(A) begin + Y_t = truth_table (A); + #1; + if (Y_t !== Y) begin + $display(""FAILED! - mismatch found for input %b in NOT operation"", A); + $finish; + end +end + +endmodule + +module test; + stimulus stim (A); + not_gate duv (.a_i(A), .c_o(Y) ); + scoreboard mon (Y, A); + + initial begin + #200; + $display(""PASSED""); + $finish; + end + +endmodule +" +"// Copyright 2008, Martin Whitaker. +// This file may be freely copied for any purpose. + +module sub_module(); + +generate + genvar i; + for (i = 0; i < 4; i = i + 1) begin:gen_block + localparam l = i + 1; + event trigger; + + always @trigger $display(""generate block %0d triggered"", l); + end +endgenerate + +initial begin:my_block + parameter p = 0; + localparam l = p + 1; + event trigger; + @trigger $display(""block %0d triggered"", l); +end + +task my_task; + parameter p = 0; + localparam l = p + 1; + event trigger; + @trigger $display(""task %0d triggered"", l); +endtask + +initial my_task; + +endmodule + + +module top_module(); + +sub_module sub(); + +defparam sub.my_block.p = 4; +defparam sub.my_task.p = 5; + +initial begin + #1 ->sub.gen_block[0].trigger; + #1 ->sub.gen_block[1].trigger; + #1 ->sub.gen_block[2].trigger; + #1 ->sub.gen_block[3].trigger; + #1 ->sub.my_block.trigger; + #1 ->sub.my_task.trigger; + #1 $finish(0); +end + +endmodule +" +"module foo (); + + parameter CLOCK_FREQUENCY = 90e6; + + // CLOCK_PERIOD_BIT_WIDTH <= log2(90e6) + // log2(90e6) = 26.423 + parameter CLOCK_PERIOD_BIT_WIDTH = 26; + + // build something big enaugh to hold CLOCK_FREQUENCY x CLOCK_PERIOD_BIT_WIDTH sums. + parameter CP_SUM_BIT_WIDTH = 2 * CLOCK_PERIOD_BIT_WIDTH; + + // + // calculate a sane reset value. + // + wire [CLOCK_PERIOD_BIT_WIDTH-1:0] rst, rst2; + + assign rst = {1\'d1, {CP_SUM_BIT_WIDTH-1 {1\'d0}}} / CLOCK_FREQUENCY; + assign rst2 = (52\'d2**(CP_SUM_BIT_WIDTH-1)) / CLOCK_FREQUENCY; + + initial + #1 if (rst == rst2) $display(""PASSED""); + else $display(""FAILED""); + +endmodule // foo +" +"// +// Copyright (c) 2002 Philip Blundell +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Disable within named block. +// + +module m(); + +initial + begin + #10; + $display(""FAILED""); + $finish; + end + +task t; + begin + begin:wait_loop + #1; + while(1) begin + #1; +\t disable wait_loop; + end\t\t// while(1) + end\t\t\t// wait_loop + end +endtask + +initial begin + t; + $display(""PASSED""); + $finish; +end + +endmodule +" +"`timescale 1us/100ns + +module top; + reg pass = 1; + + reg [3:0] ia = 4\'d1, ib = 4\'d2; + wire [2:0] icon, irep; + + /* Integer concatenation. */ + assign #1 icon = {ib[1:0], ia[0]}; // 5 + + /* Integer replication. */ + assign #1 irep = {3{ia[0]}}; // 7 + + + initial begin + #0.9; + if (icon !== 3\'bx) begin + pass = 1\'b0; + $display(""Failed: concatenation is not delayed, expected 3\'bx got %b."", icon); + end + if (irep !== 3\'bx) begin + pass = 1\'b0; + $display(""Failed: replication is not delayed, expected 3\'bx got %b."", irep); + end + #0.1; + #0; + if (icon !== 3\'d5) begin + pass = 1\'b0; + $display(""Failed: concatenation has incorrect value, expected 3\'d5 got %b."", icon); + end + if (irep !== 3\'d7) begin + pass = 1\'b0; + $display(""Failed: replication has incorrect value, expected 3\'d7 got %b."", irep); + end + if (pass) $display(""PASSED""); + end +endmodule +" +"/* PR#704 */ +module foo; + + reg [80*8:1] filename; + reg [31:0] memory[1:2048]; + + initial filename = ""ivltests/pr704.hex""; + + initial begin + $display(""The filename is %0s"", filename); + $readmemb(filename, memory, 1); + + if (memory[1] !== 32\'haa_aa_aa_aa) begin +\t$display(""FAILED""); +\t$finish; + end + + if (memory[2] !== 32\'h55_55_55_55) begin +\t$display(""FAILED""); +\t$finish; + end + + $display(""PASSED""); + $finish; + end + +endmodule +" +"module main; + + wire [3:0] b = 4\'b1111; + wire [3:0] c = 4\'b1111; + + initial begin + #0; // avoid time-0 race + $display(""%b"", ((c & ~(1\'b1<<9\'h00)) & b)); // s.b. 1110 + $display(""%b"", |((c & ~(1\'b1<<9\'h00)) & b)); // s.b. 1 + + if ( ((c & ~(1\'b1<<9\'h00)) & b) !== 4\'b1110) begin +\t $display(""FAILED (1)""); +\t $finish; + end + + if (|((c & ~(1\'b1<<9\'h00)) & b) !== 1\'b1) begin +\t $display(""FAILED (2)""); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"timeunit 1ns; +timeprecision 10ps; + +module test; + +parameter factor = 1e-9/10e-12; + +longint tmanual, tnow, tdiff; +longint incr; + +initial begin + tmanual = 0; + if ($realtime != 0) begin +\t\t$display (""FAILED""); +\t\t$finish; +\tend +\t#33.1ns; +\tincr = 33.1e-9/10e-12; +\ttmanual = tmanual + incr; +\ttnow = $realtime*factor; +\ttdiff = tnow-tmanual; + if (tdiff != 0) begin +\t\t$display (""FAILED""); +\t\t$finish; +\tend +\t#78.1ps; +\tincr = 78.1e-12/10e-12; +\ttmanual = tmanual + incr; +\ttnow = $realtime*factor; +\ttdiff = tnow-tmanual; + if (tdiff != 0) begin +\t\t$display (""FAILED""); +\t\t$finish; +\tend +\t#123.08ns; +\tincr = 123.08e-9/10e-12; +\ttmanual = tmanual + incr; +\ttnow = $realtime*factor; +\ttdiff = tnow-tmanual; + if (tdiff != 0) begin +\t\t$display (""FAILED""); +\t\t$finish; +\tend +\t#9.006ns; +\tincr = 9.006e-9/10e-12; +\ttmanual = tmanual + incr; +\ttnow = $realtime*factor; +\ttdiff = tnow-tmanual; + if (tdiff != 0) begin +\t\t$display (""FAILED""); +\t\t$finish; +\tend +\t#17.003ns; +\tincr = 17.003e-9/10e-12; +\ttmanual = tmanual + incr; +\ttnow = $realtime*factor; +\ttdiff = tnow-tmanual; + if (tdiff != 0) begin +\t\t$display (""FAILED""); +\t\t$finish; +\tend +\t#578.23us; +\tincr = 578.23e-6/10e-12; +\ttmanual = tmanual + incr; +\ttnow = $realtime*factor; +\ttdiff = tnow-tmanual; + if (tdiff != 0) begin +\t\t$display (""FAILED""); +\t\t$finish; +\tend +\t#0.0356ms; +\tincr = 0.0356e-3/10e-12; +\ttmanual = tmanual + incr; +\ttnow = $realtime*factor; +\ttdiff = tnow-tmanual; + if (tdiff != 0) begin +\t\t$display (""FAILED""); +\t\t$finish; +\tend +\t#1.011s; +\tincr = 1.011e0/10e-12; +\ttmanual = tmanual + incr; +\ttnow = $realtime*factor; +\ttdiff = tnow-tmanual; + if (tdiff != 0) begin +\t\t$display (""FAILED""); +\t\t$finish; +\tend +\t$display(""PASSED""); +\t//$display (""Time now is: %t, manual = %0d, tnow = %0d, diff = %0d "", $realtime, tmanual, tnow, tdiff); +\t$finish; +end + +endmodule +" +"module dut(input wire [7:0] i = 8\'d10, output wire [7:0] o); + +assign o = i; + +endmodule + +module tb(); + +wire [7:0] result; + +dut dut(,result); + +initial begin + #1; + if (result === 10) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"// Released under GPL2.0 +// (c) 2002 Tom Verbeure + +module main; + +\tinteger myInt; +\treg [39:0] myReg40; +\treg [0:39] myReg40r; +\treg [0:38] myReg39r; +\treg [13:0] myReg14; +\treg [7:0] myReg8; +\treg [31:0] myReg32; + +\tinitial begin +\t\t$display(""============================ myReg8 = 65""); +\t\tmyReg8 = 65; +\t\t$display("">| 65|""); +\t\t$display(""*|%d|"", myReg8); +\t\t$display(""*|"",myReg8,""|""); + + +\t\t$display(""============================ myReg14 = -10""); +\t\tmyReg14 = -10; +\t\t$display("">|16374|""); +\t\t$display(""*|%d|"", myReg14); +\t\t$display(""*|"",myReg14,""|""); + +\t\t$display(""============================ myReg14 = 65""); +\t\tmyReg14 = 65; +\t\t$display("">1| 65|""); +\t\t$display(""*1|%d|"", myReg14); +\t\t$display("">2|65|""); +\t\t$display(""*2|%0d|"", myReg14); +\t\t$display("">3| 65|""); +\t\t$display(""*3|%10d|"", myReg14); +\t\t$display("">4| 65|""); +\t\t$display(""*4|%08d|"", myReg14); +\t\t$display(""*4|%8d|"", myReg14); +\t\t$display("">5| 65|""); +\t\t$display(""*5|%03d|"", myReg14); +\t\t$display(""*5|%3d|"", myReg14); + +\t\t$display(""============================ myReg14 = 1000""); +\t\tmyReg14 = 1000; +\t\t$display("">|1000|""); +\t\t$display(""*|%03d|"", myReg14); + +\t\t$finish(0); + +\t\t$display(""*|"",myReg14,""|""); + +\t\t$display("">|0041|""); +\t\t$display(""*|%h|"", myReg14); +\t\t$display("">|00000001000001|""); +\t\t$display(""*|%b|"", myReg14); +\t\t$display("">|41|""); +\t\t$display(""*|%0h|"", myReg14); +\t\t$display("">|1000001|""); +\t\t$display(""*|%0b|"", myReg14); +\t\t$display("">| A|""); +\t\t$display(""*|%s|"", myReg14); +\t\t$display("">|A|""); +\t\t$display(""*|%0s|"", myReg14); + +\t\t$display(""============================ myInt = -10""); +\t\tmyInt = -10; +\t\t$display("">| -10|""); +\t\t$display(""*|%d|"", myInt); +\t\t$display(""*|"",myInt,""|""); + +\t\t$display("">|fffffff6|""); +\t\t$display(""*|%h|"", myInt); + +\t\t$display(""============================ myReg32 = -10""); +\t\tmyReg32 = -10; +\t\t$display("">|4294967286|""); +\t\t$display(""*|%d|"", myReg32); +\t\t$display(""*|"",myReg32,""|""); + +\t\t$display("">|fffffff6|""); +\t\t$display(""*|%h|"", myReg32); + +\t\t$display(""============================ myInt = 65""); +\t\tmyInt = 65; +\t\t$display("">| 65|""); +\t\t$display(""*|%d|"", myInt); +\t\t$display(""*|"",myInt,""|""); +\t\t$display(""*| A|""); +\t\t$display("">|%s|"", myInt); +\t\t$display(""*|A|""); +\t\t$display("">|%0s|"", myInt); + +\t\t$display(""============================ myReg32 = 65""); +\t\tmyReg32 = 65; +\t\t$display("">| 65|""); +\t\t$display(""*|%d|"", myReg32); +\t\t$display(""*|"",myReg32,""|""); +\t\t$display(""*| A|""); +\t\t$display("">|%s|"", myReg32); +\t\t$display(""*|A|""); +\t\t$display("">|%0s|"", myReg32); + +\t\t$display(""*| A|""); +\t\t$display("">|%s|"", "" A""); +\t\t$display(""*| A|""); +\t\t$display("">|%0s|"", "" A""); + +\t\t$display(""*|0|""); +\t\t$display("">|%0t|"", $time); +\t\t$display(""*| 0|""); +\t\t$display("">|%t|"", $time); +\tend +endmodule +" +"/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test checks that signed comparisons of constants work + * properly in conditional expressions. These cases are of + * interest because they are evaluated at compile time, so + * that dead code can be skipped. + */ +module main; + + initial begin + if ((0 < -255) || (0 > 255)) begin +\t $display(""FAILED -- expression evaluated true""); +\t $finish; + end + + if ((0 <= -255) || (0 >= 255)) begin +\t $display(""FAILED -- expression evaluated true""); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"// Regression test for GitHub issue 13 : Icarus Verilog creates huge in-memory +// arrays for shifts with large rhs. + +module bug(); + +localparam [4:0] p = 1\'b1 << ~40\'b0; + +initial begin + $display(""%b"", p); + if (p === 5\'b00000) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"/* + * integer4ge - a verilog test for integer greater-or-equal conditional >= + * + * Copyright (C) 2000 Steve Wilson stevew@home.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ +`timescale 100s/1s +module test; + +reg [3:0] result; +reg error; +integer num1; +wire [3:0] result1; + +assign result1 = 1 + (num1 /4); + +initial + begin + error = 0; + num1 = 32\'h24 ; + result = 1 + (num1 / 4); + #1; + if(result !== 4\'ha) + begin + $display(""FAILED - division didn\'t work s/b A, is %h"",result); + error = 1; + end + if(result1 !== 4\'ha) + begin + $display(""FAILED - assign division didn\'t work s/b A, is %h"",result1); + error = 1; + end + if(error == 0) + $display(""PASSED""); + end + +endmodule +" +"module test_top(); + + wire [3:0] test_val; + + test_mod test_mod0 [3:0]( + .in_0(1\'b1), + .out_0(test_val) + ); + + initial begin + #1; + if(test_val != 4\'b0000) $display(""Failed""); + else $display(""PASSED""); + end +endmodule + +module test_mod( + in_0, out_0 + ); + input in_0; + output out_0; + + function test; + input moo; + begin + test = ~moo; + end + endfunction + + assign out_0 = test(in_0); + +endmodule +" +"// Copyright 2008, Martin Whitaker. +// This file may be freely copied for any purpose. + +module array_word_part_select(); +reg pass = 1\'b1; + +reg [3:0]\tData[15:0]; + +reg [3:0]\tIndex; + +wire [2:0]\tValue; + + +assign Value = Data[Index][2:0]; + +integer\t\ti; + +initial begin + for (i = 0; i < 16; i = i + 1) begin + Data[i] = i; + end + for (i = 0; i < 16; i = i + 1) begin + #2 Index = i; + end + #2 if (pass) $display(""PASSED""); +end + +always @(Index) begin +// $display(Index,, Value); + #1 if (Value !== Index % 8) begin + $display(""Failed: testing index %d, expected %d, got %d"", Index, + Index % 8, Value); + pass = 1\'b0; + end +end + +endmodule +" +" $display(""file %s line %0d"", `__FILE__, `__LINE__); +" +"/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module displaysigned(); + +reg signed [7:0] foo; +reg [7:0] bar; + +initial begin + foo = -8\'sd2; + bar = foo; + + $display(""foo=%0d bar=%0d $signed(bar)=%0d"", +\t foo, bar, $signed(bar)); + + $finish(0); +end + +endmodule +" +"/* + * Some more detailed tests of the abs() function. + * + * Copyright (C) 2007-2008 Cary R. (cygcary@yahoo.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +module main; + + reg signed [7:0] a; + wire signed [7:0] vala = abs(a); + + reg\t real b; + wire real valb = abs(b); + + initial begin + a = 0; + b = 0; + #1 if (vala !== 0) begin +\t $display(""FAILED -- a=%b, vala=%b"", a, vala); +\t $finish; + end + + #1 if (valb != 0) begin +\t $display(""FAILED -- b=%g valb=%g"", b, valb); +\t $finish; + end + + a = 1; + b = 1; + #1 if (vala !== 1) begin +\t $display(""FAILED -- a=%b, vala=%b"", a, vala); +\t $finish; + end + + #1 if (valb != 1) begin +\t $display(""FAILED -- b=%g valb=%g"", b, valb); +\t $finish; + end + + a = -1; + b = -1; + #1 if (vala !== 1) begin +\t $display(""FAILED -- a=%b, vala=%b"", a, vala); +\t $finish; + end + + #1 if (valb != 1) begin +\t $display(""FAILED -- b=%g valb=%g"", b, valb); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"// Regression test for GitHub issue 12 : Ternary lval-rval width mismatch. + +module bug(); + +wire [1:0] a; +wire [1:0] y; + +assign a = 2\'b10; + +assign y = \'bx ? 2\'b00 : a; + +reg failed = 0; + +initial begin + #0; + + $display(""%b"", y); + if (y !== 2\'bx0) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"// +// Copyright (c) 1999 Thomas Coonan (tcoonan@mindspring.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SYNTHETIC PIC 2.0 4/23/98 +// +// This is a synthesizable Microchip 16C57 compatible +// microcontroller. This core is not intended as a high fidelity model of +// the PIC, but simply a way to offer a simple processor core to people +// familiar with the PIC who also have PIC tools. +// +// pictest.v - top-level testbench (NOT SYNTHESIZABLE) +// piccpu.v - top-level synthesizable module +// picregs.v - register file instantiated under piccpu +// picalu.v - ALU instantiated under piccpu +// picidec.v - Instruction Decoder instantiated under piccpu +// hex2rom.c - C program used to translate MPLAB\'s INTEL HEX output +// into the Verilog $readmemh compatible file +// test*.asm - (note the wildcard..) Several test programs used +// to help debug the verilog. I used MPLAB and the simulator +// to develop these programs and get the expected results. +// Then, I ran them on Verilog-XL where they appeared to +// match. +// +// Copyright, Tom Coonan, \'97. +// Use freely, but not for resale as is. You may use this in your +// own projects as desired. Just don\'t try to sell it as is! +// +// +module picalu ( + op, + a, + b, + y, + cin, + cout, + zout +); + +input [3:0]\top;\t// ALU Operation +input [7:0]\ta;\t// 8-bit Input a +input [7:0]\tb;\t// 8-bit Input b +output [7:0]\ty;\t// 8-bit Output +input\t\tcin; +output\t\tcout; +output\t\tzout; + +// Reg declarations for outputs +reg\t\tcout; +reg\t\tzout; +reg [7:0]\ty; + +// Internal declarations +reg\t\taddercout; // Carry out straight from the adder itself. + +parameter ALUOP_ADD = 4\'b0000; +parameter ALUOP_SUB = 4\'b1000; +parameter ALUOP_AND = 4\'b0001; +parameter ALUOP_OR = 4\'b0010; +parameter ALUOP_XOR = 4\'b0011; +parameter ALUOP_COM = 4\'b0100; +parameter ALUOP_ROR = 4\'b0101; +parameter ALUOP_ROL = 4\'b0110; +parameter ALUOP_SWAP = 4\'b0111; + + +always @(a or b or cin or op) begin + case (op) // synopsys full_case parallel_case + ALUOP_ADD: {addercout, y} <= a + b; + ALUOP_SUB: {addercout, y} <= a - b; // Carry out is really ""borrow"" + ALUOP_AND: {addercout, y} <= {1\'b0, a & b}; + ALUOP_OR: {addercout, y} <= {1\'b0, a | b}; + ALUOP_XOR: {addercout, y} <= {1\'b0, a ^ b}; + ALUOP_COM: {addercout, y} <= {1\'b0, ~a}; + ALUOP_ROR: {addercout, y} <= {a[0], cin, a[7:1]}; + ALUOP_ROL: {addercout, y} <= {a[7], a[6:0], cin}; + ALUOP_SWAP: {addercout, y} <= {1\'b0, a[3:0], a[7:4]}; + default: {addercout, y} <= {1\'b0, 8\'h00}; + endcase +end + +always @(y) + zout <= (y == 8\'h00); + +always @(addercout or op) + if (op == ALUOP_SUB) cout <= ~addercout; // Invert adder\'s carry to get borrow + else cout <= addercout; + +endmodule +// +// SYNTHETIC PIC 2.0 4/23/98 +// +// This is a synthesizable Microchip 16C57 compatible +// microcontroller. This core is not intended as a high fidelity model of +// the PIC, but simply a way to offer a simple processor core to people +// familiar with the PIC who also have PIC tools. +// +// pictest.v - top-level testbench (NOT SYNTHESIZABLE) +// piccpu.v - top-level synthesizable module +// picregs.v - register file instantiated under piccpu +// picalu.v - ALU instantiated under piccpu +// picidec.v - Instruction Decoder instantiated under piccpu +// hex2rom.c - C program used to translate MPLAB\'s INTEL HEX output +// into the Verilog $readmemh compatible file +// test*.asm - (note the wildcard..) Several test programs used +// to help debug the verilog. I used MPLAB and the simulator +// to develop these programs and get the expected results. +// Then, I ran them on Verilog-XL where they appeared to +// match. +// +// Copyright, Tom Coonan, \'97. +// Use freely, but not for resale as is. You may use this in your +// own projects as desired. Just don\'t try to sell it as is! +// +// +module piccpu ( + clk, + reset, + paddr, + pdata, + portain, + portbout, + portcout, + + debugw, + debugpc, + debuginst, + debugstatus +); + +input\t\tclk; +input\t\treset; +output [8:0]\tpaddr; +input [11:0]\tpdata; +input [7:0]\tportain; +output [7:0]\tportbout; +output [7:0]\tportcout; + +output [7:0]\tdebugw; +output [8:0]\tdebugpc; +output [11:0]\tdebuginst; +output [7:0]\tdebugstatus; + +// Register declarations for outputs +reg [8:0]\tpaddr; +reg [7:0]\tportbout; +reg [7:0]\tportcout; + +// This should be set to the ROM location where our restart vector is. +// As set here, we have 512 words of program space. +// +parameter RESET_VECTOR = 9\'h1FF; + +parameter\tINDF_ADDRESS\t= 3\'h0, +\t\tTMR0_ADDRESS\t= 3\'h1, +\t\tPCL_ADDRESS\t= 3\'h2, +\t\tSTATUS_ADDRESS\t= 3\'h3, +\t\tFSR_ADDRESS\t= 3\'h4, +\t\tPORTA_ADDRESS\t= 3\'h5, +\t\tPORTB_ADDRESS\t= 3\'h6, +\t\tPORTC_ADDRESS\t= 3\'h7; + +// Experimental custom peripheral, ""Lil Adder (a 4-bit adder)"" is at this address. +// +parameter\tEXPADDRESS_LILADDER = 7\'h7F; + +// ********* Special internal registers + +// Instruction Register +reg [11:0]\tinst; + +// Program Counter +reg [8:0]\tpc; +reg [8:0]\tpcplus1; // Output of the pc incrementer. + +// Stack Registers and Stack ""levels"" register. +reg [ 1:0]\tstacklevel; +reg [ 8:0]\tstack1; +reg [ 8:0]\tstack2; + +// W Register +reg [ 7:0]\tw; + +// The STATUS register (#3) is 8 bits wide, however, we only currently use 2 bits +// of it; the C and Z bit. +// +// bit 0 - C +// bit 2 - Z +// +reg [ 7:0]\tstatus; + +// The FSR register is the pointer register used for Indirect addressing (e.g. using INDF). +reg [ 7:0]\tfsr; + +// Timer 0 +reg [ 7:0]\ttmr0; +reg [ 7:0]\tprescaler; + +// Option Register +reg [7:0]\toption; + +// Tristate Control registers. We do not neccessarily support bidirectional ports, but +// will save a place for these registers and the TRIS instruction. Use for debug. +reg [7:0]\ttrisa; +reg [7:0]\ttrisb; +reg [7:0]\ttrisc; + +// I/O Port registers +// +reg [7:0]\tporta;\t// Input PORT +reg [7:0]\tportb;\t// Output PORT +reg [7:0]\tportc;\t// Output PORT + +// ********** Instruction Related signals ****** + +reg\t\tskip; // When HI force a NOP (all zeros) into inst + +reg [2:0]\tpcinsel; + +// Derive special sub signals from inst register +wire [ 7:0]\tk; +wire [ 4:0]\tfsel; +wire [ 8:0]\tlongk; +wire\t\td; +wire [ 2:0]\tb; + +// ********** File Address ************ +// +// This is the 7-bit Data Address that includes the lower 5-bit fsel, the +// FSR bits and any indirect addressing. +// Use this bus to address the Register File as well as all special registers, etc. +// +reg [6:0]\tfileaddr; + +// Address Selects +reg\t\tspecialsel; +reg\t\tregfilesel; +reg\t\texpsel; + +// ****** Instruction Decoder Outputs ************** + +// Write enable for the actual ZERO and CARRY bits within the status register. +// Generated by the Instruction Decoder. +// +wire [1:0]\taluasel; +wire [1:0]\talubsel; +wire [3:0]\taluop; + +wire\t\tzwe; +wire\t\tcwe; + +wire\t\tisoption; +wire\t\tistris; + +wire\t\tfwe;\t// High if any ""register"" is being written to at all. +wire\t\twwe;\t// Write Enable for the W register. Produced by Instruction Decoder. + +// ************* Internal Busses, mux connections, etc. ******************** + +// Bit decoder bits. +reg [7:0]\tbd;\t// Final decoder value after any polarity inversion. +reg [7:0]\tbdec;\t// e.g. ""Bit Decoded"" + +// Data in and out of the and out of the register file +// +reg [7:0]\tregfilein;\t// Input into Register File, is connected to the dbus. +wire [7:0]\tregfileout;\t// Path leaving the register file, goes to SBUS Mux +reg\t\tregfilewe;\t// Write Enable +reg\t\tregfilere;\t// Read Enable + +// +// The dbus (Destination Bus) comes out of the ALU. It is available to all +// writable registers. +// +// The sbus (Source Bus) comes from all readable registers as well as the output +// of the Register File. It is one of the primary inputs into the ALU muxes. +// +// The ebus (Expansion Bus) comes from any of our custom modules. They must +// all coordinate to place whoever\'s data onto ebus. +// +reg [7:0]\tdbus; +reg [7:0]\tsbus; +reg [7:0]\tebus; + + +// ALU Signals +// +reg [7:0]\talua; +reg [7:0]\talub; +wire [7:0]\taluout; +wire\t\talucin; +wire\t\talucout; +wire\t\taluz; + +// ALU A and B mux selects. +// +parameter\tALUASEL_W\t= 2\'b00, +\t\tALUASEL_SBUS\t= 2\'b01, +\t\tALUASEL_K\t= 2\'b10, +\t\tALUASEL_BD\t= 2\'b11; + +parameter\tALUBSEL_W\t= 2\'b00, +\t\tALUBSEL_SBUS\t= 2\'b01, +\t\tALUBSEL_K\t= 2\'b10, +\t\tALUBSEL_1\t= 2\'b11; + +// ALU Operation codes. +// +parameter ALUOP_ADD = 4\'b0000; +parameter ALUOP_SUB = 4\'b1000; +parameter ALUOP_AND = 4\'b0001; +parameter ALUOP_OR = 4\'b0010; +parameter ALUOP_XOR = 4\'b0011; +parameter ALUOP_COM = 4\'b0100; +parameter ALUOP_ROR = 4\'b0101; +parameter ALUOP_ROL = 4\'b0110; +parameter ALUOP_SWAP = 4\'b0111; + + +// Instantiate each of our subcomponents +// +picregs regs ( + .clk\t\t(clk), + .reset\t(reset), + .we\t\t(regfilewe), + .re\t\t(regfilere), + .bank\t(fileaddr[6:5]), + .location\t(fileaddr[4:0]), + .din\t\t(regfilein), + .dout\t(regfileout) +); + +// Instatiate the ALU. +// +picalu alu ( + .op (aluop), + .a (alua), + .b (alub), + .y (aluout), + .cin (status[0]), + .cout (alucout), + .zout (aluz) +); + +// Instantiate the Instruction Decoder. This is really just a lookup table. +// Given the instruction, generate all the signals we need. +// +// For example, each instruction implies a specific ALU operation. Some of +// these are obvious such as the ADDW uses an ADD alu op. Less obvious is +// that a mov instruction uses an OR op which lets us do a simple copy. +// +// Data has to funnel through the ALU, which sometimes makes for contrived +// ALU ops. +// +picidec idec ( + .inst (inst), + .aluasel (aluasel), + .alubsel (alubsel), + .aluop (aluop), + .wwe (wwe), + .fwe (fwe), + .zwe (zwe), + .cwe (cwe), + .bdpol (bdpol), + .option (isoption), + .tris (istris) +); + +// *********** Debug **************** +assign\tdebugw = w; +assign\tdebugpc = pc; +assign\tdebuginst = inst; +assign\tdebugstatus = status; + +// *********** REGISTER FILE Addressing **************** +// +// We implement the following: +// - The 5-bit fsel address is within a ""BANK"" which is 32 bytes. +// - The FSR bits 6:5 are the BANK select, so there are 4 BANKS, a +// total of 128 bytes. Minus the 8 special registers, that\'s +// really 120 bytes. +// - The INDF register is for indirect addressing. Referencing INDF +// uses FSR as the pointer. Therefore, using INDF/FSR you address +// 7-bits of memory. +// We DO NOT currently implement the PAGE for program (e.g. STATUS register +// bits 6:5) +// +// The fsel address *may* be zero in which case, we are to do indirect +// addressing, using FSR register as the 8-bit pointer. +// +// Otherwise, use the 5-bits of FSEL (from the Instruction itself) and +// 2 bank bits from the FSR register (bits 6:5). +// +always @(fsel or fsr) begin + if (fsel == INDF_ADDRESS) begin + // The INDEX register is addressed. There really is no INDEX register. + // Use the FSR as an index, e.g. the FSR contents are the fsel. + // + fileaddr <= fsr[6:0]; + end + else begin + // Use FSEL field and status bank select bits + // + fileaddr <= {fsr[6:5], fsel}; + end +end + +// Write Enable to Register File. +// Assert this when the general fwe (write enable to *any* register) is true AND Register File +// address range is specified. +// +always @(regfilesel or fwe) + regfilewe <= regfilesel & fwe; + +// Read Enable (this if nothing else, helps in debug.) +// Assert if Register File address range is specified AND the ALU is actually using some +// data off the SBUS. +// +always @(regfilesel or aluasel or alubsel) + regfilere <= regfilesel & ((aluasel == ALUASEL_SBUS) | (alubsel == ALUBSEL_SBUS)); + +// *********** Address Decodes ************** +// +// Generate 3 selects: specialsel, regfilesel and expsel +always @(fileaddr) begin + casex (fileaddr) + 7\'bXX00XXX: // The SPECIAL Registers are lower 8 addresses, in ALL BANKS + begin + specialsel\t<= 1\'b1; + regfilesel\t<= 1\'b0; + expsel\t<= 1\'b0; + end + 7\'b1111111: // EXPANSION Registers are the top (1) addresses + begin + specialsel\t<= 1\'b0; + regfilesel\t<= 1\'b0; + expsel\t<= 1\'b1; + end + default: // Anything else must be in the Register File + begin + specialsel\t<= 1\'b0; + regfilesel\t<= 1\'b1; + expsel\t<= 1\'b0; + end + endcase +end + +// *********** SBUS ************** +// The sbus (Source Bus) is the output of a multiplexor that takes +// inputs from the Register File, and all other special registers +// and input ports. The Source Bus then, one of the inputs to the ALU + + +// First MUX selects from all the special regsiters +// +always @(fsel or fsr or tmr0 or pc or status + or porta or portb or portc or regfileout or ebus + or specialsel or regfilesel or expsel) begin + + // For our current mix of registers and peripherals, only the first 8 addresses + // are ""special"" registers (e.g. not in the Register File). As more peripheral + // registers are added, they must be muxed into this MUX as well. + // + // We currently prohibit tristates. + // + // + if (specialsel) begin + // Special register + case (fsel[2:0]) // synopsys parallel_case full_case + 3\'h0:\tsbus <= fsr; + 3\'h1:\tsbus <= tmr0; + 3\'h2:\tsbus <= pc[7:0]; + 3\'h3:\tsbus <= status; + 3\'h4:\tsbus <= fsr; + 3\'h5:\tsbus <= porta; // PORTA is an input-only port + 3\'h6:\tsbus <= portb; // PORTB is an output-only port + 3\'h7:\tsbus <= portc; // PORTC is an output-only port + endcase + end + else begin + // + // Put whatever address equation is neccessary here. Remember to remove unnecessary + // memory elements from Register File (picregs.v). It\'ll still work, but they\'d be + // wasted flip-flops. + // + if (expsel) begin + sbus <= ebus; + end + else begin + if (regfilesel) begin + // Final Priority is Choose the register file + sbus <= regfileout; + end + else begin + sbus <= 8\'h00; + end + end + end +end + +// ************** DBUS ****** +// The Destination bus is just the output of the ALU. +// +always @(aluout) + dbus <= aluout; + +always @(dbus) + regfilein <= dbus; + +// Drive the ROM address bus straight from the PC +// +always @(pc) + paddr = pc; + + +// Define sub-signals out of inst +// +assign k = inst[7:0]; +assign fsel = inst[4:0]; +assign longk = inst[8:0]; +assign d = inst[5]; +assign b = inst[7:5]; + +// Bit Decoder. +// +// Simply take the 3-bit b field in the PIC instruction and create the +// expanded 8-bit decoder field, which is used as a mask. +// + + +always @(b) begin + case (b) + 3\'b000: bdec <= 8\'b00000001; + 3\'b001: bdec <= 8\'b00000010; + 3\'b010: bdec <= 8\'b00000100; + 3\'b011: bdec <= 8\'b00001000; + 3\'b100: bdec <= 8\'b00010000; + 3\'b101: bdec <= 8\'b00100000; + 3\'b110: bdec <= 8\'b01000000; + 3\'b111: bdec <= 8\'b10000000; + endcase +end + +always @(bdec or bdpol) + bd <= bdec ^ bdpol; + +// Instruction regsiter usually get the ROM data as its input, but +// sometimes for branching, the skip signal must cause a NOP. +// +always @(posedge clk) begin + if (reset) begin + inst <= 12\'h000; + end + else begin + if (skip == 1\'b1) begin + inst <= 12\'b000000000000; // FORCE NOP + end + else begin + inst <= pdata; + end + end +end + +// SKIP signal. +// +// We want to insert the NOP instruction for the following conditions: +// GOTO,CALL and RETLW instructions (All have inst[11:10] = 2\'b10 +// BTFSS instruction when aluz is HI ( +// BTFSC instruction when aluz is LO +// +always @(inst or aluz) begin + casex ({inst, aluz}) + 13\'b10??_????_????_?: // A GOTO, CALL or RETLW instructions + skip <= 1\'b1; + + 13\'b0110_????_????_1: // BTFSC instruction and aluz == 1 + skip <= 1\'b1; + + 13\'b0111_????_????_0: // BTFSS instruction and aluz == 0 + skip <= 1\'b1; + + 13\'b0010_11??_????_1: // DECFSZ instruction and aluz == 1 + skip <= 1\'b1; + + 13\'b0011_11??_????_1: // INCFSZ instruction and aluz == 1 + skip <= 1\'b1; + + default: + skip <= 1\'b0; + endcase +end + +// 4:1 Data MUX into alua +// +// +always @(aluasel or w or sbus or k or bd) begin + case (aluasel) + 2\'b00: alua <= w; + 2\'b01: alua <= sbus; + 2\'b10: alua <= k; + 2\'b11: alua <= bd; + endcase +end + +// 4:1 Data MUX into alub +// +// +always @(alubsel or w or sbus or k) begin + case (alubsel) + 2\'b00: alub <= w; + 2\'b01: alub <= sbus; + 2\'b10: alub <= k; + 2\'b11: alub <= 8\'b00000001; + endcase +end + +// W Register +always @(posedge clk) begin + if (reset) begin + w <= 8\'h00; + end + else begin + if (wwe) begin + w <= dbus; + end + end +end + +// ************ Writes to various Special Registers (fsel between 0 and 7) + +// INDF Register (Register #0) +// +// Not a real register. This is the Indirect Addressing mode register. +// See the regfileaddr logic. + +// TMR0 Register (Register #1) +// +// Timer0 is currently only a free-running timer clocked by the main system clock. +// +always @(posedge clk) begin + if (reset) begin + tmr0 <= 8\'h00; + end + else begin + // See if the status register is actually being written to + if (fwe & specialsel & (fsel == TMR0_ADDRESS)) begin + // Yes, so just update the register from the dbus + tmr0 <= dbus; + end + else begin + // Mask off the prescaler value based on desired divide ratio. + // Whenever this is zero, then that is our divided pulse. Increment + // the final timer value when it\'s zero. + // + case (option[2:0]) // synopsys parallel_case full_case + 3\'b000: if (~|(prescaler & 8\'b00000001)) tmr0 <= tmr0 + 1; + 3\'b001: if (~|(prescaler & 8\'b00000011)) tmr0 <= tmr0 + 1; + 3\'b010: if (~|(prescaler & 8\'b00000111)) tmr0 <= tmr0 + 1; + 3\'b011: if (~|(prescaler & 8\'b00001111)) tmr0 <= tmr0 + 1; + 3\'b100: if (~|(prescaler & 8\'b00011111)) tmr0 <= tmr0 + 1; + 3\'b101: if (~|(prescaler & 8\'b00111111)) tmr0 <= tmr0 + 1; + 3\'b110: if (~|(prescaler & 8\'b01111111)) tmr0 <= tmr0 + 1; + 3\'b111: if (~|(prescaler & 8\'b11111111)) tmr0 <= tmr0 + 1; + endcase + end + end +end + +// The prescaler is always counting from 00 to FF +always @(posedge clk) begin + if (reset) begin + prescaler <= 8\'h00; + end + else begin + // See if the status register is actually being written to + prescaler <= prescaler + 1; + end +end + + +// PCL Register (Register #2) +// +// PC Lower 8 bits. This is handled in the PC section below... + + +// STATUS Register (Register #3) +// +always @(posedge clk) begin + if (reset) begin + status <= 8\'h00; + end + else begin + // See if the status register is actually being written to + if (fwe & specialsel & (fsel == STATUS_ADDRESS)) begin + // Yes, so just update the register from the dbus + status <= dbus; + end + else begin + // Update status register on a bit-by-bit basis. + // + // For the carry and zero flags, each instruction has its own rule as + // to whether to update this flag or not. The instruction decoder is + // providing us with an enable for C and Z. Use this to decide whether + // to retain the existing value, or update with the new alu status output. + // + status <= { + status[7],\t\t\t// BIT 7: Undefined.. (maybe use for debugging) + status[6],\t\t\t// BIT 6: Program Page, HI bit + status[5],\t\t\t// BIT 5: Program Page, LO bit + status[4],\t\t\t// BIT 4: Time Out bit (not implemented at this time) + status[3],\t\t\t// BIT 3: Power Down bit (not implemented at this time) + (zwe) ? aluz : status[2],\t// BIT 2: Z + status[1],\t\t\t// BIT 1: DC + (cwe) ? alucout : status[0]\t// BIT 0: C + }; + end + end +end + +// FSR Register (Register #4) +// +always @(posedge clk) begin + if (reset) begin + fsr <= 8\'h00; + end + else begin + // See if the status register is actually being written to + if (fwe & specialsel & (fsel == FSR_ADDRESS)) begin + fsr <= dbus; + end + end +end + +// OPTION Register +// +// The special OPTION instruction should move W into the OPTION register. +always @(posedge clk) begin + if (reset) begin + option <= 8\'h00; + end + else begin + if (isoption) + option <= dbus; + end +end + +// PORTA Input Port (Register #5) +// +// Register anything on the module\'s porta input on every single clock. +// +always @(posedge clk) begin + if (reset) begin + porta <= 8\'h00; + end + else begin + porta <= portain; + end +end + +// PORTB Output Port (Register #6) +always @(posedge clk) begin + if (reset) begin + portb <= 8\'h00; + end + else begin + if (fwe & specialsel & (fsel == PORTB_ADDRESS) & ~istris) begin + portb <= dbus; + end + end +end + +// Connect the output ports to the register output. +always @(portb) + portbout <= portb; + +// PORTC Output Port (Register #7) +always @(posedge clk) begin + if (reset) begin + portc <= 8\'h00; + end + else begin + if (fwe & specialsel & (fsel == PORTC_ADDRESS) & ~istris) begin + portc <= dbus; + end + end +end + +// Connect the output ports to the register output. +always @(portc) + portcout <= portc; + +// TRIS Registers +always @(posedge clk) begin + if (reset) begin + trisa <= 8\'hff; // Default is to tristate them + end + else begin + if (fwe & specialsel & (fsel == PORTA_ADDRESS) & istris) begin + trisa <= dbus; + end + end +end + +always @(posedge clk) begin + if (reset) begin + trisb <= 8\'hff; // Default is to tristate them + end + else begin + if (fwe & specialsel & (fsel == PORTB_ADDRESS) & istris) begin + trisb <= dbus; + end + end +end + +always @(posedge clk) begin + if (reset) begin + trisc <= 8\'hff; // Default is to tristate them + end + else begin + if (fwe & specialsel & (fsel == PORTC_ADDRESS) & istris) begin + trisc <= dbus; + end + end +end + + +// ********** PC AND STACK ************************* +// +// There are 4 ways to change the PC. They are: +// GOTO 101k_kkkk_kkkk +// CALL 1001_kkkk_kkkk +// RETLW 1000_kkkk_kkkk +// MOVF 0010_0010_0010 (e.g. a write to reg #2) +// +// Remember that the skip instructions work by inserting +// a NOP instruction or not into program stream and don\'t +// change the PC. +// + +// We need pc + 1 in several places, so lets define this incrementor and +// its output signal it in one place so that we never get redundant adders. +// +always @(pc) + pcplus1 <= pc + 1; + +parameter\tPC_SELECT_PCPLUS1\t= 3\'b000, +\t\tPC_SELECT_K = 3\'b001, +\t\tPC_SELECT_STACK1 = 3\'b010, +\t\tPC_SELECT_STACK2 = 3\'b011, +\t\tPC_SELECT_DBUS = 3\'b100, +\t\tPC_SELECT_RESET_VECTOR = 3\'b101; + +// 8:1 Data MUX into PC +always @(posedge clk) begin + case (pcinsel) // synopsys parallel_case full_case + 3\'b000: pc <= pcplus1; + 3\'b001: pc <= k; + 3\'b010: pc <= stack1; + 3\'b011: pc <= stack2; + 3\'b100: pc <= dbus; + 3\'b101: pc <= RESET_VECTOR; + + // Don\'t really carry about these... + 3\'b110: pc <= pc; + 3\'b111: pc <= pc; + endcase +end + +// Select for the MUX going into the PC. +// +// +always @(inst or stacklevel or reset) begin + if (reset == 1\'b1) begin + pcinsel <= PC_SELECT_RESET_VECTOR; + end + else begin + casex ({inst, stacklevel}) + 14\'b101?_????_????_??: pcinsel <= PC_SELECT_K;\t\t// GOTO + 14\'b1001_????_????_??: pcinsel <= PC_SELECT_K;\t\t// CALL + 14\'b1000_????_????_00: pcinsel <= PC_SELECT_STACK1;\t// RETLW + 14\'b1000_????_????_01: pcinsel <= PC_SELECT_STACK1;\t// RETLW + 14\'b1000_????_????_10: pcinsel <= PC_SELECT_STACK2;\t// RETLW + 14\'b1000_????_????_11: pcinsel <= PC_SELECT_STACK2;\t// RETLW + 14\'b0010_0010_0010_??: pcinsel <= PC_SELECT_DBUS;\t// MOVF where f=PC + default: + pcinsel <= PC_SELECT_PCPLUS1; + endcase + end +end + + +// Implement STACK1 and STACK2 registers +// +// The Stack registers are only fed from the PC itself! +// +always @(posedge clk) begin + if (reset) begin + stack1 <= 9\'h000; + end + else begin + // CALL instruction + if (inst[11:8] == 4\'b1001) begin + case (stacklevel) + 2\'b00: + // No previous CALLs + begin + stack1 <= pc; + $display (""Write to STACK1: %0h"", pc); + end + 2\'b01: + // ONE previous CALL + begin + stack2 <= pc; + $display (""Write to STACK2: %0h"", pc); + end + 2\'b10: + // TWO previous CALLs -- This is illegal on the 16C5X! + begin + $display (""Too many CALLs!!""); + end + 2\'b11: + begin + $display (""Too many CALLs!!""); + end + endcase + end + end +end + +// Write to stacklevel +// +// The stacklevel register keeps track of the current stack depth. On this +// puny processor, there are only 2 levels (you could fiddle with this and +// increase the stack depth). There are two stack registers, stack1 and stack2. +// The stack1 register is used first (e.g. the first time a call is performed), +// then stack2. As CALLs are done, stacklevel increments. Conversely, as +// RETs are done, stacklevel goes down. + +always @(posedge clk) begin + if (reset == 1\'b1) begin + stacklevel <= 2\'b00; // On reset, there should be no CALLs in progress + end + else begin + casex ({inst, stacklevel}) + // Call instructions + 14\'b1001_????_????_00: stacklevel <= 2\'b01; // Record 1st CALL + 14\'b1001_????_????_01: stacklevel <= 2\'b10; // Record 2nd CALL + 14\'b1001_????_????_10: stacklevel <= 2\'b10; // Already 2! Ignore + 14\'b1001_????_????_11: stacklevel <= 2\'b00; // {shouldn\'t happen} + + // Return instructions + 14\'b1000_????_????_00: stacklevel <= 2\'b00; // {shouldn\'t happen} + 14\'b1000_????_????_01: stacklevel <= 2\'b00; // Go back to no CALL in progress + 14\'b1000_????_????_10: stacklevel <= 2\'b01; // Go back to 1 CALL in progress + 14\'b1000_????_????_11: stacklevel <= 2\'b10; // {shouldn\'t happen} sort of like, Go back to 2 calls in progress + default: + stacklevel <= stacklevel; + endcase + end +end + + + +// ************ EXPANSION ************************* +// +// The following is an example of customization. +// +// Example: Create a read/write port located at address 7F. It\'ll be 8-bits, where +// 'b' the upper 4 bits are outputs and the lower 4 bits are inputs. +// Use indirect addressing to access it (INDF/FSR). Just for fun, let\'s +// attach a special loop-back circuit between the outputs and inputs. +// Let\'s attach... say... a 4-bit adder. +// + +reg [3:0]\tspecial_peripheral_writeable_bits; +reg [3:0]\tspecial_peripheral_readeable_bits; + +// Implement the writeable bits. +// +always @(posedge clk) begin + if (reset) begin + special_peripheral_writeable_bits <= 4\'b0000; + end + else begin + if (fwe & expsel & (fileaddr == EXPADDRESS_LILADDER)) begin + special_peripheral_writeable_bits <= dbus; + end + end +end + +// Implement the special peripheral function (the 4-bit adder for this example). +always @(special_peripheral_writeable_bits) begin + special_peripheral_readeable_bits <= special_peripheral_writeable_bits + 1; +end + +// Drive the ebus. With only one custom address, no more muxing needs to be +// done, but if there are multiple custom circuits, everyone needs to cooperate +// and drive ebus properly. +// +always @(fileaddr or special_peripheral_readeable_bits) begin + if (fileaddr == EXPADDRESS_LILADDER) + ebus <= special_peripheral_readeable_bits; + else + ebus <= 8\'hff; +end + +endmodule +// +// SYNTHETIC PIC 2.0 4/23/98 +// +// This is a synthesizable Microchip 16C57 compatible +// microcontroller. This core is not intended as a high fidelity model of +// the PIC, but simply a way to offer a simple processor core to people +// familiar with the PIC who also have PIC tools. +// +// pictest.v - top-level testbench (NOT SYNTHESIZABLE) +// piccpu.v - top-level synthesizable module +// picregs.v - register file instantiated under piccpu +// picalu.v - ALU instantiated under piccpu +// picidec.v - Instruction Decoder instantiated under piccpu +// hex2rom.c - C program used to translate MPLAB\'s INTEL HEX output +// into the Verilog $readmemh compatible file +// test*.asm - (note the wildcard..) Several test programs used +// to help debug the verilog. I used MPLAB and the simulator +// to develop these programs and get the expected results. +// Then, I ran them on Verilog-XL where they appeared to +// match. +// +// Copyright, Tom Coonan, \'97. +// Use freely, but not for resale as is. You may use this in your +// own projects as desired. Just don\'t try to sell it as is! +// +// +// This is the PIC Instruction Decoder. +// +// The 12-bit PIC instruction must result in a set of control +// signals to the ALU, register write enables and other wires. +// This is purely combinatorial. This can physically be +// implemented as a ROM, or, in this implementation a Verilog +// casex statement is used to directly synthesize the signals. +// This approach is more portable, and hopefully much reduction +// occurs in the equations. +// +// The Synthetic PIC Manual contains a table that better shows +// all the required signals per instruction. I basically +// took that table and created the Verilog implementation below. +// + +module picidec ( +\tinst, +\taluasel, +\talubsel, +\taluop, +\twwe, +\tfwe, +\tzwe, +\tcwe, +\tbdpol, +\toption, +\ttris +); + +input [11:0]\tinst; + +output [1:0]\taluasel; +output [1:0]\talubsel; +output [3:0]\taluop; +output\t\twwe; +output\t\tfwe; +output\t\tzwe; +output\t\tcwe; +output\t\tbdpol; +output\t\toption; +output\t\ttris; + +reg [14:0] decodes; + +// For reference, the ALU Op codes are: +// +// ADD 0000 +// SUB 1000 +// AND 0001 +// OR 0010 +// XOR 0011 +// COM 0100 +// ROR 0101 +// ROL 0110 +// SWAP 0111 + +assign {\taluasel,\t// Select source for ALU A input. 00=W, 01=SBUS, 10=K, 11=BD +\t\talubsel,\t// Select source for ALU B input. 00=W, 01=SBUS, 10=K, 11=""1"" +\t\taluop,\t\t// ALU Operation (see comments above for these codes) +\t\twwe,\t\t// W register Write Enable +\t\tfwe,\t\t// File Register Write Enable +\t\tzwe,\t\t// Status register Z bit update +\t\tcwe,\t\t// Status register Z bit update +\t\tbdpol,\t\t// Polarity on bit decode vector (0=no inversion, 1=invert) +\t\ttris,\t\t// Instruction is an TRIS instruction +\t\toption\t\t// Instruction is an OPTION instruction +\t} = decodes; + +// This is a large combinatorial decoder. +// I use the casex statement. + +always @(inst) begin +\tcasex (inst) +\t\t// *** Byte-Oriented File Register Operations +\t\t// +\t\t// A A ALU W F Z C B T O +\t\t// L L O W W W W D R P +\t\t// U U P E E E E P I T +\t\t// A B O S +\t\t// L +\t\t12\'b0000_0000_0000: decodes <= 15\'b00_00_0000_0_0_0_0_0_0_0; // NOP +\t\t12\'b0000_001X_XXXX: decodes <= 15\'b00_00_0010_0_1_0_0_0_0_0; // MOVWF +\t\t12\'b0000_0100_0000: decodes <= 15\'b00_00_0011_1_0_1_0_0_0_0; // CLRW +\t\t12\'b0000_011X_XXXX: decodes <= 15\'b00_00_0011_0_1_1_0_0_0_0; // CLRF +\t\t12\'b0000_100X_XXXX: decodes <= 15\'b01_00_1000_1_0_1_1_0_0_0; // SUBWF (d=0) +\t\t12\'b0000_101X_XXXX: decodes <= 15\'b01_00_1000_0_1_1_1_0_0_0; // SUBWF (d=1) +\t\t12\'b0000_110X_XXXX: decodes <= 15\'b01_11_1000_1_0_1_0_0_0_0; // DECF (d=0) +\t\t12\'b0000_111X_XXXX: decodes <= 15\'b01_11_1000_0_1_1_0_0_0_0; // DECF (d=1) +\t\t12\'b0001_000X_XXXX: decodes <= 15\'b00_01_0010_1_0_1_0_0_0_0; // IORWF (d=0) +\t\t12\'b0001_001X_XXXX: decodes <= 15\'b00_01_0010_0_1_1_0_0_0_0; // IORWF (d=1) +\t\t12\'b0001_010X_XXXX: decodes <= 15\'b00_01_0001_1_0_1_0_0_0_0; // ANDWF (d=0) +\t\t12\'b0001_011X_XXXX: decodes <= 15\'b00_01_0001_0_1_1_0_0_0_0; // ANDWF (d=1) +\t\t12\'b0001_100X_XXXX: decodes <= 15\'b00_01_0011_1_0_1_0_0_0_0; // XORWF (d=0) +\t\t12\'b0001_101X_XXXX: decodes <= 15\'b00_01_0011_0_1_1_0_0_0_0; // XORWF (d=1) +\t\t12\'b0001_110X_XXXX: decodes <= 15\'b00_01_0000_1_0_1_1_0_0_0; // ADDWF (d=0) +\t\t12\'b0001_111X_XXXX: decodes <= 15\'b00_01_0000_0_1_1_1_0_0_0; // ADDWF (d=1) +\t\t12\'b0010_000X_XXXX: decodes <= 15\'b01_01_0010_1_0_1_0_0_0_0; // MOVF (d=0) +\t\t12\'b0010_001X_XXXX: decodes <= 15\'b01_01_0010_0_1_1_0_0_0_0; // MOVF (d=1) +\t\t12\'b0010_010X_XXXX: decodes <= 15\'b01_01_0100_1_0_1_0_0_0_0; // COMF (d=0) +\t\t12\'b0010_011X_XXXX: decodes <= 15\'b01_01_0100_0_1_1_0_0_0_0; // COMF (d=1) +\t\t12\'b0010_100X_XXXX: decodes <= 15\'b01_11_0000_1_0_1_0_0_0_0; // INCF (d=0) +\t\t12\'b0010_101X_XXXX: decodes <= 15\'b01_11_0000_0_1_1_0_0_0_0; // INCF (d=1) +\t\t12\'b0010_110X_XXXX: decodes <= 15\'b01_11_1000_1_0_0_0_0_0_0; // DECFSZ(d=0) +\t\t12\'b0010_111X_XXXX: decodes <= 15\'b01_11_1000_0_1_0_0_0_0_0; // DECFSZ(d=1) +\t\t12\'b0011_000X_XXXX: decodes <= 15\'b01_01_0101_1_0_0_1_0_0_0; // RRF (d=0) +\t\t12\'b0011_001X_XXXX: decodes <= 15\'b01_01_0101_0_1_0_1_0_0_0; // RRF (d=1) +\t\t12\'b0011_010X_XXXX: decodes <= 15\'b01_01_0110_1_0_0_1_0_0_0; // RLF (d=0) +\t\t12\'b0011_011X_XXXX: decodes <= 15\'b01_01_0110_0_1_0_1_0_0_0; // RLF (d=1) +\t\t12\'b0011_100X_XXXX: decodes <= 15\'b01_01_0111_1_0_0_0_0_0_0; // SWAPF (d=0) +\t\t12\'b0011_101X_XXXX: decodes <= 15\'b01_01_0111_0_1_0_0_0_0_0; // SWAPF (d=1) +\t\t12\'b0011_110X_XXXX: decodes <= 15\'b01_11_0000_1_0_0_0_0_0_0; // INCFSZ(d=0) +\t\t12\'b0011_111X_XXXX: decodes <= 15\'b01_11_0000_0_1_0_0_0_0_0; // INCFSZ(d=1) + +\t\t// *** Bit-Oriented File Register Operations + // +\t\t// A A ALU W F Z C B T O +\t\t// L L O W W W W D R P +\t\t// U U P E E E E P I T +\t\t// A B O S +\t\t// L +\t\t12\'b0100_XXXX_XXXX: decodes <= 15\'b11_01_0001_0_1_0_0_1_0_0; // BCF +\t\t12\'b0101_XXXX_XXXX: decodes <= 15\'b11_01_0010_0_1_0_0_0_0_0; // BSF +\t\t12\'b0110_XXXX_XXXX: decodes <= 15\'b11_01_0001_0_0_0_0_0_0_0; // BTFSC +\t\t12\'b0111_XXXX_XXXX: decodes <= 15\'b11_01_0001_0_0_0_0_0_0_0; // BTFSS + +\t\t// *** Literal and Control Operations + // +\t\t// A A ALU W F Z C B T O +\t\t// L L O W W W W D R P +\t\t// U U P E E E E P I T +\t\t// A B O S +\t\t// L +\t\t12\'b0000_0000_0010: decodes <= 15\'b00_00_0010_0_1_0_0_0_0_1; // OPTION +\t\t12\'b0000_0000_0011: decodes <= 15\'b00_00_0000_0_0_0_0_0_0_0; // SLEEP +\t\t12\'b0000_0000_0100: decodes <= 15\'b00_00_0000_0_0_0_0_0_0_0; // CLRWDT +\t\t12\'b0000_0000_0101: decodes <= 15\'b00_00_0000_0_1_0_0_0_1_0; // TRIS 5 +\t\t12\'b0000_0000_0110: decodes <= 15\'b00_00_0010_0_1_0_0_0_1_0; // TRIS 6 +\t\t12\'b0000_0000_0111: decodes <= 15\'b00_00_0010_0_1_0_0_0_1_0; // TRIS 7 + // +\t\t// A A ALU W F Z C B T O +\t\t// L L O W W W W D R P +\t\t// U U P E E E E P I T +\t\t// A B O S +\t\t// L +\t\t12\'b1000_XXXX_XXXX: decodes <= 15\'b10_10_0010_1_0_0_0_0_0_0; // RETLW +\t\t12\'b1001_XXXX_XXXX: decodes <= 15\'b10_10_0010_0_0_0_0_0_0_0; // CALL +\t\t12\'b101X_XXXX_XXXX: decodes <= 15\'b10_10_0010_0_0_0_0_0_0_0; // GOTO +\t\t12\'b1100_XXXX_XXXX: decodes <= 15\'b10_10_0010_1_0_0_0_0_0_0; // MOVLW +\t\t12\'b1101_XXXX_XXXX: decodes <= 15\'b00_10_0010_1_0_1_0_0_0_0; // IORLW +\t\t12\'b1110_XXXX_XXXX: decodes <= 15\'b00_10_0001_1_0_1_0_0_0_0; // ANDLW +\t\t12\'b1111_XXXX_XXXX: decodes <= 15\'b00_10_0011_1_0_1_0_0_0_0; // XORLW + +\t\tdefault: +\t\t\tdecodes <= 15\'b00_00_0000_0_0_0_0_0_0_0; +\tendcase +end + +endmodule + + +// +// SYNTHETIC PIC 2.0 4/23/98 +// +// This is a synthesizable Microchip 16C57 compatible +// microcontroller. This core is not intended as a high fidelity model of +// the PIC, but simply a way to offer a simple processor core to people +// familiar with the PIC who also have PIC tools. +// +// pictest.v - top-level testbench (NOT SYNTHESIZABLE) +// piccpu.v - top-level synthesizable module +// picregs.v - register file instantiated under piccpu +// picalu.v - ALU instantiated under piccpu +// picidec.v - Instruction Decoder instantiated under piccpu +// hex2rom.c - C program used to translate MPLAB\'s INTEL HEX output +// into the Verilog $readmemh compatible file +// test*.asm - (note the wildcard..) Several test programs used +// to help debug the verilog. I used MPLAB and the simulator +// to develop these programs and get the expected results. +// Then, I ran them on Verilog-XL where they appeared to +// match. +// +// Copyright, Tom Coonan, \'97. +// Use freely, but not for resale as is. You may use this in your +// own projects as desired. Just don\'t try to sell it as is! +// +// + +//`define DEBUG_SHOWREADS +//`define DEBUG_SHOWWRITES + +// Memory Map: +// +// PIC Data Memory addressing is complicated. See the Data Book for full explanation.. +// +// Basically, each BANK contains 32 locations. The lowest 16 locations in ALL Banks +// are really all mapped to the same bank (bank #0). The first 8 locations are the Special +// registers like the STATUS and PC registers. The upper 16 words in each bank, really are +// unique to each bank. The smallest PIC (16C54) only has the one bank #0. +// +// So, as a programmer, what you get is this. No matter what bank you are in (FSR[6:5]) +// you always have access to your special registers and also to registers 8-15. You can +// change to a 1 of 4 banks by setting FSR[6:5] and get 4 different sets of registers +// 16-31. +// +// For numbering purposes, I\'ve numbered the registers as if they are one linear memory +// space, just like in the Data Book (see Figure 4-15 ""Direct/Indirect Addressing""). +// So, the unique 16 registers in bank #1 are named r48 - r63 (I use decimal). The +// unique registers in bank #3 are therefore r112 - r127. There is no r111 because, +// remember, the lower 16 registers each each bank are all reall the same registers 0-15. +// +// Confused?! The Data Book explains it better than I can. +// +// bank location +// XX 00rrr - The special registers are not implemented in this register file. +// XX 01rrr - The 8 common words, just above the Special Regs, same for all Banks +// 00 1rrrr - The 16 words unique to Bank #0 +// 01 1rrrr - The 16 words unique to Bank #1 +// 10 1rrrr - The 16 words unique to Bank #2 +// 11 1rrrr - The 16 words unique to Bank #3 +// +// So, +// Special Regs are location[4:3] == 00 +// Common Regs are location[4:3] == 01 +// Words in banks location[4] == 1 +// +// +// I had problems trying to use simple register file declarations that +// would always, always work right, were synthesizable and allowed +// me to easily remove locations from the memory space. SOOOooo... I +// did the brute force thing and enumerated all the locations.. +// +// Much larger spaces will probably need a RAM and whatever I do would need +// custom hacking anyway.. I don\'t see an obvious solution to all this, but +// welcome suggestions.. +// +module picregs (clk, reset, we, re, bank, location, din, dout); + +input\t\tclk; +input\t\treset; +input\t\twe; +input\t\tre; +input [1:0]\tbank;\t\t// Bank 0,1,2,3 +input [4:0]\tlocation;\t// Location +input [7:0]\tdin;\t\t// Input +output [7:0]\tdout;\t\t// Output + +//parameter\tMAX_ADDRESS = 127; + +reg [7:0]\tdout; + +integer index; + +// Declare the major busses in and out of each block. +// +reg [7:0]\tcommonblockout;\t// Data Memory common across all banks +reg [7:0]\thighblock0out;\t// Upper 16 bytes in BANK #0 +reg [7:0]\thighblock1out;\t// Upper 16 bytes in BANK #1 +reg [7:0]\thighblock2out;\t// Upper 16 bytes in BANK #2 +reg [7:0]\thighblock3out;\t// Upper 16 bytes in BANK #3 + +reg [7:0]\tcommonblockin;\t// Data Memory common across all banks +reg [7:0]\thighblock0in;\t// Upper 16 bytes in BANK #0 +reg [7:0]\thighblock1in;\t// Upper 16 bytes in BANK #1 +reg [7:0]\thighblock2in;\t// Upper 16 bytes in BANK #2 +reg [7:0]\thighblock3in;\t// Upper 16 bytes in BANK #3 + +reg\t\tcommonblocksel;\t// Select +reg\t\thighblock0sel;\t// Select +reg\t\thighblock1sel;\t// Select +reg\t\thighblock2sel;\t// Select +reg\t\thighblock3sel;\t// Select +// synopsys translate_off +integer cycle_counter; +initial cycle_counter = 0; +always @(negedge clk) begin + if (re) begin +`ifdef DEBUG_SHOWREADS + $display (""[%0d] Read: data = %0h(hex), from bank #%0d(dec) location %0h"", cycle_counter, dout, bank, location); +`endif + end + if (we) begin +`ifdef DEBUG_SHOWWRITES + $display (""[%0d] Write: data = %0h(hex), to bank #%0d(dec) location %0h"", cycle_counter, din, bank, location); +`endif + end + if (~reset) cycle_counter = cycle_counter + 1; +end +// synopsys translate_on + +// READ the Register File +// +always @(bank or location or re +\t\tor commonblockout +\t\tor highblock0out +\t\tor highblock1out +\t\tor highblock2out +\t\tor highblock3out) begin + if (re) begin + if (location[4:3] == 2\'b01) begin + // This is the lower 8 words, common to all banks, just above special registers + dout <= commonblockout;\t// Access to first 8 locations past Special Registers + end + else begin + if (location[4]) begin + // Address is in the upper 16 words on one of the 4 banks + case (bank) // synopsys full_case parallel_case + 2\'b00: dout <= highblock0out;\t// Upper 16 words of Bank #0 + 2\'b01: dout <= highblock1out;\t// Upper 16 words of Bank #1 + 2\'b10: dout <= highblock2out;\t// Upper 16 words of Bank #2 + 2\'b11: dout <= highblock3out;\t// Upper 16 words of Bank #3 + endcase + end + else begin + dout <= 8\'hff; + end + end + end + else begin + dout <= 8\'hff; + end +end + +// Initial Write logic. +// +// Generate the specific write enables based on the PIC\'s bank/location rules. +// The individual memory blocks will do the actual synchronous write. +// +always @(we or bank or location or reset) begin + if (reset) begin + commonblocksel <= 1\'b0; + highblock0sel <= 1\'b0; + highblock1sel <= 1\'b0; + highblock2sel <= 1\'b0; + highblock3sel <= 1\'b0; + end + else begin + if (we) begin + if (location[4:3] == 2\'b01) begin + // This is the lower 8 words, common to all banks, just above special registers + commonblocksel <= 1\'b1; + highblock0sel <= 1\'b0; + highblock1sel <= 1\'b0; + highblock2sel <= 1\'b0; + highblock3sel <= 1\'b0; + end + else begin + if (location[4]) begin + // Address is in the upper 16 words on one of the 4 banks + commonblocksel <= 1\'b0; + case (bank) // synopsys full_case parallel_case + 2\'b00: {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4\'b1000; // Upper 16 words of Bank #0 + 2\'b01: {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4\'b0100; // Upper 16 words of Bank #1 + 2\'b10: {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4\'b0010; // Upper 16 words of Bank #2 + 2\'b11: {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4\'b0001; // Upper 16 words of Bank #3 + endcase + end + else begin + commonblocksel <= 1\'b0; + highblock0sel <= 1\'b0; + highblock1sel <= 1\'b0; + highblock2sel <= 1\'b0; + highblock3sel <= 1\'b0; + end + end + end + else begin + commonblocksel <= 1\'b0; + highblock0sel <= 1\'b0; + highblock1sel <= 1\'b0; + highblock2sel <= 1\'b0; + highblock3sel <= 1\'b0; + end + end +end + +// *** Buses feeding the memory blocks are driven directly from din. + +always @(din) + commonblockin <= din; + +always @(din) + highblock0in <= din; + +always @(din) + highblock1in <= din; + +always @(din) + highblock2in <= din; + +always @(din) + highblock3in <= din; + +// ****************** Common Block ************* + +reg [7:0]\tr8, r9, r10, r11, r12, r13, r14, r15; + +// Read from common block +always @(location or +\t\tr8 or r9 or r10 or r11 or r12 or r13 or r14 or r15) begin + case (location[2:0]) + 3\'h0: commonblockout <= r8; + 3\'h1: commonblockout <= r9; + 3\'h2: commonblockout <= r10; + 3\'h3: commonblockout <= r11; + 3\'h4: commonblockout <= r12; + 3\'h5: commonblockout <= r13; + 3\'h6: commonblockout <= r14; + 3\'h7: commonblockout <= r15; + endcase +end + +// Write to common block +always @(posedge clk) begin + if (we & commonblocksel) begin + case (location[2:0]) + 3\'h0: r8 <= commonblockin; + 3\'h1: r9 <= commonblockin; + 3\'h2: r10 <= commonblockin; + 3\'h3: r11 <= commonblockin; + 3\'h4: r12 <= commonblockin; + 3\'h5: r13 <= commonblockin; + 3\'h6: r14 <= commonblockin; + 3\'h7: r15 <= commonblockin; + endcase + end +end + +// **************** Highblock0 **************** + +reg [7:0]\tr16, r17, r18, r19, r20, r21, r22, r23; +reg [7:0]\tr24, r25, r26, r27, r28, r29, r30, r31; + +// Read from high block bank0 +always @(location or +\t\tr16 or r17 or r18 or r19 or r20 or r21 or r22 or r23 or +\t\tr24 or r25 or r26 or r27 or r28 or r29 or r30 or r31 +) begin + case (location[3:0]) + 4\'h0: highblock0out <= r16; + 4\'h1: highblock0out <= r17; + 4\'h2: highblock0out <= r18; + 4\'h3: highblock0out <= r19; + 4\'h4: highblock0out <= r20; + 4\'h5: highblock0out <= r21; + 4\'h6: highblock0out <= r22; + 4\'h7: highblock0out <= r23; + 4\'h8: highblock0out <= r24; + 4\'h9: highblock0out <= r25; + 4\'hA: highblock0out <= r26; + 4\'hB: highblock0out <= r27; + 4\'hC: highblock0out <= r28; + 4\'hD: highblock0out <= r29; + 4\'hE: highblock0out <= r30; + 4\'hF: highblock0out <= r31; + endcase +end + +// Write to high block bank 0 +always @(posedge clk) begin + if (we & highblock0sel) begin + case (location[3:0]) + 4\'h0: r16 <= highblock0in; + 4\'h1: r17 <= highblock0in; + 4\'h2: r18 <= highblock0in; + 4\'h3: r19 <= highblock0in; + 4\'h4: r20 <= highblock0in; + 4\'h5: r21 <= highblock0in; + 4\'h6: r22 <= highblock0in; + 4\'h7: r23 <= highblock0in; + 4\'h8: r24 <= highblock0in; + 4\'h9: r25 <= highblock0in; + 4\'hA: r26 <= highblock0in; + 4\'hB: r27 <= highblock0in; + 4\'hC: r28 <= highblock0in; + 4\'hD: r29 <= highblock0in; + 4\'hE: r30 <= highblock0in; + 4\'hF: r31 <= highblock0in; + endcase + end +end + +// **************** Highblock1 **************** + +reg [7:0]\tr48, r49, r50, r51, r52, r53, r54, r55; +reg [7:0]\tr56, r57, r58, r59, r60, r61, r62, r63; + +// Read +always @(location or +\t\tr48 or r49 or r50 or r51 or r52 or r53 or r54 or r55 or +\t\tr56 or r57 or r58 or r59 or r60 or r61 or r62 or r63 +) begin + case (location[3:0]) + 4\'h0: highblock1out <= r48; + 4\'h1: highblock1out <= r49; + 4\'h2: highblock1out <= r50; + 4\'h3: highblock1out <= r51; + 4\'h4: highblock1out <= r52; + 4\'h5: highblock1out <= r53; + 4\'h6: highblock1out <= r54; + 4\'h7: highblock1out <= r55; + 4\'h8: highblock1out <= r56; + 4\'h9: highblock1out <= r57; + 4\'hA: highblock1out <= r58; + 4\'hB: highblock1out <= r59; + 4\'hC: highblock1out <= r60; + 4\'hD: highblock1out <= r61; + 4\'hE: highblock1out <= r62; + 4\'hF: highblock1out <= r63; + endcase +end + +// Write +always @(posedge clk) begin + if (we & highblock1sel) begin + case (location[3:0]) + 4\'h0: r48 <= highblock1in; + 4\'h1: r49 <= highblock1in; + 4\'h2: r50 <= highblock1in; + 4\'h3: r51 <= highblock1in; + 4\'h4: r52 <= highblock1in; + 4\'h5: r53 <= highblock1in; + 4\'h6: r54 <= highblock1in; + 4\'h7: r55 <= highblock1in; + 4\'h8: r56 <= highblock1in; + 4\'h9: r57 <= highblock1in; + 4\'hA: r58 <= highblock1in; + 4\'hB: r59 <= highblock1in; + 4\'hC: r60 <= highblock1in; + 4\'hD: r61 <= highblock1in; + 4\'hE: r62 <= highblock1in; + 4\'hF: r63 <= highblock1in; + endcase + end +end + + +// **************** Highblock2 **************** + +reg [7:0]\tr80, r81, r82, r83, r84, r85, r86, r87; +reg [7:0]\tr88, r89, r90, r91, r92, r93, r94, r95; + +// Read +always @(location or +\t\tr80 or r81 or r82 or r83 or r84 or r85 or r86 or r87 or +\t\tr88 or r89 or r90 or r91 or r92 or r93 or r94 or r95 +) begin + case (location[3:0]) + 4\'h0: highblock2out <= r80; + 4\'h1: highblock2out <= r81; + 4\'h2: highblock2out <= r82; + 4\'h3: highblock2out <= r83; + 4\'h4: highblock2out <= r84; + 4\'h5: highblock2out <= r85; + 4\'h6: highblock2out <= r86; + 4\'h7: highblock2out <= r87; + 4\'h8: highblock2out <= r88; + 4\'h9: highblock2out <= r89; + 4\'hA: highblock2out <= r90; + 4\'hB: highblock2out <= r91; + 4\'hC: highblock2out <= r92; + 4\'hD: highblock2out <= r93; + 4\'hE: highblock2out <= r94; + 4\'hF: highblock2out <= r95; + endcase +end + +// Write +always @(posedge clk) begin + if (we & highblock2sel) begin + case (location[3:0]) + 4\'h0: r80 <= highblock2in; + 4\'h1: r81 <= highblock2in; + 4\'h2: r82 <= highblock2in; + 4\'h3: r83 <= highblock2in; + 4\'h4: r84 <= highblock2in; + 4\'h5: r85 <= highblock2in; + 4\'h6: r86 <= highblock2in; + 4\'h7: r87 <= highblock2in; + 4\'h8: r88 <= highblock2in; + 4\'h9: r89 <= highblock2in; + 4\'hA: r90 <= highblock2in; + 4\'hB: r91 <= highblock2in; + 4\'hC: r92 <= highblock2in; + 4\'hD: r93 <= highblock2in; + 4\'hE: r94 <= highblock2in; + 4\'hF: r95 <= highblock2in; + endcase + end +end + +// **************** Highblock3 **************** + +// *** The Following Registers are removed because of CUSTOM Hardware (see piccpu.v) ** +// +// r129 (or 7E) +// +// ********** +reg [7:0]\tr112, r113, r114, r115, r116, r117, r118, r119; +reg [7:0]\tr120, r121, r122, r123, r124, r125, r126 /*, r127*/ ; + +// Read +always @(location or +\t\tr112 or r113 or r114 or r115 or r116 or r117 or r118 or r119 or +\t\tr120 or r121 or r122 or r123 or r124 or r125 or r126 /* or r127 */ +) begin + case (location[3:0]) + 4\'h0: highblock3out <= r112; + 4\'h1: highblock3out <= r113; + 4\'h2: highblock3out <= r114; + 4\'h3: highblock3out <= r115; + 4\'h4: highblock3out <= r116; + 4\'h5: highblock3out <= r117; + 4\'h6: highblock3out <= r118; + 4\'h7: highblock3out <= r119; + 4\'h8: highblock3out <= r120; + 4\'h9: highblock3out <= r121; + 4\'hA: highblock3out <= r122; + 4\'hB: highblock3out <= r123; + 4\'hC: highblock3out <= r124; + 4\'hD: highblock3out <= r125; + 4\'hE: highblock3out <= r126; + 4\'hF: highblock3out <= 8\'hff /* r127*/ ; + endcase +end + +// Write +always @(posedge clk) begin + if (we & highblock3sel) begin + case (location[3:0]) + 4\'h0: r112 <= highblock3in; + 4\'h1: r113 <= highblock3in; + 4\'h2: r114 <= highblock3in; + 4\'h3: r115 <= highblock3in; + 4\'h4: r116 <= highblock3in; + 4\'h5: r117 <= highblock3in; + 4\'h6: r118 <= highblock3in; + 4\'h7: r119 <= highblock3in; + 4\'h8: r120 <= highblock3in; + 4\'h9: r121 <= highblock3in; + 4\'hA: r122 <= highblock3in; + 4\'hB: r123 <= highblock3in; + 4\'hC: r124 <= highblock3in; + 4\'hD: r125 <= highblock3in; + 4\'hE: r126 <= highblock3in; + 4\'hF: /* r127 <= highblock3in */; + endcase + end +end + +// synopsys translate_off +`define CLEAR_MEMORY +`ifdef CLEAR_MEMORY +initial +begin + $display (""Clearing SRAM.""); + clear_memory; +end +task clear_memory; +begin + // Common registers + r8 = 0; + r9 = 0; + r10 = 0; + r11 = 0; + r12 = 0; + r13 = 0; + r14 = 0; + r15 = 0; + + // Bank #0 + r16 = 0; + r17 = 0; + r18 = 0; + r19 = 0; + r20 = 0; + r21 = 0; + r22 = 0; + r23 = 0; + r24 = 0; + r25 = 0; + r26 = 0; + r27 = 0; + r28 = 0; + r29 = 0; + r30 = 0; + r31 = 0; + + // Bank #1 + r48 = 0; + r49 = 0; + r50 = 0; + r51 = 0; + r52 = 0; + r53 = 0; + r54 = 0; + r55 = 0; + r56 = 0; + r57 = 0; + r58 = 0; + r59 = 0; + r60 = 0; + r61 = 0; + r62 = 0; + r63 = 0; + + // Bank #2 + r80 = 0; + r94 = 0; + + // Bank #3 + r112 = 0; + r126 = 0; + +end +endtask +`endif +// synopsys translate_on +endmodule +// +// SYNTHETIC PIC 2.0 4/23/98 +// +// This is a synthesizable Microchip 16C57 compatible +// microcontroller. This core is not intended as a high fidelity model of +// the PIC, but simply a way to offer a simple processor core to people +// familiar with the PIC who also have PIC tools. +// +// pictest.v - top-level testbench (NOT SYNTHESIZABLE) +// piccpu.v - top-level synthesizable module +// picregs.v - register file instantiated under piccpu +// picalu.v - ALU instantiated under piccpu +// picidec.v - Instruction Decoder instantiated under piccpu +// hex2rom.c - C program used to translate MPLAB\'s INTEL HEX output +// into the Verilog $readmemh compatible file +// test*.asm - (note the wildcard..) Several test programs used +// to help debug the verilog. I used MPLAB and the simulator +// to develop these programs and get the expected results. +// Then, I ran them on Verilog-XL where they appeared to +// match. +// +// Copyright, Tom Coonan, \'97. +// Use freely, but not for resale as is. You may use this in your +// own projects as desired. Just don\'t try to sell it as is! +// +// + +module pictest; + +// Select which test to run HERE.. +parameter\tTEST_NUMBER = 9; + +// *** Testing variables +// Debug flags. +integer\t\tdbg_showporta;\t// Are set in an \'initial\' for default values, +integer\t\tdbg_showportb;\t// override in specific tests... +integer\t\tdbg_showportc;\t// Setting to 1 will cause variable to be displayed. +integer\t\tdbg_showinst; +integer\t\tdbg_showrom; +integer\t\tdbg_showw; +integer\t\tdbg_showpc; + +// cycles counter variables +integer\t\tdbg_showcycles;\t// Set to 1 to see cycles +integer\t\tdbg_limitcycles;// Set to one to enable maxcycles check +integer\t\tdbg_maxcycles;\t// Limit simulation to some number of cycles. +integer\t\tcycles;\t\t// Cycles counter. + + + +// *** Interface to the PICCPU +reg\t\tclk; +reg\t\treset; +reg [7:0]\tporta; +wire [7:0]\tportb; +wire [7:0]\tportc; + +reg [11:0]\trom[0:511]; +wire [8:0]\tromaddr; +reg [11:0]\tromdata; + +// ROM Interface +always @(romaddr) begin + romdata = rom[romaddr]; +end + +reg [7:0]\tlast_debugw; +reg [8:0]\tlast_debugpc; +reg [11:0]\tlast_debuginst; +reg [7:0]\tlast_debugstatus; +wire [7:0]\tdebugw; +wire [8:0]\tdebugpc; +wire [11:0]\tdebuginst; +wire [7:0]\tdebugstatus; + +// Instantiate one PICCPU to be tested. +piccpu piccpu_inst ( + .clk\t\t(clk), + .reset\t(reset), + .paddr\t(romaddr), + .pdata\t(romdata), + .portain\t(porta), + .portbout\t(portb), + .portcout\t(portc), + .debugw\t(debugw), + .debugpc\t(debugpc), + .debuginst\t(debuginst), + .debugstatus\t(debugstatus) +); + + +// Reset +initial begin +//\t$dumpfile(""pic.vcd""); +//\t$dumpvars(0,pictest); + reset = 1; + #200; + reset = 0; +end + + +// Drive the clock input +initial begin + clk = 0; + forever begin + #50 clk = 1; + #50 clk = 0; + end +end + +// Debug defaults. Override in individual test tasks. +// +initial begin + dbg_showporta = 0; + dbg_showportb = 0; + dbg_showportc = 0; + dbg_showinst = 0; + dbg_showrom = 0; + dbg_showw = 0; + dbg_showpc = 0; + dbg_showcycles = 0; + + dbg_limitcycles = 1; + dbg_maxcycles = 50000; +end + +// Call the appropriate test task based on the TEST_NUMBER parameter set at top. +// +initial begin + case (TEST_NUMBER) + 1: test1; + 2: test2; + 3: test3; + 4: test4; + 5: test5; + 6: test6; + 7: test7; + 8: test8; + 9: test9; + default: + begin + $display (""ERROR: Unknown Test Number: %0d"", TEST_NUMBER); + $finish; + end + endcase +end + +task test1; +begin + $display (""SYNTHETIC PIC 2.0. This is TEST #1""); + #1; + + // Only Watch Port B + dbg_showportb = 1; + dbg_showcycles = 1; + + $readmemh (""TEST1.ROM"",rom); + dbg_limitcycles = 1; + dbg_maxcycles = 500; +end +endtask + +task test2; +begin + $display (""SYNTHETIC PIC 2.0. This is TEST #2""); + #1; + + // Only Watch Port B + dbg_showportb = 1; + + $readmemh (""TEST2.ROM"", rom); + dbg_limitcycles = 1; + dbg_maxcycles = 500; +end +endtask + +task test3; +begin + $display (""SYNTHETIC PIC 2.0. This is TEST #3""); + #1; + + // Only Watch Port B + dbg_showportb = 1; + + $readmemh (""TEST3.ROM"", rom); + dbg_limitcycles = 1; + dbg_maxcycles = 500; +end +endtask + +task test4; +begin + $display (""SYNTHETIC PIC 2.0. This is TEST #4""); + #1; + + // Only Watch Port B + dbg_showportb = 1; + + $readmemh (""TEST4.ROM"", rom); + dbg_limitcycles = 1; + dbg_maxcycles = 500; +end +endtask + +task test5; +begin + $display (""SYNTHETIC PIC 2.0. This is TEST #5""); + #1; + + // Only Watch Port B + dbg_showportb = 1; + + $readmemh (""TEST5.ROM"", rom); + dbg_limitcycles = 1; + dbg_maxcycles = 500; +end +endtask + +task test6; +begin + $display (""SYNTHETIC PIC 2.0. This is TEST #6""); + #1; + + // Watch Port B and C + dbg_showportb = 1; + dbg_showportc = 1; + dbg_limitcycles = 0; + + $readmemh (""TEST6.ROM"", rom); + #200; + + repeat (20) begin + porta = $random; + #10000; + end + + $finish; +end +endtask + +task test7; +begin + $display (""SYNTHETIC PIC 2.0. This is TEST #7""); + #1; + + // Only Watch Port B + dbg_showportb = 1; + + $readmemh (""TEST7.ROM"", rom); + dbg_limitcycles = 1; + dbg_maxcycles = 500; +end +endtask + +task test8; +begin + $display (""SYNTHETIC PIC 2.0. This is TEST #8""); + #1; + + // Watch All ports + dbg_showporta = 1; + dbg_showportb = 1; + dbg_showportc = 1; + + $readmemh (""TEST8.ROM"", rom); + dbg_limitcycles = 1; + dbg_maxcycles = 500; +end +endtask + +task test9; +begin + $display (""SYNTHETIC PIC 2.0. This is TEST #9""); + #1; + + // Watch All ports + dbg_showportb = 1; + dbg_showportc = 1; + + $readmemh (""contrib/TEST9.ROM"", rom); + dbg_limitcycles = 1; + dbg_maxcycles = 2000; +end +endtask + +// ******** END Of TEST TASKS + +// Cycles counter +// +initial begin + cycles = 0; + #1; + // Don\'t start counting until after reset. + @(negedge reset); + + forever begin + @(posedge clk); + cycles = cycles + 1; + if ((cycles % 256) == 0) begin + if (dbg_showcycles) begin + $display (""#Cycles = %0d"", cycles); + end + end + + if (dbg_limitcycles) begin + if (cycles > dbg_maxcycles) begin + $display (""Maximum cycles (%0d) Exceeded. Halting simulation."", dbg_maxcycles); + $finish(0); + end + end + end +end + +always @(romaddr) begin + if (dbg_showrom) + $display (""ROM Address = %h, Data = %h"", romaddr, romdata); +end + +always @(porta) begin + if (dbg_showporta) + $display (""%d: porta changes to: %h"", $time, porta); +end + +always @(portb) begin + if (dbg_showportb) + $display (""%d: portb changes to: %h"", $time, portb); +end + +always @(portc) begin + if (dbg_showportc) + $display (""%d: portc changes to: %h"", $time, portc); +end + +initial begin + if (dbg_showw) begin + forever begin + @(negedge clk); + if (debugw != last_debugw) begin + $display (""W = %0h"", debugw); + end + last_debugw = debugw; + end + end +end + +initial begin + if (dbg_showpc) begin + forever begin + @(negedge clk); + $display (""PC = %0h"", debugpc); + end + end +end + + + +reg [11:0] last_pc; + +always @(posedge clk) begin + last_pc = debugpc; +end + +initial begin + if (dbg_showinst) begin + forever begin + @(negedge clk); + +\tif (debuginst[11:0] == 12\'b0000_0000_0000) begin +\t\t$display (""%h NOP"", last_pc); +\tend +\telse if (debuginst[11:5] == 7\'b0000_001) begin +\t\t$display (""%h MOVWF f=0x%0h"", last_pc, debuginst[4:0]); +\tend +\telse if (debuginst == 12\'b0000_0100_0000) begin +\t\t$display (""%h CLRW"", last_pc); +\tend +\telse if (debuginst[11:5] == 7\'b0000_011) begin +\t\t$display (""%h CLRF f=0x%0h"", last_pc, debuginst[4:0]); +\tend +\telse if (debuginst[11:6] == 7\'b0000_10) begin +\t\tif (piccpu_inst.d == 0)\t$display (""%h SUBWF f=0x%0h, W"", last_pc, debuginst[4:0]); +\t\telse\t\t$display (""%h SUBWF f=0x%0h, f"", last_pc, debuginst[4:0]); +\tend + +\telse if (debuginst[11:6] == 7\'b0000_11) begin +\t\tif (piccpu_inst.d == 0)\t$display (""%h DECF f=0x%0h, W"", last_pc, debuginst[4:0]); +\t\telse\t\t$display (""%h DECF f=0x%0h, f"", last_pc, debuginst[4:0]); +\tend +\telse if (debuginst[11:6] == 7\'b0001_00) begin +\t\tif (piccpu_inst.d == 0)\t$display (""%h IORWF f=0x%0h, W"", last_pc, debuginst[4:0]); +\t\telse\t\t$display (""%h IORWF f=0x%0h, f"", last_pc, debuginst[4:0]); +\tend +\telse if (debuginst[11:6] == 7\'b0001_01) begin +\t\tif (piccpu_inst.d == 0)\t$display (""%h ANDWF f=0x%0h, W"", last_pc, debuginst[4:0]); +\t\telse\t\t$display (""%h ANDWF f=0x%0h, f"", last_pc, debuginst[4:0]); +\tend +\telse if (debuginst[11:6] == 7\'b0001_10) begin +\t\tif (piccpu_inst.d == 0)\t$display (""XORWF f=0x%0h, W"", last_pc, debuginst[4:0]); +\t\telse\t\t$display (""%h XORWF f=0x%0h, f"", last_pc, debuginst[4:0]); +\tend +\telse if (debuginst[11:6] == 7\'b0001_11) begin +\t\tif (piccpu_inst.d == 0)\t$display (""%h ADDWF f=0x%0h, W"", last_pc, debuginst[4:0]); +\t\telse\t\t$display (""%h ADDWF f=0x%0h, f"", last_pc, debuginst[4:0]); +\tend +\telse if (debuginst[11:6] == 7\'b0010_00) begin +\t\tif (piccpu_inst.d == 0)\t$display (""%h MOVF f=0x%0h, W"", last_pc, debuginst[4:0]); +\t\telse\t\t$display (""%h MOVF f=0x%0h, f"", last_pc, debuginst[4:0]); +\tend +\telse if (debuginst[11:6] == 7\'b0010_01) begin +\t\tif (piccpu_inst.d == 0)\t$display (""%h COMF f=0x%0h, W"", last_pc, debuginst[4:0]); +\t\telse\t\t$display (""%h COMF f=0x%0h, f"", last_pc, debuginst[4:0]); +\tend +\telse if (debuginst[11:6] == 7\'b0010_10) begin +\t\tif (piccpu_inst.d == 0)\t$display (""%h INCF f=0x%0h, W"", last_pc, debuginst[4:0]); +\t\telse\t\t$display (""%h INCF f=0x%0h, f"", last_pc, debuginst[4:0]); +\tend +\telse if (debuginst[11:6] == 7\'b0010_11) begin +\t\tif (piccpu_inst.d == 0)\t$display (""%h DECFSZ f=0x%0h, W"", last_pc, debuginst[4:0]); +\t\telse\t\t$display (""%h DECFSZ f=0x%0h, f"", last_pc, debuginst[4:0]); +\tend +\telse if (debuginst[11:6] == 7\'b0011_00) begin +\t\tif (piccpu_inst.d == 0)\t$display (""%h RRF f=0x%0h, W"", last_pc, debuginst[4:0]); +\t\telse\t\t$display (""%h RRF f=0x%0h, f"", last_pc, debuginst[4:0]); +\tend +\telse if (debuginst[11:6] == 7\'b0011_01) begin +\t\tif (piccpu_inst.d == 0)\t$display (""%h RLF f=0x%0h, W"", last_pc, debuginst[4:0]); +\t\telse\t\t$display (""%h RLF f=0x%0h, f"", last_pc, debuginst[4:0]); +\tend +\telse if (debuginst[11:6] == 7\'b0011_10) begin +\t\tif (piccpu_inst.d == 0)\t$display (""%h SWAPF f=0x%0h, W"", last_pc, debuginst[4:0]); +\t\telse\t\t$display (""%h SWAPF f=0x%0h, f"", last_pc, debuginst[4:0]); +\tend +\telse if (debuginst[11:6] == 7\'b0011_11) begin +\t\tif (piccpu_inst.d == 0)\t$display (""%h INCFSZ f=0x%0h, W"", last_pc, debuginst[4:0]); +\t\telse\t\t$display (""%h INCFSZ f=0x%0h, f"", last_pc, debuginst[4:0]); +\tend + +\t// Bit-Oriented File Register Operations +\telse if (debuginst[11:8] == 4\'b0100) begin +\t\t$display (""%h BCF f=0x%0h, bit=%0d"", last_pc, debuginst[4:0], piccpu_inst.b); +\tend +\telse if (debuginst[11:8] == 4\'b0101) begin +\t\t$display (""%h BCF f=0x%0h, bit=%0d"", last_pc, debuginst[4:0], piccpu_inst.b); +\tend +\telse if (debuginst[11:8] == 4\'b0110) begin +\t\tif (piccpu_inst.skip) $display (""%h BTFSC f=0x%0h, bit=%0d {Will Skip..}"", last_pc, debuginst[4:0], piccpu_inst.b); +\t\telse $display (""%h BTFSC f=0x%0h, bit=%0d {Will NOT Skip..}"", last_pc, debuginst[4:0], piccpu_inst.b); +\tend +\telse if (debuginst[11:8] == 4\'b0111) begin +\t\tif (piccpu_inst.skip) $display (""%h BTFSS f=0x%0h, bit=%0d {Will Skip..}"", last_pc, debuginst[4:0], piccpu_inst.b); +\t\telse $display (""%h BTFSS f=0x%0h, bit=%0d {Will NOT Skip..}"", last_pc, debuginst[4:0], piccpu_inst.b); +\tend + +\t// Literal and Control Operations +\telse if (debuginst[11:0] == 16\'b0000_0000_0010) begin +\t\t$display (""%h OPTION"", last_pc); +\tend +\telse if (debuginst[11:0] == 16\'b0000_0000_0011) begin +\t\t$display (""%h SLEEP"", last_pc); +\tend +\telse if (debuginst[11:0] == 16\'b0000_0000_0100) begin +\t\t$display (""%h CLRWDT"", last_pc); +\tend +\telse if (debuginst[11:3] == 13\'b0000_0000_0) begin +\t\t$display (""%h TRIS, f=0x%0h"", last_pc, debuginst[2:0]); +\tend +\telse if (debuginst[11:8] == 4\'b1000) begin +\t\t$display (""%h RETLW, k=0x%0h"", last_pc, debuginst[7:0]); +\tend +\telse if (debuginst[11:8] == 4\'b1001) begin +\t\t$display (""%h CALL, k=0x%0h"", last_pc, debuginst[7:0]); +\tend +\telse if (debuginst[11:9] == 3\'b101) begin +\t\t$display (""%h GOTO, k=0x%0h"", last_pc, debuginst[8:0]); +\tend +\telse if (debuginst[11:8] == 4\'b1100) begin +\t\t$display (""%h MOVLW, k=0x%0h"", last_pc, debuginst[7:0]); +\tend +\telse if (debuginst[11:8] == 4\'b1101) begin +\t\t$display (""%h IORLW, k=0x%0h"", last_pc, debuginst[7:0]); +\tend +\telse if (debuginst[11:8] == 4\'b1110) begin +\t\t$display (""%h ANDLW, k=0x%0h"", last_pc, debuginst[7:0]); +\tend +\telse if (debuginst[11:8] == 4\'b1111) begin +\t\t$display (""%h XORLW, k=0x%0h"", last_pc, debuginst[7:0]); +\tend +\telse begin +\t\t$display (""Hmmm! instruction not recognized?! %0h"", debuginst); +\tend + end + end +end + + +endmodule +" +" +// This tests the basic support for default arguments to task/function +// ports. The default port syntax gives SystemVerilog a limited form +// of variable argument lists. + +program main; + + class foo_t; + int int_val; + logic [3:0] log_val; + + task init (int int_init, logic[3:0] log_init = 4\'bzzzz); +\t int_val = int_init; +\t log_val = log_init; + endtask + + endclass : foo_t + + + foo_t obj1; + + initial begin + obj1 = new; + obj1.init(5, 4\'b1111); + if (obj1.int_val != 5 || obj1.log_val !== 4\'b1111) begin +\t $display(""FAILED -- obj1.int_val=%0d, obj1.log_val=%b"", obj1.int_val, obj1.log_val); +\t $finish; + end + + obj1 = new; + obj1.init(7); + if (obj1.int_val != 7 || obj1.log_val !== 4\'bzzzz) begin +\t $display(""FAILED -- obj1.int_val=%0d, obj1.log_val=%0s"", obj1.int_val, obj1.log_val); +\t $finish; + end + + $display(""PASSED""); + end + +endprogram // main +" +"`define PATH\t\t/usr/local/bin/ +`define STRINGIFY(x)\t`""x`"" + +module test(); + +initial begin + $display( `STRINGIFY(`PATH) ); +end + +endmodule +" +" +// This tests the basic support for default arguments to task/function +// ports. The default port syntax gives SystemVerilog a limited form +// of variable argument lists. + +program main; + + class foo_t; + int int_val; + logic[3:0] log_val; + string text_val; + + function new (int int_init, logic[3:0]log_init = 4\'bzzzz, string text_init = ""default text""); +\t this.init2(int_init, log_init, text_init); + endfunction : new + + function void init2 (int int_init, logic[3:0]log_init, string text_init); +\t int_val = int_init; +\t log_val = log_init; +\t text_val = text_init; + endfunction : init2 + + endclass : foo_t + + + foo_t obj1; + + initial begin + obj1 = new(4, 4\'b0101, ""new text""); + if (obj1.int_val != 4 || obj1.log_val !== 4\'b0101 || obj1.text_val != ""new text"") begin +\t $display(""FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s"", obj1.int_val, obj1.log_val, obj1.text_val); +\t $finish; + end + + obj1 = new(5, , ""new text""); + if (obj1.int_val != 5 || obj1.log_val !== 4\'bzzzz || obj1.text_val != ""new text"") begin +\t $display(""FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s"", obj1.int_val, obj1.log_val, obj1.text_val); +\t $finish; + end + + obj1 = new(6, 4\'b1010); + if (obj1.int_val != 6 || obj1.log_val !== 4\'b1010 || obj1.text_val != ""default text"") begin +\t $display(""FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s"", obj1.int_val, obj1.log_val, obj1.text_val); +\t $finish; + end + + obj1 = new(7); + if (obj1.int_val != 7 || obj1.text_val != ""default text"") begin +\t $display(""FAILED -- obj1.int_val=%0d, obj1.text_val=%0s"", obj1.int_val, obj1.text_val); +\t $finish; + end + + $display(""PASSED""); + end + +endprogram // main +" +"/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This trivial test has triggered problems with the empty parameter + * is encountered. The output should be: ""Hello, World."" + */ +module main; + initial begin + $display(""Hello,"",,""World.""); + $display(""PASSED""); + end +endmodule +" +"module top; + reg passed; + reg a[]; + + initial begin + passed = 1\'b1; + + a = new[3]; + + a[0] = 1\'b0; + a[1] = 1\'b1; + + if (a[0] !== 1\'b0) begin + $display(""Failed a[0], expected 1\'b0, got %b"", a[0]); + passed = 1\'b0; + end + + if (a[1] !== 1\'b1) begin + $display(""Failed a[1], expected 1\'b1, got %b"", a[1]); + passed = 1\'b0; + end + + if (a[2] !== 1\'bx) begin + $display(""Failed a[2], expected 1\'bx, got %b"", a[2]); + passed = 1\'b0; + end + + if (passed) $display(""PASSED""); + end +endmodule +" +"module test(); + +reg [1:0] IN; +wire [1:0] OUT; + +assign OUT = IN; + +initial begin + #1 $peek(IN); + #0 $display(""display : %b"", OUT); + #1 $force(IN); + #1 $peek(IN); + #0 $display(""display : %b"", OUT); + #1 $release(IN); + #0 $display(""display : %b"", OUT); + #1 $force(IN); + #1 $peek(IN); + #0 $display(""display : %b"", OUT); + #1 $poke(IN); + #1 $peek(IN); + #0 $display(""display : %b"", OUT); + #1 $release(IN); + #0 $display(""display : %b"", OUT); + #1 $poke(IN); + #1 $peek(IN); + #0 $display(""display : %b"", OUT); +end + +endmodule +" +"module signed_logic_operators_bug(); + +reg sel; +reg [7:0] a, b; +reg [5:0] c; +wire [15:0] y_mux_uu, y_mux_us, y_mux_su, y_mux_ss; +wire y_eql_uu, y_eql_us, y_eql_su, y_eql_ss; +wire y_neq_uu, y_neq_us, y_neq_su, y_neq_ss; +wire [15:0] y_sgn_u, y_sgn_s; +wire [15:0] y_add_uu, y_add_us, y_add_su, y_add_ss; +wire [15:0] y_sub_uu, y_sub_us, y_sub_su, y_sub_ss; +wire [15:0] y_mul_uu, y_mul_us, y_mul_su, y_mul_ss; +wire y_ltn_uu, y_ltn_us, y_ltn_su, y_ltn_ss; +wire y_leq_uu, y_leq_us, y_leq_su, y_leq_ss; +wire [15:0] z_mux_uu, z_mux_us, z_mux_su, z_mux_ss; +wire z_eql_uu, z_eql_us, z_eql_su, z_eql_ss; +wire z_neq_uu, z_neq_us, z_neq_su, z_neq_ss; +wire [15:0] z_sgn_u, z_sgn_s; +wire [15:0] z_add_uu, z_add_us, z_add_su, z_add_ss; +wire [15:0] z_sub_uu, z_sub_us, z_sub_su, z_sub_ss; +wire [15:0] z_mul_uu, z_mul_us, z_mul_su, z_mul_ss; +wire z_ltn_uu, z_ltn_us, z_ltn_su, z_ltn_ss; +wire z_leq_uu, z_leq_us, z_leq_su, z_leq_ss; + +integer i; + +initial begin + for (i = 0; i < 100; i = i + 1) begin + // Example vector + sel = $random; + a = $random; + b = $random; + c = $random; + + // Wait for results to be calculated + #1; + + // Display results + $display(""sel = %b"", sel); + $display(""a = %b"", a); + $display(""b = %b"", b); + $display(""c = %b"", c); + $display(""y_mux_uu = %b y_mux_us = %b y_mux_su = %b y_mux_ss = %b"", y_mux_uu, y_mux_us, y_mux_su, y_mux_ss); + $display(""z_mux_uu = %b z_mux_us = %b z_mux_su = %b z_mux_ss = %b"", z_mux_uu, z_mux_us, z_mux_su, z_mux_ss); + $display(""y_eql_uu = %b y_eql_us = %b y_eql_su = %b y_eql_ss = %b"", y_eql_uu, y_eql_us, y_eql_su, y_eql_ss); + $display(""z_eql_uu = %b z_eql_us = %b z_eql_su = %b z_eql_ss = %b"", z_eql_uu, z_eql_us, z_eql_su, z_eql_ss); + $display(""y_neq_uu = %b y_neq_us = %b y_neq_su = %b y_neq_ss = %b"", y_neq_uu, y_neq_us, y_neq_su, y_neq_ss); + $display(""z_neq_uu = %b z_neq_us = %b z_neq_su = %b z_neq_ss = %b"", z_neq_uu, z_neq_us, z_neq_su, z_neq_ss); + $display(""y_sgn_u = %b y_sgn_s = %b"" , y_sgn_u, y_sgn_s); + $display(""z_sgn_u = %b z_sgn_s = %b"" , z_sgn_u, z_sgn_s); + $display(""y_add_uu = %b y_add_us = %b y_add_su = %b y_add_ss = %b"", y_add_uu, y_add_us, y_add_su, y_add_ss); + $display(""z_add_uu = %b z_add_us = %b z_add_su = %b z_add_ss = %b"", z_add_uu, z_add_us, z_add_su, z_add_ss); + $display(""y_sub_uu = %b y_sub_us = %b y_sub_su = %b y_sub_ss = %b"", y_sub_uu, y_sub_us, y_sub_su, y_sub_ss); + $display(""z_sub_uu = %b z_sub_us = %b z_sub_su = %b z_sub_ss = %b"", z_sub_uu, z_sub_us, z_sub_su, z_sub_ss); + $display(""y_mul_uu = %b y_mul_us = %b y_mul_su = %b y_mul_ss = %b"", y_mul_uu, y_mul_us, y_mul_su, y_mul_ss); + $display(""z_mul_uu = %b z_mul_us = %b z_mul_su = %b z_mul_ss = %b"", z_mul_uu, z_mul_us, z_mul_su, z_mul_ss); + $display(""y_ltn_uu = %b y_ltn_us = %b y_ltn_su = %b y_ltn_ss = %b"", y_ltn_uu, y_ltn_us, y_ltn_su, y_ltn_ss); + $display(""z_ltn_uu = %b z_ltn_us = %b z_ltn_su = %b z_ltn_ss = %b"", z_ltn_uu, z_ltn_us, z_ltn_su, z_ltn_ss); + $display(""y_leq_uu = %b y_leq_us = %b y_leq_su = %b y_leq_ss = %b"", y_leq_uu, y_leq_us, y_leq_su, y_leq_ss); + $display(""z_leq_uu = %b z_leq_us = %b z_leq_su = %b z_leq_ss = %b"", z_leq_uu, z_leq_us, z_leq_su, z_leq_ss); + end + + // Finished + $finish(0); +end + +// Manually sign extended operators +manually_extended_operators INST1( + sel, + a, b, + c, + y_mux_uu, y_mux_us, y_mux_su, y_mux_ss, + y_eql_uu, y_eql_us, y_eql_su, y_eql_ss, + y_neq_uu, y_neq_us, y_neq_su, y_neq_ss, + y_sgn_u, y_sgn_s, + y_add_uu, y_add_us, y_add_su, y_add_ss, + y_sub_uu, y_sub_us, y_sub_su, y_sub_ss, + y_mul_uu, y_mul_us, y_mul_su, y_mul_ss, + y_ltn_uu, y_ltn_us, y_ltn_su, y_ltn_ss, + y_leq_uu, y_leq_us, y_leq_su, y_leq_ss + ); + +// $signed() sign extended operators +signed_operators INST2( + sel, + a, b, + c, + z_mux_uu, z_mux_us, z_mux_su, z_mux_ss, + z_eql_uu, z_eql_us, z_eql_su, z_eql_ss, + z_neq_uu, z_neq_us, z_neq_su, z_neq_ss, + z_sgn_u, z_sgn_s, + z_add_uu, z_add_us, z_add_su, z_add_ss, + z_sub_uu, z_sub_us, z_sub_su, z_sub_ss, + z_mul_uu, z_mul_us, z_mul_su, z_mul_ss, + z_ltn_uu, z_ltn_us, z_ltn_su, z_ltn_ss, + z_leq_uu, z_leq_us, z_leq_su, z_leq_ss + ); + +endmodule + +module signed_operators( + sel, + a, b, + c, + mux_uu, mux_us, mux_su, mux_ss, + eql_uu, eql_us, eql_su, eql_ss, + neq_uu, neq_us, neq_su, neq_ss, + sgn_u, sgn_s, + add_uu, add_us, add_su, add_ss, + sub_uu, sub_us, sub_su, sub_ss, + mul_uu, mul_us, mul_su, mul_ss, + ltn_uu, ltn_us, ltn_su, ltn_ss, + leq_uu, leq_us, leq_su, leq_ss + ); + +input sel; +input [7:0] a, b; +input [5:0] c; +output [15:0] mux_uu, mux_us, mux_su, mux_ss; +output eql_uu, eql_us, eql_su, eql_ss; +output neq_uu, neq_us, neq_su, neq_ss; +output [15:0] sgn_u, sgn_s; +output [15:0] add_uu, add_us, add_su, add_ss; +output [15:0] sub_uu, sub_us, sub_su, sub_ss; +output [15:0] mul_uu, mul_us, mul_su, mul_ss; +output ltn_uu, ltn_us, ltn_su, ltn_ss; +output leq_uu, leq_us, leq_su, leq_ss; + +// Note that the operation is only consider signed if ALL data operands are signed +// - Therefore $signed(a) does NOT sign extend ""a"" in expression ""X_su"" +// - But ""a"" and ""b"" are both sign extended before the operation in expression ""X_ss"" + +assign mux_uu = sel ? a : b ; +assign mux_us = sel ? a : $signed(b); +assign mux_su = sel ? $signed(a) : b ; +assign mux_ss = sel ? $signed(a) : $signed(b); + +assign eql_uu = a == c ; +assign eql_us = a == $signed(c); +assign eql_su = $signed(a) == c ; +assign eql_ss = $signed(a) == $signed(c); + +assign neq_uu = a != c ; +assign neq_us = a != $signed(c); +assign neq_su = $signed(a) != c ; +assign neq_ss = $signed(a) != $signed(c); + +assign sgn_u = ~$unsigned(c) ; +assign sgn_s = ~$signed(c) ; + +assign add_uu = a + c ; +assign add_us = a + $signed(c); +assign add_su = $signed(a) + c ; +assign add_ss = $signed(a) + $signed(c); + +assign sub_uu = a - c ; +assign sub_us = a - $signed(c); +assign sub_su = $signed(a) - c ; +assign sub_ss = $signed(a) - $signed(c); + +assign mul_uu = a * c ; +assign mul_us = a * $signed(c); +assign mul_su = $signed(a) * c ; +assign mul_ss = $signed(a) * $signed(c); + +assign ltn_uu = a < c ; +assign ltn_us = a < $signed(c); +assign ltn_su = $signed(a) < c ; +assign ltn_ss = $signed(a) < $signed(c); + +assign leq_uu = a <= c ; +assign leq_us = a <= $signed(c); +assign leq_su = $signed(a) <= c ; +assign leq_ss = $signed(a) <= $signed(c); + +endmodule + +module manually_extended_operators( + sel, + a, b, + c, + mux_uu, mux_us, mux_su, mux_ss, + eql_uu, eql_us, eql_su, eql_ss, + neq_uu, neq_us, neq_su, neq_ss, + sgn_u, sgn_s, + add_uu, add_us, add_su, add_ss, + sub_uu, sub_us, sub_su, sub_ss, + mul_uu, mul_us, mul_su, mul_ss, + ltn_uu, ltn_us, ltn_su, ltn_ss, + leq_uu, leq_us, leq_su, leq_ss + ); + +input sel; +input [7:0] a, b; +input [5:0] c; +output [15:0] mux_uu, mux_us, mux_su, mux_ss; +output eql_uu, eql_us, eql_su, eql_ss; +output neq_uu, neq_us, neq_su, neq_ss; +output [15:0] sgn_u, sgn_s; +output [15:0] add_uu, add_us, add_su, add_ss; +output [15:0] sub_uu, sub_us, sub_su, sub_ss; +output [15:0] mul_uu, mul_us, mul_su, mul_ss; +output ltn_uu, ltn_us, ltn_su, ltn_ss; +output leq_uu, leq_us, leq_su, leq_ss; + +// Manually zero or sign extend operands before the operation. +// - Note the operands are zero extended in ""X_uu"", ""X_us"" and ""X_su"" +// - The operands are sign extended in ""X_ss"" + +assign mux_uu = sel ? {{8{1\'b0}}, a} : {{8{1\'b0}}, b}; +assign mux_us = sel ? {{8{1\'b0}}, a} : {{8{1\'b0}}, b}; +assign mux_su = sel ? {{8{1\'b0}}, a} : {{8{1\'b0}}, b}; +assign mux_ss = sel ? {{8{a[7]}}, a} : {{8{b[7]}}, b}; + +assign eql_uu = {a} == {{2{1\'b0}}, c}; +assign eql_us = {a} == {{2{1\'b0}}, c}; +assign eql_su = {a} == {{2{1\'b0}}, c}; +assign eql_ss = {a} == {{2{c[5]}}, c}; + +assign neq_uu = {a} != {{2{1\'b0}}, c}; +assign neq_us = {a} != {{2{1\'b0}}, c}; +assign neq_su = {a} != {{2{1\'b0}}, c}; +assign neq_ss = {a} != {{2{c[5]}}, c}; + +assign sgn_u = ~{{10{1\'b0}}, c} ; +assign sgn_s = ~{{10{c[5]}}, c} ; + +assign add_uu = {{8{1\'b0}}, a} + {{10{1\'b0}}, c}; +assign add_us = {{8{1\'b0}}, a} + {{10{1\'b0}}, c}; +assign add_su = {{8{1\'b0}}, a} + {{10{1\'b0}}, c}; +assign add_ss = {{8{a[7]}}, a} + {{10{c[5]}}, c}; + +assign sub_uu = {{8{1\'b0}}, a} - {{10{1\'b0}}, c}; +assign sub_us = {{8{1\'b0}}, a} - {{10{1\'b0}}, c}; +assign sub_su = {{8{1\'b0}}, a} - {{10{1\'b0}}, c}; +assign sub_ss = {{8{a[7]}}, a} - {{10{c[5]}}, c}; + +assign mul_uu = {{8{1\'b0}}, a} * {{10{1\'b0}}, c}; +assign mul_us = {{8{1\'b0}}, a} * {{10{1\'b0}}, c}; +assign mul_su = {{8{1\'b0}}, a} * {{10{1\'b0}}, c}; +assign mul_ss = {{8{a[7]}}, a} * {{10{c[5]}}, c}; + +assign ltn_uu = {{8{1\'b0}}, a} < {{10{1\'b0}}, c}; +assign ltn_us = {{8{1\'b0}}, a} < {{10{1\'b0}}, c}; +assign ltn_su = {{8{1\'b0}}, a} < {{10{1\'b0}}, c}; +assign ltn_ss = {c[5],{7{a[7]}}, a} < {a[7],{9{c[5]}}, c}; + +assign leq_uu = {{8{1\'b0}}, a} <= {{10{1\'b0}}, c}; +assign leq_us = {{8{1\'b0}}, a} <= {{10{1\'b0}}, c}; +assign leq_su = {{8{1\'b0}}, a} <= {{10{1\'b0}}, c}; +assign leq_ss = {c[5],{7{a[7]}}, a} <= {a[7],{9{c[5]}}, c}; + +endmodule +" +"// Copyright 2007, Martin Whitaker +// This file may be freely copied for any purpose. +module macro_with_args(); + +`define\tforward_and_reverse(str1,str2,str3) /* comment */ \\ + $write(""%0s"", str1); /* comment */ \\ + $write(""..""); /* comment */ \\ + $write(""%0s"", str3); /* comment */ \\ + $write(""%0s"", str2); /* comment */ \\ + $write(""%0s"", str3); /* comment */ \\ + $write(""..""); /* comment */ \\ + $write(""%0s"", str1); /* comment */ \\ + $write(""\ +"") + +`define\tsqr( x ) (x * x) // comment + +`define\tsum( a /* comment */ , b /* comment */ ) /* comment */ \\ + (a + b) + +`define sumsqr( + a // comment + , + b // comment + ) \\ + `sum ( \\ + `sqr(a) \\ + , \\ + `sqr(b) \\ + ) + +`define no_args (a,b,c) + +`define null1 // null +`define null2 + +integer\tvalue; + +reg [79:0] astr, bstr, cstr; + +initial begin + `forward_and_reverse(""first"","" first,last "",""last""); + + $sformat(astr, ""(a%s)"", ``null1); + $sformat(bstr, "" %s "", ``no_args); + $sformat(cstr, ""(c%s)"", ``null2); + `forward_and_reverse // comment + (\t\t\t// comment + astr\t\t// comment + ,\t\t\t// comment + bstr\t\t// comment + ,\t\t\t// comment + cstr\t\t// comment + );\t\t\t// comment + + value = `sumsqr(3,4); + $display(""sumsqr(3,4) = %1d"", value); + if (value != `sqr(5)) $display(""sumsqr expansion failed""); + + value = `sumsqr + ( + (2 + 3) /* 5 */ + , + (4 + 8) /* 12 */ + ); + $display(""sumsqr(5,12) = %1d"", value); + if (value != `sqr(13)) $display(""sumsqr expansion failed""); +end + +endmodule +" +"// The IEEE standard allows the out-of-bounds part-selects to be flagged as +// compile-time errors. If they are not, this test should pass. +module top; + +reg [3:0][3:0] array; + +reg failed = 0; + +initial begin + array = 16\'h4321; + + $display(""%h"", array[-2+:2]); if (array[-2+:2] !== 8\'hxx) failed = 1; + $display(""%h"", array[-1+:2]); if (array[-1+:2] !== 8\'h1x) failed = 1; + $display(""%h"", array[ 0+:2]); if (array[ 0+:2] !== 8\'h21) failed = 1; + $display(""%h"", array[ 1+:2]); if (array[ 1+:2] !== 8\'h32) failed = 1; + $display(""%h"", array[ 2+:2]); if (array[ 2+:2] !== 8\'h43) failed = 1; + $display(""%h"", array[ 3+:2]); if (array[ 3+:2] !== 8\'hx4) failed = 1; + $display(""%h"", array[ 4+:2]); if (array[ 4+:2] !== 8\'hxx) failed = 1; + + $display(""%h"", array[-1-:2]); if (array[-1-:2] !== 8\'hxx) failed = 1; + $display(""%h"", array[ 0-:2]); if (array[ 0-:2] !== 8\'h1x) failed = 1; + $display(""%h"", array[ 1-:2]); if (array[ 1-:2] !== 8\'h21) failed = 1; + $display(""%h"", array[ 2-:2]); if (array[ 2-:2] !== 8\'h32) failed = 1; + $display(""%h"", array[ 3-:2]); if (array[ 3-:2] !== 8\'h43) failed = 1; + $display(""%h"", array[ 4-:2]); if (array[ 4-:2] !== 8\'hx4) failed = 1; + $display(""%h"", array[ 5-:2]); if (array[ 5-:2] !== 8\'hxx) failed = 1; + + $display(""%h"", array[-1:-2]); if (array[-1:-2] !== 8\'hxx) failed = 1; + $display(""%h"", array[ 0:-1]); if (array[ 0:-1] !== 8\'h1x) failed = 1; + $display(""%h"", array[ 1:0 ]); if (array[ 1:0 ] !== 8\'h21) failed = 1; + $display(""%h"", array[ 2:1 ]); if (array[ 2:1 ] !== 8\'h32) failed = 1; + $display(""%h"", array[ 3:2 ]); if (array[ 3:2 ] !== 8\'h43) failed = 1; + $display(""%h"", array[ 4:3 ]); if (array[ 4:3 ] !== 8\'hx4) failed = 1; + $display(""%h"", array[ 5:4 ]); if (array[ 5:4 ] !== 8\'hxx) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module test(); + +wire [7:0] value1; +reg [7:0] value2; + +reg clk; + +assign value1[3:0] = 4\'b1010; + +always @(posedge clk) begin + value2[3:0] <= value1; +end + +(* ivl_synthesis_off *) +initial begin + #1 clk = 0; + #1 clk = 1; + #1 clk = 0; + $display(""%b %b"", value1, value2); +`ifdef __ICARUS_SYNTH__ + if (value2 === 8\'bzzzz1010) +`else + if (value2 === 8\'bxxxx1010) +`endif + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module main; + + parameter use_wid = 4; + + reg [use_wid-1:0] d; + wire [use_wid-1:0] q; + reg\t\t clk; + + defparam\t dut.wid = use_wid; + B dut (.Q(q), .D(d), .C(clk)); + + initial begin + clk = 0; + d = 4\'b0000; + + #1 clk = 1; + #1 clk = 0; + + if (q !== 4\'b0000) begin +\t $display(""FAILED -- d=%b, q=%b"", d, q); +\t $finish; + end + + d = 4\'b1111; + #1 clk = 1; + #1 clk = 0; + + if (q !== 4\'b1111) begin +\t $display(""FAILED -- d=%b, q=%b"", d, q); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main + +/* + * although the wid paramter is default to 3 in this module, the point + * of this test is to have the instantiating module (main) give a + * different value and have that value properly handlued in all the + * situations of this module. + */ +module B + #(parameter wid = 3) + (output [wid-1:0] Q, + input [wid-1:0] D, + input C); + + // the override from main will cause this to be a width of 4. + prim U [wid-1:0] (Q, D, C); + //prim U [wid-1:0] (.Q(Q), .D(D), .C(C)); + +endmodule // B + +module prim(output reg Q, input D, C); + + always @(posedge C) + Q <= D; + +endmodule // prim +" +"`timescale 1ns/1ps + +module test; + + reg pass; + reg c1reg,c2reg; + wire rla, rlc, rlo; + wire rha, rhc, rho; + wire c1 = c1reg; + wire c2 = c2reg; + + // Pull the pins opposite to the arm. + pulldown pd1 (rla); + pullup (weak1) pu1 (rlc,rlo); + + pulldown (weak0) pd2 (rhc,rho); + pullup pu2 (rha); + + SPDT_RELAY rl (.COIL1(c1), .COIL2(c2), .ARM(rla), .NC(rlc), .NO(rlo)); + SPDT_RELAY rh (.COIL1(c1), .COIL2(c2), .ARM(rha), .NC(rhc), .NO(rho)); + + initial begin + pass = 1\'b1; + + // Test both coil terminals low. + c1reg = 0; + c2reg = 0; + #10; + if (rla !== 1\'b0 || rlo !== 1\'b1 || rlc !== 1\'b0) begin + $display(""Failed R1 coil (%b-%b), arm=%b, NC=%b, NO=%b"", + c1, c2, rla, rlc, rlo); + pass = 1\'b0; + end + if (rha !== 1\'b1 || rho !== 1\'b0 || rhc !== 1\'b1) begin + $display(""Failed R2 coil (%b-%b), arm=%b, NC=%b, NO=%b"", + c1, c2, rha, rhc, rho); + pass = 1\'b0; + end + + // Test c1 low and c2 high. + c2reg = 1; + #10; + if (rla !== 1\'b0 || rlo !== 1\'b0 || rlc !== 1\'b1) begin + $display(""Failed R1 coil (%b-%b), arm=%b, NC=%b, NO=%b"", + c1, c2, rla, rlc, rlo); + pass = 1\'b0; + end + if (rha !== 1\'b1 || rho !== 1\'b1 || rhc !== 1\'b0) begin + $display(""Failed R2 coil (%b-%b), arm=%b, NC=%b, NO=%b"", + c1, c2, rha, rhc, rho); + pass = 1\'b0; + end + + // Test both coil terminal high. + c1reg = 1; + #10; + if (rla !== 1\'b0 || rlo !== 1\'b1 || rlc !== 1\'b0) begin + $display(""Failed R1 coil (%b-%b), arm=%b, NC=%b, NO=%b"", + c1, c2, rla, rlc, rlo); + pass = 1\'b0; + end + if (rha !== 1\'b1 || rho !== 1\'b0 || rhc !== 1\'b1) begin + $display(""Failed R2 coil (%b-%b), arm=%b, NC=%b, NO=%b"", + c1, c2, rha, rhc, rho); + pass = 1\'b0; + end + + // Test c1 high and c2 low. + c2reg = 0; + #10; + if (rla !== 1\'b0 || rlo !== 1\'b0 || rlc !== 1\'b1) begin + $display(""Failed R1 coil (%b-%b), arm=%b, NC=%b, NO=%b"", + c1, c2, rla, rlc, rlo); + pass = 1\'b0; + end + if (rha !== 1\'b1 || rho !== 1\'b1 || rhc !== 1\'b0) begin + $display(""Failed R2 coil (%b-%b), arm=%b, NC=%b, NO=%b"", + c1, c2, rha, rhc, rho); + pass = 1\'b0; + end + + if (pass) $display (""PASSED""); + $finish; + end +endmodule + + +module SPDT_RELAY (COIL1, COIL2, ARM, NC, NO); + inout COIL1, COIL2, ARM, NC, NO; + wire coil = ((COIL1===1\'b1) && (COIL2===1\'b0)) || + ((COIL1===1\'b0) && (COIL2===1\'b1)); + + wire #1 dly_coil = coil; + wire coil_on = coil & dly_coil; + wire coil_off = !coil & !dly_coil; + + tranif1 t1 (ARM,NC,coil_off); + tranif1 t2 (ARM,NO,coil_on); +endmodule +" +"// +// Copyright (c) 2000 Paul Campbell (paul@verifarm.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +module compl1001; +\treg\t[104:86]r0; +\treg\t[261:230]r1; +\treg\t[101:78]r2; +\treg\t[216:215]r3; +\treg\t[140:123]r4; +\treg\t[70:53]r5; +\treg\t[150:150]r6; +\treg\t[143:133]r7; +\treg\t[261:239]r8; +\treg\t[228:211]r9; +\treg\t[273:244]r10; +\treg\t[42:21]r11; +\treg\t[137:130]r12; +\treg\t[103:96]r13; +\treg\t[257:239]r14; +\treg\t[230:205]r15; +\treg\t[216:212]r16; +\treg\t[64:40]r17; +\treg\t[156:155]r18; +\treg\t[103:94]r19; +\treg\t[216:204]r20; +\treg\t[170:165]r21; +\treg\t[25:22]r22; +\treg\t[125:105]r23; +\treg\t[57:32]r24; +\treg\t[261:250]r25; +\treg\t[32:13]r26; +\treg\t[251:246]r27; +\treg\t[210:209]r28; +\treg\t[121:119]r29; +\treg\t[57:55]r30; +\treg\t[255:253]r31; +\treg\t[196:174]r32; +\treg\t[26:26]r33; +\treg\t[216:215]r34; +\treg\t[238:224]r35; +\treg\t[212:207]r36; +\treg\t[32:11]r37; +\treg\t[89:60]r38; +\treg\t[246:237]r39; +\treg\t[50:25]r40; +\treg\t[43:29]r41; +\treg\t[94:66]r42; +\treg\t[235:222]r43; +\treg\t[213:190]r44; +\treg\t[102:81]r45; +\treg\t[211:208]r46; +\treg\t[108:91]r47; +\treg\t[189:188]r48; +\treg\t[97:84]r49; +\treg\t[108:90]r50; +\treg\t[124:116]r51; +\treg\t[113:92]r52; +\treg\t[278:254]r53; +\treg\t[98:94]r54; +\treg\t[43:42]r55; +\treg\t[191:178]r56; +\treg\t[230:211]r57; +\treg\t[250:233]r58; +\treg\t[236:229]r59; +\treg\t[65:34]r60; +\treg\t[155:132]r61; +\treg\t[32:18]r62; +\treg\t[253:253]r63; +\treg\t[243:215]r64; +\treg\t[133:109]r65; +\treg\t[133:124]r66; +\treg\t[66:51]r67; +\treg\t[94:75]r68; +\treg\t[31:23]r69; +\treg\t[230:214]r70; +\treg\t[75:55]r71; +\treg\t[209:196]r72; +\treg\t[200:181]r73; +\treg\t[101:92]r74; +\treg\t[43:34]r75; +\treg\t[228:211]r76; +\treg\t[171:169]r77; +\treg\t[112:86]r78; +\treg\t[257:252]r79; +\treg\t[214:214]r80; +\treg\t[279:254]r81; +\treg\t[149:149]r82; +\treg\t[80:53]r83; +\treg\t[140:117]r84; +\treg\t[265:238]r85; +\treg\t[277:251]r86; +\treg\t[71:45]r87; +\treg\t[56:38]r88; +\treg\t[95:91]r89; +\treg\t[271:242]r90; +\treg\t[187:174]r91; +\treg\t[176:171]r92; +\treg\t[100:88]r93; +\treg\t[273:242]r94; +\treg\t[137:111]r95; +\treg\t[148:144]r96; +\treg\t[168:159]r97; +\treg\t[269:254]r98; +\treg\t[149:145]r99; +\treg\t[202:176]r100; +\treg\t[37:26]r101; +\treg\t[62:37]r102; +\treg\t[47:36]r103; +\treg\t[195:176]r104; +\treg\t[124:93]r105; +\treg\t[8:4]r106; +\treg\t[170:161]r107; +\treg\t[150:129]r108; +\treg\t[54:40]r109; +\treg\t[86:64]r110; +\treg\t[132:111]r111; +\treg\t[224:224]r112; +\treg\t[262:232]r113; +\treg\t[27:14]r114; +\treg\t[99:97]r115; +\treg\t[234:214]r116; +\treg\t[66:52]r117; +\treg\t[178:173]r118; +\treg\t[83:52]r119; +\treg\t[67:58]r120; +\treg\t[110:82]r121; +\treg\t[255:232]r122; +\treg\t[41:19]r123; +\treg\t[67:45]r124; +\treg\t[179:178]r125; +\treg\t[173:151]r126; +\treg\t[35:20]r127; +\treg\t[168:155]r128; +\treg\t[129:112]r129; +\treg\t[47:29]r130; +\treg\t[199:186]r131; +\treg\t[217:190]r132; +\treg\t[241:212]r133; +\treg\t[256:233]r134; +\treg\t[129:116]r135; +\treg\t[168:157]r136; +\treg\t[230:211]r137; +\treg\t[261:248]r138; +\treg\t[39:27]r139; +\treg\t[137:135]r140; +\treg\t[169:142]r141; +\treg\t[103:79]r142; +\treg\t[118:118]r143; +\treg\t[156:154]r144; +\treg\t[234:208]r145; +\treg\t[154:131]r146; +\treg\t[211:183]r147; +\treg\t[74:65]r148; +\treg\t[161:145]r149; +\treg\t[58:51]r150; +\treg\t[268:253]r151; +\treg\t[193:175]r152; +\treg\t[148:120]r153; +\treg\t[169:138]r154; +\treg\t[213:210]r155; +\treg\t[119:103]r156; +\treg\t[104:83]r157; +\treg\t[212:193]r158; +\treg\t[172:172]r159; +\treg\t[206:182]r160; +\treg\t[176:159]r161; +\treg\t[172:153]r162; +\treg\t[119:110]r163; +\treg\t[75:53]r164; +\treg\t[5:5]r165; +\treg\t[238:226]r166; +\treg\t[258:230]r167; +\treg\t[95:74]r168; +\treg\t[231:216]r169; +\treg\t[252:248]r170; +\treg\t[98:79]r171; +\treg\t[191:166]r172; +\treg\t[161:154]r173; +\treg\t[67:67]r174; +\treg\t[214:207]r175; +\treg\t[204:198]r176; +\treg\t[131:118]r177; +\treg\t[212:181]r178; +\treg\t[258:248]r179; +\treg\t[141:116]r180; +\treg\t[201:198]r181; +\treg\t[108:78]r182; +\treg\t[83:72]r183; +\treg\t[81:69]r184; +\treg\t[144:140]r185; +\treg\t[174:154]r186; +\treg\t[191:171]r187; +\treg\t[48:27]r188; +\treg\t[260:251]r189; +\treg\t[69:47]r190; +\treg\t[259:246]r191; +\treg\t[167:162]r192; +\treg\t[245:237]r193; +\treg\t[67:49]r194; +\treg\t[133:108]r195; +\treg\t[224:213]r196; +\treg\t[126:108]r197; +\treg\t[230:208]r198; +\treg\t[80:59]r199; +\treg\t[136:120]r200; +\treg\t[62:44]r201; +\treg\t[206:198]r202; +\treg\t[284:254]r203; +\treg\t[184:158]r204; +\treg\t[32:13]r205; +\treg\t[233:220]r206; +\treg\t[69:59]r207; +\treg\t[46:34]r208; +\treg\t[181:156]r209; +\treg\t[105:100]r210; +\treg\t[240:228]r211; +\treg\t[51:48]r212; +\treg\t[149:144]r213; +\treg\t[201:190]r214; +\treg\t[234:215]r215; +\treg\t[212:188]r216; +\treg\t[98:79]r217; +\treg\t[237:214]r218; +\treg\t[105:96]r219; +\treg\t[10:7]r220; +\treg\t[134:105]r221; +\treg\t[192:162]r222; +\treg\t[202:180]r223; +\treg\t[50:31]r224; +\treg\t[50:26]r225; +\treg\t[181:166]r226; +\treg\t[146:117]r227; +\treg\t[118:93]r228; +\treg\t[222:202]r229; +\treg\t[135:114]r230; +\treg\t[78:51]r231; +\treg\t[260:231]r232; +\treg\t[172:142]r233; +\treg\t[58:32]r234; +\treg\t[245:232]r235; +\treg\t[51:46]r236; +\treg\t[198:167]r237; +\treg\t[217:217]r238; +\treg\t[130:121]r239; +\treg\t[130:111]r240; +\treg\t[28:0]r241; +\treg\t[87:79]r242; +\treg\t[60:58]r243; +\treg\t[59:53]r244; +\treg\t[200:178]r245; +\treg\t[81:67]r246; +\treg\t[110:104]r247; +\treg\t[233:211]r248; +\treg\t[139:129]r249; +\treg\t[262:254]r250; +\treg\t[177:175]r251; +\treg\t[262:236]r252; +\treg\t[111:94]r253; +\treg\t[230:218]r254; +\treg\t[191:164]r255; +\tinitial begin +\t\tr0 = 32'h2eec; +\t\tr1 = 32'h1584; +\t\tr2 = 32'h47e5; +\t\tr3 = 32'h587f; +\t\tr4 = 32'hab8; +\t\tr5 = 32'h71e9; +\t\tr6 = 32'h4e49; +\t\tr7 = 32'h6794; +\t\tr8 = 32'h5c8e; +\t\tr9 = 32'h1a61; +\t\tr10 = 32'h55df; +\t\tr11 = 32'h2da5; +\t\tr12 = 32'h3d89; +\t\tr13 = 32'h76ab; +\t\tr14 = 32'h6d8e; +\t\tr15 = 32'h66ed; +\t\tr16 = 32'hc57; +\t\tr17 = 32'h615c; +\t\tr18 = 32'h29c0; +\t\tr19 = 32'h7ed1; +\t\tr20 = 32'h11c7; +\t\tr21 = 32'h5f7a; +\t\tr22 = 32'h59cc; +\t\tr23 = 32'h36df; +\t\tr24 = 32'h6217; +\t\tr25 = 32'h35da; +\t\tr26 = 32'h2827; +\t\tr27 = 32'h418b; +\t\tr28 = 32'h6fb; +\t\tr29 = 32'h7839; +\t\tr30 = 32'h114b; +\t\tr31 = 32'h4ca3; +\t\tr32 = 32'h3e6d; +\t\tr33 = 32'h6e1d; +\t\tr34 = 32'h5d63; +\t\tr35 = 32'h3797; +\t\tr36 = 32'h5a38; +\t\tr37 = 32'h6969; +\t\tr38 = 32'h8bb; +\t\tr39 = 32'h716b; +\t\tr40 = 32'hc42; +\t\tr41 = 32'h6ac3; +\t\tr42 = 32'h46ea; +\t\tr43 = 32'h3a78; +\t\tr44 = 32'h2b9c; +\t\tr45 = 32'h2fa6; +\t\tr46 = 32'hcbc; +\t\tr47 = 32'h45e6; +\t\tr48 = 32'h3e4b; +\t\tr49 = 32'h646; +\t\tr50 = 32'h4ce2; +\t\tr51 = 32'h76e9; +\t\tr52 = 32'h53d4; +\t\tr53 = 32'h327; +\t\tr54 = 32'h5359; +\t\tr55 = 32'h35be; +\t\tr56 = 32'h7c89; +\t\tr57 = 32'h747c; +\t\tr58 = 32'h6b9a; +\t\tr59 = 32'h1864; +\t\tr60 = 32'h6996; +\t\tr61 = 32'h2f40; +\t\tr62 = 32'h3d86; +\t\tr63 = 32'h5b1b; +\t\tr64 = 32'h1ca; +\t\tr65 = 32'h1216; +\t\tr66 = 32'hd10; +\t\tr67 = 32'h649e; +\t\tr68 = 32'h7727; +\t\tr69 = 32'h59e1; +\t\tr70 = 32'h48a8; +\t\tr71 = 32'h521f; +\t\tr72 = 32'h2928; +\t\tr73 = 32'h2423; +\t\tr74 = 32'h126b; +\t\tr75 = 32'h4707; +\t\tr76 = 32'h5fd4; +\t\tr77 = 32'h3b16; +\t\tr78 = 32'h300c; +\t\tr79 = 32'h7c6a; +\t\tr80 = 32'h2b87; +\t\tr81 = 32'h78c; +\t\tr82 = 32'hd80; +\t\tr83 = 32'h4c4c; +\t\tr84 = 32'h757b; +\t\tr85 = 32'h4487; +\t\tr86 = 32'h3e6c; +\t\tr87 = 32'h3496; +\t\tr88 = 32'hd19; +\t\tr89 = 32'h5098; +\t\tr90 = 32'h2a4f; +\t\tr91 = 32'hdd6; +\t\tr92 = 32'h3e02; +\t\tr93 = 32'h38f8; +\t\tr94 = 32'h4f6f; +\t\tr95 = 32'h71ba; +\t\tr96 = 32'h3adc; +\t\tr97 = 32'h5a68; +\t\tr98 = 32'h4884; +\t\tr99 = 32'hd4a; +\t\tr100 = 32'h68dd; +\t\tr101 = 32'h33c8; +\t\tr102 = 32'h127; +\t\tr103 = 32'h5ae8; +\t\tr104 = 32'h5818; +\t\tr105 = 32'h4679; +\t\tr106 = 32'h44f9; +\t\tr107 = 32'h9; +\t\tr108 = 32'h748a; +\t\tr109 = 32'h2074; +\t\tr110 = 32'h1593; +\t\tr111 = 32'h4ab1; +\t\tr112 = 32'h3be4; +\t\tr113 = 32'h6c27; +\t\tr114 = 32'h7331; +\t\tr115 = 32'hab0; +\t\tr116 = 32'h416; +\t\tr117 = 32'h2213; +\t\tr118 = 32'h41d; +\t\tr119 = 32'h429e; +\t\tr120 = 32'h1ea0; +\t\tr121 = 32'h3827; +\t\tr122 = 32'h46dd; +\t\tr123 = 32'h6c97; +\t\tr124 = 32'h6497; +\t\tr125 = 32'h6ada; +\t\tr126 = 32'h3b1c; +\t\tr127 = 32'h4eb7; +\t\tr128 = 32'h7779; +\t\tr129 = 32'h7c0a; +\t\tr130 = 32'h2d59; +\t\tr131 = 32'h1b54; +\t\tr132 = 32'h42b2; +\t\tr133 = 32'h397; +\t\tr134 = 32'h1151; +\t\tr135 = 32'h58fe; +\t\tr136 = 32'h9ea; +\t\tr137 = 32'h2dbe; +\t\tr138 = 32'h172d; +\t\tr139 = 32'h4e38; +\t\tr140 = 32'h1015; +\t\tr141 = 32'h337; +\t\tr142 = 32'h676c; +\t\tr143 = 32'h6cf3; +\t\tr144 = 32'h2338; +\t\tr145 = 32'h170f; +\t\tr146 = 32'h318e; +\t\tr147 = 32'h79ce; +\t\tr148 = 32'h18fc; +\t\tr149 = 32'h3643; +\t\tr150 = 32'h7986; +\t\tr151 = 32'h6b10; +\t\tr152 = 32'h7f4; +\t\tr153 = 32'h7520; +\t\tr154 = 32'h4fdd; +\t\tr155 = 32'h3b61; +\t\tr156 = 32'h49ae; +\t\tr157 = 32'h365d; +\t\tr158 = 32'h60a6; +\t\tr159 = 32'h2c4b; +\t\tr160 = 32'h117b; +\t\tr161 = 32'h7f4; +\t\tr162 = 32'h525; +\t\tr163 = 32'h3475; +\t\tr164 = 32'h23fe; +\t\tr165 = 32'h71c5; +\t\tr166 = 32'h443e; +\t\tr167 = 32'h1599; +\t\tr168 = 32'h7b77; +\t\tr169 = 32'h11ea; +\t\tr170 = 32'h6d9f; +\t\tr171 = 32'h564a; +\t\tr172 = 32'h64cd; +\t\tr173 = 32'h22d8; +\t\tr174 = 32'h3bad; +\t\tr175 = 32'h1b68; +\t\tr176 = 32'h615d; +\t\tr177 = 32'h473a; +\t\tr178 = 32'h282f; +\t\tr179 = 32'h1d5e; +\t\tr180 = 32'h5985; +\t\tr181 = 32'h378d; +\t\tr182 = 32'h5fbd; +\t\tr183 = 32'h3522; +\t\tr184 = 32'h6bef; +\t\tr185 = 32'h2d7c; +\t\tr186 = 32'h7fe6; +\t\tr187 = 32'h3cea; +\t\tr188 = 32'h659d; +\t\tr189 = 32'h28f9; +\t\tr190 = 32'hc24; +\t\tr191 = 32'h40af; +\t\tr192 = 32'h2eb9; +\t\tr193 = 32'h6b1f; +\t\tr194 = 32'h4581; +\t\tr195 = 32'h3a63; +\t\tr196 = 32'h381a; +\t\tr197 = 32'h42cb; +\t\tr198 = 32'h5105; +\t\tr199 = 32'h55f1; +\t\tr200 = 32'h3596; +\t\tr201 = 32'h6f4; +\t\tr202 = 32'h58e6; +\t\tr203 = 32'h78f8; +\t\tr204 = 32'h310a; +\t\tr205 = 32'h5ace; +\t\tr206 = 32'h146f; +\t\tr207 = 32'ha48; +\t\tr208 = 32'h422a; +\t\tr209 = 32'h17a3; +\t\tr210 = 32'h62ac; +\t\tr211 = 32'h3518; +\t\tr212 = 32'h7709; +\t\tr213 = 32'h786c; +\t\tr214 = 32'h63db; +\t\tr215 = 32'h240d; +\t\tr216 = 32'h3967; +\t\tr217 = 32'h6332; +\t\tr218 = 32'h3d92; +\t\tr219 = 32'h6fec; +\t\tr220 = 32'h3cbe; +\t\tr221 = 32'h6c27; +\t\tr222 = 32'h75af; +\t\tr223 = 32'h3e19; +\t\tr224 = 32'h410b; +\t\tr225 = 32'h6e83; +\t\tr226 = 32'h1004; +\t\tr227 = 32'h4ad7; +\t\tr228 = 32'h365d; +\t\tr229 = 32'h5720; +\t\tr230 = 32'h5abf; +\t\tr231 = 32'h5b3e; +\t\tr232 = 32'hd1f; +\t\tr233 = 32'h7cd4; +\t\tr234 = 32'h159b; +\t\tr235 = 32'h52fb; +\t\tr236 = 32'h3f25; +\t\tr237 = 32'h2292; +\t\tr238 = 32'h5fc9; +\t\tr239 = 32'h69ca; +\t\tr240 = 32'h5d77; +\t\tr241 = 32'h7f3f; +\t\tr242 = 32'h189c; +\t\tr243 = 32'h3cb5; +\t\tr244 = 32'h2ee1; +\t\tr245 = 32'h6755; +\t\tr246 = 32'h1ef7; +\t\tr247 = 32'h370a; +\t\tr248 = 32'h2b36; +\t\tr249 = 32'h743a; +\t\tr250 = 32'h1b77; +\t\tr251 = 32'hf1d; +\t\tr252 = 32'h5f68; +\t\tr253 = 32'h455e; +\t\tr254 = 32'h415f; +\t\tr255 = 32'h52c2; +\t\t#10; r73 = r189; +\t\t#10; r132 = 11'h783; +\t\t#10; r86 = ( ( & ( (14'h1136 ^ ((25'hd6c == $time) * r2)))) != 26'h1ef2); +\t\t#10; r246 = ( | ( 22'h6337)); +\t\t#10; r35 = (r155 * ((r190 > (((((((r127 % ( | ( r81))) & r150) | r11) !== (((r207 <= (22'h4d2b ? ((r158 == ( - ( r219))) | 13'hdae) : r43)) != ((r97 > ((r240 != ((26'h259a * 13'h465) >= (5'h2 * 11'h7ed))) % (((12'h279 < 28'h3026) || 4'h1) && r111))) & ( ! ( ( ! ( (16'h7a99 <= 4'h6))))))) & 26'h5fa4)) && (((r15 | (( ( | ( ( ~ ( (r235 && 31'h2eeb))))) / r90) !== r56)) <= ((22'h640f !== r182) <= (31'h1b37 !== ( ( | ( (((9'hc9 / 32'h7c3b) - (8'ha6 - 3'h2)) == ((12'h36b - 9'h171) < ( + ( 23'h425)))))) % r72)))) + $time)) > r1) !== 18'h6d7b)) >= 28'h6e25)); +\t\t#10; r144 = 4'h9; +\t\t#10; r206 = ( ( | ( 12'h4ff)) | 17'h43ef); +\t\t#10; r138 = $time; +\t\t#10; r74 = 22'h38ad; +\t\t#10; r49 = r2; +\t\t#10; r50 = ((31'h744c ? ((r164 && r191) >= 16'h6c50) : ((r137 / ((1'h0 ^ ((r169 >= (((20'h5ab3 == ( & ( ( & ( (21'hb12 < (7'h16 || 10'h24e))))))) != r155) - ( | ( ( + ( ( ( ! ( r166)) % (26'h296c > 32'h62ed)))))))) === ( + ( ( | ( r187)))))) - r92)) * r99)) >= r189); +\t\t#10; r150 = ((12'h24d != r248) / ( & ( (((r34 - ( ! ( 20'h40cd))) === (((7'h52 > (25'h7f1d || 1'h1)) && 5'h12) ? ( ^ ( (r61 && ( ~ ( ( ( + ( ( ! ( (r73 <= ( | ( ( ( & ( 28'h57c)) / (24'h60a8 < 28'h7acc))))))))) | (8'h61 < ( ! ( (r184 === ( ~ ( (r72 == (15'h508 / 24'h5073)))))))))))))) : r24)) | r86)))); +\t\t#10; r73 = ( ( + ( ( ( ~ ( ((((20'h23e2 === ((11'h649 ^ 21'hfee) | ((r35 % 30'h856) <= r67))) !== ((r183 || (((r19 / (15'h304d + 25'h523a)) && 17'h7692) - r178)) - (((((25'h34f5 || r199) === r255) <= r12) !== (((((5'hb / 5'h11) == (5'h17 | 24'h408)) / (r255 ^ r181)) && ( & ( 14'h2e37))) === ((17'h1e79 <= r84) / (r0 !== ( ^ ( (26'h587b <= 20'h7403))))))) >= ( - ( r184))))) !== ( - ( r248))) === $time))) * 12'h5))) || r191); +\t\t#10; r134 = (1'h1 === 24'h12a0); +\t\t#10; r214 = 30'h3839; +\t\t#10; r255 = 30'h242b; +\t\t#10; r7 = 9'h132; +\t\t#10; r130 = r65; +\t\t#10; r64 = r162; +\t\t#10; r174 = ((r91 <= (r231 + ( - ( 1'h1)))) <= ((((r93 <= (r183 / ( ( & ( ( ^ ( ( ^ ( 1'h1)))))) <= r75))) * 12'ha95) & r27) | ((((((20'hf1f === ((r175 >= 20'h3632) | ((r109 & (r88 < r248)) < 10'h2e5))) & r37) % $stime) || ( ( + ( ( ! ( r160)))) & r17)) > ( ( | ( (r124 & ( - ( ( - ( (22'hd2b != ( ! ( r196)))))))))) && r84)) | (r51 / 16'h5f0d)))); +\t\t#10; r41 = ( ( ^ ( ( ( ^ ( ((3'h6 >= (r215 & (31'h3d8b && ( ^ ( 5'h11))))) <= $time))) & ( & ( r7))))) * ( ( - ( (12'he7e ? ( + ( ((3'h2 ^ r250) & (r214 <= (r19 - r249))))) : (r140 | r104)))) || r250)); +\t\t#10; r195 = 9'h1ac; +\t\t#10; r242 = 21'h527c; +\t\t#10; r143 = ((((((r68 ? (6'h1e ? ( ^ ( 26'h4f04)) : ( - ( ( ( - ( $time)) - (( ( + ( r96)) !== (r185 / 6'h22)) ? r133 : r2))))) : r20) * ((28'h20ec % r109) / ( + ( ( ( & ( 1'h0)) | (13'h13f1 === ((r96 - r204) * ( | ( 1'h0))))))))) === ((23'h4c6b / (20'h7a3b === r184)) == (( ( ! ( ( ( + ( (((7'h59 ? ((3'h4 <= 13'had1) | 15'h1a5c) : r123) % $stime) == ( + ( (((15'h74fe === 2'h0) == ( + ( 3'h0))) <= ((26'h2e1 | 8'h3b) + (16'h76a4 == 26'h645a)))))))) + ( + ( ((r123 & (r37 != (r211 >= (21'hcee < 18'h2845)))) >= (27'h5efd ^ r116))))))) | ((25'h4cd6 + r74) ? r115 : ((r133 - ((r198 ? r55 : (($stime % 17'h38a5) | $time)) === ( ~ ( r217)))) ? (r250 !== 19'h49e1) : ( ! ( r15))))) == r224))) - ((r244 > (r229 - ( & ( (( ( + ( r244)) != ( ! ( ((29'h6d1b === 10'h364) - ((17'h43c9 & ( + ( r238))) == r113))))) % 30'h7539))))) & ( | ( 23'h4205)))) | 5'h19) <= ( ! ( r92))); +\t\t#10; r74 = r232; +\t\t#10; r31 = ( ( ~ ( r181)) && ( - ( 7'h8))); +\t\t#10; r75 = (6'h10 === r188); +\t\t#10; r75 = ( ( & ( $stime)) + ( - ( ((( ( | ( (16'h1c8a % 32'h503f))) ? ((r161 ^ r59) == ( ! ( ( - ( (((r191 === r182) == ( ( + ( ( | ( r168)))) > ( ( | ( 1'h1)) * (( ( ^ ( 32'h2923)) != (14'h3cd7 * 24'h1162)) > (25'h7bc2 - 6'hd))))) - r31)))))) : ((4'hd & ( ^ ( (r130 - ((r96 === r154) == (32'h2fba >= ( | ( 4'h3)))))))) >= ( & ( (((r253 !== 18'h4189) >= (11'h679 < r133)) * r109))))) != $time) !== ( ( ~ ( (((21'h5dd3 / (10'h22e ^ (( ( ! ( ( + ( ( & ( (21'h5c32 * 12'h7e))))))) - ((((16'h132e || 23'hf58) <= 21'h1302) ^ ((2'h1 | 4'hb) - r113)) & (r207 || 24'h1190))) || ((r224 && r246) > 7'h19)))) % ( ( ~ ( r150)) - ((1'h1 & 24'h7aa2) | ($stime !== r24)))) >= 14'h29de))) !== ( + ( 10'h207))))))); +\t\t#10; r195 = 4'h7; +\t\t#10; r129 = r208; +\t\t#10; r152 = r144; +\t\t#10; r9 = (( ( ! ( ( & ( (r39 >= r176))))) - 5'h6) ^ 12'h837); +\t\t#10; r159 = ( + ( ((r132 <= (((( ( + ( (24'h5c17 + r12))) == 24'h3ca7) > r164) >= ( ( ^ ( r114)) > r126)) < ((r0 & ( ~ ( (22'h7ece <= (((2'h3 % (r90 + ( ( + ( 6'h1)) | $stime))) | r51) !== (27'h1d94 == (r189 & r252))))))) ? 2'h0 : r110))) <= ((r124 % r178) <= ( ( & ( $time)) - (((r22 == 27'h4da6) != 19'h14be) ^ (r155 / r52))))))); +\t\t#10; r92 = (28'h4175 + ( - ( ((( ( ~ ( (4'hf % (($stime ? 5'hf : ((((4'h8 | (r118 !== 10'h222)) != ($time / r53)) ? ( ~ ( r49)) : ((r251 > r162) - r163)) == 17'h72a0)) && (16'h486b === r203))))) + r130) + 14'h3094) ? (((r153 | 12'h53b) + (((r97 ^ (28'h6257 > 4'h5)) !== ( & ( ( ( ^ ( ( | ( ( & ( 13'h1537)))))) != ((18'h18c7 != r154) & r105))))) != r241)) - r193) : ((14'hcba !== (r26 | ($time && ((22'h643d ^ ( ( ~ ( r117)) < (r206 === ( ^ ( ( ! ( ( ! ( (11'h3b3 >= 27'h6d33)))))))))) / 6'h2c)))) > ((25'h6f8d >= 26'h4258) == ( ( & ( (( ( ! ( ( ~ ( ( ( | ( 32'h41ba)) + ( ( ! ( 14'h2b91)) + r190)))))) <= (26'h5532 + 14'h12cb)) == (r232 % ((21'h2891 / r76) + ( + ( ( ( & ( ((8'h43 <= 24'h19c2) > ( & ( 25'h70d2))))) + ((31'h65e0 !== (10'h18a ^ 1'h1)) < r191))))))))) / ((16'h16d0 ? 26'h5ce4 : (r66 ? ( ! ( r127)) : ((((((18'h6d90 ^ 19'h2911) % (18'h5898 * 3'h0)) && $stime) !== ( ( & ( ( ~ ( 25'h56ef)))) - ( | ( r124)))) * ( | ( ( ! ( (r62 ? r238 : (22'h5c72 <= 28'h4c3))))))) != ( | ( 22'h388d))))) | (((( ( + ( r248)) !== ((r240 % 30'h5a83) - r4)) + 31'h131) || r147) & ((r36 | (((((15'h5184 > 29'h7846) + 15'h4959) ^ (r123 * r200)) / ($time & ( + ( (8'hc8 & 9'h1db))))) > 5'hd)) / ((r86 > 29'h4da1) !== r118))))))))))); +\t\t#10; r222 = (r106 * 32'h1826); +\t\t#10; r88 = ( ( ! ( ((((r249 != 18'h6b91) > ( ! ( ((r65 == r236) & 7'h59)))) ? r146 : ((r162 === $time) <= r135)) > (( ( + ( 32'h2513)) !== r252) || r147)))) <= ((32'h371b == r72) < 5'h1f)); +\t\t#10; r131 = r22; +\t\t#10; r48 = ( ( & ( (((( ( - ( ((r9 - 30'h63a0) * r22))) | ( - ( r212))) ^ 10'h1d5) === ( ^ ( 14'h2dbb))) % (9'h178 % (r241 !== ( ( | ( ( ~ ( (((21'h280 !== ((29'h1c0a - (1'h0 + 2'h3)) / (26'h2be2 * (r98 && ( & ( 22'hac0)))))) | (17'h5864 || r147)) <= (r51 ? ( ^ ( r226)) : (r15 != ( | ( (8'hb6 && 6'h34)))))))))) < (9'h1bb != r114))))))) === r208); +\t\t#10; r217 = ( | ( (r7 || ((r98 === (r212 === ( ( ! ( $time)) | (6'h3 + 23'h6819)))) / (r154 >= ( & ( r135))))))); +\t\t#10; r145 = ((7'h5d > r79) != ( - ( r98))); +\t\t#10; r22 = ( ~ ( 22'h43eb)); +\t\t#10; r115 = r221; +\t\t#10; r239 = (r198 !== (10'h79 !== (12'h444 ^ ((r204 && r214) % ( ~ ( r7)))))); +\t\t#10; r170 = ((r185 % 25'h5b50) - r104); +\t\t#10; r139 = (( ( ^ ( (((29'h158a && r170) ? r64 : 26'h4955) - (r100 >= r61)))) * r136) | r122); +\t\t#10; r78 = 7'h10; +\t\t#10; r72 = r70; +\t\t#10; r145 = ( | ( (8'h86 && r159))); +\t\t#10; r123 = $stime; +\t\t#10; r220 = ( ! ( ( ~ ( ((((r79 === 12'hd3) && r55) % ((r1 <= ((r226 % (( ( | ( r107)) != r227) < (($stime < r242) != ( ! ( ( ( ! ( 29'h6b4e)) * (r221 || ( ( ! ( 29'h162a)) > 25'h45be)))))))) !== ((( ( ! ( ( | ( (r179 <= $stime))))) && 20'h7a52) & r249) < 29'h58eb))) & 25'h4a32)) == (r63 == r136)))))); +\t\t#10; r31 = 32'h3c62; +\t\t#10; r216 = (r148 != r198); +\t\t#10; r140 = r215; +\t\t#10; r227 = ((r246 ? $stime : r163) && (((( ( ~ ( r157)) + 13'h1de6) / 2'h1) !== (($time <= (r195 & ( ^ ( r121)))) && ( ( ~ ( r165)) * ((r124 !== 13'h9f1) && (r226 == (r79 <= ((r188 | ((((r70 >= (29'h4a7 % 2'h3)) < ((8'hba >= 4'h5) || 24'h394b)) !== r140) + $time)) / r68))))))) && r193)); +\t\t#10; r168 = 2'h3; +\t\t#10; r208 = r211; +\t\t#10; r196 = ((((r227 < 24'h299e) != 10'hac) && (((r16 && ((r10 ? ($time / $stime) : r229) >= ( & ( (( ( | ( ( ( | ( 15'h5c9d)) / ( ^ ( (r242 !== r117)))))) && r200) <= ( & ( ( + ( ( ! ( r228))))))))))) - (7'h2c != (( ( & ( 17'hd65)) ^ $time) + (r82 >= r124)))) ? ( ^ ( r222)) : ( & ( ( ^ ( ((r146 != $stime) ^ ( ! ( (r4 % ( ^ ( r114)))))))))))) ^ r88); +\t\t#10; r200 = 12'h3e9; +\t\t#10; r158 = (24'h2147 - 4'h4); +\t\t#10; r72 = r219; +\t\t#10; r101 = ( | ( (r104 + r252))); +\t\t#10; r98 = (27'h401a ^ ( | ( ( ( ~ ( 13'h74a)) * (( ( ^ ( r121)) ? 5'hf : ( ( ^ ( 17'h6a2d)) % 2'h3)) != (r43 === (32'h2ec9 % ( - ( ( ~ ( (($time !== ((21'h583a + ( & ( r117))) * r30)) <= r167)))))))))))); +\t\t#10; r57 = ( ^ ( r87)); +\t\t#10; r54 = ( ( + ( ((( ( - ( r109)) ? 6'h9 : r99) - 28'h6c8c) + ((((((25'h46be && 14'h16f3) > r158) / r249) % (r168 || (r95 === ( + ( (((((r204 % $stime) <= ( + ( (27'hb65 != 6'h1b)))) <= ((r139 && (11'h577 || 27'h5dbd)) + 1'h1)) || ((((13'h9d1 !== 22'h14cf) | (26'h101a + 23'h31a9)) | ((7'h4b - 26'h63f8) | (30'ha4d * 32'h760))) < ( ( ^ ( 3'h1)) < r111))) < (((r215 & 32'h4838) / ( ( ^ ( (24'h2d6f || 28'h4fde))) && ((4'hb <= 9'h24) & r112))) | (r97 === (r76 < 8'h76))))))))) ^ ( ^ ( ((26'h3743 || ( ( - ( ( ! ( ((3'h4 * ((7'h66 !== 32'h4200) & 14'h2b24)) ? ( - ( r57)) : 21'h6ef))))) <= r70)) | ((r159 <= r181) - ( ( + ( (r36 || (r49 != (r185 === ( ^ ( ( ! ( 10'h2dc))))))))) === r150)))))) >= ( | ( ( ( & ( ( ! ( 22'h416f)))) !== (r137 + ( | ( $time)))))))))) ^ r148); +\t\t#10; r44 = (11'h11 || 13'h99d); +\t\t#10; r213 = r254; +\t\t#10; r101 = 31'h6ed; +\t\t#10; r190 = ( ^ ( r133)); +\t\t#10; r222 = (32'h2008 >= 24'h68a3); +\t\t#10; r12 = r13; +\t\t#10; r235 = ( + ( (r42 / $stime))); +\t\t#10; r50 = ( ( ^ ( ((r251 <= ((27'h6eee > ( & ( (($time ? r43 : $time) !== (7'h36 !== ((((((23'h6f4 != 26'h7c8b) & (32'h5eeb < 25'h6227)) | $stime) * (((29'h6a61 === 11'h6bf) & (30'h6956 / 21'h637d)) > r209)) + ( | ( (($time % (22'h3516 ? 11'h405 : 6'h5)) % (11'h49d >= (4'he ^ 17'h9e1)))))) + r82)))))) & r152)) * ((((((r53 & r240) != ((((r146 === ((14'h1ccc - r221) % 1'h0)) !== ((( ( | ( 23'h24bd)) & r79) >= (26'h2a62 / 23'h59d6)) !== r94)) < ( ( ! ( ( ~ ( ((26'h1762 / 12'h3bb) === ( ~ ( 20'h2582))))))) > r104)) * r190)) != (21'h5a98 >= r53)) && ($time * 13'h1dc3)) / $time) - r217)))) < (( ( - ( ( + ( (2'h2 !== r32))))) != ( ( ~ ( ( & ( (r130 != ((29'hc97 - $time) ^ ( - ( r18)))))))) - r102)) + r33)); +\t\t#10; r224 = r199; +\t\t#10; r74 = 31'he64; +\t\t#10; r92 = ((( ( ^ ( ((r138 ? (((((r82 == (r128 * (r32 % (15'h7083 <= r219)))) > ( + ( ( ~ ( 31'h75c7))))) && $time) <= 2'h3) | 23'h7c7b) : r20) + ((25'h4238 >= (( ( ~ ( r30)) < r97) ? (((((24'h5cda + r34) === 31'h60c9) != r72) == 11'h5c8) | (r92 / r77)) : (r26 != r174))) % (( ( + ( (((13'h507 + $time) < (r230 < r79)) / ((""b"" ( - ( ( & ( (21'h77de >= 21'h595c))))) & (6'h29 == r159)) == r120)))) ? (( ( ^ ( ($stime % ( & ( (r44 ^ 19'h4868)))))) || 29'h425) != ((((((27'h3be5 <= 21'h73b3) >= 5'h1e) - ( ! ( (24'h14b5 | 12'h81f)))) != (((31'h6c1a >= 7'h66) != (21'h2b37 * 5'hc)) | 26'h1e08)) ? $time : ((r238 && 9'he4) | $time)) / $time)) : ($stime || 10'h2af)) | 30'h6f3b))))) != ( & ( ( & ( (30'h2102 - (r214 ^ (r148 != r173)))))))) || r12) + $time); +\t\t#10; r20 = (r109 ? (((((r205 * r142) - ($time && (14'h12d7 & (25'h300a ^ $stime)))) != 8'h46) || ( ~ ( ( ( + ( ( ~ ( ($stime < ( ! ( ( ^ ( (r127 + r51)))))))))) == (r175 % ( ! ( (((r70 == r189) > (((r1 !== 9'h40) != (5'h3 !== r198)) + (r221 ^ 30'h283b))) || 29'h1a0c)))))))) + (((r220 + (26'h5440 != (2'h1 == 6'h2e))) & r219) & 28'h5a06)) : (14'h1a0a < 6'h15)); +\t\t#10; r253 = ( ! ( 32'h3419)); +\t\t#10; r95 = 16'h3cbd; +\t\t#10; r49 = 2'h1; +\t\t#10; r17 = (r251 <= r61); +\t\t#10; r151 = 4'h7; +\t\t#10; r136 = (r253 || ((r68 <= 30'h5ad3) != (3'h0 % ( + ( 27'h5cc2))))); +\t\t#10; r35 = (r153 & (r74 | ( ( & ( r94)) <= r72))); +\t\t#10; r120 = (30'h3c55 + ((r48 || r173) & r231)); +\t\t#10; r214 = ( ( & ( (r168 % ((((28'h55b2 ^ ( ( ! ( 8'h4b)) === 11'h221)) < r217) != ( ( ~ ( ((r213 / ( + ( ( ( | ( (((18'h5f95 * 8'h91) || (7'h17 & 16'h8ab)) && r127))) == 16'h5aae)))) * ( + ( ((r109 == ((((18'h3972 + 25'h7165) == (4'h4 >= 7'h58)) * (6'h2a - (28'h4a9a + 16'h768d))) != (r130 !== ((11'h36b < 17'h7bb9) / 31'h65db)))) ? ( | ( r139)) : ( - ( 28'h5d29)))))))) !== (((15'h7581 < 5'hd) + ((((20'h61ac ^ r219) < 1'h0) | (r79 ^ r25)) * (r90 < $time))) - ( ^ ( ( - ( (( ( + ( ( + ( r130)))) == (( ( ~ ( r200)) >= 24'h433) < 1'h1)) + 17'h7ce2)))))))) ^ (( ( & ( ((r161 + ( & ( ( ( ^ ( r63)) * (((r201 & (13'h1fa9 || 2'h3)) * ( ^ ( r103))) * r28))))) | 1'h1))) === $stime) > ( ^ ( ( ! ( r165))))))))) >= ((( ( | ( 3'h6)) | r66) | 5'h8) ? ( - ( r24)) : (r227 / ( ^ ( ((( ( ~ ( (((r63 * ( ( & ( (r92 / (24'h565a + 12'h647)))) - (r124 < r138))) || ( - ( (18'h1d84 | ((r186 - 28'h4f76) | ( ( - ( 4'h5)) != 25'h57d1)))))) ^ ((r196 >= ( | ( r186))) ? ((32'h15b6 & (26'h458a > ( ! ( r103)))) / r171) : r99)))) || (($stime - (((((r64 | r129) / 18'h31eb) | $stime) & (1'h0 / r226)) != ( + ( r173)))) != r3)) % (r109 >= 9'h119)) + (((((20'hf4b ? ( & ( (16'h394b > ($time * ( + ( (16'h480 === 32'h42fb))))))) : 24'h56a7) ? 22'h5ab9 : r136) === 14'h2f0a) <= r83) % r134))))))); +\t\t#10; r223 = (r227 ^ ( ! ( ((28'heb ? ( + ( (r213 | (20'h18bc >= r78)))) : ( & ( 10'h333))) | ((r132 != r21) - (r23 | r235)))))); +\t\t#10; r70 = $time; +\t\t#10; r76 = (r49 / (((( ( - ( r188)) && r46) <= (r73 * r159)) || (r109 ^ ( & ( 13'h12a8)))) / (( ( - ( $stime)) > (r165 / ((25'h7b9e * ( - ( ( ^ ( (((r28 + (r247 > ( - ( (2'h0 % 10'h360))))) % 13'h48d) ? (29'h6a6f - 27'h5199) : 22'h2db7)))))) < 17'h6a8e))) >= ( ^ ( ( - ( 5'h3))))))); +\t\t#10; r184 = ( & ( ( & ( r95)))); +\t\t#10; r244 = ( | ( (12'hb7 / 9'hb9))); +\t\t#10; r239 = 19'h7f7c; +\t\t#10; r246 = (r224 != ((($time < 11'h493) !== (18'h148b - r178)) == (7'h4c < (r198 && ( | ( ((((((r140 & ( ~ ( (( ( - ( 15'h988)) | r21) || ( ( ^ ( 11'h5c4)) <= (20'h7942 >= 15'hca5)))))) % r6) && (($stime + 6'h16) > ( & ( 13'h76d)))) > ( ( - ( r13)) >= ( ( + ( 13'hc6a)) / (r247 * r180)))) >= (7'h20 || (( ( ! ( (((12'haae > 10'h15a) && 16'h4261) > r16))) & ((r100 / (r60 + (r99 / (27'h2093 - 8'hd5)))) - r234)) & ( ( ! ( $time)) === $stime)))) >= r31))))))); +\t\t#10; r208 = r57; +\t\t#10; r120 = 26'h5f9c; +\t\t#10; r176 = 5'h2; +\t\t#10; r205 = ( ^ ( 31'h6209)); +\t\t#10; r219 = (1'h0 * ( | ( r56))); +\t\t#10; r9 = 19'h2d05; +\t\t#10; r112 = ( ( ~ ( ( + ( ( ^ ( r163)))))) <= ( - ( ( | ( (r78 % ( ( + ( ( ! ( $time)))) != (31'h4aff * r79)))))))); +\t\t#10; r163 = r143; +\t\t#10; r20 = (((r127 | 17'h3217) ^ r11) || (8'ha2 != (r189 === r201))); +\t\t#10; r45 = ((r171 ^ ( ! ( (r42 === 5'he)))) >= 13'h1b72); +\t\t#10; r72 = ( ( | ( ( + ( r110)))) - 10'h189); +\t\t#10; r238 = $stime; +\t\t#10; r234 = r199; +\t\t#10; r247 = r34; +\t\t#10; r138 = r206; +\t\t#10; r245 = ( | ( r167)); +\t\t#10; r253 = (( ( | ( 14'h394d)) != (( ( ^ ( (((10'h1c6 == r212) ? ( + ( ( ~ ( r148)))) : r51) ? ( ( ^ ( $time)) < r233) : (7'h3c ^ ( ^ ( 17'h7cde)))))) !== ( ( | ( r155)) !== r64)) <= r224)) % (( ( + ( (r79 === ((1'h1 <= (r81 / r68)) + (r139 != ((r180 ? ( + ( ( ! ( ( ~ ( r46)))))) : (r171 % r237)) * r102)))))) % ( ^ ( ( | ( r78))))) <= (17'h2b1f ^ ((17'h3160 ^ r59) > (((6'h3 + $time) * ((7'h3f !== $stime) ^ 3'h2)) ^ ((r181 > (r221 | (((r187 != ( - ( (((14'h3871 - 31'h1261) < (8'had / 6'ha)) & r192)))) || $time) ? ( + ( r154)) : $stime))) + ( & ( 21'hfbf)))))))); +\t\t#10; r193 = ( & ( 15'h1a54)); +\t\t#10; r143 = r132; +\t\t#10; r161 = ($time & ( ~ ( (r107 ^ $stime)))); +\t\t#10; r47 = r197; +\t\t#10; r72 = ((($time == 14'h3eb9) !== r242) < 12'hee0); +\t\t#10; r167 = ( ( ! ( ( + ( r50)))) + ( ^ ( (r231 * ((6'h26 <= ( ( ~ ( ( ( + ( ( - ( ((( ( + ( (2'h1 != 19'h3fa5))) === ((6'h11 % 4'h1) / (10'h37a / 30'h1e1c))) * 9'h1b6) != ( ( & ( (8'h22 === 2'h1))) * $stime)))))) * 13'h1daa))) * r192)) === 26'h5f03))))); +\t\t#10; r99 = ( ~ ( ( ~ ( r218)))); +\t\t#10; r66 = ( ( ~ ( ((( ( ^ ( ((11'h73f ? ($stime === ( ~ ( r187))) : ((((20'h4125 + $stime) | r85) == r13) === ((22'h47f0 & (r164 % ( & ( ( + ( (23'h1879 + 19'h28f2))))))) >= 4'hf))) * $stime))) === ( ^ ( 29'h67cf))) || ( | ( r240))) > ( - ( (r78 + (23'h272f && (r132 != (( ( & ( (($stime === (((16'hed3 * 1'h0) < $time) && ((6'h2 / 9'h101) ? (21'h637d - 26'h4190) : r63))) * ((((9'haf & 14'h2ce7) ? (2'h2 & 9'h197) : 9'hd5) <= ( ( + ( 27'h32c1)) && (9'h147 - 5'h11))) >= (r159 == (r200 <= 28'h3218)))))) ^ ( - ( ( + ( (r202 ? ( ( - ( 14'h190e)) % ((16'hffb >= 26'ha6d) + (23'h3a46 | 3'h4))) : r83)))))) % r246))))))))) ? ( ( ! ( ( ^ ( ((r117 === r65) & (r92 & r196)))))) / ((((((16'h4c37 !== ((r124 * r17) < (r161 + ((r55 === ( ( ~ ( r209)) & 10'h3fc)) % ( ( & ( ((7'h2f + 18'h274a) * (31'h4de5 < 12'hb26)))) >= ( ^ ( ((14'h3161 >= 25'h7632) * (25'h2a76 * 8'he))))))))) > ( ! ( ((10'h390 - r60) % (((13'h649 + ( - ( r187))) !== r61) | 19'h40eb))))) >= (19'h49d9 <= r1)) & (( ( & ( r174)) == r111) / 18'h4732)) - ( ( ! ( ( | ( (r232 > r110))))) + (r73 < $stime))) <= r163)) : ( ^ ( ( ! ( ((((r195 | ( ( | ( 22'h41f9)) ? (23'h754e / 6'h28) : (25'h7d32 == (4'h6 < 5'h1f)))) & ( | ( ( ( ! ( r87)) - r71)))) - ( ^ ( r179))) | ( ( & ( (3'h2 > $stime))) + ( ! ( r165))))))))); +\t\t#10; r9 = (26'h2a2e != 15'h83d); +\t\t#10; r125 = 15'h6f76; +\t\t#10; r245 = ( | ( 28'h74c2)); +\t\t#10; r157 = r203; +\t\t#10; r166 = ((21'h29d6 != (($time - r242) == ( ( & ( (((11'h323 && ( ~ ( (1'h1 + ((r68 / (((13'h18c8 + 15'h2554) % r147) === (9'h40 === (4'he || 1'h0)))) ^ ($time & r189)))))) | 30'h4919) <= r151))) < (r137 ? (r50 % (( ( - ( $time)) >= 19'hbdc) * r216)) : ( ( ~ ( (6'h3d | $stime))) <= 1'h0))))) <= ( ( - ( r229)) >= 22'h3540)); +\t\t#10; r138 = r246; +\t\t#10; r163 = 32'h357d; +\t\t#10; r251 = ( & ( ( - ( r85)))); +\t\t#10; r83 = ((23'h34a0 <= r246) === 11'h66b); +\t\t#10; r183 = (r152 || (($time ? (21'h6ca4 > 28'h650) : r140) != ($stime !== 27'h1214))); +\t\t#10; r171 = 32'h6d44; +\t\t#10; r180 = 9'h180; +\t\t#10; r167 = (r199 ? ( | ( r212)) : 23'h3844); +\t\t#10; r221 = 12'h1b; +\t\t#10; r198 = (r72 ? ( ! ( r4)) : ( - ( r213))); +\t\t#10; r97 = ( & ( 14'h290e)); +\t\t#10; r164 = 5'h3; +\t\t#10; r33 = ((($stime || (7'h9 >= 9'h1bf)) < 14'hb12) < ((r246 / ((r116 ? 20'h1b7c : ((r189 + 17'h6013) - $time)) % $stime)) == (r100 ^ ( ( ~ ( (r189 !== r96))) & r40)))); +\t\t#10; r154 = ( ( - ( ((26'h562a && r20) && (r167 | ( ( & ( (r219 | (r185 ? (r114 || ($time / r206)) : (1'h0 < $stime))))) ^ 21'h4aae))))) / ( ~ ( (r253 % ($stime * 15'h5c88))))); +\t\t#10; r25 = (r5 & r139); +\t\t#10; r205 = ( ( ! ( ( ! ( 29'h4196)))) && ((13'h19ed != (r149 != (24'h3ba0 !== ((r142 != (30'h3f71 || r189)) - ((((r109 / ((8'h1b % ( ( | ( r115)) === ( & ( ( | ( 30'h3325)))))) || ( + ( 6'h6)))) !== r180) || 26'h3874) - ((((15'h26a5 - ((((10'h36c % 18'h1c8) && (3'h0 <= 1'h0)) !== ( & ( (30'h1ae9 - 29'h35cf)))) > 23'h24e9)) || ( & ( (r194 * r105)))) & $stime) % ( ! ( (( ( + ( ( | ( r76)))) | ( ( ! ( ((3'h5 - 10'h2ec) + (32'h73bf & 20'h6da1)))) <= r79)) / r48))))))))) % r32)); +\t\t#10; r180 = ( ( | ( ((12'hc2a % ( + ( (((4'he < r151) >= ( ! ( r53))) >= (((( ( ! ( ((7'h1a ? ((21'h60e7 / 26'h652f) / ( ! ( 16'h3871))) : (29'h69c9 && (29'h415d >= 15'h4e98))) && (((27'h4d27 === 5'h11) == (5'h7 / 27'h23f2)) > ( + ( ( ~ ( 18'h3e82)))))))) != ( ( ! ( ( ( - ( r245)) != r141))) < (((r169 && 18'h2377) * ((19'hf5c && 21'h6ee0) || 2'h3)) / r178))) * ((((((16'h46dc >= 13'h54) >= (17'h793b >= 25'h35db)) < ((27'h7f99 > 23'h7718) != (12'hc9e == 3'h3))) || ( ( & ( (17'h2856 !== 18'h357))) * r241)) && ( ( ~ ( ((12'hfd6 * 14'h2446) / r102))) || ( ^ ( (r18 ? r25 : r123))))) == 5'h13)) ^ r185) | r245))))) !== (((r52 && ($time == r43)) !== ((14'h101e < ( ( + ( ( & ( ( ( + ( r195)) !== r50))))) || ( - ( 20'h140)))) != ((r48 != (r78 >= 6'h1c)) | (9'h8c ^ ( | ( 29'h4eb7)))))) < (((r199 + 11'h4f4) || r190) != 19'h5fcb))))) !== (((($time == ( + ( 4'hf))) / ( + ( (24'h4ff8 * ( ( ! ( ( - ( (((((r11 | (11'h26b - 6'h39)) ^ r52) & (($stime % (15'h3778 == 15'h3a4a)) % $stime)) ? ( ^ ( (r49 > r191))) : ( ^ ( ( & ( ((15'h721d >= 11'h498) !== 13'h113c)))))) == r247))))) !== 15'h3ec5))))) === r154) | ( & ( ((31'h5377 && ((r11 || ((((r70 > (r202 !== r43)) ? (r221 >= (((r255 == $stime) < ( | ( ( - ( 23'h36a7))))) != (13'h1664 !== 32'h669a))) : r32) | (((7'h56 && 5'h1b) && (r106 == r168)) !== ( & ( ((22'h15c7 && (r210 ^ ( - ( 30'h3a9c)))) ^ (((6'h12 | 1'h0) - (24'h3128 * 26'h265)) === (31'h947 | (28'h7be5 & 31'h336f)))))))) & ((r91 + ( + ( 17'h1d47))) & (( ( | ( 28'h2f2)) && ( ^ ( 26'h663d))) <= ( ~ ( ( ! ( ( ! ( (19'h5235 % (19'h3511 - 32'h5628)))))))))))) || (13'h82e | (r15 || (20'h145c != ( ( & ( r228)) == ( ( - ( (((2'h3 ? 10'h31f : 8'h32) + ( & ( 13'h567))) % ( ( ^ ( 5'h2)) <= r117)))) != (r138 == ( & ( 14'h2b3a)))))))))) && (8'h99 ^ ( & ( (((((r157 + (30'h3c00 || $stime)) / r106) === ($stime !== ( + ( ((9'h1b1 > ((19'h62e4 * 22'h2f20) - r190)) / 25'h38aa))))) != r200) % 1'h1))))))))); +\t\t#10; r29 = ( + ( 8'h46)); +\t\t#10; r70 = (r45 ? ((2'h0 > ( & ( ((((28'h54b0 != ((r240 <= r248) - ((r123 <= 20'h4d70) ^ (r183 == (r182 == ( + ( ( + ( (11'h50f && 24'h6d05)))))))))) == (9'h45 % ( & ( (20'h5daa | (((( ( + ( 7'h66)) && (23'h2117 && 5'h15)) ? r134 : 14'h2f50) > r236) != r231)))))) ? 8'hbc : ( ( ! ( (( ( | ( ((r70 * (18'h58fb ? r227 : (19'h4843 <= 23'h461d))) === ( ( + ( (7'h30 ? 13'h163e : 8'hb2))) & ((16'h7ef || 18'hef9) > (28'h3502 < 25'h15a7)))))) - 9'h1ad) - (((r129 | r81) > r41) || (r76 <= 17'h6b6e))))) & ( | ( r125)))) < ( + ( r6)))))) | ((r75 === (4'h3 !== (24'h4381 <= r157))) + r112)) : r244); +\t\t#10; r146 = (( ( + ( ( ( - ( 16'h6078)) + (r112 - ( | ( 26'h4c17)))))) <= (( ( - ( ((r203 | (((12'h954 ? ($stime | ( ! ( ( - ( ($time && (9'h1b3 !== 19'h3078))))))) : $time) == 19'h4592) >= ( ( - ( $stime)) > ( - ( 12'h242))))) >= ( | ( ( ( & ( 32'h6a4c)) <= r3)))))) * (6'h14 == ( | ( r84)))) * (((((((11'h412 - r64) === ( | ( ((r141 || ( ^ ( ($time !== $time)))) ^ ( ~ ( $stime)))))) * r242) ? (31'h4adf | (r170 && (($stime * (r75 ^ (4'h3 < 23'h1faa))) >= 14'h2445))) : ( + ( r186))) === r215) % r60) % ( ( & ( (4'h0 || $time))) ^ r179)))) > r82); +\t\t#10; r219 = ( | ( (9'h14b * ( ^ ( ($stime ^ 12'h40c)))))); +\t\t#10; r164 = ( + ( ( - ( 5'h18)))); +\t\t#10; r197 = (r243 % (( ( & ( r105)) && 25'h3a96) * (23'h1425 | $stime))); +\t\t#10; r50 = (((r217 & r223) !== $time) + r81); +\t\t#10; r185 = (5'h6 | (r31 >= r194)); +\t\t#10; r133 = (r210 / r112); +\t\t#10; r203 = $stime; +\t\t#10; r178 = (14'h258f <= 14'h1fb1); +\t\t#10; r235 = ((12'h62a == ((r235 - r30) ^ 11'h49b)) ? ( & ( 13'h1647)) : r237); +\t\t#10; r46 = (r241 !== (((((13'h1466 === ( ~ ( (((r106 - r139) >= ( ^ ( r97))) + 12'h69d)))) >= ( & ( ((r94 ^ r251) <= 10'h389)))) && 28'h116b) <= ( | ( ((( ( ! ( ((20'h14cc != ( & ( r45))) != r97))) + $time) == (( ( + ( ( ~ ( (11'h166 % (r79 ^ 15'h4c0a)))))) % ((27'h4742 + (r109 !== ( ! ( (r238 >= ((13'h1bc2 ? 27'h21ab : 12'h85d) / r65)))))) ? (( ( - ( 22'h3a77)) && (r24 === (( ( + ( 24'h42f9)) <= (17'h1d1c >= 30'hed9)) - ( - ( 31'h3f78))))) <= (r57 * (r252 !== r239))) : r117)) % r175)) === r66)))) ? ((r105 - r24) >= ( & ( 6'h3f))) : ( ~ ( ((((r27 || ((r72 != r105) === 30'h5332)) <= r58) < $time) > (r11 ^ ( & ( 28'h5de6)))))))); +\t\t#10; r14 = r60; +\t\t#10; r158 = 3'h0; +\t\t#10; r92 = 16'h5cb0; +\t\t#10; r168 = (22'h238a == ((29'h737d % ((($stime || (r170 & ((((30'h2570 ? r246 : (r90 == (((2'h2 <= 11'hb6) > (20'h333a ? 3'h0 : 19'h4cae)) ? 8'he0 : ((16'h63a % 19'h22bd) - 12'h78c)))) != (r152 ? (r232 ? (((29'h7a19 >= 28'h28d5) ? (12'hdd9 + 19'h6d4d) : 16'h2ab9) ^ (r196 / (5'h6 >= 31'h55a4))) : r35) : r73)) <= (20'h4ff2 - ( - ( ( + ( ( | ( 3'h0)))))))) % 5'h15))) * r34) !== $time)) || ( & ( 17'h1c43)))); +\t\t#10; r31 = ( + ( ((3'h6 ^ ( ^ ( (r30 * r118)))) % ( ( - ( ((r131 <= r109) | ( ( - ( ($time % ( ! ( 1'h1))))) + $time)))) / r228)))); +\t\t#10; r227 = r113; +\t\t#10; r69 = ( + ( ( | ( ((r175 * r252) >= 32'h458))))); +\t\t#10; r160 = r171; +\t\t#10; r99 = r171; +\t\t#10; r26 = ($time >= (14'h3a77 ^ r235)); +\t\t#10; r188 = (( ( ! ( 19'hce0)) ^ (r32 ? (($stime <= (r90 * 15'h5bc5)) < r45) : (30'h7f25 == ( ( & ( ( ( ~ ( ((r137 / 22'h505) && r114))) || r72))) != r210)))) === (r220 | r130)); +\t\t#10; r210 = r221; +\t\t#10; r241 = ( ( + ( r24)) + 10'h16e); +\t\t#10; r24 = ( + ( (3'h1 + 27'h6ef2))); +\t\t#10; r104 = ( + ( ( ~ ( r45)))); +\t\t#10; r39 = 12'h75f; +\t\t#10; r136 = ( - ( 5'h18)); +\t\t#10; r186 = $stime; +\t\t#10; r202 = 3'h6; +\t\t#10; r216 = 25'h70bd; +\t\t#10; r208 = r211; +\t\t#10; r143 = ( + ( (r114 < r197))); +\t\t#10; r118 = ((r187 * r55) <= ( & ( ( - ( ( - ( ((( ( ~ ( 14'h3306)) % (((15'h67f + ($stime ^ ($stime % ( ^ ( ((11'h82 < 18'h7222) ^ ( + ( 25'h1c3b)))))))) - (($stime <= ( ! ( ( ( | ( (29'h166e % 7'h22))) >= 21'h608)))) <= ( ^ ( ($time > r232))))) | r5)) > 2'h2) !== r89)))))))); +\t\t#10; r234 = 9'h1f5; +\t\t#10; r254 = r6; +\t\t#10; r39 = ( & ( $stime)); +\t\t#10; r238 = ((15'h7bb7 >= 29'h70ec) & 22'hf47); +\t\t#10; r65 = ((1'h1 - r123) + 12'h583); +\t\t#10; r27 = (r221 == (r115 < r95)); +\t\t#10; r204 = ( | ( 19'h10b)); +\t\t#10; r232 = (r78 / ( ~ ( (((((8'hfa < r34) * ( + ( (r91 != ($time + (3'h2 ? (21'h3c7a / r249) : (r205 * ((r71 % r26) && r39)))))))) | (1'h0 >= 21'h4545)) != 31'h1e16) !== (((5'hc / $time) == 27'h150d) !== 5'h1))))); +\t\t#10; r213 = (r116 || ( ( ~ ( 9'h1cc)) !== (((23'h10fb == (((((21'h5703 * $time) >= ((29'h1274 !== ( ( - ( 11'h56d)) | ( & ( ( + ( (6'h2 + 17'h129b))))))) >= ((( ( - ( r163)) > ((23'h2857 != 30'h64e4) / 5'h5)) || (((23'h7345 <= 21'hdf7) == r154) | r189)) > r117))) > (( ( + ( ( + ( r118)))) / 26'h7e4) <= ( + ( ( - ( ( + ( (( ( ^ ( 16'h3752)) & (11'h2b && 4'he)) != ( & ( r63))))))))))) < ( ( ^ ( r82)) == ( ( ^ ( (( ( + ( $time)) ? ( ( ~ ( $stime)) > r142) : (13'h19ae | ((25'hced != 12'h2ff) !== 30'h290b))) && (r108 > r38)))) || (29'h7ef2 | r0)))) * $stime)) == ($time ? r49 : ((30'h1631 != (r225 - r55)) - (27'h3be0 ^ ($time ? 14'h2bb1 : r25))))) | 9'h1b9))); +\t\t#10; r198 = ($stime <= ((2'h0 || (r230 * r145)) || ((r31 !== 20'h7fd3) !== (r98 % ( ~ ( ( + ( (r110 <= $time))))))))); +\t\t#10; r8 = 19'h16e0; +\t\t#10; r145 = r147; +\t\t#10; r125 = r193; +\t\t#10; r182 = 1'h0; +\t\t#10; r253 = ((10'h2de <= (25'h4a1d & r188)) < r181); +\t\t#10; r44 = (24'h2e9a * (((( ( | ( ((r29 & r182) == r131))) / (15'h6295 | 3'h7)) > 14'had2) & r100) & (((7'h1b !== $time) % ((( ( - ( ( ( & ( ( + ( (r208 | ( & ( ( + ( (1'h0 + 30'h6481)))))))))) / 10'h170))) != r170) === ((r216 && 20'h7e5a) || ((r115 && ( ~ ( ( & ( (r68 | (r149 < (r233 < r186)))))))) | r213))) || 15'h789)) && (r59 !== 8'hfc)))); +\t\t#10; r229 = ( + ( r72)); +\t\t#10; r155 = 19'h69ae; +\t\t#10; r56 = r65; +\t\t#10; r84 = $stime; +\t\t#10; r76 = $stime; +\t\t#10; r235 = ((( ( ! ( r97)) | (29'h463 >= (( ( - ( r73)) | (r115 + $stime)) % 5'h15))) & ((r67 * ((( ( + ( ( ~ ( ( | ( (2'h0 !== ( + ( (((6'h37 === 20'h7815) - (8'h25 & 26'h1ee9)) != 26'h152d)))))))))) % (r128 || (r140 * ( - ( ((1'h0 > r41) == 17'h2448)))))) !== (12'h312 * ( ( ! ( r17)) > 6'h36))) + ((r172 ^ r139) / ( & ( r127))))) || 29'h6f45)) ? (((r63 ^ ((($stime === 15'h3fb7) != (( ( ~ ( ((( ( ~ ( r77)) != ($time <= ( | ( (19'h51cb != 19'hea0))))) ^ ( | ( (((27'h7fb1 ^ 22'h2e65) !== 8'h56) !== r60)))) + (8'h5b === (((10'h93 == r244) <= (14'h2620 && 3'h5)) <= ((22'h77e0 >= 13'hb60) && ( ^ ( ( ~ ( 20'h754a)))))))))) % ((((r106 & r242) | (9'h1a <= 17'h67c)) + ((r119 ^ (r206 < (r194 + (1'h1 <= 4'ha)))) ^ ( ~ ( r34)))) | ( & ( $stime)))) + ( ~ ( (r166 != 13'h147d))))) * ( - ( ( ( ~ ( 3'h0)) % ( ! ( r53))))))) ? (r102 == 3'h7) : (r60 * ( ( & ( ((r30 > (r33 <= ( | ( $stime)))) ? ((r17 <= ( ( - ( 22'h7b0a)) ? ( & ( (( ( - ( ( & ( 3'h0)))) & (r90 != (3'h1 !== 7'h2c))) / (((5'h14 ? 9'h1f : 21'h5421) & 27'h6fd6) || ( - ( r105)))))) : ((7'h52 + (r82 & (20'h218f !== (19'hca5 > 28'h7ddb)))) && ( | ( 15'h5da5))))) === 2'h1) : r187))) || 15'h3aa5))) & r178) : 16'h50d3); +\t\t#10; r104 = r197; +\t\t#10; r173 = 31'h818; +\t\t#10; r205 = (((r254 >= ( & ( (r51 || 10'h2bd)))) | ((12'h778 ? (4'h3 && ((r82 == r40) < ((r68 <= ( ! ( ($time % r254)))) - ( ^ ( ( - ( r179))))))) : (((r196 ^ ( ! ( ( + ( r61))))) == (18'h6246 < r0)) !== ( | ( 23'h7fe)))) ^ r0)) & ( ( & ( ( | ( (10'h31a ? ((15'h5a76 != ((r49 > ( ( | ( (r106 % (( ( ~ ( 28'h4fd6)) - ( + ( 29'h7066))) > ((27'hc41 === 28'hd4b) | (6'h2d & 8'h64)))))) && ((r242 <= 24'h2822) | $stime))) && r169)) != $stime) : r56))))) ^ ( | ( (r180 ^ r203))))); +\t\t#10; r237 = (((((4'h5 - ( ^ ( (((((((6'h27 ? ((2'h0 & 25'h3301) < (6'h25 | 9'h1ec)) : r223) | 31'h65e1) >= ((((31'h4659 + 17'h5965) < ( | ( 11'h631))) !== ( ~ ( $time))) * (($time / (10'h7d && 1'h1)) ^ 3'h1))) & 15'h5e87) ^ ( ( ^ ( r233)) && ( | ( 24'h3d10)))) == r49) > ( - ( 2'h0)))))) - 5'h8) && 32'h3aa2) ? r27 : 27'h7c25) ? (25'h6fc1 !== (r8 & (((r82 >= 27'h5432) === ((25'h1d79 < ( ^ ( 22'h53a7))) < r44)) / 2'h1))) : (r98 <= ((18'h56be === 13'h1971) % (r188 | r126)))); +\t\t#10; r72 = (r29 / ((4'ha - (( ( - ( ((r110 == (r68 != r28)) && 23'h1d5d))) !== $time) & ( ! ( ((32'h122 >= r161) | 16'h36a9))))) < $stime)); +\t\t#10; r215 = r150; +\t\t#10; r32 = (23'h22ba & r68); +\t\t#10; r251 = ((((((((( ( & ( ((( ( + ( r230)) || ( ~ ( (10'h214 - 8'hca)))) & 29'h64fb) * r148))) <= $stime) == $time) - ((((((r247 >= r170) > ((r209 - r248) | ( ( - ( 15'h2d06)) ? 1'h1 : (14'h2f73 | 25'h3e87)))) % ( ( | ( r170)) > (r2 === ($stime > $time)))) !== r98) / ( + ( ( | ( r156))))) + ( + ( 30'h1f05)))) != r171) === (23'h16f4 & (((( ( + ( ( ( + ( ((10'h176 % 27'h709d) !== r155))) || ( ^ ( ( ( & ( 8'hbc)) != ( ^ ( 18'h426a)))))))) === r80) !== 23'h72f3) != r118) ^ (r122 - ( ! ( (r57 * (25'h14f1 === (r168 / r149))))))))) | (r65 / $time)) == r250) ? r193 : r163) && 32'h1880); +\t\t#10; r16 = ( - ( ( - ( ( - ( r182)))))); +\t\t#10; r82 = r63; +\t\t#10; r173 = 30'h254b; +\t\t#10; r120 = (14'hd78 ^ r193); +\t\t#10; r133 = ((r37 != r131) ^ r221); +\t\t#10; r215 = ((25'hb1f || ( ( & ( (((((r198 | ((28'h6191 / 4'h2) > ( & ( ((((25'h4f79 | 26'h5a16) ^ (3'h2 > 21'h51e3)) * 21'h31e8) >= (r25 / 26'h3a40)))))) !== (r33 % ( - ( (((((15'h2a8c % 1'h0) + 32'h5653) + r172) || $time) ^ 23'h5215))))) == r173) != (23'h1aaa == (13'hccb ? r24 : (r86 && ((( ( ! ( (r126 !== (28'h2588 == 29'h7d09)))) == (24'h10c2 > 22'h5f23)) || ( ! ( ( - ( r16))))) % ( ( & ( r0)) ^ r129)))))) <= 3'h0))) - r115)) && ( ^ ( ( + ( ( ^ ( $stime))))))); +\t\t#10; r98 = r156; +\t\t#10; r129 = (((r44 <= (((r14 > ( - ( r236))) < ((23'h5704 > (r163 === ((r136 != ( ( | ( 16'h7a29)) >= 21'h19b8)) !== (31'h53bd <= r38)))) != ( & ( 24'h332a)))) > (((((((r75 >= 23'h659f) !== (29'h2824 > r29)) <= ( + ( r103))) - (r69 * ((r222 != ( & ( r11))) <= $time))) || (r252 - r29)) >= (9'h0 != 30'h7bb1)) || ( ^ ( (r204 != r33)))))) + $time) & (( ( ~ ( r161)) == 18'h371b) - ( ( + ( ( + ( ( + ( ($stime > 10'h349))))))) == $time))); +\t\t#10; r224 = (25'h3bb6 ^ ((r169 !== ( + ( (($time <= r231) ? 12'h7e7 : ( ( ^ ( ( ~ ( r186)))) >= ( ~ ( ((r202 && ( & ( (11'h3f4 > (r148 < 24'h6a71))))) <= r104)))))))) == (((2'h2 % (((r226 < 2'h3) | (((2'h0 + (8'h1 || 7'h52)) !== ((r234 | ((( ( ! ( 12'h2fa)) + 23'h54ed) >= ( ! ( ( - ( 6'h1e))))) >= r230)) != 20'h7209)) - (14'hc55 % (r243 != r235)))) & (10'h110 > r103))) == ( ! ( r102))) || $time))); +\t\t#10; r15 = r135; +\t\t#10; r18 = r148; +\t\t#10; r179 = 13'h807; +\t\t#10; r144 = r116; +\t\t#10; r100 = r116; +\t\t#10; r44 = $time; +\t\t#10; r133 = 8'h67; +\t\t#10; r119 = $time; +\t\t#10; r155 = ( ! ( ( + ( r55)))); +\t\t#10; r241 = (r252 == ($time || r154)); +\t\t#10; r162 = 21'h4542; +\t\t#10; r154 = 25'h3c0a; +\t\t#10; r172 = ( & ( r130)); +\t\t#10; r152 = ( ~ ( r25)); +\t\t#10; r229 = r1; +\t\t#10; r238 = $stime; +\t\t#10; r180 = 21'h942; +\t\t#10; r231 = r199; +\t\t#10; r39 = r247; +\t\t#10; r46 = (23'h5bc != 3'h0); +\t\t#10; r166 = ( | ( ( | ( (13'h8cd ^ (((r12 || ( ( | ( 10'h14b)) && 12'h430)) === r195) & (30'h28c0 % ( ~ ( 27'h521b))))))))); +\t\t#10; r23 = r20; +\t\t#10; r102 = ( ( | ( r216)) | 27'h7337); +\t\t#10; r223 = ((1'h0 > $time) % r228); +\t\t#10; r42 = ( ^ ( ((r181 === r129) && ((r204 !== ((r112 ^ ( ( | ( 9'h199)) <= (r75 == ( ( ! ( 28'h5b63)) < ( ~ ( ((r96 <= (((15'h6ad0 !== 13'h5a1) <= ( ~ ( 24'h2def))) == ( ( ^ ( 24'h146e)) / (28'h13b1 >= 11'h94)))) || ( + ( (( ( ! ( 27'h51f3)) > ( & ( 10'h2c7))) - ( ^ ( ( ! ( 1'h0)))))))))))))) == ( ( ^ ( (( ( ^ ( (((32'h4dc3 - (r216 - 27'h503c)) <= 11'h1fd) | ( | ( r46))))) && 22'h5f72) === r74))) !== (r190 / ((r33 || ( | ( ( ( + ( r53)) !== (28'h1cb9 || ( ( | ( (1'h1 && 27'h699))) * ( & ( (16'h3dd0 === 17'h5fae))))))))) ^ ( | ( 12'h1de))))))) < r38)))); +\t\t#10; r174 = ( & ( 12'h666)); +\t\t#10; r79 = ((r135 && r189) != ( | ( r186))); +\t\t#10; r150 = (3'h3 * ((r251 !== ((9'h1ef - $stime) - (( ( - ( ( - ( r49)))) || r241) == ((( ( - ( 32'h4db1)) == ((r247 !== ((($stime + ((16'h42ad != 23'h2b27) ? r203 : (17'h2b91 % 27'h7fd3))) + ( ( & ( ( | ( 12'ha1b)))) !== ((21'h4286 % 22'h536e) ^ 16'h6608))) ? $stime : 14'h380a)) | ( ~ ( ((r115 & ((r16 + (30'h5605 & 17'h245)) - 19'h4ee4)) !== 14'h899))))) != ( ( ! ( r204)) >= (r58 + ((1'h0 === 8'h8b) + ((((9'h10 === r7) / r217) <= 5'ha) * r254))))) == ( ( & ( 6'hd)) && 11'h440))))) ^ ( - ( (r27 & ((r177 === (r226 != $stime)) | 9'hf)))))); +\t\t#10; r248 = r209; +\t\t#10; r5 = r51; +\t\t#10; r21 = 12'h97c; +\t\t#10; r51 = ( ( | ( ( ! ( (r174 > ( ( - ( 8'h2a)) >= ( ( + ( (( ( ~ ( r65)) + 8'h41) ^ 28'h7bc3))) / (13'hf60 * r126)))))))) >= ( ( - ( $stime)) <= ((r14 ^ (r25 >= 10'h344)) & ( ( - ( 21'h2549)) <= ((22'h7049 > 4'hd) ^ r172))))); +\t\t#10; r158 = (r89 !== (( ( ^ ( ((r215 <= r205) * ((r142 % 15'hce6) < r253)))) | r84) + ( & ( (r75 > ( - ( ( ( ! ( ( | ( (r183 > 26'h7d82))))) >= ( ~ ( (((r79 % ((r124 === ((r168 * ( ~ ( 19'h6332))) <= ( + ( ( + ( 32'h4365)))))) & ( ( ! ( ( - ( ( + ( 31'h67f5)))))) && r70))) >= (1'h1 & ( ( | ( ( ! ( $time)))) != ( & ( 7'h57))))) + r71))))))))))); +\t\t#10; r180 = ((r27 ? ($time - ( - ( ( ^ ( r86))))) : r20) - (( ( ~ ( (( ( ~ ( (30'h1d1e == ($time == (23'h196b === r86))))) & (21'h7750 >= ( ( ~ ( ( ( ""b'! ( ($stime == 25\'h47c6))) % ($stime && r93)))) / ($stime && ((r237 || r84) ^ ( | ( ( + ( r121))))))))) % ( - ( ( ( + ( r158)) + r54)))))) == ( ( | ( 16\'h315f)) >= ((((( ( + ( ( ~ ( r74)))) + 20\'h7b7f) || ( & ( ( + ( 23\'h4708))))) | (( ( & ( (4\'h6 === r209))) || 13\'h9c8) / r229)) ^ ( | ( ((4\'hf ? 24\'h4865 : 16\'h6051) > (10\'h250 <= 16\'h354))))) || (r139 === (6\'h3e <= 16\'h59a))))) || (r80 ? (($time != ( ~ ( ( ~ ( (r243 ? ((28\'h741c % r164) + ( & ( ((( ( & ( r252)) || 26\'h14dd) && r76) % r123)))) : 12\'h35b)))))) ? (18\'h36a6 === r202) : (((((27\'h473b | r219) * r121) | (r30 >= (( ( ! ( 21\'h52b8)) != (3\'h0 <= (r38 % (((4\'hf === 17\'h45ca) % ( - ( 15\'haa3))) === ((20\'h6ddf > 31\'h6ad1) !== $stime))))) < r48))) > r110) >= 6\'h3d)) : r163))); +\t\t#10; r72 = (( ( ~ ( ( ( ~ ( ( ( - ( ( & ( ( ^ ( r217)))))) | (r180 == r234)))) <= 24\'h480a))) % $stime) !== (24\'h5c74 > ((r244 | ( ( ~ ( (((((23\'h971 / ( | ( (13\'h121f <= ( ( - ( 28\'h6b51)) >= (12\'hcfc || 2\'h1)))))) ? ((r11 | ( - ( 32\'h450d))) > r254) : ( ~ ( $stime))) + (r74 & r104)) || ( - ( r235))) | ((12\'hafb % r158) - 17\'h7d6b)))) ^ r225)) ? ( ! ( ( ~ ( ((((((((((29\'h532 <= 16\'h3d4b) ? r138 : r213) || (16\'h52cf > (10\'hc9 + 1\'h1))) || $time) >= 16\'h2a91) | ( & ( ( ^ ( r43))))) < ( ^ ( ( | ( (r91 | 2\'h3)))))) / r186) * ($time / (r182 != r171))) < (( ( ! ( 19\'hf53)) % r173) ^ r90)))))) : $stime))); +\t\t#10; r162 = (13\'h1684 !== 20\'h5bae); +\t\t#10; r125 = $time; +\t\t#10; r65 = ((21\'h5040 % ( & ( (r168 / (r250 * r214))))) <= (21\'h5bf != ( ~ ( $time)))); +\t\t#10; r132 = 14\'h1f62; +\t\t#10; r35 = ( ! ( ( - ( (((((((8\'h0 % ((( ( - ( ((17\'h4f6 || 23\'h241d) * (24\'h3ec2 <= 31\'h7ec8)))) / $time) >= (r114 & r213)) == (10\'h33f === r79))) ? ( ~ ( 16\'h7540)) : ($stime || ((r144 - 20\'h7607) !== ( & ( 6\'h7))))) == ( ( ~ ( ( ^ ( (r251 / ( ( ~ ( $stime)) < (((12\'hcdd & 7\'h6f) && (18\'h7be < 16\'h51a7)) || ( ( ! ( 31\'h5b74)) ^ r127)))))))) + r254)) - r158) === ( | ( 11\'h317))) ^ (r88 - ( ^ ( (( ( ^ ( r179)) | ((r137 <= r77) === ($stime == ( ( + ( (r190 !== ( ! ( 24\'h667d))))) ^ $time)))) / r135))))) | (((r151 || ( ^ ( $stime))) >= r38) == (((( ( + ( ( ( - ( 3\'h5)) > (((((11\'h7ed > 23\'h4848) + (12\'hbf8 / 5\'hb)) ^ r115) && ((32\'h4a9d | (30\'h66c5 & 30\'h3e62)) >= 22\'h14fe)) > (((r54 | (19\'h3af4 ? 20\'h63c8 : 3\'h6)) | ((5\'h19 | 2\'h0) >= ( ~ ( 2\'h2)))) === ( ( ^ ( ( ~ ( 5\'h1d)))) != (r8 == (27\'h69be % 32\'h3b05)))))))) > 17\'h6896) <= $time) * 9\'h17e) >= (r253 | r11)))))))); +\t\t#10; r42 = 16\'hf15; +\t\t#10; r139 = ((( ( & ( (14\'h3f9d === ( ^ ( 21\'h5f2f))))) + 2\'h2) % 22\'h5b3c) !== ( | ( ((( ( ! ( r51)) / r88) ? 9\'h1a3 : $stime) > 9\'h194)))); +\t\t#10; r8 = ( ( & ( 20\'h40b8)) ? ( ( + ( (( ( + ( ($time | ((3\'h4 <= r197) == r234)))) != r4) - (r114 * 23\'h46dc)))) % r68) : r172); +\t\t#10; r181 = ( - ( ($stime % (23\'h1d8f && ( - ( ( ( ^ ( $time)) | (r108 & r26)))))))); +\t\t#10; r159 = (((18\'h535a % r30) * r65) >= ((( ( & ( ((((((r105 || 31\'h4634) * ((r174 == (r61 || ( & ( ( + ( 6\'he)))))) <= r233)) / $stime) || (((20\'h55e8 * 20\'h57da) != 27\'h10ab) && (((( ( ^ ( (25\'h574b != 25\'h59bb))) % ((5\'h13 === 17\'h4256) !== (28\'h5ecc !== 1\'h1))) <= ( | ( r173))) !== $stime) || (( ( ! ( ($time >= (12\'h42c | 23\'h60eb)))) % (($stime >= 14\'h23de) == r219)) > r65)))) && (18\'h7c43 !== r96)) != (( ( - ( ( ( - ( ((r100 ? ( & ( r142)) : ( - ( r30))) === r236))) < ( ! ( r38))))) | $stime) - (( ( | ( r68)) < ( ^ ( (29\'h6ea5 === ((((10\'h243 === 31\'h625f) > ( ~ ( 26\'h75a))) - r95) <= ( | ( (r92 === $stime)))))))) > ( & ( ($stime >= r76)))))))) | r92) ^ (10\'h2f2 !== $stime)) >= r103)); +\t\t#10; r35 = (31\'h1e3a * 13\'h289); +\t\t#10; r50 = ( ( + ( ( ( - ( 13\'h1945)) & ( | ( ( ! ( r128))))))) * (((($stime >= 7\'h61) || (((( ( ! ( (r180 > r44))) * (($stime >= (( ( + ( r106)) == ( ~ ( 32\'h59e7))) || 5\'h9)) && 13\'hcd)) < ( ( & ( 15\'h5791)) === ( + ( ($time - (((( ( ~ ( 30\'h6092)) & r184) + 31\'h27e1) == ((31\'h1dfa + 7\'h68) != ( ~ ( 22\'h10ab)))) & (16\'h30ab / r158))))))) ? 12\'hcb7 : (31\'h4c6d !== (26\'h4e33 < ((20\'h1dcd / ((( ( & ( (23\'h3c7c < 4\'h6))) % ( ( | ( 18\'h6b37)) / (31\'h56e7 - 9\'h1b5))) - r174) >= 12\'h281)) !== (r100 * r11))))) ^ r201)) * ( | ( 21\'h41a0))) <= r130)); +\t\t#10; r17 = ( & ( ( + ( r76)))); +\t\t#10; r99 = ( ~ ( ((((r50 + (((r49 / (($stime * $stime) >= ( | ( r137)))) > (r27 <= 9\'h151)) / ((((((r222 > r101) % r93) + ( ^ ( (3\'h2 || ( - ( 28\'h2340)))))) == ( ( ^ ( (r62 | (r201 === $time)))) <= 18\'h6c9e)) > ( | ( r235))) <= ( ( ^ ( (((22\'h402 | 12\'h9b) | r92) * (r181 / ((r17 & $time) > r160))))) != r20)))) & (((r109 >= ((r237 == ( ( + ( ((((27\'h7c62 > 5\'h10) || 28\'h4e87) | ((17\'h62af === 21\'h4f4) < ( ! ( 22\'h4838)))) >= $stime))) && 23\'h2eb3)) ^ ( ( ^ ( (r112 < (r212 > 6\'h3d)))) ^ ((( ( + ( 8\'hcc)) && 22\'h6bf5) >= (r109 <= (((8\'h3a == 25\'h11d) == 19\'h19b8) / ( & ( $time))))) ^ (32\'h174d % 31\'h75c7))))) / ((r37 >= ( ( ! ( ( ~ ( (r0 <= ((r215 * 27\'h649a) + 20\'h7c51)))))) < r221)) !== ( ^ ( r159)))) === r133)) + (23\'h38d1 ? ((($stime ? ( - ( ( - ( ( ( & ( ($time < r66))) ? r170 : (( ( ^ ( ((20\'h6ff5 * 26\'h4341) - r78))) / r196) < r246)))))) : ( ( + ( ( ( | ( ( ^ ( 18\'h3e9)))) ? r129 : r245))) % ( ! ( r128)))) / $time) * r156) : 16\'h1426)) == 9\'h114))); +\t\t#10; r102 = ( ^ ( ( ^ ( ((r211 ^ (r229 === r249)) < (((r17 * r174) * r229) <= ( ( & ( 26\'h56cf)) || $time))))))); +\t\t#10; r7 = r109; +\t\t#10; r195 = (r100 - r246); +\t\t#10; r248 = ( ! ( ((r14 === (((r120 > ( ( | ( r100)) !== ( ! ( 2\'h2)))) > (( ( & ( 6\'h18)) % ( | ( 1\'h0))) && ( + ( r251)))) / ( ~ ( ((r233 - 24\'h7a6a) / r56))))) === ( ( - ( r104)) != ( ^ ( 1\'h0)))))); +\t\t#10; r160 = r14; +\t\t#10; r164 = r57; +\t\t#10; r26 = ( ~ ( r63)); +\t\t#10; r20 = 27\'h7948; +\t\t#10; r33 = (((r235 > ( ( + ( ((22\'h4078 % 28\'h43d5) ^ ( ( | ( ( + ( r216)))) == r196)))) || (((14\'h3a11 - $stime) == ((r45 - 5\'h5) ^ ( ~ ( ( ( + ( (((((11\'h70b | 19\'h604f) > (29\'h2b8 * 4\'h8)) ^ r130) && ( ( & ( (13\'h2b5 - 14\'h34f9))) ^ ($stime < 10\'ha5))) < r19))) * (((( ( ^ ( (7\'h51 === 9\'h7d))) / ( & ( r242))) * ( + ( (r120 * (31\'h3f97 != 27\'h5c58))))) & 6\'h2f) < ( ( & ( r148)) ^ ( + ( 14\'hfd5))))))))) == ( ! ( r231))))) + r248) && ((r48 | (r187 | (r221 == ((r42 & r204) == r140)))) < r15)); +\t\t#10; r221 = (16\'h49d1 || (r58 + ( ( + ( ( ^ ( r240)))) > r5))); +\t\t#10; r245 = ($time | $time); +\t\t#10; r80 = r72; +\t\t#10; r47 = $stime; +\t\t#10; r43 = r104; +\t\t#10; r128 = r105; +\t\t#10; r253 = r67; +\t\t#10; r145 = r81; +\t\t#10; r126 = 15\'h9eb; +\t\t#10; r24 = r162; +\t\t#10; r233 = $time; +\t\t#10; r182 = ( ! ( (($time ^ (r171 === 11\'h452)) - r95))); +\t\t#10; r94 = r219; +\t\t#10; r231 = (((((r234 == r75) - ( ^ ( $time))) | ( ( & ( ((((( ( + ( ((((19\'h3cbc != 29\'h50b3) === r179) === $time) >= 31\'h7c7b))) > ( ( & ( ((r174 & (3\'h0 - 18\'h4c8f)) / 23\'h16fc))) !== ( | ( ( ^ ( ((32\'h1b5c * 24\'h1c03) > r120))))))) || (( ( ^ ( r53)) != ((((8\'hec <= 9\'h169) !== $stime) === ( ( - ( 16\'h304e)) < (26\'h3834 <= 18\'h58bc))) ? 25\'h6ca3 : 27\'h60a2)) >= 7\'h74)) - $stime) !== ( ( & ( (r193 <= r106))) && ( & ( ((9\'hc || r173) != r85))))) / ( ~ ( ((r82 / 25\'h5809) <= ((r166 % (10\'he3 - ( ! ( ( ( ~ ( ( + ( 21\'h5ea1)))) ? 32\'h6caa : $stime))))) === (($time !== 15\'h2f0c) > ((r134 && r13) & r131))))))))) < ((19\'h706d && ($time & (($time === 18\'h786a) <= 13\'h1ed6))) ? (r176 == r217) : (r15 < (19\'h4b23 ^ 20\'h3584))))) ? 19\'h46f1 : 16\'h10bc) ^ (28\'h57a5 >= ( | ( $stime)))); +\t\t#10; r64 = (((( ( & ( ((((19\'h1c36 >= 27\'h1fc7) ^ r191) <= 18\'h479f) && ((((((17\'h38f5 / 16\'h7871) > r19) < ( ^ ( ( ( ! ( r255)) <= ((r196 / $time) ? ( & ( r91)) : $stime))))) - (15\'hc67 ^ ( ( ! ( (( ( | ( 10\'h2bd)) == (9\'hba > 4\'h8)) + r104))) >= ( & ( r46))))) !== ( ( & ( r158)) - (( ( & ( 27\'h5bca)) ^ ( ~ ( r185))) === (r208 | ( ! ( (((31\'h3393 && 24\'h16f4) <= (14\'he7a / 15\'h3c50)) & r73))))))) != ( ( ! ( 5\'h14)) >= ( ( ^ ( 25\'h2f7f)) / r25)))))) + ((7\'h32 ^ (( ( + ( ((((r171 == ( - ( (24\'h24c9 != 27\'h188c)))) % (21\'h1cd3 !== ((21\'h4f82 !== 5\'h5) !== (30\'h592c && 31\'h4d6)))) & ( ( | ( 32\'h10e6)) * (r51 < (2\'h3 && ( ! ( 9\'hb5)))))) >= ((( ( - ( r100)) + (r94 < (4\'h9 - 19\'h7687))) / 30\'h3d99) < ((22\'h1717 <= (30\'h7a58 ? 23\'h26de : (2\'h3 * 32\'h15f2))) + r226))))) || r220) ^ r147)) & r163)) && 25\'h4a4b) === r71) | 13\'h13da); +\t\t#10; r247 = ((r64 >= (6\'h6 - 30\'h1466)) < 10\'h89); +\t\t#10; r80 = 19\'h4198; +\t\t#10; r186 = r249; +\t\t#10; r95 = r153; +\t\t#10; r32 = 17\'h76a7; +\t\t#10; r81 = ((r230 & r127) >= ( ( ^ ( r166)) == (20\'h625d % r106))); +\t\t#10; r150 = r47; +\t\t#10; r16 = ( ( ! ( ( - ( r127)))) == (20\'h2d74 ^ ((( ( & ( ( + ( ($time === ( | ( r121))))))) - r238) | ((26\'h7f81 | r147) || (16\'h564f & r121))) | 29\'h30a3))); +\t\t#10; r159 = 7\'h5; +\t\t#10; r50 = r178; +\t\t#10; r198 = (( ( ! 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+\t\t$displayb(""r94 = "",r94); +\t\t$displayb(""r95 = "",r95); +\t\t$displayb(""r96 = "",r96); +\t\t$displayb(""r97 = "",r97); +\t\t$displayb(""r98 = "",r98); +\t\t$displayb(""r99 = "",r99); +\t\t$displayb(""r100 = "",r100); +\t\t$displayb(""r101 = "",r101); +\t\t$displayb(""r102 = "",r102); +\t\t$displayb(""r103 = "",r103); +\t\t$displayb(""r104 = "",r104); +\t\t$displayb(""r105 = "",r105); +\t\t$displayb(""r106 = "",r106); +\t\t$displayb(""r107 = "",r107); +\t\t$displayb(""r108 = "",r108); +\t\t$displayb(""r109 = "",r109); +\t\t$displayb(""r110 = "",r110); +\t\t$displayb(""r111 = "",r111); +\t\t$displayb(""r112 = "",r112); +\t\t$displayb(""r113 = "",r113); +\t\t$displayb(""r114 = "",r114); +\t\t$displayb(""r115 = "",r115); +\t\t$displayb(""r116 = "",r116); +\t\t$displayb(""r117 = "",r117); +\t\t$displayb(""r118 = "",r118); +\t\t$displayb(""r119 = "",r119); +\t\t$displayb(""r120 = "",r120); +\t\t$displayb(""r121 = "",r121); +\t\t$displayb(""r122 = "",r122); +\t\t$displayb(""r123 = "",r123); +\t\t$displayb(""r124 = "",r124); +\t\t$displayb(""r125 = "",r125); +\t\t$displayb(""r126 = "",r126); +\t\t$displayb(""r127 = "",r127); +\t\t$displayb(""r128 = "",r128); +\t\t$displayb(""r129 = "",r129); +\t\t$displayb(""r130 = "",r130); +\t\t$displayb(""r131 = "",r131); +\t\t$displayb(""r132 = "",r132); +\t\t$displayb(""r133 = "",r133); +\t\t$displayb(""r134 = "",r134); +\t\t$displayb(""r135 = "",r135); +\t\t$displayb(""r136 = "",r136); +\t\t$displayb(""r137 = "",r137); +\t\t$displayb(""r138 = "",r138); +\t\t$displayb(""r139 = "",r139); +\t\t$displayb(""r140 = "",r140); +\t\t$displayb(""r141 = "",r141); +\t\t$displayb(""r142 = "",r142); +\t\t$displayb(""r143 = "",r143); +\t\t$displayb(""r144 = "",r144); +\t\t$displayb(""r145 = "",r145); +\t\t$displayb(""r146 = "",r146); +\t\t$displayb(""r147 = "",r147); +\t\t$displayb(""r148 = "",r148); +\t\t$displayb(""r149 = "",r149); +\t\t$displayb(""r150 = "",r150); +\t\t$displayb(""r151 = "",r151); +\t\t$displayb(""r152 = "",r152); +\t\t$displayb(""r153 = "",r153); +\t\t$displayb(""r154 = "",r154); +\t\t$displayb(""r155 = "",r155); +\t\t$displayb(""r156 = "",r156); +\t\t$displayb(""r157 = "",r157); +\t\t$displayb(""r158 = "",r158); +\t\t$displayb(""r159 = "",r159); +\t\t$displayb(""r160 = "",r160); +\t\t$displayb(""r161 = "",r161); +\t\t$displayb(""r162 = "",r162); +\t\t$displayb(""r163 = "",r163); +\t\t$displayb(""r164 = "",r164); +\t\t$displayb(""r165 = "",r165); +\t\t$displayb(""r166 = "",r166); +\t\t$displayb(""r167 = "",r167); +\t\t$displayb(""r168 = "",r168); +\t\t$displayb(""r169 = "",r169); +\t\t$displayb(""r170 = "",r170); +\t\t$displayb(""r171 = "",r171); +\t\t$displayb(""r172 = "",r172); +\t\t$displayb(""r173 = "",r173); +\t\t$displayb(""r174 = "",r174); +\t\t$displayb(""r175 = "",r175); +\t\t$displayb(""r176 = "",r176); +\t\t$displayb(""r177 = "",r177); +\t\t$displayb(""r178 = "",r178); +\t\t$displayb(""r179 = "",r179); +\t\t$displayb(""r180 = "",r180); +\t\t$displayb(""r181 = "",r181); +\t\t$displayb(""r182 = "",r182); +\t\t$displayb(""r183 = "",r183); +\t\t$displayb(""r184 = "",r184); +\t\t$displayb(""r185 = "",r185); +\t\t$displayb(""r186 = "",r186); +\t\t$displayb(""r187 = "",r187); +\t\t$displayb(""r188 = "",r188); +\t\t$displayb(""r189 = "",r189); +\t\t$displayb(""r190 = "",r190); +\t\t$displayb(""r191 = "",r191); +\t\t$displayb(""r192 = "",r192); +\t\t$displayb(""r193 = "",r193); +\t\t$displayb(""r194 = "",r194); +\t\t$displayb(""r195 = "",r195); +\t\t$displayb(""r196 = "",r196); +\t\t$displayb(""r197 = "",r197); +\t\t$displayb(""r198 = "",r198); +\t\t$displayb(""r199 = "",r199); +\t\t$displayb(""r200 = "",r200); +\t\t$displayb(""r201 = "",r201); +\t\t$displayb(""r202 = "",r202); +\t\t$displayb(""r203 = "",r203); +\t\t$displayb(""r204 = "",r204); +\t\t$displayb(""r205 = "",r205); +\t\t$displayb(""r2'b'06 = "",r206); +\t\t$displayb(""r207 = "",r207); +\t\t$displayb(""r208 = "",r208); +\t\t$displayb(""r209 = "",r209); +\t\t$displayb(""r210 = "",r210); +\t\t$displayb(""r211 = "",r211); +\t\t$displayb(""r212 = "",r212); +\t\t$displayb(""r213 = "",r213); +\t\t$displayb(""r214 = "",r214); +\t\t$displayb(""r215 = "",r215); +\t\t$displayb(""r216 = "",r216); +\t\t$displayb(""r217 = "",r217); +\t\t$displayb(""r218 = "",r218); +\t\t$displayb(""r219 = "",r219); +\t\t$displayb(""r220 = "",r220); +\t\t$displayb(""r221 = "",r221); +\t\t$displayb(""r222 = "",r222); +\t\t$displayb(""r223 = "",r223); +\t\t$displayb(""r224 = "",r224); +\t\t$displayb(""r225 = "",r225); +\t\t$displayb(""r226 = "",r226); +\t\t$displayb(""r227 = "",r227); +\t\t$displayb(""r228 = "",r228); +\t\t$displayb(""r229 = "",r229); +\t\t$displayb(""r230 = "",r230); +\t\t$displayb(""r231 = "",r231); +\t\t$displayb(""r232 = "",r232); +\t\t$displayb(""r233 = "",r233); +\t\t$displayb(""r234 = "",r234); +\t\t$displayb(""r235 = "",r235); +\t\t$displayb(""r236 = "",r236); +\t\t$displayb(""r237 = "",r237); +\t\t$displayb(""r238 = "",r238); +\t\t$displayb(""r239 = "",r239); +\t\t$displayb(""r240 = "",r240); +\t\t$displayb(""r241 = "",r241); +\t\t$displayb(""r242 = "",r242); +\t\t$displayb(""r243 = "",r243); +\t\t$displayb(""r244 = "",r244); +\t\t$displayb(""r245 = "",r245); +\t\t$displayb(""r246 = "",r246); +\t\t$displayb(""r247 = "",r247); +\t\t$displayb(""r248 = "",r248); +\t\t$displayb(""r249 = "",r249); +\t\t$displayb(""r250 = "",r250); +\t\t$displayb(""r251 = "",r251); +\t\t$displayb(""r252 = "",r252); +\t\t$displayb(""r253 = "",r253); +\t\t$displayb(""r254 = "",r254); +\t\t$finish(0); +\tend +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always while (boolean_expression ) statement ; + + +module main ; + +reg [3:0] value1,value2,value3; + +initial +\tbegin + value1 = 0;\t\t// Time 0 assignemnt + value2 = 0; + #6 ; + if(value1 != 4\'h1) + begin + $display(""FAILED - 3.1.7C always while (1\'b1 )"") ; + value2 = 1; + end + #5 ; + if(value1 != 4\'h2) + begin + $display(""FAILED - 3.1.7C always while (1\'b1) ""); + value2 = 1; + end + #5 ; + if(value1 != 4\'h3) + begin + $display(""FAILED - 3.1.7C always while (1\'b1) ""); + value2 = 1; + end + if(value2 == 0) + $display(""PASSED""); +\t $finish; + end + +always while (1\'b1 && 1\'b1) begin + #5 ; + value1 = value1 + 1; +\t\t\t end + + +endmodule +" +"module test(); + parameter BITS = 4; + parameter C = 1; + + wire [BITS-1:0] a; + reg [BITS-1:0] a_bc; + assign\t a = a_bc - 2*C; + + initial begin + a_bc = 9; + #1 if (a !== 7) begin +\t $display(""FAILED -- a_bc=%d, a=%d"", a_bc, a); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule +" +"module top; + reg pass; + time change; + reg in; + wire c1, c2a, c2b, c3; + wire v1, v2, v3; + + const_1 d_c1(c1, in); + const_2a d_c2a(c2a, in); + const_2b d_c2b(c2b, in); + const_3 d_c3(c3, in); + + var_1 d_v1(v1, in); +// var_2 d_v2(v2, in); + var_3 d_v3(v2, in); + + initial begin + pass = 1\'b1; + #1000 in = 1\'b0; + #1000 in = 1\'b1; + #1000 in = 1\'b0; + #1000 in = 1\'b1; + #1000 in = 1\'bx; + #1000 in = 1\'b0; + #1000 in = 1\'bx; + #1000 in = 1\'b1; + #1000 in = 1\'b0; + #1000 if (pass) $display(""PASSED""); + end + + always @(in) change = $time; +endmodule + +// All delays should be 200. +module const_1 (output out, input in); + assign #(200) out = (in === 1\'bx) ? 1\'bz : ~in; + + always @(out) begin + case (out) + 1\'b0: if ($time - top.change != 200) begin + $display(""Failed const_1 fall""); + top.pass = 1\'b0; + end + 1\'b1: if ($time - top.change != 200) begin + $display(""Failed const_1 rise""); + top.pass = 1\'b0; + end + 1\'bz: if ($time - top.change != 200) begin + $display(""Failed const_1 high-Z""); + top.pass = 1\'b0; + end + default: begin + $display(""FAILED const_1 default""); + top.pass = 1\'b0; + end + endcase + end +endmodule + +// Decay should also be 100. +module const_2a (output out, input in); + assign #(200, 100) out = (in === 1\'bx) ? 1\'bz : ~in; + + always @(out) begin + case (out) + 1\'b0: if ($time - top.change != 100) begin + $display(""Failed const_2a fall""); + top.pass = 1\'b0; + end + 1\'b1: if ($time - top.change != 200) begin + $display(""Failed const_2a rise""); + top.pass = 1\'b0; + end + 1\'bz: if ($time - top.change != 100) begin + $display(""Failed const_2a high-Z""); + top.pass = 1\'b0; + end + default: begin + $display(""FAILED const_2a default""); + top.pass = 1\'b0; + end + endcase + end +endmodule + +// Decay should also be 100. +module const_2b (output out, input in); + assign #(100, 200) out = (in === 1\'bx) ? 1\'bz : ~in; + + always @(out) begin + case (out) + 1\'b0: if ($time - top.change != 200) begin + $display(""Failed const_2b fall""); + top.pass = 1\'b0; + end + 1\'b1: if ($time - top.change != 100) begin + $display(""Failed const_2b rise""); + top.pass = 1\'b0; + end + 1\'bz: if ($time - top.change != 100) begin + $display(""Failed const_2b high-Z""); + top.pass = 1\'b0; + end + default: begin + $display(""FAILED const_2b default""); + top.pass = 1\'b0; + end + endcase + end +endmodule + +// All delays as given. +module const_3 (output out, input in); + assign #(100, 200, 300) out = (in === 1\'bx) ? 1\'bz : ~in; + + always @(out) begin + case (out) + 1\'b0: if ($time - top.change != 200) begin + $display(""Failed const_3 fall""); + top.pass = 1\'b0; + end + 1\'b1: if ($time - top.change != 100) begin + $display(""Failed const_3 rise""); + top.pass = 1\'b0; + end + 1\'bz: if ($time - top.change != 300) begin + $display(""Failed const_3 high-Z""); + top.pass = 1\'b0; + end + default: begin + $display(""FAILED const_3 default""); + top.pass = 1\'b0; + end + endcase + end +endmodule + +// All delays should be delay. +module var_1 (output out, input in); + time delay = 200; + assign #(delay) out = (in === 1\'bx) ? 1\'bz : ~in; + + always @(out) begin + case (out) + 1\'b0: if ($time - top.change != delay) begin + $display(""Failed var_1 fall""); + top.pass = 1\'b0; + end + 1\'b1: if ($time - top.change != delay) begin + $display(""Failed var_1 rise""); + top.pass = 1\'b0; + end + 1\'bz: if ($time - top.change != delay) begin + $display(""Failed var_1 high-Z""); + top.pass = 1\'b0; + end + default: begin + $display(""FAILED var_1 default""); + top.pass = 1\'b0; + end + endcase + end +endmodule + +/* + * We do not currently support calculating the decay time from the + * variable rise and fall times. The compiler will print a message + * and assert in the code generator. + * + * We need an a and b version to check both ways. + * +// Decay should be the minimum of rise and fall delay. +module var_2 (output out, input in); + time delayr = 100; + time delayf = 200; + assign #(delayr, delayf) out = ~in; + + function automatic real min_real(real a, real b); + min_real = a < b ? a : b; + endfunction + + always @(out) begin + case (out) + 1\'b0: if ($time - top.change != delayf) begin + $display(""Failed var_2 fall""); + top.pass = 1\'b0; + end + 1\'b1: if ($time - top.change != delayr) begin + $display(""Failed var_2 rise""); + top.pass = 1\'b0; + end + 1\'bz: if ($time - top.change != min_real(delayf, delayr)) begin + $display(""Failed var_2 high-Z""); + top.pass = 1\'b0; + end + default: begin + $display(""FAILED var_2 default""); + top.pass = 1\'b0; + end + endcase + end +endmodule +*/ + +// All delays as given. +module var_3 (output out, input in); + time delayr = 100; + time delayf = 200; + time delayd = 300; + assign #(delayr, delayf, delayd) out = (in === 1\'bx) ? 1\'bz : ~in; + + always @(out) begin + case (out) + 1\'b0: if ($time - top.change != delayf) begin + $display(""Failed var_3 fall""); + top.pass = 1\'b0; + end + 1\'b1: if ($time - top.change != delayr) begin + $display(""Failed var_3 rise""); + top.pass = 1\'b0; + end + 1\'bz: if ($time - top.change != delayd) begin + $display(""Failed var_3 high-Z""); + top.pass = 1\'b0; + end + default: begin + $display(""FAILED var_3 default""); + top.pass = 1\'b0; + end + endcase + end +endmodule +" +"// +// Copyright (c) 1999 Thomas Coonan (tcoonan@mindspring.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// **** Here\'s a simple, sequential multiplier. Very simple, unsigned.. +// Not very well tested, play with testbench, use at your own risk, blah blah blah.. +// + +// +// Unsigned 16-bit multiply (multiply two 16-bit inputs to get a 32-bit output) +// +// Present data and assert start synchronous with clk. +// Assert start for ONLY one cycle. +// Wait N cycles for answer (at most). Answer will remain stable until next start. +// You may use DONE signal as handshake. +// +// Written by tom coonan +// +module mult16 (clk, resetb, start, done, ain, bin, yout); +parameter N = 16; +input\t\t\tclk; +input\t\t\tresetb; +input\t\t\tstart; // Register the ain and bin inputs (they can change afterwards) +//input [N-1:0]\t\tain; +//input [N-1:0]\t\tbin; +//output [2*N-1:0]\tyout; +input [15:0]\t\tain; +input [15:0]\t\tbin; +output [31:0]\tyout; + +output\t\t\tdone; + +//reg [2*N-1:0]\t\ta; +//reg [N-1:0]\t\tb; +//reg [2*N-1:0]\t\tyout; +reg [31:0]\t\ta; +reg [15:0]\t\tb; +reg [31:0]\t\tyout; + +reg\t\tdone; + +always @(posedge clk or negedge resetb) begin + if (~resetb) begin + a <= 0; + b <= 0; + yout <= 0; + done <= 1\'b1; + end + else begin + // Load will register the input and clear the counter. + if (start) begin + a <= ain; + b <= bin; + yout <= 0; + done <= 0; + end + else begin + // Go until b is zero + if (~done) begin + if (b != 0) begin + // If \'1\' then add a to sum + if (b[0]) begin + yout <= yout + a; + end + b <= b >> 1; + a <= a << 1; + $display (""a = %h, b = %h, yout = %h"", a,b,yout); + end + else begin + done <= 1\'b1; + end + end + end + end +end +endmodule + + +module mul16; +reg clk, resetb, start; +reg [15:0] a; +reg [15:0] b; +wire [31:0] y; +wire done; + +mult16 mult16inst (clk, resetb, start, done, a, b, y); + +initial begin + clk = 0; + forever begin + #10 clk = ~clk; + end +end + +initial begin + resetb = 0; + #30 resetb = 1; +end + +integer num_errors; +parameter MAX_TRIALS = 10; + +initial begin +// $dumpfile (""multdiv.vcd""); +// $dumpvars (0,a); +// $dumpvars (0,b); +// $dumpvars (0,y); +// $dumpvars (0,resetb); +// $dumpvars (0,done); + num_errors = 0; + + #100; + + // Do a bunch of random multiplies + repeat (MAX_TRIALS) begin + test_multiply ($random, $random); + end + + // Special cases + test_multiply ($random, 1); + test_multiply (1, $random); + test_multiply ($random, 0); + test_multiply (0, $random); + + $display (""Done. %0d Errors"", num_errors); + #800; + $finish; +end + +task test_multiply; + input [15:0] aarg; + input [15:0] barg; + + integer expected_answer; + + begin + if (~done) begin + $display (""Multiplier is Busy!!""); + end + else begin + @(negedge clk); + start = 1; + a = aarg; + b = barg; + @(negedge clk) start = 0; + @(posedge done); + expected_answer = a*b; + $display (""%0d * %0d = %0h, Reality = %0h"", a, b, y, expected_answer); + if (y !== expected_answer) begin + $display ("" FAILURE!""); + num_errors = num_errors + 1; + end + end + end +endtask + +endmodule +" +"module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:0]; + +assign Array[0][0] = In[0]; +assign Array[0][7:1] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:N] = Array[0][7:1]; +end + +endmodule +" +"module top; + reg pass; + integer result; + reg [3:0] expr; + reg bval; + + initial begin + pass = 1\'b1; + + result = $countbits(1\'bx, 1\'bx); + if (result != 1) begin + $display(""FAILED: for 1\'bx/x expected a count of 1, got %d"", result); + pass = 1\'b0; + end + + result = $countbits(2\'bxx, 1\'bx); + if (result != 2) begin + $display(""FAILED: for 2\'bxx/x expected a count of 2, got %d"", result); + pass = 1\'b0; + end + + result = $countbits(2\'bxz, 1\'bz, 1\'bx); + if (result != 2) begin + $display(""FAILED: for 2\'bxz/zx expected a count of 2, got %d"", result); + pass = 1\'b0; + end + + result = $countbits(4\'b01zx, 1\'bz, 1\'bx); + if (result != 2) begin + $display(""FAILED: for 4\'b01zx/zx expected a count of 2, got %d"", result); + pass = 1\'b0; + end + + result = $countbits(4\'b01zx, 1\'b0, 1\'b1); + if (result != 2) begin + $display(""FAILED: for 4\'b01zx/01 expected a count of 2, got %d"", result); + pass = 1\'b0; + end + + bval = 1\'b0; + expr = 4\'b1001; + result = $countbits(expr, bval); + if (result != 2) begin + $display(""FAILED: for 4\'b1001/0 expected a count of 2, got %d"", result); + pass = 1\'b0; + end + + bval = 1\'b1; + result = $countbits(expr, bval); + if (result != 2) begin + $display(""FAILED: for 4\'b1001/1 expected a count of 2, got %d"", result); + pass = 1\'b0; + end + + result = $countbits(34\'bzx00000000000000000000000000000000, 1\'bz, 1\'bx); + if (result != 2) begin + $display(""FAILED: for 34\'zx00000000000000000000000000000000/zx expected a count of 2, got %d"", result); + pass = 1\'b0; + end + + result = $countbits(34\'bzxxz000000xz000000xz000000xz000000, 1\'bz, 1\'bx); + if (result != 10) begin + $display(""FAILED: for 34\'zxxz000000xz000000xz000000xz000000/zx expected a count of 10, got %d"", result); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end + +endmodule +" +"/* + * This is a reduced example from comp1001 to demonstrate a problem + * in the Icarus Verilog code generator. If the left && argument is + * replaced with a single 1\'b1 which should be logically equivalent + * this will work correctly. It appears that the width of the + * expression is being calculated incorrectly. + */ +module top; + reg [119:110] r163; + reg [192:162] r222; + + initial begin + r163 = 10\'h17d; + + r222 = (1\'b1 + (22\'h3a15 && ((^r163) < 4\'h8))) != 1\'bx; + + // ... the subexpression ^r163 is the 1-bit value 1\'b1 + // = (1\'b1 + (22\'h3a15 && ((1\'b1) < 4\'h8))) != 1\'bx + // ... the operands of && are self determined, but the widths of the + // operands of < must match + // = (1\'b1 + (22\'h3a15 && (4\'h1 < 4\'h8))) != 1\'bx + // ... The && is a 1\'bit result. + // = (1\'b1 + 1\'b1) != 1\'bx + // ... Operands of != are sized to max of i and j, namely 1 in this case. + // = 1\'b0 != 1\'bx + // = 1\'bx + // ... but the result is 31 bits, so the result is... + // = 31\'b0x + + if (r222 !== 31\'b0x) $display(""FAILED -- r222=%b"", r222); + else $display(""PASSED""); + end +endmodule +" +"// This is currently unsupported, but is legal code. +module test(); + +typedef enum { a, b, c } enum_type; + +enum_type enum_value; + +assign enum_value = enum_type'(1); + +endmodule +" +"/* + * This program is derived from iverilog issue # 1327436. + */ + +`timescale 1ns/1ns +module verilog_test (); + +reg [24:0] APAD; +wire [24:0] AIN; + +initial begin +// $dumpfile(""dumpfile.vcd""); +// $dumpvars; + + APAD=25\'h1ffffff; + #21 if (AIN !== APAD) begin + $display(""FAILED -- APAD=%b, AIN=%b, time=%0t"", APAD, AIN, $time); + $finish; + end + + #79 + APAD=25\'h1555555; + + #19 if (AIN !== 25\'h1ffffff) begin + $display(""FAILED -- APAD=%b, AIN=%b, time=%0t"", APAD, AIN, $time); + $finish; + end + #2 if (AIN !== 25\'h1555555) begin + $display(""FAILED -- APAD=%b, AIN=%b, time=%0t"", APAD, AIN, $time); + $finish; + end + + #79 + APAD=25\'h0aaaaaa; + + #19 if (AIN !== 25\'h1555555) begin + $display(""FAILED -- APAD=%b, AIN=%b, time=%0t"", APAD, AIN, $time); + $finish; + end + #2 if (AIN !== 25\'h0aaaaaa) begin + $display(""FAILED -- APAD=%b, AIN=%b, time=%0t"", APAD, AIN, $time); + $finish; + end + + #79 + APAD=25\'h1555555; + + #19 if (AIN !== 25\'h0aaaaaa) begin + $display(""FAILED -- APAD=%b, AIN=%b, time=%0t"", APAD, AIN, $time); + $finish; + end + #2 if (AIN !== 25\'h1555555) begin + $display(""FAILED -- APAD=%b, AIN=%b, time=%0t"", APAD, AIN, $time); + $finish; + end + + #79 + APAD=25\'h0aaaaaa; + + #19 if (AIN !== 25\'h1555555) begin + $display(""FAILED -- APAD=%b, AIN=%b, time=%0t"", APAD, AIN, $time); + $finish; + end + #2 if (AIN !== 25\'h0aaaaaa) begin + $display(""FAILED -- APAD=%b, AIN=%b, time=%0t"", APAD, AIN, $time); + $finish; + end + + $display(""PASSED""); +end + +assign #20 AIN= APAD; +endmodule +" +"module main; + + // Declare word1 as a VARIABLE + struct packed { + logic [7:0] high; + logic [7:0] low; + } word1; + + // Declare word2 as a NET + wire struct packed { + logic [7:0] high; + logic [7:0] low; + } word2; + + assign word2.high = word1.high; + assign word2.low = word1.low; + + initial begin + word1 = 16\'haa_55; + if (word1.high !== 8\'haa || word1.low !== 8\'h55) begin +\t $display(""FAILED: word1 = %h, word1.high = %h, word1.low = %h"", +\t\t word1, word1.high, word1.low); +\t $finish; + end + + #1 /* Make sure word2 assign propagates */; + + if (word2.high !== 8\'haa || word2.low !== 8\'h55) begin +\t $display(""FAILED: word2 = %h, word2.high = %h, word2.low = %h"", +\t\t word1, word2.high, word2.low); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"`define MACRO(_param_,_def_) \\ +`ifdef _def_ \\ +module _param_ (); \\ +endmodule \\ +`endif + +`MACRO(FOFO, CFG_FOFO) +" +"module test; + string x[], y[], z[]; + string src[0:7]; + int\t i; + + initial begin + src[0] = ""a""; + src[1] = ""b""; + src[2] = ""c""; + src[3] = ""d""; + src[4] = ""e""; + src[5] = ""f""; + src[6] = ""g""; + src[7] = ""h""; + + x = new [4]; + + for (i = 0; i < 4; i = i + 1) x[i] = src[i]; + + y = x; + z = new [4](x); + for (i = 0; i < 4; i = i + 1) y[i] = src[3 - i]; + for (i = 0; i < 4; i = i + 1) z[i] = src[7 - i]; + // Expected output: + // a b c d + // d c b a + // h g f e + $display(x[0],,x[1],,x[2],,x[3]); + $display(y[0],,y[1],,y[2],,y[3]); + $display(z[0],,z[1],,z[2],,z[3]); + end + +endmodule +" +"module static test(); + +task accumulate1(input integer value, output integer result); +begin:blk + static int acc = 1; + acc = acc + value; + result = acc; +end +endtask + +task automatic accumulate2(input integer value, output integer result); +begin:blk + int acc = 1; + acc = acc + value; + result = acc; +end +endtask + +integer value; + +initial begin + static reg failed = 0; + + accumulate1(2, value); + $display(""%d"", value); + if (value !== 3) failed = 1; + + accumulate1(3, value); + $display(""%d"", value); + if (value !== 6) failed = 1; + + accumulate2(2, value); + $display(""%d"", value); + if (value !== 3) failed = 1; + + accumulate2(3, value); + $display(""%d"", value); + if (value !== 4) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module test(); + +integer src; +reg dst; + +initial begin + assign dst = src; + src = 1; + #1 $display(dst); + if (dst === 1) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module test(); + +specparam sp1 = 1; +specparam sp2 = 2; +specparam [3:0] sp3 = 4\'b0101; + +localparam lp1 = {sp2{1\'b1}}; +localparam lp2 = sp3[sp1 +: sp2]; + +reg pass = 1; + +initial begin + $display(""%b"", lp1); + if (($bits(lp1) != 2) || (lp1 !== 2\'b11)) pass = 0; + $display(""%b"", lp2); + if (($bits(lp2) != 2) || (lp2 !== 2\'b10)) pass = 0; + + if (pass) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"// When registering a simulation time callback, some simulators interpret +// the specified time value as relative to the current simulation time. To +// support this case, define the macro CB_TIME_IS_RELATIVE when compiling +// this module. + +module main; + + integer val1, val2; + + initial begin + val1 = 0; + val2 = 1; + #1; + $poke_at_simtime(val1, 1, 10); + $poke_at_simtime(val2, 2, 10); + +`ifdef CB_TIME_IS_RELATIVE + #1; +`endif + #8; + if (val1 !== 0) begin +\t $display(""FAILED -- val1==%0d before delayed poke"", val1); +\t $finish; + end + if (val2 !== 1) begin +\t $display(""FAILED -- val2==%0d before delayed poke"", val2); +\t $finish; + end + + #1; + if (val1 !== 1) begin +\t $display(""FAILED -- val1==%0d: poke didn\'t happen"", val1); +\t $finish; + end + if (val2 !== 2) begin +\t $display(""FAILED -- val2==%0d: poke didn\'t happen"", val2); +\t $finish; + end + + $display(""PASSED""); + $finish(0); + end + +endmodule // main +" +"/* + * Copyright (c) 2002 Michael Ruff (mruff @chiaro.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module top; + + reg \\bot.r ; + + bot bot(); + + initial begin + #1; + \\bot.r = 1; + #1; + $display(""\\\\bot.r == %b"", \\bot.r ); + $display(""bot.r == %b"", bot.r ); + + if (\\bot.r !== 1) begin +\t $display(""FAILED -- \\\\bot.r !== 1""); +\t $finish; + end + + if (bot.r !== 0) begin +\t $display(""FAILED -- bot.r !== 0""); +\t $finish; + end + + $display(""PASSED""); + end +endmodule // top + +module bot; + + reg r; + + initial begin + r = 0; + end +endmodule +" +"module automatic_error(); + +reg global; + +task automatic auto_task; + +reg local; + +begin:block + force local = global; +end + +endtask + +endmodule +" +"// Check that when the right hand operand of a shift operation +// contains \'x\' or \'z\' bits, the result is undefined. +module test; + reg pass; + reg signed [3:0] lhs; + reg [3:0] rhs; + reg [3:0] res; + + wire [3:0] res1 = lhs << rhs; + wire [3:0] res2 = lhs >> rhs; + wire [3:0] res3 = lhs >>> rhs; + + wire [3:0] res4 = lhs << 4\'b000x; + wire [3:0] res5 = lhs >> 4\'b00x0; + wire [3:0] res6 = lhs >>> 4\'b0z00; + + wire [3:0] res7 = 4\'d1 << 4\'b000x; + wire [3:0] res8 = 4\'d1 >> 4\'b00x0; + wire [3:0] res9 = 4\'d1 >>> 4\'b0z00; + + wire [3:0] res10 = 4\'d0 << rhs; + wire [3:0] res11 = 4\'d0 >> rhs; + wire [3:0] res12 = 4\'d0 >>> rhs; + + initial begin + pass = 1\'b1; + lhs = 4\'d1; + + if (res1 !== 4\'bxxxx) begin + $display(""FAILED test 1, expected 4\'bxxxx, got 4\'b%b"", res1); + pass = 1\'b0; + end + + if (res2 !== 4\'bxxxx) begin + $display(""FAILED test 2, expected 4\'bxxxx, got 4\'b%b"", res2); + pass = 1\'b0; + end + + if (res3 !== 4\'bxxxx) begin + $display(""FAILED test 3, expected 4\'bxxxx, got 4\'b%b"", res3); + pass = 1\'b0; + end + + if (res4 !== 4\'bxxxx) begin + $display(""FAILED test 4, expected 4\'bxxxx, got 4\'b%b"", res4); + pass = 1\'b0; + end + + if (res5 !== 4\'bxxxx) begin + $display(""FAILED test 5, expected 4\'bxxxx, got 4\'b%b"", res5); + pass = 1\'b0; + end + + if (res6 !== 4\'bxxxx) begin + $display(""FAILED test 6, expected 4\'bxxxx, got 4\'b%b"", res6); + pass = 1\'b0; + end + + if (res7 !== 4\'bxxxx) begin + $display(""FAILED test 7, expected 4\'bxxxx, got 4\'b%b"", res7); + pass = 1\'b0; + end + + if (res8 !== 4\'bxxxx) begin + $display(""FAILED test 8, expected 4\'bxxxx, got 4\'b%b"", res8); + pass = 1\'b0; + end + + if (res9 !== 4\'bxxxx) begin + $display(""FAILED test 9, expected 4\'bxxxx, got 4\'b%b"", res9); + pass = 1\'b0; + end + + if (res10 !== 4\'bxxxx) begin + $display(""FAILED test 10, expected 4\'bxxxx, got 4\'b%b"", res10); + pass = 1\'b0; + end + + if (res11 !== 4\'bxxxx) begin + $display(""FAILED test 11, expected 4\'bxxxx, got 4\'b%b"", res11); + pass = 1\'b0; + end + + if (res12 !== 4\'bxxxx) begin + $display(""FAILED test 12, expected 4\'bxxxx, got 4\'b%b"", res12); + pass = 1\'b0; + end + + res = lhs << rhs; + if (res !== 4\'bxxxx) begin + $display(""FAILED test 13, expected 4\'bxxxx, got 4\'b%b"", res); + pass = 1\'b0; + end + + res = lhs >> rhs; + if (res !== 4\'bxxxx) begin + $display(""FAILED test 14, expected 4\'bxxxx, got 4\'b%b"", res); + pass = 1\'b0; + end + + res = lhs >>> rhs; + if (res !== 4\'bxxxx) begin + $display(""FAILED test 15, expected 4\'bxxxx, got 4\'b%b"", res); + pass = 1\'b0; + end + + res = lhs << 4\'b000x; + if (res !== 4\'bxxxx) begin + $display(""FAILED test 16, expected 4\'bxxxx, got 4\'b%b"", res); + pass = 1\'b0; + end + + res = lhs >> 4\'b00x0; + if (res !== 4\'bxxxx) begin + $display(""FAILED test 17, expected 4\'bxxxx, got 4\'b%b"", res); + pass = 1\'b0; + end + + res = lhs >>> 4\'b0z00; + if (res !== 4\'bxxxx) begin + $display(""FAILED test 18, expected 4\'bxxxx, got 4\'b%b"", res); + pass = 1\'b0; + end + + res = 4\'d1 << 4\'b000x; + if (res !== 4\'bxxxx) begin + $display(""FAILED test 19, expected 4\'bxxxx, got 4\'b%b"", res); + pass = 1\'b0; + end + + res = 4\'d1 >> 4\'b00x0; + if (res !== 4\'bxxxx) begin + $display(""FAILED test 20, expected 4\'bxxxx, got 4\'b%b"", res); + pass = 1\'b0; + end + + res = 4\'d1 >>> 4\'b0z00; + if (res !== 4\'bxxxx) begin + $display(""FAILED test 21, expected 4\'bxxxx, got 4\'b%b"", res); + pass = 1\'b0; + end + + res = 4\'d0 << rhs; + if (res !== 4\'bxxxx) begin + $display(""FAILED test 22, expected 4\'bxxxx, got 4\'b%b"", res); + pass = 1\'b0; + end + + res = 4\'d0 >> rhs; + if (res !== 4\'bxxxx) begin + $display(""FAILED test 23, expected 4\'bxxxx, got 4\'b%b"", res); + pass = 1\'b0; + end + + res = 4\'d0 >>> rhs; + if (res !== 4\'bxxxx) begin + $display(""FAILED test 24, expected 4\'bxxxx, got 4\'b%b"", res); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +" +/* + * This is a post-synthesis test for the blif01a.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif01a.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter WID = 4; + reg [WID-1:0] A, B; + wire\t\t QE, QN, QGT, QGE; + + cmpN ucmp(.\\A[3] (A[3]), .\\A[2] (A[2]), .\\A[1] (A[1]), .\\A[0] (A[0]), +\t .\\B[3] (B[3]), .\\B[2] (B[2]), .\\B[1] (B[1]), .\\B[0] (B[0]), +\t .QE(QE), .QN(QN), .QGT(QGT), .QGE(QGE)); + + int\t\t adx; + int\t\t bdx; + initial begin + for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin +\t for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin +\t A <= adx[WID-1:0]; +\t B <= bdx[WID-1:0]; +\t #1 ; +\t if (QE !== (adx[WID-1:0]==bdx[WID-1:0])) begin +\t $display(""FAILED -- A=%b, B=%b, QE=%b"", A, B, QE); +\t $finish; +\t end +\t if (QN !== (adx[WID-1:0]!=bdx[WID-1:0])) begin +\t $display(""FAILED -- A=%b, B=%b, QN=%b"", A, B, QN); +\t $finish; +\t end +\t if (QGT !== (adx[WID-1:0] > bdx[WID-1:0])) begin +\t $display(""FAILED -- A=%b, B=%b, QGT=%b"", A, B, QGT); +\t $finish; +\t end +\t if (QGE !== (adx[WID-1:0] >= bdx[WID-1:0])) begin +\t $display(""FAILED -- A=%b, B=%b, QGE=%b"", A, B, QGE); +\t $finish; +\t end +\t end + end + $display(""PASSED""); + end + +endmodule // main +" +" +/* + * This is a post-wynthesis test for the blif01a.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif01a.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter WID = 4; + reg [WID-1:0] A, B; + wire [WID:0] Q; + + subN usum(.\\A[3] (A[3]), .\\A[2] (A[2]), .\\A[1] (A[1]), .\\A[0] (A[0]), +\t .\\B[3] (B[3]), .\\B[2] (B[2]), .\\B[1] (B[1]), .\\B[0] (B[0]), +\t .\\Q[4] (Q[4]), .\\Q[3] (Q[3]), .\\Q[2] (Q[2]), .\\Q[1] (Q[1]), .\\Q[0] (Q[0])); + + int\t\t adx; + int\t\t bdx; + initial begin + for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin +\t for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin +\t A <= adx[WID-1:0]; +\t B <= bdx[WID-1:0]; +\t #1 if (Q !== (adx[WID-1:0]-bdx[WID-1:0])) begin +\t $display(""FAILED -- A=%b, B=%b, Q=%b"", A, B, Q); +\t $finish; +\t end +\t end + end + $display(""PASSED""); + end + +endmodule // main +" +"/* + * Copyright (c) 1998-2000 Andrei Purdea (andrei@purdea.ro) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + // Test that functions without parantheses for port-list, + // and without any declarations compile successfully. + // Valid according to IEEE1800-2005. + // IEEE1364-2005 requires at least one declaration. + function void empty_function; + endfunction + initial begin + empty_function(); + end +endmodule +" +"`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +// +// Copyright (c) 1999 Steve Tell (tell@telltronics.org) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Concat in fopen not substituted correctly. + +module write_sp_vectors(Clk, a, b, c); +input Clk, a, b, c; + +parameter fname = ""PhCount.unnamed""; +parameter source_id = ""(unknown source module RCSID)$""; + +integer fp; +initial + begin + // fails at runtime: ""ERROR: $fopen parameter must be a constant"" + fp = $fopen({""work/"",fname,"".inv""}); + // this fails too + // fp = $fopen({""blurfl"", "".inv""}); +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $fdisplay(fp, ""# captured from: %0s\ +"", source_id[8*80:8]); +`else + $fdisplay(fp, ""# captured from: %0s\ +"", source_id[$bits(source_id)-1:8]); +`endif + end +endmodule + +module main; +parameter fname = ""PhCount.unnamed""; + +reg clk; +reg a,b,c; + +write_sp_vectors #(""sp2"", ""foo"") v0 (clk,a, b, c); + +initial + begin + #10 $finish; + end +endmodule +" +"module top; + parameter a_res = 16\'b000001xx0xxx0xxx; + parameter o_res = 16\'b01xx1111x1xxx1xx; + parameter x_res = 16\'b01xx10xxxxxxxxxx; + reg pass; + reg [15:0] y, z, a, o, x; + reg [127:0] yl, zl, al, ol, xl; + initial begin + pass = 1\'b1; + + y = 16\'b01xz01xz01xz01xz; + z = 16\'b00001111xxxxzzzz; + yl = {8{y}}; + zl = {8{z}}; + + // Check the & results + a = y & z; + if (a !== a_res) begin + $display(""FAILED: & test, expected %b, got %b"", a_res, a); + pass = 1\'b0; + end + + al = yl & zl; + if (al !== {8{a_res}}) begin + $display(""FAILED: & (large) test, expected %b, got %b"", {8{a_res}}, al); + pass = 1\'b0; + end + + // Check the | results + o = y | z; + if (o !== o_res) begin + $display(""FAILED: | test, expected %b, got %b"", o_res, o); + pass = 1\'b0; + end + + ol = yl | zl; + if (ol !== {8{o_res}}) begin + $display(""FAILED: | (large) test, expected %b, got %b"", {8{o_res}}, ol); + pass = 1\'b0; + end + + // Check the ^ results + x = y ^ z; + if (x !== x_res) begin + $display(""FAILED: | test, expected %b, got %b"", x_res, x); + pass = 1\'b0; + end + + xl = yl ^ zl; + if (xl !== {8{x_res}}) begin + $display(""FAILED: ^ (large) test, expected %b, got %b"", {8{x_res}}, xl); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Report & assert tests. + +module vhdl_report_test; + +logic start_test; +vhdl_report dut(start_test); +int a; + +initial begin + // as of the moment of writing vhdlpp does not handle procedure calls + a = vhdl_report_pkg::test_asserts(0); + + start_test = 1'b0; + #1 start_test = 1'b1; +end +endmodule +" +"// (c) 2001 Kenji KISE ivl-bugs PR#307 + +module top; + reg [63:0] in1,in2; + reg [63:0] out; + + initial begin + in1 = 64\'hffffffffffffffff; + in2 = 64\'hfffffffffffffff7; + out = in1 + in2; + $display(""%h + %h = %h"", in1,in2,out); + if (out === 64\'hfffffffffffffff6) +\t$display(""PASSED""); + else +\t$display(""FAILED""); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate unary or ~^(value) +// + + +module main; + +reg [3:0] vect; +reg\terror; +wire\tresult; + +assign result = ~^(vect); + +initial + begin + error = 0; + for(vect=4\'b0001;vect<4\'b0000;vect = vect << 1) + begin + #1; + if(result !== 1\'b0) + begin + $display(""FAILED - Unary xnor ~^(%b)=%b"",vect,result); + error = 1\'b1; + end + end + #1; + for(vect=4\'b0011;vect<4\'b0000;vect = vect << 1) + begin + #1; + if(result !== 1\'b0) + begin + $display(""FAILED - Unary xnor ~^(%b)=%b"",vect,result); + error = 1\'b1; + end + end + #1; + + vect = 4\'b0000; + #1; + if(result !== 1\'b1) + begin + $display(""FAILED - Unary xnor ~^(%b)=%b"",vect,result); + error = 1\'b1; + end + if(error === 0 ) + $display(""PASSED""); + end + +endmodule // main +" +"/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This checks that ! of x works properly. + */ + +module main; + + reg x; + reg [1:0] xx; + + + initial begin + if (1\'bx !== 1\'bx) begin +\t $display(""FAILED -- simple constant x does\'t compare.""); +\t $finish; + end + + if (1\'bx !== !1\'bx) begin +\t $display(""FAILED -- !1\'bx comes out wrong.""); +\t $finish; + end + + x = 1\'bx; + if (x !== 1\'bx) begin +\t $display(""FAILED -- variable x comes out wrong.""); +\t $finish; + end + + x = !x; + if (x !== 1\'bx) begin +\t $display(""FAILED -- ! of variable x comes out wrong.""); +\t $finish; + end + + xx = 2\'bx0; + if (xx !== 2\'bx0) begin +\t $display(""FAILED -- variable x comes out wrong.""); +\t $finish; + end + + x = !xx; + if (x !== 1\'bx) begin +\t $display(""FAILED -- ! of variable xx comes out wrong.""); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +" +"// deliberately empty +" +"/* + * Copyright (c) 2000 Intrinsity, Inc. + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module test_rpmos (); + +reg gnd, vdd, x, z; +wire t0, t1, t2, t3, t4, t5, t6, t7, + t8, t9, ta, tb, tc, td, te, tf; + +wire StH, StL; + +assign (strong1, highz0) StH = 1\'bx; +assign (highz1, strong0) StL = 1\'bx; + +reg failed; + + +rpmos n0 ( t0, gnd, gnd); +rpmos n1 ( t1, gnd, vdd); +rpmos n2 ( t2, gnd, x); +rpmos n3 ( t3, gnd, z); + +rpmos n4 ( t4, vdd, gnd); +rpmos n5 ( t5, vdd, vdd); +rpmos n6 ( t6, vdd, x); +rpmos n7 ( t7, vdd, z); + +rpmos n8 ( t8, x, gnd); +rpmos n9 ( t9, x, vdd); +rpmos na ( ta, x, x); +rpmos nb ( tb, x, z); + +rpmos nc ( tc, z, gnd); +rpmos nd ( td, z, vdd); +rpmos ne ( te, z, x); +rpmos nf ( tf, z, z); + +initial begin + + assign gnd = 1\'b1; + assign vdd = 1\'b0; + assign x = 1\'b0; + assign z = 1\'b0; + #10; + + assign gnd = 1\'b0; + assign vdd = 1\'b1; + assign x = 1\'b1; + assign z = 1\'b1; + #10; + + assign gnd = 1\'b0; + assign vdd = 1\'b1; + assign x = 1\'bx; + assign z = 1\'bz; + #10; + + failed = 0; + + if (t0 !== gnd) + begin + failed = 1; + $display (""FAILED: rpmos s:%d g:%d d:%d expected:0"", gnd, gnd, t0 ); + end + + if (t1 !== z) + begin + failed = 1; + $display (""FAILED: rpmos s:%d g:%d d:%d expected:z"", gnd, vdd, t1 ); + end + if (t2 !== StL) + begin + failed = 1; + $display (""FAILED: rpmos s:%d g:%d d:%d expected:StL"", gnd, x, t2 ); + end + if (t3 !== StL) + begin + failed = 1; + $display (""FAILED: rpmos s:%d g:%d d:%d expected:StL"", gnd, z, t3 ); + end + + if (t4 !== 1\'b1) + begin + failed = 1; + $display (""FAILED: rpmos s:%d g:%d d:%d expected:1"", vdd, gnd, t4 ); + end + if (t5 !== z) + begin + failed = 1; + $display (""FAILED: rpmos s:%d g:%d d:%d expected:z"", vdd, vdd, t5 ); + end + if (t6 !== StH) + begin + failed = 1; + $display (""FAILED: rpmos s:%d g:%d d:%d expected:StH"", vdd, x, t6 ); + end + if (t7 !== StH) + begin + failed = 1; + $display (""FAILED: rpmos s:%d g:%d d:%d expected:StH"", vdd, z, t7 ); + end + + if (t8 !== 1\'bx) + begin + failed = 1; + $display (""FAILED: rpmos s:%d g:%d d:%d expected:x"", x, gnd, t8 ); + end + if (t9 !== 1\'bz) + begin + failed = 1; + $display (""FAILED: rpmos s:%d g:%d d:%d expected:z"", x, vdd, t9 ); + end + if (ta !== 1\'bx) + begin + failed = 1; + $display (""FAILED: rpmos s:%d g:%d d:%d expected:x"", x, x, ta ); + end + if (tb !== 1\'bx) + begin + failed = 1; + $display (""FAILED: rpmos s:%d g:%d d:%d expected:x"", x, z, tb ); + end + + if (tc !== 1\'bz) + begin + failed = 1; + $display (""FAILED: rpmos s:%d g:%d d:%d expected:z"", z, gnd, tc ); + end + if (td !== 1\'bz) + begin + failed = 1; + $display (""FAILED: rpmos s:%d g:%d d:%d expected:z"", z, vdd, td ); + end + if (te !== 1\'bz) + begin + failed = 1; + $display (""FAILED: rpmos s:%d g:%d d:%d expected:z"", z, x, te ); + end + if (tf !== 1\'bz) + begin + failed = 1; + $display (""FAILED: rpmos s:%d g:%d d:%d expected:z"", z, z, tf ); + end + + if (failed == 0) + $display (""PASSED""); +end +endmodule +" +"// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test limited length strings in VHDL. + +module vhdl_string_lim_test; +logic start, res; +vhdl_string_lim dut(start, res); + +initial begin + #1; + + if(res !== 1\'b1) begin + $display(""FAILED""); + $finish(); + end + + $display(""PASSED""); +end +endmodule +" +"module main; + reg a, b, reset, pass; + + always @* + a = b | reset; + + always @* begin + b = 1\'b0; + #2; + b = a; + end + + initial begin + pass = 1\'b1; + reset = 1\'b1; + #1 if(b !== 1\'b0) begin + $display(""FAILED initial zero for 1\'b1, got %b"", b); + pass = 1\'b0; + end + #2 if(b !== 1\'b1) begin + $display(""FAILED initial set to 1\'b1, got %b"", b); + pass = 1\'b0; + end + + // Since b is already 1\'b1 reset can not change a to zero. + reset = 1\'b0; + #1 if(b !== 1\'b1) begin + $display(""FAILED block of initial zero for 1\'b0, got %b"", b); + pass = 1\'b0; + end + #2 if(b !== 1\'b1) begin + $display(""FAILED block of initial set to 1\'b0, got %b"", b); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end + +endmodule +" +"module top; + reg passed; + reg [4:1] result; + + initial begin + passed = 1\'b1; + result = 4\'b0000; + // Fork some processes and wait for the one with the least delay to finish. + fork + #3 result[3] = 1\'b1; + #4 result[4] = 1\'b1; + join_none + fork + #1 result[1] = 1\'b1; + #2 result[2] = 1\'b1; + join_any + // Disable the rest of the forked processes. + disable fork; + // Only the 1st bit should be set. + if (result !== 4\'b0001) begin + $display(""More than one process ran before the disable fork: %b"", result); + passed = 1\'b0; + result = 4\'b0001; + end + // Wait to make sure the disabled processes do not run at a later time. + #10; + // Only the 1st bit should still be set. + if (result !== 4\'b0001) begin + $display(""Processes ran to completion after being disabled: %b"", result); + passed = 1\'b0; + end + + if (passed) $display(""PASSED""); + end +endmodule +" +"`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +// Test array variables inside a constant function +module constfunc14(); + +function [7:0] concat1(input [7:0] value); + +reg [3:0] tmp[1:2]; + +begin + {tmp[1], tmp[2]} = {value[3:0], value[7:4]}; + {concat1[3:0], concat1[7:4]} = {tmp[2], tmp[1]}; +end + +endfunction + +function [7:0] concat2(input [7:0] value); + +reg [3:0] tmp[1:2]; + +begin +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + {tmp[1], tmp[3]} = {value[3:0], value[7:4]}; + {concat2[3:0], concat2[7:4]} = {tmp[3], tmp[1]}; +`else + {tmp[1]} = {value[3:0]}; + {concat2[3:0], concat2[7:4]} = {4\'bxxxx, tmp[1]}; +`endif +end + +endfunction + +function [7:0] concat3(input [7:0] value); + +reg [3:0] tmp[1:2]; + +begin +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + {tmp[\'bx], tmp[1]} = {value[3:0], value[7:4]}; + {concat3[3:0], concat3[7:4]} = {tmp[\'bx], tmp[1]}; +`else + {tmp[1]} = {value[7:4]}; + {concat3[3:0], concat3[7:4]} = {4\'bxxxx, tmp[1]}; +`endif +end + +endfunction + +localparam res1 = concat1(8\'ha5); +localparam res2 = concat2(8\'ha5); +localparam res3 = concat2(8\'ha5); + +reg failed = 0; + +initial begin + $display(""%h"", res1); if (res1 !== 8\'h5a) failed = 1; + $display(""%h"", res2); if (res2 !== 8\'h5x) failed = 1; + $display(""%h"", res3); if (res3 !== 8\'h5x) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module cb(); + +always begin + #1; +end + +endmodule +" +"// Trigger breakage of Icarus Verilog CVS 2004-06-18 +// $ iverilog netnet.v +// netnet.v:7: internal error: pin(3) out of bounds(3) +// netnet.v:7: : typeid=6NetNet +// ivl: netlist.cc:208: Link &NetObj::pin (unsigned int): Assertion `idx < npins_\' failed. +// $ +// Larry Doolittle + +`timescale 1ns / 1ns + +module netnet(); + +reg [2:0] s; +wire s_ones; +assign s_ones = (s==7); + +initial begin + s = 3\'b111; + + #1 if (s_ones !== 1) begin + $display(""FAILED -- %b==7 returns %b"", s, s_ones); + $finish; + end + s = 3\'b011; + + #1 if (s_ones !== 0) begin + $display(""FAILED -- %b==7 returns %b"", s, s_ones); + $finish; + end + + $display(""PASSED""); +end +endmodule +" +"module main; + + reg [31:0] a, b, c; + + initial begin + a = 1; + b = 1; + b[2] = 1\'bx; + c = a << b; + //$display( ""a: %b, b: %b, c: %b"", a, b, c ); + if (c != 32\'bx) $display(""FAILED""); + else $display(""PASSED""); + end +endmodule +" +"module top; + wire [2:-1] vec; + integer idx; + + initial begin + idx = 'bx; + force vec[idx+:1] = 1'b1; + release vec[idx+:1]; + end +endmodule +" +"module top; + parameter parm = 1.4; + reg [31:0] str; + + initial begin + $sformat(str, ""R: %d"", parm); + if (str !== "" 1"") $display(""FAILED: expected \' 1\', got %s"", str); + else $display(""PASSED""); + end +endmodule +" +"// Test concatenation inside a constant function +module constfunc14(); + +function [7:0] concat1(input [7:0] value); + +reg [3:0] tmp1; +reg [3:0] tmp2; + +begin + {tmp1, tmp2} = {value[3:0], value[7:4]}; + {concat1[3:0], concat1[7:4]} = {tmp2, tmp1}; +end + +endfunction + +function [7:0] concat2(input [7:0] value); + +reg [2:0] tmp1; +reg [3:0] tmp2; + +begin + {tmp1, tmp2} = {value[3:0], value[7:4]}; + {concat2[3:0], concat2[7:4]} = {tmp2, tmp1}; +end + +endfunction + +function [7:0] concat3(input [7:0] value); + +reg signed [2:0] tmp1; +reg signed [2:0] tmp2; + +begin + {tmp1, tmp2} = {value[2:0], value[6:4]}; + concat3[7:4] = tmp1; + concat3[3:0] = tmp2; +end + +endfunction + +localparam res1 = concat1(8\'h5a); +localparam res2 = concat2(8\'h5a); +localparam res3 = concat3(8\'h5a); + +reg failed = 0; + +initial begin + $display(""%h"", res1); if (res1 !== 8\'ha5) failed = 1; + $display(""%h"", res2); if (res2 !== 8\'ha2) failed = 1; + $display(""%h"", res3); if (res3 !== 8\'h2d) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"`timescale 1ns/10ps + +module top; + reg pass; + real result; + + initial begin + pass = 1\'b1; + + result = $abstime; + if (result != 0.0) begin + $display(""FAILED at time 0, expected 0.0, got %g"", result); + pass = 1\'b0; + end + + #10; + result = $abstime; + if ($abs(result-10e-9) > result*1e-9) begin + $display(""FAILED at time 10ns, expected 1e-8, got %g"", result); + pass = 1\'b0; + end + + #999990; + result = $abstime; + if ($abs(result-0.001) > result*1e-9) begin + $display(""FAILED at time 1ms, expected 0.001, got %g"", result); + pass = 1\'b0; + end + +`ifdef __ICARUS_UNSIZED__ + #9999000000; +`else + #9999000000.0; +`endif + result = $abstime; + if ($abs(result-10.0) > result*1e-9) begin + $display(""FAILED at time 10s, expected 10.0, got %g"", result); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module constfunc1(); + +function integer median; + +input integer a; +input integer b; +input integer c; + +begin + if (a < b) + begin + if (a < c) + median = (b < c) ? b : c; + else + median = a; + end + else + begin + if (a < c) + median = a; + else + median = (b < c) ? c : b; + end +end + +endfunction + +localparam value1 = median(1, 2, 3); +localparam value2 = median(1, 3, 2); +localparam value3 = median(2, 1, 3); +localparam value4 = median(2, 3, 1); +localparam value5 = median(3, 1, 2); +localparam value6 = median(3, 2, 1); + +initial begin + $display(""value 1 = %0d"", value1); + $display(""value 2 = %0d"", value2); + $display(""value 3 = %0d"", value3); + $display(""value 4 = %0d"", value4); + $display(""value 5 = %0d"", value5); + $display(""value 6 = %0d"", value6); + if ((value1 === 2) + && (value2 === 2) + && (value3 === 2) + && (value4 === 2) + && (value5 === 2) + && (value6 === 2)) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW - Memory array instantiation, validation +// +// D: First do the declaration, and assignment of bit wide arrays +// D: and 16 bit wide 4 deep arrays. Then assign values and validate +// D: the assignment worked. + +module main(); + +reg\t\tmem_1 [1:0];\t// Define 2 locations, each 1 bit in depth +reg [15:0]\tmem_2 [3:0];\t// Define a 16 bit wide array - 4 in depth +reg [15:0]\twork16; +reg\t\twork1; + +initial // Excitation block + begin +\tmem_1 [0] = 0;\t\t// Do the initial assignment of values +\tmem_1 [1] = 1; +\tmem_2 [0] = 16\'h0; +\tmem_2 [1] = 16\'h1; +\tmem_2 [2] = 16\'h2; +\tmem_2 [3] = 16\'h3; + + #5 ; + mem_1 [1] = mem_1 [0] ;\t// use the mem array on the rhs + mem_2 [3] = mem_2 [0] ; + + #5; + + end + +initial // Validation block + begin + #1 ; + // Validate initialization + work1 = mem_1[0]; + if(work1 != 0) + begin + $display(""FAILED - mem_1 [0] init failed\ +""); + $finish ; + end + work1 = mem_1[1]; + if(work1 != 1) + begin + $display(""FAILED - mem_1 [1] init failed\ +""); + $finish ; + end + work16 = mem_2 [0]; + if(work16 != 16\'h0) + begin + $display(""FAILED - mem_2 [0] init failed\ +""); + $finish ; + end + work16 = mem_2 [1]; + if(work16 != 16\'h1) + begin + $display(""FAILED - mem_2 [1] init failed\ +""); + $finish ; + end + work16 = mem_2 [2]; + if(work16 != 16\'h2) + begin + $display(""FAILED - mem_2 [2] init failed\ +""); + $finish ; + end + work16 = mem_2 [3]; + if(work16 != 16\'h3) + begin + $display(""FAILED - mem_2 [3] init failed\ +""); + $finish ; + end + + #5 ; + work1 = mem_1[1]; + if(work1 != 0) + begin + $display(""FAILED - mem_1 [1] rhs assignment \ +""); + $finish ; + end + work16 = mem_2 [3]; + if(work16 != 16\'h0) + begin + $display(""FAILED - mem_2 [3] rhs assignment\ +""); + $finish ; + end + + $display(""PASSED\ +""); + $finish ; + end + +endmodule +" +"module main; + + int foo; + + initial begin + foo = 1; + foo ++; + ++ foo; + if (foo !== 3) begin +\t $display(""FAILED -- foo=%0d"", foo); +\t $finish; + end + + foo --; + -- foo; + if (foo !== 1) begin +\t $display(""FAILED -- foo=%0d"", foo); +\t $finish; + end + + $display(""PASSED""); + $finish; + end // initial begin + +endmodule // main +" +"module event_array_test(); + +event my_event[3:0]; + +integer event_count[3:0]; + +generate + genvar i; + + for (i = 0; i < 4; i = i + 1) begin + always @(my_event[i]) begin + $display(""Got event %d"", i); + event_count[i] = event_count[i] + 1; + end + end +endgenerate + +initial begin + event_count[0] = 0; + event_count[1] = 0; + event_count[2] = 0; + event_count[3] = 0; + #1 ->my_event[0]; + #1 ->my_event[1]; + #1 ->my_event[2]; + #1 ->my_event[3]; + #1 ->my_event[1]; + #1 ->my_event[2]; + #1 ->my_event[3]; + #1 ->my_event[2]; + #1 ->my_event[3]; + #1 ->my_event[3]; + #1; + if ((event_count[0] === 1) + && (event_count[1] === 2) + && (event_count[2] === 3) + && (event_count[3] === 4)) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"/* + * Copyright (c) 1999-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This is derived from pr602. + */ + +module main; + + reg [1:0] a [3:0], x; + + integer i; + initial begin + a[0] = 0; + a[1] = 1; + a[2] = 2; + a[3] = 3; + + // The index expressions of this parameter expression + // should be evaluated to constants. + $display(""a[(1-1)+0] = %b"", a[(1-1)+0]); + $display(""a[(2-1)+0] = %b"", a[(2-1)+0]); + x = a[(1-1)+0]; + if (x !== 2\'b00) begin +\t $display(""FAILED -- x == %b"", x); +\t $finish; + end + + x = a[(2-1)+0]; + if (x !== 2\'b01) begin +\t $display(""FAILED -- x == %b"", x); +\t $finish; + end + + x <= a[(1-1)+0]; + #1 if (x !== 2\'b00) begin +\t $display(""FAILED -- x == %b"", x); +\t $finish; + end + + x <= a[(2-1)+0]; + #1 if (x !== 2\'b01) begin +\t $display(""FAILED -- x == %b"", x); +\t $finish; + end + + $display(""PASSED""); + end // initial begin +endmodule // main +" +"module top2; + real vo; + + initial begin + vo = 3.3; + #1000 vo = 4.5776; + #1000 vo = -4; + end + + always @(vo) + $display(""Real value is %f at %g"", vo, $time); +endmodule +" +" +module addN + #(parameter WID = 4) + (input wire [WID-1:0] A, + input wire [WID-1:0] B, + output reg [WID:0] Q + /* */); + + always @* Q = A + B; + +endmodule // add +" +"module tb; + +reg [1:0] i, j; +reg [3:0] x; +reg error; + +initial begin + error = 0; + + i = 0; + j = i++; + if (i !== 2\'b01 || j !== 2\'b00) begin + $display(""FAILED j = i++ --> j=%b, i=%b"", j, i); + error = 1; + end + + i = 0; + x[0] = 1\'bx; + x[1] = 1\'bx; + x[0] = 1\'b0; + if (x[0] !== 1\'b0 || x[1] !== 1\'bx) begin + $display(""FAILED x[i++] = 0 --> x[0]=%b, x[1]=%b, i=%b"", x[0], x[1], i); + error = 1; + end + + i = 0; + x[0] = 1\'b1; + x[0] += 1\'b1; + if (x[0] !== 1\'b0) begin + $display(""FAILED x[0] should be 0, but it is %b."", x[0]); + error = 1; + end + if (i !== 2\'d0) begin + $display(""FAILED i should be 1, but it is %d."", i); + error = 1; + end + if (error == 0) + $display(""PASSED""); +end +endmodule // tb +" +"module top; + reg [31:0] in_32, ck_32, out_32, out_32x; + reg [63:0] out_64; + integer res, fd; + reg passed; + + initial begin + passed = 1\'b1; + + // Check that a normal 32 bit %u catches missing bytes. + fd = $fopen(""work/test_fscanf.bin"", ""wb""); + in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, ""%c%c"", in_32[15:8], in_32[7:0]); + $fclose(fd); + fd = $fopen(""work/test_fscanf.bin"", ""rb""); + res = $fscanf(fd, ""%u"", out_32); + if (res !== -1) begin + $display(""FAILED: $fscanf() #1 returned %d (%b)"", res, out_32); + passed = 1\'b0; + end + $fclose(fd); + + // Check that a normal 64 bit %u catches missing bytes (1/4). + fd = $fopen(""work/test_fscanf.bin"", ""wb""); + in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, ""%c%c"", in_32[15:8], in_32[7:0]); + $fclose(fd); + fd = $fopen(""work/test_fscanf.bin"", ""rb""); + res = $fscanf(fd, ""%u"", out_64); + if (res !== -1) begin + $display(""FAILED: $fscanf() #2a returned %d (%b)"", res, out_64); + passed = 1\'b0; + end + $fclose(fd); + + // Check that a normal 64 bit %u catches missing bytes (1/2). + fd = $fopen(""work/test_fscanf.bin"", ""wb""); + in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, ""%u"", in_32); + $fclose(fd); + fd = $fopen(""work/test_fscanf.bin"", ""rb""); + res = $fscanf(fd, ""%u"", out_64); + if (res !== -1) begin + $display(""FAILED: $fscanf() #2b returned %d (%b)"", res, out_64); + passed = 1\'b0; + end + $fclose(fd); + + // Check that a normal 64 bit %u catches missing bytes (3/4). + fd = $fopen(""work/test_fscanf.bin"", ""wb""); + in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, ""%u%c%c"", in_32, in_32[15:8], in_32[7:0]); + $fclose(fd); + fd = $fopen(""work/test_fscanf.bin"", ""rb""); + res = $fscanf(fd, ""%u"", out_64); + if (res !== -1) begin + $display(""FAILED: $fscanf() #2c returned %d (%b)"", res, out_64); + passed = 1\'b0; + end + $fclose(fd); + + // Check that a normal 32 bit %u suppression catches missing bytes. + fd = $fopen(""work/test_fscanf.bin"", ""wb""); + in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, ""%c%c"", in_32[15:8], in_32[7:0]); + $fclose(fd); + fd = $fopen(""work/test_fscanf.bin"", ""rb""); + res = $fscanf(fd, ""%*u"", out_32); + if (res !== -1) begin + $display(""FAILED: $fscanf() #3 returned %d (%b)"", res, out_32); + passed = 1\'b0; + end + $fclose(fd); + + // Check that a multiple read %u catches missing bytes (1/2). + fd = $fopen(""work/test_fscanf.bin"", ""wb""); + in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32\'b00001000_00100000_10100000_10001110; + $fwrite(fd, ""%u%c%c"", in_32, in_32[15:8], in_32[7:0]); + $fclose(fd); + fd = $fopen(""work/test_fscanf.bin"", ""rb""); + res = $fscanf(fd, ""%u%u"", out_32, out_32x); + if (res !== 1) begin + $display(""FAILED: $fscanf() #4 returned %d (%b)"", res, out_32x); + passed = 1\'b0; + end else begin + if (ck_32 !== out_32) begin + $display(""FAILED: $fscanf() #4 %b !== %b"", ck_32, out_32); + passed = 1\'b0; + end + if (out_32x !== 32\'bx) begin + $display(""FAILED: $fscanf() #4 %b !== 32\'bx"", out_32x); + passed = 1\'b0; + end + end + res = $fscanf(fd, ""%u"", out_32); + if (res !== -1) begin + $display(""FAILED: $fscanf() #4 EOF returned %d (%b)"", res, out_32); + passed = 1\'b0; + end + $fclose(fd); + + // Check that a suppression/read %u catches missing bytes (1/2). + fd = $fopen(""work/test_fscanf.bin"", ""wb""); + in_32 = 32\'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, ""%u%c%c"", in_32, in_32[15:8], in_32[7:0]); + $fclose(fd); + fd = $fopen(""work/test_fscanf.bin"", ""rb""); + out_32 = 32\'bx; + res = $fscanf(fd, ""%*u%u"", out_32); + if (res !== -1) begin + $display(""FAILED: $fscanf() #5 returned %d (%b)"", res, out_32); + passed = 1\'b0; + end else if (out_32 !== 32\'bx) begin + $display(""FAILED: $fscanf() #5 %b !== 32\'bx"", out_32); + passed = 1\'b0; + end + $fclose(fd); + + if (passed) $display(""PASSED""); + end +endmodule +" +"module top; + integer chr, fd, code; + reg [14*8:1] str; + + initial begin + // Put a string into the file. + fd = $fopen(""work/test.txt"", ""w""); + if (fd == 0) begin + $display(""Failed to open test file for writing!""); + $finish; + end + $fdisplay(fd, ""Hello World!""); + $fclose(fd); + + // Now read it back and verify that $ungetc() and other things work. + fd = $fopen(""work/test.txt"", ""r""); + if (fd == 0) begin + $display(""Failed to open test file for reading!""); + $finish; + end + + chr = $fgetc(fd); + if (chr != ""H"") begin + $display(""Failed first character read!""); + $finish; + end + + code = $ungetc(chr, fd); + if (code == -1) begin + $display(""Failed to ungetc() character!""); + $finish; + end + + chr = $fgetc(fd); + if (chr != ""H"") begin + $display(""Failed first character reread!""); + $finish; + end + + code = $ungetc(chr, fd); + if (code == -1) begin + $display(""Failed to ungetc() character (2)!""); + $finish; + end + + code = $fgets(str, fd); + if (code == 0) begin + $display(""Failed to read characters!""); + $finish; + end + if (str[13*8:9] != ""Hello World!"") begin + $display(""Read wrong characters!""); + $finish; + end + + $fclose(fd); + + $display(""PASSED""); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate XOR gate vector +// + + +module main; + +reg globvar; + +wire [15:0] out; +reg [15:0] a,b, rslt; +reg error; + +// The test gate goes HERE! + +xor foo [15:0] (out,a,b); + +// This is the computed value used to determine if the gate is sane. +always @(a or b) + rslt = a ^ b; + +initial + begin // { + error = 0; + # 1; + for(a = 16\'h1; a != 16\'hffff; a = (a << 1) | 1) + begin // { + for(b = 16\'hffff; b !== 16\'h0; b = b >> 1) + begin // { + #1 ; + if(out !== rslt) + begin // { + $display(""FAILED - GA XOR a=%h,b=%h,expct=%h - rcvd=%h"", + a,b,rslt,out); + error = 1; + end // } + end // } + end // } + if( error == 0) + $display(""PASSED""); + end // } +endmodule // main +" +"module top; + parameter ab = 8; + parameter ch = 2; + + reg [63:0] r; + + initial begin + r[0+:ab * ch] = 2; + if (r !== 64\'hxxxxxxxxxxxx0002) $display(""Failed, got %h"", r); + else $display(""PASSED""); + end +endmodule +" +"`begin_keywords ""1364-2005"" +// +// Copyright (c) 1999 Thomas Coonan (tcoonan@mindspring.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// Synchronous FIFO. 4 x 16 bit words. +// +// Modified by SDW to print out PASSED only if DEBUG not defined. +// Also changed TEST1 so that it is ""self checking"" by adding a +// passed in value to read_word. +// +module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp); +input\t\tclk; +input\t\trstp; +input [15:0]\tdin; +input\t\treadp; +input\t\twritep; +output [15:0]\tdout; +output\t\temptyp; +output\t\tfullp; + +// Defines sizes in terms of bits. +// +parameter\tDEPTH = 3,\t\t// 2 bits, e.g. 4 words in the FIFO. +\t\tMAX_COUNT = 3\'b111;\t// topmost address in FIFO. + +reg\t\temptyp; +reg\t\tfullp; + +// Registered output. +reg [15:0]\tdout; + +// Define the FIFO pointers. A FIFO is essentially a circular queue. +// +reg [(DEPTH-1):0]\ttail; +reg [(DEPTH-1):0]\thead; + +// Define the FIFO counter. Counts the number of entries in the FIFO which +// is how we figure out things like Empty and Full. +// +reg [(DEPTH-1):0]\tcount; + +// Define our regsiter bank. This is actually synthesizable! +// +reg [15:0] fifomem[0:MAX_COUNT]; + +// Dout is registered and gets the value that tail points to RIGHT NOW. +// +always @(posedge clk) + begin + if (rstp == 1) + dout <= 16\'h0000; + else + dout <= fifomem[tail]; + end + + +// Update FIFO memory. +always @(posedge clk) begin + if (rstp == 1\'b0 && writep == 1\'b1 && fullp == 1\'b0) begin + fifomem[head] <= din; + end +end + +// Update the head register. +// +always @(posedge clk) begin + if (rstp == 1\'b1) begin + head <= 2\'b00; + end + else begin + if (writep == 1\'b1 && fullp == 1\'b0) begin + // WRITE + head <= head + 1; + end + end +end + +// Update the tail register. +// +always @(posedge clk) begin + if (rstp == 1\'b1) begin + tail <= 2\'b00; + end + else begin + if (readp == 1\'b1 && emptyp == 1\'b0) begin + // READ + tail <= tail + 1; + end + end +end + +// Update the count regsiter. +// +always @(posedge clk) begin + if (rstp == 1\'b1) begin + count <= 2\'b00; + end + else begin + case ({readp, writep}) + 2\'b00: count <= count; + 2\'b01: + // WRITE + if (count != MAX_COUNT) + count <= count + 1; + 2\'b10: + // READ + if (count != 2\'b00) + count <= count - 1; + 2\'b11: + // Concurrent read and write.. no change in count + count <= count; + endcase + end +end + + +// *** Update the flags +// +// First, update the empty flag. +// +always @(count) begin + if (count == 2\'b00) + emptyp <= 1\'b1; + else + emptyp <= 1\'b0; +end + + +// Update the full flag +// +always @(count) begin + if (count == MAX_COUNT) + fullp <= 1\'b1; + else + fullp <= 1\'b0; +end + +endmodule + +// synopsys translate_off + +`define TEST_FIFO +// synopsys translate_off +`ifdef TEST_FIFO + + +module test_fifo; + +reg\t\tclk; +reg\t\trstp; +reg [15:0]\tdin; +reg\t\treadp; +reg\t\twritep; +wire [15:0]\tdout; +wire\t\temptyp; +wire\t\tfullp; +reg\t\terror ; + +reg [15:0]\tvalue; + +fifo U1 ( + .clk\t\t(clk), + .rstp\t(rstp), + .din\t\t(din), + .readp\t(readp), + .writep\t(writep), + .dout\t(dout), + .emptyp\t(emptyp), + .fullp\t(fullp) +); + +// +// SDW Added self testing aspect here.. +// +task read_word; +input [15:0] expect; +begin + @(negedge clk); + readp = 1; + @(posedge clk) #5; +`ifdef DEBUG + $display (""Expect %0h, Read %0h from FIFO"", +`endif // DEBUG + if(expect !== dout) + begin + $display (""FAILED - Expect %0h, Read %0h from FIFO"", + expect,dout); + error = 1; + end + readp = 0; +end +endtask + +task write_word; +input [15:0]\tvalue; +begin + @(negedge clk); + din = value; + writep = 1; + @(posedge clk); +`ifdef DEBUG + $display (""Write %0h to FIFO"", din); +`endif // DEBUG + #5; + din = 16\'hzzzz; + writep = 0; +end +endtask + +initial begin + clk = 0; + forever begin + #10 clk = 1; + #10 clk = 0; + end +end + +initial begin + error = 0;\t// Set error to zero here. +`ifdef DEBUG + $dumpfile(""test.vcd""); + $dumpvars(0,test_fifo); +`endif // DEBUG + test1; + //test2; + + if(error == 0) + $display(""PASSED""); + $finish; +end + +task test1; +begin + din = 16\'hzzzz; + writep = 0; + readp = 0; + + // Reset + rstp = 1; + #50; + rstp = 0; + #50; + + // ** Write 3 values. + write_word (16\'h1111); + write_word (16\'h2222); + write_word (16\'h3333); + + // ** Read 2 values + read_word(16\'h1111); + read_word(16\'h2222); + + // ** Write one more + write_word (16\'h4444); + + // ** Read a bunch of values + read_word(16\'h3333); + + // *** Write a bunch more values + write_word (16\'h0001); + write_word (16\'h0002); + write_word (16\'h0003); + write_word (16\'h0004); + write_word (16\'h0005); + write_word (16\'h0006); + write_word (16\'h0007); + write_word (16\'h0008); + + // ** Read a bunch of values + read_word(16\'h4444); + read_word(16\'h0001); + read_word(16\'h0002); + read_word(16\'h0003); + read_word(16\'h0004); + read_word(16\'h0005); + read_word(16\'h0006); +end +endtask +`ifdef TEST2 +// TEST2 +// +// This test will operate the FIFO in an orderly manner the way it normally works. +// 2 threads are forked; a reader and a writer. The writer writes a counter to +// the FIFO and obeys the fullp flag and delays randomly. The reader likewise +// obeys the emptyp flag and reads at random intervals. The result should be that +// the reader reads the incrementing counter out of the FIFO. The empty/full flags +// should bounce around depending on the random delays. The writer repeats some +// fixed number of times and then terminates both threads and kills the sim. +// +task test2; +reg [15:0] writer_counter; +begin + writer_counter = 16\'h0001; + din = 16\'hzzzz; + writep = 0; + readp = 0; + + // Reset + rstp = 1; + #50; + rstp = 0; + #50; + + fork + // Writer + begin + repeat (500) begin + @(negedge clk); + if (fullp == 1\'b0) begin + write_word (writer_counter); + #5; + writer_counter = writer_counter + 1; + end + else begin + $display (""WRITER is waiting..""); + end + // Delay a random amount of time between 0ns and 100ns + #22 ; + end + $display (""Done with WRITER fork..""); + $finish; + end + + // Reader + begin + forever begin + @(negedge clk); + if (emptyp == 1\'b0) begin + read_word; + end + else begin + $display (""READER is waiting..""); + end + // Delay a random amount of time between 0ns and 100ns + #50; + end + end + join +end +endtask + +/* +always @(fullp) + $display (""fullp = %0b"", fullp); + +always @(emptyp) + $display (""emptyp = %0b"", emptyp); + +always @(U1.head) + $display (""head = %0h"", U1.head); + +always @(U1.tail) + $display (""tail = %0h"", U1.tail); +*/ + +`endif // TEST2 + +endmodule +`endif +`end_keywords +" +"// Three basic tests in here: +// 1. byte must be initialised before any initial or always block +// 2. assignments to (unsigned) bytes with random numbers +// 3. assignments to (unsigned) bytes with random values including X and Z + + +module ibyte_test; + parameter TRIALS = 100; + parameter MAX = \'h7fffffff_ffffffff; + reg [63:0] ar; // should it be ""reg unsigned [7:0] aw""? + reg [63:0] ar_xz; // same as above here? + reg [63:0] ar_expected; // and here + longint unsigned bu; + longint unsigned bu_xz; + + integer i; + + assign bu = ar; + assign bu_xz = ar_xz; + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if (bu !== 64\'b0 | bu_xz != 64\'b0) + begin + $display (""FAILED - time zero initialisation incorrect: %b %b"", bu, bu_xz); + $finish; + end + // random numbers + for (i = 0; i< TRIALS; i = i+1) + begin + #1; + ar = {$random} % MAX; + #1; + if (bu !== ar) + begin + $display (""FAILED - incorrect assigment to byte: %b"", bu); + $finish; + end + end + # 1; + // with \'x injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< TRIALS; i = i+1) + begin + #1; + ar = {$random} % MAX; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0 + begin + $display (""FAILED - incorrect assigment to byte (when \'x): %b"", bu); + $finish; + end + end + # 1; + $display(""PASSED""); + end + + // this returns X and Z states into bit random positions for a value + function [63:0] xz_inject (input [63:0] value); // should it be ""input unsigned [7:0]"" instead? + integer i, temp; + begin + temp = {$random} % MAX; + for (i=0; i<64; i=i+1) + begin + if (temp[i] == 1\'b1) + begin + temp = $random % MAX; + if (temp <= 0) + value[i] = 1\'bx; // \'x noise + else + value[i] = 1\'bz; // \'z noise + end + end + xz_inject = value; + end + endfunction + + // this function returns bit positions with either X or Z to 0 for an input value + function [63:0] xz_expected (input [63:0] value_xz); // should it be ""input unsigned [7:0] instead? + integer i; + begin + for (i=0; i<64; i=i+1) + begin + if (value_xz[i] === 1\'bx || value_xz[i] === 1\'bz ) + value_xz[i] = 1\'b0; // forced to zero + end + xz_expected = value_xz; + end + endfunction + + +endmodule +" +"module top; + reg [8*80-1:0] str; + integer fd, pos, result; + + initial begin + fd = $fopen(""ivltests/pr1819452.txt"",""rb""); + result = $fgets(str, fd); + while (!$feof(fd)) begin + pos = $ftell(fd); + $display(""Found: %5s currently at byte %0d"", str[8*10-1:8], pos); + result = $fgets(str, fd); + end + + result = $rewind(fd); + result = $fgets(str, fd); + pos = $ftell(fd); + $display(""Found: %5s currently at byte %0d"", str[8*10-1:8], pos); + + result = $fseek(fd, 0, 0); + result = $fgets(str, fd); + pos = $ftell(fd); + $display(""Found: %5s currently at byte %0d"", str[8*10-1:8], pos); + + result = $fseek(fd, -3, 2); + result = $fgets(str, fd); + pos = $ftell(fd); + $display(""Found: %5s currently at byte %0d"", str[8*10-1:8], pos); + + result = $fseek(fd, -6, 1); + result = $fgets(str, fd); + pos = $ftell(fd); + $display(""Found: %5s currently at byte %0d"", str[8*10-1:8], pos); + + result = $fseek(32\'hffffffff, 0, 0); + $display(""Check fseek EOF = %0d"", result); + + result = $ftell(32\'hffffffff); + $display(""Check ftell EOF = %0d"", result); + + result = $rewind(32\'hffffffff); + $display(""Check rewind EOF = %0d"", result); + + $fclose(fd); + end +endmodule +" +"module mixed_width_case(); + +function [2:0] lookup1(input signed [2:0] value); + +begin + case (value) + 4\'sb0100 : lookup1 = 1; + 3\'sb100 : lookup1 = 2; + 2\'sb10 : lookup1 = 3; + default : lookup1 = 4; + endcase + $display(""case = %d"", lookup1); +end + +endfunction + +function [2:0] lookup2(input signed [2:0] value); + +begin + case (value) + 4\'b1100 : lookup2 = 1; + 3\'sb100 : lookup2 = 2; + 2\'sb10 : lookup2 = 3; + default : lookup2 = 4; + endcase + $display(""case = %d"", lookup2); +end + +endfunction + +function [2:0] lookup3(input real value); + +begin + case (value) + 4\'b0001 : lookup3 = 1; + 3\'sb010 : lookup3 = 2; + 2\'sb11 : lookup3 = 3; + default : lookup3 = 4; + endcase + $display(""case = %d"", lookup3); +end + +endfunction + +function [2:0] lookup4(input signed [2:0] value); + +begin + case (value) + 4\'b0110 : lookup4 = 1; + 3\'sb110 : lookup4 = 2; + -1.0 : lookup4 = 3; + default : lookup4 = 4; + endcase + $display(""case = %d"", lookup4); +end + +endfunction + +reg [2:0] result; + +reg failed = 0; + +initial begin + result = lookup1(3\'sb100); if ( result != 2) failed = 1; + result = lookup1(3\'sb110); if ( result != 3) failed = 1; + result = lookup1(3\'sb010); if ( result != 4) failed = 1; + $display(""""); + result = lookup2(3\'sb100); if ( result != 2) failed = 1; + result = lookup2(3\'sb010); if ( result != 3) failed = 1; + result = lookup2(3\'sb110); if ( result != 4) failed = 1; + $display(""""); + result = lookup3( 1.0); if ( result != 1) failed = 1; + result = lookup3( 2.0); if ( result != 2) failed = 1; + result = lookup3(-1.0); if ( result != 3) failed = 1; + result = lookup3( 1.5); if ( result != 4) failed = 1; + $display(""""); + result = lookup4(3\'sb110); if ( result != 2) failed = 1; + result = lookup4(3\'sb111); if ( result != 3) failed = 1; + result = lookup4(3\'sb011); if ( result != 4) failed = 1; + $display(""""); + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module bug(); + +reg [64:0] d; +reg [31:0] x; +reg [31:0] y; +reg [31:0] z; + +initial begin + d = 65\'h1_0000_0000_0000_0000; + x = 32\'hffffffff << d; + y = 32\'hffffffff >> d; + z = 32\'hffffffff >>> d; + $display(""%h"", x); + $display(""%h"", y); + $display(""%h"", z); + if (x === 32\'d0 && y === 32\'d0 && z === 32\'d0) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * SDW: Verify addition in a param declaration + */ +module test; + +parameter A0 = 4\'b0011 + 4\'b0001 ; + +initial + begin + if(A0 !== 4\'b0100) + $display(""FAILED - Addition in a param declaration.""); + else + $display(""PASSED""); + end + +endmodule +" +"module top; + parameter pnani = $sqrt(-1); + parameter pnanr = $sqrt(-1.0); + parameter p0i = $sqrt(0); + parameter p0r = $sqrt(0.0); + parameter p2i = $sqrt(4); + parameter p2r = $sqrt(4.0); + parameter pln = $ln(1); + parameter plog10 = $log10(10); + parameter pexp = $exp(0); + parameter pfloor = $floor(1.5); + parameter pceil = $ceil(1.5); + parameter psin = $sin(0); + parameter pcos = $cos(0); + parameter ptan = $tan(0); + parameter pasin = $asin(0); + parameter pacos = $acos(1); + parameter patan = $atan(0); + parameter psinh = $sinh(0); + parameter pcosh = $cosh(0); + parameter ptanh = $tanh(0); + parameter pasinh = $asinh(0); + parameter pacosh = $acosh(1); + parameter patanh = $atanh(0); + parameter ppow = $pow(-2, 2); + parameter patan2 = $atan2(0, 0); + parameter phypot = $hypot(-1, 0); + + reg [$sqrt(16)-1:0] reg4 = \'b0; + + reg pass = 1\'b1; + + real result, rin; + + wire [7:0] out = $sqrt(rin); + wire real rout = $sqrt(rin); + + initial begin + + /* Test the elab_pexpr implementation. */ + + if ($bits(reg4) !== 4) begin + $display(""Failed register size, expected 4, got %d"", $bits(reg4)); + pass = 1\'b0; + end + + if (!(pnani != pnani)) begin + $display(""Failed with param. NaN (int), expected NaN, got %f"", pnani); + pass = 1\'b0; + end + if (!(pnanr != pnanr)) begin + $display(""Failed with param. NaN (real), expected NaN, got %f"", pnanr); + pass = 1\'b0; + end + if (p0i != 0.0) begin + $display(""Failed with param. 0, expected 0.0, got %f"", p0i); + pass = 1\'b0; + end + if (p0r != 0.0) begin + $display(""Failed with param. 0.0, expected 0.0, got %f"", p0r); + pass = 1\'b0; + end + if (p2i != 2.0) begin + $display(""Failed with param. 4, expected 2.0, got %f"", p2i); + pass = 1\'b0; + end + if (p2r != 2.0) begin + $display(""Failed with param. 4.0, expected 2.0, got %f"", p2r); + pass = 1\'b0; + end + + if (pln != 0.0) begin + $display(""Failed with param. $ln, expected 0.0, got %f"", pln); + pass = 1\'b0; + end + if (plog10 != 1.0) begin + $display(""Failed with param. $log10, expected 1.0, got %f"", plog10); + pass = 1\'b0; + end + if (pexp != 1.0) begin + $display(""Failed with param. $exp, expected 1.0, got %f"", pexp); + pass = 1\'b0; + end + + if (pfloor != 1.0) begin + $display(""Failed with param. $floor, expected 1.0, got %f"", pfloor); + pass = 1\'b0; + end + if (pceil != 2.0) begin + $display(""Failed with param. $ceil, expected 2.0, got %f"", pceil); + pass = 1\'b0; + end + + if (psin != 0.0) begin + $display(""Failed with param. $sin, expected 0.0, got %f"", psin); + pass = 1\'b0; + end + if (pcos != 1.0) begin + $display(""Failed with param. $cos, expected 1.0, got %f"", pcos); + pass = 1\'b0; + end + if (ptan != 0.0) begin + $display(""Failed with param. $tan, expected 0.0, got %f"", ptan); + pass = 1\'b0; + end + if (pasin != 0.0) begin + $display(""Failed with param. $asin, expected 0.0, got %f"", pasin); + pass = 1\'b0; + end + if (pacos != 0.0) begin + $display(""Failed with param. $acos, expected 0.0, got %f"", pacos); + pass = 1\'b0; + end + if (patan != 0.0) begin + $display(""Failed with param. $atan, expected 0.0, got %f"", patan); + pass = 1\'b0; + end + + if (psinh != 0.0) begin + $display(""Failed with param. $sinh, expected 0.0, got %f"", psinh); + pass = 1\'b0; + end + if (pcosh != 1.0) begin + $display(""Failed with param. $cosh, expected 1.0, got %f"", pcosh); + pass = 1\'b0; + end + if (ptanh != 0.0) begin + $display(""Failed with param. $tanh, expected 0.0, got %f"", ptanh); + pass = 1\'b0; + end + if (pasinh != 0.0) begin + $display(""Failed with param. $asinh, expected 0.0, got %f"", pasinh); + pass = 1\'b0; + end + if (pacosh != 0.0) begin + $display(""Failed with param. $acosh, expected 0.0, got %f"", pacosh); + pass = 1\'b0; + end + if (patanh != 0.0) begin + $display(""Failed with param. $atanh, expected 0.0, got %f"", patanh); + pass = 1\'b0; + end + + if (ppow != 4.0) begin + $display(""Failed with param. $pow, expected 4.0, got %f"", ppow); + pass = 1\'b0; + end + if (patan2 != 0.0) begin + $display(""Failed with param. $atan2, expected 4.0, got %f"", patan2); + pass = 1\'b0; + end + if (phypot != 1.0) begin + $display(""Failed with param. $hypot, expected 1.0, got %f"", phypot); + pass = 1\'b0; + end + + /* Test the eval_tree implementation. */ + + result = $sqrt(0); + if (result != 0.0) begin + $display(""Failed with 0, expected 0.0, got %f"", result); + pass = 1\'b0; + end + result = $sqrt(0.0); + if (result != 0.0) begin + $display(""Failed with 0.0, expected 0.0, got %f"", result); + pass = 1\'b0; + end + + result = $sqrt(4); + if (result != 2.0) begin + $display(""Failed with 4, expected 2.0, got %f"", result); + pass = 1\'b0; + end + result = $sqrt(4.0); + if (result != 2.0) begin + $display(""Failed with 4.0, expected 2.0, got %f"", result); + pass = 1\'b0; + end + + result = $ln(1); + if (result != 0.0) begin + $display(""Failed with $ln, expected 0.0, got %f"", result); + pass = 1\'b0; + end + result = $log10(10); + if (result != 1.0) begin + $display(""Failed with $log10, expected 1.0, got %f"", result); + pass = 1\'b0; + end + result = $exp(0); + if (result != 1.0) begin + $display(""Failed with $exp, expected 1.0, got %f"", result); + pass = 1\'b0; + end + result = $floor(1.5); + if (result != 1.0) begin + $display(""Failed with $floor, expected 1.0, got %f"", result); + pass = 1\'b0; + end + result = $ceil(1.5); + if (result != 2.0) begin + $display(""Failed with $ceil, expected 2.0, got %f"", result); + pass = 1\'b0; + end + + result = $sin(0); + if (result != 0.0) begin + $display(""Failed with $sin, expected 0.0, got %f"", result); + pass = 1\'b0; + end + result = $cos(0); + if (result != 1.0) begin + $display(""Failed with $cos, expected 1.0, got %f"", result); + pass = 1\'b0; + end + result = $tan(0); + if (result != 0.0) begin + $display(""Failed with $tan, expected 0.0, got %f"", result); + pass = 1\'b0; + end + result = $asin(0); + if (result != 0.0) begin + $display(""Failed with $asin, expected 0.0, got %f"", result); + pass = 1\'b0; + end + result = $acos(1); + if (result != 0.0) begin + $display(""Failed with $acos, expected 0.0, got %f"", result); + pass = 1\'b0; + end + result = $atan(0); + if (result != 0.0) begin + $display(""Failed with $atan, expected 0.0, got %f"", result); + pass = 1\'b0; + end + + result = $sinh(0); + if (result != 0.0) begin + $display(""Failed with $sinh, expected 0.0, got %f"", result); + pass = 1\'b0; + end + result = $cosh(0); + if (result != 1.0) begin + $display(""Failed with $cosh, expected 1.0, got %f"", result); + pass = 1\'b0; + end + result = $tanh(0); + if (result != 0.0) begin + $display(""Failed with $tanh, expected 0.0, got %f"", result); + pass = 1\'b0; + end + result = $asinh(0); + if (result != 0.0) begin + $display(""Failed with $asinh, expected 0.0, got %f"", result); + pass = 1\'b0; + end + result = $acosh(1); + if (result != 0.0) begin + $display(""Failed with $acosh, expected 0.0, got %f"", result); + pass = 1\'b0; + end + result = $atanh(0); + if (result != 0.0) begin + $display(""Failed with $atanh, expected 0.0, got %f"", result); + pass = 1\'b0; + end + + result = $pow(-2, 2); + if (result != 4.0) begin + $display(""Failed with $pow, expected 4.0, got %f"", result); + pass = 1\'b0; + end + result = $atan2(0, 0); + if (result != 0.0) begin + $display(""Failed with $atan2, expected 0.0, got %f"", result); + pass = 1\'b0; + end + result = $hypot(-1, 0); + if (result != 1.0) begin + $display(""Failed with $hypot, expected 1.0, got %f"", result); + pass = 1\'b0; + end + + /* Test the CA statements and the vpi implementation. */ + + rin = -1; + #1 if (out !== 8\'bx) begin + $display(""Failed CA (int) with -1.0, expected \'bx, got %d"", out); + pass = 1\'b0; + end + if (!(rout != rout)) begin + $display(""Failed CA (real) with -1.0, expected NaN, got %f"", rout); + pass = 1\'b0; + end + rin = 4.0; + #1 if (out !== 2) begin + $display(""Failed CA (int) with 4.0, expected 2, got %d"", out); + pass = 1\'b0; + end + if (rout != 2.0) begin + $display(""Failed CA (real) with 4.0, expected 2.0, got %f"", rout); + pass = 1\'b0; + end + + // Run time generated. + rin = -1.0; + result = $sqrt(rin); + if (!(result != result)) begin + $display(""Failed run time with -1.0, expected NaN got %f"", result); + pass = 1\'b0; + end + + rin = 1.0; + result = $ln(rin); + if (result != 0.0) begin + $display(""Failed run time $ln, expected 0.0, got %f"", result); + pass = 1\'b0; + end + rin = 10.0; + result = $log10(rin); + if (result != 1.0) begin + $display(""Failed run time $log10, expected 1.0, got %f"", result); + pass = 1\'b0; + end + rin = 0.0; + result = $exp(rin); + if (result != 1.0) begin + $display(""Failed run time $exp, expected 1.0, got %f"", result); + pass = 1\'b0; + end + rin = 1.5; + result = $floor(rin); + if (result != 1.0) begin + $display(""Failed run time $floor, expected 1.0, got %f"", result); + pass = 1\'b0; + end + result = $ceil(rin); + if (result != 2.0) begin + $display(""Failed run time $ceil, expected 2.0, got %f"", result); + pass = 1\'b0; + end + + rin = 0.0; + result = $sin(rin); + if (result != 0.0) begin + $display(""Failed run time $sin, expected 0.0, got %f"", result); + pass = 1\'b0; + end + result = $cos(rin); + if (result != 1.0) begin + $display(""Failed run time $cos, expected 1.0, got %f"", result); + pass = 1\'b0; + end + result = $tan(rin); + if (result != 0.0) begin + $display(""Failed run time $tan, expected 0.0, got %f"", result); + pass = 1\'b0; + end + result = $asin(rin); + if (result != 0.0) begin + $display(""Failed run time $asin, expected 0.0, got %f"", result); + pass = 1\'b0; + end + rin = 1.0; + result = $acos(rin); + if (result != 0.0) begin + $display(""Failed run time $acos, expected 0.0, got %f"", result); + pass = 1\'b0; + end + rin = 0.0; + result = $atan(rin); + if (result != 0.0) begin + $display(""Failed run time $atan, expected 0.0, got %f"", result); + pass = 1\'b0; + end + + result = $sinh(rin); + if (result != 0.0) begin + $display(""Failed run time $sinh, expected 0.0, got %f"", result); + pass = 1\'b0; + end + result = $cosh(rin); + if (result != 1.0) begin + $display(""Failed run time $cosh, expected 1.0, got %f"", result); + pass = 1\'b0; + end + result = $tanh(rin); + if (result != 0.0) begin + $display(""Failed run time $tanh, expected 0.0, got %f"", result); + pass = 1\'b0; + end + result = $asinh(rin); + if (result != 0.0) begin + $display(""Failed run time $asinh, expected 0.0, got %f"", result); + pass = 1\'b0; + end + rin = 1.0; + result = $acosh(rin); + if (result != 0.0) begin + $display(""Failed run time $acosh, expected 0.0, got %f"", result); + pass = 1\'b0; + end + rin = 0.0; + result = $atanh(rin); + if (result != 0.0) begin + $display(""Failed run time $atanh, expected 0.0, got %f"", result); + pass = 1\'b0; + end + + rin = 2.0; + result = $pow(-2, rin); + if (result != 4.0) begin + $display(""Failed run time $pow, expected 4.0, got %f"", result); + pass = 1\'b0; + end + rin = 0.0; + result = $atan2(0, rin); + if (result != 0.0) begin + $display(""Failed run time $atan2, expected 0.0, got %f"", result); + pass = 1\'b0; + end + result = $hypot(-1, rin); + if (result != 1.0) begin + $display(""Failed run time $hypot, expected 1.0, got %f"", result); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module dut1(input real i1, output real o1); + +assign o1 = i1; + +endmodule + +module dut2(input real i2, output real o2); + +assign o2 = i2; + +endmodule + +module test(); + +real a, b, c; + +dut2 dut2(a, b); +dut1 dut1(b, c); + +initial begin + $list_vars; +end + +endmodule +" +"module example; + reg r, c, e; + reg [4:0] a, b; + wire d; + + assign d = ( r | ( a == b ) ) ? 1\'b0 : 1\'b1; + + // Change inputs at time n*100 + + initial begin + #100 r = 1\'bx; a = 5\'bxxxxx; b = 5\'bxxxxx; + #100 r = 1\'b1; a = 5\'bxxxxx; b = 5\'bxxxxx; + #100 r = 1\'b1; a = 5\'b00000; b = 5\'b00000; + #100 r = 1\'b0; a = 5\'b00000; b = 5\'b00000; + #100 $finish(0); + end + + // Store c and e at time n*100 + 25. + // Note that the value assigned to c is exactly the same as + // the continuous assignment RHS for d (assigned to e). + + initial #25 forever begin + #100 + c = ( r | ( a == b ) ) ? 1\'b0 : 1\'b1; + e = d; + end + + // Display all values at time n*100 + 50 + + initial #50 forever begin + #100 + $display( ""%b,%b,%b = ( %b | ( %b == %b ) ) ? 0 : 1"", + c, d, e, r, a, b ); + end + +endmodule +" +"// Test implicit casts during procedural non-blocking assignments. + +module implicit_cast(); + +real src_r; + +bit unsigned [7:0] src_u2; +bit signed [7:0] src_s2; + +logic unsigned [7:0] src_u4; +logic signed [7:0] src_s4; + +logic unsigned [7:0] src_ux; +logic signed [7:0] src_sx; + +real dst_r; + +bit unsigned [3:0] dst_u2s; +bit signed [3:0] dst_s2s; + +bit unsigned [11:0] dst_u2l; +bit signed [11:0] dst_s2l; + +logic unsigned [3:0] dst_u4s; +logic signed [3:0] dst_s4s; + +logic unsigned [11:0] dst_u4l; +logic signed [11:0] dst_s4l; + +bit failed; + +initial begin + failed = 0; + + src_r = -7; + src_u2 = 7; + src_s2 = -7; + src_u4 = 7; + src_s4 = -7; + src_ux = 8\'bx0z00111; + src_sx = 8\'bx0z00111; + + $display(""cast to real""); + dst_r <= src_r; #1 $display(""%g"", dst_r); if (dst_r != -7.0) failed = 1; + dst_r <= src_u2; #1 $display(""%g"", dst_r); if (dst_r != 7.0) failed = 1; + dst_r <= src_s2; #1 $display(""%g"", dst_r); if (dst_r != -7.0) failed = 1; + dst_r <= src_u4; #1 $display(""%g"", dst_r); if (dst_r != 7.0) failed = 1; + dst_r <= src_s4; #1 $display(""%g"", dst_r); if (dst_r != -7.0) failed = 1; + dst_r <= src_ux; #1 $display(""%g"", dst_r); if (dst_r != 7.0) failed = 1; + dst_r <= src_sx; #1 $display(""%g"", dst_r); if (dst_r != 7.0) failed = 1; + + $display(""cast to small unsigned bit""); + dst_u2s <= src_r; #1 $display(""%d"", dst_u2s); if (dst_u2s !== 4\'d9) failed = 1; + dst_u2s <= src_u2; #1 $display(""%d"", dst_u2s); if (dst_u2s !== 4\'d7) failed = 1; + dst_u2s <= src_s2; #1 $display(""%d"", dst_u2s); if (dst_u2s !== 4\'d9) failed = 1; + dst_u2s <= src_u4; #1 $display(""%d"", dst_u2s); if (dst_u2s !== 4\'d7) failed = 1; + dst_u2s <= src_s4; #1 $display(""%d"", dst_u2s); if (dst_u2s !== 4\'d9) failed = 1; + dst_u2s <= src_ux; #1 $display(""%d"", dst_u2s); if (dst_u2s !== 4\'d7) failed = 1; + dst_u2s <= src_sx; #1 $display(""%d"", dst_u2s); if (dst_u2s !== 4\'d7) failed = 1; + + $display(""cast to small signed bit""); + dst_s2s <= src_r; #1 $display(""%d"", dst_s2s); if (dst_s2s !== -4\'sd7) failed = 1; + dst_s2s <= src_u2; #1 $display(""%d"", dst_s2s); if (dst_s2s !== 4\'sd7) failed = 1; + dst_s2s <= src_s2; #1 $display(""%d"", dst_s2s); if (dst_s2s !== -4\'sd7) failed = 1; + dst_s2s <= src_u4; #1 $display(""%d"", dst_s2s); if (dst_s2s !== 4\'sd7) failed = 1; + dst_s2s <= src_s4; #1 $display(""%d"", dst_s2s); if (dst_s2s !== -4\'sd7) failed = 1; + dst_s2s <= src_ux; #1 $display(""%d"", dst_s2s); if (dst_s2s !== 4\'sd7) failed = 1; + dst_s2s <= src_sx; #1 $display(""%d"", dst_s2s); if (dst_s2s !== 4\'sd7) failed = 1; + + $display(""cast to large unsigned bit""); + dst_u2l <= src_r; #1 $display(""%d"", dst_u2l); if (dst_u2l !== 12\'d4089) failed = 1; + dst_u2l <= src_u2; #1 $display(""%d"", dst_u2l); if (dst_u2l !== 12\'d7) failed = 1; + dst_u2l <= src_s2; #1 $display(""%d"", dst_u2l); if (dst_u2l !== 12\'d4089) failed = 1; + dst_u2l <= src_u4; #1 $display(""%d"", dst_u2l); if (dst_u2l !== 12\'d7) failed = 1; + dst_u2l <= src_s4; #1 $display(""%d"", dst_u2l); if (dst_u2l !== 12\'d4089) failed = 1; + dst_u2l <= src_ux; #1 $display(""%b"", dst_u2l); if (dst_u2l !== 12\'b000000000111) failed = 1; + dst_u2l <= src_sx; #1 $display(""%b"", dst_u2l); if (dst_u2l !== 12\'b000000000111) failed = 1; + + $display(""cast to large signed bit""); + dst_s2l <= src_r; #1 $display(""%d"", dst_s2l); if (dst_s2l !== -12\'sd7) failed = 1; + dst_s2l <= src_u2; #1 $display(""%d"", dst_s2l); if (dst_s2l !== 12\'sd7) failed = 1; + dst_s2l <= src_s2; #1 $display(""%d"", dst_s2l); if (dst_s2l !== -12\'sd7) failed = 1; + dst_s2l <= src_u4; #1 $display(""%d"", dst_s2l); if (dst_s2l !== 12\'sd7) failed = 1; + dst_s2l <= src_s4; #1 $display(""%d"", dst_s2l); if (dst_s2l !== -12\'sd7) failed = 1; + dst_s2l <= src_ux; #1 $display(""%b"", dst_s2l); if (dst_s2l !== 12\'b000000000111) failed = 1; + dst_s2l <= src_sx; #1 $display(""%b"", dst_s2l); if (dst_s2l !== 12\'b000000000111) failed = 1; + + $display(""cast to small unsigned logic""); + dst_u4s <= src_r; #1 $display(""%d"", dst_u4s); if (dst_u4s !== 4\'d9) failed = 1; + dst_u4s <= src_u2; #1 $display(""%d"", dst_u4s); if (dst_u4s !== 4\'d7) failed = 1; + dst_u4s <= src_s2; #1 $display(""%d"", dst_u4s); if (dst_u4s !== 4\'d9) failed = 1; + dst_u4s <= src_u4; #1 $display(""%d"", dst_u4s); if (dst_u4s !== 4\'d7) failed = 1; + dst_u4s <= src_s4; #1 $display(""%d"", dst_u4s); if (dst_u4s !== 4\'d9) failed = 1; + dst_u4s <= src_ux; #1 $display(""%d"", dst_u4s); if (dst_u4s !== 4\'d7) failed = 1; + dst_u4s <= src_sx; #1 $display(""%d"", dst_u4s); if (dst_u4s !== 4\'d7) failed = 1; + + $display(""cast to small signed logic""); + dst_s4s <= src_r; #1 $display(""%d"", dst_s4s); if (dst_s4s !== -4\'sd7) failed = 1; + dst_s4s <= src_u2; #1 $display(""%d"", dst_s4s); if (dst_s4s !== 4\'sd7) failed = 1; + dst_s4s <= src_s2; #1 $display(""%d"", dst_s4s); if (dst_s4s !== -4\'sd7) failed = 1; + dst_s4s <= src_u4; #1 $display(""%d"", dst_s4s); if (dst_s4s !== 4\'sd7) failed = 1; + dst_s4s <= src_s4; #1 $display(""%d"", dst_s4s); if (dst_s4s !== -4\'sd7) failed = 1; + dst_s4s <= src_ux; #1 $display(""%d"", dst_s4s); if (dst_s4s !== 4\'sd7) failed = 1; + dst_s4s <= src_sx; #1 $display(""%d"", dst_s4s); if (dst_s4s !== 4\'sd7) failed = 1; + + $display(""cast to large unsigned logic""); + dst_u4l <= src_r; #1 $display(""%d"", dst_u4l); if (dst_u4l !== 12\'d4089) failed = 1; + dst_u4l <= src_u2; #1 $display(""%d"", dst_u4l); if (dst_u4l !== 12\'d7) failed = 1; + dst_u4l <= src_s2; #1 $display(""%d"", dst_u4l); if (dst_u4l !== 12\'d4089) failed = 1; + dst_u4l <= src_u4; #1 $display(""%d"", dst_u4l); if (dst_u4l !== 12\'d7) failed = 1; + dst_u4l <= src_s4; #1 $display(""%d"", dst_u4l); if (dst_u4l !== 12\'d4089) failed = 1; + dst_u4l <= src_ux; #1 $display(""%b"", dst_u4l); if (dst_u4l !== 12\'b0000x0z00111) failed = 1; + dst_u4l <= src_sx; #1 $display(""%b"", dst_u4l); if (dst_u4l !== 12\'bxxxxx0z00111) failed = 1; + + $display(""cast to large signed logic""); + dst_s4l <= src_r; #1 $display(""%d"", dst_s4l); if (dst_s4l !== -12\'sd7) failed = 1; + dst_s4l <= src_u2; #1 $display(""%d"", dst_s4l); if (dst_s4l !== 12\'sd7) failed = 1; + dst_s4l <= src_s2; #1 $display(""%d"", dst_s4l); if (dst_s4l !== -12\'sd7) failed = 1; + dst_s4l <= src_u4; #1 $display(""%d"", dst_s4l); if (dst_s4l !== 12\'sd7) failed = 1; + dst_s4l <= src_s4; #1 $display(""%d"", dst_s4l); if (dst_s4l !== -12\'sd7) failed = 1; + dst_s4l <= src_ux; #1 $display(""%b"", dst_s4l); if (dst_s4l !== 12\'b0000x0z00111) failed = 1; + dst_s4l <= src_sx; #1 $display(""%b"", dst_s4l); if (dst_s4l !== 12\'bxxxxx0z00111) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"`timescale 1ns/1ps + +module top; + lower dut(); +endmodule + +module lower; + parameter bad_name = ""this_is_a_bad_name""; + reg [15:0] def = ""OK""; + reg pass = 1\'b1; + reg [1023:0] result; + real rl_res; + + initial begin + + #1; + + /* Display the version and other information. */ + $display(""Testing with Icarus Verilog version: %g, subversion: %g"", + $simparam(""simulatorVersion""), $simparam(""simulatorSubversion"")); + $display(""Using a CPU word size of %g bits."", $simparam(""CPUWordSize"")); + $display(""Running in directory: %0s\ +"", $simparam$str(""cwd"")); + + /* + * Check the time units and precision. + * + * Since this is double math check that the result is within a + * factor of 1e-10 of the correct value. + */ + rl_res = $simparam(""timeUnit"") - 1e-9; + rl_res = (rl_res < 0) ? -rl_res : rl_res; + if (rl_res > 1e-9*1e-10) begin + $display(""$simparam(\\""timeUnit\\"") failed, got %g."", rl_res); + pass = 1\'b0; + end + + rl_res = $simparam(""timePrecision"") - 1e-12; + rl_res = (rl_res < 0) ? -rl_res : rl_res; + if (rl_res >= 1e-12*1e-10) begin + $display(""$simparam(\\""timePrecision\\"") failed, got %g."", rl_res); + pass = 1\'b0; + end + + /* Check the string routines, see below for why this is a task. */ + check_string; + + /* Check that a bad parameter name with a default works. */ + if ($simparam(bad_name, 1.0) != 1.0) begin + $display(""$simparam with a bad name and a default value failed.""); + pass = 1\'b0; + end + + result = $simparam$str(bad_name, def); + if (result[15:0] != ""OK"") begin + $display(""$simparam$str with a bad name and a default value failed.""); + pass = 1\'b0; + end + + /* These should also print an error message. */ + if ($simparam(bad_name) != 0.0) begin + $display(""$simparam with a bad name failed.""); + pass = 1\'b0; + end + + result = $simparam$str(bad_name); + if (result[55:0] != """") begin + $display(""$simparam$str with a bad name failed.""); + pass = 1\'b0; + end + + + /* All these are currently unimplemented and just return 0.0 or N/A. */ + if ($simparam(""gdev"") != 0.0) begin + $display(""$simparam(\\""gdev\\"") failed.""); + pass = 1\'b0; + end + + if ($simparam(""gmin"") != 0.0) begin + $display(""$simparam(\\""gmin\\"") failed.""); + pass = 1\'b0; + end + + if ($simparam(""imax"") != 0.0) begin + $display(""$simparam(\\""imax\\"") failed.""); + pass = 1\'b0; + end + + if ($simparam(""imelt"") != 0.0) begin + $display(""$simparam(\\""imelt\\"") failed.""); + pass = 1\'b0; + end + + if ($simparam(""iteration"") != 0.0) begin + $display(""$simparam(\\""iteration\\"") failed.""); + pass = 1\'b0; + end + + if ($simparam(""scale"") != 0.0) begin + $display(""$simparam(\\""scale\\"") failed.""); + pass = 1\'b0; + end + + if ($simparam(""shrink"") != 0.0) begin + $display(""$simparam(\\""shrink\\"") failed.""); + pass = 1\'b0; + end + + if ($simparam(""sourceScaleFactor"") != 0.0) begin + $display(""$simparam(\\""sourceScaleFactor\\"") failed.""); + pass = 1\'b0; + end + + if ($simparam(""tnom"") != 0.0) begin + $display(""$simparam(\\""tnom\\"") failed.""); + pass = 1\'b0; + end + + result = $simparam$str(""analysis_name""); + if (result[23:0] != ""N/A"") begin + $display(""$simparam$str(\\""analysis_name\\"") failed.""); + pass = 1\'b0; + end + + result = $simparam$str(""analysis_type""); + if (result[23:0] != ""N/A"") begin + $display(""$simparam$str(\\""analysis_type\\"") failed.""); + pass = 1\'b0; + end + + if (pass) $display(""\ +PASSED""); + + end + + /* We need this to make instance and path different. */ + task check_string; + begin + result = $simparam$str(""module""); + if (result[39:0] != ""lower"") begin + $display(""$simparam$str(\\""module\\"") failed, got %0s."", result); + pass = 1\'b0; + end + + result = $simparam$str(""instance""); + if (result[55:0] != ""top.dut"") begin + $display(""$simparam$str(\\""instance\\"") failed, got %0s."", result); + pass = 1\'b0; + end + + result = $simparam$str(""path""); + if (result[159:0] != ""top.dut.check_string"") begin + $display(""$simparam$str(\\""instance\\"") failed, got %0s."", result); + pass = 1\'b0; + end + end + endtask + +endmodule +" +"// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +// Test for multiple choices in case alternative statements. + +module vhdl_case_multi_test; + reg [2:0] test_vec; + reg parity; + vhdl_case_multi dut(test_vec, parity); + + initial begin + // Execute both paths + test_vec = \'b101; + #1; + if(parity !== 1\'b0) begin + $display(""FAILED 1""); + $finish(); + end + + test_vec = \'b001; + #1; + if(parity !== 1\'b1) begin + $display(""FAILED 2""); + $finish(); + end + + $display(""PASSED""); + end +endmodule + +" +" +program main; + + function real sum_array(real array[]); + int idx; + sum_array = 0.0; + for (idx = 0 ; idx < array.size() ; idx = idx+1) +\tsum_array = sum_array + array[idx]; + endfunction // sum_array + + real obj[]; + real foo; + initial begin + foo = sum_array(\'{}); + if (foo != 0.0) begin +\t $display(""FAILED -- sum of empty array returns %0d"", foo); +\t $finish; + end + + obj = new[3]; + obj = \'{1.0,2.0,3.0}; + foo = sum_array(obj); + if (foo != 6.0) begin +\t $display(""FAILED -- sum of \'{%f,%f,%f} is %0d"", obj[0], obj[1], obj[2], foo); +\t $finish; + end + + obj = new[3] (\'{4.0,5.0,6.0}); + foo = sum_array(obj); + if (foo != 15.0) begin +\t $display(""FAILED -- sum of \'{4,5,6} is %0d"", foo); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endprogram // main +" +" +// This tests the basic support for default arguments to task/function +// ports. The default port syntax gives SystemVerilog a limited form +// of variable argument lists. + +program main; + + class foo_t; + int int_val; + logic[3:0] log_val; + string text_val; + + task init (int int_init, logic[3:0]log_init = 4\'bzzzz, string text_init = ""default text""); +\t this.init2(int_init, log_init, text_init); + endtask : init + + task init2 (int int_init, logic[3:0]log_init, string text_init); +\t int_val = int_init; +\t log_val = log_init; +\t text_val = text_init; + endtask : init2 + + endclass : foo_t + + + foo_t obj1; + + initial begin + obj1 = new; + obj1.init(4, 4\'b0101, ""new text""); + if (obj1.int_val != 4 || obj1.log_val !== 4\'b0101 || obj1.text_val != ""new text"") begin +\t $display(""FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s"", obj1.int_val, obj1.log_val, obj1.text_val); +\t $finish; + end + + obj1 = new; + obj1.init(5, , ""new text""); + if (obj1.int_val != 5 || obj1.log_val !== 4\'bzzzz || obj1.text_val != ""new text"") begin +\t $display(""FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s"", obj1.int_val, obj1.log_val, obj1.text_val); +\t $finish; + end + + obj1 = new; + obj1.init(6, 4\'b1010); + if (obj1.int_val != 6 || obj1.log_val !== 4\'b1010 || obj1.text_val != ""default text"") begin +\t $display(""FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s"", obj1.int_val, obj1.log_val, obj1.text_val); +\t $finish; + end + + obj1 = new; + obj1.init(7); + if (obj1.int_val != 7 || obj1.text_val != ""default text"") begin +\t $display(""FAILED -- obj1.int_val=%0d, obj1.text_val=%0s"", obj1.int_val, obj1.text_val); +\t $finish; + end + + $display(""PASSED""); + end + +endprogram // main +" +"module top; + reg test; + event ev; + reg val; + + initial begin + #10; + test = 1\'b1; + #20; + $display(""FAILED""); + // I would expect this watchdog to require a $finish() since the other + // initial did not finish, but it\'s not needed so that implies the + // other initial is getting disabled not just the named begin. + end + + initial begin + test = 1\'b0; + val = 1\'b0; + fork + // With the @ line here development fails. If it is after the named + // begin it passes. + @(test) disable nb; + begin : nb + // Any blocking item here causes the problem. +// wait(val); +// @(ev); + #20; + end + join + // This is never executed even though it should run at time 10. + $display(""PASSED""); + // The finish is required to prevent the watchdog from running. + $finish; + end +endmodule +" +"// Test unary operators in constant functions +module constfunc4(); + +function [7:0] LInv(input [7:0] x); + LInv = ~x; +endfunction + +function [7:0] LNeg(input [7:0] x); + LNeg = -x; +endfunction + +function real RNeg(input real x); + RNeg = -x; +endfunction + +function LAnd(input [7:0] x); + LAnd = &x; +endfunction + +function LNot(input [7:0] x); + LNot = !x; +endfunction + +function RNot(input real x); + RNot = !x; +endfunction + +localparam [7:0] ResultLInv = LInv(8\'h0f); +localparam [7:0] ResultLNeg = LNeg(8\'h0f); +localparam real ResultRNeg = RNeg(15.0); +localparam ResultLAnd = LAnd(8\'hff); +localparam ResultLNot = LNot(8\'h00); +localparam ResultRNot = RNot(0.0); + +reg failed; + +initial begin + failed = 0; + $display(""%h"", ResultLInv); + $display(""%h"", ResultLNeg); + $display(""%g"", ResultRNeg); + $display(""%b"", ResultLAnd); + $display(""%b"", ResultLNot); + $display(""%b"", ResultRNot); + if (ResultLNeg !== 8\'hf1) failed = 1; + if (ResultRNeg != -15.0) failed = 1; + if (ResultLAnd !== 1\'b1) failed = 1; + if (ResultLNot !== 1\'b1) failed = 1; + if (ResultRNot !== 1\'b1) failed = 1; + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"`begin_keywords ""1364-2001-noconfig"" +// Copyright 2007, Martin Whitaker. +// This code may be freely copied for any purpose. + +module gen_param_test(); + +localparam\tW = 3; +localparam\tD = 3; + +reg [W-1:0]\tA[1:D]; +reg [W-1:0]\tB[1:D]; +wire [W-1:0]\tY[1:D]; + +generate + genvar\tj; + + for (j = 1; j <= D; j = j + 1) begin:sum + adder #(W) instance(A[j], B[j], Y[j]); + end +endgenerate + +integer\t\ti; + +initial begin + for (i = 1; i <= D; i = i + 1) begin + A[i] = i - 1; + B[i] = i + 1; + end + #1; + for (i = 1; i <= D; i = i + 1) begin + $display(""%d + %d = %d"", A[i-1], B[i-1], Y[i-1]); + end +end + +endmodule + + +module adder #(parameter W = 1) ( + +input wire [W-1:0]\tA, +input wire [W-1:0]\tB, +output wire [W-1:0]\tY + +); + +assign Y = A + B; + +endmodule +`end_keywords +" +"// Test implicit casts during net declaration assignments. + +`ifdef __ICARUS__ + `define SUPPORT_REAL_NETS_IN_IVTEST + `define SUPPORT_TWO_STATE_NETS_IN_IVTEST +`endif + +module implicit_cast(); + +real src_r; + +bit unsigned [7:0] src_u2; +bit signed [7:0] src_s2; + +logic unsigned [7:0] src_u4; +logic signed [7:0] src_s4; + +logic unsigned [7:0] src_ux; +logic signed [7:0] src_sx; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +wire real dst1_r = src_r; +wire real dst2_r = src_u2; +wire real dst3_r = src_s2; +wire real dst4_r = src_u4; +wire real dst5_r = src_s4; +wire real dst6_r = src_ux; +wire real dst7_r = src_sx; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +wire bit unsigned [3:0] dst1_u2s = src_r; +wire bit unsigned [3:0] dst2_u2s = src_u2; +wire bit unsigned [3:0] dst3_u2s = src_s2; +wire bit unsigned [3:0] dst4_u2s = src_u4; +wire bit unsigned [3:0] dst5_u2s = src_s4; +wire bit unsigned [3:0] dst6_u2s = src_ux; +wire bit unsigned [3:0] dst7_u2s = src_sx; + +wire bit signed [3:0] dst1_s2s = src_r; +wire bit signed [3:0] dst2_s2s = src_u2; +wire bit signed [3:0] dst3_s2s = src_s2; +wire bit signed [3:0] dst4_s2s = src_u4; +wire bit signed [3:0] dst5_s2s = src_s4; +wire bit signed [3:0] dst6_s2s = src_ux; +wire bit signed [3:0] dst7_s2s = src_sx; + +wire bit unsigned [11:0] dst1_u2l = src_r; +wire bit unsigned [11:0] dst2_u2l = src_u2; +wire bit unsigned [11:0] dst3_u2l = src_s2; +wire bit unsigned [11:0] dst4_u2l = src_u4; +wire bit unsigned [11:0] dst5_u2l = src_s4; +wire bit unsigned [11:0] dst6_u2l = src_ux; +wire bit unsigned [11:0] dst7_u2l = src_sx; + +wire bit signed [11:0] dst1_s2l = src_r; +wire bit signed [11:0] dst2_s2l = src_u2; +wire bit signed [11:0] dst3_s2l = src_s2; +wire bit signed [11:0] dst4_s2l = src_u4; +wire bit signed [11:0] dst5_s2l = src_s4; +wire bit signed [11:0] dst6_s2l = src_ux; +wire bit signed [11:0] dst7_s2l = src_sx; +`endif + +wire logic unsigned [3:0] dst1_u4s = src_r; +wire logic unsigned [3:0] dst2_u4s = src_u2; +wire logic unsigned [3:0] dst3_u4s = src_s2; +wire logic unsigned [3:0] dst4_u4s = src_u4; +wire logic unsigned [3:0] dst5_u4s = src_s4; +wire logic unsigned [3:0] dst6_u4s = src_ux; +wire logic unsigned [3:0] dst7_u4s = src_sx; + +wire logic signed [3:0] dst1_s4s = src_r; +wire logic signed [3:0] dst2_s4s = src_u2; +wire logic signed [3:0] dst3_s4s = src_s2; +wire logic signed [3:0] dst4_s4s = src_u4; +wire logic signed [3:0] dst5_s4s = src_s4; +wire logic signed [3:0] dst6_s4s = src_ux; +wire logic signed [3:0] dst7_s4s = src_sx; + +wire logic unsigned [11:0] dst1_u4l = src_r; +wire logic unsigned [11:0] dst2_u4l = src_u2; +wire logic unsigned [11:0] dst3_u4l = src_s2; +wire logic unsigned [11:0] dst4_u4l = src_u4; +wire logic unsigned [11:0] dst5_u4l = src_s4; +wire logic unsigned [11:0] dst6_u4l = src_ux; +wire logic unsigned [11:0] dst7_u4l = src_sx; + +wire logic signed [11:0] dst1_s4l = src_r; +wire logic signed [11:0] dst2_s4l = src_u2; +wire logic signed [11:0] dst3_s4l = src_s2; +wire logic signed [11:0] dst4_s4l = src_u4; +wire logic signed [11:0] dst5_s4l = src_s4; +wire logic signed [11:0] dst6_s4l = src_ux; +wire logic signed [11:0] dst7_s4l = src_sx; + +bit failed; + +initial begin + failed = 0; + + src_r = -7; + src_u2 = 7; + src_s2 = -7; + src_u4 = 7; + src_s4 = -7; + src_ux = 8\'bx0z00111; + src_sx = 8\'bx0z00111; + + #1; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST + $display(""cast to real""); + $display(""%g"", dst1_r); if (dst1_r != -7.0) failed = 1; + $display(""%g"", dst2_r); if (dst4_r != 7.0) failed = 1; + $display(""%g"", dst3_r); if (dst5_r != -7.0) failed = 1; + $display(""%g"", dst4_r); if (dst2_r != 7.0) failed = 1; + $display(""%g"", dst5_r); if (dst3_r != -7.0) failed = 1; + $display(""%g"", dst6_r); if (dst6_r != 7.0) failed = 1; + $display(""%g"", dst7_r); if (dst7_r != 7.0) failed = 1; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST + $display(""cast to small unsigned bit""); + $display(""%d"", dst1_u2s); if (dst1_u2s !== 4\'d9) failed = 1; + $display(""%d"", dst2_u2s); if (dst4_u2s !== 4\'d7) failed = 1; + $display(""%d"", dst3_u2s); if (dst5_u2s !== 4\'d9) failed = 1; + $display(""%d"", dst4_u2s); if (dst2_u2s !== 4\'d7) failed = 1; + $display(""%d"", dst5_u2s); if (dst3_u2s !== 4\'d9) failed = 1; + $display(""%d"", dst6_u2s); if (dst6_u2s !== 4\'d7) failed = 1; + $display(""%d"", dst7_u2s); if (dst7_u2s !== 4\'d7) failed = 1; + + $display(""cast to small signed bit""); + $display(""%d"", dst1_s2s); if (dst1_s2s !== -4\'sd7) failed = 1; + $display(""%d"", dst2_s2s); if (dst4_s2s !== 4\'sd7) failed = 1; + $display(""%d"", dst3_s2s); if (dst5_s2s !== -4\'sd7) failed = 1; + $display(""%d"", dst4_s2s); if (dst2_s2s !== 4\'sd7) failed = 1; + $display(""%d"", dst5_s2s); if (dst3_s2s !== -4\'sd7) failed = 1; + $display(""%d"", dst6_s2s); if (dst6_s2s !== 4\'sd7) failed = 1; + $display(""%d"", dst7_s2s); if (dst7_s2s !== 4\'sd7) failed = 1; + + $display(""cast to large unsigned bit""); + $display(""%d"", dst1_u2l); if (dst1_u2l !== 12\'d4089) failed = 1; + $display(""%d"", dst2_u2l); if (dst4_u2l !== 12\'d7) failed = 1; + $display(""%d"", dst3_u2l); if (dst5_u2l !== 12\'d4089) failed = 1; + $display(""%d"", dst4_u2l); if (dst2_u2l !== 12\'d7) failed = 1; + $display(""%d"", dst5_u2l); if (dst3_u2l !== 12\'d4089) failed = 1; + $display(""%b"", dst6_u2l); if (dst6_u2l !== 12\'b000000000111) failed = 1; + $display(""%b"", dst7_u2l); if (dst7_u2l !== 12\'b000000000111) failed = 1; + + $display(""cast to large signed bit""); + $display(""%d"", dst1_s2l); if (dst1_s2l !== -12\'sd7) failed = 1; + $display(""%d"", dst2_s2l); if (dst4_s2l !== 12\'sd7) failed = 1; + $display(""%d"", dst3_s2l); if (dst5_s2l !== -12\'sd7) failed = 1; + $display(""%d"", dst4_s2l); if (dst2_s2l !== 12\'sd7) failed = 1; + $display(""%d"", dst5_s2l); if (dst3_s2l !== -12\'sd7) failed = 1; + $display(""%b"", dst6_s2l); if (dst6_s2l !== 12\'b000000000111) failed = 1; + $display(""%b"", dst7_s2l); if (dst7_s2l !== 12\'b000000000111) failed = 1; +`endif + + $display(""cast to small unsigned logic""); + $display(""%d"", dst1_u4s); if (dst1_u4s !== 4\'d9) failed = 1; + $display(""%d"", dst2_u4s); if (dst4_u4s !== 4\'d7) failed = 1; + $display(""%d"", dst3_u4s); if (dst5_u4s !== 4\'d9) failed = 1; + $display(""%d"", dst4_u4s); if (dst2_u4s !== 4\'d7) failed = 1; + $display(""%d"", dst5_u4s); if (dst3_u4s !== 4\'d9) failed = 1; + $display(""%d"", dst6_u4s); if (dst6_u4s !== 4\'d7) failed = 1; + $display(""%d"", dst7_u4s); if (dst7_u4s !== 4\'d7) failed = 1; + + $display(""cast to small signed logic""); + $display(""%d"", dst1_s4s); if (dst1_s4s !== -4\'sd7) failed = 1; + $display(""%d"", dst2_s4s); if (dst4_s4s !== 4\'sd7) failed = 1; + $display(""%d"", dst3_s4s); if (dst5_s4s !== -4\'sd7) failed = 1; + $display(""%d"", dst4_s4s); if (dst2_s4s !== 4\'sd7) failed = 1; + $display(""%d"", dst5_s4s); if (dst3_s4s !== -4\'sd7) failed = 1; + $display(""%d"", dst6_s4s); if (dst6_s4s !== 4\'sd7) failed = 1; + $display(""%d"", dst7_s4s); if (dst7_s4s !== 4\'sd7) failed = 1; + + $display(""cast to large unsigned logic""); + $display(""%d"", dst1_u4l); if (dst1_u4l !== 12\'d4089) failed = 1; + $display(""%d"", dst2_u4l); if (dst4_u4l !== 12\'d7) failed = 1; + $display(""%d"", dst3_u4l); if (dst5_u4l !== 12\'d4089) failed = 1; + $display(""%d"", dst4_u4l); if (dst2_u4l !== 12\'d7) failed = 1; + $display(""%d"", dst5_u4l); if (dst3_u4l !== 12\'d4089) failed = 1; + $display(""%b"", dst6_u4l); if (dst6_u4l !== 12\'b0000x0z00111) failed = 1; + $display(""%b"", dst7_u4l); if (dst7_u4l !== 12\'bxxxxx0z00111) failed = 1; + + $display(""cast to large signed logic""); + $display(""%d"", dst1_s4l); if (dst1_s4l !== -12\'sd7) failed = 1; + $display(""%d"", dst2_s4l); if (dst4_s4l !== 12\'sd7) failed = 1; + $display(""%d"", dst3_s4l); if (dst5_s4l !== -12\'sd7) failed = 1; + $display(""%d"", dst4_s4l); if (dst2_s4l !== 12\'sd7) failed = 1; + $display(""%d"", dst5_s4l); if (dst3_s4l !== -12\'sd7) failed = 1; + $display(""%b"", dst6_s4l); if (dst6_s4l !== 12\'b0000x0z00111) failed = 1; + $display(""%b"", dst7_s4l); if (dst7_s4l !== 12\'bxxxxx0z00111) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"// Copyright (c) 2015-2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test reading files using std.textio library. + +module vhdl_textio_read_test; +reg clk, active, ok; +int line_counter; +vhdl_textio_read dut(clk, active, line_counter, ok); + +always #1 clk = ~clk; + +initial begin + clk = 0; + active = 1; + + // wait until the input file is read + #14 active = 0; + + if(ok !== 1\'b1) begin + $display(""FAILED""); + $finish(); + end + + $display(""PASSED""); + #0; // Need to wait for the file to close before we finish! + $finish(); +end +endmodule +" +"/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Test the select of a bit from a vector. + */ + +module main; + + reg [3:0] a = 4\'b0110; + reg [1:0] s = 0; + + wire b = a[s]; + + initial begin + #1 if (b !== 0) begin +\t $display(""FAILED -- a=%b, s=%b, b=%b"", a, s, b); +\t $finish; + end + + s = 1; + + #1 if (b !== 1) begin +\t $display(""FAILED -- a=%b, s=%b, b=%b"", a, s, b); +\t $finish; + end + + s = 2; + + #1 if (b !== 1) begin +\t $display(""FAILED -- a=%b, s=%b, b=%b"", a, s, b); +\t $finish; + end + + s = 3; + + #1 if (b !== 0) begin +\t $display(""FAILED -- a=%b, s=%b, b=%b"", a, s, b); +\t $finish; + end + + s = 2\'bxx; + #1 if (b !== 1\'bx) begin +\t $display(""FAILED -- a=%b, s=%b, b=%b"", a, s, b); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate parameter passing override in module declaration. +// +// Build a single line of storage - Note it\'s +// + +module reg32 (clk,we, din, dout); + +parameter WIDTH=32; + +input\t\t\twe; +input\t\t\tclk; +input [WIDTH-1:0]\tdin; + +output [WIDTH-1:0]\tdout; + +reg [WIDTH-1:0] store; + +always @(posedge clk) + if(we) + store <= din; + +assign dout = store ; + +endmodule + +module memory(clk, we, addr, din, dout); + +parameter WIDTH=8; + +input\t\t\tclk; +input\t\t\twe; +input [1:0]\t\taddr; +input [WIDTH-1:0]\tdin; + +output [WIDTH-1:0]\tdout; +reg [WIDTH-1:0]\tdout; + +wire [WIDTH-1:0]\tdout0,dout1,dout2,dout3; +reg\t\t\twe0,we1,we2,we3; + +reg32 #(WIDTH) reg0 (.clk(clk),.we(we0),.din(din[WIDTH-1:0]), + .dout(dout0[WIDTH-1:0])); +reg32 #(WIDTH) reg1 (.clk(clk),.we(we1),.din(din[WIDTH-1:0]), + .dout(dout1[WIDTH-1:0])); +reg32 #(WIDTH) reg2 (.clk(clk),.we(we2),.din(din[WIDTH-1:0]), + .dout(dout2[WIDTH-1:0])); +reg32 #(WIDTH) reg3 (.clk(clk),.we(we3),.din(din[WIDTH-1:0]), + .dout(dout3[WIDTH-1:0])); + +// +// Build we decode +// +always @(addr or we) + case (addr) + 2\'b00: begin + we0 = we; + we1 = 0; + we2 = 0; + we3 = 0; + end + 2\'b01: begin + we0 = 0; + we1 = we; + we2 = 0; + we3 = 0; + end + 2\'b10: begin + we0 = 0; + we1 = 0; + we2 = we; + we3 = 0; + end + 2\'b11: begin + we0 = 0; + we1 = 0; + we2 = 0; + we3 = we; + end + endcase + +// +// Connect dout to register output +// +always @(addr or dout0 or dout1 or dout2 or dout3) + case (addr) + 2\'b00: dout = dout0; + 2\'b01: dout = dout1; + 2\'b10: dout = dout2; + 2\'b11: dout = dout3; + endcase + +endmodule + +module top; + +parameter WIDTH=8; +reg\t\t\tclk; +reg\t\t\twe; +reg [1:0]\t\taddr; +reg [WIDTH-1:0]\t\tdin; +reg\t\t\terror; +wire [WIDTH-1:0]\t\tdout; + +memory mem (clk, we, addr, din, dout); + +initial + begin +// $dumpfile(""test.vcd""); +// $dumpvars(0,top.mem.reg0); + + clk = 0; + error =0; + #3; + we = 1; + addr = 0; + din = 32\'b0_00; + #10; + addr = 1; + din = 32\'h1; + #10; + addr = 2; + din = 32\'h2; + #10; + addr = 3; + din = 32\'h3; + #10; + we = 0; + addr = 0; + #1; + if(dout[7:0] !== 8\'h00) + begin + $display(""FAILED - Ram[0] not 0, is %h"",dout[7:0]); + error = 1; + end + if(error == 0) + $display(""PASSED""); + $finish ; + end + +always #(5) clk = ~clk; +endmodule +" +"// pr1664684 + +module bug (rdo, rm, cpen, up14, rdi); + output [31:0] rdo; + input\t rm, cpen; + input [31:0] up14, rdi; + + initial $monitor($time,,rdo,,rm,cpen,,up14,,rdi); + assign\t rdo = (rm | cpen) ? up14 : rdi; + + endmodule + + module bench; + + reg [31:0] up14; + wire [31:0] rdo; + reg\t rm, cpen; + tri0 [31:0] rdi; + + bug u1 (rdo, rm, cpen, up14, rdi); + + initial begin + rm = 1'bX; + cpen = 1'b0; + up14 = 'hX; + #40; + up14 = 32'd0; + rm = 1'b0; + #40; + $finish(0); + end + endmodule +" +"module test; + +bit [7:0] mema[]; +bit [7:0] memb[]; + +reg failed = 0; + +initial begin + mema = new[4] (\'{8\'d1,8\'d2,8\'d3,8\'d4}); + $display(""%x %x %x %x"", mema[0], mema[1], mema[2], mema[3]); + memb = new[4] (mema); + $display(""%x %x %x %x"", memb[0], memb[1], memb[2], memb[3]); + if (memb[0] !== 8\'d1 || memb[1] !== 8\'d2 || memb[2] !== 8\'d3 || memb[3] !== 8\'d4) failed = 1; + memb = new[5] (memb); + $display(""%x %x %x %x %x"", memb[0], memb[1], memb[2], memb[3], memb[4]); + if (memb[0] !== 8\'d1 || memb[1] !== 8\'d2 || memb[2] !== 8\'d3 || memb[3] !== 8\'d4 || memb[4] !== 8\'b0) failed = 1; + memb = new[3] (memb); + $display(""%x %x %x"", memb[0], memb[1], memb[2]); + if (memb[0] !== 8\'d1 || memb[1] !== 8\'d2 || memb[2] !== 8\'d3) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +" +// This tests the basic support for default arguments to task/function +// ports. The default port syntax gives SystemVerilog a limited form +// of variable argument lists. + +program main; + + class foo_t; + int int_val; + logic[3:0] log_val; + string text_val; + + task init (int int_init, logic[3:0]log_init = 4\'bzzzz, string text_init = ""default text""); +\t int_val = int_init; +\t log_val = log_init; +\t text_val = text_init; + endtask : init + + endclass : foo_t + + + foo_t obj1; + + initial begin + obj1 = new; + obj1.init(4, 4\'b0101, ""new text""); + if (obj1.int_val != 4 || obj1.log_val !== 4\'b0101 || obj1.text_val != ""new text"") begin +\t $display(""FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s"", obj1.int_val, obj1.log_val, obj1.text_val); +\t $finish; + end + + obj1 = new; + obj1.init(5, , ""new text""); + if (obj1.int_val != 5 || obj1.log_val !== 4\'bzzzz || obj1.text_val != ""new text"") begin +\t $display(""FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s"", obj1.int_val, obj1.log_val, obj1.text_val); +\t $finish; + end + + obj1 = new; + obj1.init(6, 4\'b1010); + if (obj1.int_val != 6 || obj1.log_val !== 4\'b1010 || obj1.text_val != ""default text"") begin +\t $display(""FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s"", obj1.int_val, obj1.log_val, obj1.text_val); +\t $finish; + end + + obj1 = new; + obj1.init(7); + if (obj1.int_val != 7 || obj1.text_val != ""default text"") begin +\t $display(""FAILED -- obj1.int_val=%0d, obj1.text_val=%0s"", obj1.int_val, obj1.text_val); +\t $finish; + end + + $display(""PASSED""); + end + +endprogram // main +" +" +program main; + + function string sum_array(string array[]); + int idx; + sum_array = """"; + for (idx = 0 ; idx < array.size() ; idx = idx+1) +\tsum_array = {sum_array, array[idx]}; + endfunction // sum_array + + string obj[]; + string foo; + initial begin + foo = sum_array(\'{}); + if (foo != """") begin +\t $display(""FAILED -- sum of empty array returns %0s"", foo); +\t $finish; + end + + obj = new[3]; + obj = \'{""1"", ""2"", ""3""}; + foo = sum_array(obj); + if (foo != ""123"") begin +\t $display(""FAILED -- sum of \'{\\""1\\"",\\""2\\"",\\""3\\""} is %0s"", foo); +\t $finish; + end + + obj = new[3] (\'{""A"", ""B"", ""C""}); + foo = sum_array(obj); + if (foo != ""ABC"") begin +\t $display(""FAILED -- sum of \'{\\""A\\"",\\""B\\"",\\""C\\""} is %0s"", foo); +\t $finish; + end + + obj = new[3] (""A""); + foo = sum_array(obj); + if (foo != ""AAA"") begin +\t $display(""FAILED -- sum of \\""AAA\\"" is %0s"", foo); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endprogram // main +" +"module top; + reg pass; + integer result; + reg [3:0] expr; + + initial begin + pass = 1\'b1; + + result = $countones(1\'b0); + if (result != 0) begin + $display(""FAILED: for 1\'b0 expected a count of 0, got %d"", result); + pass = 1\'b0; + end + + result = $countones(1\'b1); + if (result != 1) begin + $display(""FAILED: for 1\'b1 expected a count of 1, got %d"", result); + pass = 1\'b0; + end + + result = $countones(2\'b01); + if (result != 1) begin + $display(""FAILED: for 2\'b01 expected a count of 1, got %d"", result); + pass = 1\'b0; + end + + result = $countones(4\'b0111); + if (result != 3) begin + $display(""FAILED: for 4\'b0111 expected a count of 3, got %d"", result); + pass = 1\'b0; + end + + expr = 4\'b1100; + result = $countones(expr); + if (result != 2) begin + $display(""FAILED: for 4\'b1100 expected a count of 2, got %d"", result); + pass = 1\'b0; + end + + result = $countones(34\'b1100000000000000000000000000000001); + if (result != 3) begin + $display(""FAILED: for 34\'1100000000000000000000000000000001 expected a count of 3, got %d"", result); + pass = 1\'b0; + end + + result = $countones(34\'b1111000000110000001100000011000000); + if (result != 10) begin + $display(""FAILED: for 34\'1111000000110000001100000011000000 expected a count of 10, got %d"", result); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate that an lvalue concat can receive an assignment. +// +// D: Validate that an lvalue can be a concatenation. +// + +module main (); +reg a; +reg b; +reg working; + +initial +begin + working = 1; + {a,b} = 2\'b00 ; + + if( (a != 0) & (b != 0)) + begin + $display(""FAILED {a,b} Expected 2\'b00 - received %b%b"",a,b); + working = 0; + end + + {a,b} = 2\'b01 ; + + if( (a != 0) & (b != 1)) + begin + $display(""FAILED {a,b} Expected 2\'b01 - received %b%b"",a,b); + working = 0; + end + + {a,b} = 2\'b10 ; + + if( (a != 1) & (b != 0)) + begin + $display(""FAILED {a,b} Expected 2\'b10 - received %b%b"",a,b); + working = 0; + end + + {a,b} = 2\'b11 ; + + if( (a != 1) & (b != 1)) + begin + $display(""FAILED {a,b} Expected 2\'b11 - received %b%b"",a,b); + working = 0; + end + + if(working) + $display(""PASSED\ +""); + +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate casez/endcase w/ default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 ) + casez (val1) + 5\'b0000z: result = 0; + 5\'b001?0: result = 1 ; + 5\'b01?z0: result = 2; + default: result = 4; + endcase + +initial + begin + error = 0; + + val1 = 5\'b0000z ; + if(result !=0) + begin + $display(""FAILED casez 3.10D - case (expr) lab1: ""); + error = 1; + end + + val1 = 5\'b001z0; + if(result !=1) + begin + $display(""FAILED casez 3.10D - case (expr) lab2: ""); + error = 1; + end + + val1 = 5\'b1zzzz;\t// Should get no-action - expr = 3\'b011 + if(result !=4) + begin + $display(""FAILED casez 3.10D - case (expr) lab1: ""); + error = 1; + end + + if(error == 0) + $display(""PASSED""); + end + +endmodule // main +" +"`timescale 1us/100ns + +module top; + reg pass = 1\'b1; + + real ra, rb, rpow; + + initial begin + ra = 1.0; rb = 2.0; + rpow = ra ** rb; + if (rpow != 1.0) begin + pass = 1\'b0; + $display(""Real: power value not correct, expected 1.0 got %g."", rpow); + end + + ra = 2.0; + rpow = ra ** rb; + if (rpow != 4.0) begin + pass = 1\'b0; + $display(""Real: power value not correct, expected 4.0 got %g."", rpow); + end + + ra = 0.0; + rpow = ra ** rb; + if (rpow != 0.0) begin + pass = 1\'b0; + $display(""Real: power value not correct, expected 0.0 got %g."", rpow); + end + + ra = 10.0; + rpow = ra ** rb; + if (rpow != 100.0) begin + pass = 1\'b0; + $display(""Real: power value not correct, expected 100.0 got %g."", rpow); + end + + ra = 0.0; rb = -1.0; + rpow = ra ** rb; + $display(""0.0 ** -1.0 = %g"", rpow); + + ra = -1.0; rb = 2.5; + rpow = ra ** rb; + $display(""-1.0 ** 2.5 = %g"", rpow); + + if (pass) $display(""PASSED""); + end +endmodule +" +"// This is a simple test of automatic functions +module autof(); + reg [7:0] result; + + function automatic [7:0] fact; + input [7:0] n; + if (n == 0) + fact = 1; + else + fact = n * fact(n-1); + endfunction // fact + + initial begin + result = fact(4); + if (result == 24) + $display(""PASSED""); + else + $display(""FAILED -- Expected 24 but got %d"", result); + end + +endmodule // autof +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - include a single file +// + +`include ""ivltests/else3.v"" +" +"module cast_large_real; + +reg [63:0] u64; +reg signed [63:0] i64; + +reg [64:0] u65; +reg signed [64:0] i65; + +real r; + +reg fail; + +initial begin + fail = 0; + + u64 = {1\'b1, 63\'d0}; + r = u64; + $display(""Convert u64 to real""); + $display(""Expect : %0f"", 2.0**63); + $display(""Got : %0f"", r); + if (r != 2.0**63) fail = 1; + u64 = r; + $display(""Convert real to u64""); + $display(""Expect : %0d"", {1\'b1, 63\'d0}); + $display(""Got : %0d"", u64); + if (u64 != {1\'b1, 63\'d0}) fail = 1; + + i64 = {1\'b1, 63\'d0}; + r = i64; + $display(""Convert i64 to real""); + $display(""Expect : %0f"", -(2.0**63)); + $display(""Got : %0f"", r); + if (r != -(2.0**63)) fail = 1; + i64 = r; + $display(""Convert real to i64""); + $display(""Expect : %0d"", $signed({1\'b1, 63\'d0})); + $display(""Got : %0d"", i64); + if (i64 != {1\'b1, 63\'d0}) fail = 1; + + u65 = {1\'b1, 64\'d0}; + r = u65; + $display(""Convert u65 to real""); + $display(""Expect : %0f"", 2.0**64); + $display(""Got : %0f"", r); + if (r != 2.0**64) fail = 1; + u65 = r; + $display(""Convert real to u65""); + $display(""Expect : %0d"", {1\'b1, 64\'d0}); + $display(""Got : %0d"", u65); + if (u65 != {1\'b1, 64\'d0}) fail = 1; + + i65 = {1\'b1, 64\'d0}; + r = i65; + $display(""Convert i65 to real""); + $display(""Expect : %0f"", -(2.0**64)); + $display(""Got : %0f"", r); + if (r != -(2.0**64)) fail = 1; + i65 = r; + $display(""Convert real to i65""); + $display(""Expect : %0d"", $signed({1\'b1, 64\'d0})); + $display(""Got : %0d"", i65); + if (i65 != {1\'b1, 64\'d0}) fail = 1; + + if (fail) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"typedef logic data_t; + +module dut(i, o); + +input data_t i; +output data_t o; + +always @* o = i; + +endmodule + +module test(); + +data_t i, o; + +dut dut(i, o); + +reg failed = 0; + +initial begin + i = 1\'b0; + #0 $display(i,,o); + if (o !== 1\'b0) failed = 1; + i = 1\'b1; + #0 $display(i,,o); + if (o !== 1\'b1) failed = 1; + i = 1\'bx; + #0 $display(i,,o); + if (o !== 1\'bx) failed = 1; + i = 1\'bz; + #0 $display(i,,o); + if (o !== 1\'bz) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"// +// Copyright (c) 2002 Steven Wilson (steve@ka6s.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Synth of basic expression assign with add +// +// +module adder (q,a,b ); +input a,b; +output [1:0] q; + +assign q = a + b; + +endmodule + +module test ; + +reg d; + +wire [1:0] q; + +adder u_add (.q(q),.a(d),.b(d)); + +(* ivl_synthesis_off *) +initial + begin +// $dumpfile(""test.vcd""); +// $dumpvars(0,test); + d = 0; + # 1; + if (q !== 2\'b0) + begin + $display(""FAILED - Q isn\'t 0 ""); +\t $finish; + end + #1 ; + d = 1; + # 1; + if (q !== 2\'b10) + begin + $display(""FAILED - Q isn\'t 2 ""); +\t $finish; + end + $display(""PASSED""); + + end +endmodule +" +"// Released under GPL 2.0 +// (C) 2002 Tom Verbeure + +module main; + +\tinitial begin +\t\t$display(""============================""); +\t\t$display("">|This is a test|""); +\t\t$display(""*|%s|"", ""This is a test""); +\t\t$display(""*|"", ""This is a test"", ""|""); + +\t\t$display("">| 65|""); +\t\t$display(""*|%d|"", ""A""); +\t\t$display("">|16706|""); +\t\t$display(""*|%d|"", ""AB""); +\t\t$display("">| 4276803|""); +\t\t$display(""*|%d|"", ""ABC""); +\t\t$display("">|1094861636|""); +\t\t$display(""*|%d|"", ""ABCD""); + +\t\t$display("">|01000001|""); +\t\t$display(""*|%b|"", ""A""); +\t\t$display("">|01000001010000100100001101000100|""); +\t\t$display(""*|%b|"", ""ABCD""); +\t\t$display("">|01000001010000100100001101000100010010000100100101001010010010110100110001001101010011100100111101010000010100010101001001010011|""); +\t\t$display(""*|%b|"", ""ABCDHIJKLMNOPQRS""); + +\t\t$display("">|41|""); +\t\t$display(""*|%h|"", ""A""); +\t\t$display("">|41424344|""); +\t\t$display(""*|%h|"", ""ABCD""); +\t\t$display("">|4142434448494a4b4c4d4e4f50515253|""); +\t\t$display(""*|%h|"", ""ABCDHIJKLMNOPQRS""); +\tend +endmodule +" +"module top(); + reg pass = 1\'b1; + reg [31:0] in = \'bx; + reg signed [31:0] sin = \'bx; + wire [63:0] res, sres; + + lower lwr(res, in); + slower slwr(sres, sin); + + initial begin + #1; + if (res !== {32\'b0, 32\'bx}) begin + $display(""FAILED: unsigned output (%b)"", res); + pass = 1\'b0; + end + + if (lwr.lout !== {32\'b0, 32\'bx}) begin + $display(""FAILED: unsigned input (%b)"", lwr.lout); + pass = 1\'b0; + end + + if (sres !== 64\'bx) begin + $display(""FAILED: signed output (%b)"", sres); + pass = 1\'b0; + end + + if (slwr.lout !== 64\'bx) begin + $display(""FAILED: signed input (%b)"", slwr.lout); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule + +module lower(lrtn, lin); + output [31:0] lrtn; + input [63:0] lin; + + wire [63:0] lout = lin; + + assign lrtn = lout[31:0]; +endmodule + +module slower(lrtn, lin); + output signed [31:0] lrtn; + input [63:0] lin; + + wire [63:0] lout = lin; + + assign lrtn = lout[31:0]; +endmodule +" +"// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for dynamic arrays used as the function parameters and return type. + +module sv_darray_function(); +typedef logic[7:0] byte_array []; +typedef logic[3*8-1:0] byte_vector; + +function byte_array inc_array(byte_array inp); + byte_array tmp; + tmp = new[$size(inp)]; + + for(int i = 0; i < $size(inp); ++i) + begin + tmp[i] = inp[i] + 1; + end + + return tmp; +endfunction + +initial begin + byte_array a, b; + byte_vector c; + + a = new[3]; + a[0] = 10; + a[1] = 11; + a[2] = 12; + b = inc_array(a); + + if($size(a) != 3 || a[0] !== 10 || a[1] !== 11 || a[2] !== 12) begin + $display(""FAILED 1""); + $finish(); + end + + if($size(b) != 3 || b[0] !== 11 || b[1] !== 12 || b[2] !== 13) begin + $display(""FAILED 2""); + $finish(); + end + + // Cast dynamic array returned by function to logic vector + c = byte_vector\'(inc_array(b)); + if(c !== 24\'h0c0d0e) begin + $display(""FAILED 3""); + $finish(); + end + + $display(""PASSED""); +end +endmodule +" +"// +// Author: Pawel Szostek (pawel.szostek@cern.ch) +// Date: 01.08.2011 + +`timescale 1ns/1ps +module match_bits_v(input [7:0] a,b, output reg [7:0] match); + integer i; + wire ab_xor; + always @(a or b) begin + for (i=7; i>=0; i=i-1) begin + match[i] = ~(a[i]^b[i]); + end + end +endmodule + +module check(input [7:0] a,b,o_vhdl, o_verilog); + +always @(a or b) begin + #1 if (o_vhdl !== o_verilog) begin + $display(""ERROR!""); + $display(""VERILOG: "", o_verilog); + $display(""VHDL: "", o_vhdl); + $finish; + end +end +endmodule + +module stimulus (output reg [7:0] a,b); + parameter S = 20000; + int unsigned i,j,k,l; + initial begin //stimulate data + for (i=0; i= 10) + inject = 1\'b1; + else + inject = 1\'b0; + end + endfunction +endmodule + +module main; + wire [7:0] a,b,o_vhdl, o_verilog; + + match_bits match_vhdl(a,b,o_vhdl); + match_bits_v match_verilog(a,b,o_verilog); + stimulus stim(a,b); + check c(a,b,o_vhdl, o_verilog); +endmodule +" +"// Icarus doesn\'t properly support variable expressions on the right hand +// side of a procedural CA - see bug 605. + +module test(); + +reg [1:0] addr; +reg [3:0] memory[3:0]; +reg [3:0] data; + +initial begin + assign data = memory[addr]; + addr = 1; + memory[addr] = 2; + #0 $display(""%d"", data); + if (data === 2) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module test(); + +`define MACRO 1 +`define MACRO 1 +`define MACRO 2 +`undef MACRO +`define MACRO 1 + +endmodule +" +"module m; + + reg [15:8] r; + integer i; + +initial + begin + r = 8'b01101001; + for (i = 8; i <= 15; i = i + 1) + $display(r[i]); + end + +endmodule +" +"package my_package; + +parameter p1 = 1; +localparam p2 = p1 + 2; + +typedef logic [15:0] word; + +typedef struct packed { + word v; +} st; + +st s; + +event e; + +function word f(word g); + f = g + 1; +endfunction + +task h(word i); + s.v = s.v + i; + $display(s.v); +endtask + +endpackage + +module test(); + +import my_package::*; + +word my_v; + +initial begin + my_v = p1; + #1 ->e; +end + +initial begin + @e s.v = my_v; + h(f(1)); + if (p2 === 3 && s.v === 3) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate unary nor ~|(value) +// SJW - ~| in behavioral assignment to reg. + + +module main; + +reg [3:0] vect; +reg\terror; +reg\tresult; + + +initial + begin + error = 0; + for(vect=4\'b0001;vect<4\'b1111;vect = vect + 1) + begin + result = ~| vect; + if(result !== 1\'b0) + begin + $display(""FAILED - Unary nor ~|(%b)=%b"",vect,result); + error = 1\'b1; + end + end + #1; + vect = 4\'b0000; + result = ~| vect; + if(result !== 1\'b1) + begin + $display(""FAILED - Unary nor |~(%b)=%b"",vect,result); + error = 1\'b1; + end + if(error === 0 ) + $display(""PASSED""); + end + +endmodule // main +" +"module lvl3; + reg [1:0] m[1:0]; + initial begin +\tfork: my_fork +\t repeat (1) begin +\t\tm[0] = 2'b0; +\t end +\t repeat (1) begin +\t\tm[1] = 2'b1; +\t end +\tjoin + end +endmodule + + +module lvl2_0; + reg r; + initial r = $random; + lvl3 lvl3(); +endmodule + +module lvl1_0; + reg r; + function f_foo; +\tinput bar; + begin +\tf_foo = bar; + end + endfunction + initial r = f_foo(r); + lvl2_0 lvl2(); +endmodule + +module top0; + reg r; + task t_bar; +\tr = 1'b0; + endtask + initial begin: my_init +\tr = $random; +\tt_bar; + end + lvl1_0 lvl1(); +endmodule + + +module lvl2_1; + integer i; + initial i = $random; + lvl3 lvl3(); +endmodule + +module lvl1_1; + integer i; + initial i = $random; + lvl2_1 lvl2(); +endmodule + +module top1; + integer i; + initial i = $random; + lvl1_1 lvl1(); +endmodule + +module top2; + initial $test; +endmodule +" +"module test; + +reg signed [3:0] a; +reg signed [3:0] b; +reg [3:0] u; +reg [3:0] r; + +reg fail; + +initial begin + fail = 0; + a = 4\'b1000; + b = 4\'b0010; + u = 4\'b0001; + + r = ((a >>> 1) | b ) | u; + $display(""step 1 expected \'0111\', got \'%b\'"", r); + if (r !== 4\'b0111) fail = 1; + + r = ((4\'b1000 >>> 1) | b ) | u; + $display(""step 2 expected \'0111\', got \'%b\'"", r); + if (r !== 4\'b0111) fail = 1; + + r = ((a >>> 1) | 4\'b0010) | u; + $display(""step 3 expected \'0111\', got \'%b\'"", r); + if (r !== 4\'b0111) fail = 1; + + r = ((a >>> 1) | b ) | 4\'b0001; + $display(""step 4 expected \'0111\', got \'%b\'"", r); + if (r !== 4\'b0111) fail = 1; + + r = ((4\'b1000 >>> 1) | 4\'b0010) | u; + $display(""step 5 expected \'0111\', got \'%b\'"", r); + if (r !== 4\'b0111) fail = 1; + + r = ((a >>> 1) | 4\'b0010) | 4\'b0001; + $display(""step 6 expected \'0111\', got \'%b\'"", r); + if (r !== 4\'b0111) fail = 1; + + r = ((4\'b1000 >>> 1) | 4\'b0010) | 4\'b0001; + $display(""step 7 expected \'0111\', got \'%b\'"", r); + if (r !== 4\'b0111) fail = 1; + + if (fail) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module test(); + +wire [7:0] value1; +wire [15:0] value2; + +assign value1[3:0] = 4\'d2; + +assign value2 = {2{value1}}; + +initial begin + #2 $display(""%b %b"", value1, value2); + if (value2 === 16\'bzzzz0010zzzz0010) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"// Eleven basic tests in here: +// 1. int must be initialised before any initial or always block +// 2. assignments to (signed) int with random numbers +// 3. assignments to (signed) int with random values including X and Z +// 4. converting unsigned integers to signed int +// 5. converting signed integers to signed int +// 6. converting integers including X and Z states to signed int +// 7. trying signed sums (procedural, function, task and module) +// 8. trying signed mults (procedural, function and task) +// 9. trying relational operators +// 10. smaller signed numbers to signed int (signed extension) +// 11. trying some concatenations from bytes, shortints to ints + +module ms_add (input int signed a, b, output int signed sc, ss); + assign sc = a + b; + always @(a, b) ss = a + b; +endmodule + +module main; + parameter N_REPS = 500; // repetition with random numbers + parameter XZ_REPS = 500; // repetition with \'x \'z values + parameter UMAX = \'h7fff_ffff; + parameter MAX8 = \'h7f; + parameter MAX16 = \'h7fff; + parameter LEN = 32; + // variables used as golden references + reg signed [LEN-1:0] ar; // holds numbers + reg signed [LEN-1:0] ar_xz; // holds \'x and/or \'z in random positions + reg signed [LEN-1:0] ar_expected; + integer unsigned ui; + integer signed si; + reg signed [LEN/2-1:0] slice; + + // type assumed tested before + byte signed pt1, pt2; + shortint signed ps1, ps2; + + // types to be tested + int signed bu; // holds numbers + int signed bu_xz; // \'x and \'z are attempted on this + int signed bresult; // hold results from sums and mults + int signed mcaresult; // wired to a module instance + int signed mabresult; // also wired to a module instance + + + integer i; + + // continuous assigments + // type LHS type RHS + // --------- --------- + // int 4-value logic + assign bu = ar; + assign bu_xz = ar_xz; + + // module instantiation + ms_add duv (.a(bu), .b(bu_xz), .sc(mcaresult), .ss(mabresult) ); + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if (bu !== 32\'b0 || bu_xz !== 32\'b0 || bresult !== 32\'b0 || mcaresult !== 32\'b0 || mabresult !== 32\'b0) + begin + $display (""FAILED - time zero initialisation incorrect: %b %b"", bu, bu_xz); + $finish; + end + // driving int type with signed random numbers from a variable + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = $random; + #1; + if (bu !== ar) + begin + $display (""FAILED - incorrect assigment to int: %b"", bu); + $finish; + end + end + # 1; + // attempting to drive variables having \'x \'z values into type signed int + // \'x \'z injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + ar = $random; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0 + begin + $display (""FAILED - incorrect assigment to int (when \'x \'z): %b"", bu); + $finish; + end + end + // converting unsigned integers to signed int + // maintaining bit representation is expected + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ui = {$random}; + #1; + force bu = ui; + #1; + if (bu !== ui) + begin + $display (""FAILED - incorrect truncation from unsigned integer to int: %b"", bu); + $finish; + end + end + release bu; + // converting signed integers to signed ints + // bit representation should be maintained + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + si = $random; + #1; + force bu = si; + #1; + if (bu !== si) + begin + $display (""FAILED - incorrect assignment from signed integer to int: %b mismatchs %b"", bu, si); + $finish; + end + end + release bu; + // converting integers having \'x \'z values into type signed int + // \'x \'z injections (Section 4.3.2 of IEEE 1850 LRM) + // coercion to zero expected + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + si = $random; + ar_xz = xz_inject (si); + si = ar_xz; + ar_expected = xz_expected (ar_xz); + #1; + force bu_xz = si; + #1; + if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0 + begin + $display (""FAILED - incorrect conversion from integer (with \'x \'z) to int: %b mismatchs %b"", bu_xz, ar_expected); + $finish; + end + end + release bu_xz; + // trying signed sums + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = $random; + ar_xz = $random; + #1; + bresult = bu + bu_xz; + #1; + if ( bresult !== s_sum(ar, ar_xz) ) + begin + $display (""FAILED - incorrect addition of signed ints: %0d mismatchs %0d"", bresult, s_sum(ar, ar_xz)); + $finish; + end + // invoking shortint sum function + if ( fs_sum (bu, bu_xz) !== s_sum(ar, ar_xz) ) + begin + $display (""FAILED - incorrect addition of signed int in function""); + $finish; + end + // invoking byte sum task + ts_sum (bu, bu_xz, bresult); + if ( bresult !== s_sum(ar, ar_xz) ) + begin + $display (""FAILED - incorrect addition of signed int in task: %0d mismatchs %0d"", bresult, s_sum(ar, ar_xz)); + $finish; + end + // checking byte sum from module + if ( mcaresult !== s_sum(ar, ar_xz) || mabresult !== s_sum(ar, ar_xz)) + begin + $display (""FAILED - incorrect addition of signed int from module""); + $finish; + end + end + // trying signed mults + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = ($random % UMAX) << (LEN/2); + ar_xz = ($random % UMAX) << (LEN/2 - 1); + #1; + bresult = bu * bu_xz; // truncated multiplication + #1; + if ( bresult !== sh_mul(ar, ar_xz) ) + begin + $display (""FAILED - incorrect multiplication of signed ints (truncated)""); + $finish; + end + #1; + ps1 = $random % \'h7fff; + ps2 = $random % \'h7fff; + #1; + bresult = ps1 * ps2; // int = shorint x shortint + #1; + if ( bresult !== s_mul(ps1, ps2) ) + begin + $display (""FAILED - incorrect multiplication of signed shortints""); + $finish; + end + // invoking int mult function (shortint*shortint) + if ( fs_mul (ps1, ps2) !== s_mul(ps1, ps2) ) + begin + $display (""FAILED - incorrect product of signed shortint for a function returning signed int""); + $finish; + end + // invoking int mult task (shortint*shortint) + ts_mul (ps1, ps2, bresult); + if ( bresult !== s_mul(ps1, ps2) ) + begin + $display (""FAILED - incorrect product of signed shortint in task returning signed int""); + $finish; + end + end + // trying relational operators + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = $random; + ar_xz = $random; + #1; + if ( (bu < bu_xz ) !== (ar < ar_xz) ) + begin + $display (""FAILED - incorrect \'less than\' on signed ints""); + $finish; + end + if ( (bu <= bu_xz ) !== (ar <= ar_xz) ) + begin + $display (""FAILED - incorrect \'less than or equal\' on signed ints""); + $finish; + end + if ( (bu > bu_xz ) !== (ar > ar_xz) ) + begin + $display (""FAILED - incorrect \'greater than\' on signed ints""); + $finish; + end + if ( (bu >= bu_xz ) !== (ar >= ar_xz) ) + begin + $display (""FAILED - incorrect \'greater than or equal\' than on signed ints""); + $finish; + end + if ( (bu == bu_xz ) !== (ar == ar_xz) ) + begin + $display (""FAILED - incorrect \'equal to\' on signed ints""); + $finish; + end + if ( (bu != bu_xz ) !== (ar != ar_xz) ) + begin + $display (""FAILED - incorrect \'not equal to\' on signed ints""); + $finish; + end + end + # 1; + // signed small number to signed int + for (i = 0; i < (1< %0d"", $bits(foo)); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule +" +"`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module main; + + reg [7:0] foo; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + wire [3:0] below = foo[2:-1]; + wire [3:0] above = foo[8:5]; + wire [9:0] span = foo[8:-1]; +`else + wire [3:0] below = {foo[2:0], 1\'bx}; + wire [3:0] above = {1\'bx, foo[7:5]}; + wire [9:0] span = {1\'bx, foo[7:0], 1\'bx}; +`endif + + initial begin + foo = \'h55; + #1 ; + if (below !== 4\'b101_x) begin +\t $display(""FAILED""); +\t $finish; + end + if (above !== 4\'bx_010) begin +\t $display(""FAILED""); +\t $finish; + end + if (span !== 10\'bx_01010101_x) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""PASSED""); + end + +endmodule // main +" +"/********************************************************************** + * $my_monitor example -- Verilog HDL test bench. + * + * Verilog test bench to test the $my_monitor PLI application. + * + * For the book, ""The Verilog PLI Handbook"" by Stuart Sutherland + * Copyright 1999 & 2001, Kluwer Academic Publishers, Norwell, MA, USA + * Contact: www.wkap.il + * Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA + * Contact: www.sutherland-hdl.com + *********************************************************************/ +`timescale 1ns / 1ns +module test; + reg a, b, ci, clk; + wire sum, co; + + addbit i1 (a, b, ci, sum, co); + + initial + $my_monitor(i1); + + initial + begin + #0 a = 0; + #0 b = 0; + #0 ci = 0; + #10 a = 1; + #10 a = 0; + #10 b = 1; + #10 a = 1; + #10 $finish(0); + end + +endmodule + +/*** A gate level 1 bit adder model ***/ +`timescale 1ns / 1ns +module addbit (a, b, ci, sum, co); + input a, b, ci; + output sum, co; + + wire a, b, ci, sum, co, + n1, n2, n3; + +/* + assign n1 = a ^ b; + assign sum = n1 ^ ci; + assign n2 = a & b; + assign n3 = n1 & ci; + assign co = n2 | n3; +*/ + // Gate delays are used to ensure the signal changes occur in a + // defined order. + xor #1 (n1, a, b); + and #2 (n2, a, b); + and #3 (n3, n1, ci); + xor #4 (sum, n1, ci); + or #4 (co, n2, n3); + +endmodule +/*********************************************************************/ +" +"// +// Copyright (c) 1999 Steve Wilson (stevew@home.com) +// Based on code contributed by Peter Monta (pmonta@imedia.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +//\tSDW - Validate XOR op using non-blocking assignment +// + +module main; +reg [7:0] a; +reg b; +reg c; +reg error; + +initial + begin + #1; + error = 0; + for(a = 0; a <= 8\'h1; a = a + 1) + begin + b = 0; + #1 ; + if(a) + begin + if(!c) + begin + $display(""FAILED - XOR a=%b,b=%b,c=%b"",a,b,c); + error = 1; + end + end + if(!a) + begin + if(c) + begin + $display(""FAILED - XOR a=%b,b=%b,c=%b"",a,b,c); + error = 1; + end + end + b = 1; + #1 ; + if(!a) + begin + if(!c) + begin + $display(""FAILED - XOR a=%b,b=%b,c=%b"",a,b,c); + error = 1; + end + end + if(a) + begin + if(c) + begin + $display(""FAILED - XOR a=%b,b=%b,c=%b"",a,b,c); + error = 1; + end + end + end + if(!error) + $display(""PASSED""); + end + +always @(a or b) + c <= a ^ b; +endmodule +" +"module top (); + reg [31:0] din; + wire [31:0] dout; + + test t(din, dout); + + initial begin + din = 5; + #1; + $display(""dout=%d"", dout); + if (dout == 5) + $display(""PASSED""); + else + $display(""FAILED""); + end + +endmodule // top + +module test ( din, dout); + input [31:0] din; + output [31:0] dout; + buff #(1) d0_1 ( .in(din[0:0]), .out(dout[0:0])); + buff #(32) d0_32 ( .in(din[31:0]), .out(dout[31:0])); +endmodule // test + +module buff (out, in); + parameter SIZE=1; + output [SIZE-1:0] out; + input [SIZE-1:0] in; + assign out[SIZE-1:0] = in[SIZE-1:0]; +endmodule // buff +" +"// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for concurrent assertion statements. + +module vhdl_concurrent_assert_test; +vhdl_concurrent_assert dut(); +// we do not need anything else here +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue = # (mintypmax_expression) boolean_exp ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + begin + # 3; /* Wait till here to verify didn\'t see 2ns delay! */ + if(value1 !== 4\'hx) +\t$display(""FAILED - always reg_lvalue = # (mintypmax_expression) boolean_exp \ +""); + #12 ; + if(value1 != 4\'b1) +\t$display(""FAILED - always reg_lvalue = # (mintypmax_expression) boolean_exp \ +""); + else + begin + $display(""PASSED\ +""); + $finish ; + end + end + +always value1 = # (2:10:17) 1\'b1 && 1\'b1 ; + +endmodule +" +"module dut(a,); + + input wire a; + +endmodule + +module top; + + wire a; + + dut i(.*); + +endmodule +" +"/* + * Based on pr#859. + * This test makes sure the @* input search can handle null + * statements within case alternatives. + */ + +module test(output reg [15:0] probe_data,input wire [3:0] probe_sel); + + always @* + case(probe_sel) + 4\'h0 :; + default : probe_data = 16\'b0; + endcase // case(probe_sel) + + initial #1 $display(""PASSED""); + +endmodule // test +" +"// Copyright (c) 2000 Stephen Williams (steve@icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + + +/* + * This module implements what essentially amounts to an array of DFF + * devices with output enable. This test checks the operation of the + * bufif0 and bufif1 devices. + */ +module grayGap (ad, clk, read, write); + + output [31:0] ad; + input\t clk, read, write; + + reg [15:0] regff; + + bufif0 ad_drv [31:0] (ad, {16\'b0, regff}, read); + + always @(posedge clk) + if (write) regff = ad[15:0]; + + +endmodule + + +module main; + + wire [31:0] ad; + reg\t clk, read, write; + + reg [31:0] ad_val; + reg ad_en; + + bufif1 ad_drv[31:0] (ad, ad_val, ad_en); + + grayGap test (ad, clk, read, write); + + always #10 clk = ~clk; + + initial begin + clk = 1; + read = 1; + write = 0; + $monitor($time, ""ad=%b"", ad); + + // Set up to write a value into the grayGap register. + @(negedge clk) +\tad_val = 32\'haaaa_aaaa; + read = 1; + write = 1; + ad_en = 1; + + // The posedge has passed, now set up to read that value + // out. Turn all the drivers off for a moment, to see that the + // line becomes tri-state... + @(negedge clk) +\tad_en = 0; + write = 0; + + // Now read the value. + #1 read = 0; + + #1 $display(""Wrote %h, got %h"", ad_val, ad); + + if (ad !== 32\'b0000_0000_0000_0000_1010_1010_1010_1010) begin +\t $display(""FAILED -- ad is %b"", ad); +\t $finish; + end + + #2 read = 1; + + $display(""PASSED""); + $finish; + end + +endmodule // main +" +"/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* This tests the printing of a string constant. */ + +module main; + + initial + begin +\t$display(""%s"", ""PASSED""); + end + +endmodule // main +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// + +module main (); + + reg [7:0] array [7:0]; + reg\t error ; + reg [3:0] count; + + initial + begin + +\tfor(count = 0; count <= 7; count = count + 1) +\t begin +\t array[count] = 1 << count; +\t end + +\t$writememh(""work/writememh2.dat"", array, 6, 1); + +\tfor(count = 0; count <= 7; count = count + 1) +\t begin +\t array[count] = \'bx; +\t end + +\terror = 0; + +\t$readmemh(""work/writememh2.dat"", array); + +\tfor(count = 0; count <= 5; count = count + 1) +\t begin +\t if(array[count] !== (1<<(6-count))) + begin +\t\t error = 1; +\t\t $display(""FAILED - array[count] == %h, s/b %h"", +\t\t\t array[count], 1 << count); + end +\t end + +\tif(error == 0) +\t $display(""PASSED\ +""); +\t$finish ; + end +endmodule +" +"// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for expression concatenation in VHDL. + +module concat_test; +concat dut(); + +initial begin + #1; // wait for signal assignments + + if(dut.concat1 !== 2\'b10) + begin + $display(""FAILED: concat1 should be 10 but is %b"", dut.concat1); + $finish(); + end + + if(dut.concat2 !== 5\'b11010) + begin + $display(""FAILED: concat2 should be 11010 but is %b"", dut.concat2); + $finish(); + end + + $display(""PASSED""); +end +endmodule +" +"// This is a regression test for the bug fixed in patch tracker #1268. +module test(); + +reg [19:0] a[15:0]; + +reg [3:0] idx[3:1]; + +initial begin + idx[1] = 2; + idx[2] = 3; + idx[3] = 4; + a[idx[1]][idx[2]*4 +: 4] <= #(idx[3]) 4\'ha; + #4; + $display(""%h"", a[2]); + if (a[2] !== 20\'hxxxxx) begin + $display(""FAILED""); + $finish; + end + #1; + $display(""%h"", a[2]); + if (a[2] !== 20\'hxaxxx) begin + $display(""FAILED""); + $finish; + end + $display(""PASSED""); +end + +endmodule +" +"module top; + int bound = 2; + real q_real [$]; + real q_real1 [$:-1]; + real q_real2 [$:\'X]; + real q_real3 [$:bound]; + + initial begin + $display(q_real.size(1.0)); + $display(q_real.pop_front(1.0)); + $display(q_real.pop_back(1.0)); + q_real.push_front(1.0, 2.0); + q_real.push_back(1.0, 2.0); + $display(""FAILED""); + end +endmodule : top +" +"// This tests assigning value lists to packed structures +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test; + + typedef struct packed { + logic [7:0] high; + logic [7:0] low; + } word_t; + + // Declare word* as a VARIABLE + word_t word0, word1, word2, word3, word4, word5; + + // error counter + bit err = 0; + + // access to structure elements + assign word0 = \'{2, 3}; + assign word1 = \'{high:5, low:6}; + assign word2 = \'{low:7, high:8}; + assign word3 = \'{default:13}; + assign word4 = \'{high:8\'haa, default:1}; + assign word5 = \'{high:9\'h000, low:9\'h1ff}; + + initial begin + #1; + // check for correctness + if (word0 !== 16\'b00000010_00000011) begin $display(""FAILED -- word0 = \'b%b"", word0); err=1; end + if (word1 !== 16\'b00000101_00000110) begin $display(""FAILED -- word1 = \'b%b"", word1); err=1; end + if (word2 !== 16\'b00001000_00000111) begin $display(""FAILED -- word2 = \'b%b"", word2); err=1; end + if (word3 !== 16\'b00001101_00001101) begin $display(""FAILED -- word3 = \'b%b"", word3); err=1; end + if (word4 !== 16\'b10101010_00000001) begin $display(""FAILED -- word4 = \'b%b"", word4); err=1; end + if (word5 !== 16\'b00000000_11111111) begin $display(""FAILED -- word5 = \'b%b"", word5); err=1; end + + if (!err) $display(""PASSED""); + end + +endmodule // test +" +"module t(); + +wire [63:0] a; +wire [63:0] b; + +assign a = 3; + +am dut(a, b); + +initial +begin +\t#1; +\tif(b !== 2) +\t\t$display(""FAILED""); +\telse +\t\t$display(""PASSED""); +\t$finish; +end +endmodule + +module am( +\ta, b +); + +input [15:0] a; +output [15:0] b; + +assign b = a ^ 1; + +endmodule +" +"/* + * Copyright (c) 2000 Peter monta (pmonta@pacbell.net) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// Reworked slightly to be self checking. +module main; + + wire y; + reg a,b; + reg error; + + assign y = a && (b ? 0 : 1); + + initial + begin + error = 0; + #1 ; // get passed the time 0 race problems ;-) + b = 1; + a = 1; + #1 ; + if(y !== 0) + begin + $display(""FAILED""); + error = 1; + end + #1 ; + b = 0; + #1 ; + if(y !== 1) + begin + $display(""FAILED""); + error = 1; + end + if(error === 0) + $display(""PASSED""); + end + +endmodule +" +"module bug; + enum logic[1:0] { + RST[2], + IDLE, + ACTIVE + } state; + + initial begin + state = RST0; + #1 state = IDLE; // A non-blocking works, but IDLE is still a net + #1 state = ACTIVE; + #1 $display(""PASSED""); + end + + other other(state == IDLE); // This is treating IDLE as a net +endmodule + +module other(input logic val); + always @(val) $display(""%0t %b"", $time, val); +endmodule +" +"module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:0]; + +assign Array[0][0] = In[0]; +assign Array[0][7:1] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:1] = Array[0][N:1]; +end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Play with defines a bit +// + +`define NUM1 10 +`define NUM2 4\'b0001 +`define NUM3 4\'h4 +`define WIDTH 4 + +module define1 ; + +reg [`WIDTH-1:0] val ; +reg error; + +initial + begin + error = 0; + val = `NUM1 ; + if(val !== 10) + begin + error = 1; + $display(""FAILED - define NUM1 10 didn\'t""); + end + + val = `NUM2 ; + if(val !== 4\'h1) + begin + error = 1; + $display(""FAILED - define NUM1 10 didn\'t""); + end + val = `NUM3 ; + if(val !== 4\'b0100) + begin + error = 1; + $display(""FAILED - define NUM1 10 didn\'t""); + end + if(error == 0) + $display(""PASSED""); + end + +endmodule +" +"`timescale 1ns/100ps +module top; + reg in; + wire [3:0] vec; + wire [4:0] bvec; + wire real r_vec, r_arr, r_io; + + initial in <= 1'b0; + + // You cannot go to multiple real values (have multiple instances). + vec_to_real u1[1:0](r_vec, in); + + // A real port cannot be used in an arrayed instance. + arr_real u2a[1:0](bvec, in); + arr_real u2b[1:0](r_arr, in); + + // You cannot connect a real to an inout port. + io_vec_to_real u3(r_io, in); + + // You cannot have a inout port declared real. + io_real_to_vec u4(vec, in); + +endmodule + +module vec_to_real (output wire [3:0] out, input wire in); + reg [3:0] rval = 0; + assign out = rval; + always @(posedge in) rval = rval + 1; +endmodule + +module arr_real(output wire real out, input wire in); + real rval; + assign out = rval; + always @(posedge in) rval = rval + 1; +endmodule + +module io_vec_to_real(inout wire [3:0] out, input wire in); + reg [3:0] rval = 0; + assign out = rval; + always @(posedge in) rval = rval + 1; +endmodule + +module io_real_to_vec(inout wire real out, input wire in); + real rval; + assign out = rval; + always @(posedge in) rval = rval + 1; +endmodule +" +"module top; + reg passed; + int q[$]; + + initial begin + passed = 1\'b1; + q.push_front(10); + q.pop_back(); // This should emit a warning + if (q.size() != 0) begin + $display(""FAILED: pop_back() did not pop value when called as a task.""); + passed = 1\'b0; + end + + q.delete(); + q.push_front(20); + q.pop_front(); // This should emit a warning + if (q.size() != 0) begin + $display(""FAILED: pop_front() did not pop value when called as a task.""); + passed = 1\'b0; + end + + q.size(); + + if (passed) $display(""PASSED""); + end +endmodule +" +"// This test is intended to generate a IVL_LPM_SELECT_PV +// in the `b' port map + +module top; + + wire [7:0] foo; + + bot b( .q(foo[3:0]) ); + +endmodule // top + +module bot(q); + output [3:0] q; + +endmodule +" +"/* + * Hierarchical event testcase + * + * Copyright (C) 2002 Charles Lepple + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * compilation options: none necessary + */ + +`define TEST_HIERARCHICAL_EVENT +// yields parse error when defined + +module top(); + event toplevel_event; + + submodule sub(); + + initial #10 -> toplevel_event; +endmodule // top + +module submodule(); + event local_event; + + initial #25 -> local_event; + + always + begin +`ifdef TEST_HIERARCHICAL_EVENT +\t@(top.toplevel_event) +\t $display(""at %0d: toplevel event triggered"", $time); +`endif +\t@local_event +\t $display(""at %0d: local event triggered"", $time); + end +endmodule // submodule + +// local variables: +// verilog-simulator: ""iverilog"" +// end: +" +"/* + * This module instantiates the fa4 entity, which in turn + * instantiates other entities. This demonstrates hierarchical + * constructs in VHDL. + */ +module test; + +reg [3:0] a, b; +reg cin; + +wire [3:0] s; +wire cout; + +initial begin + cin = 0; + a = 4\'h2; + b = 4\'h3; +end + +initial begin + #1; + if (s !== 4\'h5) begin + $display(""Error in trivial sum""); + $finish; + end + $display (""PASSED""); +end + +fa4 duv (.c_i(cin), .va_i(a), .vb_i(b), .vs_o(s), .c_o(cout) ); + +endmodule // test +" +"/* + * This is based on PR#1029 + */ +module main(); + +`define none +`define fred eric +`define bill main`none.eric +reg [8*8:0] eric; +initial + begin + eric = ""PASSED""; + $display(""%0s"",`bill); + $finish ; + end + +endmodule +" +"// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +// Tests for various subprogram features (see the responding VHDL file for +// details). + +module subprogram_test; + subprogram dut(); + + initial begin + #1; // wait for signal assignment + + if(dut.negated !== \'b00111000) begin + $display(""FAILED 1""); + $finish; + end + + if(dut.reversed != \'b11100001) begin + $display(""FAILED 2""); + $finish; + end + + $display(""PASSED""); + end +endmodule +" +"`begin_keywords ""1364-2005"" +// Module to test the messages/results for out of bound R-value constant +// bit selects. + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + reg big_param; + reg bit; + + integer idx; + + parameter pvar0 = 0; + parameter pvar1 = 1; + parameter pvar2 = -1; + parameter pvar3 = 4\'b0001; + parameter [4:1] pvar4 = 4\'b0001; + parameter [1:4] pvar5 = 4\'b0001; + reg [4:1] rvar = 4\'b0010; + reg [1:4] rvar2 = 4\'b0010; + reg [4:1] ravar [2:1]; + reg [1:4] ravar2 [2:1]; + wire [4:1] wvar = 4\'b0100; + wire [1:4] wvar2 = 4\'b0100; + wire [4:1] wavar [2:1]; + wire [1:4] wavar2 [2:1]; + + assign wavar[1] = 4\'b1001; + assign wavar[2] = 4\'b1010; + assign wavar2[1] = 4\'b1001; + assign wavar2[2] = 4\'b1010; + + initial begin + pass = 1\'b1; + ravar[1] = 4\'b1101; + ravar[2] = 4\'b1110; + ravar2[1] = 4\'b1101; + ravar2[2] = 4\'b1110; + #1; + + // Icarus supports an unlimited size for unsized parameters. The + // following checks the 33rd bit to see if it is 1\'bx. If so we + // assume that the simulator only support 32 bit, otherwise we + // modify our after check for unsized parameters to work (pass) + // with a larger constant. + big_param = 1\'b1; + idx = 32; + if (pvar0[idx] === 1\'bx) big_param = 1\'b0; + + // Check a parameter with default size equal to 0. + bit = pvar0[31]; // At end + if (bit !== 1\'b0) begin + $display(""Failed at end bit select of a parameter (0), got %b"", bit); + pass = 1\'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = pvar0[32]; // May be after + if (bit !== (big_param ? 1\'b0: 1\'bx)) begin + $display(""Failed after bit select of a parameter (0), got %b"", bit); + pass = 1\'b0; + end + bit = pvar0[-1]; // Before + if (bit !== 1\'bx) begin + $display(""Failed before bit select of a parameter (0), got %b"", bit); + pass = 1\'b0; + end + bit = pvar0[1\'bx]; // Undefined + if (bit !== 1\'bx) begin + $display(""Failed undefined bit select of a parameter (0), got %b"", bit); + pass = 1\'b0; + end + bit = pvar0[1\'bz]; // High-Z + if (bit !== 1\'bx) begin + $display(""Failed high-Z bit select of a parameter (0), got %b"", bit); + pass = 1\'b0; + end +`endif + + // Check a parameter with default size equal to 1. + bit = pvar1[31]; // At end + if (bit !== 1\'b0) begin + $display(""Failed at end bit select of a parameter (1), got %b"", bit); + pass = 1\'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = pvar1[32]; // May be after + if (bit !== (big_param ? 1\'b0: 1\'bx)) begin + $display(""Failed after bit select of a parameter (1), got %b"", bit); + pass = 1\'b0; + end + bit = pvar1[-1]; // Before + if (bit !== 1\'bx) begin + $display(""Failed before bit select of a parameter (1), got %b"", bit); + pass = 1\'b0; + end + bit = pvar1[1\'bx]; // Undefined + if (bit !== 1\'bx) begin + $display(""Failed undefined bit select of a parameter (1), got %b"", bit); + pass = 1\'b0; + end + bit = pvar1[1\'bz]; // High-Z + if (bit !== 1\'bx) begin + $display(""Failed high-Z bit select of a parameter (1), got %b"", bit); + pass = 1\'b0; + end +`endif + + // Check a parameter with default size equal to -1. + bit = pvar2[31]; // At end + if (bit !== 1\'b1) begin + $display(""Failed at end bit select of a parameter (-1), got %b"", bit); + pass = 1\'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = pvar2[32]; // May be after + if (bit !== (big_param ? 1\'b1: 1\'bx)) begin + $display(""Failed after bit select of a parameter (-1), got %b"", bit); + pass = 1\'b0; + end + bit = pvar2[-1]; // Before + if (bit !== 1\'bx) begin + $display(""Failed before bit select of a parameter (-1), got %b"", bit); + pass = 1\'b0; + end + bit = pvar2[1\'bx]; // Undefined + if (bit !== 1\'bx) begin + $display(""Failed undefined bit select of a parameter (-1), got %b"", bit); + pass = 1\'b0; + end + bit = pvar2[1\'bz]; // High-Z + if (bit !== 1\'bx) begin + $display(""Failed high-Z bit select of a parameter (-1), got %b"", bit); + pass = 1\'b0; + end +`endif + + // Check a parameter with size four from the value. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = pvar3[4]; // After + if (bit !== 1\'bx) begin + $display(""Failed after bit select of a parameter (3), got %b"", bit); + pass = 1\'b0; + end + bit = pvar3[-1]; // Before + if (bit !== 1\'bx) begin + $display(""Failed before bit select of a parameter (3), got %b"", bit); + pass = 1\'b0; + end + bit = pvar3[1\'bx]; // Undefined + if (bit !== 1\'bx) begin + $display(""Failed undefined bit select of a parameter (3), got %b"", bit); + pass = 1\'b0; + end + bit = pvar3[1\'bz]; // High-Z + if (bit !== 1\'bx) begin + $display(""Failed high-Z bit select of a parameter (3), got %b"", bit); + pass = 1\'b0; + end +`endif + + // Check a parameter with size four from the range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = pvar4[5]; // After + if (bit !== 1\'bx) begin + $display(""Failed after bit select of a parameter (4), got %b"", bit); + pass = 1\'b0; + end + bit = pvar4[0]; // Before + if (bit !== 1\'bx) begin + $display(""Failed before bit select of a parameter (4), got %b"", bit); + pass = 1\'b0; + end + bit = pvar4[1\'bx]; // Undefined + if (bit !== 1\'bx) begin + $display(""Failed undefined bit select of a parameter (4), got %b"", bit); + pass = 1\'b0; + end + bit = pvar4[1\'bz]; // High-Z + if (bit !== 1\'bx) begin + $display(""Failed high-Z bit select of a parameter (4), got %b"", bit); + pass = 1\'b0; + end +`endif + + // Check a parameter with size four from the range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = pvar5[0]; // After + if (bit !== 1\'bx) begin + $display(""Failed after bit select of a parameter (5), got %b"", bit); + pass = 1\'b0; + end + bit = pvar5[5]; // Before + if (bit !== 1\'bx) begin + $display(""Failed before bit select of a parameter (5), got %b"", bit); + pass = 1\'b0; + end + bit = pvar5[1\'bx]; // Undefined + if (bit !== 1\'bx) begin + $display(""Failed undefined bit select of a parameter (5), got %b"", bit); + pass = 1\'b0; + end + bit = pvar5[1\'bz]; // High-Z + if (bit !== 1\'bx) begin + $display(""Failed high-Z bit select of a parameter (5), got %b"", bit); + pass = 1\'b0; + end +`endif + + + // Check a register with range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = rvar[5]; // After + if (bit !== 1\'bx) begin + $display(""Failed after bit select of a register, got %b"", bit); + pass = 1\'b0; + end + bit = rvar[0]; // Before + if (bit !== 1\'bx) begin + $display(""Failed before bit select of a register, got %b"", bit); + pass = 1\'b0; + end + bit = rvar[1\'bx]; // Undefined + if (bit !== 1\'bx) begin + $display(""Failed undefined bit select of a register, got %b"", bit); + pass = 1\'b0; + end + bit = rvar[1\'bz]; // High-Z + if (bit !== 1\'bx) begin + $display(""Failed high-Z bit select of a register, got %b"", bit); + pass = 1\'b0; + end +`endif + + // Check a register with range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = rvar2[0]; // After + if (bit !== 1\'bx) begin + $display(""Failed after bit select of a register (2), got %b"", bit); + pass = 1\'b0; + end + bit = rvar2[5]; // Before + if (bit !== 1\'bx) begin + $display(""Failed before bit select of a register (2), got %b"", bit); + pass = 1\'b0; + end + bit = rvar2[1\'bx]; // Undefined + if (bit !== 1\'bx) begin + $display(""Failed undefined bit select of a register (2), got %b"", bit); + pass = 1\'b0; + end + bit = rvar2[1\'bz]; // High-Z + if (bit !== 1\'bx) begin + $display(""Failed high-Z bit select of a register (2), got %b"", bit); + pass = 1\'b0; + end +`endif + + + // Check an array word with range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = ravar[1][5]; // After + if (bit !== 1\'bx) begin + $display(""Failed after bit select of an array word, got %b"", bit); + pass = 1\'b0; + end + bit = ravar[1][0]; // Before + if (bit !== 1\'bx) begin + $display(""Failed before bit select of an array word, got %b"", bit); + pass = 1\'b0; + end + bit = ravar[1][1\'bx]; // Undefined + if (bit !== 1\'bx) begin + $display(""Failed undefined bit select of an array word, got %b"", bit); + pass = 1\'b0; + end + bit = ravar[1][1\'bz]; // High-Z + if (bit !== 1\'bx) begin + $display(""Failed high-Z bit select of an array word, got %b"", bit); + pass = 1\'b0; + end +`endif + + // Check an array word with range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = ravar2[1][0]; // After + if (bit !== 1\'bx) begin + $display(""Failed after bit select of an array word (2), got %b"", bit); + pass = 1\'b0; + end + bit = ravar2[1][5]; // Before + if (bit !== 1\'bx) begin + $display(""Failed before bit select of an array word (2), got %b"", bit); + pass = 1\'b0; + end + bit = ravar2[1][1\'bx]; // Undefined + if (bit !== 1\'bx) begin + $display(""Failed undefined bit select of an array word (2), got %b"", bit); + pass = 1\'b0; + end + bit = ravar2[1][1\'bz]; // High-Z + if (bit !== 1\'bx) begin + $display(""Failed high-Z bit select of an array word (2), got %b"", bit); + pass = 1\'b0; + end +`endif + + + // Check a wire with range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = wvar[5]; // After + if (bit !== 1\'bx) begin + $display(""Failed after bit select of a wire, got %b"", bit); + pass = 1\'b0; + end + bit = wvar[0]; // Before + if (bit !== 1\'bx) begin + $display(""Failed before bit select of a wire, got %b"", bit); + pass = 1\'b0; + end + bit = wvar[1\'bx]; // Undefined + if (bit !== 1\'bx) begin + $display(""Failed undefined bit select of a wire, got %b"", bit); + pass = 1\'b0; + end + bit = wvar[1\'bz]; // High-Z + if (bit !== 1\'bx) begin + $display(""Failed high-Z bit select of a wire, got %b"", bit); + pass = 1\'b0; + end +`endif + + // Check a wire with range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = wvar2[0]; // After + if (bit !== 1\'bx) begin + $display(""Failed after bit select of a wire (2), got %b"", bit); + pass = 1\'b0; + end + bit = wvar2[5]; // Before + if (bit !== 1\'bx) begin + $display(""Failed before bit select of a wire (2), got %b"", bit); + pass = 1\'b0; + end + bit = wvar2[1\'bx]; // Undefined + if (bit !== 1\'bx) begin + $display(""Failed undefined bit select of a wire (2), got %b"", bit); + pass = 1\'b0; + end + bit = wvar2[1\'bz]; // High-Z + if (bit !== 1\'bx) begin + $display(""Failed high-Z bit select of a wire (2), got %b"", bit); + pass = 1\'b0; + end +`endif + + + // Check a wire array word with range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = wavar[1][5]; // After + if (bit !== 1\'bx) begin + $display(""Failed after bit select of a wire array word, got %b"", bit); + pass = 1\'b0; + end + bit = wavar[1][0]; // Before + if (bit !== 1\'bx) begin + $display(""Failed before bit select of a wire array word, got %b"", bit); + pass = 1\'b0; + end + bit = wavar[1][1\'bx]; // Undefined + if (bit !== 1\'bx) begin + $display(""Failed undefined bit select of a wire array word, got %b"", bit); + pass = 1\'b0; + end + bit = wavar[1][1\'bz]; // High-Z + if (bit !== 1\'bx) begin + $display(""Failed high-Z bit select of a wire array word, got %b"", bit); + pass = 1\'b0; + end +`endif + + // Check a wire array word with range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = wavar2[1][0]; // After + if (bit !== 1\'bx) begin + $display(""Failed after bit select of a wire array word (2), got %b"", bit); + pass = 1\'b0; + end + bit = wavar2[1][5]; // Before + if (bit !== 1\'bx) begin + $display(""Failed before bit select of a wire array word (2), got %b"", + bit); + pass = 1\'b0; + end + bit = wavar2[1][1\'bx]; // Undefined + if (bit !== 1\'bx) begin + $display(""Failed undefined bit select of a wire array word (2), got %b"", + bit); + pass = 1\'b0; + end + bit = wavar2[1][1\'bz]; // High-Z + if (bit !== 1\'bx) begin + $display(""Failed high-Z bit select of a wire array word (2), got %b"", + bit); + pass = 1\'b0; + end +`endif + + if (pass) $display(""PASSED""); + end +endmodule +`end_keywords +" +"`define DECLAREINT(name, i) integer name=i + +module foo(); + +`DECLAREINT(bar, 2); + +initial begin + if (bar === 2) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"/* + * This is the most basic test of string variables. + */ +module main; + + string foo = ""PASSED""; + + initial begin + $display(foo); + $finish; + end +endmodule // main +" +"module top; + + reg [2:0] bar = 1; + wire [3:0] foo; + + assign foo = { 1\'b1, 0 ? 3\'d0 : bar[2:0] }; + + initial begin + #1 if (foo !== 4\'b1001) begin +\t $display(""FAILED bar=%b, foo=%b"", bar, foo); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule +" +"/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * SDW: This test is a first expression test inside a parameter declaration. + */ +module test; + +parameter A0 = 2\'b10 & 2\'b11 ; + +initial + begin + if(A0 !== 2\'b10) + $display(""FAILED - A0 expression AND doesn\'t work.""); + else + $display(""PASSED""); + end + +endmodule +" +"module test; + + parameter some = 4; + wire [some-1:0] flag1; + + genvar i; + + generate + for (i = 0; i < some; i = i + 1) +\tbegin : what +\t wire [some-1:0] slice; +\tend + endgenerate + + generate + for (i = 0; i < some; i = i + 1) +\tbegin : ab +\t assign what[i].slice[i] = 1\'b1; +\t assign flag1[i] = &what[i].slice; +\tend + endgenerate + + integer\t idx; + initial #1 begin + for (idx = 0 ; idx < some ; idx = idx+1) begin +\t if (flag1[idx] !== 1\'bx) begin +\t $display(""FAILED -- flag1=%b"", flag1); +\t $finish; +\t end + end + $display(""PASSED""); + $finish; + end + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: readmemh function - Read less data than length of array +// +// + +module main (); + +reg [7:0] array [0:7]; +reg error ; +reg [3:0] count; + +initial + begin + error = 0; + + /* pre init the array to all zeroes. */ + for(count = 0; count <= 7; count = count + 1) + array[count] = 8\'h0; + + $readmemh(""ivltests/readmemh1.dat"",array,0,3); + + for(count = 0; count <= 3; count = count + 1) + begin + if(array[count[2:0]] !== count) + begin + error = 1; + $display(""FAILED - array[count] == %h, s/b %h"", + array[count],count); + end + end + + if(array[4] !== 8\'h0) + begin + error = 1; + $display(""FAILED - array[4] == %h, s/b 0"", + array[count]); + end + + if(error == 0) + $display(""PASSED\ +""); + $finish ; + end +endmodule +" +"module main; + + assign impl = 1; + wire expl = 1; + + genvar i; + for (i = 0; i < 4; i = i+1) begin : scope + test dut(.foo(impl), .bar(expl)); + end + +endmodule // main + +module test(input wire foo, bar); + + initial begin + #1 $display(""foo=%b, bar=%b"", foo, bar); + end +endmodule // test +" +"/////////////////////////////////////////////////////////////////////////// +// +// To test: +// (a) The use & representation of time variables +// (b) The display of time variables +// +// Compile and run the program +// iverilog tt_clean.v +// vvp a.out +// +// VISUALLY INSPECT the displays. (There ain\'t no way to automate this) +// +/////////////////////////////////////////////////////////////////////////// +`timescale 1 ns / 10 ps + +`define\tPCI_CLK_PERIOD\t\t15.0\t\t// 66 Mhz + +module top; + reg PCI_Clk; + reg fail; + + initial PCI_Clk <= 0; + always #(`PCI_CLK_PERIOD/2) PCI_Clk <= ~PCI_Clk; + + initial begin + fail = 0; + $display(""\ +\\t\\t==> CHECK THIS DISPLAY ==>\ +""); + $display(""pci_clk_period:\\t\\t\\t %0d"",`PCI_CLK_PERIOD); + $display(""pci_clk_period:\\t\\t\\t %0t"",`PCI_CLK_PERIOD); + if($time !== 0) fail = 1; + if (fail == 1) + $display(""$time=%0d (0)"", $time); + delay_pci(3); + if($simtime !== 4500) fail = 1; + if($time !== 45) fail = 1; + if (fail == 1) + $display(""$time=%0d (45)"", $time); + #15; + if($simtime !== 6000) fail = 1; + if($time !== 60) fail = 1; + #(`PCI_CLK_PERIOD); + if($simtime !== 7500) fail = 1; + if($time !== 75) fail = 1; + #(`PCI_CLK_PERIOD *2); + if($simtime !== 10500) fail = 1; + if($time !== 105) fail = 1; + + $timeformat(-9,2,""ns"",20); + $display(""after setting timeformat:""); + $display(""pci_clk_period:\\t\\t\\t %0d"",`PCI_CLK_PERIOD); + $display(""pci_clk_period:\\t\\t\\t %0t"",`PCI_CLK_PERIOD); + delay_pci(3); + if($simtime !== 15000) fail = 1; + if($time !== 150) fail = 1; + #15; + if($simtime !== 16500) fail = 1; + if($time !== 165) fail = 1; + #(`PCI_CLK_PERIOD); + if($simtime !== 18000) fail = 1; + if($time !== 180) fail = 1; + #(`PCI_CLK_PERIOD *2); + if($simtime !== 21000) fail = 1; + if($time !== 210) fail = 1; + + $display(""\\t\\t**********************************************""); + if(fail) $display(""\\t\\t****** time representation test BAD *******""); + else $display(""\\t\\t****** time representation test OK *******""); + $display(""\\t\\t**********************************************\ +""); + $finish(0); + end + + task delay_pci; + input delta; + integer delta; + integer ii; + begin + #(`PCI_CLK_PERIOD * delta); + end + endtask + +endmodule +" +"module top; + integer a; + + initial begin + a = 15'1; + a = 15'0; + a = 15'x; + a = 15'X; + a = 15'z; + a = 15'Z; + end +endmodule +" +"/* pr1634526.v */ + +module test; + initial begin + $display(""Working: This (%0d) should be 255."", minus1(256)); +// This crashes! + $display(""Broken: This (%0d) should be 255"", minus1(2**8)); +// And this gives the wrong result! + $display(""Broken: This (%0d) should be 255."", minus1(2**8-1+1)); + $display("" started with %0d."", 2**8-1+1); + $finish(0); + end + + function integer minus1; + input value; + integer value; + minus1 = value - 1; + endfunction +endmodule +" +"module automatic_error(); + +reg global; + +task automatic auto_task; + +reg local; + +begin:block + release local; +end + +endtask + +endmodule +" +"/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test checks that the upwards search for a name stops at a + * module boundary. In this example, the q variable in the instance + * ""inst"" of the test module should be an implicit wire, even though + * it is placed into the containing main scope that has a wire q in it. + */ + +module test(p); + output p; + + assign q = 1; // This should generate an error, q not defined + assign p = q; + +endmodule // test + +module main; + + wire q = 0; + wire sig; + test inst(sig); + + initial begin + #1 if (q !== 1\'b0) begin +\t $display(""FAILED -- main.q == %b"", q); +\t $finish; + end + + if (sig !== 1\'b1) begin +\t $display(""FAILED -- main.test.q == %b"", sig); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"/* pr1650842 */ + + module test; + + initial main; + + task main; + integer _$ID241, _$ID246, _$ID247, _$ID248, _$ID249, a; + begin +\t a = 0; +\t _$ID241 = a; +\t a = 9; +\t _$ID246 = a; +\t _$ID247 = 3; +\t a = _$ID247; +\t _$ID248 = _$ID246 + _$ID247 ; +\t _$ID249 = _$ID248; +\t a = _$ID249; +\t if( a !== 12 ) begin +\t $write(""FAIL: expected 12; got %d\ +"", a); +\t $display(""_$ID241=%d"", _$ID241); +\t $display(""_$ID246=%d"", _$ID246); +\t $display(""_$ID247=%d"", _$ID247); +\t $display(""_$ID248=%d"", _$ID248); +\t $display(""_$ID249=%d"", _$ID249); +\t end else begin +\t $write(""PASSED\ +""); +\t end + end + endtask + endmodule +" +"module test; + reg [1:0] r1, r2; + + initial begin +\tr1 = 2\'d2; +\tr2 = 2\'d0; + +\tif (r1 || r2) +\t $display(""PASSED""); +\telse +\t $display(""FAILED""); + +\tr1 = 2\'d2; +\tr2 = 2\'d1; +\tif (r1 && r2) +\t $display(""PASSED""); +\telse +\t $display(""FAILED""); + + end +endmodule +" +"module bug(); + +reg [0:-1][14:-1][6:-1] array; + +reg failed = 0; + +integer i; + +reg signed [4:0] index; + +initial begin + i = $bits(array); + $display(""width 0 = %0d"", i); + if (i !== 256) failed = 1; + + i = $bits(array[0]); + $display(""width 1 = %0d"", i); + if (i !== 128) failed = 1; + + i = $bits(array[0][0]); + $display(""width 2 = %0d"", i); + if (i !== 8) failed = 1; + + for (i = 0; i < 16; i++) begin + index = i[3:0]; + array[-1][-5\'sd1+index] = {4\'d0, index[3:0]}; + array[ 0][-5\'sd1+index] = {4\'d1, index[3:0]}; + end + $display(""%h"", array); + if (array !== 256\'h1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09080706050403020100) + failed = 1; + for (i = 0; i < 16; i++) begin + index = i[3:0]; + $display(""%h : %h %h"", index, array[-1][-5\'sd1+index], array[0][-5\'sd1+index]); + if (array[-1][-5\'sd1+index] !== {4\'d0, index[3:0]}) failed = 1; + if (array[ 0][-5\'sd1+index] !== {4\'d1, index[3:0]}) failed = 1; + end + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"// A very simple test to check continuous assignment +// of a constant +module main(); + wire p; + + assign p = 1; + + initial begin + #1; + if (p == 1) + $display(""PASSED""); + else + $display(""FAILED""); + end + +endmodule // main +" +"module top; + reg pass; + reg [5:0] cond; + reg [2:1] expr; + integer result; + + always @(cond or expr) begin + casex (cond) + 6\'b01_??10 : result = 1; + {2\'b10, 4\'b??10} : result = 2; + {expr, 4\'b??01} : result = 3; + {expr[2], 5\'b0??11} : result = 4; + {expr[2:1], 4\'b??11} : result = 5; + {expr, 4\'b??00} : result = 6; + default : result = 0; + endcase + end + + initial begin + pass = 1\'b1; + + cond = 6\'b01_xx10; + #1; + if (result != 1) begin + $display(""Failed case expr 1 test, got expr %0d"", result); + pass = 1\'b0; + end + + cond = 6\'b10_zz10; + #1; + if (result != 2) begin + $display(""Failed case expr 2 test, got expr %0d"", result); + pass = 1\'b0; + end + + expr = 2\'b1?; + cond = 6\'b1x_xx01; + #1; + if (result != 3) begin + $display(""Failed case expr 3 test, got expr %0d"", result); + pass = 1\'b0; + end + + expr = 2\'b0z; + cond = 6\'b00_xx11; + #1; + if (result != 4) begin + $display(""Failed case expr 4 test, got expr %0d"", result); + pass = 1\'b0; + end + + expr = 2\'b?1; + cond = 6\'bx1_xx11; + #1; + if (result != 5) begin + $display(""Failed case expr 5 test, got expr %0d"", result); + pass = 1\'b0; + end + + expr = 2\'b11; + cond = 6\'b11_xx00; + #1; + if (result != 6) begin + $display(""Failed case expr 6 test, got expr %0d"", result); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module top; + reg ctl, in0, in1; + wire out3, out4; + + // A UDP can only take two delay values. + mux2 #(10, 20, 30) q1(out3, ctl, in0, in1); + mux2 #(10, 20, 30, 40) q2(out4, ctl, in0, in1); + + initial $display(""FAILED""); +endmodule + +primitive mux2 (out, ctl, in0, in1); + output out; + input ctl, in0, in1; + + table + 0 0 ? : 0; + 0 1 ? : 1; + 1 ? 0 : 0; + 1 ? 1 : 1; + x 0 0 : 0; + x 1 1 : 1; + endtable +endprimitive +" +"/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test tests simple zero-extend of small r-values into large + * l-values. + * + * Correction and extensions by EML; 2007-11-15 + */ +module main; + + reg [3:0] y; + reg signed xs; + reg\t x; + reg\t fail; + + initial begin + fail = 0; + x = 1\'b0; + y = x; + if (y !== 4\'b0000) begin +\t $display(""FAILED 1 -- x=%b, y=%b"", x, y); +\t fail = 1; + end + + x = 1\'b1; + y = x; + if (y !== 4\'b0001) begin +\t $display(""FAILED 2 -- x=%b, y=%b"", x, y); +\t fail = 1; + end + + // x is a 1-bit unsigned reg; it zero-extends when assigned to y + x = 1\'bx; + y = x; + if (y !== 4\'b000x) begin +\t $display(""FAILED 3 -- x=%b, y=%b"", x, y); +\t fail = 1; + end + + // x is a 1-bit unsigned reg; it zero-extends when assigned to y + x = 1\'bz; + y = x; + if (y !== 4\'b000z) begin +\t $display(""FAILED 4 -- x=%b, y=%b"", x, y); +\t fail = 1; + end + + // xs is a 1-bit signed reg; it top-bit-extends when assigned to y + xs = 1\'bx; + y = xs; + if (y !== 4\'bxxxx) begin +\t $display(""FAILED 5 -- xs=%b, y=%b"", xs, y); +\t fail = 1; + end + + // xs is a 1-bit signed reg; it top-bit-extends when assigned to y + xs = 1\'bz; + y = xs; + if (y !== 4\'bzzzz) begin +\t $display(""FAILED 6 -- xs=%b, y=%b"", xs, y); +\t fail = 1; + end + + // \'bx is an unsized unsigned constant; it X-extends to the size of + // the expression it is in + y = \'bx; + if (y !== 4\'bxxxx) begin +\t $display(""FAILED 7 -- y=%b"", y); +\t fail = 1; + end + + // \'bz is an unsized unsigned constant; it Z-extends to the size of + // the expression it is in + y = \'bz; + if (y !== 4\'bzzzz) begin +\t $display(""FAILED 8 -- y=%b"", y); +\t fail = 1; + end + + // this is the only case in which a constant pads to the left with + // X\'s. 4\'bx is 4-bit unsigned, but it is specified with fewer than 4 + // bits + y = 4\'bx; + if (y !== 4\'bxxxx) begin +\t $display(""FAILED 9 -- y=%b"", y); +\t fail = 1; + end + + // this is the only case in which a constant pads to the left with + // Z\'s. 4\'bz is 4-bit unsigned, but it is specified with fewer than 4 + // bits + y = 4\'bz; + if (y !== 4\'bzzzz) begin +\t $display(""FAILED 10 -- y=%b"", y); +\t fail = 1; + end + + if (!fail) $display(""PASSED""); + end // initial begin + +endmodule // main +" +"module test; + bit [7:0] i, x[], y[], z[]; + + + initial begin + x = new [4]; + + for (i = 0; i < 4; i = i + 1) x[i] = 1 + i; + y = x; + z = new [4](x); + for (i = 0; i < 4; i = i + 1) y[i] = 4 - i; + for (i = 0; i < 4; i = i + 1) z[i] = 8 - i; + // Expected output: + // 1 2 3 4 + // 4 3 2 1 + // 8 7 6 5 + $display(x[0],,x[1],,x[2],,x[3]); + $display(y[0],,y[1],,y[2],,y[3]); + $display(z[0],,z[1],,z[2],,z[3]); + end + +endmodule +" +"/* + * This is based on PR#1026. + */ +module main; + + reg [4:0] index; + reg [31:0] foo; + + initial begin + for (index = 0 ; index < 31 ; index = index + 1) begin +\t #1 $display(""index=%d, foo=%b"", index, foo); + end + $finish(0); + end + + always @(*) + begin +\tfoo = 32\'b0; +\tfoo[index]=1\'b1; + end +endmodule +" +"/* )* */ +/* (* /* *) */ +module test(); +initial $display(""PASSED""); +endmodule +" +"function int hello(int a); + begin + $display(""hello from unit 1""); + hello = a; + end +endfunction + + +task hello1; + begin + $display(""hello1 from unit 1""); + end +endtask + + +task hello2; + begin + $display(""hello2 from unit 1""); + end +endtask + + +task hello3; + begin + $display(""hello3 from unit 1""); + end +endtask + + +class c1; + + task hello2; + begin + hello1; + $display(""hello2 from c1""); + end + endtask + +endclass + + +module m1(); + + int i; + + c1 obj; + + initial begin + #1; + i = $unit::hello(1); + obj = new; + obj.hello2; + hello1; + hello2; + hello3; + hello4; + end + + task hello2; + begin + $display(""hello2 from m1""); + end + endtask + +endmodule + + +module m2(); + + m1 m1inst(); + + task hello1; + begin + $display(""hello1 from m2""); + end + endtask + + task hello2; + begin + $display(""hello2 from m2""); + end + endtask + + task hello3; + begin + $display(""hello3 from m2""); + end + endtask + + task hello4; + begin + $display(""hello4 from m2""); + end + endtask + +endmodule +" +"/* + */ +module main; + + reg [1:0] sel, in; + reg [1:0] out; + + (* ivl_combinational *) + always @* + (* ivl_full_case *) case (sel) + 2\'b01: out = 2\'b10; + 2\'b10: out = in[0]; + 2\'b11: out = in[1]; + endcase // casex(sel) + + (* ivl_synthesis_off *) + initial begin + in = 2\'b10; + + sel = 1; + #1 if (out !== 2\'b10) begin +\t $display(""FAILED -- sel=%b, out=%b"", sel, out); +\t $finish; + end + + sel = 2; + #1 if (out !== 2\'b00) begin +\t $display(""FAILED -- sel=%b, in=%b, out=%b"", sel, in, out); +\t $finish; + end + + sel = 3; + #1 if (out !== 2\'b01) begin +\t $display(""FAILED -- sel=%b, in=%b, out=%b"", sel, in, out); +\t $finish; + end + + $display(""PASSED""); + end +endmodule // main +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW: Instantiation of Modules: +// +// D: Instantiate two versions of a module containing a single +// D: resetable f/f. Reset both - then feed 1 module with a clock +// D: and validate that the output toggles. Feed the 2nd module +// D: with a clock and validate that the 2nd output toggles. +// +// + +module test_mod (reset,clka,out); +input reset; +input clka; +output out; + +reg out; + +always @(posedge clka or posedge reset) + if(reset) + out = 0; + else + begin + out = ~out; + $display(""saw a clk at %d, out is %b\ +"",$time,out); + end + +endmodule + +module main(); + +reg reset,clk_0,clk_1; +wire out_0,out_1; + +test_mod module_1 (reset,clk_0,out_0); +test_mod module_2 (reset,clk_1,out_1); + +initial + begin + clk_0 = 0; + clk_1 = 0; + #1 reset = 1; + # 2; + $display(""time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\ +"",$time,reset,clk_0, + clk_1,out_0,out_1); + // Validate that both out_0 and out_1 are reset + if(out_0) + begin + $display(""FAILED - out_0 not reset\ +""); + $finish ; + end + + if(out_1) + begin + $display(""FAILED - out_1 not reset\ +""); + $finish ; + end + reset = 0; + $display(""time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\ +"",$time,reset,clk_0, + clk_1,out_0,out_1); + # 2; + clk_0 = 1; + # 2; // Wait so we don\'t worry about races. + $display(""time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\ +"",$time,reset,clk_0, + clk_1,out_0,out_1); + if(!out_0) + begin + $display(""FAILED - out_0 didn\'t set on clk_0\ +""); + $finish ; + end + + if(out_1) + begin + $display(""FAILED - out_1 set on wrong clk!\ +""); + $finish ; + end + + clk_1 = 1; + # 2; // Wait so we don\'t worry about races. + $display(""time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\ +"",$time,reset,clk_0, + clk_1,out_0,out_1); + if(!out_1) + begin + $display(""FAILED - out_1 didn\'t set on clk_1\ +""); + $finish ; + end + + if(!out_0) + begin + $display(""FAILED - out_0 changed due to clk_0\ +""); + $finish ; + end + + + $display(""PASSED\ +""); + $finish ; + end +endmodule +" +" +/* + * This tests a trivial class. In SystemVerilong, classes are garbage + * collected dynamic objects, so this tests the creation of class objects, + * some simple manipulations, copying (by reference) and cleanup. + */ + +// Trivial example of a class + +program main; + + class base_t; + int x; + int y; + endclass : base_t + + class foo_t; + int a; + int b; + base_t base = new ( ); + endclass : foo_t + + foo_t obj, copy; + + initial begin + obj = new; + + if (obj == null) begin +\t $display(""FAILED -- After allocation, object is NOT null.""); +\t $finish; + end + + // This is the most trivial assignment of class properties. + obj.a = 10; + obj.b = 11; + obj.base.x = 12; + obj.base.y = 13; + + if (obj.a != 10 || obj.b != 11) begin +\t $display(""FAILED -- assign to object: obj.a=%0d, obj.b=%0d"", obj.a, obj.b); +\t $finish; + end + + // This actually makes a shared link to the same object. This + // will make a link to the object. + copy = obj; + + if (copy.a != 10 || copy.b != 11) begin +\t $display(""FAILED -- copy object: copy.a=%0d, copy.b=%0d"", copy.a, copy.b); +\t $finish; + end + + copy.a = 7; + copy.b = 8; + + if (obj.a != 7 || obj.b != 8) begin +\t $display(""FAILED -- check shared-ness: obj.a=%0d, obj.b=%0d"", obj.a, obj.b); +\t $finish; + end + + // Clear the copy pointer. obj still exists, though. + copy = null; + if (obj.a != 7 || obj.b != 8) begin +\t $display(""FAILED -- clear copy preserved link: obj.a=%0d, obj.b=%0d"", obj.a, obj.b); +\t $finish; + end + + // This is the last reference to the class, so it should cause + // the object to be destroyed. How to test that? + obj = null; + + $display(""PASSED""); + $finish; + end +endprogram // main +" +"module stimulus (output reg A, B); + + initial begin + // both inputs are x + #0 {A, B} = 2\'bxx; + // both inputs are z + #10 {A, B} = 2\'bzz; + // one input is a zero + #10 {A, B} = 2\'b0x; + #10 {A, B} = 2\'bx0; + #10 {A, B} = 2\'b0z; + #10 {A, B} = 2\'bz0; + // one input is a one + #10 {A, B} = 2\'b1x; + #10 {A, B} = 2\'bx1; + #10 {A, B} = 2\'b1z; + #10 {A, B} = 2\'bz1; + // normal bit operands + #10 {A, B} = 2\'b00; + #10 {A, B} = 2\'b01; + #10 {A, B} = 2\'b10; + #10 {A, B} = 2\'b11; + end + +endmodule + +module scoreboard (input Y, A, B); + +function truth_table (input a, b); + reg [1:0] gate_operand; + reg gate_output; + begin + gate_operand[1:0] = {a, b}; + case (gate_operand) + // both inputs are x + 2\'bxx: gate_output = 1\'bx; + // both inputs are z + 2\'bzz: gate_output = 1\'bx; + // output should be one (one input is a zero) + 2\'b0x: gate_output = 1; + 2\'bx0: gate_output = 1; + 2\'b0z: gate_output = 1; + 2\'bz0: gate_output = 1; + // output is x (one input is a one) + 2\'b1x: gate_output = 1\'bx; + 2\'bx1: gate_output = 1\'bx; + 2\'b1z: gate_output = 1\'bx; + 2\'bz1: gate_output = 1\'bx; + // inputs x, z + 2\'bxz: gate_output = 1\'bx; + 2\'bzx: gate_output = 1\'bx; + // normal operation on bit + 2\'b00: gate_output = 1; + 2\'b01: gate_output = 1; + 2\'b10: gate_output = 1; + 2\'b11: gate_output = 0; + endcase + + truth_table = gate_output; + end +endfunction + + +reg Y_t; + +always @(A or B) begin + Y_t = truth_table (A, B); + #1; + //$display (""a = %b, b = %b, Y_s = %b, Y = %b"", A, B, Y_s, Y); + if (Y_t !== Y) begin + $display(""FAILED! - mismatch found for inputs %b and %b in NAND operation"", A, B); + $finish; + end +end + +endmodule + +module test; + stimulus stim (A, B); + nand_gate duv (.a_i(A), .b_i(B), .c_o(Y) ); + scoreboard mon (Y, A, B); + + initial begin + #200; + $display(""PASSED""); + $finish; + end + +endmodule +" +"module main; + + real x; + real y; + + real bar; + + initial begin + x = 5.0; + y = 10.0; + bar = x % y; + $display(""bar=%f"", bar); + + if (bar != 5.0) begin +\t $display(""FAILED -- x %% y --> %f (s.b. 5.0)"", bar); +\t $finish; + end + + $display(""PASSED""); + end +endmodule // main +" +" +class test_t; + typedef enum bit [1:0] { U, V } uv_t; + uv_t foo; + + task go; + foo = U; + $display(""test_t.foo=%b (U==0)"", foo); + if (foo !== U) begin +\t $display(""FAILED""); +\t $finish; + end + foo = V; + $display(""test_t.foo=%b (V==1)"", foo); + if (foo !== V) begin +\t $display(""FAILED""); +\t $finish; + end + endtask +endclass // test_t + +module main; + typedef enum bit [1:0] { X, Y } xy_t; + xy_t foo; + + initial begin + foo = Y; + $display(""foo=%b (Y==1)"", foo); + if (foo !== Y) begin +\t $display(""FAILED""); +\t $finish; + end + foo = X; + $display(""foo=%b (X==0)"", foo); + if (foo !== X) begin +\t $display(""FAILED""); +\t $finish; + end + end + + test_t bar; + initial begin + bar = new; + bar.go(); + end + + initial begin + #1 $display(""PASSED""); + $finish; + end + +endmodule // main +" +"module stimulus (output reg A, B); + + initial begin + // both inputs are x + #0 {A, B} = 2\'bxx; + // both inputs are z + #10 {A, B} = 2\'bzz; + // one input is a zero + #10 {A, B} = 2\'b0x; + #10 {A, B} = 2\'bx0; + #10 {A, B} = 2\'b0z; + #10 {A, B} = 2\'bz0; + // one input is a one + #10 {A, B} = 2\'b1x; + #10 {A, B} = 2\'bx1; + #10 {A, B} = 2\'b1z; + #10 {A, B} = 2\'bz1; + // one input x, other z + #10 {A, B} = 2\'bxz; + #10 {A, B} = 2\'bzx; + // normal bit operands + #10 {A, B} = 2\'b00; + #10 {A, B} = 2\'b01; + #10 {A, B} = 2\'b10; + #10 {A, B} = 2\'b11; + end + +endmodule + +module scoreboard (input Y, A, B); + +function truth_table (input a, b); + reg [1:0] gate_operand; + reg gate_output; + begin + gate_operand[1:0] = {a, b}; + case (gate_operand) + // both inputs are x + 2\'bxx: gate_output = 1\'bx; + // both inputs are z + 2\'bzz: gate_output = 1\'bx; + // output should be one (one input is a one) + 2\'b1x: gate_output = 1; + 2\'bx1: gate_output = 1; + 2\'b1z: gate_output = 1; + 2\'bz1: gate_output = 1; + // output is x (one input is a zero) + 2\'b0x: gate_output = 1\'bx; + 2\'bx0: gate_output = 1\'bx; + 2\'b0z: gate_output = 1\'bx; + 2\'bz0: gate_output = 1\'bx; + // inputs x, z + 2\'bxz: gate_output = 1\'bx; + 2\'bzx: gate_output = 1\'bx; + // normal operation on bit + 2\'b00: gate_output = 0; + 2\'b01: gate_output = 1; + 2\'b10: gate_output = 1; + 2\'b11: gate_output = 1; + endcase + + truth_table = gate_output; + end +endfunction + + +reg Y_t; + +always @(A or B) begin + Y_t = truth_table (A, B); + #1; + //$display (""a = %b, b = %b, Y_s = %b, Y = %b"", A, B, Y_s, Y); + if (Y_t !== Y) begin + $display(""FAILED! - mismatch found for inputs %b and %b in OR operation"", A, B); + $finish; + end +end + +endmodule + +module test; + stimulus stim (A, B); + or_gate duv (.a_i(A), .b_i(B), .c_o(Y) ); + scoreboard mon (Y, A, B); + + initial begin + #200; + $display(""PASSED""); + $finish; + end + +endmodule +" +"module main; + + reg [4:0] src; + wire dst; + + test dut(.i(src[3:0]), .o(dst)); + + initial begin + for (src = 0 ; src < 16 ; src = src+1) begin +\t #1 if (dst !== & src[3:0]) begin +\t $display(""FAILED: src=%b, dst=%b"", src, dst); +\t $finish; +\t end + end + + $display(""PASSED""); + end + +endmodule // main +" +"// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for casting a string to a vector type. + +module sv_cast_string(); + string str; + typedef logic [55:0] strbits; + strbits chars; + + initial begin + int i; + str = ""0123456""; + chars = strbits\'(str); + if(chars != 56\'h30313233343536) + begin + $display(""FAILED 1 chars = %x"", chars); + $finish(); + end + + str = ""6543210""; + chars = strbits\'(str); + if(chars != ""6543210"") + begin + $display(""FAILED 2 chars = %x"", chars); + $finish(); + end + + str = ""wrong string""; + // Vector to string casting + str = string\'(chars); + if(str != ""6543210"") + begin + $display(""FAILED 3 str = %s"", str); + $finish(); + end + + $display(""PASSED""); +end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate casex/endcase - label w/ X no default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 or val2) + casex (val1 & val2 ) + 3\'b000: result = 0; + 3\'b0x1: result = 1 ; + 3\'b010: result = 2; + endcase + +initial + begin + error = 0; + + val1 = 3\'b0; + val2 = 3\'b0; + if(result !=0) + begin + $display(""FAILED casex 3.9C - label w/ x: ""); + error = 1; + end + + val1 = 3\'b001; + val2 = 3\'b011; + if(result !=1) + begin + $display(""FAILED casex 3.9C - label w/ x: ""); + error = 1; + end + + + val1 = 3\'b111;\t// Should get no-action - expr = 3\'b011 + if(result !=1) + begin + $display(""FAILED casex 3.9C - label w/ x ""); + error = 1; + end + + if(error == 0) + $display(""PASSED""); + end + +endmodule // main +" +"module test; + + function f_0; + input i; + begin +\t f_0 = f_1(i); + end + endfunction + + function f_1; + input i; + begin +\t f_1 = !i; + end + endfunction + + wire w = f_0(1\'b0); + + initial begin +\t#1; +\tif ( w !== 1\'b1) +\t $display (""FAILED w (%b) !== 1\'b1"", w); +\telse +\t $display (""PASSED""); + end +endmodule +" +"module test; + +wire real array[1:0]; + +reg [7:0] index; + +real value; + +initial begin + index = 3; + value = array[index]; + if (value == 0.0) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"// This tests SystemVerilog packages +// +// This tests the elaboration infrastructure of packages in +// SystemVerilog. It actually covers a fair number of features, +// given the small size of the program: +// +// *) Parsing of package blocks and import statements +// *) Manage scope of names in package +// *) Actual references of imported names from packages. +// + +package pkg; + parameter int foo = 1; +endpackage + + +module test (); + + // import all from p1 + //import pkg::foo; + + initial begin + $display(""pkg::foo = %0d"", pkg::foo); + if (pkg::foo != 1) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""PASSED""); + end + +endmodule // test +" +"module ge8(output wire out, input wire [7:0] A, input wire [7:0] B); + + assign out = A >= B; + +endmodule +" +"class my_class; + task run_test(); + $display(""PASSED""); + endtask +endclass + +class extended_class extends my_class; +endclass + +module test(); + +extended_class obj; + +initial begin + obj = new(); + obj.run_test(); +end + +endmodule +" +"// This slightly convoluted module used to cause an argument-size +// mismatch in the call to the function extend_data + +module test (c); + + parameter MAX_SIZE = 32; + + input\t\t\tc; + + reg\t[MAX_SIZE-1:0]\td, +\t\t\te, +\t\t\tf; + reg\t[7:0]\t\tg; + + wire\t\t\th; + + always @(posedge h or negedge c) + if (~c) + f <= #2 {MAX_SIZE{1'b0}}; + else + case (g) + 8'h18 : + f <= #2 hw(d, e); + default : + f <= #2 {MAX_SIZE{1'b0}}; + endcase + + parameter FALSE_RESULT = {MAX_SIZE{1'b0}}, +\t TRUE_RESULT = FALSE_RESULT | 1'b1; + + function integer sign_of; + + input\t[2*MAX_SIZE-1:0]\tdata; + input\t\t\t\tsize; + + reg\t[2*MAX_SIZE-1:0]\tdata; + integer\t\t\tsize; + + if (data[size-1]===1'b1) + sign_of = -1; + else + sign_of = 1; + endfunction + + function [2*MAX_SIZE-1:0] extend_data; + + input\t[2*MAX_SIZE-1:0]\tdata; + input\t\t\t\tsize; + input\t\t\t\tnew_size; + input\t\t\t\textend; + + reg\t[2*MAX_SIZE-1:0]\tdata; + integer\t\t\tsize, +\t\t\t\tnew_size; + reg\t\t\t\textend; + + for (extend_data = data ; new_size-size>0 ; new_size=new_size-1) + extend_data[new_size-1] = extend & data[size-1]; + endfunction + + function [MAX_SIZE-1:0] hw; + input\t[MAX_SIZE-1:0]\t\ta; + input\t[MAX_SIZE-1:0]\t\tb; + + reg\t[MAX_SIZE-1:0]\t\ta, +\t\t\t\tb; + + reg\t[MAX_SIZE:0]\t\tdiff; + + begin + diff = extend_data(b, MAX_SIZE, MAX_SIZE+1, 1'b1) - + extend_data(a, MAX_SIZE, MAX_SIZE+1, 1'b1); + if (sign_of(diff, MAX_SIZE+1)==-1) + hw = TRUE_RESULT; + else + hw = FALSE_RESULT; + end + endfunction + +endmodule +" +"// Icarus 0.6, snapshot 20020907 +// ================================================== +// -- confused by disables from within a fork -- vvp fails +// +// -- to run, incant +// iverilog tt.v +// vvp a.out +// +// Veriwell +// ======== +// -- OK +// +module top; + + integer simple_fail, loop_fail, fork_fail, tlp_fail; + integer tfk_fail, tfk2_fail, tfk3_fail; + integer tfk2pos, tfk2nega, tfk2negb; + integer tfk3pos, tfk3nega, tfk3negb; + integer loop_cntr, tlp_cntr; + reg fred, abort; + + initial begin + #1; + simple_fail = 0; + loop_fail = 0; + fork_fail = 0; + tlp_fail = 0; + tfk_fail = 0; + tfk2_fail = 0; + tfk2pos = 0; + tfk2nega = 1; + tfk2negb = 1; + tfk3pos = 0; + tfk3nega = 1; + tfk3negb = 1; + fred = 0; + abort = 1; + #4; + fred = 1; + #4 + $display(""Check disable:""); + if(simple_fail) $display(""***** simple block FAILED *****""); + else $display(""***** simple block PASSED *****""); + if(loop_fail) $display(""***** block with loop FAILED *****""); + else $display(""***** block with loop PASSED *****""); + if(fork_fail) $display(""***** forked block FAILED *****""); + else $display(""***** forked block PASSED *****""); + if(tlp_fail) $display(""***** task with loop FAILED *****""); + else $display(""***** task with loop PASSED *****""); + if(tfk_fail) $display(""***** task with forked block FAILED *****""); + else $display(""***** task with forked block PASSED *****""); + if(tfk2_fail) $display(""***** one forked block FAILED *****""); + else $display(""***** one forked block PASSED *****""); + if(tfk3_fail) $display(""***** the other forked block FAILED *****""); + else $display(""***** the other forked block PASSED *****""); + $display(""""); + $finish(0); + end + + // simple block disable + initial begin: block_name + #2; + disable block_name; + simple_fail = 1; + end + + // more complex: block disable inside for-loop + initial begin + #2; + begin: configloop + for (loop_cntr = 0; loop_cntr < 3; loop_cntr=loop_cntr+1) begin +\twait (fred); +\tif (abort) begin +\t disable configloop; +\tend +\tloop_fail = 1; + end + end // configloop block + if (loop_fail) $display(""\ +\\ttime: %0t, loop_cntr: %0d"",$time,loop_cntr); + end + + // still more complex: disable from within a forked block + initial begin + #2; + begin: forked_tasks + fork +\tbegin +\t #5; +\t fork_fail = 1; +\tend +\tbegin +\t @(fred); +\t disable forked_tasks; +\t fork_fail = 1; +\tend + join + fork_fail = 1; + end //forked_tasks + end + + // disables inside tasks + initial begin + task_with_loop; + end + initial begin + task_with_fork; + end + initial begin + task_with_fork2; + if(tfk2pos || tfk2nega || tfk2negb) tfk2_fail = 1; + end + initial begin + task_with_fork3; + if(tfk3pos || tfk3nega || tfk3negb) tfk3_fail = 1; + end + +task task_with_loop; + begin + #2; + begin: configtlp + for (tlp_cntr = 0; tlp_cntr < 3; tlp_cntr=tlp_cntr+1) begin +\twait (fred); +\tif (abort) begin +\t disable configtlp; +\tend +\ttlp_fail = 1; + end + end // configloop block + end +endtask // task_with_loop + +task task_with_fork; // disable block whick calls fork + begin + #2; + begin: forked_tasks_in_task + fork +\tbegin: alf +\t #5; +\t tfk_fail = 1; +\tend +\tbegin: bet +\t @(fred); +\t disable forked_tasks_in_task; +\t tfk_fail = 1; +\tend + join + tfk_fail = 1; + end //forked_tasks_in_task + end +endtask // task_with_fork + +task task_with_fork2; // disable *one* of the forked blocks + begin + #2; + begin: forked_tasks_in_task2 + fork +\tbegin: gam +\t #5; +\t tfk2pos = 1; +\tend +\tbegin: delt +\t @(fred); +\t disable gam; +\t tfk2nega = 0; +\tend + join + tfk2negb = 0; + end //forked_tasks_in_task + end +endtask // task_with_fork + +task task_with_fork3; // disable *one* of the forked blocks + begin + #2; + begin: forked_tasks_in_task3 + fork +\tbegin: eps +\t #5; +\t tfk3nega = 0; +\tend +\tbegin: zet +\t @(fred); +\t disable zet; +\t tfk3pos = 1; +\tend + join + tfk3negb = 0; + end //forked_tasks_in_task + end +endtask // task_with_fork + +endmodule +" +"module top; + reg [2:-1] vec; + integer idx; + + initial begin + idx = 'bx; + assign vec[idx+:1] = 1'b1; + deassign vec[idx+:1]; + end +endmodule +" +"/* + * Copyright (c) 2000 Steven Wilson (stevew@homeaddress.org) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test looks for == operation in a continuous assignment. + */ +module test; + +integer a; +integer b; +wire result; +integer error; + +assign result = (a == b); + +initial + begin + a = 0; + b = 0; + error = 0; + #5 ; + if( result !== 1\'b1) + error =1; + a = 1; + #5; + if( result !== 1\'b0) + error =1; + + b = 1; + #5 ; + if( result !== 1\'b1) + error =1; + + a = 1002; + b = 1001; + #5 ; + if( result !== 1\'b0) + error =1; + a = 1001; + #5 ; + if( result !== 1\'b1) + error =1; + + if(error === 0) +\t $display(""PASSED""); + else +\t $display(""FAILED""); + end + +endmodule +" +"module ternary; + + wire [5:0] a; + wire [6:0] b; + wire c; + + wire [5:0] d = c ? a : b; + + initial + begin +\t$display(""PASSED""); +\t$finish; + end + +endmodule +" +"`begin_keywords ""1364-2005"" +/* + * Copyright (c) 2005 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* tern7.v + * This tests types. + */ +module main; + + reg b, c, d, e; + wire a = b ? c : (d&e); + + reg [4:0] tmp; + reg\t ref; + initial begin + // Do an exaustive scan of the possible values. + for (tmp = 0 ; tmp < 16 ; tmp = tmp + 1) begin +\t b <= tmp[0]; +\t c <= tmp[1]; +\t d <= tmp[2]; +\t e <= tmp[3]; +\t ref = tmp[0] ? tmp[1] : (tmp[2]&tmp[3]); + +\t #1 if (ref !== a) begin +\t $display(""FAILED -- a=%b, b=%b, c=%b, d=%b, e=%b"", +\t\t a, b, c, d, e); +\t $finish; +\t end + end // for (tmp = 0 ; tmp < 16 ; tmp = tmp + 1) + + b <= 0; + c <= 1; + d <= 1; + e <= 0; + #1 if (a !== 1\'b0) begin +\t $display(""FAILED (1)""); +\t $finish; + end + + e <= 1; + #1 if (a !== 1\'b1) begin +\t $display(""FAILED (2)""); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule // main +`end_keywords +" +"/** + * Author: Evan Lavelle, Riverside Machines Ltd. + * Version: 0.1 (2007-05-22) + * Licence: This code is released into the public domain. + * + * Test implicit Verilog-95 style ports. According to 12.3.2 of the 2005 + * LRM: + * + * ""The port reference for each port in the list of ports at the top of each + * module declaration can be one of the following: + * + * A simple identifier or escaped identifier + * A bit-select of a vector declared within the module + * A part-select of a vector declared within the module + * A concatenation of any of the above + * + * The port expression is optional because ports can be defined that do not + * connect to anything internal to the module."" + * + * The expected output is: + * + * sum[ 1] = 0101010101100000 + * sum[ 2] = 0101010101100000 + * sum[ 3] = 0101010101100000 + * sum[ 4] = 0101010101100000 + * sum[ 5] = 0101010101100000 + * sum[ 6] = 0101010101100000 + * sum[ 7] = 0101010101100000 + * sum[ 8] = 0101010101100000 + * sum[ 9] = 0101010101100000 + * sum[ 10] = 0101010101100000 + * sum[ 11] = 0101010101100000 + * sum[ 12] = 0101010101100000 + * sum[ 13] = 0101010101100000 + * sum[ 14] = 0101010101100000 + * sum[ 15] = 0101010101100000 + * sum[ 16] = 0101010101100000 + * sum[ 17] = 0101010101100000 + * sum[ 18] = 0101010101100000 + * sum[ 19] = 0101010101100000 + * sum[ 20] = 0101010101100000 + * sum[ 21] = 0101010101100000 + * sum[ 22] = 0101010101100000 + * sum[ 23] = 0101010101100000 + * + */ +module test; + + reg [15:0] sum[23:1]; + wire [7:0] data = 1; + wire dummy1, dummy2; + wire [15:0] wire5, wire9, wire13, wire17, wire21; + + initial + main; + + task main; + integer i; + begin +\t for(i=1; i<=23; i=i+1) +\t sum[i] = \'h555f; +\t #2; + +\t sum[5] = wire5; +\t sum[9] = wire9; +\t sum[13] = wire13; +\t sum[17] = wire17; +\t sum[21] = wire21; + +\t for(i=1; i<=23; i=i+1) +\t $display(""sum[%d] = %b"", i, sum[i]); + end + endtask + + m1 m1(); + m2 m2(dummy1, dummy2); + m3 m3(dummy1, , dummy2); + + m4 m4(data); + m5 m5(data, wire5); + m6 m6(dummy1, data); + m7 m7(data, ); + + m8 m8 (data); + m9 m9 (data, wire9); + m10 m10( , data); + m11 m11(data, ); + + m12 m12(data[0]); + m13 m13(data[0], wire13); + m14 m14( , data[0]); + m15 m15(data[0], ); + + m16 m16(data); + m17 m17(data, wire17); + m18 m18(dummy1, data); + m19 m19(data, ); + + m20 m20(data); + m21 m21(data, wire21); + m22 m22(dummy1, data); + m23 m23(data, ); + +endmodule + +/* ---------------------------------------------------------------------------- + * the test modules + * ------------------------------------------------------------------------- */ + +// 95, no ports +module m1; + initial #1 test.sum[1] = test.sum[1] + test.data; +endmodule + +// 95, two ports, but neither has an internal connection +module m2(,); + initial #1 test.sum[2] = test.sum[2] + test.data; +endmodule + +// 95, three ports, but none have an internal connection +module m3(,,); + initial #1 test.sum[3] = test.sum[3] + test.data; +endmodule + +/* ---------------------------------------------------------------------------- + * 95, one and two ports, with implicit and simple identifiers + * ------------------------------------------------------------------------- */ + +// 95, one implicit port, simple identifier +module m4(a); + input a; + wire [7:0] a; + initial #1 test.sum[4] = test.sum[4] + a; +endmodule + +// 95, two implicit ports, simple identifiers +module m5(a, b); + input a; + output b; + wire [7:0] a; + reg [15:0] b; + initial #1 b <= test.sum[5] + a; +endmodule + +// 95, two ports; the first has no internal connection; the second is implicit/ +// simple +module m6(,a); + input a; + wire [7:0] a; + initial #1 test.sum[6] = test.sum[6] + a; +endmodule + +// 95, two ports; the second has no internal connection; the first is implicit/ +// simple +module m7(a,); + input a; + wire [7:0] a; + initial #1 test.sum[7] = test.sum[7] + a; +endmodule + +/* ---------------------------------------------------------------------------- + * 95, one and two ports, with implicit and extended identifiers + * ------------------------------------------------------------------------- */ + +// 95, one implicit port, extended identifier +module m8(\\a ); + input \\a ; + wire [7:0] \\a ; + initial #1 test.sum[8] = test.sum[8] + \\a ; +endmodule + +// 95, two implicit ports, extended identifiers +module m9(\\a , \\b ); + input \\a ; + output \\b ; + wire [7:0] \\a ; + reg [15:0] \\b ; + initial #1 \\b = test.sum[9] + \\a ; +endmodule + +// 95, two ports; the first has no internal connection; the second is implicit/ +// extended +module m10(,\\a ); + input \\a ; + wire [7:0] \\a ; + initial #1 test.sum[10] = test.sum[10] + \\a ; +endmodule + +// 95, two ports; the second has no internal connection; the first is implicit/ +// extended +module m11(\\a ,); + input \\a ; + wire [7:0] \\a ; + initial #1 test.sum[11] = test.sum[11] + \\a ; +endmodule + +/* ---------------------------------------------------------------------------- + * 95, one and two ports, with implicit and vector bit-select ports + * ------------------------------------------------------------------------- */ + +// 95, one implicit port, vector bit-select +module m12(a[0]); + input a; + wire [7:0] a; + initial #1 test.sum[12] = test.sum[12] + {test.data[7:1], a[0]}; +endmodule + +// 95, two implicit ports, vector bit-selects. the output is actually a part +// select, since ISE core dumps on the assign below, and doing anything +// else in -95 is difficult +module m13(a[0], b[15:0]); + input a; + output b; + wire [7:0] a; + reg [31:0] b; + reg [15:0] temp; + +// assign test.wire13[15:1] = temp[15:1]; // drives the rest of wire13 + + initial begin + #1 temp = test.sum[13] + {test.data[7:1], a[0]}; + b = temp; // drives wire13[0] + end +endmodule + +// 95, two ports; the first has no internal connection; the second is implicit/ +// vector bit-select +module m14(,a[0]); + input [7:0] a; + initial #1 test.sum[14] = test.sum[14] + {test.data[7:1], a[0]}; +endmodule + +// 95, two ports; the second has no internal connection; the first is implicit/ +// vector bit-select +module m15(a[0],); + input [7:0] a; + initial #1 test.sum[15] = test.sum[15] + {test.data[7:1], a[0]}; +endmodule + +/* ---------------------------------------------------------------------------- + * 95, one and two ports, with implicit and vector part-select ports + * ------------------------------------------------------------------------- */ + +// 95, one implicit port, vector bit-select +module m16(a[7:0]); + input a; + wire [15:0] a; + initial #1 test.sum[16] = test.sum[16] + {8\'h00, a[7:0]}; +endmodule + +// 95, two implicit ports, vector bit-selects +module m17(a[7:0], b[15:0]); + input a; + output b; + wire [7:0] a; + reg [31:0] b; + initial #1 b[15:0] = test.sum[17] + a; +endmodule + +// 95, two ports; the first has no internal connection; the second is implicit/ +// vector part-select +module m18(,a[7:0]); + input [15:0] a; + initial #1 test.sum[18] = test.sum[18] + {8\'h00, a[7:0]}; +endmodule + +// 95, two ports; the second has no internal connection; the first is implicit/ +// vector part-select +module m19(a[7:0],); + input [15:0] a; +// initial #1 test.sum[19] = test.sum[19] + a; + initial #1 test.sum[19] = test.sum[19] + {8\'h00, a[7:0]}; +endmodule + +/* ---------------------------------------------------------------------------- + * 95, one and two ports, with ports which are a concatenation of a bit select + * and a 3-bit part select + * ------------------------------------------------------------------------- */ + +// 95, one implicit port, concatenation +module m20({a[7], a[6:0]}); + input a; + wire [15:0] a; + initial #1 test.sum[20] = test.sum[20] + {8\'h00, a[7:0]}; +endmodule + +// 95, two implicit ports, concatenations +module m21({a[7], a[6:0]}, {b[15], b[14:0]}); + input a; + output b; + wire [7:0] a; + reg [15:0] b; + initial #1 b = test.sum[21] + {8\'h00, a[7:0]}; +endmodule + +// 95, two ports; the first has no internal connection; the second is implicit/ +// concatenation +module m22(,{a[7], a[6:0]}); + input [15:0] a; + initial #1 test.sum[22] = test.sum[22] + {8\'h00, a[7:0]}; +endmodule + +// 95, two ports; the second has no internal connection; the first is implicit/ +// concatenation. note that both modelsim and ISE set the entire sum, and not +// just the top 8 bits, to all x\'s for \'test.sum[23] = test.sum[23] + a\' +module m23({a[7], a[6:0]},); + input a; + wire [15:0] a; + initial #1 test.sum[23] = test.sum[23] + a[7:0]; +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate various module formats + + +// Template 1 + +module mod1 ; +endmodule + +// Template 2 +module mod2 (); +endmodule + +// Template 3 +module mod3 (a,b); +input a; +input b; +endmodule + +//Template 4 - +module mod4 (ident1,out1); +input [31:0] ident1; +output [31:0] out1; + +wire [31:0] out1 = ident1; +endmodule + +module main (); + +wire [31:0] out1,out2; +reg [31:0] val1,val2; +reg error; + +mod4 inst1 (val1,out1);\t\t\t// Ordered port list +mod4 inst2 (.ident1(val2),.out1(out2)); // List by portname + +initial + begin + error = 0; + val1 = 32\'h11223344; + #1 if(out1 != 32\'h11223344) + begin + $display(""FAILED - module 3.12A - Ordered module port list failed""); + error = 1; + end + val2 = 32\'h44332211; + #1 if(out2 != 32\'h44332211) + begin + $display(""FAILED -module 3.12A -named module port list (.x(a)) failed""); + error = 1; + end + if(error == 0) + $display(""PASSED""); + end + + +endmodule // main +" +"module example; + + reg [7:0] vec; + reg [3:0] ix; + wire vix = vec[ix]; + + initial begin + $display( "" time ix vix vec"" ); + $display( "" ---- ---- --- --------"" ); + $monitor( ""%T %b %b %b"", $time, ix, vix, vec ); + vec = 8\'b00000000; + ix = 0; // 0 + #100 ix = 1; // 100 + #100 ix = 2; // 200 + #100 ix = 3; // 300 + #100 ix = 4; // 400 + #100 ix = 5; // 500 + #100 ix = 6; // 600 + #100 ix = 7; // 700 + #100 ix = 8; // 800 + #100 ix = 4\'b001x; // 900 + #100 ix = 4\'b01x0; // 1000 + #100 ix = 4\'b0x01; // 1100 + #100 ix = 0; // 1200 + #100 vec[ix] = 1\'b1; // 1300 + #100 vec[ix] = 1\'b0; // 1400 + #100 ix = 3; // 1500 + #100 vec[ix] = 1\'b1; // 1600 + #100 vec[ix] = 1\'b0; // 1700 + #100 ix = 6; // 1800 + #100 vec[ix] = 1\'b1; // 1900 + #100 vec[ix] = 1\'b0; // 2000 + #100 ix = 8; // 2100 + #100 vec[ix] = 1\'b1; // 2200 + #100 vec[ix] = 1\'b0; // 2300 + #100 ix = 4\'b010x; // 2400 + #100 vec[ix] = 1\'b1; // 2500 + #100 vec[ix] = 1\'b0; // 2600 + #100 ix = 4\'b00x1; // 2700 + #100 vec[ix] = 1\'b1; // 2800 + #100 vec[ix] = 1\'b0; // 2900 + #100 ix = 4\'b0x10; // 3000 + #100 vec[ix] = 1\'b1; // 3100 + #100 vec[ix] = 1\'b0; // 3200 + #100 ix = 4\'bxxxx; // 3300 + #100 vec[ix] = 1\'b1; // 3400 + #100 vec[ix] = 1\'b0; // 3500 + #100 $display( ""Finish at time %T"", $time ); + end + +endmodule +" +"module stimulus (output reg A); + + initial begin + // input is x + #0 A = 1\'bx; + // input is z + #10 A = 1\'bz; + // one input is a zero + #10 A = 1\'b0; + // one input is a one + #10 A = 1\'b1; + end + +endmodule + +module scoreboard (input Y, A); + +function truth_table (input a); + reg gate_operand; + reg gate_output; + begin + gate_operand = a; + case (gate_operand) + // input is x + 1\'bx: gate_output = 1\'bx; + // inputs is z + 1\'bz: gate_output = 1\'bx; + // normal operation on bit + 1\'b0: gate_output = 1; + 1\'b1: gate_output = 0; + endcase + + truth_table = gate_output; + end +endfunction + + +reg Y_t; + +always @(A) begin + Y_t = truth_table (A); + #1; + if (Y_t !== Y) begin + $display(""FAILED! - mismatch found for input %b in NOT operation"", A); + $finish; + end +end + +endmodule + +module test; + stimulus stim (A); + not_func duv (.a_i(A), .c_o(Y) ); + scoreboard mon (Y, A); + + initial begin + #200; + $display(""PASSED""); + $finish; + end + +endmodule +" +"module test(); + +parameter signed snv1 = 4\'d1; +parameter signed [2:0] s3v1 = 4\'d1; +parameter signed [3:0] s4v1 = 4\'d1; +parameter signed [4:0] s5v1 = 4\'d1; + +parameter signed snv15 = 4\'d15; +parameter signed [2:0] s3v15 = 4\'d15; +parameter signed [3:0] s4v15 = 4\'d15; +parameter signed [4:0] s5v15 = 4\'d15; + +parameter signed snvm1 = -4\'sd1; +parameter signed [2:0] s3vm1 = -4\'sd1; +parameter signed [3:0] s4vm1 = -4\'sd1; +parameter signed [4:0] s5vm1 = -4\'sd1; + +parameter signed snrm1 = -1.0; +parameter signed [2:0] s3rm1 = -1.0; +parameter signed [3:0] s4rm1 = -1.0; +parameter signed [4:0] s5rm1 = -1.0; + +parameter nnv1 = 4\'d1; +parameter [2:0] u3v1 = 4\'d1; +parameter [3:0] u4v1 = 4\'d1; +parameter [4:0] u5v1 = 4\'d1; + +parameter nnv15 = 4\'d15; +parameter [2:0] u3v15 = 4\'d15; +parameter [3:0] u4v15 = 4\'d15; +parameter [4:0] u5v15 = 4\'d15; + +parameter nnvm1 = -4\'sd1; +parameter [2:0] u3vm1 = -4\'sd1; +parameter [3:0] u4vm1 = -4\'sd1; +parameter [4:0] u5vm1 = -4\'sd1; + +parameter nnrm1 = -1.0; +parameter [2:0] u3rm1 = -1.0; +parameter [3:0] u4rm1 = -1.0; +parameter [4:0] u5rm1 = -1.0; + +reg fail = 0; + +reg match; + +initial begin + match = ($bits(snv1) == 4) && (snv1 === 1); + $display(""snv1 : %2d (%0d`b%b) %c"", snv1, $bits(snv1), snv1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(s3v1) == 3) && (s3v1 === 1); + $display(""s3v1 : %2d (%0d`b%b) %c"", s3v1 , $bits(s3v1), s3v1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(s4v1) == 4) && (s4v1 === 1); + $display(""s4v1 : %2d (%0d`b%b) %c"", s4v1 , $bits(s4v1), s4v1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(s5v1) == 5) && (s5v1 === 1); + $display(""s5v1 : %2d (%0d`b%b) %c"", s5v1 , $bits(s5v1), s5v1, match ? "" "" : ""*""); + fail = fail || !match; + + match = ($bits(snv15) == 4) && (snv15 === -1); + $display(""snv15 : %2d (%0d`b%b) %c"", snv15, $bits(snv15), snv15, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(s3v15) == 3) && (s3v15 === -1); + $display(""s3v15 : %2d (%0d`b%b) %c"", s3v15, $bits(s3v15), s3v15, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(s4v15) == 4) && (s4v15 === -1); + $display(""s4v15 : %2d (%0d`b%b) %c"", s4v15, $bits(s4v15), s4v15, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(s5v15) == 5) && (s5v15 === 15); + $display(""s5v15 : %2d (%0d`b%b) %c"", s5v15, $bits(s5v15), s5v15, match ? "" "" : ""*""); + fail = fail || !match; + + match = ($bits(snvm1) == 4) && (snvm1 === -1); + $display(""snvm1 : %2d (%0d`b%b) %c"", snvm1, $bits(snvm1), snvm1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(s3vm1) == 3) && (s3vm1 === -1); + $display(""s3vm1 : %2d (%0d`b%b) %c"", s3vm1, $bits(s3vm1), s3vm1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(s4vm1) == 4) && (s4vm1 === -1); + $display(""s4vm1 : %2d (%0d`b%b) %c"", s4vm1, $bits(s4vm1), s4vm1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(s5vm1) == 5) && (s5vm1 === -1); + $display(""s5vm1 : %2d (%0d`b%b) %c"", s5vm1, $bits(s5vm1), s5vm1, match ? "" "" : ""*""); + fail = fail || !match; + + match = (snrm1 == -1); + $display(""snrm1 : %4.1f %c"", snrm1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(s3rm1) == 3) && (s3rm1 === -1); + $display(""s3rm1 : %2d (%0d`b%b) %c"", s3rm1, $bits(s3rm1), s3rm1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(s4rm1) == 4) && (s4rm1 === -1); + $display(""s4rm1 : %2d (%0d`b%b) %c"", s4rm1, $bits(s4rm1), s4rm1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(s5rm1) == 5) && (s5rm1 === -1); + $display(""s5rm1 : %2d (%0d`b%b) %c"", s5rm1, $bits(s5rm1), s5rm1, match ? "" "" : ""*""); + fail = fail || !match; + + match = ($bits(nnv1) == 4) && (nnv1 === 1); + $display(""nnv1 : %2d (%0d`b%b) %c"", nnv1, $bits(nnv1), nnv1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(u3v1) == 3) && (u3v1 === 1); + $display(""u3v1 : %2d (%0d`b%b) %c"", u3v1 , $bits(u3v1), u3v1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(u4v1) == 4) && (u4v1 === 1); + $display(""u4v1 : %2d (%0d`b%b) %c"", u4v1 , $bits(u4v1), u4v1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(u5v1) == 5) && (u5v1 === 1); + $display(""u5v1 : %2d (%0d`b%b) %c"", u5v1 , $bits(u5v1), u5v1, match ? "" "" : ""*""); + fail = fail || !match; + + match = ($bits(nnv15) == 4) && (nnv15 === 15); + $display(""nnv15 : %2d (%0d`b%b) %c"", nnv15, $bits(nnv15), nnv15, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(u3v15) == 3) && (u3v15 === 7); + $display(""u3v15 : %2d (%0d`b%b) %c"", u3v15, $bits(u3v15), u3v15, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(u4v15) == 4) && (u4v15 === 15); + $display(""u4v15 : %2d (%0d`b%b) %c"", u4v15, $bits(u4v15), u4v15, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(u5v15) == 5) && (u5v15 === 15); + $display(""u5v15 : %2d (%0d`b%b) %c"", u5v15, $bits(u5v15), u5v15, match ? "" "" : ""*""); + fail = fail || !match; + + match = ($bits(nnvm1) == 4) && (nnvm1 === -1); + $display(""nnvm1 : %2d (%0d`b%b) %c"", nnvm1, $bits(nnvm1), nnvm1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(u3vm1) == 3) && (u3vm1 === 7); + $display(""u3vm1 : %2d (%0d`b%b) %c"", u3vm1, $bits(u3vm1), u3vm1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(u4vm1) == 4) && (u4vm1 === 15); + $display(""u4vm1 : %2d (%0d`b%b) %c"", u4vm1, $bits(u4vm1), u4vm1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(u5vm1) == 5) && (u5vm1 === 31); + $display(""u5vm1 : %2d (%0d`b%b) %c"", u5vm1, $bits(u5vm1), u5vm1, match ? "" "" : ""*""); + fail = fail || !match; + + match = (nnrm1 == -1.0); + $display(""nnrm1 : %4.1f %c"", nnrm1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(u3rm1) == 3) && (u3rm1 === 7); + $display(""u3rm1 : %2d (%0d`b%b) %c"", u3rm1, $bits(u3rm1), u3rm1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(u4rm1) == 4) && (u4rm1 === 15); + $display(""u4rm1 : %2d (%0d`b%b) %c"", u4rm1, $bits(u4rm1), u4rm1, match ? "" "" : ""*""); + fail = fail || !match; + match = ($bits(u5rm1) == 5) && (u5rm1 === 31); + $display(""u5rm1 : %2d (%0d`b%b) %c"", u5rm1, $bits(u5rm1), u5rm1, match ? "" "" : ""*""); + fail = fail || !match; + + if (fail) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module test (); + reg pass = 1\'b1; + reg d; + real f = 0.0, z = 0.0, y = 1.0; + + always @(d) force f = z; + + initial begin + // Verify the initial value. + #1; + if (f != 0.0) begin + $display(""Failed initial value, expected 0.0, got %f"", f); + pass = 1\'b0; + end + + // Verify that the force changed the value and that a normal assign + // is blocked. + #1 d = 0; + #1 f = 1.0; + if (f != 0.0) begin + $display(""Failed force holding (normal), expected 0.0, got %f"", f); + pass = 1\'b0; + end + + // Verify that an assign does not change the value when forced. + #1 assign f = y; + if (f != 0.0) begin + $display(""Failed force holding (assign), expected 0.0, got %f"", f); + pass = 1\'b0; + end + + // Verify that a force will propagate. + z = 1.0; + #1; + if (f != 1.0) begin + $display(""Failed force propagation, expected 1.0, got %f"", f); + pass = 1\'b0; + end + + // Verify that the release holds the previous value. + #1 release f; + if (f != 1.0) begin + $display(""Failed release holding, expected 1.0, got %f"", f); + pass = 1\'b0; + end + + // Verify that a release correctly breaks the variable link. + #1 z = 0.0; + if (f != 1.0) begin + $display(""Failed variable unlinking (force), expected 1.0, got %f"", f); + pass = 1\'b0; + end + + // Verify that a deassign holds the previous value. + #1 deassign f; + if (f != 1.0) begin + $display(""Failed deassign holding, expected 1.0, got %f"", f); + pass = 1\'b0; + end + + // Verify that a deassign correctly breaks the variable link. + #1 y = 0.0; + if (f != 1.0) begin + $display(""Failed variable unlinking (deassign), expected 1.0, got %f"", f); + pass = 1\'b0; + end + + // Verify that the value can be changed after a release and a deassign. + #1 f = 2.0; + if (f != 2.0) begin + $display(""Failed release, expected 2.0, got %f"", f); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4\'d2; + +assign #1 value2 = value1; + +initial begin + #2 $display(""%b %b"", value1, value2); + if (value2 === 8\'bzzzz0010) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module check (input unsigned [103:0] a, b, c); + wire [103:0] int_AB; + + assign int_AB = ~(a | b); + +always @(a, b, int_AB, c) begin + #1; + if (int_AB !== c) begin + $display(""ERROR""); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [103:0] A, B); + parameter S = 2000; + int unsigned i; + + + initial begin + A = 0; B= 0; + // values with 0, 1 + for (i=0; i %b"", A, B, select, out); + end + end + +endmodule + + +primitive prim_mux2(output out, input in1, input in0, input select); + +table + +//in1 in0 select : out + 0 0 1 : 0; + 1 1 ? : 1; + 0 ? 1 : 0; + 1 ? 1 : 1; + ? 0 0 : 0; + ? 1 0 : 1; +endtable + +endprimitive +" +"`timescale 1us/1ns + +module top; + initial begin + + // This should print the following: + + // Time scale of (top) is 1us / 1ns + // Time scale of (top) is 1us / 1ns + // Time scale of (top.dut) is 10ns / 10ps + // Time scale of (top.dut.dut) is 1ns / 10ps + // Time scale of (othertop) is 1ms / 1us + + // But currently the precisions will all be 10ps the finest precision. + $printtimescale; + $printtimescale(); + $printtimescale(dut); + $printtimescale(dut.dut); + $printtimescale(othertop); + end + + lower dut(); +endmodule + +`timescale 10ns/10ps +module lower; + evenlower dut(); +endmodule + +`timescale 1ns/10ps +module evenlower; +endmodule + +`timescale 1ms/1us +module othertop; +endmodule +" +"module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + always @(posedge clk) + if (rst) out <= 1\'d0; + else out <= ~inp; + +endmodule + +module foo(clk, rst, inp, out_a, out_b); + input wire clk; + input wire rst; + input wire inp; + output wire out_a; + output wire out_b; + + bar bar_instance_1 ( (* this_is_clock *) .clk(clk), .rst(rst), .inp(inp), .out(out_a) ); + bar bar_instance_2 ( clk, (* this_is_reset *) rst, inp, out_b ); + + initial begin + $display(""PASSED""); + end + +endmodule +" +"module test(); + +`define MACRO 1 +`define MACRO 1 +`define MACRO 2 +`undef MACRO +`define MACRO 1 + +endmodule +" +"/* + * Exhaustive check of all the compare results. + */ +module main; + + wire out; + reg [7:0] A, B; + + ge8 dut(.out(out), .A(A), .B(B)); + + reg\t error = 0; + integer adx, bdx; + + initial begin + A = 0; + B = 0; + #1 $display(""%b >= %b: %b"", A, B, out); + + for (adx = 0 ; adx < 256 ; adx = adx + 1) begin +\t A = adx; +\t for (bdx = 0 ; bdx < 256 ; bdx = bdx + 1) begin +\t B = bdx; +\t #1 $write(""%b >= %b: %b"", A, B, out); +\t if (out === 1) begin +\t if (A < B) begin +\t\t $display("" ERROR""); +\t\t error = 1; +\t end else begin +\t\t $display("" OK""); +\t end + +\t end else if (out === 0) begin +\t if (A < B) begin +\t\t $display("" OK""); +\t end else begin +\t\t $display("" ERROR""); +\t\t error = 1; +\t end + +\t end else begin +\t $display("" ERROR""); +\t error = 1; +\t end // else: !if(out === 0) + +\t end // for (bdx = 0 ; bdx < 256 ; bdx += 1) + end // for (adx = 0 ; adx < 256 ; adx = adx + 1) + + if (error == 0) +\t$display(""PASSED""); + else +\t$display(""FAILED""); + + end // initial begin +endmodule // main +" +"module pli_test; + +wire [15:0] a = 16\'h4321; +wire [ 7:0] b = a[15:8]; + +integer rc; + +initial + begin + #1 /* Allow the continuous assignments above to settle. */ ; + $display(""Passing parameter to PLI routine: 0x%x"",a[15:8]); + rc = $pli_test(a[15:8]); + $display(""Passing parameter to PLI routine: 0x%x"",b); + rc = $pli_test(b); + end + +endmodule +" +"module copy(output [1:0] out, input [1:0] in); + +assign out = in; + +endmodule + +module top(); + +reg [2:0] r; +wire [1:0] i1; +wire [1:0] i2; +wire [1:0] i3; +wire [0:0] o1; +wire [1:0] o2; +wire [2:0] o3; + +assign i1 = r; +assign i2 = r; +assign i3 = r; + +copy copy1(o1, i1); +copy copy2(o2, i2); +copy copy3(o3, i3); + +reg failed; + +initial begin + failed = 0; + for (r = 0; r < 4; r = r + 1) begin + #1 $display(""%b : %b %b : %b %b : %b %b"", r[1:0], i1, o1, i2, o2, i3, o3); + if (o1 !== r[0]) failed = 1; + if (o2 !== r[1:0]) failed = 1; + if (o3 !== {1\'b0, r[1:0]}) failed = 1; + end + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"/* + * Based on bug report PR#842. + */ + +module test; + foo _foo(); + + initial + begin + // Access the FOO parameter inside the _foo instance ? + $display(""%d"", _foo.FOO); +\t if (_foo.FOO != 17) begin +\t $display(""FAILED -- _foo.FOO=%d"", _foo.FOO); +\t $finish; +\t end +\t $display(""PASSED""); + end +endmodule + +module foo; + parameter FOO = 17; +endmodule +" +"// This module generate M single 2*HW-1 bit vector each T time steps + +module stimulus #(parameter HW = 4, T = 10, M = 200) ( + output reg [2*HW-1:0] a + ); + +int i; +int MAX; + + +initial begin + MAX = 1 << 2*HW; + for (i = 0; i < M; i=i+1) begin + a = $random % MAX ; + #T; + end + +end + + +endmodule + +// This module always checks that y complies with an XOR reduction operation on 2*HW-1 bits input as x + +module check #(parameter HW = 4) (input [2*HW-1:0] x, input y); + +wire yi = ^x; + +always @(y, yi) begin + #1; + if (y !== yi) begin + $display(""ERROR""); + $finish; + end +end + +endmodule + + +module test; + parameter M = 200; // number of test vectors + parameter T = 10; // time step unit + parameter HW = 4; // bit width of input vecotrs + parameter S = M*T + 40; + + wire [2*HW-1:0] a; + wire y; + + stimulus #(HW, T, M) stim (.a(a)); + gxor_reduce #(HW) duv (.a(a), .ar(y)); + check check (.x(a), .y(y) ); + + initial begin + #S; + $display(""PASSED""); + $finish; + end + +endmodule +" +"// Check that all sorts of enum dimension declarations are handled correctly and +// do not cause an assert or segfault. + +module test; + +// These are invalid + +enum logic [$] { +\tA +} a; + +enum logic [] { + B +} b; + +enum logic [-1] { +\tC +} c; + +enum logic [0] { +\tD +} d; + +enum logic [1:0][3:0] { +\tE +} e; + +// These are valid + +enum logic [0:2] { +\tF +} f; + +enum logic [2:0] { +\tG +} g; + +enum logic [-1:-2] { +\tH +} h; + +// These are valid as an extension in iverilog + +enum logic [16] { +\tI +} i; + +int x; + +endmodule +" +"/* + * Copyright (c) 2014 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +`default_nettype none + +module main; + + class test_t; + reg [1:0] a; + reg [2:0] b; + + function new (int ax, int bx); +\t begin +\t a = ax; +\t b = bx; +\t end + endfunction // new + + endclass // test_t + + test_t foo [0:3][0:7], tmp; + bit [3:0] idx1, idx2; + + initial begin + for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin +\t for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1) +\t foo[idx1][idx2] = new(idx1,idx2); + end + + foreach (foo[ia,ib]) begin +\t if (ia > 3 || ib > 7) begin +\t $display(""FAILED -- index out of range: ia=%0d, ib=%0d"", ia, ib); +\t $finish; +\t end + +\t tmp = foo[ia][ib]; +\t if (tmp.a !== ia[1:0] || tmp.b !== ib[2:0]) begin +\t $display(""FAILED -- foo[%0d][%0d] == %b"", ia, ib, {tmp.a, tmp.b}); +\t $finish; +\t end + +\t foo[ia][ib] = null; + end + + for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin +\t for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1) +\t if (foo[idx1][idx2] != null) begin +\t $display(""FAILED -- foreach failed to visit foo[%0d][%0d]"", idx1,idx2); +\t $finish; +\t end + end + + $display(""PASSED""); + end + +endmodule // main +" +"/* + * Check declarations and repeat declarations in nested modules. + */ +timeunit 100us; +timeprecision 1us; + +// A local time unit is OK. +module check_tu_nest; + timeunit 10us; + module nested; + timeunit 100us; + timeunit 100us; + endmodule + timeunit 10us; +endmodule + +// A local time precision is OK. +module check_tp_nest; + timeprecision 10us; + module nested; + timeprecision 1us; + timeprecision 1us; + endmodule + timeprecision 10us; +endmodule + +// Both a local time unit and precision are OK. +module check_tup_nest; + timeunit 10us; + timeprecision 10us; + module nested; + timeunit 100us; + timeprecision 1us; + timeunit 100us; + timeprecision 1us; + endmodule + timeunit 10us; + timeprecision 10us; +endmodule + +// Both a local time unit and precision are OK (check both orders). +module check_tpu_nest; + timeprecision 10us; + timeunit 10us; + module nested; + timeprecision 1us; + timeunit 100us; + timeprecision 1us; + timeunit 100us; + endmodule + timeprecision 10us; + timeunit 10us; +endmodule + +module check2; + +initial begin + $printtimescale(check_tu_nest); + $printtimescale(check_tp_nest); + $printtimescale(check_tup_nest); + $printtimescale(check_tpu_nest); + $display(""""); + $printtimescale(check_tu_nest.nested); + $printtimescale(check_tp_nest.nested); + $printtimescale(check_tup_nest.nested); + $printtimescale(check_tpu_nest.nested); +end + +endmodule +" +"// Check behaviour with out-of-range and undefined array indices +// on LHS of continuous assignment. + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + `define SUPPORT_REAL_NETS_IN_IVTEST +`endif + +module top; + +wire [1:0] array1[2:1]; +wire [1:0] array2[1:0]; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +assign array1[0] = 2\'d0; +`endif +assign array1[1] = 2\'d1; +assign array1[2] = 2\'d2; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +assign array1[3] = 2\'d3; +`endif + +assign array2[0] = 2\'d0; +assign array2[1] = 2\'d1; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +assign array2[\'bx] = 2\'d2; +`endif + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +wire real array3[2:1]; +wire real array4[1:0]; + +assign array3[0] = 0.0; +assign array3[1] = 1.0; +assign array3[2] = 2.0; +assign array3[3] = 3.0; + +assign array4[0] = 0.0; +assign array4[1] = 1.0; +assign array4[\'bx] = 2.0; +`endif + +reg failed; + +initial begin + #1 failed = 0; + + $display(""array = %h %h"", array1[2], array1[1]); + if ((array1[1] !== 2\'d1) || (array1[2] !== 2\'d2)) failed = 1; + + $display(""array = %h %h"", array2[1], array2[0]); + if ((array2[0] !== 2\'d0) || (array2[1] !== 2\'d1)) failed = 1; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST + $display(""array = %0g %0g"", array3[2], array3[1]); + if ((array3[1] != 1.0) || (array3[2] != 2.0)) failed = 1; + + $display(""array = %0g %0g"", array4[1], array4[0]); + if ((array4[0] != 0.0) || (array4[1] != 1.0)) failed = 1; +`endif + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"module m; + task t1; + input make_me_crash i; + begin + end + endtask + task t2; + input integer i; + begin + end + endtask +endmodule +" +"module check (input unsigned [22:0] a, b, c); + wire unsigned [22:0] int_AB; + + assign int_AB = a + b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB !== c) begin + $display(""ERROR""); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [22:0] A, B); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; B= 0; + for (i=0; i LSB). +module top; + parameter [4:1] ap = 4\'h8; + parameter [4:1] bp = 4\'h7; + parameter [0:-3] cp = 4\'h8; + parameter [0:-3] dp = 4\'h7; + + reg passed; + + wire [4:1] a = 4\'h8; + wire [4:1] b = 4\'h7; + wire [0:0] s0 = 0; + wire [1:0] s1 = 0; + wire [2:0] s2 = 0; + reg [4:1] ar = 4\'h8; + reg [4:1] br = 4\'h7; + + wire [0:-3] c = 4\'h8; + wire [0:-3] d = 4\'h7; + wire [0:0] s3 = 0; + wire [1:0] s4 = 0; + reg [0:-3] cr = 4\'h8; + reg [0:-3] dr = 4\'h7; + + wire res_a0 = a[s0]; + wire res_b0 = b[s0]; + wire res_a1 = a[s1]; + wire res_b1 = b[s1]; + wire res_a2 = a[s2]; + wire res_b2 = b[s2]; + + wire res_c3 = c[s3]; + wire res_d3 = d[s3]; + wire res_c4 = c[s4]; + wire res_d4 = d[s4]; + + reg [4:1] res_ab; + reg [0:-3] res_cd; + + initial begin + #1; + passed = 1\'b1; + + // Check procedural R-value variable bit selects of a net. + + $display(""a[s0]: %b"", a[s0]); + if (a[s0] !== 1\'bx) begin + $display(""Failed a[s0], expected 1\'bx, got %b"", a[s0]); + passed = 1\'b0; + end + + $display(""b[s0]: %b"", b[s0]); + if (b[s0] !== 1\'bx) begin + $display(""Failed b[s0], expected 1\'bx, got %b"", b[s0]); + passed = 1\'b0; + end + + $display(""a[s1]: %b"", a[s1]); + if (a[s1] !== 1\'bx) begin + $display(""Failed a[s1], expected 1\'bx, got %b"", a[s1]); + passed = 1\'b0; + end + + $display(""b[s1]: %b"", b[s1]); + if (b[s1] !== 1\'bx) begin + $display(""Failed b[s1], expected 1\'bx, got %b"", b[s1]); + passed = 1\'b0; + end + + $display(""a[s2]: %b"", a[s2]); + if (a[s2] !== 1\'bx) begin + $display(""Failed a[s2], expected 1\'bx, got %b"", a[s2]); + passed = 1\'b0; + end + + $display(""b[s2]: %b"", b[s2]); + if (b[s2] !== 1\'bx) begin + $display(""Failed b[s2], expected 1\'bx, got %b"", b[s2]); + passed = 1\'b0; + end + + $display(""c[s3]: %b"", c[s3]); + if (c[s3] !== 1\'b1) begin + $display(""Failed c[s3], expected 1\'b1, got %b"", c[s3]); + passed = 1\'b0; + end + + $display(""d[s3]: %b"", d[s3]); + if (d[s3] !== 1\'b0) begin + $display(""Failed d[s3], expected 1\'b0, got %b"", d[s3]); + passed = 1\'b0; + end + + $display(""c[s4]: %b"", c[s4]); + if (c[s4] !== 1\'b1) begin + $display(""Failed c[s4], expected 1\'b1, got %b"", c[s4]); + passed = 1\'b0; + end + + $display(""d[s4]: %b"", d[s4]); + if (d[s4] !== 1\'b0) begin + $display(""Failed d[s4], expected 1\'b0, got %b"", d[s4]); + passed = 1\'b0; + end + + // Check procedural R-value variable bit selects of a parameter. + + $display(""ap[s0]: %b"", ap[s0]); + if (ap[s0] !== 1\'bx) begin + $display(""Failed ap[s0], expected 1\'bx, got %b"", ap[s0]); + passed = 1\'b0; + end + + $display(""bp[s0]: %b"", bp[s0]); + if (bp[s0] !== 1\'bx) begin + $display(""Failed bp[s0], expected 1\'bx, got %b"", bp[s0]); + passed = 1\'b0; + end + + $display(""ap[s1]: %b"", ap[s1]); + if (ap[s1] !== 1\'bx) begin + $display(""Failed ap[s1], expected 1\'bx, got %b"", ap[s1]); + passed = 1\'b0; + end + + $display(""bp[s1]: %b"", bp[s1]); + if (bp[s1] !== 1\'bx) begin + $display(""Failed bp[s1], expected 1\'bx, got %b"", bp[s1]); + passed = 1\'b0; + end + + $display(""ap[s2]: %b"", ap[s2]); + if (ap[s2] !== 1\'bx) begin + $display(""Failed ap[s2], expected 1\'bx, got %b"", ap[s2]); + passed = 1\'b0; + end + + $display(""bp[s2]: %b"", bp[s2]); + if (bp[s2] !== 1\'bx) begin + $display(""Failed bp[s2], expected 1\'bx, got %b"", bp[s2]); + passed = 1\'b0; + end + + $display(""cp[s3]: %b"", cp[s3]); + if (cp[s3] !== 1\'b1) begin + $display(""Failed cp[s3], expected 1\'b1, got %b"", cp[s3]); + passed = 1\'b0; + end + + $display(""dp[s3]: %b"", dp[s3]); + if (dp[s3] !== 1\'b0) begin + $display(""Failed dp[s3], expected 1\'b0, got %b"", dp[s3]); + passed = 1\'b0; + end + + $display(""cp[s4]: %b"", cp[s4]); + if (cp[s4] !== 1\'b1) begin + $display(""Failed cp[s4], expected 1\'b1, got %b"", cp[s4]); + passed = 1\'b0; + end + + $display(""dp[s4]: %b"", dp[s4]); + if (dp[s4] !== 1\'b0) begin + $display(""Failed dp[s4], expected 1\'b0, got %b"", dp[s4]); + passed = 1\'b0; + end + + // Check procedural R-value variable bit selects of a reg. + + $display(""ar[s0]: %b"", ar[s0]); + if (ar[s0] !== 1\'bx) begin + $display(""Failed ar[s0], expected 1\'bx, got %b"", ar[s0]); + passed = 1\'b0; + end + + $display(""br[s0]: %b"", br[s0]); + if (br[s0] !== 1\'bx) begin + $display(""Failed br[s0], expected 1\'bx, got %b"", br[s0]); + passed = 1\'b0; + end + + $display(""ar[s1]: %b"", ar[s1]); + if (ar[s1] !== 1\'bx) begin + $display(""Failed ar[s1], expected 1\'bx, got %b"", ar[s1]); + passed = 1\'b0; + end + + $display(""br[s1]: %b"", br[s1]); + if (br[s1] !== 1\'bx) begin + $display(""Failed br[s1], expected 1\'bx, got %b"", br[s1]); + passed = 1\'b0; + end + + $display(""ar[s2]: %b"", ar[s2]); + if (ar[s2] !== 1\'bx) begin + $display(""Failed ar[s2], expected 1\'bx, got %b"", ar[s2]); + passed = 1\'b0; + end + + $display(""br[s2]: %b"", br[s2]); + if (br[s2] !== 1\'bx) begin + $display(""Failed br[s2], expected 1\'bx, got %b"", br[s2]); + passed = 1\'b0; + end + + $display(""cr[s3]: %b"", cr[s3]); + if (cr[s3] !== 1\'b1) begin + $display(""Failed cr[s3], expected 1\'b1, got %b"", cr[s3]); + passed = 1\'b0; + end + + $display(""dr[s3]: %b"", dr[s3]); + if (dr[s3] !== 1\'b0) begin + $display(""Failed dr[s3], expected 1\'b0, got %b"", dr[s3]); + passed = 1\'b0; + end + + $display(""cr[s4]: %b"", cr[s4]); + if (cr[s4] !== 1\'b1) begin + $display(""Failed cr[s4], expected 1\'b1, got %b"", cr[s4]); + passed = 1\'b0; + end + + $display(""dr[s4]: %b"", dr[s4]); + if (dr[s4] !== 1\'b0) begin + $display(""Failed dr[s4], expected 1\'b0, got %b"", dr[s4]); + passed = 1\'b0; + end + + // Check continuous assignment R-value variable bit selects. + + if (res_a0 !== 1\'bx) begin + $display(""Failed res_a0, expected 1\'bx, got %b"", res_a0); + passed = 1\'b0; + end + + if (res_b0 !== 1\'bx) begin + $display(""Failed res_b0, expected 1\'bx, got %b"", res_b0); + passed = 1\'b0; + end + + if (res_a1 !== 1\'bx) begin + $display(""Failed res_a1, expected 1\'bx, got %b"", res_a1); + passed = 1\'b0; + end + + if (res_b1 !== 1\'bx) begin + $display(""Failed res_b1, expected 1\'bx, got %b"", res_b1); + passed = 1\'b0; + end + + if (res_a2 !== 1\'bx) begin + $display(""Failed res_a2, expected 1\'bx, got %b"", res_a2); + passed = 1\'b0; + end + + if (res_b2 !== 1\'bx) begin + $display(""Failed res_b2, expected 1\'bx, got %b"", res_b2); + passed = 1\'b0; + end + + if (res_c3 !== 1\'b1) begin + $display(""Failed res_c3, expected 1\'b1, got %b"", res_c3); + passed = 1\'b0; + end + + if (res_d3 !== 1\'b0) begin + $display(""Failed res_d3, expected 1\'b0, got %b"", res_d3); + passed = 1\'b0; + end + + if (res_c4 !== 1\'b1) begin + $display(""Failed res_c4, expected 1\'b1, got %b"", res_c4); + passed = 1\'b0; + end + + if (res_d4 !== 1\'b0) begin + $display(""Failed res_d4, expected 1\'b0, got %b"", res_d4); + passed = 1\'b0; + end + + // Check procedural L-value variable bit selects. + + res_ab = 4\'bxxxx; + res_ab[s0] = 1\'b0; + if (res_ab !== 4\'bxxxx) begin + $display(""Failed res_ab[s0], expected 4\'bxxxx, got %b"", res_ab); + passed = 1\'b0; + end + + res_ab = 4\'bxxxx; + res_ab[s1] = 1\'b0; + if (res_ab !== 4\'bxxxx) begin + $display(""Failed res_ab[s1], expected 4\'bxxxx, got %b"", res_ab); + passed = 1\'b0; + end + + res_ab = 4\'bxxxx; + res_ab[s2] = 1\'b0; + if (res_ab !== 4\'bxxxx) begin + $display(""Failed res_ab[s2], expected 4\'bxxxx, got %b"", res_ab); + passed = 1\'b0; + end + + res_cd = 4\'bxxxx; + res_cd[s3] = 1\'b0; + if (res_cd !== 4\'b0xxx) begin + $display(""Failed res_cd[s3], expected 4\'b0xxx, got %b"", res_cd); + passed = 1\'b0; + end + + res_cd = 4\'bxxxx; + res_cd[s4] = 1\'b0; + if (res_cd !== 4\'b0xxx) begin + $display(""Failed res_cd[s4], expected 4\'b0xxx, got %b"", res_cd); + passed = 1\'b0; + end + + if (passed) $display(""Compare tests passed""); + end +endmodule +" +"module top; + enum bit [3:0] {first, second, third, fourth, last = -4\'sd1} my_type; + initial $display(""PASSED""); +endmodule +" +"// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Tests signal initializers. + +module vhdl_init_testbench; + vhdl_init dut(); + + initial begin + // Simply check if the assigned values are correct + if (dut.a !== \'b11101001) begin + $display(""FAILED #1: expected 11101001, got %b"", dut.a); + $finish; + end + + if (dut.b !== \'b1010) begin + $display(""FAILED #2: expected 1010, got %b"", dut.b); + $finish; + end + + if (dut.c !== \'b1000) begin + $display(""FAILED #3: expected 1000, got %b"", dut.c); + $finish; + end + + $display(""PASSED""); + end +endmodule +" +"// +// Verifies that the PRNG seed streams are unique, well trys anyway. +// +module test; + reg [31:0] rtn; + reg [31:0] pseed, seed1, seed2; + reg [31:0] mem1[3:0], mem2[3:0]; + integer i; + + initial begin +\tseed1 = 32\'hcafe_babe; +\tseed2 = 32\'hdead_beef; + +\t// Isolated stream +\tfor (i = 0; i < 4; i = i + 1) begin +\t mem1[i] = $random(seed1); +\tend + +\t// Pull from multiple streams +\tseed1 = 32\'hcafe_babe; +\tseed2 = 32\'hdead_beef; +\tfor (i = 0; i < 4; i = i + 1) begin +\t mem2[i] = $random(seed1); +\t // pull more values from other pools +\t rtn = $random(seed2); +\t rtn = $random; +\tend + +\t// Verify the seed1 streams match +\tfor (i = 0; i < 4; i = i + 1) begin +\t if (mem1[i] != mem2[i]) begin +\t\t$display(""FAILED %0d: %x != %x"", i, mem1[i], mem2[i]); +\t\t$finish; +\t end +\tend + +\t$display(""PASSED""); +\t$finish; + end +endmodule +" +"module check (input unsigned [22:0] a, b, c); + wire [22:0] int_AB; + + assign int_AB = ~(a & b); + +always @(a, b, int_AB, c) begin + #1; + if (int_AB != c) begin + $display(""ERROR""); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [22:0] A, B); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; B= 0; + for (i=0; i> 1) + begin // { + #1 ; + if(out !== rslt) + begin // { + $display(""FAILED - GA XNOR a=%h,b=%h,expct=%h - rcvd=%h"", + a,b,rslt,out); + error = 1; + end // } + end // } + end // } + if( error == 0) + $display(""PASSED""); + end // } +endmodule // main +" +"`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module test(); + +reg [4:1] value; + +reg failed; + +initial begin + failed = 0; + value = 4\'b0000; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + value[5] = 1\'b1; +`endif + $display(""%b"", value); + if (value !== 4\'b0000) failed = 1; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + value[5:5] = 1\'b1; +`endif + $display(""%b"", value); + if (value !== 4\'b0000) failed = 1; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + value[5:4] = 2\'b11; +`else + value[4] = 1\'b1; +`endif + $display(""%b"", value); + if (value !== 4\'b1000) failed = 1; + + if (failed) + $display(""FAILED""); + else + $display(""PASSED""); +end + +endmodule +" +"package fooPkg; + localparam FOO = 5; +endpackage + +package barPkg; + function int get_size ( + input int x + ); + return x + 3; + endfunction +endpackage + +package bazPkg; + typedef int baz; +endpackage + +/* +IEEE 1800-2012 A.1.2 says: + +module_nonansi_header ::= + { attribute_instance } module_keyword [ lifetime ] module_identifier + { package_import_declaration } [ parameter_port_list ] list_of_ports ; +module_ansi_header ::= + { attribute_instance } module_keyword [ lifetime ] module_identifier + { package_import_declaration } [ parameter_port_list ] [ list_of_port_declarations ] ; + +This allows for the importing of packages during module definition which can be used in the + parameter and port lists. +*/ + +module foo +// Testing comman separated imports +import + fooPkg::*, + barPkg::*; +// Testing multiple import statements +import bazPkg::*; +#( + parameter FOO_PARAM = FOO +) +( + input [get_size(7)-1:0] inport +); + + baz value = 11; + + initial begin + if ($bits(inport) != 10) begin + $display(""FAILED -- function import in module declaration failed (%d)"", $bits(inport)); + $finish; + end + + if (value != 11) begin + $display(""FAILED -- Something is wrong with typedef import (%d)"", value); + $finish; + end + + if (FOO_PARAM != 5) begin + $display(""FAILED -- Something is wrong with paramater imports (%d)"", FOO_PARAM); + $finish; + end + + $display(""PASSED""); + $finish; + end + +endmodule +" +" +// This simple program tests that a variable can be assigned +// party by continuous assignment, and partly by behavioral +// assignment. As long as the parts don\'t overlap, this is +// legal (in SystemVerilog) + +module main; + + logic [3:0] foo; + + // Part of the vector is assigned by continuous assignment + logic [1:0] bar; + assign foo[2:1] = bar; + + initial begin + // Part of the vector is assigned behaviorally. + foo[0:0] = 1\'b1; + foo[3:3] = 1\'b1; + bar = 2\'b00; + + #1 if (foo !== 4\'b1001) begin +\t $display(""FAILED -- foo=%b"", foo); +\t $finish; + end + + $display(""PASSED""); + $finish; + end // initial begin + +endmodule // main +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - always force reg_lvalue = boolean_expr ; +// D: This is an infinite loop - thus compile only + +module main ; + +reg [3:0] value1 ; + +initial + begin + #15; + if(value1 != 4\'b1) + $display(""FAILED - 3.1.3E always force reg_lvalue = boolean_expr;\ +""); + else +\tbegin + $display(""PASSED\ +""); +\t $finish; + end + end + +always force value1 = 1\'b1 & 1\'b1 ; + +endmodule +" +"module tb; + +reg [1:0] i, j; +reg [3:0] x[0:2]; +reg error; + +initial begin + error = 0; + + i = 0; + j = i++; + if (i !== 2\'b01 || j !== 2\'b00) begin + $display(""FAILED j = i++ --> j=%b, i=%b"", j, i); + error = 1; + end + + i = 0; + x[0] = 4\'dx; + x[1] = 4\'dx; + x[i++] = 0; + if (x[0] !== 4\'d0 || x[1] !== 4\'dx) begin + $display(""FAILED x[i++] = 0 --> x[0]=%b, x[1]=%b, i=%b"", x[0], x[1], i); + error = 1; + end + + i = 0; + x[0] = 1; + x[i++] += 2; + if (x[0] !== 4\'d3) begin + $display(""FAILED x[0] should be 3, but it is %d."", x[0]); + error = 1; + end + if (i !== 2\'d1) begin + $display(""FAILED i should be 1, but it is %d."", i); + error = 1; + end + if (error == 0) + $display(""PASSED""); +end +endmodule // tb +" +"/* + * Copyright (c) 1998-2000 Andrei Purdea (andrei@purdea.ro) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// This test checks that returning from a void function works correctly. +module main; + int res = 123; + function void bla(); + int i; + for (i=0;i<10;i=i+1) begin + res = i; + $display(""loop %d"", i); + if (i == 5) + begin + return; + end + end + endfunction + initial begin + bla(); + if (res == 5) begin + $display(""PASS""); + end else begin + $display(""FAIL""); + end + end +endmodule +" +"`timescale 1 ps / 1 ps +module use_wid_gt_zero_assert ( +); + +parameter width = 1; +parameter option = ""OFF""; + +reg [width-1:0] dst; + +initial +begin + dst = (option == ""ON"") ? {width{1\'b1}} : {width{1\'b0}}; + if (dst === 1\'b0) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module top; + reg pass; + real rval; + reg [7:0] res; + + initial begin + pass = 1\'b1; + res = 6.0; + if (res !== 8\'d6) begin + $display(""Failed blocking assignment, expeted 6, got %d"", res); + pass = 1\'b0; + end + + // The compiler is generating bad code for a NB-assign with a real r-value. + res <= 7.0; + #1 if (res !== 8\'d7) begin + $display(""Failed nonblocking assignment, expeted 7, got %d"", res); + pass = 1\'b0; + end + rval = 8.0; + res <= rval; + #1 if (res !== 8\'d8) begin + $display(""Failed nonblocking assignment, expeted 8, got %d"", res); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module Main(); + + logic[2:0] a = 3\'b111; + logic signed[2:0] a_signed = 3\'b111; + + logic[2:0] b = 0; + + logic[3:0] c0; + logic[3:0] c1; + + initial begin + c0 = 4\'($signed(a)) + b; + c1 = 4\'(a_signed) + b; + + $display(""c0: %b"", c0); + $display(""c1: %b"", c1); + + if (c0 === 4\'b1111 && c1 === 4\'b1111) + $display(""PASSED""); + else + $display(""FAILED""); + end + +endmodule +" +"// +// Copyright (c) 1999 Peter Monta (pmonta@imedia.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module main; + parameter PARM = 2; + reg [3:0] b; + wire [1:0] a; + + assign a = b[3:(3-PARM+1)] + 1; + + initial begin + b = 4\'b1011; + #1; + if (a===2\'b11) + $display(""PASSED""); + else + $display(""FAILED""); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue <= @ event_identifier boolean_expression +// D: There is a dependency here between this and event keyword and -> + +module main ; + +reg [3:0] value1 ; +event event_ident ; + +initial +begin + # 5 -> event_ident ; +end + +initial + begin + if(value1 !== 4\'bxxxx) +\t$display(""FAILED - always reg_lvalue <= @ event_identifier boolean_expression\ +""); + #10 ; + if(value1 != 4\'b1) +\t$display(""FAILED - always reg_lvalue <= @ event_identifier boolean_expression\ +""); + else + begin + $display(""PASSED\ +""); + $finish ; + end + end + +always value1 <= @ event_ident 1\'b1 && 1\'b1 ; + + +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate continuous xor in assignment..dependent on always ^ working +// + + +module main; + +reg globvar; + +reg [3:0] var1,var2,var3; +wire [3:0] var3a; +reg error; + +assign var3a = var1 ^ var2; + +always @( var1 or var2) + var3 = var1 ^ var2 ; + +initial +begin +error = 0; +for ( var1 = 4\'b0; var1 != 4\'hf; var1 = var1 + 1) + for ( var2 = 4\'b0; var2 != 4\'hf; var2 = var2 + 1) + begin + #1 ; + if(var3 != var3a) + begin + $display(""FAILED continuous xor 1=%h,2=%h,3=%h,3a=%h"", + var1,var2,var3,var3a); + error = 1; + end + #1; + end +if(error == 0) + $display(""PASSED""); +end + +endmodule // main +" +"// Use the default timescale. +module top; + initial begin + $printtimescale(top); + $printtimescale(other); + $printtimescale(other2); + end +endmodule + +`timescale 1ms/1ms + +// Use the given timescale. +module other; +endmodule + +`resetall + +// Use the default timescale. +module other2; +endmodule +" +"// Copyright 2007, Martin Whitaker. +// This file may be freely copied for any purpose. +module memory_monitor(); + +reg [7:0] Memory[0:15]; + +reg [3:0] Index; + +wire Flag1; +wire FlagI; + +assign Flag1 = (Memory[1] == 0); + +assign FlagI = (Memory[Index] == 0); + +initial begin + Index = 1; + Memory[Index] = 0; + #1 $display(""Flag1 = %b, FlagI = %b"", Flag1, FlagI); + Memory[Index] = 1; + #1 $display(""Flag1 = %b, FlagI = %b"", Flag1, FlagI); +end + +endmodule +" +"module top; + reg pass; + integer val; + + initial begin + pass = 1\'b1; + + // Check ARS in a fully signed context. + // All operands are signed. + val = -1; + val = 7\'sd10 + (val >>> 1); + if (val !== 9) begin + $display(""Failed ARS in signed context, got %d"", val); + pass = 1\'b0; + end + + // Check ARS in a cast signed context. + // This is fully signed as well because of the cast. + val = -1; + val = $signed(7\'d10) + (val >>> 1); + if (val !== 9) begin + $display(""Failed ARS in cast signed context, got %d"", val); + pass = 1\'b0; + end + // Check ARS in a self determined context. + // The system function is a primary and should create a self-determined + // context for the ARS. The addition is then done in an unsigned + // context, but this should still give the correct result. + // + // The bug is that Icarus is not sign padding the ARS since the + // addition is casting it to be unsigned. It should only be able to + // cast the sign of the result not the actual ARS! This casting is + // happening in suppress_binary_operand_sign_if_needed() defined in + // elab_expr.cc. It looks like $signed and $unsigned need some way + // to protect their argument self-determined context. + val = -1; + val = 7\'d10 + $signed(val >>> 1); + if (val !== 9) begin + $display(""Failed ARS in $signed context, got %d"", val); + pass = 1\'b0; + end + // Check ARS in a different self determined context. + // See comments above for $signed. + val = -1; + val = 7\'d10 + $unsigned(val >>> 1); + if (val !== 9) begin + $display(""Failed ARS in $unsigned context, got %d"", val); + pass = 1\'b0; + end + + // Check ARS in a different self determined context. + val = -1; + val = 7\'d10 + {val >>> 1}; + if (val !== 9) begin + $display(""Failed ARS in a concatenation context, got %d"", val); + pass = 1\'b0; + end + if (pass) $display(""PASSED""); + end +endmodule +" +"/* + * Copyright (c) 2001 Brendan J Simon + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +//**************************************************************************** +// +// MODULE : parameter_test +// +// DESCRIPTION : Test module to demonstrate parameter evaluation bug. +// +// AUTHOR : Brendan J Simon (brendan.simon@bigpond.com) +// +// DATE : Monday 5th January 2001. +// +// NOTES : It seems that Icarus Verilog 0.4 does not evaluate +// moderately complex parameter statements properly. +// +//**************************************************************************** + +module parameter_test; + + +parameter foo_size = 32 * 6; +parameter foo_lsb = 0; + +`ifdef GOOD_CODE + parameter foo_msb_temp = foo_lsb + foo_size; + parameter foo_msb = foo_msb_temp - 1; +`else + parameter foo_msb = foo_lsb + foo_size - 1; +`endif + + +// These complex statements work; +parameter temp0 = 1 + 2 + 3 + 4 + 5; +parameter temp1 = 1 + 2 + 3 + 4 + 5 - 1; + +reg [foo_msb:foo_lsb] foo; +integer i; + + +initial begin + for (i=0; i MSB). +module top; + parameter [-4:-1] ap = 4\'h1; + parameter [-4:-1] bp = 4\'he; + parameter [-3:0] cp = 4\'h1; + parameter [-3:0] dp = 4\'he; + + reg passed; + + wire [-4:-1] a = 4\'h1; + wire [-4:-1] b = 4\'he; + wire [0:0] s0 = 0; + wire [1:0] s1 = 0; + wire [2:0] s2 = 0; + reg [-4:-1] ar = 4\'h1; + reg [-4:-1] br = 4\'he; + + wire [-3:0] c = 4\'h1; + wire [-3:0] d = 4\'he; + wire [0:0] s3 = 0; + wire [1:0] s4 = 0; + reg [-3:0] cr = 4\'h1; + reg [-3:0] dr = 4\'he; + + wire res_a0 = a[s0]; + wire res_b0 = b[s0]; + wire res_a1 = a[s1]; + wire res_b1 = b[s1]; + wire res_a2 = a[s2]; + wire res_b2 = b[s2]; + + wire res_c3 = c[s3]; + wire res_d3 = d[s3]; + wire res_c4 = c[s4]; + wire res_d4 = d[s4]; + + reg [-4:-1] res_ab; + reg [-3:0] res_cd; + + initial begin + #1; + passed = 1\'b1; + + // Check procedural R-value variable bit selects of a net. + + $display(""a[s0]: %b"", a[s0]); + if (a[s0] !== 1\'bx) begin + $display(""Failed a[s0], expected 1\'bx, got %b"", a[s0]); + passed = 1\'b0; + end + + $display(""b[s0]: %b"", b[s0]); + if (b[s0] !== 1\'bx) begin + $display(""Failed b[s0], expected 1\'bx, got %b"", b[s0]); + passed = 1\'b0; + end + + $display(""a[s1]: %b"", a[s1]); + if (a[s1] !== 1\'bx) begin + $display(""Failed a[s1], expected 1\'bx, got %b"", a[s1]); + passed = 1\'b0; + end + + $display(""b[s1]: %b"", b[s1]); + if (b[s1] !== 1\'bx) begin + $display(""Failed b[s1], expected 1\'bx, got %b"", b[s1]); + passed = 1\'b0; + end + + $display(""a[s2]: %b"", a[s2]); + if (a[s2] !== 1\'bx) begin + $display(""Failed a[s2], expected 1\'bx, got %b"", a[s2]); + passed = 1\'b0; + end + + $display(""b[s2]: %b"", b[s2]); + if (b[s2] !== 1\'bx) begin + $display(""Failed b[s2], expected 1\'bx, got %b"", b[s2]); + passed = 1\'b0; + end + + $display(""c[s3]: %b"", c[s3]); + if (c[s3] !== 1\'b1) begin + $display(""Failed c[s3], expected 1\'b1, got %b"", c[s3]); + passed = 1\'b0; + end + + $display(""d[s3]: %b"", d[s3]); + if (d[s3] !== 1\'b0) begin + $display(""Failed d[s3], expected 1\'b0, got %b"", d[s3]); + passed = 1\'b0; + end + + $display(""c[s4]: %b"", c[s4]); + if (c[s4] !== 1\'b1) begin + $display(""Failed c[s4], expected 1\'b1, got %b"", c[s4]); + passed = 1\'b0; + end + + $display(""d[s4]: %b"", d[s4]); + if (d[s4] !== 1\'b0) begin + $display(""Failed d[s4], expected 1\'b0, got %b"", d[s4]); + passed = 1\'b0; + end + + // Check procedural R-value variable bit selects of a parameter. + + $display(""ap[s0]: %b"", ap[s0]); + if (ap[s0] !== 1\'bx) begin + $display(""Failed ap[s0], expected 1\'bx, got %b"", ap[s0]); + passed = 1\'b0; + end + + $display(""bp[s0]: %b"", bp[s0]); + if (bp[s0] !== 1\'bx) begin + $display(""Failed bp[s0], expected 1\'bx, got %b"", bp[s0]); + passed = 1\'b0; + end + + $display(""ap[s1]: %b"", ap[s1]); + if (ap[s1] !== 1\'bx) begin + $display(""Failed ap[s1], expected 1\'bx, got %b"", ap[s1]); + passed = 1\'b0; + end + + $display(""bp[s1]: %b"", bp[s1]); + if (bp[s1] !== 1\'bx) begin + $display(""Failed bp[s1], expected 1\'bx, got %b"", bp[s1]); + passed = 1\'b0; + end + + $display(""ap[s2]: %b"", ap[s2]); + if (ap[s2] !== 1\'bx) begin + $display(""Failed ap[s2], expected 1\'bx, got %b"", ap[s2]); + passed = 1\'b0; + end + + $display(""bp[s2]: %b"", bp[s2]); + if (bp[s2] !== 1\'bx) begin + $display(""Failed bp[s2], expected 1\'bx, got %b"", bp[s2]); + passed = 1\'b0; + end + + $display(""cp[s3]: %b"", cp[s3]); + if (cp[s3] !== 1\'b1) begin + $display(""Failed cp[s3], expected 1\'b1, got %b"", cp[s3]); + passed = 1\'b0; + end + + $display(""dp[s3]: %b"", dp[s3]); + if (dp[s3] !== 1\'b0) begin + $display(""Failed dp[s3], expected 1\'b0, got %b"", dp[s3]); + passed = 1\'b0; + end + + $display(""cp[s4]: %b"", cp[s4]); + if (cp[s4] !== 1\'b1) begin + $display(""Failed cp[s4], expected 1\'b1, got %b"", cp[s4]); + passed = 1\'b0; + end + + $display(""dp[s4]: %b"", dp[s4]); + if (dp[s4] !== 1\'b0) begin + $display(""Failed dp[s4], expected 1\'b0, got %b"", dp[s4]); + passed = 1\'b0; + end + + // Check procedural R-value variable bit selects of a reg. + + $display(""ar[s0]: %b"", ar[s0]); + if (ar[s0] !== 1\'bx) begin + $display(""Failed ar[s0], expected 1\'bx, got %b"", ar[s0]); + passed = 1\'b0; + end + + $display(""br[s0]: %b"", br[s0]); + if (br[s0] !== 1\'bx) begin + $display(""Failed br[s0], expected 1\'bx, got %b"", br[s0]); + passed = 1\'b0; + end + + $display(""ar[s1]: %b"", ar[s1]); + if (ar[s1] !== 1\'bx) begin + $display(""Failed ar[s1], expected 1\'bx, got %b"", ar[s1]); + passed = 1\'b0; + end + + $display(""br[s1]: %b"", br[s1]); + if (br[s1] !== 1\'bx) begin + $display(""Failed br[s1], expected 1\'bx, got %b"", br[s1]); + passed = 1\'b0; + end + + $display(""ar[s2]: %b"", ar[s2]); + if (ar[s2] !== 1\'bx) begin + $display(""Failed ar[s2], expected 1\'bx, got %b"", ar[s2]); + passed = 1\'b0; + end + + $display(""br[s2]: %b"", br[s2]); + if (br[s2] !== 1\'bx) begin + $display(""Failed br[s2], expected 1\'bx, got %b"", br[s2]); + passed = 1\'b0; + end + + $display(""cr[s3]: %b"", cr[s3]); + if (cr[s3] !== 1\'b1) begin + $display(""Failed cr[s3], expected 1\'b1, got %b"", cr[s3]); + passed = 1\'b0; + end + + $display(""dr[s3]: %b"", dr[s3]); + if (dr[s3] !== 1\'b0) begin + $display(""Failed dr[s3], expected 1\'b0, got %b"", dr[s3]); + passed = 1\'b0; + end + + $display(""cr[s4]: %b"", cr[s4]); + if (cr[s4] !== 1\'b1) begin + $display(""Failed cr[s4], expected 1\'b1, got %b"", cr[s4]); + passed = 1\'b0; + end + + $display(""dr[s4]: %b"", dr[s4]); + if (dr[s4] !== 1\'b0) begin + $display(""Failed dr[s4], expected 1\'b0, got %b"", dr[s4]); + passed = 1\'b0; + end + + // Check continuous assignment R-value variable bit selects. + + if (res_a0 !== 1\'bx) begin + $display(""Failed res_a0, expected 1\'bx, got %b"", res_a0); + passed = 1\'b0; + end + + if (res_b0 !== 1\'bx) begin + $display(""Failed res_b0, expected 1\'bx, got %b"", res_b0); + passed = 1\'b0; + end + + if (res_a1 !== 1\'bx) begin + $display(""Failed res_a1, expected 1\'bx, got %b"", res_a1); + passed = 1\'b0; + end + + if (res_b1 !== 1\'bx) begin + $display(""Failed res_b1, expected 1\'bx, got %b"", res_b1); + passed = 1\'b0; + end + + if (res_a2 !== 1\'bx) begin + $display(""Failed res_a2, expected 1\'bx, got %b"", res_a2); + passed = 1\'b0; + end + + if (res_b2 !== 1\'bx) begin + $display(""Failed res_b2, expected 1\'bx, got %b"", res_b2); + passed = 1\'b0; + end + + if (res_c3 !== 1\'b1) begin + $display(""Failed res_c3, expected 1\'b1, got %b"", res_c3); + passed = 1\'b0; + end + + if (res_d3 !== 1\'b0) begin + $display(""Failed res_d3, expected 1\'b0, got %b"", res_d3); + passed = 1\'b0; + end + + if (res_c4 !== 1\'b1) begin + $display(""Failed res_c4, expected 1\'b1, got %b"", res_c4); + passed = 1\'b0; + end + + if (res_d4 !== 1\'b0) begin + $display(""Failed res_d4, expected 1\'b0, got %b"", res_d4); + passed = 1\'b0; + end + + // Check procedural L-value variable bit selects. + + res_ab = 4\'bxxxx; + res_ab[s0] = 1\'b0; + if (res_ab !== 4\'bxxxx) begin + $display(""Failed res_ab[s0], expected 4\'bxxxx, got %b"", res_ab); + passed = 1\'b0; + end + + res_ab = 4\'bxxxx; + res_ab[s1] = 1\'b0; + if (res_ab !== 4\'bxxxx) begin + $display(""Failed res_ab[s1], expected 4\'bxxxx, got %b"", res_ab); + passed = 1\'b0; + end + + res_ab = 4\'bxxxx; + res_ab[s2] = 1\'b0; + if (res_ab !== 4\'bxxxx) begin + $display(""Failed res_ab[s2], expected 4\'bxxxx, got %b"", res_ab); + passed = 1\'b0; + end + + res_cd = 4\'bxxxx; + res_cd[s3] = 1\'b0; + if (res_cd !== 4\'bxxx0) begin + $display(""Failed res_cd[s3], expected 4\'bxxx0, got %b"", res_cd); + passed = 1\'b0; + end + + res_cd = 4\'bxxxx; + res_cd[s4] = 1\'b0; + if (res_cd !== 4\'bxxx0) begin + $display(""Failed res_cd[s4], expected 4\'bxxx0, got %b"", res_cd); + passed = 1\'b0; + end + + if (passed) $display(""Compare tests passed""); + end +endmodule +" +"module test(); + +reg [3:0] IN; +wire [3:0] OUT; + +assign OUT = IN; + +initial begin + #1 $peek(IN[2:1]); + #0 $display(""display :%b"", OUT); + #1 $force(IN[2:1]); + #1 $peek(IN[2:1]); + #0 $display(""display :%b"", OUT); + #1 $release(IN[2:1]); + #0 $display(""display :%b"", OUT); + #1 $force(IN[2:1]); + #1 $peek(IN[2:1]); + #0 $display(""display :%b"", OUT); + #1 $poke(IN[2:1]); + #1 $peek(IN[2:1]); + #0 $display(""display :%b"", OUT); + #1 $release(IN[2:1]); + #0 $display(""display :%b"", OUT); + #1 $poke(IN[2:1]); + #1 $peek(IN[2:1]); + #0 $display(""display :%b"", OUT); +end + +endmodule +" +"module top; + reg pass = 1\'b1; + + integer count; + reg [2:0] icount; + reg clk = 0; + reg [3:0] in = 4\'h0; + reg [7:0] result; + + always #10 clk = ~clk; + always #20 in = in + 4\'h1; + + initial begin + count = 3; + result[3:0] <= repeat(count) @(posedge clk) in; + if ($simtime != 0 || result !== 8\'bx) begin + $display(""Failed repeat(3) blocked at %0t, expected 8\'hxx, got %h"", + $simtime, result); + pass = 1\'b0; + end + @(result); + if ($simtime != 50 || result !== 8\'hx0) begin + $display(""Failed repeat(3) at %0t, expected 8\'hx0, got %h"", + $simtime, result); + pass = 1\'b0; + end + + #15; + count = 0; + result[7:4] <= repeat(count) @(posedge clk) in; + @(result); // Reals happen faster so they can use an #0, vectors are slower. + if ($simtime != 65 || result !== 8\'h30) begin + $display(""Failed repeat(0) at %0t, expected 8\'h30, got %h"", + $simtime, result); + pass = 1\'b0; + end + + #20; + count = -1; + result[8:5] <= repeat(count) @(posedge clk) in; + @(result); // Reals happen faster so they can use an #0, vectors are slower. + if ($simtime != 85 || result !== 8\'h90) begin + $display(""Failed repeat(-1) at %0t, expected 8\'h80, got %h"", + $simtime, result); + pass = 1\'b0; + end + + #20; + result[7:4] <= @(posedge clk) 4\'h0; + result[7:4] <= @(posedge clk) in; // This one sets the final value. + @(result); + if ($simtime != 110 || result !== 8\'h50) begin + $display(""Failed @ at %0t, expected 8\'h50, got %h"", + $simtime, result); + pass = 1\'b0; + end + + icount = 3\'d2; + result[3:0] <= @(posedge clk) 4\'h1; + result[7:4] <= repeat(icount) @(posedge clk) 4\'h2; + result[1:-2] <= repeat(3) @(posedge clk) 4\'h3; + @(result); + if ($simtime != 130 || result !== 8\'h51) begin + $display(""Failed first @ at %0t, expected 8\'h51, got %h"", + $simtime, result); + pass = 1\'b0; + end + @(result); + if ($simtime != 150 || result !== 8\'h21) begin + $display(""Failed second @ at %0t, expected 8\'h21, got %h"", + $simtime, result); + pass = 1\'b0; + end + @(result); + if ($simtime != 170 || result !== 8\'h20) begin + $display(""Failed third @ at %0t, expected 8\'h20, got %h"", + $simtime, result); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + $finish; + end +endmodule +" +"`begin_keywords ""1364-2005"" +module test; + reg [800:1] string; + integer code; + real f; + + initial begin + string = ""1e1""; + code = $sscanf(string, ""%f"", f); + if (f != 10.0) $display(""FAILED: got %f"", f); + else $display(""PASSED""); + end +endmodule +`end_keywords +" +"int num1 = 201; string str1 = ""unit2""; +int num2 = 202; string str2 = ""unit2""; +int num3 = 203; string str3 = ""unit2""; + +module m3(); + + int num2 = 232; string str2 = ""m3""; + + initial begin + #2; // allow m1 to go first + m2.m1inst.obj.display; + $display(""%d from %s"", num1, str1); + $display(""%d from %s"", num2, str2); + $display(""%d from %s"", num3, str3); + $display(""%d from %s"", m4.num4, m4.str4); + end + +/* This should not change the result, but Icarus ignores the order in + which variables are declared and used. + int num3 = 113; string str3 = ""m3""; +*/ + +endmodule + + +module m4(); + + int num1 = 241; string str1 = ""m4""; + int num2 = 242; string str2 = ""m4""; + int num3 = 243; string str3 = ""m4""; + int num4 = 244; string str4 = ""m4""; + + m3 m3inst(); + +endmodule +" +"/* + * This is the crux of PR487. + */ + +module test(); + +parameter[1:4] async_wrport = 4\'b1100; +reg async_wri; +reg[1:4] async_i; + +initial begin + for(async_i=1;async_i<=4;async_i=async_i+1) begin + async_wri=async_wrport[async_i]; + $display(""async_wrport[%d] --> %b"", async_i, async_wri); + end +end +endmodule +" +"`define DEV_TYPE ""DEVICE 2"" + +module top; + parameter device = `DEV_TYPE; + wire res; + +function is_dev1; + input[8*20:1] device; + reg is_device; +begin + if ((device == ""DEVICE1"") || (device == ""DEVICE 1"")) + is_device = 1; + else + is_device = 0; + + is_dev1 = is_device; +end +endfunction + +function is_dev2; + input[8*20:1] device; + reg is_device; +begin + if ((device == ""DEVICE2"") || (device == ""DEVICE 2"")) + is_device = 1; + else + is_device = 0; + + is_dev2 = is_device; +end +endfunction + +function is_dev; + input[8*20:1] device; + reg is_device; +begin +// Changing this to a single item makes things work. + if (is_dev1(device) || is_dev2(device)) + is_device = 1; + else + is_device = 0; + + is_dev = is_device; +end +endfunction + + assign res = (is_dev(device) == 1) ? 1\'b1 : 1\'b0; + + initial #1 if (res == 1\'b1) $display(""PASSED""); + else $display(""FAILED""); +endmodule +" +"module top; + reg passed = 1\'b1; + real rval = 1.0; + wire real rvar [1:0]; + + assign rvar[0] = -1.0; + assign rvar[1] = 2.0*rval; + + initial begin + #1; + if (rvar[0] != -1.0) begin + $display(""Failed: real wire array[0], expected -1.0, got %g"", rvar[0]); + passed = 1\'b0; + end + + if (rvar[1] != 2.0) begin + $display(""Failed: real wire array[1], expected 2.0, got %g"", rvar[1]); + passed = 1\'b0; + end + + rval = 2.0; + #1; + if (rvar[1] != 4.0) begin + $display(""Failed: real wire array[1], expected 4.0, got %g"", rvar[1]); + passed = 1\'b0; + end + + if (passed) $display(""PASSED""); + end +endmodule +" +"// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +module br987_test; +logic clk_i, clk_ib, clk_o; +bug3 dut(clk_i, clk_ib, clk_o); + +initial begin + // it is enough to have the test unit compiled + $display(""PASSED""); +end + +endmodule + +" +"module main; + + reg [1:0] a, b; + reg\t flag; + + (* ivl_combinational *) + always @(a, b) + flag = a && b; + + (* ivl_synthesis_off *) + initial begin + a = 1; + b = 0; + #1 if (flag !== 0) begin +\t $display(""FAILED -- a=%b, b=%b, flag=%b"", a, b, flag); +\t $finish; + end + + b = 2; + #1 if (flag !== 1) begin +\t $display(""FAILED -- a=%b, b=%b, flag=%b"", a, b, flag); +\t $finish; + end + + $display(""PASSED""); + + end + +endmodule // main +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate unary nand ~&(value) +// + + +module main; + +reg [3:0] vect; +reg\terror; +wire\tresult; + +assign result = ~&(vect); + +initial + begin + error = 0; + for(vect=4\'b000;vect<4\'b1111;vect = vect + 1) + begin + #1; + if(result !== 1\'b1) + begin + $display(""FAILED - Unary nand ~&(%b)=%b"",vect,result); + error = 1\'b1; + end + end + #1; + vect = 4\'b1111; + #1; + if(result !== 1\'b0) + begin + $display(""FAILED - Unary nand ~&(%b)=%b"",vect,result); + error = 1\'b1; + end + if(error === 0 ) + $display(""PASSED""); + end + +endmodule // main +" +"module top; + parameter NAME = ""def""; + wire i = 0; + + generate + case(NAME) + ""test"" : assign i = 1\'b1; + default : ; + endcase + endgenerate + + initial begin + #1 if (i !== 1\'b0) $display(""FAILED""); + else $display(""PASSED""); + end +endmodule +" +"// Regression test for GitHub issue #37 +module test; + wire [5:0] a; + wire [15:0] y; + + assign a = ~0; + assign y = 1 ? ~a >>> 5 : 0; + + initial begin + #10 $display(""%b"", y); + if (y === 16\'b1111111111111110) + $display(""PASSED""); + else + $display(""FAILED""); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate continuous >> in assignment..dependent on always >> working +// + + +module main; + +reg globvar; + +reg [3:0] var1,var2,var3; +wire [3:0] var3a; +reg error; + +assign var3a = var1 >> var2; + +always @( var1 or var2) + var3 = var1 >> var2 ; + +initial +begin +error =0; +for ( var1 = 4\'b0; var1 != 4\'hf; var1 = var1 + 1) + for ( var2 = 4\'b0; var2 != 4\'hf; var2 = var2 + 1) + begin + #1 ; + if(var3 != var3a) + begin + $display(""FAILED continuous >> 1=%h,2=%h,3=%h,3a=%h"", + var1,var2,var3,var3a); + error = 1; + end + #1; + end +if(error == 0) + $display(""PASSED""); +end + +endmodule // main +" +"/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program tests the magic $signed system function. + */ + +module main; + + reg [3:0] a; + + initial begin + a = 4\'d12; + + // The expression should not change the bit pattern in any way + if ($signed(a) !== 4\'b1100) begin +\t $display(""FAILED -- $signed(%b) === %b"", a, $signed(a)); +\t $finish; + end + + if ($signed(a) == 4) begin +\t $display(""FAILED -- $signed(%b) == 4"", a); +\t $finish; + end + + // The >= should do a signed comparison here. + if ($signed(a) >= 0) begin +\t $display(""FAILED -- $signed(%b) > 0"", a); +\t $finish; + end + + $display(""PASSED""); + end // initial begin + +endmodule +" +"module top; + + reg [7:0] a; + reg [7:0] b; + reg [7:0] c; + + integer retcode; + + + initial + begin + #0; // avoid T0 race +\t a = 0; +\t b = 0; +\t c = 0; +\t /* Use VPI to set values on these registers */ +\t retcode = $example(a, b, c); + end + + always @(a) + $display(""%t The value of A is: %b"", $time, a); + + always @(b) + $display(""%t The value of B is: %b"", $time, b); + + always @(c) + $display(""%t The value of C is: %b"", $time, c); + +endmodule // top +" +"module nested_func(); + +function automatic real sum; + +input real a; +input real b; + +begin + sum = a + b; +end + +endfunction + +real r1; +real r2; +real r3; + +initial begin + r1 = sum(sum(2, 3), sum(4, 5)); + r2 = sum(3, sum(4, sum(5, 6))); + r3 = sum(sum(sum(4, 5), 6), 7); + $display(""sum of 2 to 5 = %0d"", r1); + $display(""sum of 3 to 6 = %0d"", r2); + $display(""sum of 4 to 7 = %0d"", r3); +end + +endmodule +" +"/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +`timescale 1ns / 1ns + +module U1 (OUT); + + parameter VALUE = -384; + + output [9:0] OUT; + + assign\tOUT = VALUE; + +endmodule + +module U2 (OUT); + + parameter VALUE = 96; + + output [9:0] OUT; + + assign\tOUT = VALUE; + +endmodule + +module main; + wire [9:0] out1, out2; + + U1 u1 (out1); + U2 u2 (out2); + + initial #1 begin + if (out1 !== 10\'h280) begin +\t $display(""FAILED -- out1 = %b"", out1); +\t $finish; + end + + if (out2 !== 10\'h060) begin +\t $display(""FAILED -- out2 = %b"", out2); +\t $finish; + end + + $display(""PASSED""); + end // initial #1 +endmodule // main +" +"// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test file_open() function. + +module file_open_test; +logic active, ok; +vhdl_file_open dut(active, ok); + +initial begin + active = 1; + #1; + if(ok !== 1\'b1) begin + $display(""FAILED""); + $finish(); + end + + $display(""PASSED""); +end +endmodule +" +"// This tests unalligned write/read access to packed structures +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test; + + typedef struct packed { + logic [7:0] high; + logic [7:0] low; + } word_t; + + // Declare word* as a VARIABLE + word_t word_se0, word_se1, word_se2, word_se3; + word_t word_sw0, word_sw1, word_sw2, word_sw3; + word_t word_sp0, word_sp1, word_sp2, word_sp3; + word_t word_ep0, word_ep1, word_ep2, word_ep3; + + // error counter + bit err = 0; + + // access to structure elements + assign word_se1.high = {8+0{1\'b1}}; + assign word_se1.low = {8+0{1\'b0}}; + assign word_se2.high = {8+1{1\'b1}}; + assign word_se2.low = {8+1{1\'b0}}; + assign word_se3.high = {8-1{1\'b1}}; + assign word_se3.low = {8-1{1\'b0}}; + // access to whole structure + assign word_sw1 = {16+0{1\'b1}}; + assign word_sw2 = {16+1{1\'b1}}; + assign word_sw3 = {16-1{1\'b1}}; + // access to parts of structure elements + assign word_ep1.high [3:0] = {4+0{1\'b1}}; + assign word_ep1.low [3:0] = {4+0{1\'b0}}; + assign word_ep2.high [3:0] = {4+1{1\'b1}}; + assign word_ep2.low [3:0] = {4+1{1\'b0}}; + assign word_ep3.high [3:0] = {4-1{1\'b1}}; + assign word_ep3.low [3:0] = {4-1{1\'b0}}; + // access to parts of the whole structure + assign word_sp1 [11:4] = {8+0{1\'b1}}; + assign word_sp2 [11:4] = {8+1{1\'b1}}; + assign word_sp3 [11:4] = {8-1{1\'b1}}; + + initial begin + #1; + // access to structure elements + if (word_se0 !== 16\'bxxxxxxxx_xxxxxxxx) begin $display(""FAILED -- word_se0 = \'b%b"", word_se0 ); err=1; end + if (word_se1 !== 16\'b11111111_00000000) begin $display(""FAILED -- word_se1 = \'b%b"", word_se1 ); err=1; end + if (word_se1.high !== 8\'b11111111 ) begin $display(""FAILED -- word_se1.high = \'b%b"", word_se1.high); err=1; end + if (word_se1.low !== 8\'b00000000 ) begin $display(""FAILED -- word_se1.low = \'b%b"", word_se1.low ); err=1; end + if (word_se2 !== 16\'b11111111_00000000) begin $display(""FAILED -- word_se2 = \'b%b"", word_se2 ); err=1; end + if (word_se2.high !== 8\'b11111111 ) begin $display(""FAILED -- word_se2.high = \'b%b"", word_se2.high); err=1; end + if (word_se2.low !== 8\'b00000000 ) begin $display(""FAILED -- word_se2.low = \'b%b"", word_se2.low ); err=1; end + if (word_se3 !== 16\'b01111111_00000000) begin $display(""FAILED -- word_se3 = \'b%b"", word_se3 ); err=1; end + if (word_se3.high !== 8\'b01111111 ) begin $display(""FAILED -- word_se3.high = \'b%b"", word_se3.high); err=1; end + if (word_se3.low !== 8\'b00000000 ) begin $display(""FAILED -- word_se3.low = \'b%b"", word_se3.low ); err=1; end + // access to whole structure + if (word_sw0 !== 16\'bxxxxxxxx_xxxxxxxx) begin $display(""FAILED -- word_sw0 = \'b%b"", word_sw0 ); err=1; end + if (word_sw1 !== 16\'b11111111_11111111) begin $display(""FAILED -- word_sw1 = \'b%b"", word_sw1 ); err=1; end + if (word_sw2 !== 16\'b11111111_11111111) begin $display(""FAILED -- word_sw2 = \'b%b"", word_sw2 ); err=1; end + if (word_sw3 !== 16\'b01111111_11111111) begin $display(""FAILED -- word_sw3 = \'b%b"", word_sw3 ); err=1; end + // access to parts of structure elements + if (word_ep0 !== 16\'bxxxxxxxx_xxxxxxxx) begin $display(""FAILED -- word_ep0 = \'b%b"", word_ep0 ); err=1; end + if (word_ep1 !== 16\'bxxxx1111_xxxx0000) begin $display(""FAILED -- word_ep1 = \'b%b"", word_ep1 ); err=1; end + if (word_ep1.high !== 8\'bxxxx1111 ) begin $display(""FAILED -- word_ep1.high = \'b%b"", word_ep1.high); err=1; end + if (word_ep1.low !== 8\'bxxxx0000 ) begin $display(""FAILED -- word_ep1.low = \'b%b"", word_ep1.low ); err=1; end + if (word_ep2 !== 16\'bxxxx1111_xxxx0000) begin $display(""FAILED -- word_ep2 = \'b%b"", word_ep2 ); err=1; end + if (word_ep2.high !== 8\'bxxxx1111 ) begin $display(""FAILED -- word_ep2.high = \'b%b"", word_ep2.high); err=1; end + if (word_ep2.low !== 8\'bxxxx0000 ) begin $display(""FAILED -- word_ep2.low = \'b%b"", word_ep2.low ); err=1; end + if (word_ep3 !== 16\'bxxxx0111_xxxx0000) begin $display(""FAILED -- word_ep3 = \'b%b"", word_ep3 ); err=1; end + if (word_ep3.high !== 8\'bxxxx0111 ) begin $display(""FAILED -- word_ep3.high = \'b%b"", word_ep3.high); err=1; end + if (word_ep3.low !== 8\'bxxxx0000 ) begin $display(""FAILED -- word_ep3.low = \'b%b"", word_ep3.low ); err=1; end + // access to parts of the whole structure + if (word_sp0 !== 16\'bxxxxxxxx_xxxxxxxx) begin $display(""FAILED -- word_sp0 = \'b%b"", word_sp0 ); err=1; end + if (word_sp1 !== 16\'bxxxx1111_1111xxxx) begin $display(""FAILED -- word_sp1 = \'b%b"", word_sp1 ); err=1; end + if (word_sp2 !== 16\'bxxxx1111_1111xxxx) begin $display(""FAILED -- word_sp2 = \'b%b"", word_sp2 ); err=1; end + if (word_sp3 !== 16\'bxxxx0111_1111xxxx) begin $display(""FAILED -- word_sp3 = \'b%b"", word_sp3 ); err=1; end + + if (!err) $display(""PASSED""); + end + +endmodule // test +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate function within a continuous assignment + +module main (); + +reg error; +reg [3:0] val2; + + +function [3:0] myfunc ; + input [31:0] in1 ; + myfunc = in1; +endfunction + +wire [3:0] val1; +assign val1 = myfunc(val2); + +initial + begin + error = 0; + val2 = 4\'h0; + # 1 ; + if(val1 !== 4\'b0) + begin + $display(""FAILED - function3.11D - function within continuous assign(1)""); + error = 1; + end + + val2 = 32\'h8; + # 1 ; + if(val1 !== val2) + begin + $display(""FAILED - function3.11D - function within continuous assign(2)""); + error = 1; + end + + if(error == 0) + $display(""PASSED""); + end + +endmodule // main +" +"/* + * This program demonstrates non-constant part selects + * applied to a signal value. + */ +module main; + + wire [31:0] foo = 32\'h76543210; + + reg [3:0] tmp; + reg [3:0] idx; + + initial begin + #1 /* Wait for initial assignments to settle. */ ; + + if (foo[0 +: 4] !== 4\'h0) begin +\t $display(""FAILED -- %b !== 0"", foo[0 +: 4]); +\t $finish; + end + + if (foo[4 +: 4] !== 4\'h1) begin +\t $display(""FAILED -- %b !== 1"", foo[4 +: 4]); +\t $finish; + end + + if (foo[8 +: 4] !== 4\'h2) begin +\t $display(""FAILED -- %b !== 2"", foo[8 +: 4]); +\t $finish; + end + + if (foo[12+: 4] !== 4\'h3) begin +\t $display(""FAILED -- %b !== 3"", foo[12 +: 4]); +\t $finish; + end + + for (idx = 0 ; idx < 8 ; idx = idx + 1) begin +\t tmp = foo[(idx*4) +: 4]; +\t if (tmp !== idx) begin +\t $display(""FAILED -- %b !== %b"", idx, tmp); +\t $finish; +\t end + + end + + for (idx = 0 ; idx < 8 ; idx = idx + 1) begin +\t tmp = foo[(idx*4+3) -: 4]; +\t if (tmp !== idx) begin +\t $display(""FAILED -- %b !== %b"", idx, tmp); +\t $finish; +\t end + + end + + $display(""PASSED""); + end + +endmodule // main +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate casex/endcase w/ null_statement as default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 or val2) + casex (val1 & val2 ) + 3\'b000,3\'b001: result = 0; + 3\'b11x: result = 2; + 3\'b001: result = 1; + default result = 3; + endcase + +initial + begin + error = 0; + + val1 = 3\'b0; + val2 = 3\'b0; + if(result !=0) + begin + $display(""FAILED casex 3.9E - default: ""); + error = 1; + end + + val1 = 3\'b001; + val2 = 3\'b011; + if(result !=1) + begin + $display(""FAILED casex 3.9E - default: ""); + error = 1; + end + + + val1 = 3\'b111;\t// Should get no-action - expr = 3\'b010 + val2 = 3\'b010; + if(result !=3) + begin + $display(""FAILED casex 3.9E - default: ""); + error = 1; + end + + if(error == 0) + $display(""PASSED""); + end + +endmodule // main +" +"`begin_keywords ""1364-2005"" +module top; + localparam string = ""ab""; + localparam rg_res = string & 9\'h1ff; + + reg passed; + integer fd, res; + reg [8:0] rg; + reg [7:0] mem [31:0]; + + initial begin + passed = 1\'b1; + + fd = $fopen(""ThisFileDoesNotExist.txt"", ""r""); + + res = $fread(rg, fd); // Try to read from an invalid fd. + if (res != 0) begin + $display(""$fread (register fd) count is wrong, expected 0, got %0d"", res); + passed = 1\'b0; + end + if (rg !== 9\'bx) begin + $display(""$fread (register fd) value is wrong, expected 9\'bx, got %b"", + rg); + passed = 1\'b0; + end + + fd = $fopen(""ivltests/fread.txt"", ""r""); + + res = $fread(mem, fd, -1); // Try an invalid start + if (res != 0) begin + $display(""$fread (mem. start) count is wrong, expected 0, got %0d"", res); + passed = 1\'b0; + end + if (mem[0] !== 8\'bx) begin + $display(""$fread (mem. start[0]) value is wrong, expected 8\'bx, got %b"", + mem[0]); + passed = 1\'b0; + end + if (mem[15] !== 8\'bx) begin + $display(""$fread (mem. start[15]) value is wrong, expected 8\'bx, got %b"", + mem[15]); + passed = 1\'b0; + end + if (mem[31] !== 8\'bx) begin + $display(""$fread (mem. start[31]) value is wrong, expected 8\'bx, got %b"", + mem[31]); + passed = 1\'b0; + end + + // Check $fread with a register value. + res = $fread(rg, fd); // Load with the lower nine bits of ""ab"". + if (res != 2) begin + $display(""$fread (register) count is wrong, expected 2, got %0d"", res); + passed = 1\'b0; + end + if (rg !== rg_res) begin + $display(""$fread (register) value is wrong, expected %b, got %b"", + rg_res, rg); + passed = 1\'b0; + end + + // Check $fread with a memory. + res = $fread(mem, fd, 0, 2); // Load 0 with ""0"" and 1 with ""1"". + if (res != 2) begin + $display(""$fread (mem. 1) count is wrong, expected 2, got %0d"", res); + passed = 1\'b0; + end + if (mem[0] !== ""0"") begin + $display(""$fread (mem. 1[0]) value is wrong, expected %b, got %b"", + ""0"", mem[0]); + passed = 1\'b0; + end + if (mem[1] !== ""1"") begin + $display(""$fread (mem. 1[1]) value is wrong, expected %b, got %b"", + ""1"", mem[1]); + passed = 1\'b0; + end + + res = $fread(mem, fd, 31); // Load 31 with ""z"". + if (res != 1) begin + $display(""$fread (mem. 2) count is wrong, expected 1, got %0d"", res); + passed = 1\'b0; + end + if (mem[31] !== ""z"") begin + $display(""$fread (mem. 2[31]) value is wrong, expected %b, got %b"", + ""z"", mem[31]); + passed = 1\'b0; + end + + res = $fread(mem, fd, 31, 2); // Load 31 with ""y"" and warns. + if (res != 1) begin + $display(""$fread (mem. 3) count is wrong, expected 1, got %0d"", res); + passed = 1\'b0; + end + if (mem[31] !== ""y"") begin + $display(""$fread (mem. 3[31]) value is wrong, expected %b, got %b"", + ""y"", mem[31]); + passed = 1\'b0; + end + + res = $fread(mem, fd); // Load with repeated ""0"" .. ""9"" pattern. + if (res != 32) begin + $display(""$fread (mem. 4) count is wrong, expected 32, got %0d"", res); + passed = 1\'b0; + end + // Just check the end values and a value in the middle (15). + if (mem[0] !== ""0"") begin + $display(""$fread (mem. 4[0]) value is wrong, expected %b, got %b"", + ""0"", mem[0]); + passed = 1\'b0; + end + if (mem[15] !== ""5"") begin + $display(""$fread (mem. 4[15]) value is wrong, expected %b, got %b"", + ""5"", mem[15]); + passed = 1\'b0; + end + if (mem[31] !== ""1"") begin + $display(""$fread (mem. 4[31]) value is wrong, expected %b, got %b"", + ""1"", mem[31]); + passed = 1\'b0; + end + + // This only gets the trailing new line. + rg = 9\'bx; + res = $fread(rg, fd); + if (res != 1) begin + $display(""$fread (EOL) count is wrong, expected 1, got %0d"", res); + passed = 1\'b0; + end + if (rg !== 9\'h0xx) begin + $display(""$fread (EOL value is wrong, expected 9\'b0xx, got %b"", rg); + passed = 1\'b0; + end + + // There are no bits left so this array should be the same. + res = $fread(mem, fd); + if (res != 0) begin + $display(""$fread (mem. EOL) count is wrong, expected 0, got %0d"", res); + passed = 1\'b0; + end + // Just check the end values and a value in the middle (15). + if (mem[0] !== ""0"") begin + $display(""$fread (mem. EOL[0]) value is wrong, expected %b, got %b"", + ""0"", mem[0]); + passed = 1\'b0; + end + if (mem[15] !== ""5"") begin + $display(""$fread (mem. EOL[15]) value is wrong, expected %b, got %b"", + ""5"", mem[15]); + passed = 1\'b0; + end + if (mem[31] !== ""1"") begin + $display(""$fread (mem. EOL[31]) value is wrong, expected %b, got %b"", + ""1"", mem[31]); + passed = 1\'b0; + end + + $fclose(fd); + + if (passed) $display(""PASSED""); + else $display(""FAILED""); + end +endmodule +`end_keywords +" +"module test; + +parameter TRUE = 1; + +genvar i; +genvar j; + +for (i = 0; i < 2; i = i + 1) begin : l1 + reg r1 = 1; +end + +for (i = 0; i < 2; i = i + 1) begin : l2 + for (j = 0; j < 2; j = j + 1) begin : l1 + reg r2 = 1; + end +end + +for (i = 0; i < 2; i = i + 1) begin : l3 + case (TRUE) + 0: begin : c1 + reg r3a = 1; + end + 1: begin : c1 + reg r3b = 1; + end + endcase +end + +for (i = 0; i < 2; i = i + 1) begin : l4 + if (TRUE) + begin : i1 + reg r4a = 1; + end + else + begin : i1 + reg r4b = 1; + end +end + +for (i = 0; i < 2; i = i + 1) begin : l5 + if (!TRUE) + begin : i1 + reg r5a = 1; + end + else + begin : i1 + if (TRUE) + begin : i1 + reg r5b = 1; + end + else + begin : i1 + reg r5c = 1; + end + end +end + +for (i = 0; i < 2; i = i + 1) begin : l6 + if (!TRUE) + begin : i1 + reg r6a = 1; + end + else + begin : i1 + if (!TRUE) + begin : i1 + reg r6b = 1; + end + else + begin : i1 + reg r6c = 1; + end + end +end + +case (TRUE) + 0: begin : c1 + reg r7a = 1; + end + 1: begin : c1 + reg r7b = 1; + end +endcase + +case (TRUE) + 0: begin : c2 + case (TRUE) + 0: begin : c1 + reg r8a = 1; + end + 1: begin : c1 + reg r8b = 1; + end + endcase + end + 1: begin : c2 + case (TRUE) + 0: begin : c1 + reg r8c = 1; + end + 1: begin : c1 + reg r8d = 1; + end + endcase + end +endcase + +case (TRUE) + 0: begin : c3 + if (TRUE) + begin : i1 + reg r9a = 1; + end + else + begin : i1 + reg r9b = 1; + end + end + 1: begin : c3 + if (TRUE) + begin : i1 + reg r9c = 1; + end + else + begin : i1 + reg r9d = 1; + end + end +endcase + +case (TRUE) + 0: begin : c4 + if (!TRUE) + begin : i1 + reg r10a = 1; + end + else + begin : i1 + if (TRUE) + begin : i1 + reg r10b = 1; + end + else + begin : i1 + reg r10c = 1; + end + end + end + 1: begin : c4 + if (!TRUE) + begin : i1 + reg r10d = 1; + end + else + begin : i1 + if (TRUE) + begin : i1 + reg r10e = 1; + end + else + begin : i1 + reg r10f = 1; + end + end + end +endcase + +case (TRUE) + 0: begin : c5 + if (!TRUE) + begin : i1 + reg r11a = 1; + end + else + begin : i1 + if (!TRUE) + begin : i1 + reg r11b = 1; + end + else + begin : i1 + reg r11c = 1; + end + end + end + 1: begin : c5 + if (!TRUE) + begin : i1 + reg r11d = 1; + end + else + begin : i1 + if (!TRUE) + begin : i1 + reg r11e = 1; + end + else + begin : i1 + reg r11f = 1; + end + end + end +endcase + +case (TRUE) + 0: begin : c6 + if (!TRUE) + begin : i1 + reg r12a = 1; + end + else if (TRUE) + begin : i1 + reg r12b = 1; + end + else + begin : i1 + reg r12c = 1; + end + end + 1: begin : c6 + if (!TRUE) + begin : i1 + reg r12d = 1; + end + else if (TRUE) + begin : i1 + reg r12e = 1; + end + else + begin : i1 + reg r12f = 1; + end + end +endcase + +case (TRUE) + 0: begin : c7 + if (!TRUE) + begin : i1 + reg r13a = 1; + end + else if (!TRUE) + begin : i1 + reg r13b = 1; + end + else + begin : i1 + reg r13c = 1; + end + end + 1: begin : c7 + if (!TRUE) + begin : i1 + reg r13d = 1; + end + else if (!TRUE) + begin : i1 + reg r13e = 1; + end + else + begin : i1 + reg r13f = 1; + end + end +endcase + +if (TRUE) + begin : i01 + reg r14a = 1; + end +else + begin : i01 + reg r14b = 1; + end + +if (!TRUE) + begin : i02 + reg r15a = 1; + end +else + begin : i02 + if (TRUE) + begin : i1 + reg r15b = 1; + end + else + begin : i1 + reg r15c = 1; + end + end + +if (!TRUE) + begin : i03 + reg r16a = 1; + end +else + begin : i03 + if (!TRUE) + begin : i1 + reg r16b = 1; + end + else + begin : i1 + reg r16c = 1; + end + end + +if (!TRUE) + begin : i04 + reg r17a = 1; + end +else if (TRUE) + begin : i04 + reg r17b = 1; + end +else + begin : i04 + reg r17c = 1; + end + +if (!TRUE) + begin : i05 + reg r18a = 1; + end +else if (!TRUE) + begin : i05 + reg r18b = 1; + end +else + begin : i05 + reg r18c = 1; + end + +if (TRUE) + begin : i06 + if (TRUE) + begin : i1 + reg r19a = 1; + end + else + begin : i1 + reg r19b = 1; + end + end +else + begin : i06 + reg r19c = 1; + end + +if (TRUE) + begin : i07 + if (!TRUE) + begin : i1 + reg r20a = 1; + end + else + begin : i1 + reg r20b = 1; + end + end +else + begin : i07 + reg r20c = 1; + end + +if (TRUE) + begin : i08 + case (TRUE) + 0: begin : c1 + reg r21a = 1; + end + 1: begin : c1 + reg r21b = 1; + end + endcase + end +else + begin : i08 + case (TRUE) + 0: begin : c1 + reg r21c = 1; + end + 1: begin : c1 + reg r21d = 1; + end + endcase + end + +if (!TRUE) + begin : i09 + case (TRUE) + 0: begin : c1 + reg r22a = 1; + end + 1: begin : c1 + reg r22b = 1; + end + endcase + end +else if (TRUE) + begin : i09 + case (TRUE) + 0: begin : c1 + reg r22c = 1; + end + 1: begin : c1 + reg r22d = 1; + end + endcase + end +else + begin : i09 + case (TRUE) + 0: begin : c1 + reg r22e = 1; + end + 1: begin : c1 + reg r22f = 1; + end + endcase + end + +if (!TRUE) + begin : i10 + case (TRUE) + 0: begin : c1 + reg r23a = 1; + end + 1: begin : c1 + reg r23b = 1; + end + endcase + end +else if (!TRUE) + begin : i10 + case (TRUE) + 0: begin : c1 + reg r23c = 1; + end + 1: begin : c1 + reg r23d = 1; + end + endcase + end +else + begin : i10 + case (TRUE) + 0: begin : c1 + reg r23e = 1; + end + 1: begin : c1 + reg r23f = 1; + end + endcase + end + +initial begin + $list_regs; +end + +endmodule +" +"module test(output [7:0] dataout[1:0]); + +assign dataout[0] = 8\'h55; +assign dataout[1] = 8\'haa; + +initial begin + #0; + if (dataout[0] === 8\'h55 && dataout[1] === 8\'haa) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module main; + + reg [7:0] mem [7:0], D; + reg [3:0] radr, wadr; + reg\t wr, clk; + + /* + * This implements the synchronous write port to the memory. + */ + always @(posedge clk) + if (wr) mem[wadr] <= D; + + // This is the asynchronous read port from the memory. + wire[7:0] Q = mem[radr]; + + (* ivl_synthesis_off *) + initial begin + wr = 0; + clk = 0; + #1 clk = 1; + #1 clk = 0; + + for (wadr = 0 ; wadr < 8 ; wadr = wadr+1) begin +\t wr = 1; +\t D = { 2{wadr} }; +\t #1 clk = 1; +\t #1 clk = 0; + end + + wr = 0; + for (radr = 0 ; radr < 8 ; radr = radr+1) begin +\t #1 if (Q !== {2{radr}}) begin +\t $display(""FAILED -- mem[%d] == \'b%b"", radr, Q); +\t $finish; +\t end + end + + $display(""PASSED""); + end +endmodule +" +"module test(); + wire x, y; +a__a a_( +.b_buf(y), +.b (x) +); +endmodule + +module a__a(b_buf, b); +output b_buf; +input b; +endmodule // a__a +" +" +module dut (output reg[31:0] size, +\t output reg signed [31:0] ival, +\t output reg [31:0] hval); + parameter string foo = ""1234""; + string\t tmp; + real\t\t rval; + + initial begin + size = foo.len(); + ival = foo.atoi(); + hval = foo.atohex(); + rval = foo.atoreal(); + + tmp = foo; + $display(""foo=%0s, tmp=%0s"", foo, tmp); + if (tmp != foo) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""rval=%f"", rval); + if (rval != ival) begin +\t $display(""FAILED -- rval=%f, ival=%0d"", rval, ival); +\t $finish; + end + end +endmodule // dut + +module main; + + wire [31:0] dut0_size, dut1_size, dut2_size; + wire signed [31:0] dut0_ival, dut1_ival, dut2_ival; + wire unsigned [31:0] dut0_hval, dut1_hval, dut2_hval; + + + // Instantate module with string parameter, use default value. + dut dut0 (dut0_size, dut0_ival, dut0_hval); + + // Instantate module with string parameter, use override value. + dut #(.foo(""12345"")) dut1 (dut1_size, dut1_ival, dut1_hval); + + // Instantate module with string parameter, use defparam value. + defparam dut2.foo = ""123456""; + dut dut2 (dut2_size, dut2_ival, dut2_hval); + + initial begin + #100 ; + $display(""dut0_size=%0d"", dut0_size); + if (dut0_size !== 4) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""dut1_size=%0d"", dut1_size); + if (dut1_size !== 5) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""dut2_size=%0d"", dut2_size); + if (dut2_size !== 6) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""dut0_ival=%0d"", dut0_ival); + if (dut0_ival !== 1234) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""dut1_ival=%0d"", dut1_ival); + if (dut1_ival !== 12345) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""dut2_ival=%0d"", dut2_ival); + if (dut2_ival !== 123456) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""dut0_hval=%0h"", dut0_hval); + if (dut0_hval !== 32\'h1234) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""dut1_hval=%0h"", dut1_hval); + if (dut1_hval !== 32\'h12345) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""dut2_hval=%0h"", dut2_hval); + if (dut2_hval !== 32\'h123456) begin +\t $display(""FAILED""); +\t $finish; + end + $display(""PASSED""); + $finish; + end +endmodule // main +" +"module top; + real var1, var2; + reg [7:0] bvar; + reg result; + + wire r_a = &var1; + wire r_o = |var1; + wire r_x = ^var1; + wire r_na = ~&var1; + wire r_no = ~|var1; + wire r_xn1 = ~^var1; + wire r_xn2 = ^~var1; + + wire r_b_a = var1 & var2; + wire r_b_o = var1 | var2; + wire r_b_x = var1 ^ var2; + wire r_b_na = var1 ~& var2; + wire r_b_no = var1 ~| var2; + wire r_b_xn1 = var1 ~^ var2; + wire r_b_xn2 = var1 ^~ var2; + + wire r_eeq = var1 === var2; + wire r_neeq = var1 !== var2; + + wire r_ls = var1 << var2; + wire r_als = var1 <<< var2; + wire r_rs = var1 >> var2; + wire r_ars = var1 >>> var2; + + wire r_con = {var1}; + wire r_rep = {2.0{var1}}; + + initial begin + var1 = 1.0; + var2 = 2.0; + + #1; + + /* These should all fail in the compiler. */ + result = &var1; + result = |var1; + result = ^var1; + result = ~&var1; + result = ~|var1; + result = ~^var1; + result = ^~var1; + + result = var1 & var2; + result = var1 | var2; + result = var1 ^ var2; + result = var1 ~& var2; + result = var1 ~| var2; + result = var1 ~^ var2; + result = var1 ^~ var2; + + result = var1 === var2; + result = var1 !== var2; + + bvar = var1 << var2; + bvar = var1 <<< var2; + bvar = var1 >> var2; + bvar = var1 >>> var2; + + bvar = {var1}; + bvar = {2.0{var1}}; + + $display(""Failed""); + end +endmodule +" +"/* pr1623097 */ +`timescale 1ns/1ns + + +module top; + + reg [3:0] state; + reg [3:0] data; + reg [3:0] clear; + reg clk; + + genvar i; + + initial begin + #0; // avoid time-0 race + clk = 0; data = 4\'b1111; clear = 4\'b1111; + $monitor($time,,""clk=%b, data=%b, clear=%b, state=%b"", +\t clk, data, clear, state); + + #10 clear = 4\'b0000; + #10 clk = 1; + #10 clk = 0; clear = 4\'b0010; + #10 clear = 4\'b0000; data = 4\'b1010; + #10 clk = 1; + #10 clk = 0; + end + + + // This fails! + generate for (i=0; i<4; i=i+1) begin:sm + always @(posedge clk or posedge clear[i]) begin + if (clear[i]) state[i] <= 1\'b0; // Async. clear the flip bit. + else begin + state[i] <= #1 data[i]; + end + end + end endgenerate + + + + + + + + + + + + + + + + + + + + + + + + + + + +endmodule +" +" module RegisterArrayBug01; + + reg [15:0] rf[0:7]; + + wire [15:0] rf_0 = rf[1]; + + initial begin + $monitor($time,, ""rf[0] is %h %h"", rf[1], rf_0); + + rf[1] = 16\'hffff; + #10 rf[1] = 16\'h0000; + #10 rf[1] = 16\'hbeef; + #10 $finish(0); + end + + endmodule + + /* + System prints: + 0 rf[0] is xxxx ffff + 10 rf[0] is xxxx 0000 + 20 rf[0] is beef beef + Expected is: + 0 rf[0] is ffff ffff + 10 rf[0] is 0000 0000 + 20 rf[0] is beef beef + */ +" +"module test; + reg a,b; + integer x; + initial begin + x=10; + + // ok + a=x; + + // fails at run time with + // vvm_func.cc:49: failed assertion `v.nbits == p.nbits\' + // Abort (core dumped) + b = ~x; + + if (b === 1\'b1) +\t$display(""PASSED""); + else +\t$display(""FAILED --- b = %b"", b); + + end // initial begin +endmodule // test + + + +/* + * Copyright (c) 2000 Gerard A. Allan (gaa@ee.ed.ac.uk) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +" +"module test(); + +wire [7:0] value1; +wire value2; + +assign value1[3:0] = 4\'d2; + +assign value2 = |value1; + +initial begin + #2 $display(""%b %b"", value1, value2); + if (value2 === 1\'b1) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +" /* + * This module is a test bench for the sqrt32 module. It runs some + * test input values through the sqrt32 module, and checks that the + * output is valid. If an invalid output is generated, print and + * error message and stop immediately. If all the tested values pass, + * then print PASSED after the test is complete. + */ +module main; + + reg [31:0] x; + reg\t clk, reset; + + wire [15:0] y; + wire rdy; + + chip_root dut(.clk(clk), .reset(reset), .rdy(rdy), .x(x), .y(y)); + + (* ivl_synthesis_off *) + always #5 clk = !clk; + + task reset_dut; + begin +\t reset = 1; +\t #1 reset = 0; +\t @(negedge clk) ; + end + endtask // reset_dut + + task crank_dut; + begin +\t while (rdy == 0) begin +\t @(posedge clk) /* wait */; +\t end + end + endtask // crank_dut + + reg GSR; + assign glbl.GSR = GSR; + + integer idx; + + (* ivl_synthesis_off *) + initial begin + reset = 0; + clk = 0; + + /* If doing a post-map simulation, when we need to wiggle + The GSR bit to simulate chip power-up. */ + GSR = 1; + #100 GSR = 0; + #100 x = 1; + reset_dut; + crank_dut; + $display(""x=%d, y=%d"", x, y); + + x = 3; + reset_dut; + crank_dut; + $display(""x=%d, y=%d"", x, y); + + x = 4; + reset_dut; + crank_dut; + $display(""x=%d, y=%d"", x, y); + + for (idx = 0 ; idx < 200 ; idx = idx + 1) begin +\t x = $random; +\t reset_dut; +\t crank_dut; +\t $display(""x=%d, y=%d"", x, y); + +\t if (x < (y * y)) begin +\t $display(""ERROR: y is too big""); +\t $finish; +\t end + +\t if (x > ((y + 1)*(y + 1))) begin +\t $display(""ERROR: y is too small""); +\t $finish; +\t end + end + + $display(""PASSED""); + $finish; + end + +endmodule // main +" +"module top; + integer ival; + real rval; + initial begin + $display(""--- Printing as real ---""); + $display(""1/0 is %f. (Should be 0 -- x prints as 0)"", 1/0); + $display(""1/0.0 is %f. (Should be inf)"", 1/0.0); + $display(""1.0/0 is %f. (Should be inf)"", 1.0/0); + $display(""1.0/0.0 is %f. (should be inf)"", 1.0/0.0); + + // Moving these two lines before the previous four lines makes 1/0 print + // a large number, but not inf! + rval = 0.0; + ival = 0; + $display(""1/integer zero is %f. (Should be 0 -- x prints as 0)"", 1/ival); + $display(""1/real zero is %f. (should be inf)"", 1/rval); + $display(""1.0/integer zero is %f. (Should be inf)"", 1.0/ival); + $display(""1.0/real zero is %f."", 1.0/rval); + + $display(""\ +--- Printing as integer ---""); + $display(""1/0 is %d (Should be x)"", 1/0); + $display(""1/0.0 is %d"", 1/0.0); + $display(""1.0/0 is %d"", 1.0/0); + $display(""1.0/0.0 is %d"", 1.0/0.0); + + $display(""1/integer zero is %d. (Should be x)"", 1/ival); + $display(""1/real zero is %d."", 1/rval); + $display(""1.0/integer zero is %d."", 1.0/ival); + $display(""1.0/real zero is %d."", 1.0/rval); + end +endmodule +" +"// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Function with if clause +// +// D: +// + +module main (); + +reg [3:0] global_var; +reg [3:0] result; +// Interesting because 2 * 0 is 0 ;-) +function [3:0] my_func ; +input [3:0] a; +begin + if(a == 4\'b0) + my_func = 4\'b0; + else + my_func = a + a; +end +endfunction + +initial + begin + global_var = 2; + result = my_func(global_var); + + if(result != 4) + begin + $display(""FAILED - function didn\'t function!\ +""); + $finish ; + end + + $display(""PASSED\ +""); + $finish ; + end +endmodule +" +"// +// Copyright (c) 2002 Steven Wilson (steve@ka6s.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Synth of basic reg form +// +// +module basicreg ( clk, d, q); +input clk, d; +output [2:0] q; +reg [2:0] q; + +(* ivl_synthesis_on *) +always @(posedge clk) + begin +\tq[0] <= d; +\tq[1] <= d; +\tq[2] <= d; + end + +endmodule + +module test ; + +reg clk, d; + +wire [2:0] q; + +basicreg u_reg (clk,d,q); + +(* ivl_synthesis_off *) +initial + begin +// $dumpfile(""test.vcd""); +// $dumpvars(0,test); + clk = 0; + d = 0; + # 1; + clk = 1; + # 1; + if (q !== 3\'b0) + begin + $display(""FAILED - Q isn\'t 0 on first edge""); +\t $finish; + end + d = 1; + # 1; + clk = 0; + # 1; + if (q !== 3\'b0) + begin + $display(""FAILED - Q isn\'t 0 after first falling edge""); +\t $finish; + end + # 1; + clk = 1; + # 1; + if (q !== 3\'b111) + begin +\t #1 ; + $display(""FAILED - Q isn\'t 1 2nd raising edge""); +\t $finish; + end + # 1; + clk = 0; + # 1; + if (q !== 3\'b111) + begin + $display(""FAILED - Q isn\'t 1 after 2nd falling edge""); +\t $finish; + end + $display(""PASSED""); + + end +endmodule +" +"`begin_keywords ""1364-2005"" +module top; + reg pass; + reg [3:0] var; + integer lp; + + initial begin + pass = 1\'b1; + for (lp = 0; lp < 16; lp = lp + 1) begin + var = lp; + // This should bit extend var as unsigned and then + // convert it into a signed value. + if (lp !== $signed(var+5\'b0)) begin + $display(""FAILED: expected %2d, got %2d"", lp, $signed(var+5\'b0)); + pass = 1\'b0; + end + end + + if (pass) $display(""PASSED""); + end +endmodule +`end_keywords +" +"/* + * Copyright (c) 2000 Nadim Shaikli + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* This is made up from PR#63 */ +module main; + + reg one, clk; + reg [1:0] a, b, c, passed; + reg [7:0] count; + + always + #1 one = ~one; + + // generate a clock + always + #10 clk = ~clk; + + initial + begin + $display (""\ +<< BEGIN >>""); + one = 1\'b1; + clk = 1\'b0; + passed = 2\'b00; + count = 0; + #15 a[1:0] = 2\'b01; + #10 a[1:0] = 2\'b10; + #20 $display (""\ +<< END >>""); +\tif (passed == 2) + $display (""PASSED""); + else + $display (""FAILED""); + $finish; + end + + always @(clk) + begin + // Problematic lines below -- comment them out to see timing skew + b[1:0] <= #2.5 a[1:0]; + c[1:0] <= #7.8 a[1:0]; + end + + always @(one) + count[7:0] <= count + 1; + + always @(count) + begin + case ( count ) + \'d25: + if (b[1:0] == 2\'b01) + begin + $display (""@ %0t - Got ONE"", $time); + passed = passed + 1; + end + else + $display (""@ %0t - failure"", $time); + \'d29: + if (b[1:0] == 2\'b01) + begin + $display (""@ %0t - Got ONE"", $time); + passed = passed + 1; + end + else + $display (""@ %0t - failure"", $time); + default: + $display (""@ %0t - no count"", $time); + endcase + end + + // Waves definition +// initial +// begin +// $recordvars(""primitives"", ""drivers""); +// $dumpfile(""out.dump""); +// $dumpvars(5, main); +// Line below ought to work +// $dumpvars; +// end + +endmodule // main +" +"module table_out( +\tinput [1:0] a, +\t(* rom_style = ""distributed"" *) output reg signed [9:0] phase +); + +always @(*) case (a) +\t2\'d 0: phase = 0; +\t2\'d 1: phase = 90; +\t2\'d 2: phase = 180; +\t2\'d 3: phase = 270; +endcase + +initial $display(""PASSED""); + +endmodule +" +"module shift; + reg pass = 1\'b1; + integer i; + reg [7:0] foo; + parameter [2:0] + ZERO = 0, + THREE = 3; + + initial begin + foo = 1\'b1 << ZERO; + if (foo != \'d1) begin + $display(""FAILED shift by ZERO, got %d expected 1"", foo); + pass = 1\'b0; + end + + foo = 1\'b1 << THREE; + if (foo != \'d8) begin + $display(""FAILED shift by THREE, got %d expected 8"", foo); + pass = 1\'b0; + end + + foo = 1\'b1 << 3; + if (foo != \'d8) begin + $display(""FAILED shift by 3, got %d expected 8"", foo); + pass = 1\'b0; + end + + foo = 1\'b1 << \'d3; + if (foo != \'d8) begin + $display(""FAILED shift by \'d3, got %d expected 8"", foo); + pass = 1\'b0; + end + + i = \'d3; + foo = 1\'b1 << i; + if (foo != \'d8) begin + $display(""FAILED shift by variable set to \'d3, got %d expected 8"", foo); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4\'d2; + +cmos buffer[7:0](value2, value1, 1\'b1, 1\'b0); + +initial begin + #2 $display(""%b %b"", value1, value2); + if (value2 === 8\'bzzzz0010) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"module top; + reg pass; + reg [3:0] val; + reg [3:0] pv_val; + real rval; + + initial begin + pass = 1\'b1; + + // A release of an unforced variable should not change the variable. + val = 4\'b0110; + release val; + if (val !== 4\'b0110) begin + $display(""Failed release of unforced sig, expected 4\'b0110, got %b"", + val); + pass = 1\'b0; + end + + // Verify that a force/release leaves the variable set correctly. + force val = 4\'b1001; + release val; + if (val !== 4\'b1001) begin + $display(""Failed release of forced sig, expected 4\'b1001, got %b"", + val); + pass = 1\'b0; + end + + // A release of a currently unforced varaible should not change it. + val = 4\'b0110; + release val; + if (val !== 4\'b0110) begin + $display(""Failed release of unforced sig(2), expected 4\'b0110, got %b"", + val); + pass = 1\'b0; + end + + // A release of an unforced variable should not change the variable. + pv_val = 4\'b1001; + release pv_val[1]; + if (pv_val !== 4\'b1001) begin + $display(""Failed pv release of unforced sig, expected 4\'b1001, got %b"", + pv_val); + pass = 1\'b0; + end + + // Verify that a force/release leaves the variable set correctly. + force pv_val[1] = 1\'b1; + release pv_val[2:0]; + if (pv_val !== 4\'b1011) begin + $display(""Failed pv release of forced sig, expected 4\'b1011, got %b"", + pv_val); + pass = 1\'b0; + end + + // A release of a currently unforced varaible should not change it. + pv_val = 4\'b1001; + release pv_val[1]; + if (pv_val !== 4\'b1001) begin + $display(""Failed pv release of unforced sig(2), expected 4\'b1001, got %b"", + pv_val); + pass = 1\'b0; + end + + // A release of an unforced variable should not change the variable. + rval = 1.0; + release rval; + if (rval != 1.0) begin + $display(""Failed release of unforced sig, expected 1.0, got %.1f"", + rval); + pass = 1\'b0; + end + + // Verify that a force/release leaves the variable set correctly. + force rval = 2.0; + release rval; + if (rval != 2.0) begin + $display(""Failed release of forced sig, expected 2.0, got %.1f"", + rval); + pass = 1\'b0; + end + + // A release of a currently unforced varaible should not change it. + rval = 1.0; + release rval; + if (rval != 1.0) begin + $display(""Failed release of unforced sig(2), expected 1.0, got %.1f"", + rval); + pass = 1\'b0; + end + + if (pass) $display(""PASSED""); + end +endmodule +" +"module top; + parameter wid = 9; + + wire [31:0] apass; + wire [31:0] afail; + + assign apass = {(wid-8){ 8'b0}}; // This will pass. + assign afail = {(wid-16){8'b0}}; // and this will fail. +endmodule +" +"/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: ldelay1.v,v 1.2 2007/12/06 02:31:10 stevewilliams Exp $ + +// Test for delays in structural logic. Inertial delays + +module test; + + wire q; + reg a, b; + and #6 (q, a, b); + + task ok; + input qq; + reg error; + begin +\t if (q !== qq) +\t begin +\t error = 1; +\t $display(""%0d: FAILED: q=%b, expect %b"", $time, q, qq); +\t end + end + endtask + + initial + begin +\tok.error = 0; +//\t$dumpvars; +\ta <= 0; +\tb <= 1; +\t#5 ok(1\'b x); +\t#2 ok(1\'b 0); +\ta <= 1; +\t#5 ok(1\'b 0); +\t#2 ok(1\'b 1); +\ta <= 0; +\t#3 ok(1\'b 1); +\ta <= 1; +\t#1 ok(1\'b 1); +\t#1 ok(1\'b 1); +\t#1 ok(1\'b 1); +\t#1 ok(1\'b 1); +\t#1 ok(1\'b 1); +\t#1 ok(1\'b 1); +\t#1 ok(1\'b 1); +\tif (!ok.error) +\t $display(""PASSED""); + end +endmodule +" +"/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This tests the rule in section 2.7.1: + * ""Neither the leading backslash character nor the terminating + * white space is considered to be part of the identifier. There- + * fore, an escaped identifier \\cpu3 is treated the same as a + * non escaped identifier cpu3."" + * + * The cpu3 and \\cpu3 notations are for the same object. + */ + +module top; + + reg \\cpu3 ; + + initial begin + cpu3 = 1; + $display(""cpu3 == %b"", \\cpu3 ); + if (top.\\cpu3 !== cpu3) begin +\t $display(""FAILED -- top.\\\\cpu3 !== cpu3""); +\t $finish; + end + + if (\\top .cpu3 !== \\cpu3 ) begin +\t $display(""FAILED -- \\\\top .cpu3 !== cpu3""); +\t $finish; + end + + if (top.\\cpu3 !== 1) begin +\t $display(""FAILED -- top.\\\\cpu3 !== 1""); +\t $finish; + end + + $display(""PASSED""); + end +endmodule // top +" +"(* foo, bar=1 *) (* baz=1 *) module foo; + initial $display(""PASSED""); +endmodule +" +"module test (); + reg [30:0] a, b; + + initial begin + b = 1; + a = (0 << b); + // $display (""a: %d"", a); + if (a !== 31\'b0) $display(""FAILED""); + else $display(""PASSED""); + end +endmodule +" +"module pr2849783(); + +reg i; +wire a, b, c, d; + +assign a = i; +assign b = a; + +assign c = 1; +assign d = c; + +reg pass; + +initial begin + i = 1; + pass = 1; + #1 $display(""%b %b"", a, b); + if ((a !== 1) || (b !== 1)) pass = 0; + #1 force a = 0; + #1 $display(""%b %b"", a, b); + if ((a !== 0) || (b !== 0)) pass = 0; + #1 release a; + #1 $display(""%b %b"", a, b); + if ((a !== 1) || (b !== 1)) pass = 0; + + #1 $display(""%b %b"", c, d); + if ((c !== 1) || (d !== 1)) pass = 0; + #1 force c = 0; + #1 $display(""%b %b"", c, d); + if ((c !== 0) || (d !== 0)) pass = 0; + #1 release c; + #1 $display(""%b %b"", c, d); + if ((c !== 1) || (d !== 1)) pass = 0; + + if (pass) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Bit select of a net (a wire) using the index of a for loop. + */ + +module main; + + // Make a vector of bits, an array of functors in practice, and + // create a net that hooks to that array backwards. + reg [4:0] vect = 5\'b10100; + wire [4:0] tmp = { vect[0], vect[1], vect[2], vect[3], vect[4] }; + + reg [2:0] idx; + initial begin + #1 $display(""vect=%b, tmp=%b"", vect, tmp); + + for (idx = 0 ; idx < 5 ; idx = idx + 1) begin +\t $display(""idx=%d: vect=%b, tmp=%b"", idx, vect[idx], tmp[idx]); +\t if (tmp[idx] !== vect[4-idx]) begin +\t $display(""FAILED""); +\t $finish; +\t end + end + + $display(""PASSED""); + end + +endmodule // main +" +"/* + I seem to have found a problem with the $monitor task/events. + (this is probably related to bug 399) + The problem only seems to arise in vvp mode and not in vvm. + Problem: $monitor seems to lose both the first and last time steps. + + A complete copy of the run follows with source appended at the end. + (The correct output from vvm is shown in the last run) + This file compiles and produces the problem. + + jungle_geo@hotmail.com + +*/ + +/* + +bubba> uname -a +Linux bubba 2.2.15-4mdk #1 Wed May 10 15:31:30 CEST 2000 i686 unknown + +bubba> iverilog -V +Icarus Verilog version 0.6 +Copyright 1998-2002 Stephen Williams +$Name: $ + +bubba> iverilog -Wall -tvvp stim.v +bubba> a.out +Time = 1 a = 1 + +bubba> iverilog -Wall -tvvm stim.v +bubba> a.out +Time = 0 a = 0 +Time = 1 a = 1 +Time = 2 a = 0 + +*/ + +// -------------------------------------------------------------------------stim +module stim; + reg a; + + initial begin + a = 0; + #1 a = 1; + #1 a = 0; + end + + initial begin + $monitor(""Time = %0d a = %b"", $time, a); + end + +endmodule +" +"module check (input unsigned [22:0] a, b, c); + wire unsigned [22:0] int_AB; + + assign int_AB = a - b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB != c) begin + $display(""ERROR""); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [22:0] A, B); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; B= 0; + for (i=0; i> 1; + parameter PARM16 = PARM08 << 1; + + parameter PARM10 = ((PARM08 <=2) ? 1: + ((PARM08 <=4) ? 2: + ((PARM08 <=8) ? 3:4))); + + // this parameterized input compiles ok + wire [PARM04 : 0] in04; + wire [PARM16 : 0] in05; + + reg [PARM08 : 0] out00; + reg [PARM04 : 0] out04; + reg [PARM16 : 0] out05; + + // this parameterized doesn\'t compile, stack dump + wire [PARM10:0] in99; + + initial begin + if (PARM08 !== 8) begin +\t $display(""FAILED -- PARM08 == %b"", PARM08); +\t $finish; + end + + if (PARM04 !== 4) begin +\t $display(""FAILED -- PARM04 == %b"", PARM04); +\t $finish; + end + + if (PARM16 !== 16) begin +\t $display(""FAILED -- PARM16 == %b"", PARM16); +\t $finish; + end + + + if (PARM10 !== 3) begin +\t $display(""FAILED -- PARM10 == %b"", PARM10); +\t $finish; + end + + $display(""PASSED""); + end + +endmodule +" +"// Eleven basic tests in here: +// 1. longint must be initialised before any initial or always block +// 2. assignments to (signed) longint with random numbers +// 3. assignments to (signed) longint with random values including X and Z +// 4. converting unsigned 64-bit integer time to signed longint +// 5. converting signed integers to signed longint +// 6. converting 64-bit integers including X and Z states to unsigned longint +// 7. trying unsigned sums (procedural, function, task and module) +// 8. trying unsigned mults (procedural, function and task) +// 9. trying relational operators +// 10. smaller signed numbers to unsigned longint (signed extension) +// 11. trying some concatenations from bytes, shortints, ints to longints + +module ms_add (input longint signed a, b, output longint signed sc, ss); + assign sc = a + b; + always @(a, b) ss = a + b; +endmodule + +module main; + parameter N_REPS = 500; // repetition with random numbers + parameter XZ_REPS = 500; // repetition with \'x \'z values + parameter MAX8 = \'h7f; + parameter MAX16 = \'h7fff; + parameter LEN = 64; + // variables used as golden references + reg signed [LEN-1:0] ar; // holds numbers + reg signed [LEN-1:0] ar_xz; // holds \'x and/or \'z in random positions + reg signed [LEN-1:0] ar_expected; + reg unsigned [LEN-1:0] ui; // unsigned 64-bit integer + reg signed [LEN-1:0] si; // signed 64-bit integer + reg signed [LEN/2-1:0] slice; + + // type assumed to be tested before hand + byte signed pt1, pt2; + shortint signed ps1, ps2; + int signed pv1, pv2; + + // types to be tested + longint signed bu; // holds numbers + longint signed bu_xz; // \'x and \'z are attempted on this + longint signed bresult; // hold results from sums and mults + longint signed mcaresult; // wired to a module instance + longint signed mabresult; // also wired to a module instance + + + integer i; + + // continuous assigments + // type LHS type RHS + // --------- --------- + // longint 4-value logic + assign bu = ar; + assign bu_xz = ar_xz; + + // module instantiation + ms_add duv (.a(bu), .b(bu_xz), .sc(mcaresult), .ss(mabresult) ); + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if (bu !== 64\'b0 || bu_xz != 64\'b0 || bresult !== 64\'b0 || mcaresult !== 64\'b0 || mabresult !== 64\'b0) + begin + $display (""FAILED - time zero initialisation incorrect: %b %b"", bu, bu_xz); + $finish; + end + // driving longint type with signed random numbers from a variable + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = { $random, $random }; + #1; + if (bu !== ar) + begin + $display (""FAILED - incorrect assigment to int: %b"", bu); + $finish; + end + end + # 1; + // attempting to drive variables having \'x \'z values into type unsigned longint + // \'x \'z injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + ar = { $random, $random }; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0 + begin + $display (""FAILED - incorrect assigment to longint (when \'x \'z): %b"", bu); + $finish; + end + end + // converting unsigned 64-bit integers (time) to unsigned longint + // this should pass trivially + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ui = { {$random}, {$random} }; + #1; + force bu = ui; + #1; + if (bu !== ui) + begin + $display (""FAILED - incorrect assignment from 64-bit integer to longint: %b"", bu); + $finish; + end + end + release bu; + // converting signed 64-bit integers to unsigned longints + // keeping the same bit representation is expected + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + si = { {$random}, {$random} }; + #1; + force bu = si; + #1; + if (bu !== si) + begin + $display (""FAILED - incorrect assignment from 64-bit signed integer to longint: %d mismatchs %d"", bu, -ui); + $finish; + end + end + release bu; + // converting integers having \'x \'z values into type unsigned longint + // \'x \'z injections (Section 4.3.2 of IEEE 1850 LRM) + // coercion to zero expected + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + ui = { {$random}, {$random} }; + ar_xz = xz_inject (ui); + ui = ar_xz; + ar_expected = xz_expected (ar_xz); + #1; + force bu_xz = ui; + #1; + if (bu_xz !== ar_expected) // \'x -> \'0, \'z -> \'0 + begin + $display (""FAILED - incorrect conversion from 64-bit integer (with \'x \'z) to longint: %b mismatchs %b"", bu_xz, ar_expected); + $finish; + end + end + release bu_xz; + // trying signed sums + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = { $random, $random }; + ar_xz = { $random, $random }; + #1; + bresult = bu + bu_xz; + #1; + if ( bresult !== s_sum(ar, ar_xz) ) + begin + $display (""FAILED - incorrect addition of signed longints: %0d mismatchs %0d"", bresult, s_sum(ar, ar_xz)); + $finish; + end + // invoking longint sum function + if ( fs_sum (bu, bu_xz) !== s_sum(ar, ar_xz) ) + begin + $display (""FAILED - incorrect addition of unsigned longint in function""); + $finish; + end + // invoking longint sum task + ts_sum (bu, bu_xz, bresult); + if ( bresult !== s_sum(ar, ar_xz) ) + begin + $display (""FAILED - incorrect addition of unsigned longint in task: %0d mismatchs %0d"", bresult, s_sum(ar, ar_xz)); + $finish; + end + // checking longint sum from module + if ( mcaresult !== s_sum(ar, ar_xz) || mabresult !== s_sum(ar, ar_xz)) + begin + $display (""FAILED - incorrect addition of signed longtint from module""); + $finish; + end + end + // trying signed mults + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = { $random % 32\'d32768, $random % 32\'d16384 }; + ar_xz = { $random % 32\'d16384, $random % 32\'d32768 }; + #1; + bresult = bu * bu_xz; // truncated mult + #1; + if ( bresult !== sh_mul(ar, ar_xz) ) + begin + $display (""FAILED - incorrect multiplication of signed longints: %0d mismatchs %0d"", bresult, sh_mul(ar, ar_xz)); + $finish; + end + #1; + pv1 = $random; + pv2 = $random; + #1; + bresult = pv1 * pv2; // longint = int x int + #1; + if ( bresult !== s_mul(pv1, pv2) ) + begin + $display (""FAILED - incorrect multiplication of signed longints for int inputs""); + $finish; + end + // invoking longint mult function (int*int) + if ( fs_mul (pv1, pv2) !== s_mul(pv1, pv2) ) + begin + $display (""FAILED - incorrect product of signed ints for a function returning signed longint""); + $finish; + end + // invoking longint mult task (int*int) + ts_mul (pv1, pv2, bresult); + if ( bresult !== s_mul(pv1, pv2) ) + begin + $display (""FAILED - incorrect product of signed int in task returning signed longint""); + $finish; + end + end + // trying relational operators + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = { $random, $random }; + ar_xz = { $random, $random }; + #1; + if ( (bu < bu_xz ) != (ar < ar_xz) ) + begin + $display (""FAILED - incorrect \'less than\' on signed longints""); + $finish; + end + if ( (bu <= bu_xz ) != (ar <= ar_xz) ) + begin + $display (""FAILED - incorrect \'less than or equal\' on signed longints""); + $finish; + end + if ( (bu > bu_xz ) != (ar > ar_xz) ) + begin + $display (""FAILED - incorrect \'greater than\' on signed longints""); + $finish; + end + if ( (bu >= bu_xz ) != (ar >= ar_xz) ) + begin + $display (""FAILED - incorrect \'greater than or equal\' than on signed longints""); + $finish; + end + if ( (bu == bu_xz ) != (ar == ar_xz) ) + begin + $display (""FAILED - incorrect \'equal to\' on signed longints""); + $finish; + end + if ( (bu != bu_xz ) != (ar != ar_xz) ) + begin + $display (""FAILED - incorrect \'not equal to\' on signed ints""); + $finish; + end + end + # 1; + // signed small number to unsigned shorint + for (i = 0; i < N_REPS; i = i+1) + begin + #1; + slice = $random % \'h7fff_ffff; + force bu = slice; + ar = slice; + #1; + if (bu !== ar) + begin + $display (""FAILED - incorrect signed extend to signed longint""); + $finish; + end + end + release bu; + // trying concatenations (and replication) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + pt1 = $random % MAX8; + pt2 = $random % MAX8; + #1; + bresult = { {4{pt1}}, {4{pt2}} }; + #1; + if ( bresult[63:56] !== pt1 || bresult[55:48] !== pt1 || bresult[47:40] !== pt1 || bresult[39:32] !== pt1 || + bresult[31:24] !== pt2 || bresult[23:16] !== pt2 || bresult[15:8] !== pt2 || bresult[7:0] !== pt2) + begin + $display (""FAILED - incorrect concatenation and replication of bytes into signed longints""); + $finish; + end + #1; + ps1 = $random % MAX16; + ps2 = $random % MAX16; + #1; + bresult = { {2{ps1}}, {2{ps2}} }; + #1; + if ( bresult[63:48] !== ps1 || bresult[47:32] !== ps1 || bresult[31:16] !== ps2 || bresult[15:0] !== ps2) + begin + $display (""FAILED - incorrect concatenation and replication of shortint into signed long ints""); + $finish; + end + #1; + pv1 = $random; + pv2 = $random; + #1; + bresult = { pv1, pv2 }; + #1; + if ( bresult[63:32] !== pv1 || bresult[31:0] !== pv2) + begin + $display (""FAILED - incorrect concatenation and replication of int into signed longints""); + $finish; + end + end + #1; + $display(""PASSED""); + end + + // this returns X and Z states into bit random positions for a value + function [LEN-1:0] xz_inject (input signed [LEN-1:0] value); + integer i, k; + time temp; + begin + temp = {$random, $random}; + for (i=0; i P) = (td, td, th, 0, th, 0); + endspecify + + +endmodule +`endcelldefine +" +"// Test disable statements inside a constant function +module constfunc10(); + +function [31:0] pow2(input [5:0] x); + +begin:body + pow2 = 1; + while (1) begin:loop + if (x == 0) disable body; + pow2 = 2 * pow2; + x = x - 1; + disable loop; + pow2 = 0; + end +end + +endfunction + +localparam val = pow2(8); + +initial begin + $display(""%0d"", val); + if (val === 256) + $display(""PASSED""); + else + $display(""FAILED""); +end + +endmodule +" +"/* + * Notice how the port direction and type are declared + * together in each statement. + */ +module one_a(sum,co,a,b,ci); + output reg sum; + output reg co; + input wire a; + input wire b; + input wire ci; + +always@(a or b or ci) + begin + sum = a ^ b ^ ci; + co = a*b || a*ci || b*ci; + end +endmodule + + +module main; + + wire sum, co; + reg [3:0] in; + + one_a dut (sum, co, in[0], in[1], in[2]); + + initial begin + in = 0; + #1 for (in = 0 ; in[3] == 0 ; in = in + 1) begin +\t #1 $display(""in=%b; co/sum = %b/%b"", in, co, sum); + end + end + +endmodule // main +" +"module test(); + +task t(a, b); + $display(a,,b); +endtask + +initial t(0, 1); + +endmodule +" +"module top; + reg [63:0] str; + reg [31:0] in, out; + integer res; + + initial begin + // To avoid embedded NULL bytes each byte must have an x or a 1 and a z. + in = 32\'b000x100z_001z000x_101xxxzz_100z111x; + $sformat(str, ""%z"", in); + res = $sscanf(str, ""%z"", out); + if (res !== 1) $display(""FAILED: $sscanf() returned %d"", res); + else if (in !== out) $display(""FAILED: %b !== %b"", in, out); + else $display(""PASSED""); + end +endmodule +" +"module main; + + function integer my_ceil; + input number; + real number; + if (number > $rtoi(number)) + my_ceil = $rtoi(number) + 1; + else + my_ceil = number; + endfunction + + real tck; + parameter CL_TIME = 13125; + wire [31:0] result1 = my_ceil( CL_TIME/tck ); + integer result2; + initial begin + tck = 2.0; + + result2 = my_ceil( CL_TIME/tck ); + if (result2 !== 6563) begin +\t $display(""FAILED -- result2=%d"", result2); +\t $finish; + end + + #1 if (result1 !== 6563) begin +\t $display(""FAILED -- result1=%d"", result1); +\t $finish; + end + $display(""PASSED""); + end // initial begin + +endmodule // main +" +"// Copyright (c) 2006 Stephen Williams +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module main; + + reg [7:0] mem [0:1]; + + initial begin + mem[0] = 0; + mem[1] = 1; + $memmonitor(mem); + + #1 mem[0] = 4; + #1 mem[1] = 5; + #1 $finish(0); + end + +endmodule // main +" +"// This module generates M pairs of N-1 bits unsigned numbers A, B +// and also serialises them starting from LSB bits between +// activation of active-high reset signal + +module stimulus #(parameter N = 4, M = 10) (input clk, + output reg reset, + output reg sa, sb, + output reg unsigned [N-1:0] A, B ); + +parameter D = 5; +int unsigned i; +reg unsigned [N-1:0] r1, r2; + +initial begin + repeat(M) begin + r1 = {$random} % N; + r2 = {$random} % N; + do_items(r1, r2); + end +end + +task do_items (input unsigned [N-1:0] v1, v2); +begin + A = 0; B = 0; reset = 0; + do_reset(); + A = v1; B = v2; + for (i=0; i