Safetensors
qwen2
observerw commited on
Commit
a53593c
·
verified ·
1 Parent(s): 22f647f

Create README.md

Browse files
Files changed (1) hide show
  1. README.md +109 -0
README.md ADDED
@@ -0,0 +1,109 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ ---
2
+ license: mit
3
+ datasets:
4
+ - observerw/ChiseLLM-Completion
5
+ - observerw/ChiseLLM-Decompile
6
+ base_model:
7
+ - Qwen/Qwen2.5-Coder-7B-Instruct
8
+ ---
9
+
10
+ # ChiseLLM Models
11
+
12
+ <img src="https://raw.githubusercontent.com/observerw/ChiseLLM/refs/heads/main/assets/logo.svg" alt="ChiseLLM" style="width:30%">
13
+
14
+ ![GitHub Repo stars](https://img.shields.io/github/stars/observerw/ChiseLLM)
15
+
16
+ ChiseLLM is a series of **large reasoning models specifically trained for the [Chisel Hardware Construction language](https://www.chisel-lang.org)**, aimed at revolutionizing HCL-Baed Agile Hardware Development Methodology (AHDM).
17
+
18
+ Built on [Qwen/Qwen2.5-Coder-Instruct](https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct) with domain-adaptive fine-tuning, the model combines high-quality reasoning datasets and specific thinking patterns to significantly enhance performance in hardware design tasks.
19
+
20
+ ChiseLLM Models can:
21
+
22
+ - **Transform natural language specifications into high-quality Chisel code** (Spec-to-Chisel)
23
+ - **Intelligently translate Verilog code into enhanced Chisel implementations** (Decompile-to-Chisel)
24
+ - **Generate hardware designs with superior variability and extensibility**, surpassing traditional design approaches
25
+
26
+ ### Use Cases
27
+
28
+ ChiseLLM Models is particularly suited for the following applications:
29
+
30
+ - **Rapid Hardware Design Prototyping**: Dramatically shortens the design cycle from specification to implementation
31
+ - **Verilog Code Modernization**: Intelligently converts legacy Verilog code into extensible Chisel implementations
32
+ - **Hardware Architecture Exploration**: Generates multiple design variants for the same functional requirements
33
+ - **Design Refactoring and Optimization**: Leverages Chisel's advanced features to improve existing hardware designs
34
+ - **Agile Hardware Development Education**: Serves as an assistive tool for learning Chisel and modern hardware design methods
35
+
36
+ ### Training results
37
+
38
+ Spec-to-Chisel task on VerilogEval:
39
+
40
+ | Models | pass@1 | pass@3 | pass@5 | syntax(%) |
41
+ | ------------------------------ | --------- | --------- | --------- | --------- |
42
+ | Llama3.1-8B-Instruct | 4.33 | 9.90 | 13.21 | 9.02 |
43
+ | Qwen2.5-Coder-7B-Instruct | 21.94 | 31.87 | 36.73 | 37.08 |
44
+ | \*Deepseek-R1-Distill-Llama-8B | 9.31 | 15.44 | 17.72 | 16.01 |
45
+ | \*ChiseLLM-7B | **29.41** | **47.08** | **54.04** | **58.82** |
46
+
47
+ | Models | pass@1 | pass@3 | pass@5 | syntax(%) |
48
+ | ------------------------------- | --------- | --------- | --------- | --------- |
49
+ | Qwen2.5-Coder-32B-Instruct | 41.02 | 53.85 | 58.79 | 73.47 |
50
+ | Qwen2.5-72B-Instruct | 39.74 | 49.30 | 52.90 | 61.31 |
51
+ | Llama-3.3-70B-Instruct | 38.14 | 44.90 | 48.02 | 65.97 |
52
+ | \*Deepseek-R1-Distill-Qwen-32B | 38.50 | 54.58 | 61.16 | 52.19 |
53
+ | \*Deepseek-R1-Distill-Llama-70B | 36.62 | 52.28 | 59.90 | 51.72 |
54
+ | \*ChiseLLM-32B | **51.43** | **68.29** | **72.78** | **76.45** |
55
+
56
+ | Models | pass@1 | pass@3 | pass@5 | syntax(%) |
57
+ | ------------- | --------- | --------- | --------- | --------- |
58
+ | Deepseek-V3 | 50.16 | 63.44 | 67.32 | 76.37 |
59
+ | GPT-4o | 42.04 | 60.16 | 65.17 | 69.76 |
60
+ | \*Deepseek-R1 | **62.74** | **76.05** | **80.16** | **82.85** |
61
+
62
+ Decompile-to-Chisel task on VerilogEval:
63
+
64
+ | Models | pass@1 | pass@3 | pass@5 | syntax(%) |
65
+ | ------------------------------ | --------- | --------- | --------- | --------- |
66
+ | Llama3.1-8B-Instruct | 5.43 | 12.29 | 16.08 | 11.15 |
67
+ | Qwen2.5-Coder-7B-Instruct | 27.60 | 34.58 | 37.19 | 43.23 |
68
+ | \*Deepseek-R1-Distill-Llama-8B | 10.05 | 16.15 | 18.13 | 12.03 |
69
+ | \* ChiseLLM-7B | **50.47** | **70.99** | **78.08** | **59.19** |
70
+
71
+ | Models | pass@1 | pass@3 | pass@5 | syntax(%) |
72
+ | ------------------------------- | --------- | --------- | --------- | --------- |
73
+ | Qwen2.5-Coder-32B-Instruct | 41.19 | 48.96 | 51.59 | 53.93 |
74
+ | Qwen2.5-72B-Instruct | 40.54 | 47.32 | 49.83 | 59.30 |
75
+ | Llama-3.3-70B-Instruct | 38.38 | 46.96 | 51.36 | 48.00 |
76
+ | \*Deepseek-R1-Distill-Qwen-32B | 45.03 | 63.02 | 70.18 | 53.17 |
77
+ | \*Deepseek-R1-Distill-Llama-70B | 37.50 | 55.05 | 63.84 | 45.59 |
78
+ | \*ChiseLLM-32B | **56.41** | **72.00** | **77.67** | **64.71** |
79
+
80
+ | Models | pass@1 | pass@3 | pass@5 | syntax(%) |
81
+ | ------------- | --------- | --------- | --------- | --------- |
82
+ | Deepseek-V3 | **54.57** | 63.19 | 66.71 | **66.19** |
83
+ | GPT-4o | 42.39 | 65.75 | 71.83 | 53.77 |
84
+ | \*Deepseek-R1 | 53.45 | **71.50** | **77.91** | 59.13 |
85
+
86
+ ### Framework versions
87
+
88
+ - Transformers 4.51.0
89
+ - Pytorch 2.6.0a0+df5bbc09d1.nv24.12
90
+ - Datasets 3.4.1
91
+ - Tokenizers 0.21.0
92
+
93
+ ### Training hyperparameters
94
+
95
+ The following hyperparameters were used during training:
96
+
97
+ - learning_rate: 1e-05
98
+ - train_batch_size: 2
99
+ - eval_batch_size: 8
100
+ - seed: 42
101
+ - distributed_type: multi-GPU
102
+ - num_devices: 8
103
+ - gradient_accumulation_steps: 8
104
+ - total_train_batch_size: 128
105
+ - total_eval_batch_size: 64
106
+ - optimizer: Use OptimizerNames.ADAMW_TORCH with betas=(0.9,0.999) and epsilon=1e-08
107
+ - lr_scheduler_type: cosine
108
+ - lr_scheduler_warmup_ratio: 0.05
109
+ - num_epochs: 3.0