Formally Verified Verilog Reasoning Datasets
William Patrick Yubeaton
wilyub
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VeriThoughts Models
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VeriThoughts Models
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8
wilyub/VeriThoughtsTrainSetInconsistentReasoningGT
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10.1k
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14
wilyub/VeriThoughtsTrainSetInconsistentReasoningGEN
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10.1k
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13
wilyub/VeriThoughtsTrainSetInconsistentInstructionGT
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10.1k
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wilyub/VeriThoughtsTrainSetInconsistentInstructionGEN
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10.1k
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12
wilyub/VeriThoughtsTrainSetConsistentReasoning
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10.1k
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15
wilyub/VeriThoughtsTrainSetConsistentInstruction
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10.1k
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13
wilyub/VeriThoughtsTrainSet
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20.2k
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20
wilyub/VeriThoughtsBenchmark
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291
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15