andstor/the_pile_github · Datasets at Hugging Face

text stringlengths 2 100k	meta dict
.setcpu "65c02" .org $C000 ; Set to the version of Apple //c ROM you want to build. Typically ; done on the command line. ;ROMVER = 255 ;ROMVER = 0 ;ROMVER = 3 ;ROMVER = 4 .if ROMVER = 255 .elseif ROMVER = 0 .elseif ROMVER = 3 .elseif ROMVER = 4 .else .error "ROMVER not set correctly." .endif ; This file is not part of the version 255 ROM. .if .not ROMVER = 255 .res 256 lda #$0E .byte $1C .byte $7F .byte $07 sec lda $C019 bpl $C136 sta $C079 lda #$0C bit $07FF bne $C118 sta $C05A ora #$02 sta $C078 bit $067F bne $C124 lda #$0C bit $C063 bpl $C12B eor #$04 and $07FF .byte $0C .byte $7F .byte $07 .byte $1C .byte $7F asl $69 inc $FFAD,x .byte $07 bmi $C1AD lda $C015 ora $C017 bpl $C1AD txa ldx #$00 bit $C015 bmi $C155 tya eor #$80 ldx #$80 bit $C017 bpl $C18E asl a lda $047F,x bcs $C175 cmp $047D,x bne $C168 lda $057F,x cmp $057D,x beq $C18A lda $047F,x bne $C170 dec $057F,x dec $047F,x bra $C18A cmp $067D,x bne $C182 lda $057F,x cmp $077D,x beq $C18A inc $047F,x bne $C18A inc $057F,x cpx #$00 beq $C14B sta $C048 lda #$02 and $07FF beq $C1A1 sta $C079 sta $C05B sta $C078 ora #$20 .byte $0C .byte $7F asl $A9 asl $7F2D .byte $07 adc #$FE bcs $C1B4 jmp $C784 sec rts jsr $C1BA jmp $C784 ldx #$C2 jsr $C1C2 bcc $C1B3 dex ldy $C142,x lda #$04 eor $BFFA,y and #$0C beq $C1B2 lda $BFF9,y sta $0438,x bpl $C1B2 cpx #$C2 bcs $C1DC eor #$40 bit $0538,x bvs $C20A bpl $C208 bcc $C208 bit #$40 beq $C20A lda $C000 ldy #$80 jsr $C228 cmp #$98 bne $C200 lda $C062 bpl $C200 stx $05FC .if ROMVER = 255 stx $06FF .elseif ROMVER = 0 stx $06FF .elseif ROMVER = 3 stx $06FF .elseif ROMVER = 4 stx $06FC .endif lda $C010 ldy #$B0 lda $BFF9,y and #$BF asl a asl a and #$20 beq $C24E lda $BFFA,y eor #$01 and #$03 bne $C24E txa eor $04FC bne $C1B2 php jsr $C322 bcc $C24D ldy #$00 bne $C231 phx pha lda $057C,y tax inc a bit #$7F bne $C235 tya cmp $067C,y beq $C23D sta $057C,y pla bit $C014 sta $C005 sta $0800,x bmi $C24C sta $C004 plx plp rts jsr $C255 jmp $C784 pha bit $C2AB beq $C25E inc $0738,x jsr $C2B2 and #$30 cmp #$10 bne $C25E lda $06B8,x bit #$20 beq $C28D cpx $04FC beq $C286 jsr $C2E9 bcc $C286 ldy $C234,x sta $05FE,y lda $06B8,x ora #$04 sta $06B8,x lda $06B8,x and #$02 bne $C25E ldy $C142,x pla pha sta $BFF8,y bit $06B8,x eor #$0D asl a bne $C2AA bvc $C2A5 lda #$14 ror a jsr $C255 stz $24 stz $0738,x pla rts jsr $C2B2 jmp $C784 php sei ldy $C142,x lda $BFF9,y bpl $C2C1 jsr $C1D6 bra $C2B4 plp rts jsr $C2C9 jmp $C784 cpx $04FC bne $C2D5 ldy #$00 jsr $C2FD bcs $C2F4 lda $06B8,x bit #$04 beq $C2E9 and #$FB sta $06B8,x ldy $C234,x lda $05FE,y sec rts jsr $C2B2 and #$08 clc beq $C2F4 jsr $C322 rts brk bra $C318 sbc $4CC2,x sty $C7 lda $067C,y cmp $057C,y clc beq $C321 pha inc a bit #$7F bne $C30D tya sta $067C,y ply lda $C013 asl a sta $C003 lda $0800,y bcs $C321 sta $C002 sec rts lda $BFF8,y pha ora #$80 tay lda $06B8,x bit #$08 bne $C334 cpy #$8A beq $C346 bit #$20 beq $C348 cpy #$91 bne $C340 and #$FD bra $C346 cpy #$93 bne $C348 ora #$02 clc bcs $C381 sta $06B8,x pla rts pha lda $C013 pha lda $C014 pha bcc $C361 sta $C002 sta $C005 bcs $C367 sta $C004 sta $C003 lda ($3C) sta ($42) inc $42 bne $C371 inc $43 lda $3C cmp $3E lda $3D sbc $3F inc $3C bne $C37F inc $3D bcc $C367 sta $C004 pla bpl $C38A sta $C005 sta $C002 pla bpl $C393 sta $C003 pla jmp $C784 pha lda $03ED pha lda $03EE pha bcc $C3AA sta $C003 sta $C005 bcs $C3B0 sta $C002 sta $C004 pla sta $03EE pla sta $03ED pla bvs $C3C0 sta $C008 bvc $C3C3 sta $C009 jmp $C7EB stx $01 stx $02 stx $03 ldx #$04 stx $04 sta $05 ldx #$04 stz $01 inc $01 tay sta $C083 sta $C083 lda $01 and #$F0 cmp #$C0 bne $C3F3 lda $C08B lda $C08B lda $01 adc #$0F bne $C3F5 lda $01 sta $03 tya ldy #$00 clc adc $C82A,x sta ($02),y dex bpl $C405 ldx #$04 iny bne $C3FA inc $01 bne $C3D8 inc $01 ldx #$04 lda $05 tay lda $C083 lda $C083 lda $01 and #$F0 cmp #$C0 bne $C42A lda $C08B lda $01 adc #$0F bne $C42C lda $01 sta $03 tya ldy #$00 clc adc $C82A,x eor ($02),y bne $C472 lda ($02),y dex bpl $C440 ldx #$04 iny bne $C431 inc $01 bne $C412 ror a bit $C019 bpl $C44F eor #$A5 dec $04 bmi $C456 jmp $C3D0 tax bit $C013 bmi $C46C txa sta $C005 sta $C003 sta $C009 sta $C081 jmp $D497 sta $C008 jmp $C4EF sec tax lda $C013 clv bpl $C47D bit $C82A lda #$A0 ldy #$06 sta $BFFE,y sta $C006,y dey dey bne $C481 sta $C051 sta $C054 sta $0400,y sta $0500,y sta $0600,y sta $0700,y iny bne $C491 txa beq $C4CA ldy #$03 bcs $C4A9 ldy #$05 lda #$AA bvc $C4B0 sta $05B0 lda $C866,y sta $05B1,y dey bpl $C4B0 ldy #$10 txa lsr a tax lda #$58 rol a sta $05B6,y dey dey bne $C4BB beq $C4C8 ldx #$02 ply php lda $C86C,x plp php bcc $C4D8 lda $C86F,x cpy #$06 bcc $C4E7 cpy #$08 bcc $C4E4 cpy #$11 bcc $C4E7 lda $C872,x sta $05B8,x dex bpl $C4CE bmi $C4ED ldy #$01 lda #$7F ror a ldx $C82F,y beq $C508 bcc $C4FE ldx $C841,y sta $BFFF,x iny bne $C4F3 ldx $C030 rol a dey ldx $C853,y beq $C521 bmi $C504 rol a bcc $C51A asl $C000,x bcc $C537 bcs $C508 asl $C000,x bcs $C537 bcc $C508 rol a iny sec sbc #$01 bcs $C4F3 dey beq $C533 cpy #$08 bne $C53F ldy #$11 bne $C4F1 ldy #$09 bne $C4F1 phy ldx #$00 cpy #$0A jmp $C47D lsr $80 bne $C4EF lda #$A0 ldy #$00 sta $0400,y sta $0500,y sta $0600,y sta $0700,y iny bne $C547 lda $C061 and $C062 asl a inc $FF lda $FF bcc $C566 jmp $D48E lda $C051 ldy #$08 lda $C875,y sta $05B8,y dey bpl $C56B bmi $C556 .res 10 phx ldx $0678 inc $C000,x plx lda $49 sta $BFF8,x lda $4A sta $BFF9,x lda $4B and #$7F cmp $03B8,y bcs $C5EE sta $BFFA,x bit $C014 php sta $C004 bit $4B bpl $C5AC sta $C005 ldy #$00 lda $48 sta $05F8 beq $C5C9 lda $BFFB,x sta ($45),y iny lda $BFFB,x sta ($45),y iny bne $C5B5 inc $46 dec $48 bne $C5B5 lda $47 beq $C5E3 sta $0578 lsr a bcs $C5D9 lda $BFFB,x sta ($45),y iny lda $BFFB,x sta ($45),y iny cpy $47 bne $C5D3 sta $C004 plp bpl $C5EC sta $C005 bra $C5F3 lda #$2D sta $04F8 sta $C081 rts phx ldx $0678 inc $C000,x plx lda $49 sta $BFF8,x lda $4A sta $BFF9,x lda $4B and #$7F cmp $03B8,y bcs $C5EE sta $BFFA,x bit $C013 php sta $C002 bit $4B bpl $C623 sta $C003 ldy #$00 lda $48 sta $05F8 beq $C640 lda ($45),y sta $BFFB,x iny lda ($45),y sta $BFFB,x iny bne $C62C inc $46 dec $48 bne $C62C lda $47 sta $0578 beq $C65A lsr a bcs $C650 lda ($45),y sta $BFFB,x iny lda ($45),y sta $BFFB,x iny cpy $47 bne $C64A sta $C002 plp bpl $C663 sta $C003 sta $C081 rts sed brk brk brk .byte $07 eor ($41) eor $4143 eor ($44) jsr $2020 jsr $2020 jsr $2020 brk brk .if ROMVER = 255 .byte $01 .elseif ROMVER = 0 .byte $01 .elseif ROMVER = 3 .byte $01 .elseif ROMVER = 4 .byte $02 .endif .byte $01 .byte $03 .byte $03 .byte $03 .byte $03 .byte $03 .byte $03 ora ($01,x) .byte $03 .byte $03 ora ($01,x) ora ($01,x) ora ($01,x) .byte $04 .byte $04 .byte $04 .byte $04 .byte $FF .byte $FF .byte $FF .byte $FF .byte $FF .byte $FF .byte $52 .if ROMVER = 255 .byte $73 .elseif ROMVER = 0 .byte $73 .elseif ROMVER = 3 .byte $73 .elseif ROMVER = 4 .byte $7D .endif .byte $2F .if ROMVER = 255 .byte $B8 .elseif ROMVER = 0 .byte $B8 .elseif ROMVER = 3 .byte $B8 .elseif ROMVER = 4 .byte $C2 .endif .byte $2F .if ROMVER = 255 .byte $BC .elseif ROMVER = 0 .byte $BC .elseif ROMVER = 3 .byte $BC .elseif ROMVER = 4 .byte $C6 .endif .byte $2F sec .if ROMVER = 255 .byte $69 .byte $69 .elseif ROMVER = 0 .byte $69 .byte $69 .elseif ROMVER = 3 .byte $69 .byte $69 .elseif ROMVER = 4 .byte $73 .byte $73 .endif sec sec .byte $2F .byte $2F .byte $2F .byte $2F .byte $2F and $3C2F,y .byte $45 .if ROMVER = 255 .byte $9D .elseif ROMVER = 0 .byte $9D .elseif ROMVER = 3 .byte $9D .elseif ROMVER = 4 .byte $A7 .endif .byte $AB sec .byte $3F .byte 'B' phx jsr $C816 phy sty $0678 jsr $D8F9 jmp $C80E phx jsr $C816 phy jsr $D621 jmp $C80E phx jsr $C816 phy jsr $D6C2 jmp $C80E phx jsr $C816 phy jsr $D679 jmp $C80E phx jsr $C816 phy jsr $D668 jmp $C80E phx jsr $C816 phy jsr $D6A3 jmp $C80E phx jsr $C816 phy jsr $D651 jmp $C80E phx jsr $C816 phy jsr $D600 jmp $C80E .res 13 sta $C028 jmp $C6C2 sta $C028 jmp $C6CD sta $C028 jmp $C6D8 sta $C028 jmp $C6E3 sta $C028 jmp $C6EE sta $C028 jmp $C6F9 sta $C028 jmp $C704 sta $C028 jmp $CF9A sta $C028 jmp $C6B4 sta $C028 phx jsr $C816 phy sty $0678 jsr $D800 jmp $C80E .res 29 sta $C028 rti sta $C028 rts sta $C028 jmp $FA62 sta $C028 bit $C787 jmp $C804 sta $C028 jmp $C880 sta $C028 jmp $D400 sta $C028 jmp $C7F1 sta $C028 jmp $C806 sta $C028 jmp $C34E sta $C028 jmp $C397 sta $C028 jmp $C100 sta $C028 jmp $D48E sta $C028 jmp $C580 sta $C028 jmp $C24F sta $C028 jmp $C2AC sta $C028 jmp $C2C3 sta $C028 jmp $C2F7 sta $C028 jmp $D4C5 sta $C028 jmp ($03ED) phx jsr $C816 phy jsr $D1A0 bra $C80E .res 8 jmp $C78E phx jsr $C816 phy jsr $D000 plx inc $C000,x plx jmp $C784 ldy #$81 bit $C012 bpl $C829 ldy #$8B bit $C011 bpl $C826 ldy #$83 sta $C081 rts .byte 'S' .byte 'C' .byte $2B and #$07 brk bit #$03 ora $09 ora ($7F,x) .byte '_' brk .byte $83 eor ($53),y eor $57,x .byte $0F ora $8000 brk sta ($04,x) asl $0A .byte $02 .byte $7F rts brk sty $52 .byte 'T' lsr $58,x bpl $C85F brk .byte $7F brk ora ($13),y .byte $14 asl $18,x .byte $FF .byte $7F brk ora ($1A) .byte $1B .byte $1C ora $1F1E,x brk ror $D200,x cmp ($CD,x) ldy #$DA bne $C83A cmp $C9D5 .byte $CF cmp $C7,x cpy $D3D5 sbc $F4F3,y sbc $ED ldy #$CF .byte $CB brk brk jmp $CD4C jsr $CB61 jsr $CA7D ldy #$07 jsr $CC20 lda $C08B,x lda $C089,x ldy #$32 lda $C08E,x bmi $C8A2 dey bne $C896 sec jmp $C9CC lda $C081,x ldy #$05 lda #$FF sta $C08F,x lda $C9D3,y asl $C08C,x bcc $C8AF sta $C08D,x dey bpl $C8AC lda $5A ora #$80 jsr $CA50 jsr $CA4E lda $5B jsr $CA50 jsr $CA4E jsr $CA4E lda $4C ora #$80 jsr $CA50 lda $4B ora #$80 jsr $CA50 lda $4C beq $C8F6 ldy #$FF lda $59 asl $C08C,x bcc $C8E5 sta $C08D,x iny lda ($54),y ora #$80 cpy $4C bcc $C8E5 lda $4B bne $C8FD jmp $C996 nop ldy #$00 lda $41 sta $C08D,x lda $4D ora #$80 sty $59 ldy $C08C,x bpl $C90B sta $C08D,x ldy $59 lda ($56),y sta $4D asl a rol $41 iny bne $C924 inc $57 jmp $C926 pha pla lda #$02 ora $41 sta $41 lda $4E ora #$80 sta $C08D,x lda ($56),y sta $4E asl a rol $41 iny lda $4F ora #$80 sta $C08D,x lda ($56),y sta $4F asl a rol $41 iny lda $50 ora #$80 sta $C08D,x lda ($56),y sta $50 asl a rol $41 iny bne $C960 inc $57 jmp $C962 pha pla lda $51 ora #$80 sta $C08D,x lda ($56),y sta $51 asl a rol $41 iny lda $52 ora #$80 sta $C08D,x lda ($56),y sta $52 asl a rol $41 iny lda $53 ora #$80 sta $C08D,x lda ($56),y sta $53 asl a rol $41 iny dec $4B beq $C996 jmp $C900 lda $40 ora #$AA ldy $C08C,x bpl $C99A sta $C08D,x lda $40 lsr a ora #$AA jsr $CA50 lda #$C8 jsr $CA50 lda $C08C,x and #$40 bne $C9AF sta $C08D,x ldy #$0A dey bne $C9C6 lda #$01 jsr $CA97 sec bcs $C9CC lda $C08E,x bmi $C9BB clc lda $C080,x lda $C08C,x rts .byte $C3 .byte $FF .byte $FC .byte $F3 .byte $CF .byte $3F jsr $C9DE nop nop nop rts jmp $C9C0 lda #$00 sta $40 lda $54 sta $56 lda $55 sta $57 jsr $CA7D lda $C08D,x lda $C08E,x bpl $C9F5 lda $C081,x ldy #$1E lda $C08C,x bpl $C9FF dey bmi $C9E0 cmp #$C3 bne $C9FF ldy #$06 lda $C08C,x bpl $CA0D and #$7F sta $004B,y eor #$80 eor $40 sta $40 dey bpl $CA0D lda $4C beq $CA4B clc adc $54 sta $56 lda $55 adc #$00 sta $57 ldy #$00 lda $C08C,x bpl $CA31 asl a sta $41 lda $C08C,x bpl $CA39 asl $41 bcs $CA44 eor #$80 sta ($54),y iny cpy $4C bcc $CA39 jmp $CC73 lda #$80 ldy $C08C,x bpl $CA50 sta $C08D,x eor $40 sta $40 rts jsr $CA87 lda $C081,x lda $C085,x ldy #$50 jsr $CA70 jsr $CA87 ldy #$0A jsr $CA77 dey bne $CA70 rts ldx #$C8 dex bne $CA79 rts jsr $CA97 lda $C083,x lda $C087,x rts jsr $CA97 lda $C080,x lda $C082,x lda $C084,x lda $C086,x rts ldx #$60 rts bra $CA1C bra $CA1E bra $CA20 bra $CA22 brk brk brk brk brk brk brk brk bra $CA2C bra $CA2E brk brk brk brk bra $CA34 bra $CA36 brk brk brk brk bra $CA3C brk brk bra $CA40 brk brk bra $CA44 brk brk bra $CA48 brk brk bra $CACC bra $CACE bra $CAD0 bra $CAD2 bra $CAD4 bra $CAD6 bra $CAD8 bra $CADA lda #$05 ldy #$00 jsr $CAFD bcc $CAE8 lda #$80 jsr $CF98 rts jsr $CAFD bcc $CAE8 lda #$80 jsr $CF98 lda $06F8 sta $4D lda $0778 sta $4E lda #$B8 ldy #$0B ldx $58 sta $04F3,x tya sta $0573,x lda $4D sta $06F8 lda $4E sta $0778 jsr $C883 lda $06F8 sta $4D lda $0778 sta $4E bcc $CB2F ldx $58 dec $04F3,x bne $CB0A dec $0573,x bpl $CB0A rts ldy $58 lda #$05 sta $04F3,y jsr $C9E3 bcc $CB4B ldy #$01 jsr $CA70 jsr $C9C0 ldx $58 dec $04F3,x bne $CB37 rts brk bit $49 brk .byte $04 ora ($00,x) ora ($02,x) .byte $04 ora #$12 brk ora ($02,x) .byte $04 ora ($02,x) brk .byte $7F .byte $FF ldx $4E beq $CB7C lda $55 sta $57 lda #$80 cpx #$01 beq $CB73 inc $57 lda #$00 clc adc $54 sta $56 bcc $CB7C inc $57 lda $CB4C,x sta $4B lda $CB4F,x sta $4C ldx #$05 lda $4D sta $59 and #$07 tay asl $59 bcc $CBA8 lda $CB58,x clc adc $4C cmp #$07 bcc $CB9F sbc #$07 sta $4C lda $CB52,x adc $4B sta $4B dex bmi $CBB1 bne $CB8F tya jmp $CB96 lda $55 pha lda #$00 ldx $4E beq $CBD0 ldy $CB5E,x eor ($54),y eor ($56),y dey bne $CBBD eor ($54),y eor ($56),y cpx #$01 beq $CBCE inc $55 inc $55 ldy $4D beq $CBDD eor ($54),y eor ($54),y dey bne $CBD6 eor ($54),y sta $40 pla sta $55 ldy $4C dey lda #$00 sta $59 lda ($54),y asl a ror $59 dey bpl $CBE9 sec ror $59 lda $4C clc adc $54 sta $56 lda $55 adc #$00 sta $57 ldy #$06 sec lda ($56),y sta $004D,y bmi $CC0C clc ror $41 dey bpl $CC03 sec ror $41 lda $56 clc adc #$07 sta $56 bcc $CC1F inc $57 rts lda $C088,x lda $C08D,x jmp $CC2D tya sta $C08F,x tya eor $C08E,x and #$1F bne $CC29 rts jsr $CA97 lda $C08E,x lda $C08D,x lda $C08E,x and #$20 bne $CC3F lda $C08C,x phy ldy #$8C dey bne $CC4C ply rts lda $4B tay ldx #$00 stx $4B ldx #$03 asl a rol $4B dex bne $CC5A clc adc $4C bcc $CC67 inc $4B sty $4C sec sbc $4C bcs $CC70 dec $4B ldy $4B rts ldy #$00 lda $4B pha bne $CC7D jmp $CD0A lda $C0EC bpl $CC7D sta $59 lsr a lsr a lsr a and #$0F tax lda $59 and #$07 sta $59 lda $C0EC bpl $CC90 eor $CA9A,x sta ($56),y eor $40 sta $40 iny bne $CCA3 inc $57 lda $C0EC bpl $CCA3 eor $CAAA,x sta ($56),y eor $40 sta $40 iny lda $C0EC bpl $CCB2 eor $CABA,x sta ($56),y eor $40 sta $40 iny lda $C0EC bpl $CCC1 eor $CACA,x sta ($56),y eor $40 sta $40 iny bne $CCD4 inc $57 ldx $59 lda $C0EC bpl $CCD6 eor $CAAA,x sta ($56),y eor $40 sta $40 iny lda $C0EC bpl $CCE5 eor $CABA,x sta ($56),y eor $40 sta $40 iny lda $C0EC bpl $CCF4 eor $CACA,x sta ($56),y eor $40 sta $40 iny dec $4B beq $CD0A jmp $CC7D lda $C0EC bpl $CD0A sta $59 pla sta $4B lda $C0EC bpl $CD14 sec rol a and $59 eor $40 ldy $C0EC bpl $CD1F cpy #$C8 bne $CD44 ldx $4C beq $CD34 ldy #$00 eor ($54),y iny dex bne $CD2E tax bne $CD48 lda $C0ED lda $C0EE bmi $CD3A lda $C0E0 clc rts lda #$20 bne $CD4A lda #$10 sec rts bcc $CD51 jmp $C523 lda #$40 .byte $1C sei .byte $04 cld txa tay lda $0473,y bmi $CD6F pla sta $05F3,y clc adc #$03 tax pla sta $0673,y adc #$00 pha txa pha jsr $CC36 php sei ldx #$1B lda $40,x pha dex bpl $CD76 sty $58 lda $43 rol a php rol a rol a plp rol a and #$03 eor #$02 cpy #$04 bcs $CD90 eor #$02 tax inx stx $43 lda $0473,y bpl $CD9C jmp $CE40 lda $05F3,y sta $54 lda $0673,y sta $55 ldy #$01 lda ($54),y sta $42 iny lda ($54),y tax iny lda ($54),y sta $55 stx $54 lda #$01 ldx $42 cpx #$0A bcc $CDC2 jmp $CF17 ldy #$00 lda ($54),y sta $5A ldy #$08 lda ($54),y sta $0042,y dey bne $CDCA lda $43 bne $CE40 ldx $42 lda $CF8E,x and #$7F tay lda #$04 cpy $5A bne $CDBF cpx #$05 bne $CDF2 lda #$00 jsr $CF98 lda #$00 jmp $CF39 txa bne $CE19 lda #$21 ldx $46 bne $CDBF txa ldx $58 ldy #$07 sta ($44),y dey bne $CE00 lda $06F9,x sta ($44),y iny lda $04F9 sta ($44),y lda #$08 dey jsr $CFF0 jmp $CDED cmp #$04 bne $CE28 ldx $46 beq $CE2C dex beq $CE38 lda #$21 bne $CDBF lda #$11 bne $CDBF lda #$C0 sta $05F9 lda #$0F .byte $0C txs cpy #$D0 ora $A9 ora ($1C,x) txs cpy #$4C sbc $A9CD plp ldy $58 ldx $06F9,y cpx $43 bcc $CE26 lda #$09 sta $4D lda #$00 sta $4E sta $55 lda #$42 sta $54 ldx $58 lda $0473,x bpl $CE73 ldx $42 lda $CF8E,x and #$7F sta $5A lda #$00 sta $48 lda $42 bne $CE73 sta $46 lda $5A ldx $43 stx $5A sta $43 lda #$80 sta $5B jsr $CA87 jsr $CAE9 bcs $CECD lda $44 sta $54 lda $45 sta $55 ldx $42 lda $CF8E,x bpl $CED1 cpx #$04 bne $CEB2 ldy #$01 lda ($54),y tax dey lda ($54),y pha clc lda #$02 adc $54 sta $54 pla bcc $CEC0 inc $55 jmp $CEC0 cpx #$02 bne $CEBC lda #$00 ldx #$02 bne $CEC0 ldx $47 lda $46 stx $4E sta $4D lda #$82 sta $5B jsr $CADA bcc $CED1 lda #$06 bne $CF17 ldy $58 lda $0473,y bpl $CEE4 lda $42 bne $CEE4 lda #$45 ldx #$00 sta $54 stx $55 jsr $CB30 bcs $CECD jsr $CC51 jsr $CFF0 lda $42 bne $CF15 ldx $58 lda $0473,x bpl $CF15 lda $46 sta $05F3,x lda $47 sta $0673,x lda $45 lsr a lsr a lsr a bcc $CF0F lda #$2B bra $CF17 lsr a lsr a lda #$2F bcc $CF17 lda $4D ldy $58 sta $04F3,y tax beq $CF39 ldx $0473,y bpl $CF39 ldx #$00 cmp #$40 bcs $CF38 ldx #$27 cmp #$2B beq $CF39 cmp #$28 beq $CF39 cmp #$2F beq $CF39 txa ldy $58 sta $0573,y lda $C0E8 bit $C0ED lda #$2B sta $C0EF nop nop nop nop lda $C0EE and #$20 bne $CF4D ldy #$00 ldx #$60 jsr $CC20 lda $C0EC lda $C0E2 lda $C0E6 ldy $58 ldx #$00 pla sta $40,x inx cpx #$1C bcc $CF68 plp lda $05F3,y tax lda $0573,y pha lda $0673,y tay clc pla beq $CF82 sec php bit $0478 bvs $CF8C plp jmp $C784 plp rts .byte $03 .byte $03 .byte $83 ora ($83,x) ora ($01,x) ora ($03,x) .byte $83 pha jsr $CA5D pla tax lda $42 pha lda $43 pha lda $46 pha stx $46 lda #$05 sta $42 lda #$00 sta $5A lda #$02 sta $43 lda #$42 sta $54 lda #$00 sta $55 lda #$80 sta $5B jsr $CA87 inc $5A lda #$09 sta $4D lda #$00 sta $4E jsr $C883 bcc $CFD8 dec $5A jmp $CFDF jsr $C9E3 lda $4D beq $CFC4 lda $5A ldy $58 sta $06F9,y pla sta $46 pla sta $43 pla sta $42 rts ldx $58 sta $05F3,x tya sta $0673,x rts brk brk brk brk brk brk pha bit $03B8,x bmi $D022 ldy $0638,x beq $D01F eor $0638,x asl a bne $D01F ldy $07FB sty $0679 ldy #$BF sty $07FB jmp $D0B5 sec pla rts ldy $C142,x and #$5F pha lda $03B8,x bit #$08 bne $D032 pla bra $D084 pla pha cmp #$00 bne $D03C clc pla bra $D020 lda $03B8,x pha and #$07 sta $06F8 pla and #$F0 sta $03B8,x pla phx ldx $06F8 cmp #$45 beq $D0C5 cmp #$44 beq $D0C7 plx phx cmp $0638,x php ldx $06F8 plp beq $D077 cmp #$0D beq $D07F plx lda $0679 sta $07FB asl $03B8,x lsr $03B8,x bra $D01F plx phx inc $03B8,x ldx $06F8 lda $D225,x bra $D08F phx ldx #$04 cmp $D225,x beq $D0FD dex bpl $D087 ldx #$0C cmp $D218,x beq $D10A dex bpl $D091 plx pla pha and #$7F cmp #$20 bcs $D0A5 sta $0638,x eor #$30 cmp #$0A bcs $D0DE ldy #$0A adc $077E dey bne $D0AD bra $D0BF lda $03B8,x and #$C0 sta $03B8,x lda #$00 sta $077E sec bra $D0EA sec bcc $D0E0 php cpx #$00 beq $D0F4 cpx #$04 beq $D112 txa clc asl a adc #$03 tax plp bcs $D0DB inx jmp $D139 lda $03B8,x lsr a bcs $D0B5 lda $0679 sta $07FB php asl $03B8,x plp ror $03B8,x pla rts lda #$4C plp bcs $D08F lda #$4B bra $D08F txa plx ora $03B8,x ora #$08 sta $03B8,x sec bra $D0EA lda #$D1 pha lda $D1F5,x pha rts plp plx bcs $D11B stz $04B8,x bra $D0DE ldy $D186,x jsr $D22A sta $04B8,x bra $D0DE plx stz $04B8,x lda #$00 jmp $D0A2 ply lda $077E beq $D13A sta $04B8,y beq $D1B4 lda $06B8,y and $D202,x ora $D20D,x sta $06B8,y tya tax jmp $D0DE dey lda #$1F sec bcc $D0FA beq $D16B and $BFFB,y sta $06F8 plx lda $077E and #$0F bcc $D166 asl a asl a asl a asl a asl a ora $06F8 iny bra $D183 lda $BFFA,y pha ora #$0C sta $BFFA,y lda #$E9 ldx #$53 pha pla dex bne $D179 dec a bne $D177 pla plx sta $BFFA,y bra $D148 sta $BFF9,y lda $067B asl a jsr $C797 bcc $D197 jsr $C79D clc bcs $D1D2 plx jsr $D1A0 bra $D148 lda $03B8,x bit #$40 bcc $D1B9 bne $D1C9 cpx $39 bne $D1F4 ora #$40 ldy $0679 sty $067A ldy #$DF bra $D1C0 beq $D1C9 and #$BF ldy $067A sta $03B8,x sty $0679 sty $07FB ldy $C142,x cli php sei lda $BFFA,y ora #$02 bcc $D1D8 and #$FD sta $BFFA,y lda #$00 ror a sta $05FA bpl $D1EA stz $057C stz $067C txa sta $04FC plp stx $05FC stx $06FC rts sec sec sec rol $4F2E .byte 'K' lsr a stx $87,y .byte 'k' tya and $7F .byte $BF .byte $BF .byte $7F .byte $FF .byte $DF .byte $DF .byte $EF .byte $EF .byte $F7 .byte $F7 bra $D20F rti brk brk jsr $0000 bpl $D217 php eor #$4B jmp $0D4E .byte 'B' .byte 'D' bvc $D272 eor ($53) .byte 'T' phy jmp $4658 eor $AD43 .byte $13 cpy #$0A lda $C018 php sta $C000 sta $C003 lda $0478,y plp bcs $D241 sta $C002 bpl $D246 sta $C001 rts .byte $03 .byte $07 .res 439 sta ($28),y lda #$05 sta $38 lda $C000 asl a php sei jsr $D679 ldy #$05 ldx $057F lda $047F jsr $D441 ldy #$0C ldx $05FF lda $04FF jsr $D441 lda $077F rol a rol a rol a and #$03 eor #$03 inc a plp ldy #$10 jsr $D452 ply ldx #$11 lda #$8D sta $0200,x jmp $C784 cpx #$80 bcc $D452 eor #$FF adc #$00 pha txa eor #$FF adc #$00 tax pla sec sta $0214 stx $0215 lda #$2B bcc $D45E lda #$2D pha lda #$2C sta $0201,y ldx #$11 lda #$00 clc rol a cmp #$0A bcc $D470 sbc #$0A rol $0214 rol $0215 dex bne $D469 ora #$30 sta $0200,y dey beq $D489 cpy #$07 beq $D489 cpy #$0E bne $D464 pla sta $0200,y rts sta $C050 sta $C078 sta $C05F ldy #$04 ldx #$00 clc adc $C82A,y sta $00,x inx bne $D49B clc adc $C82A,y cmp $00,x bne $D4BC inx bne $D4A4 ror a bit $C019 bpl $D4B7 eor #$A5 dey bpl $D49B bmi $D4C2 eor $00,x clc jmp $C473 jmp $C3C6 jsr $C79D pla ply pla lda #$FF tax inx eor $D4DA,x sta $0200,x bpl $D4CE jmp $C784 lda $0A3B .byte $0B pha .byte 'w' rol a:$0005,x ora $08 .byte $0C asl $6553,x .byte $37 .byte $1C .byte $07 .byte $0C eor $62 .byte $27 brk .byte $17 .byte $1C .byte $07 .byte $07 ora $4B adc $0224 asl $6145 and ($18) .byte $02 .byte $07 ora $6A53,x .byte $2B .byte $0C php asl $53,x pla and $0706,x .byte $1B ora ($E3,x) .res 240 stz $077F ldx #$80 ldy #$01 stz $047D,x stz $057D,x lda #$FF sta $067D,x lda #$03 sta $077D,x ldx #$00 dey bpl $D607 jsr $D651 lda #$00 tax jsr $C746 txa sta $0478 lsr a ora $0478 cmp #$10 bcs $D650 and #$05 beq $D636 cli adc #$55 php sei stx $07FF sta $C079 ldx #$08 dex asl a bcc $D649 sta $C058,x bne $D642 sta $C078 plp clc rts ldx #$80 bra $D657 ldx #$00 lda $047D,x sta $047F,x lda $057D,x sta $057F,x dex bpl $D655 bra $D674 stz $047F stz $057F stz $04FF stz $05FF stz $067F clc rts lda #$20 .byte $1C .byte $7F .byte $07 and $067F .byte $1C .byte $7F asl $2C .byte $FF .byte $07 bmi $D69C bit $C063 bmi $D690 ora #$80 bit $077F bpl $D697 ora #$40 sta $077F clc rts ora $077F and #$E0 bra $D697 ror a ror a and #$80 tax lda $0478 sta $047D,x lda $0578 sta $057D,x lda $04F8 sta $067D,x lda $05F8 sta $077D,x clc rts pha clc lda #$0E and $077F bne $D6CC sec pla rts .res 306 sta $42 ldy #$C4 sty $07F8 ldx #$C8 stx $0778 lda #$00 sta $04F8 jsr $D9DD ldy $42 lda $C680,y bmi $D81F cmp $43 bne $D834 lda #$D8 bra $D824 brk pha lda $C69A,y pha ldy $07F8 ldx $0778 rts lda #$01 bne $D836 lda #$04 sta $04F8 rts jmp $C580 jmp $C5F7 jmp $D959 jmp $DB3A lda $03B8,y lsr a sta $05F8 lda #$00 sta $0578 rts lda $47 bne $D878 sta $05F8 ldy #$08 sty $0578 dey sta ($45),y dey bne $D860 phy ldy $07F8 lda $03B8,y beq $D870 lda #$01 ply sta ($45),y rts lda $47 beq $D87D lda #$21 sta $04F8 rts lda #$04 ldx $47 beq $D88A cpx #$03 bne $D878 lda #$19 sta $0578 ldx #$00 stx $05F8 tay dey lda $C667,y sta ($45),y dey bpl $D894 ldy $07F8 lda $03B8,y lsr a ldy #$02 sta ($45),y rts bit $D839 bvc $D865 lda $47 sta $48 lda $46 sta $47 lda $45 sta $46 lda $44 sta $45 lda #$00 sta $49 beq $D8C8 bit $D839 bvc $D880 lda $47 asl a sta $4A lda $48 rol a sta $4B bcs $D8F3 lda $49 bne $D8F3 sta $49 sta $47 lda #$02 sta $48 lda $C014 bvs $D8E8 lda $C013 and #$80 ora $4B sta $4B bvs $D8F6 jmp $C5F7 jmp $C5EE jmp $C580 ldy #$C4 sty $07F8 ldx #$C8 stx $0778 cmp $07F8 bne $D911 lda $BF00 beq $D911 cmp #$4C bne $D931 stz $0801 lda $06B8,y cmp #$A5 bne $D92C ldy #$03 lda $D92D,y sta $0044,y dey bpl $D91D ldy $07F8 jsr $D8A8 rts brk php brk brk lda #$4C sta $BD00 lda #$D1 sta $BD01 sty $BD02 lda #$C3 sta $9D1E lda #$A6 sta $9D1F pla pla plx inc $C000,x plx pla pla ldx #$00 lda #$98 jmp $C784 rts ldy #$02 lda ($48),y cmp #$01 beq $D964 jmp $D830 ldy #$04 lda ($48),y lsr a ror $4A lsr a ror $4A lsr a sta $4B lda $4A ror a and #$E0 iny ora ($48),y sta $4A ldy #$08 lda ($48),y sta $45 iny lda ($48),y sta $46 ldy #$0C lda ($48),y beq $D958 and #$03 beq $D961 ora #$11 tay ldx #$00 stx $47 stx $49 inx stx $48 jmp $D81F lda #$00 sta $BFF8,x sta $BFF9,x lda #$10 sec sbc #$01 sta $BFFA,x lda $BFFB,x pha dec $BFF8,x lda #$A5 sta $BFFB,x dec $BFF8,x eor $BFFB,x dec $BFF8,x cmp #$01 pla sta $BFFB,x lda $BFFA,x and #$0F beq $D9D5 bcs $D9AA adc #$01 sta $03B8,y lsr a sta $0478 rts ldy $07F8 lda #$A5 cmp $06B8,y beq $DA12 sta $06B8,y cmp #$05 php jsr $D99F plp beq $DA12 lda $BF00 beq $DA13 cmp #$4C bne $DA19 ldy #$FF jsr $DA43 lda #$01 ldy #$20 sta $BFFB,x ora #$FF dey bne $DA05 dec $0478 bne $DA03 rts ldy #$78 jsr $DA43 rts ldy #$2C jsr $DA43 lda #$44 sta $BFF8,x lda $0478 ldy #$72 cmp #$04 bcc $DA2E ldy #$BA lda $BFF8,x cmp #$7C bne $DA3A lda #$7E sta $BFF8,x lda #$FF sta $BFFB,x dey bne $DA2E rts lda #$00 sta $BFF8,x sta $BFF9,x sta $BFFA,x sta $BFFB,x lda $BFF9,x and #$F0 beq $DA4E lda #$04 sta $BFF9,x iny lda $DAB1,y cmp #$FD beq $DA81 cmp #$FE beq $DA87 cmp #$FC bne $DA72 lda $0478 bne $DA7B cmp #$AA bne $DA7B lda $07F8 eor #$F0 sta $BFFB,x jmp $DA5D iny lda $DAB1,y beq $DA98 pha lda #$00 sta $BFFB,x pla sec sbc #$01 bne $DA87 beq $DA5D sta $BFFB,x cmp $BFF8,x bne $DA95 iny lda $DAB1,y beq $DAB0 sta $BFF9,x iny lda $DAB1,y sta $BFFA,x jmp $DA5D rts brk brk .byte $03 brk .byte $F4 eor ($41) eor $FDAA ora $27C3,y ora a:$0000 asl $00 brk .byte $FC sbc $FED7,x .byte $02 brk .byte $04 brk inc $03FE,x brk ora $00 inc $04FE,x brk brk inc a:$00FD,x brk brk brk brk sbc $2000,x .byte $02 .byte $02 ora ($0F),y .byte $04 brk brk .byte $FB sbc $7A20,x sbc $FF08,x .byte $FF .byte $FF .byte $FF and ($20) brk ora ($FD,x) .byte $CB inc $0111,x inc $0211,x inc $0311,x inc $0411,x inc $0511,x inc $0611,x inc $0711,x inc $0811,x inc $0911,x inc $0A11,x inc $0B11,x inc $0C11,x inc $0D11,x inc $0E11,x inc a:$00FD,x jsr $FD02 brk brk brk brk asl $FD .byte $03 .byte $04 eor ($41) eor $FDAA .byte $04 .byte $FC sbc a:$0000,x ldx #$00 lda $DC00,x sta $2000,x lda $DD00,x sta $2100,x lda $DE00,x sta $2200,x lda $DF00,x sta $2300,x inx bne $DB3C ldx $0778 lda #$1F pha lda #$FF pha jmp $C784 .res 157 lda #$00 sta $49 sta $4A sta $0438,y sta $04B8,y lda $03B8,y and #$0F sta $46 jsr $FC58 lda #$08 jsr $221D lda $46 lsr a lsr a pha ora #$04 jsr $221D lda #$09 jsr $221D pla jsr $221D jsr $FD8E lda #$05 sta $25 jsr $FD8E lda #$10 jsr $221D lda $4A jsr $FDDA lda $49 jsr $FDDA jsr $220B lda #$01 sta $00 ldy #$05 lda $22F4,y jsr $2213 cmp $BFF8,x bne $DC6C cmp $BFF9,x bne $DC6C ora #$F0 cmp $BFFA,x bne $DC6C dey bpl $DC50 bmi $DC6F jmp $2197 inc $00 dec $BFF8,x lda $BFFB,x sta $BFFB,x lda $BFFA,x and #$0F ora $BFF9,x ora $BFF8,x beq $DC8A jmp $2197 inc $00 lda #$01 sta $45 txa clc adc #$F8 sta $42 lda #$C0 sta $43 lda $46 beq $DCA2 cmp #$0C bne $DCA4 lda #$10 lsr a pha ldy #$02 pha jsr $2211 pla sta ($42),y pha lda $45 sta $BFFB,x inc $45 pla lsr a bne $DCA8 sta ($42),y ror a dey bpl $DCA8 lda #$01 sta $45 pla ldy #$02 pha jsr $2211 pla sta ($42),y sta $47 lda $BFFB,x cmp $45 bne $DCE7 inc $45 lda $47 lsr a bne $DCC8 sta ($42),y ror a dey bpl $DCC8 bmi $DCEA jmp $2197 jsr $2211 inc $00 sta $45 lda $45 sta $BFFB,x sta $BFFB,x sta $BFFB,x sta $BFFB,x lda $BFF8,x bne $DCF1 ora $BFF9,x bne $DCF1 jsr $21E4 bne $DCF1 jsr $220B lda $BFFB,x cmp $45 bne $DCE7 lda $BFFB,x cmp $45 bne $DCE7 lda $BFF8,x bne $DD11 ora $BFF9,x bne $DD11 jsr $21E4 bne $DD11 jsr $220B lda $45 eor #$FF bne $DCED inc $00 lda #$55 sta $45 jsr $21FD clc adc $47 adc $45 sta $BFFB,x sta $45 lda $BFF8,x bne $DD40 lda $BFF9,x bne $DD3D jsr $21E4 bne $DD3D jsr $220B lda #$55 sta $45 jsr $21FD clc adc $47 adc $45 sta $45 lda $BFFB,x cmp $45 bne $DD97 lda $BFF8,x bne $DD63 lda $BFF9,x bne $DD60 jsr $21E4 bne $DD60 lda #$0B jsr $221D sed lda $49 clc adc #$01 sta $49 lda $4A adc #$00 sta $4A cld jmp $2031 pha jsr $FC42 lda #$0A jsr $221D lda $00 cmp #$03 bcs $DDAF pla lda #$0C jsr $221D jmp $21DE lda #$0D jsr $221D sec lda $BFF8,x sbc #$01 pha lda $BFF9,x sbc #$00 pha lda $BFFA,x and #$0F sbc #$00 jsr $FDDA pla jsr $FDDA pla jsr $FDDA lda #$0E jsr $221D pla eor $45 jsr $FDDA lda #$0F jsr $221D rts lda #$AE jsr $FDED lda $C000 cmp #$9B bne $DDF5 pla pla sta $C010 lda $BFFA,x and #$0F cmp $46 rts clc lda $BFF9,x adc $BFFA,x adc #$55 sta $47 lda #$00 rts jsr $FD8E jsr $FC9C lda #$00 sta $BFF8,x sta $BFF9,x sta $BFFA,x rts tay lda $2230,y tay lda $2241,y pha ora #$80 jsr $FDED iny pla bpl $DE22 rts brk ora $09 ora $1411 asl $18,x .byte $1B .byte 'G' .byte '\' adc $8477 .byte $8F sta ($AA) and ($20),y eor $C745 and ($35) rol $CB,x and $31,x and ($CB) .byte $37 rol $38,x .byte $CB and ($38),y bcs $DE8A lda $39,x bcs $DE8B .byte $33 lda $4D,x eor $4D .byte 'O' eor ($59) jsr $4143 eor ($44) jsr $4554 .byte 'S' .byte 'T' ora $5345 .byte 'C' jsr $4F54 jsr $5845 eor #$54 ora $4554 .byte 'S' .byte 'T' jsr $4957 jmp $204C .byte 'T' eor ($4B,x) eor $A0 jsr $4553 .byte 'C' .byte 'O' lsr $5344 ora $4143 eor ($44) jsr $4953 phy eor $20 and $0DA0,x ora $4143 eor ($44) jsr $4146 eor #$4C eor $44 ora $0707 .byte $87 ora $430D eor ($52,x) .byte 'D' jsr $4B4F sta $4441 .byte 'D' eor ($45) .byte 'S' .byte 'S' jsr $5245 eor ($4F) cmp ($44) eor ($54,x) eor ($20,x) eor $52 eor ($4F) eor ($A0) jsr $A02D ora $4553 eor $20 .byte 'D' eor $41 jmp $5245 jsr $4F46 eor ($20) .byte 'S' eor $52 lsr $49,x .byte 'C' eor $8D bvc $DF2E .byte 'S' .byte 'S' eor $53 jsr $A03D .byte $FF cpy $55AA .byte $33 brk eor ($69) .byte 'c' pla jsr $6957 jmp ($696C) adc ($6D,x) .byte 's' .byte 'c' .byte 'o' bvs $DF84 adc ($69) .byte 'g' pla stz $20,x and ($39),y sec rol $20,x eor ($70,x) bvs $DF86 adc $20 .byte 'C' .byte 'o' adc $7570 stz $65,x adc ($20) eor #$6E .byte 'c' rol $6C61 jmp ($7220) adc #$67 pla stz $73,x jsr $6572 .byte 's' adc $72 ror $65,x stz $00 .res 8381 .word $C788 .word $C788 .word $C78E .endif ; .if ROMVER = 255	{ "language": "Assembly" }
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/// /// Perform several driver tests for OpenMP offloading /// // REQUIRES: clang-driver // REQUIRES: x86-registered-target // REQUIRES: powerpc-registered-target // REQUIRES: nvptx-registered-target /// ########################################################################### /// Check whether an invalid OpenMP target is specified: // RUN: %clang -### -fopenmp=libomp -fopenmp-targets=aaa-bbb-ccc-ddd %s 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-INVALID-TARGET %s // CHK-INVALID-TARGET: error: OpenMP target is invalid: 'aaa-bbb-ccc-ddd' /// ########################################################################### /// Check warning for empty -fopenmp-targets // RUN: %clang -### -fopenmp=libomp -fopenmp-targets= %s 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-EMPTY-OMPTARGETS %s // CHK-EMPTY-OMPTARGETS: warning: joined argument expects additional value: '-fopenmp-targets=' /// ########################################################################### /// Check error for no -fopenmp option // RUN: %clang -### -fopenmp-targets=powerpc64le-ibm-linux-gnu %s 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-NO-FOPENMP %s // RUN: %clang -### -fopenmp=libgomp -fopenmp-targets=powerpc64le-ibm-linux-gnu %s 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-NO-FOPENMP %s // CHK-NO-FOPENMP: error: The option -fopenmp-targets must be used in conjunction with a -fopenmp option compatible with offloading, please use -fopenmp=libomp or -fopenmp=libiomp5. /// ########################################################################### /// Check warning for duplicate offloading targets. // RUN: %clang -### -ccc-print-phases -fopenmp=libomp -fopenmp-targets=powerpc64le-ibm-linux-gnu,powerpc64le-ibm-linux-gnu %s 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-DUPLICATES %s // CHK-DUPLICATES: warning: The OpenMP offloading target 'powerpc64le-ibm-linux-gnu' is similar to target 'powerpc64le-ibm-linux-gnu' already specified - will be ignored. /// ########################################################################### /// Check -Xopenmp-target=powerpc64le-ibm-linux-gnu -mcpu=pwr7 is passed when compiling for the device. // RUN: %clang -### -no-canonical-prefixes -fopenmp=libomp -fopenmp-targets=powerpc64le-ibm-linux-gnu -Xopenmp-target=powerpc64le-ibm-linux-gnu -mcpu=pwr7 %s 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-FOPENMP-EQ-TARGET %s // CHK-FOPENMP-EQ-TARGET: clang{{.}} "-target-cpu" "pwr7" {{.}}"-fopenmp-is-device" /// ########################################################################### /// Check -Xopenmp-target -mcpu=pwr7 is passed when compiling for the device. // RUN: %clang -### -no-canonical-prefixes -fopenmp=libomp -fopenmp-targets=powerpc64le-ibm-linux-gnu -Xopenmp-target -mcpu=pwr7 %s 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-FOPENMP-TARGET %s // CHK-FOPENMP-TARGET: clang{{.}} "-target-cpu" "pwr7" {{.}}"-fopenmp-is-device" /// ########################################################################## /// Check -mcpu=pwr7 is passed to the same triple. // RUN: %clang -### -no-canonical-prefixes -fopenmp=libomp -fopenmp-targets=powerpc64le-ibm-linux-gnu -target powerpc64le-ibm-linux-gnu -mcpu=pwr7 %s 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-FOPENMP-MCPU-TO-SAME-TRIPLE %s // CHK-FOPENMP-MCPU-TO-SAME-TRIPLE: clang{{.}} "-target-cpu" "pwr7" {{.}}"-fopenmp-is-device" /// ########################################################################## /// Check -march=pwr7 is NOT passed to nvptx64-nvidia-cuda. // RUN: %clang -### -no-canonical-prefixes -fopenmp=libomp -fopenmp-targets=nvptx64-nvidia-cuda -target powerpc64le-ibm-linux-gnu -march=pwr7 %s 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-FOPENMP-MARCH-TO-GPU %s // CHK-FOPENMP-MARCH-TO-GPU-NOT: clang{{.}} "-target-cpu" "pwr7" {{.}}"-fopenmp-is-device" /// ########################################################################### /// Check -march=pwr7 is NOT passed to x86_64-unknown-linux-gnu. // RUN: %clang -### -no-canonical-prefixes -fopenmp=libomp -fopenmp-targets=x86_64-unknown-linux-gnu -target powerpc64le-ibm-linux-gnu -march=pwr7 %s 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-FOPENMP-MARCH-TO-X86 %s // CHK-FOPENMP-MARCH-TO-X86-NOT: clang{{.}} "-target-cpu" "pwr7" {{.}}"-fopenmp-is-device" /// ########################################################################### /// Check -Xopenmp-target triggers error when multiple triples are used. // RUN: %clang -### -no-canonical-prefixes -fopenmp=libomp -fopenmp-targets=powerpc64le-ibm-linux-gnu,powerpc64le-unknown-linux-gnu -Xopenmp-target -mcpu=pwr8 %s 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-FOPENMP-TARGET-AMBIGUOUS-ERROR %s // CHK-FOPENMP-TARGET-AMBIGUOUS-ERROR: clang{{.}} error: cannot deduce implicit triple value for -Xopenmp-target, specify triple using -Xopenmp-target=<triple> /// ########################################################################### /// Check -Xopenmp-target triggers error when an option requiring arguments is passed to it. // RUN: %clang -### -no-canonical-prefixes -fopenmp=libomp -fopenmp-targets=powerpc64le-ibm-linux-gnu -Xopenmp-target -Xopenmp-target -mcpu=pwr8 %s 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-FOPENMP-TARGET-NESTED-ERROR %s // CHK-FOPENMP-TARGET-NESTED-ERROR: clang{{.}} error: invalid -Xopenmp-target argument: '-Xopenmp-target -Xopenmp-target', options requiring arguments are unsupported /// ########################################################################### /// Check the phases graph when using a single target, different from the host. /// We should have an offload action joining the host compile and device /// preprocessor and another one joining the device linking outputs to the host /// action. // RUN: %clang -ccc-print-phases -fopenmp=libomp -target powerpc64le-ibm-linux-gnu -fopenmp-targets=x86_64-pc-linux-gnu %s 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-PHASES %s // CHK-PHASES: 0: input, "[[INPUT:.+\.c]]", c, (host-openmp) // CHK-PHASES: 1: preprocessor, {0}, cpp-output, (host-openmp) // CHK-PHASES: 2: compiler, {1}, ir, (host-openmp) // CHK-PHASES: 3: backend, {2}, assembler, (host-openmp) // CHK-PHASES: 4: assembler, {3}, object, (host-openmp) // CHK-PHASES: 5: linker, {4}, image, (host-openmp) // CHK-PHASES: 6: input, "[[INPUT]]", c, (device-openmp) // CHK-PHASES: 7: preprocessor, {6}, cpp-output, (device-openmp) // CHK-PHASES: 8: compiler, {7}, ir, (device-openmp) // CHK-PHASES: 9: offload, "host-openmp (powerpc64le-ibm-linux-gnu)" {2}, "device-openmp (x86_64-pc-linux-gnu)" {8}, ir // CHK-PHASES: 10: backend, {9}, assembler, (device-openmp) // CHK-PHASES: 11: assembler, {10}, object, (device-openmp) // CHK-PHASES: 12: linker, {11}, image, (device-openmp) // CHK-PHASES: 13: offload, "host-openmp (powerpc64le-ibm-linux-gnu)" {5}, "device-openmp (x86_64-pc-linux-gnu)" {12}, image /// ########################################################################### /// Check the phases when using multiple targets. Here we also add a library to /// make sure it is treated as input by the device. // RUN: %clang -ccc-print-phases -lsomelib -fopenmp=libomp -target powerpc64-ibm-linux-gnu -fopenmp-targets=x86_64-pc-linux-gnu,powerpc64-ibm-linux-gnu %s 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-PHASES-LIB %s // CHK-PHASES-LIB: 0: input, "somelib", object, (host-openmp) // CHK-PHASES-LIB: 1: input, "[[INPUT:.+\.c]]", c, (host-openmp) // CHK-PHASES-LIB: 2: preprocessor, {1}, cpp-output, (host-openmp) // CHK-PHASES-LIB: 3: compiler, {2}, ir, (host-openmp) // CHK-PHASES-LIB: 4: backend, {3}, assembler, (host-openmp) // CHK-PHASES-LIB: 5: assembler, {4}, object, (host-openmp) // CHK-PHASES-LIB: 6: linker, {0, 5}, image, (host-openmp) // CHK-PHASES-LIB: 7: input, "somelib", object, (device-openmp) // CHK-PHASES-LIB: 8: input, "[[INPUT]]", c, (device-openmp) // CHK-PHASES-LIB: 9: preprocessor, {8}, cpp-output, (device-openmp) // CHK-PHASES-LIB: 10: compiler, {9}, ir, (device-openmp) // CHK-PHASES-LIB: 11: offload, "host-openmp (powerpc64-ibm-linux-gnu)" {3}, "device-openmp (x86_64-pc-linux-gnu)" {10}, ir // CHK-PHASES-LIB: 12: backend, {11}, assembler, (device-openmp) // CHK-PHASES-LIB: 13: assembler, {12}, object, (device-openmp) // CHK-PHASES-LIB: 14: linker, {7, 13}, image, (device-openmp) // CHK-PHASES-LIB: 15: input, "somelib", object, (device-openmp) // CHK-PHASES-LIB: 16: input, "[[INPUT]]", c, (device-openmp) // CHK-PHASES-LIB: 17: preprocessor, {16}, cpp-output, (device-openmp) // CHK-PHASES-LIB: 18: compiler, {17}, ir, (device-openmp) // CHK-PHASES-LIB: 19: offload, "host-openmp (powerpc64-ibm-linux-gnu)" {3}, "device-openmp (powerpc64-ibm-linux-gnu)" {18}, ir // CHK-PHASES-LIB: 20: backend, {19}, assembler, (device-openmp) // CHK-PHASES-LIB: 21: assembler, {20}, object, (device-openmp) // CHK-PHASES-LIB: 22: linker, {15, 21}, image, (device-openmp) // CHK-PHASES-LIB: 23: offload, "host-openmp (powerpc64-ibm-linux-gnu)" {6}, "device-openmp (x86_64-pc-linux-gnu)" {14}, "device-openmp (powerpc64-ibm-linux-gnu)" {22}, image /// ########################################################################### /// Check the phases when using multiple targets and multiple source files // RUN: echo " " > %t.c // RUN: %clang -ccc-print-phases -lsomelib -fopenmp=libomp -target powerpc64-ibm-linux-gnu -fopenmp-targets=x86_64-pc-linux-gnu,powerpc64-ibm-linux-gnu %s %t.c 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-PHASES-FILES %s // CHK-PHASES-FILES: 0: input, "somelib", object, (host-openmp) // CHK-PHASES-FILES: 1: input, "[[INPUT1:.+\.c]]", c, (host-openmp) // CHK-PHASES-FILES: 2: preprocessor, {1}, cpp-output, (host-openmp) // CHK-PHASES-FILES: 3: compiler, {2}, ir, (host-openmp) // CHK-PHASES-FILES: 4: backend, {3}, assembler, (host-openmp) // CHK-PHASES-FILES: 5: assembler, {4}, object, (host-openmp) // CHK-PHASES-FILES: 6: input, "[[INPUT2:.+\.c]]", c, (host-openmp) // CHK-PHASES-FILES: 7: preprocessor, {6}, cpp-output, (host-openmp) // CHK-PHASES-FILES: 8: compiler, {7}, ir, (host-openmp) // CHK-PHASES-FILES: 9: backend, {8}, assembler, (host-openmp) // CHK-PHASES-FILES: 10: assembler, {9}, object, (host-openmp) // CHK-PHASES-FILES: 11: linker, {0, 5, 10}, image, (host-openmp) // CHK-PHASES-FILES: 12: input, "somelib", object, (device-openmp) // CHK-PHASES-FILES: 13: input, "[[INPUT1]]", c, (device-openmp) // CHK-PHASES-FILES: 14: preprocessor, {13}, cpp-output, (device-openmp) // CHK-PHASES-FILES: 15: compiler, {14}, ir, (device-openmp) // CHK-PHASES-FILES: 16: offload, "host-openmp (powerpc64-ibm-linux-gnu)" {3}, "device-openmp (x86_64-pc-linux-gnu)" {15}, ir // CHK-PHASES-FILES: 17: backend, {16}, assembler, (device-openmp) // CHK-PHASES-FILES: 18: assembler, {17}, object, (device-openmp) // CHK-PHASES-FILES: 19: input, "[[INPUT2]]", c, (device-openmp) // CHK-PHASES-FILES: 20: preprocessor, {19}, cpp-output, (device-openmp) // CHK-PHASES-FILES: 21: compiler, {20}, ir, (device-openmp) // CHK-PHASES-FILES: 22: offload, "host-openmp (powerpc64-ibm-linux-gnu)" {8}, "device-openmp (x86_64-pc-linux-gnu)" {21}, ir // CHK-PHASES-FILES: 23: backend, {22}, assembler, (device-openmp) // CHK-PHASES-FILES: 24: assembler, {23}, object, (device-openmp) // CHK-PHASES-FILES: 25: linker, {12, 18, 24}, image, (device-openmp) // CHK-PHASES-FILES: 26: input, "somelib", object, (device-openmp) // CHK-PHASES-FILES: 27: input, "[[INPUT1]]", c, (device-openmp) // CHK-PHASES-FILES: 28: preprocessor, {27}, cpp-output, (device-openmp) // CHK-PHASES-FILES: 29: compiler, {28}, ir, (device-openmp) // CHK-PHASES-FILES: 30: offload, "host-openmp (powerpc64-ibm-linux-gnu)" {3}, "device-openmp (powerpc64-ibm-linux-gnu)" {29}, ir // CHK-PHASES-FILES: 31: backend, {30}, assembler, (device-openmp) // CHK-PHASES-FILES: 32: assembler, {31}, object, (device-openmp) // CHK-PHASES-FILES: 33: input, "[[INPUT2]]", c, (device-openmp) // CHK-PHASES-FILES: 34: preprocessor, {33}, cpp-output, (device-openmp) // CHK-PHASES-FILES: 35: compiler, {34}, ir, (device-openmp) // CHK-PHASES-FILES: 36: offload, "host-openmp (powerpc64-ibm-linux-gnu)" {8}, "device-openmp (powerpc64-ibm-linux-gnu)" {35}, ir // CHK-PHASES-FILES: 37: backend, {36}, assembler, (device-openmp) // CHK-PHASES-FILES: 38: assembler, {37}, object, (device-openmp) // CHK-PHASES-FILES: 39: linker, {26, 32, 38}, image, (device-openmp) // CHK-PHASES-FILES: 40: offload, "host-openmp (powerpc64-ibm-linux-gnu)" {11}, "device-openmp (x86_64-pc-linux-gnu)" {25}, "device-openmp (powerpc64-ibm-linux-gnu)" {39}, image /// ########################################################################### /// Check the phases graph when using a single GPU target, and check the OpenMP /// and CUDA phases are articulated correctly. // RUN: %clang -ccc-print-phases -fopenmp=libomp -target powerpc64le-ibm-linux-gnu -fopenmp-targets=nvptx64-nvidia-cuda -x cuda %s 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-PHASES-WITH-CUDA %s // CHK-PHASES-WITH-CUDA: 0: input, "[[INPUT:.+\.c]]", cuda, (host-cuda-openmp) // CHK-PHASES-WITH-CUDA: 1: preprocessor, {0}, cuda-cpp-output, (host-cuda-openmp) // CHK-PHASES-WITH-CUDA: 2: compiler, {1}, ir, (host-cuda-openmp) // CHK-PHASES-WITH-CUDA: 3: input, "[[INPUT]]", cuda, (device-cuda, sm_20) // CHK-PHASES-WITH-CUDA: 4: preprocessor, {3}, cuda-cpp-output, (device-cuda, sm_20) // CHK-PHASES-WITH-CUDA: 5: compiler, {4}, ir, (device-cuda, sm_20) // CHK-PHASES-WITH-CUDA: 6: backend, {5}, assembler, (device-cuda, sm_20) // CHK-PHASES-WITH-CUDA: 7: assembler, {6}, object, (device-cuda, sm_20) // CHK-PHASES-WITH-CUDA: 8: offload, "device-cuda (nvptx64-nvidia-cuda:sm_20)" {7}, object // CHK-PHASES-WITH-CUDA: 9: offload, "device-cuda (nvptx64-nvidia-cuda:sm_20)" {6}, assembler // CHK-PHASES-WITH-CUDA: 10: linker, {8, 9}, cuda-fatbin, (device-cuda) // CHK-PHASES-WITH-CUDA: 11: offload, "host-cuda-openmp (powerpc64le-ibm-linux-gnu)" {2}, "device-cuda (nvptx64-nvidia-cuda)" {10}, ir // CHK-PHASES-WITH-CUDA: 12: backend, {11}, assembler, (host-cuda-openmp) // CHK-PHASES-WITH-CUDA: 13: assembler, {12}, object, (host-cuda-openmp) // CHK-PHASES-WITH-CUDA: 14: linker, {13}, image, (host-cuda-openmp) // CHK-PHASES-WITH-CUDA: 15: input, "[[INPUT]]", cuda, (device-openmp) // CHK-PHASES-WITH-CUDA: 16: preprocessor, {15}, cuda-cpp-output, (device-openmp) // CHK-PHASES-WITH-CUDA: 17: compiler, {16}, ir, (device-openmp) // CHK-PHASES-WITH-CUDA: 18: offload, "host-cuda-openmp (powerpc64le-ibm-linux-gnu)" {2}, "device-openmp (nvptx64-nvidia-cuda)" {17}, ir // CHK-PHASES-WITH-CUDA: 19: backend, {18}, assembler, (device-openmp) // CHK-PHASES-WITH-CUDA: 20: assembler, {19}, object, (device-openmp) // CHK-PHASES-WITH-CUDA: 21: linker, {20}, image, (device-openmp) // CHK-PHASES-WITH-CUDA: 22: offload, "host-cuda-openmp (powerpc64le-ibm-linux-gnu)" {14}, "device-openmp (nvptx64-nvidia-cuda)" {21}, image /// ########################################################################### /// Check of the commands passed to each tool when using valid OpenMP targets. /// Here we also check that offloading does not break the use of integrated /// assembler. It does however preclude the merge of the host compile and /// backend phases. There are also two offloading specific options: /// -fopenmp-is-device: will tell the frontend that it will generate code for a /// target. /// -fopenmp-host-ir-file-path: specifies the host IR file that can be loaded by /// the target code generation to gather information about which declaration /// really need to be emitted. /// We use -fopenmp-dump-offload-linker-script to dump the linker script and /// check its contents. /// // RUN: %clang -### -fopenmp=libomp -o %t.out -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %s -fopenmp-dump-offload-linker-script -no-canonical-prefixes 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-COMMANDS -check-prefix=CHK-LKS -check-prefix=CHK-LKS-REG %s // RUN: %clang -### -fopenmp=libomp -o %t.out -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %s -save-temps -fopenmp-dump-offload-linker-script -no-canonical-prefixes 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-COMMANDS-ST -check-prefix=CHK-LKS -check-prefix=CHK-LKS-ST %s // Make sure we are not dumping the script unless the user requested it. // RUN: %clang -### -fopenmp=libomp -o %t.out -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %s -no-canonical-prefixes 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-LKS-NODUMP %s // RUN: %clang -### -fopenmp=libomp -o %t.out -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %s -save-temps -no-canonical-prefixes 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-LKS-NODUMP %s // // Check the linker script contains what we expect. // // CHK-LKS: /* // CHK-LKS: OpenMP Offload Linker Script // CHK-LKS: * Automatically generated by Clang * // CHK-LKS-NODUMP-NOT: OpenMP Offload Linker Script. // CHK-LKS: / // CHK-LKS: TARGET(binary) // CHK-LKS-REG: INPUT([[T1BIN:.+\.out]]) // CHK-LKS-REG: INPUT([[T2BIN:.+\.out]]) // CHK-LKS-ST: INPUT([[T1BIN:.+\.out-openmp-powerpc64le-ibm-linux-gnu]]) // CHK-LKS-ST: INPUT([[T2BIN:.+\.out-openmp-x86_64-pc-linux-gnu]]) // CHK-LKS: SECTIONS // CHK-LKS: { // CHK-LKS: .omp_offloading.powerpc64le-ibm-linux-gnu : // CHK-LKS: ALIGN(0x10) // CHK-LKS: { // CHK-LKS: PROVIDE_HIDDEN(.omp_offloading.img_start.powerpc64le-ibm-linux-gnu = .); // CHK-LKS: [[T1BIN]] // CHK-LKS: PROVIDE_HIDDEN(.omp_offloading.img_end.powerpc64le-ibm-linux-gnu = .); // CHK-LKS: } // CHK-LKS: .omp_offloading.x86_64-pc-linux-gnu : // CHK-LKS: ALIGN(0x10) // CHK-LKS: { // CHK-LKS: PROVIDE_HIDDEN(.omp_offloading.img_start.x86_64-pc-linux-gnu = .); // CHK-LKS: [[T2BIN]] // CHK-LKS: PROVIDE_HIDDEN(.omp_offloading.img_end.x86_64-pc-linux-gnu = .); // CHK-LKS: } // CHK-LKS: .omp_offloading.entries : // CHK-LKS: ALIGN(0x10) // CHK-LKS: SUBALIGN(0x01) // CHK-LKS: { // CHK-LKS: PROVIDE_HIDDEN(.omp_offloading.entries_begin = .); // CHK-LKS: (.omp_offloading.entries) // CHK-LKS: PROVIDE_HIDDEN(.omp_offloading.entries_end = .); // CHK-LKS: } // CHK-LKS: } // CHK-LKS: INSERT BEFORE .data // // Generate host BC file. // // CHK-COMMANDS: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.}}"-o" " // CHK-COMMANDS-SAME: [[HOSTBC:[^\\/]+\.bc]]" "-x" "c" " // CHK-COMMANDS-SAME: [[INPUT:[^\\/]+\.c]]" "-fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu" // CHK-COMMANDS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-E" {{.}}"-fopenmp" {{.}}"-o" " // CHK-COMMANDS-ST-SAME: [[HOSTPP:[^\\/]+\.i]]" "-x" "c" " // CHK-COMMANDS-ST-SAME: [[INPUT:[^\\/]+\.c]]" // CHK-COMMANDS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.}}"-fopenmp" {{.}}"-o" " // CHK-COMMANDS-ST-SAME: [[HOSTBC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.}}[[HOSTPP]]" "-fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu" // // Compile for the powerpc device. // // CHK-COMMANDS: clang{{.}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-obj" {{.}}"-pic-level" "2" {{.}}"-fopenmp" {{.}}"-o" " // CHK-COMMANDS-SAME: [[T1OBJ:[^\\/]+\.o]]" "-x" "c" "{{.}}[[INPUT]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.}}[[HOSTBC]]" // CHK-COMMANDS: ld{{(\.exe)?}}" {{.}}"-o" " // CHK-COMMANDS-SAME: [[T1BIN:[^\\/]+\.out]]" {{.}}"{{.}}[[T1OBJ]]" // CHK-COMMANDS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-E" {{.}}"-fopenmp" {{.}}"-o" " // CHK-COMMANDS-ST-SAME: [[T1PP:[^\\/]+\.i]]" "-x" "c" "{{.}}[[INPUT]]" // CHK-COMMANDS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.}}"-pic-level" "2" {{.}}"-fopenmp" {{.}}"-o" " // CHK-COMMANDS-ST-SAME: [[T1BC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.}}[[T1PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.}}[[HOSTBC]]" // CHK-COMMANDS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-S" {{.}}"-fopenmp" {{.}}"-o" " // CHK-COMMANDS-ST-SAME: [[T1ASM:[^\\/]+\.s]]" "-x" "ir" "{{.}}[[T1BC]]" // CHK-COMMANDS-ST: clang{{.}}" "-cc1as" "-triple" "powerpc64le-ibm-linux-gnu" "-filetype" "obj" {{.}}"-o" " // CHK-COMMANDS-ST-SAME: [[T1OBJ:[^\\/]+\.o]]" "{{.}}[[T1ASM]]" // CHK-COMMANDS-ST: ld{{(\.exe)?}}" {{.}}"-shared" {{.}}"-o" " // CHK-COMMANDS-ST-SAME: [[T1BIN:[^\\/]+\.out-openmp-powerpc64le-ibm-linux-gnu]]" {{.}}"{{.}}[[T1OBJ]]" // // Compile for the x86 device. // // CHK-COMMANDS: clang{{.}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-obj" {{.}}"-pic-level" "2" {{.}}"-fopenmp" {{.}}"-o" " // CHK-COMMANDS-SAME: [[T2OBJ:[^\\/]+\.o]]" "-x" "c" "{{.}}[[INPUT]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.}}[[HOSTBC]]" // CHK-COMMANDS: ld{{(\.exe)?}}" {{.}}"-o" " // CHK-COMMANDS-SAME: [[T2BIN:[^\\/]+\.out]]" {{.}}"{{.}}[[T2OBJ]]" // CHK-COMMANDS-ST: clang{{.}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-E" {{.}}"-fopenmp" {{.}}"-o" " // CHK-COMMANDS-ST-SAME: [[T2PP:[^\\/]+\.i]]" "-x" "c" "{{.}}[[INPUT]]" // CHK-COMMANDS-ST: clang{{.}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.}}"-pic-level" "2" {{.}}"-fopenmp" {{.}}"-o" " // CHK-COMMANDS-ST-SAME: [[T2BC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.}}[[T2PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.}}[[HOSTBC]]" // CHK-COMMANDS-ST: clang{{.}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-S" {{.}}"-fopenmp" {{.}}"-o" " // CHK-COMMANDS-ST-SAME: [[T2ASM:[^\\/]+\.s]]" "-x" "ir" "{{.}}[[T2BC]]" // CHK-COMMANDS-ST: clang{{.}}" "-cc1as" "-triple" "x86_64-pc-linux-gnu" "-filetype" "obj" {{.}}"-o" " // CHK-COMMANDS-ST-SAME: [[T2OBJ:[^\\/]+\.o]]" "{{.}}[[T2ASM]]" // CHK-COMMANDS-ST: ld{{(\.exe)?}}" {{.}}"-shared" {{.}}"-o" " // CHK-COMMANDS-ST-SAME: [[T2BIN:[^\\/]+\.out-openmp-x86_64-pc-linux-gnu]]" {{.}}"{{.}}[[T2OBJ]]" // // Generate host object from the BC file and link using the linker script. // // CHK-COMMANDS: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-obj" {{.}}"-fopenmp" {{.}}"-o" " // CHK-COMMANDS-SAME: [[HOSTOBJ:[^\\/]+\.o]]" "-x" "ir" "{{.}}[[HOSTBC]]" // CHK-COMMANDS: ld{{(\.exe)?}}" {{.}}"-o" " // CHK-COMMANDS-SAME: [[HOSTBIN:[^\\/]+\.out]]" {{.}}"-lomptarget" {{.}}"-T" " // CHK-COMMANDS-SAME: [[HOSTLK:[^\\/]+\.lk]]" // CHK-COMMANDS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-S" {{.}}"-fopenmp" {{.}}"-o" " // CHK-COMMANDS-ST-SAME: [[HOSTASM:[^\\/]+\.s]]" "-x" "ir" "{{.}}[[HOSTBC]]" // CHK-COMMANDS-ST: clang{{.}}" "-cc1as" "-triple" "powerpc64le--linux" "-filetype" "obj" {{.}}"-o" " // CHK-COMMANDS-ST-SAME: [[HOSTOBJ:[^\\/]+\.o]]" "{{.}}[[HOSTASM]]" // CHK-COMMANDS-ST: ld{{(\.exe)?}}" {{.}}"-o" " // CHK-COMMANDS-ST-SAME: [[HOSTBIN:[^\\/]+\.out]]" {{.}}"-lomptarget" {{.}}"-T" " // CHK-COMMANDS-ST-SAME: [[HOSTLK:[^\\/]+\.lk]]" /// ########################################################################### /// Check separate compilation with offloading - bundling actions // RUN: %clang -### -ccc-print-phases -fopenmp=libomp -c -o %t.o -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %s -no-canonical-prefixes 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-BUACTIONS %s // CHK-BUACTIONS: 0: input, "[[INPUT:.+\.c]]", c, (host-openmp) // CHK-BUACTIONS: 1: preprocessor, {0}, cpp-output, (host-openmp) // CHK-BUACTIONS: 2: compiler, {1}, ir, (host-openmp) // CHK-BUACTIONS: 3: input, "[[INPUT]]", c, (device-openmp) // CHK-BUACTIONS: 4: preprocessor, {3}, cpp-output, (device-openmp) // CHK-BUACTIONS: 5: compiler, {4}, ir, (device-openmp) // CHK-BUACTIONS: 6: offload, "host-openmp (powerpc64le--linux)" {2}, "device-openmp (powerpc64le-ibm-linux-gnu)" {5}, ir // CHK-BUACTIONS: 7: backend, {6}, assembler, (device-openmp) // CHK-BUACTIONS: 8: assembler, {7}, object, (device-openmp) // CHK-BUACTIONS: 9: offload, "device-openmp (powerpc64le-ibm-linux-gnu)" {8}, object // CHK-BUACTIONS: 10: input, "[[INPUT]]", c, (device-openmp) // CHK-BUACTIONS: 11: preprocessor, {10}, cpp-output, (device-openmp) // CHK-BUACTIONS: 12: compiler, {11}, ir, (device-openmp) // CHK-BUACTIONS: 13: offload, "host-openmp (powerpc64le--linux)" {2}, "device-openmp (x86_64-pc-linux-gnu)" {12}, ir // CHK-BUACTIONS: 14: backend, {13}, assembler, (device-openmp) // CHK-BUACTIONS: 15: assembler, {14}, object, (device-openmp) // CHK-BUACTIONS: 16: offload, "device-openmp (x86_64-pc-linux-gnu)" {15}, object // CHK-BUACTIONS: 17: backend, {2}, assembler, (host-openmp) // CHK-BUACTIONS: 18: assembler, {17}, object, (host-openmp) // CHK-BUACTIONS: 19: clang-offload-bundler, {9, 16, 18}, object, (host-openmp) /// ########################################################################### /// Check separate compilation with offloading - unbundling actions // RUN: touch %t.i // RUN: %clang -### -ccc-print-phases -fopenmp=libomp -o %t.out -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %t.i -no-canonical-prefixes 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-UBACTIONS %s // CHK-UBACTIONS: 0: input, "somelib", object, (host-openmp) // CHK-UBACTIONS: 1: input, "[[INPUT:.+\.i]]", cpp-output, (host-openmp) // CHK-UBACTIONS: 2: clang-offload-unbundler, {1}, cpp-output, (host-openmp) // CHK-UBACTIONS: 3: compiler, {2}, ir, (host-openmp) // CHK-UBACTIONS: 4: backend, {3}, assembler, (host-openmp) // CHK-UBACTIONS: 5: assembler, {4}, object, (host-openmp) // CHK-UBACTIONS: 6: linker, {0, 5}, image, (host-openmp) // CHK-UBACTIONS: 7: input, "somelib", object, (device-openmp) // CHK-UBACTIONS: 8: compiler, {2}, ir, (device-openmp) // CHK-UBACTIONS: 9: offload, "host-openmp (powerpc64le--linux)" {3}, "device-openmp (powerpc64le-ibm-linux-gnu)" {8}, ir // CHK-UBACTIONS: 10: backend, {9}, assembler, (device-openmp) // CHK-UBACTIONS: 11: assembler, {10}, object, (device-openmp) // CHK-UBACTIONS: 12: linker, {7, 11}, image, (device-openmp) // CHK-UBACTIONS: 13: input, "somelib", object, (device-openmp) // CHK-UBACTIONS: 14: compiler, {2}, ir, (device-openmp) // CHK-UBACTIONS: 15: offload, "host-openmp (powerpc64le--linux)" {3}, "device-openmp (x86_64-pc-linux-gnu)" {14}, ir // CHK-UBACTIONS: 16: backend, {15}, assembler, (device-openmp) // CHK-UBACTIONS: 17: assembler, {16}, object, (device-openmp) // CHK-UBACTIONS: 18: linker, {13, 17}, image, (device-openmp) // CHK-UBACTIONS: 19: offload, "host-openmp (powerpc64le--linux)" {6}, "device-openmp (powerpc64le-ibm-linux-gnu)" {12}, "device-openmp (x86_64-pc-linux-gnu)" {18}, image /// ########################################################################### /// Check separate compilation with offloading - unbundling/bundling actions // RUN: touch %t.i // RUN: %clang -### -ccc-print-phases -fopenmp=libomp -c -o %t.o -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %t.i -no-canonical-prefixes 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-UBUACTIONS %s // CHK-UBUACTIONS: 0: input, "[[INPUT:.+\.i]]", cpp-output, (host-openmp) // CHK-UBUACTIONS: 1: clang-offload-unbundler, {0}, cpp-output, (host-openmp) // CHK-UBUACTIONS: 2: compiler, {1}, ir, (host-openmp) // CHK-UBUACTIONS: 3: compiler, {1}, ir, (device-openmp) // CHK-UBUACTIONS: 4: offload, "host-openmp (powerpc64le--linux)" {2}, "device-openmp (powerpc64le-ibm-linux-gnu)" {3}, ir // CHK-UBUACTIONS: 5: backend, {4}, assembler, (device-openmp) // CHK-UBUACTIONS: 6: assembler, {5}, object, (device-openmp) // CHK-UBUACTIONS: 7: offload, "device-openmp (powerpc64le-ibm-linux-gnu)" {6}, object // CHK-UBUACTIONS: 8: compiler, {1}, ir, (device-openmp) // CHK-UBUACTIONS: 9: offload, "host-openmp (powerpc64le--linux)" {2}, "device-openmp (x86_64-pc-linux-gnu)" {8}, ir // CHK-UBUACTIONS: 10: backend, {9}, assembler, (device-openmp) // CHK-UBUACTIONS: 11: assembler, {10}, object, (device-openmp) // CHK-UBUACTIONS: 12: offload, "device-openmp (x86_64-pc-linux-gnu)" {11}, object // CHK-UBUACTIONS: 13: backend, {2}, assembler, (host-openmp) // CHK-UBUACTIONS: 14: assembler, {13}, object, (host-openmp) // CHK-UBUACTIONS: 15: clang-offload-bundler, {7, 12, 14}, object, (host-openmp) /// ########################################################################### /// Check separate compilation with offloading - bundling jobs construct // RUN: %clang -### -fopenmp=libomp -c -o %t.o -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %s -no-canonical-prefixes 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-BUJOBS %s // RUN: %clang -### -fopenmp=libomp -c -o %t.o -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %s -save-temps -no-canonical-prefixes 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-BUJOBS-ST %s // Create host BC. // CHK-BUJOBS: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.}}"-fopenmp" {{.}}"-o" " // CHK-BUJOBS-SAME: [[HOSTBC:[^\\/]+\.bc]]" "-x" "c" " // CHK-BUJOBS-SAME: [[INPUT:[^\\/]+\.c]]" "-fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu" // CHK-BUJOBS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-E" {{.}}"-fopenmp" {{.}}"-o" " // CHK-BUJOBS-ST-SAME: [[HOSTPP:[^\\/]+\.i]]" "-x" "c" " // CHK-BUJOBS-ST-SAME: [[INPUT:[^\\/]+\.c]]" // CHK-BUJOBS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.}}"-fopenmp" {{.}}"-o" " // CHK-BUJOBS-ST-SAME: [[HOSTBC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.}}[[HOSTPP]]" "-fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu" // Create target 1 object. // CHK-BUJOBS: clang{{.}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-obj" {{.}}"-fopenmp" {{.}}"-o" " // CHK-BUJOBS-SAME: [[T1OBJ:[^\\/]+\.o]]" "-x" "c" "{{.}}[[INPUT]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.}}[[HOSTBC]]" // CHK-BUJOBS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-E" {{.}}"-fopenmp" {{.}}"-o" " // CHK-BUJOBS-ST-SAME: [[T1PP:[^\\/]+\.i]]" "-x" "c" "{{.}}[[INPUT]]" // CHK-BUJOBS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.}}"-fopenmp" {{.}}"-o" " // CHK-BUJOBS-ST-SAME: [[T1BC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.}}[[T1PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.}}[[HOSTBC]]" // CHK-BUJOBS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-S" {{.}}"-fopenmp" {{.}}"-o" " // CHK-BUJOBS-ST-SAME: [[T1ASM:[^\\/]+\.s]]" "-x" "ir" "{{.}}[[T1BC]]" // CHK-BUJOBS-ST: clang{{.}}" "-cc1as" "-triple" "powerpc64le-ibm-linux-gnu" "-filetype" "obj" {{.}}"-o" " // CHK-BUJOBS-ST-SAME: [[T1OBJ:[^\\/]+\.o]]" "{{.}}[[T1ASM]]" // Create target 2 object. // CHK-BUJOBS: clang{{.}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-obj" {{.}}"-fopenmp" {{.}}"-o" " // CHK-BUJOBS-SAME: [[T2OBJ:[^\\/]+\.o]]" "-x" "c" "{{.}}[[INPUT]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.}}[[HOSTBC]]" // CHK-BUJOBS-ST: clang{{.}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-E" {{.}}"-fopenmp" {{.}}"-o" " // CHK-BUJOBS-ST-SAME: [[T2PP:[^\\/]+\.i]]" "-x" "c" "{{.}}[[INPUT]]" // CHK-BUJOBS-ST: clang{{.}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.}}"-fopenmp" {{.}}"-o" " // CHK-BUJOBS-ST-SAME: [[T2BC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.}}[[T2PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.}}[[HOSTBC]]" // CHK-BUJOBS-ST: clang{{.}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-S" {{.}}"-fopenmp" {{.}}"-o" " // CHK-BUJOBS-ST-SAME: [[T2ASM:[^\\/]+\.s]]" "-x" "ir" "{{.}}[[T2BC]]" // CHK-BUJOBS-ST: clang{{.}}" "-cc1as" "-triple" "x86_64-pc-linux-gnu" "-filetype" "obj" {{.}}"-o" " // CHK-BUJOBS-ST-SAME: [[T2OBJ:[^\\/]+\.o]]" "{{.}}[[T2ASM]]" // Create host object and bundle. // CHK-BUJOBS: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-obj" {{.}}"-fopenmp" {{.}}"-o" " // CHK-BUJOBS-SAME: [[HOSTOBJ:[^\\/]+\.o]]" "-x" "ir" "{{.}}[[HOSTBC]]" // CHK-BUJOBS: clang-offload-bundler{{.}}" "-type=o" "-targets=openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu,host-powerpc64le--linux" "-outputs= // CHK-BUJOBS-SAME: [[RES:[^\\/]+\.o]]" "-inputs={{.}}[[T1OBJ]],{{.}}[[T2OBJ]],{{.}}[[HOSTOBJ]]" // CHK-BUJOBS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-S" {{.}}"-fopenmp" {{.}}"-o" " // CHK-BUJOBS-ST-SAME: [[HOSTASM:[^\\/]+\.s]]" "-x" "ir" "{{.}}[[HOSTBC]]" // CHK-BUJOBS-ST: clang{{.}}" "-cc1as" "-triple" "powerpc64le--linux" "-filetype" "obj" {{.}}"-o" " // CHK-BUJOBS-ST-SAME: [[HOSTOBJ:[^\\/]+\.o]]" "{{.}}[[HOSTASM]]" // CHK-BUJOBS-ST: clang-offload-bundler{{.}}" "-type=o" "-targets=openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu,host-powerpc64le--linux" "-outputs= // CHK-BUJOBS-ST-SAME: [[RES:[^\\/]+\.o]]" "-inputs={{.}}[[T1OBJ]],{{.}}[[T2OBJ]],{{.}}[[HOSTOBJ]]" /// ########################################################################### /// Check separate compilation with offloading - unbundling jobs construct // RUN: touch %t.i // RUN: %clang -### -fopenmp=libomp -o %t.out -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %t.i -no-canonical-prefixes 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-UBJOBS %s // RUN: %clang -### -fopenmp=libomp -o %t.out -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %t.i -save-temps -no-canonical-prefixes 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-UBJOBS-ST %s // RUN: touch %t.o // RUN: %clang -### -fopenmp=libomp -o %t.out -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %t.o -no-canonical-prefixes 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-UBJOBS2 %s // RUN: %clang -### -fopenmp=libomp -o %t.out -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %t.o -save-temps -no-canonical-prefixes 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-UBJOBS2-ST %s // Unbundle and create host BC. // CHK-UBJOBS: clang-offload-bundler{{.}}" "-type=i" "-targets=host-powerpc64le--linux,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu" "-inputs= // CHK-UBJOBS-SAME: [[INPUT:[^\\/]+\.i]]" "-outputs= // CHK-UBJOBS-SAME: [[HOSTPP:[^\\/]+\.i]], // CHK-UBJOBS-SAME: [[T1PP:[^\\/]+\.i]], // CHK-UBJOBS-SAME: [[T2PP:[^\\/]+\.i]]" "-unbundle" // CHK-UBJOBS: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBJOBS-SAME: [[HOSTBC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.}}[[HOSTPP]]" "-fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu" // CHK-UBJOBS-ST: clang-offload-bundler{{.}}" "-type=i" "-targets=host-powerpc64le--linux,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu" "-inputs= // CHK-UBJOBS-ST-SAME: [[INPUT:[^\\/]+\.i]]" "-outputs= // CHK-UBJOBS-ST-SAME: [[HOSTPP:[^\\/,]+\.i]], // CHK-UBJOBS-ST-SAME: [[T1PP:[^\\/,]+\.i]], // CHK-UBJOBS-ST-SAME: [[T2PP:[^\\/,]+\.i]]" "-unbundle" // CHK-UBJOBS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBJOBS-ST-SAME: [[HOSTBC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.}}[[HOSTPP]]" "-fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu" // Create target 1 object. // CHK-UBJOBS: clang{{.}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-obj" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBJOBS-SAME: [[T1OBJ:[^\\/]+\.o]]" "-x" "cpp-output" "{{.}}[[T1PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.}}[[HOSTBC]]" // CHK-UBJOBS: ld{{(\.exe)?}}" {{.}}"-o" " // CHK-UBJOBS-SAME: [[T1BIN:[^\\/]+\.out]]" {{.}}"{{.}}[[T1OBJ]]" // CHK-UBJOBS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBJOBS-ST-SAME: [[T1BC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.}}[[T1PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.}}[[HOSTBC]]" // CHK-UBJOBS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-S" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBJOBS-ST-SAME: [[T1ASM:[^\\/]+\.s]]" "-x" "ir" "{{.}}[[T1BC]]" // CHK-UBJOBS-ST: clang{{.}}" "-cc1as" "-triple" "powerpc64le-ibm-linux-gnu" "-filetype" "obj" {{.}}"-o" " // CHK-UBJOBS-ST-SAME: [[T1OBJ:[^\\/]+\.o]]" "{{.}}[[T1ASM]]" // CHK-UBJOBS-ST: ld{{(\.exe)?}}" {{.}}"-o" " // CHK-UBJOBS-ST-SAME: [[T1BIN:[^\\/]+\.out-openmp-powerpc64le-ibm-linux-gnu]]" {{.}}"{{.}}[[T1OBJ]]" // Create target 2 object. // CHK-UBJOBS: clang{{.}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-obj" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBJOBS-SAME: [[T2OBJ:[^\\/]+\.o]]" "-x" "cpp-output" "{{.}}[[T2PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.}}[[HOSTBC]]" // CHK-UBJOBS: ld{{(\.exe)?}}" {{.}}"-o" " // CHK-UBJOBS-SAME: [[T2BIN:[^\\/]+\.out]]" {{.}}"{{.}}[[T2OBJ]]" // CHK-UBJOBS-ST: clang{{.}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBJOBS-ST-SAME: [[T2BC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.}}[[T2PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.}}[[HOSTBC]]" // CHK-UBJOBS-ST: clang{{.}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-S" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBJOBS-ST-SAME: [[T2ASM:[^\\/]+\.s]]" "-x" "ir" "{{.}}[[T2BC]]" // CHK-UBJOBS-ST: clang{{.}}" "-cc1as" "-triple" "x86_64-pc-linux-gnu" "-filetype" "obj" {{.}}"-o" " // CHK-UBJOBS-ST-SAME: [[T2OBJ:[^\\/]+\.o]]" "{{.}}[[T2ASM]]" // CHK-UBJOBS-ST: ld{{(\.exe)?}}" {{.}}"-o" " // CHK-UBJOBS-ST-SAME: [[T2BIN:[^\\/]+\.out-openmp-x86_64-pc-linux-gnu]]" {{.}}"{{.}}[[T2OBJ]]" // Create binary. // CHK-UBJOBS: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-obj" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBJOBS-SAME: [[HOSTOBJ:[^\\/]+\.o]]" "-x" "ir" "{{.}}[[HOSTBC]]" // CHK-UBJOBS: ld{{(\.exe)?}}" {{.}}"-o" " // CHK-UBJOBS-SAME: [[HOSTBIN:[^\\/]+\.out]]" {{.}}"{{.}}[[HOSTOBJ]]" {{.}}"-T" " // CHK-UBJOBS-SAME: [[LKS:[^\\/]+\.lk]]" // CHK-UBJOBS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-S" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBJOBS-ST-SAME: [[HOSTASM:[^\\/]+\.s]]" "-x" "ir" "{{.}}[[HOSTBC]]" // CHK-UBJOBS-ST: clang{{.}}" "-cc1as" "-triple" "powerpc64le--linux" "-filetype" "obj" {{.}}"-o" " // CHK-UBJOBS-ST-SAME: [[HOSTOBJ:[^\\/]+\.o]]" "{{.}}[[HOSTASM]]" // CHK-UBJOBS-ST: ld{{(\.exe)?}}" {{.}}"-o" " // CHK-UBJOBS-ST-SAME: [[HOSTBIN:[^\\/]+\.out]]" {{.}}"{{.}}[[HOSTOBJ]]" {{.}}"-T" " // CHK-UBJOBS-ST-SAME: [[LKS:[^\\/]+\.lk]]" // Unbundle object file. // CHK-UBJOBS2: clang-offload-bundler{{.}}" "-type=o" "-targets=host-powerpc64le--linux,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu" "-inputs= // CHK-UBJOBS2-SAME: [[INPUT:[^\\/]+\.o]]" "-outputs= // CHK-UBJOBS2-SAME: [[HOSTOBJ:[^\\/]+\.o]], // CHK-UBJOBS2-SAME: [[T1OBJ:[^\\/]+\.o]], // CHK-UBJOBS2-SAME: [[T2OBJ:[^\\/]+\.o]]" "-unbundle" // CHK-UBJOBS2: ld{{(\.exe)?}}" {{.}}"-o" " // CHK-UBJOBS2-SAME: [[T1BIN:[^\\/]+\.out]]" {{.}}"{{.}}[[T1OBJ]]" // CHK-UBJOBS2: ld{{(\.exe)?}}" {{.}}"-o" " // CHK-UBJOBS2-SAME: [[T2BIN:[^\\/]+\.out]]" {{.}}"{{.}}[[T2OBJ]]" // CHK-UBJOBS2: ld{{(\.exe)?}}" {{.}}"-o" " // CHK-UBJOBS2-SAME: [[HOSTBIN:[^\\/]+\.out]]" {{.}}"{{.}}[[HOSTOBJ]]" {{.}}"-T" " // CHK-UBJOBS2-SAME: [[LKS:[^\\/]+\.lk]]" // CHK-UBJOBS2-ST: clang-offload-bundler{{.}}" "-type=o" "-targets=host-powerpc64le--linux,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu" "-inputs= // CHK-UBJOBS2-ST-SAME: [[INPUT:[^\\/]+\.o]]" "-outputs= // CHK-UBJOBS2-ST-SAME: [[HOSTOBJ:[^\\/,]+\.o]], // CHK-UBJOBS2-ST-SAME: [[T1OBJ:[^\\/,]+\.o]], // CHK-UBJOBS2-ST-SAME: [[T2OBJ:[^\\/,]+\.o]]" "-unbundle" // CHK-UBJOBS2-ST: ld{{(\.exe)?}}" {{.}}"-o" " // CHK-UBJOBS2-ST-SAME: [[T1BIN:[^\\/]+\.out-openmp-powerpc64le-ibm-linux-gnu]]" {{.}}"{{.}}[[T1OBJ]]" // CHK-UBJOBS2-ST: ld{{(\.exe)?}}" {{.}}"-o" " // CHK-UBJOBS2-ST-SAME: [[T2BIN:[^\\/]+\.out-openmp-x86_64-pc-linux-gnu]]" {{.}}"{{.}}[[T2OBJ]]" // CHK-UBJOBS2-ST: ld{{(\.exe)?}}" {{.}}"-o" " // CHK-UBJOBS2-ST-SAME: [[HOSTBIN:[^\\/]+\.out]]" {{.}}"{{.}}[[HOSTOBJ]]" {{.}}"-T" " // CHK-UBJOBS2-ST-SAME: [[LKS:[^\\/]+\.lk]]" /// ########################################################################### /// Check separate compilation with offloading - unbundling/bundling jobs /// construct // RUN: touch %t.i // RUN: %clang -### -fopenmp=libomp -c %t.o -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %t.i -no-canonical-prefixes 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-UBUJOBS %s // RUN: %clang -### -fopenmp=libomp -c %t.o -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %t.i -save-temps -no-canonical-prefixes 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-UBUJOBS-ST %s // Unbundle and create host BC. // CHK-UBUJOBS: clang-offload-bundler{{.}}" "-type=i" "-targets=host-powerpc64le--linux,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu" "-inputs= // CHK-UBUJOBS-SAME: [[INPUT:[^\\/]+\.i]]" "-outputs= // CHK-UBUJOBS-SAME: [[HOSTPP:[^\\/]+\.i]], // CHK-UBUJOBS-SAME: [[T1PP:[^\\/]+\.i]], // CHK-UBUJOBS-SAME: [[T2PP:[^\\/]+\.i]]" "-unbundle" // CHK-UBUJOBS: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBUJOBS-SAME: [[HOSTBC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.}}[[HOSTPP]]" "-fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu" // CHK-UBUJOBS-ST: clang-offload-bundler{{.}}" "-type=i" "-targets=host-powerpc64le--linux,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu" "-inputs= // CHK-UBUJOBS-ST-SAME: [[INPUT:[^\\/]+\.i]]" "-outputs= // CHK-UBUJOBS-ST-SAME: [[HOSTPP:[^\\/,]+\.i]], // CHK-UBUJOBS-ST-SAME: [[T1PP:[^\\/,]+\.i]], // CHK-UBUJOBS-ST-SAME: [[T2PP:[^\\/,]+\.i]]" "-unbundle" // CHK-UBUJOBS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBUJOBS-ST-SAME: [[HOSTBC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.}}[[HOSTPP]]" "-fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu" // Create target 1 object. // CHK-UBUJOBS: clang{{.}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-obj" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBUJOBS-SAME: [[T1OBJ:[^\\/]+\.o]]" "-x" "cpp-output" "{{.}}[[T1PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.}}[[HOSTBC]]" // CHK-UBUJOBS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBUJOBS-ST-SAME: [[T1BC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.}}[[T1PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.}}[[HOSTBC]]" // CHK-UBUJOBS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-S" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBUJOBS-ST-SAME: [[T1ASM:[^\\/]+\.s]]" "-x" "ir" "{{.}}[[T1BC]]" // CHK-UBUJOBS-ST: clang{{.}}" "-cc1as" "-triple" "powerpc64le-ibm-linux-gnu" "-filetype" "obj" {{.}}"-o" " // CHK-UBUJOBS-ST-SAME: [[T1OBJ:[^\\/]+\.o]]" "{{.}}[[T1ASM]]" // Create target 2 object. // CHK-UBUJOBS: clang{{.}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-obj" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBUJOBS-SAME: [[T2OBJ:[^\\/]+\.o]]" "-x" "cpp-output" "{{.}}[[T2PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.}}[[HOSTBC]]" // CHK-UBUJOBS-ST: clang{{.}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBUJOBS-ST-SAME: [[T2BC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.}}[[T2PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.}}[[HOSTBC]]" // CHK-UBUJOBS-ST: clang{{.}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-S" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBUJOBS-ST-SAME: [[T2ASM:[^\\/]+\.s]]" "-x" "ir" "{{.}}[[T2BC]]" // CHK-UBUJOBS-ST: clang{{.}}" "-cc1as" "-triple" "x86_64-pc-linux-gnu" "-filetype" "obj" {{.}}"-o" " // CHK-UBUJOBS-ST-SAME: [[T2OBJ:[^\\/]+\.o]]" "{{.}}[[T2ASM]]" // Create binary. // CHK-UBUJOBS: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-obj" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBUJOBS-SAME: [[HOSTOBJ:[^\\/]+\.o]]" "-x" "ir" "{{.}}[[HOSTBC]]" // CHK-UBUJOBS: clang-offload-bundler{{.}}" "-type=o" "-targets=openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu,host-powerpc64le--linux" "-outputs= // CHK-UBUJOBS-SAME: [[RES:[^\\/]+\.o]]" "-inputs={{.}}[[T1OBJ]],{{.}}[[T2OBJ]],{{.}}[[HOSTOBJ]]" // CHK-UBUJOBS-ST: clang{{.}}" "-cc1" "-triple" "powerpc64le--linux" "-S" {{.}}"-fopenmp" {{.}}"-o" " // CHK-UBUJOBS-ST-SAME: [[HOSTASM:[^\\/]+\.s]]" "-x" "ir" "{{.}}[[HOSTBC]]" // CHK-UBUJOBS-ST: clang{{.}}" "-cc1as" "-triple" "powerpc64le--linux" "-filetype" "obj" {{.}}"-o" " // CHK-UBUJOBS-ST-SAME: [[HOSTOBJ:[^\\/]+\.o]]" "{{.}}[[HOSTASM]]" // CHK-UBUJOBS-ST: clang-offload-bundler{{.}}" "-type=o" "-targets=openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu,host-powerpc64le--linux" "-outputs= // CHK-UBUJOBS-ST-SAME: [[RES:[^\\/]+\.o]]" "-inputs={{.}}[[T1OBJ]],{{.}}[[T2OBJ]],{{.}}[[HOSTOBJ]]" /// ########################################################################### /// Check -fopenmp-is-device is passed when compiling for the device. // RUN: %clang -### -no-canonical-prefixes -target powerpc64le-linux -fopenmp=libomp -fopenmp-targets=powerpc64le-ibm-linux-gnu %s 2>&1 \ // RUN: \| FileCheck -check-prefix=CHK-FOPENMP-IS-DEVICE %s // CHK-FOPENMP-IS-DEVICE: clang{{.}} "-aux-triple" "powerpc64le--linux" {{.*}}.c" "-fopenmp-is-device" "-fopenmp-host-ir-file-path"	{ "language": "Assembly" }
// RUN: %clangxx -fsycl-device-only -c -fno-color-diagnostics -Xclang -ast-dump %s -I %sycl_include -Wno-sycl-strict \| FileCheck %s // UNSUPPORTED: windows #include <CL/sycl/accessor.hpp> typedef cl::sycl::accessor<int, 1, cl::sycl::access::mode::read> dummy; // AccessorImplDevice must have MemRange and Offset fields // CHECK: CXXRecordDecl {{.}} class AccessorImplDevice definition // CHECK-NOT: CXXRecordDecl {{.}} definition // CHECK: FieldDecl {{.}} referenced Offset // CHECK-NOT: CXXRecordDecl {{.}} definition // CHECK: FieldDecl {{.}} referenced MemRange // accessor.impl must be present and of AccessorImplDevice type // CHECK: CXXRecordDecl {{.}} class accessor definition // CHECK-NOT: CXXRecordDecl {{.}} definition // CHECK: FieldDecl {{.}} referenced impl 'detail::AccessorImplDevice<AdjustedDim>'	{ "language": "Assembly" }
# REQUIRES: zlib # RUN: yaml2obj %p/Inputs/compress-debug-sections.yaml -o %t.o # RUN: llvm-objcopy --compress-debug-sections=zlib-gnu %t.o %t-compressed.o # RUN: llvm-objcopy --decompress-debug-sections %t-compressed.o %t-decompressed.o # RUN: llvm-objdump -s %t.o --section=.debug_foo \| FileCheck %s # RUN: llvm-objdump -s %t-compressed.o \| FileCheck %s --check-prefix=CHECK-COMPRESSED # RUN: llvm-readobj --relocations -S %t-compressed.o \| FileCheck %s --check-prefix=CHECK-FLAGS # RUN: llvm-readobj --relocations -S %t-decompressed.o \| FileCheck %s --check-prefix=CHECK-HEADER # RUN: llvm-readobj --relocations -S %t.o \| FileCheck %s --check-prefix=CHECK-HEADER # RUN: llvm-objdump -s %t-decompressed.o --section=.debug_foo \| FileCheck %s # CHECK: .debug_foo: # CHECK-NEXT: 0000 00000000 00000000 # CHECK-HEADER: Name: .debug_foo # CHECK-HEADER-NEXT: Type: SHT_PROGBITS # CHECK-HEADER-NEXT: Flags [ # CHECK-HEADER-NEXT: ] # CHECK-HEADER-NEXT: Address: # CHECK-HEADER-NEXT: Offset: # CHECK-HEADER-NEXT: Size: 8 # CHECK-COMPRESSED: .zdebug_foo: # CHECK-COMPRESSED: ZLIB # CHECK-COMPRESSED: .notdebug_foo: # CHECK-FLAGS-NOT: Name: .debug_foo # CHECK-FLAGS: Name: .zdebug_foo # CHECK-FLAGS-NEXT: Type: SHT_PROGBITS # CHECK-FLAGS-NEXT: Flags [ # CHECK-FLAGS-NEXT: ] # CHECK-FLAGS-NEXT: Address: # CHECK-FLAGS-NEXT: Offset: # CHECK-FLAGS-NEXT: Size: 23 # CHECK-FLAGS: Name: .notdebug_foo # CHECK-FLAGS-NEXT: Type: SHT_PROGBITS # CHECK-FLAGS-NEXT: Flags [ # CHECK-FLAGS-NEXT: ] # CHECK-FLAGS-NEXT: Address: # CHECK-FLAGS-NEXT: Offset: # CHECK-FLAGS-NEXT: Size: 8 # CHECK-FLAGS: Name: .rela.debug_foo # CHECK-FLAGS-NEXT: Type: SHT_RELA # CHECK-FLAGS-NEXT: Flags [ # CHECK-FLAGS-NEXT: ] # CHECK-FLAGS: Relocations [ # CHECK-FLAGS-NEXT: .rela.debug_foo { # CHECK-FLAGS-NEXT: 0x1 R_X86_64_32 .zdebug_foo 0x0 # CHECK-FLAGS-NEXT: 0x2 R_X86_64_32 .notdebug_foo 0x0 # CHECK-FLAGS-NEXT: } # CHECK-FLAGS-NEXT: ]	{ "language": "Assembly" }
diff -u -r a/usr/lib/libc.so b/usr/lib/libc.so --- a/usr/lib/libc.so 2016-12-30 23:00:08.284951863 +0900 +++ b/usr/lib/libc.so 2016-12-30 23:00:32.140951815 +0900 @@ -2,4 +2,4 @@ Use the shared library, but some functions are only in the static library, so try that secondarily. */ OUTPUT_FORMAT(elf32-littlearm) -GROUP ( /lib/libc.so.6 /usr/lib/libc_nonshared.a AS_NEEDED ( /lib/ld-linux.so.3 ) ) +GROUP ( libc.so.6 libc_nonshared.a AS_NEEDED ( ld-linux.so.3 ) )	{ "language": "Assembly" }
;Flag tables for normal and extended Intel opcodes ;(c) sars [HI-TECH] 2003 ;[email protected] ; ;Version: ;01-test version ;02-added: TableEXT ;03-added: new flags ;04-added: support for MMX, SSE, SSE2, 3DNOW ; ;Description: ;Size of table element is 4 bits. ;0h-one byte instruction ;1h-ModRM byte ;2h-imm8,rel8 etc ;4h-ptr16 etc ;8h-imm16/32,rel16/32 etc ;0Fh-prefix ;0Eh-unsupported opcodes ;3DNOW-Supported ;SSE-Supported ;SSE2-Supported ;MMX-Supported ;================NORMAL OPCODES================ c_Table: ; 01 23 45 67 89 AB CD EF db 011h,011h,028h,000h,011h,011h,028h,000h;0Fh db 011h,011h,028h,000h,011h,011h,028h,000h;1Fh db 011h,011h,028h,0F0h,011h,011h,028h,0F0h;2Fh db 011h,011h,028h,0F0h,011h,011h,028h,0F0h;3Fh db 000h,000h,000h,000h,000h,000h,000h,000h;4Fh db 000h,000h,000h,000h,000h,000h,000h,000h;5Fh db 000h,011h,0FFh,0FFh,089h,023h,000h,000h;6Fh db 022h,022h,022h,022h,022h,022h,022h,022h;7Fh db 039h,033h,011h,011h,011h,011h,011h,011h;8Fh db 000h,000h,000h,000h,000h,0C0h,000h,000h;9Fh db 088h,088h,000h,000h,028h,000h,000h,000h;AFh db 022h,022h,022h,022h,088h,088h,088h,088h;BFh db 033h,040h,011h,039h,060h,040h,002h,000h;CFh db 011h,011h,022h,000h,011h,011h,011h,011h;DFh db 022h,022h,022h,022h,088h,0C2h,000h,000h;EFh db 0F0h,0FFh,000h,011h,000h,000h,000h,011h;FFh ;============================================== Lentable equ $-c_Table ;===============EXTENDED OPCODES=============== c_TableEXT: ; 01 23 45 67 89 AB CD EF db 011h,011h,0E0h,000h,000h,0EEh,0E1h,003h;0Fh db 011h,011h,011h,011h,01Eh,0EEh,0EEh,0EEh;1Fh db 011h,011h,01Eh,01Eh,011h,011h,011h,011h;2Fh db 000h,000h,000h,0EEh,0EEh,0EEh,0EEh,0EEh;3Fh db 011h,011h,011h,011h,011h,011h,011h,011h;4Fh db 011h,011h,011h,011h,011h,011h,011h,011h;5Fh db 011h,011h,011h,011h,011h,011h,011h,011h;6Fh db 033h,033h,011h,010h,011h,011h,011h,011h;7Fh db 088h,088h,088h,088h,088h,088h,088h,088h;8Fh db 011h,011h,011h,011h,011h,011h,011h,011h;9Fh db 000h,001h,031h,011h,000h,001h,031h,011h;AFh db 011h,011h,011h,011h,0EEh,031h,011h,011h;BFh db 011h,031h,033h,031h,000h,000h,000h,000h;CFh db 0E1h,011h,011h,011h,011h,011h,011h,011h;DFh db 011h,011h,011h,011h,011h,011h,011h,011h;EFh db 0E1h,011h,011h,011h,011h,011h,011h,01Eh;FFh ;==============================================	{ "language": "Assembly" }
;/---------------------------------------------------------------------------------------------------------/ ;/* Holtek Semiconductor Inc. / ;/ / ;/ Copyright (C) Holtek Semiconductor Inc. / ;/ All rights reserved. / ;/ / ;/----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_iar_03_iap.s ; Version : $Rev:: 4151 $ ; Date : $Date:: 2019-07-24 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------/ ; Supported Device ; ======================================== ; HT32F0008 ; HT32F52142 ; HT32F52344, HT32F52354 ; HT32F52357, HT32F52367 ;/ <<< Use Configuration Wizard in Context Menu >>> / ;// <o> HT32 Device ;// <0=> By Project Asm Define ;// <6=> HT32F0008 ;// <6=> HT32F52142 ;// <9=> HT32F52344/54 ;// <11=> HT32F52357/67 USE_HT32_CHIP_SET EQU 0 _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00000008 ;_HT32FWID EQU 0x00052142 ;_HT32FWID EQU 0x00052344 ;_HT32FWID EQU 0x00052354 ;_HT32FWID EQU 0x00052357 ;_HT32FWID EQU 0x00052367 HT32F0008 EQU 6 HT32F52142 EQU 6 HT32F52344_54 EQU 9 HT32F52357_67 EQU 11 IF USE_HT32_CHIP_SET=0 ELSE #undef USE_HT32_CHIP #define USE_HT32_CHIP USE_HT32_CHIP_SET ENDIF MODULE ?cstartup ;; Forward declaration of sections. SECTION CSTACKIAP:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) EXTERN __iar_program_start EXTERN SystemInit PUBLIC __vector_table ;**************************************************************************** ; Fill-up the Vector Table entries with the exceptions ISR address ;***************************************************************************** DATA _RESERVED EQU 0xFFFFFFFF __vector_table DCD sfe(CSTACKIAP) ; ---, 00, 0x000, Top address of Stack DCD Reset_Handler ; ---, 01, 0x004, Reset Handler DCD NMI_Handler ; -14, 02, 0x008, NMI Handler DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler DCD _RESERVED ; ---, 04, 0x010, Reserved DCD _RESERVED ; ---, 05, 0x014, Reserved DCD _RESERVED ; ---, 06, 0x018, Reserved DCD _RESERVED ; ---, 07, 0x01C, Reserved DCD _HT32FWID ; ---, 08, 0x020, Reserved DCD _RESERVED ; ---, 09, 0x024, Reserved DCD _RESERVED ; ---, 10, 0x028, Reserved DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler DCD _RESERVED ; ---, 12, 0x030, Reserved DCD _RESERVED ; ---, 13, 0x034, Reserved DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler SECTION .usartisr:CODE:ROOT(2) EXTERN UxART_IRQHandler DATA DCD UxART_IRQHandler THUMB PUBWEAK Reset_Handler SECTION .text:CODE:REORDER:NOROOT(2) Reset_Handler LDR R0, =BootProcess BLX R0 LDR R0, =SystemInit BLX R0 LDR R0, =__iar_program_start BX R0 BootProcess LDR R0, =0x40080300 LDR R1,[R0, #0x10] CMP R1, #0 BNE BP1 LDR R1,[R0, #0x14] CMP R1, #0 BNE BP1 LDR R1,[R0, #0x18] CMP R1, #0 BNE BP1 LDR R1,[R0, #0x1C] CMP R1, #0 BEQ BP2 BP1 LDR R0, =0x40080180 LDR R1,[R0, #0xC] LSLS R1, R1, #4 LSRS R1, R1, #20 CMP R1, #0 BEQ BP3 CMP R1, #5 BEQ BP3 CMP R1, #6 BEQ BP3 BP2 DSB LDR R0, =0x20000000 LDR R1, =0x05fa0004 STR R1, [R0] LDR R1, =0xe000ed00 LDR R0, =0x05fa0004 STR R0, [R1, #0xC] DSB B . BP3 LDR R0, =0x20000000 LDR R1, [R0] LDR R0, =0x05fa0004 CMP R0, R1 BEQ BP4 BX LR BP4 LDR R0, =0x40088100 LDR R1, =0x00000001 STR R1, [R0] LDR R0, =0x20000000 LDR R1, =0x0 STR R1, [R0] BX LR PUBWEAK NMI_Handler SECTION .text:CODE:REORDER:NOROOT(1) NMI_Handler B . PUBWEAK HardFault_Handler SECTION .text:CODE:REORDER:NOROOT(1) HardFault_Handler B . PUBWEAK SVC_Handler SECTION .text:CODE:REORDER:NOROOT(1) SVC_Handler B . PUBWEAK PendSV_Handler SECTION .text:CODE:REORDER:NOROOT(1) PendSV_Handler B . PUBWEAK SysTick_Handler SECTION .text:CODE:REORDER:NOROOT(1) SysTick_Handler B . PUBWEAK LVD_BOD_IRQHandler PUBWEAK RTC_IRQHandler PUBWEAK FLASH_IRQHandler PUBWEAK EVWUP_IRQHandler PUBWEAK EXTI0_1_IRQHandler PUBWEAK EXTI2_3_IRQHandler PUBWEAK EXTI4_15_IRQHandler PUBWEAK COMP_IRQHandler PUBWEAK COMP_DAC_IRQHandler PUBWEAK ADC_IRQHandler PUBWEAK MCTM0_IRQHandler PUBWEAK GPTM0_IRQHandler PUBWEAK SCTM0_IRQHandler PUBWEAK SCTM1_IRQHandler PUBWEAK PWM0_IRQHandler PUBWEAK PWM1_IRQHandler PUBWEAK BFTM0_IRQHandler PUBWEAK BFTM1_IRQHandler PUBWEAK I2C0_IRQHandler PUBWEAK I2C1_IRQHandler PUBWEAK SPI0_IRQHandler PUBWEAK SPI1_IRQHandler PUBWEAK QSPI_IRQHandler PUBWEAK USART0_IRQHandler PUBWEAK USART1_IRQHandler PUBWEAK UART0_IRQHandler PUBWEAK UART1_IRQHandler PUBWEAK UART0_UART2_IRQHandler PUBWEAK UART1_UART3_IRQHandler PUBWEAK SCI_IRQHandler PUBWEAK I2S_IRQHandler PUBWEAK AES_IRQHandler PUBWEAK USB_IRQHandler PUBWEAK PDMA_CH0_1_IRQHandler PUBWEAK PDMA_CH2_5_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) LVD_BOD_IRQHandler RTC_IRQHandler FLASH_IRQHandler EVWUP_IRQHandler EXTI0_1_IRQHandler EXTI2_3_IRQHandler EXTI4_15_IRQHandler COMP_IRQHandler COMP_DAC_IRQHandler ADC_IRQHandler MCTM0_IRQHandler GPTM0_IRQHandler SCTM0_IRQHandler SCTM1_IRQHandler PWM0_IRQHandler PWM1_IRQHandler BFTM0_IRQHandler BFTM1_IRQHandler I2C0_IRQHandler I2C1_IRQHandler SPI0_IRQHandler SPI1_IRQHandler QSPI_IRQHandler USART0_IRQHandler USART1_IRQHandler UART0_IRQHandler UART1_IRQHandler UART0_UART2_IRQHandler UART1_UART3_IRQHandler SCI_IRQHandler I2S_IRQHandler AES_IRQHandler USB_IRQHandler PDMA_CH0_1_IRQHandler PDMA_CH2_5_IRQHandler B . END	{ "language": "Assembly" }
.TH libssh2_channel_ignore_extended_data 3 "20 Feb 2010" "libssh2 1.2.4" "libssh2 manual" .SH NAME libssh2_channel_ignore_extended_data - convenience macro for \fIlibssh2_channel_handle_extended_data(3)\fP calls .SH SYNOPSIS #include <libssh2.h> libssh2_channel_ignore_extended_data(arguments) .SH DESCRIPTION This function is deprecated. Use the \fIlibssh2_channel_handle_extended_data2(3)\fP function instead! This is a macro defined in a public libssh2 header file that is using the underlying function \fIlibssh2_channel_handle_extended_data(3)\fP. .SH RETURN VALUE See \fIlibssh2_channel_handle_extended_data(3)\fP .SH ERRORS See \fIlibssh2_channel_handle_extended_data(3)\fP .SH SEE ALSO .BR libssh2_channel_handle_extended_data(3)	{ "language": "Assembly" }
# . $ . '' . -LRB- . -RRB- . , . . . : . ADD X AFX PRT CC CONJ CD NUM DT DET EX DET FW X GW X HYPH . IN ADP JJ ADJ JJR ADJ JJS ADJ LS X MD VERB NFP . NN NOUN NNP NOUN NNPS NOUN NNS NOUN PDT DET POS PRT PRP PRON PRP$ PRON RB ADV RBR ADV RBS ADV RP PRT SYM X TO PRT UH X VB VERB VBD VERB VBG VERB VBN VERB VBP VERB VBZ VERB WDT DET WP PRON WP$ PRON WRB ADV `` . X X XX X	{ "language": "Assembly" }
rv32uf-p-fcmp: file format elf32-littleriscv Disassembly of section .text.init: 80000000 <_start>: 80000000: 04c0006f j 8000004c <reset_vector> 80000004 <trap_vector>: 80000004: 34202f73 csrr t5,mcause 80000008: 00800f93 li t6,8 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> 80000010: 00900f93 li t6,9 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> 80000018: 00b00f93 li t6,11 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> 80000020: 80000f17 auipc t5,0x80000 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> 8000002c: 000f0067 jr t5 80000030: 34202f73 csrr t5,mcause 80000034: 000f5463 bgez t5,8000003c <handle_exception> 80000038: 0040006f j 8000003c <handle_exception> 8000003c <handle_exception>: 8000003c: 5391e193 ori gp,gp,1337 80000040 <write_tohost>: 80000040: 00001f17 auipc t5,0x1 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> 80000048: ff9ff06f j 80000040 <write_tohost> 8000004c <reset_vector>: 8000004c: f1402573 csrr a0,mhartid 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> 80000054: 00000297 auipc t0,0x0 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> 8000005c: 30529073 csrw mtvec,t0 80000060: 18005073 csrwi satp,0 80000064: 00000297 auipc t0,0x0 80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38> 8000006c: 30529073 csrw mtvec,t0 80000070: 800002b7 lui t0,0x80000 80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdf0f> 80000078: 3b029073 csrw pmpaddr0,t0 8000007c: 01f00293 li t0,31 80000080: 3a029073 csrw pmpcfg0,t0 80000084: 00000297 auipc t0,0x0 80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50> 8000008c: 30529073 csrw mtvec,t0 80000090: 30205073 csrwi medeleg,0 80000094: 30305073 csrwi mideleg,0 80000098: 30405073 csrwi mie,0 8000009c: 00000193 li gp,0 800000a0: 00000297 auipc t0,0x0 800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector> 800000a8: 30529073 csrw mtvec,t0 800000ac: 00100513 li a0,1 800000b0: 01f51513 slli a0,a0,0x1f 800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78> 800000b8: 0ff0000f fence 800000bc: 00100193 li gp,1 800000c0: 00000073 ecall 800000c4: 80000297 auipc t0,0x80000 800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000> 800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c> 800000d0: 10529073 csrw stvec,t0 800000d4: 0000b2b7 lui t0,0xb 800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> 800000dc: 30229073 csrw medeleg,t0 800000e0: 30202373 csrr t1,medeleg 800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception> 800000e8: 30005073 csrwi mstatus,0 800000ec: 00002537 lui a0,0x2 800000f0: 30052073 csrs mstatus,a0 800000f4: 00305073 csrwi fcsr,0 800000f8: 00000297 auipc t0,0x0 800000fc: 01428293 addi t0,t0,20 # 8000010c <test_2> 80000100: 34129073 csrw mepc,t0 80000104: f1402573 csrr a0,mhartid 80000108: 30200073 mret 8000010c <test_2>: 8000010c: 00200193 li gp,2 80000110: 00002517 auipc a0,0x2 80000114: ef050513 addi a0,a0,-272 # 80002000 <test_2_data> 80000118: 00052007 flw ft0,0(a0) 8000011c: 00452087 flw ft1,4(a0) 80000120: 00852107 flw ft2,8(a0) 80000124: 00c52683 lw a3,12(a0) 80000128: a0102553 feq.s a0,ft0,ft1 8000012c: 001015f3 fsflags a1,zero 80000130: 00000613 li a2,0 80000134: 2ad51663 bne a0,a3,800003e0 <fail> 80000138: 2ac59463 bne a1,a2,800003e0 <fail> 8000013c <test_3>: 8000013c: 00300193 li gp,3 80000140: 00002517 auipc a0,0x2 80000144: ed050513 addi a0,a0,-304 # 80002010 <test_3_data> 80000148: 00052007 flw ft0,0(a0) 8000014c: 00452087 flw ft1,4(a0) 80000150: 00852107 flw ft2,8(a0) 80000154: 00c52683 lw a3,12(a0) 80000158: a0100553 fle.s a0,ft0,ft1 8000015c: 001015f3 fsflags a1,zero 80000160: 00000613 li a2,0 80000164: 26d51e63 bne a0,a3,800003e0 <fail> 80000168: 26c59c63 bne a1,a2,800003e0 <fail> 8000016c <test_4>: 8000016c: 00400193 li gp,4 80000170: 00002517 auipc a0,0x2 80000174: eb050513 addi a0,a0,-336 # 80002020 <test_4_data> 80000178: 00052007 flw ft0,0(a0) 8000017c: 00452087 flw ft1,4(a0) 80000180: 00852107 flw ft2,8(a0) 80000184: 00c52683 lw a3,12(a0) 80000188: a0101553 flt.s a0,ft0,ft1 8000018c: 001015f3 fsflags a1,zero 80000190: 00000613 li a2,0 80000194: 24d51663 bne a0,a3,800003e0 <fail> 80000198: 24c59463 bne a1,a2,800003e0 <fail> 8000019c <test_5>: 8000019c: 00500193 li gp,5 800001a0: 00002517 auipc a0,0x2 800001a4: e9050513 addi a0,a0,-368 # 80002030 <test_5_data> 800001a8: 00052007 flw ft0,0(a0) 800001ac: 00452087 flw ft1,4(a0) 800001b0: 00852107 flw ft2,8(a0) 800001b4: 00c52683 lw a3,12(a0) 800001b8: a0102553 feq.s a0,ft0,ft1 800001bc: 001015f3 fsflags a1,zero 800001c0: 00000613 li a2,0 800001c4: 20d51e63 bne a0,a3,800003e0 <fail> 800001c8: 20c59c63 bne a1,a2,800003e0 <fail> 800001cc <test_6>: 800001cc: 00600193 li gp,6 800001d0: 00002517 auipc a0,0x2 800001d4: e7050513 addi a0,a0,-400 # 80002040 <test_6_data> 800001d8: 00052007 flw ft0,0(a0) 800001dc: 00452087 flw ft1,4(a0) 800001e0: 00852107 flw ft2,8(a0) 800001e4: 00c52683 lw a3,12(a0) 800001e8: a0100553 fle.s a0,ft0,ft1 800001ec: 001015f3 fsflags a1,zero 800001f0: 00000613 li a2,0 800001f4: 1ed51663 bne a0,a3,800003e0 <fail> 800001f8: 1ec59463 bne a1,a2,800003e0 <fail> 800001fc <test_7>: 800001fc: 00700193 li gp,7 80000200: 00002517 auipc a0,0x2 80000204: e5050513 addi a0,a0,-432 # 80002050 <test_7_data> 80000208: 00052007 flw ft0,0(a0) 8000020c: 00452087 flw ft1,4(a0) 80000210: 00852107 flw ft2,8(a0) 80000214: 00c52683 lw a3,12(a0) 80000218: a0101553 flt.s a0,ft0,ft1 8000021c: 001015f3 fsflags a1,zero 80000220: 00000613 li a2,0 80000224: 1ad51e63 bne a0,a3,800003e0 <fail> 80000228: 1ac59c63 bne a1,a2,800003e0 <fail> 8000022c <test_8>: 8000022c: 00800193 li gp,8 80000230: 00002517 auipc a0,0x2 80000234: e3050513 addi a0,a0,-464 # 80002060 <test_8_data> 80000238: 00052007 flw ft0,0(a0) 8000023c: 00452087 flw ft1,4(a0) 80000240: 00852107 flw ft2,8(a0) 80000244: 00c52683 lw a3,12(a0) 80000248: a0102553 feq.s a0,ft0,ft1 8000024c: 001015f3 fsflags a1,zero 80000250: 00000613 li a2,0 80000254: 18d51663 bne a0,a3,800003e0 <fail> 80000258: 18c59463 bne a1,a2,800003e0 <fail> 8000025c <test_9>: 8000025c: 00900193 li gp,9 80000260: 00002517 auipc a0,0x2 80000264: e1050513 addi a0,a0,-496 # 80002070 <test_9_data> 80000268: 00052007 flw ft0,0(a0) 8000026c: 00452087 flw ft1,4(a0) 80000270: 00852107 flw ft2,8(a0) 80000274: 00c52683 lw a3,12(a0) 80000278: a0102553 feq.s a0,ft0,ft1 8000027c: 001015f3 fsflags a1,zero 80000280: 00000613 li a2,0 80000284: 14d51e63 bne a0,a3,800003e0 <fail> 80000288: 14c59c63 bne a1,a2,800003e0 <fail> 8000028c <test_10>: 8000028c: 00a00193 li gp,10 80000290: 00002517 auipc a0,0x2 80000294: df050513 addi a0,a0,-528 # 80002080 <test_10_data> 80000298: 00052007 flw ft0,0(a0) 8000029c: 00452087 flw ft1,4(a0) 800002a0: 00852107 flw ft2,8(a0) 800002a4: 00c52683 lw a3,12(a0) 800002a8: a0102553 feq.s a0,ft0,ft1 800002ac: 001015f3 fsflags a1,zero 800002b0: 01000613 li a2,16 800002b4: 12d51663 bne a0,a3,800003e0 <fail> 800002b8: 12c59463 bne a1,a2,800003e0 <fail> 800002bc <test_11>: 800002bc: 00b00193 li gp,11 800002c0: 00002517 auipc a0,0x2 800002c4: dd050513 addi a0,a0,-560 # 80002090 <test_11_data> 800002c8: 00052007 flw ft0,0(a0) 800002cc: 00452087 flw ft1,4(a0) 800002d0: 00852107 flw ft2,8(a0) 800002d4: 00c52683 lw a3,12(a0) 800002d8: a0101553 flt.s a0,ft0,ft1 800002dc: 001015f3 fsflags a1,zero 800002e0: 01000613 li a2,16 800002e4: 0ed51e63 bne a0,a3,800003e0 <fail> 800002e8: 0ec59c63 bne a1,a2,800003e0 <fail> 800002ec <test_12>: 800002ec: 00c00193 li gp,12 800002f0: 00002517 auipc a0,0x2 800002f4: db050513 addi a0,a0,-592 # 800020a0 <test_12_data> 800002f8: 00052007 flw ft0,0(a0) 800002fc: 00452087 flw ft1,4(a0) 80000300: 00852107 flw ft2,8(a0) 80000304: 00c52683 lw a3,12(a0) 80000308: a0101553 flt.s a0,ft0,ft1 8000030c: 001015f3 fsflags a1,zero 80000310: 01000613 li a2,16 80000314: 0cd51663 bne a0,a3,800003e0 <fail> 80000318: 0cc59463 bne a1,a2,800003e0 <fail> 8000031c <test_13>: 8000031c: 00d00193 li gp,13 80000320: 00002517 auipc a0,0x2 80000324: d9050513 addi a0,a0,-624 # 800020b0 <test_13_data> 80000328: 00052007 flw ft0,0(a0) 8000032c: 00452087 flw ft1,4(a0) 80000330: 00852107 flw ft2,8(a0) 80000334: 00c52683 lw a3,12(a0) 80000338: a0101553 flt.s a0,ft0,ft1 8000033c: 001015f3 fsflags a1,zero 80000340: 01000613 li a2,16 80000344: 08d51e63 bne a0,a3,800003e0 <fail> 80000348: 08c59c63 bne a1,a2,800003e0 <fail> 8000034c <test_14>: 8000034c: 00e00193 li gp,14 80000350: 00002517 auipc a0,0x2 80000354: d7050513 addi a0,a0,-656 # 800020c0 <test_14_data> 80000358: 00052007 flw ft0,0(a0) 8000035c: 00452087 flw ft1,4(a0) 80000360: 00852107 flw ft2,8(a0) 80000364: 00c52683 lw a3,12(a0) 80000368: a0100553 fle.s a0,ft0,ft1 8000036c: 001015f3 fsflags a1,zero 80000370: 01000613 li a2,16 80000374: 06d51663 bne a0,a3,800003e0 <fail> 80000378: 06c59463 bne a1,a2,800003e0 <fail> 8000037c <test_15>: 8000037c: 00f00193 li gp,15 80000380: 00002517 auipc a0,0x2 80000384: d5050513 addi a0,a0,-688 # 800020d0 <test_15_data> 80000388: 00052007 flw ft0,0(a0) 8000038c: 00452087 flw ft1,4(a0) 80000390: 00852107 flw ft2,8(a0) 80000394: 00c52683 lw a3,12(a0) 80000398: a0100553 fle.s a0,ft0,ft1 8000039c: 001015f3 fsflags a1,zero 800003a0: 01000613 li a2,16 800003a4: 02d51e63 bne a0,a3,800003e0 <fail> 800003a8: 02c59c63 bne a1,a2,800003e0 <fail> 800003ac <test_16>: 800003ac: 01000193 li gp,16 800003b0: 00002517 auipc a0,0x2 800003b4: d3050513 addi a0,a0,-720 # 800020e0 <test_16_data> 800003b8: 00052007 flw ft0,0(a0) 800003bc: 00452087 flw ft1,4(a0) 800003c0: 00852107 flw ft2,8(a0) 800003c4: 00c52683 lw a3,12(a0) 800003c8: a0100553 fle.s a0,ft0,ft1 800003cc: 001015f3 fsflags a1,zero 800003d0: 01000613 li a2,16 800003d4: 00d51663 bne a0,a3,800003e0 <fail> 800003d8: 00c59463 bne a1,a2,800003e0 <fail> 800003dc: 00301c63 bne zero,gp,800003f4 <pass> 800003e0 <fail>: 800003e0: 0ff0000f fence 800003e4: 00018063 beqz gp,800003e4 <fail+0x4> 800003e8: 00119193 slli gp,gp,0x1 800003ec: 0011e193 ori gp,gp,1 800003f0: 00000073 ecall 800003f4 <pass>: 800003f4: 0ff0000f fence 800003f8: 00100193 li gp,1 800003fc: 00000073 ecall 80000400: c0001073 unimp Disassembly of section .data: 80002000 <test_2_data>: 80002000: bfae147b 0xbfae147b 80002004: bfae147b 0xbfae147b 80002008: 0000 unimp 8000200a: 0000 unimp 8000200c: 0001 nop 8000200e: 0000 unimp 80002010 <test_3_data>: 80002010: bfae147b 0xbfae147b 80002014: bfae147b 0xbfae147b 80002018: 0000 unimp 8000201a: 0000 unimp 8000201c: 0001 nop 8000201e: 0000 unimp 80002020 <test_4_data>: 80002020: bfae147b 0xbfae147b 80002024: bfae147b 0xbfae147b 80002028: 0000 unimp 8000202a: 0000 unimp 8000202c: 0000 unimp 8000202e: 0000 unimp 80002030 <test_5_data>: 80002030: 5c29 li s8,-22 80002032: 147bbfaf 0x147bbfaf 80002036: bfae fsd fa1,504(sp) 80002038: 0000 unimp 8000203a: 0000 unimp 8000203c: 0000 unimp 8000203e: 0000 unimp 80002040 <test_6_data>: 80002040: 5c29 li s8,-22 80002042: 147bbfaf 0x147bbfaf 80002046: bfae fsd fa1,504(sp) 80002048: 0000 unimp 8000204a: 0000 unimp 8000204c: 0001 nop 8000204e: 0000 unimp 80002050 <test_7_data>: 80002050: 5c29 li s8,-22 80002052: 147bbfaf 0x147bbfaf 80002056: bfae fsd fa1,504(sp) 80002058: 0000 unimp 8000205a: 0000 unimp 8000205c: 0001 nop 8000205e: 0000 unimp 80002060 <test_8_data>: 80002060: ffff 0xffff 80002062: 7fff 0x7fff 80002064: 0000 unimp 80002066: 0000 unimp 80002068: 0000 unimp 8000206a: 0000 unimp 8000206c: 0000 unimp 8000206e: 0000 unimp 80002070 <test_9_data>: 80002070: ffff 0xffff 80002072: 7fff 0x7fff 80002074: ffff 0xffff 80002076: 7fff 0x7fff 80002078: 0000 unimp 8000207a: 0000 unimp 8000207c: 0000 unimp 8000207e: 0000 unimp 80002080 <test_10_data>: 80002080: 0001 nop 80002082: 7f80 flw fs0,56(a5) 80002084: 0000 unimp 80002086: 0000 unimp 80002088: 0000 unimp 8000208a: 0000 unimp 8000208c: 0000 unimp 8000208e: 0000 unimp 80002090 <test_11_data>: 80002090: ffff 0xffff 80002092: 7fff 0x7fff 80002094: 0000 unimp 80002096: 0000 unimp 80002098: 0000 unimp 8000209a: 0000 unimp 8000209c: 0000 unimp 8000209e: 0000 unimp 800020a0 <test_12_data>: 800020a0: ffff 0xffff 800020a2: 7fff 0x7fff 800020a4: ffff 0xffff 800020a6: 7fff 0x7fff 800020a8: 0000 unimp 800020aa: 0000 unimp 800020ac: 0000 unimp 800020ae: 0000 unimp 800020b0 <test_13_data>: 800020b0: 0001 nop 800020b2: 7f80 flw fs0,56(a5) 800020b4: 0000 unimp 800020b6: 0000 unimp 800020b8: 0000 unimp 800020ba: 0000 unimp 800020bc: 0000 unimp 800020be: 0000 unimp 800020c0 <test_14_data>: 800020c0: ffff 0xffff 800020c2: 7fff 0x7fff 800020c4: 0000 unimp 800020c6: 0000 unimp 800020c8: 0000 unimp 800020ca: 0000 unimp 800020cc: 0000 unimp 800020ce: 0000 unimp 800020d0 <test_15_data>: 800020d0: ffff 0xffff 800020d2: 7fff 0x7fff 800020d4: ffff 0xffff 800020d6: 7fff 0x7fff 800020d8: 0000 unimp 800020da: 0000 unimp 800020dc: 0000 unimp 800020de: 0000 unimp 800020e0 <test_16_data>: 800020e0: 0001 nop 800020e2: 7f80 flw fs0,56(a5) 800020e4: 0000 unimp 800020e6: 0000 unimp 800020e8: 0000 unimp 800020ea: 0000 unimp 800020ec: 0000 unimp 800020ee: 0000 unimp	{ "language": "Assembly" }
vasm is a portable and retargetable assembler to create linkable objects in various formats or absolute code. Currently the following CPUs are officially supported: M680x0 family (including M6888x, M68851 and CPU32) ColdFire family (all models of V2, V3, V4, V4e) 80x86 family (IA32 8/16/32 bit, using MIT-syntax) PowerPC family (POWER, 40x, 440, 460, 6xx, 7xx, 860, Book-E, e300 and e500) ARM (architecture ARMv1 to ARMv4, including THUMB mode) Jaguar RISC (GPU and DSP instruction sets) Z80 family (Z80, 8080, GBZ80, 64180, RCM2/3/4k) C16x/ST10 6502 & 6800 family (6800, 6801, 6803, 68HC11) QNICE (elegant 16-bit FPGA CPU) TR3200 (virtual CPU from 0x10c) Raspberry-Pi VideoCore IV These syntax flavours are supported: Standard MIT (GNU-as style) syntax Motorola/Freescale 68k syntax (Devpac compatible) Atari MadMac syntax (6502, 68k, Jaguar) Old 8-bit style syntax WWW: http://sun.hasenbraten.de/vasm/	{ "language": "Assembly" }
\| 2 1 1 4 Ꙁ 4 2 1 4 , 4 4 1 6 - 4 4 4 1 ꙃ 4 4 4 4 _ 4 4 4 6 ' 6 2 1 1 a 4 4 2 2 B 4 2 1 2 b 6 3 1 2 C 4 2 1 2 c 4 4 2 2 d 2 2 1 2 E 4 2 1 2 H 4 2 1 2 e 4 4 2 2 f 2 2 1 2 G 4 2 1 2 g 4 4 2 4 h 2 2 1 2 I 4 2 1 2 i 4 6 1 2 k 2 2 1 2 K 4 2 1 2 l 2 2 1 2 m 4 4 2 2 n 4 4 2 2 O 4 2 1 2 o 4 4 2 2 P 4 2 1 2 p 4 4 2 4 q 4 4 2 4 r 4 4 2 2 s 4 4 2 2 t 2 2 1 2 T 4 2 1 2 U 4 2 1 2 u 4 4 2 2 V 4 2 1 2 v 4 4 2 2 w 4 4 2 2 X 4 2 1 2 x 4 4 2 2 Y 4 2 1 2 y 4 4 2 4 Z 4 2 1 2 z 4 4 2 2 А 4 2 1 2 а 4 4 2 2 б 2 1 1 2 Б 4 2 1 2 В 4 2 1 2 в 4 4 2 2 Г 4 2 1 2 г 4 4 2 2 Д 4 2 1 4 Є 4 2 1 2 є 4 4 2 2 Ё 1 1 1 2 ё 2 1 1 2 Ж 4 2 1 2 ж 4 4 2 2 З 4 2 1 2 з 4 4 2 2 Ѕ 4 2 1 2 ѕ 4 4 2 2 И 4 2 1 2 и 4 4 2 2 І 4 2 1 2 і 4 6 1 2 Ї 1 1 1 2 ї 4 6 1 2 Й 1 1 1 2 й 2 1 1 2 К 4 2 1 2 к 4 4 2 2 Л 4 2 1 2 л 4 4 2 2 М 4 2 1 2 м 4 4 2 2 Н 4 2 1 2 н 4 4 2 2 О 4 2 1 2 о 4 4 2 2 П 4 2 1 2 п 4 4 2 2 Р 4 2 1 2 р 4 4 1 4 С 4 2 1 2 с 4 4 2 2 Т 4 2 1 2 т 4 4 2 2 У 4 2 1 2 ф 2 1 1 4 Ф 4 2 1 2 Х 4 2 1 2 х 4 4 2 2 Ц 4 2 1 4 Ч 4 2 1 2 ч 4 4 2 2 Ш 4 2 1 2 ш 4 4 2 2 Щ 4 2 1 4 Ъ 4 2 1 2 ъ 4 4 2 2 Ь 4 2 1 2 ь 4 4 2 2 Э 4 2 1 2 э 4 4 2 2 Ю 4 2 1 2 ю 4 4 2 2 Я 4 2 1 2 я 4 4 2 2	{ "language": "Assembly" }
// Copyright 2009 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build !gccgo #include "textflag.h" // // System call support for AMD64, DragonFly // // Just jump to package syscall's implementation for all these functions. // The runtime may know about them. TEXT ·Syscall(SB),NOSPLIT,$0-56 JMP syscall·Syscall(SB) TEXT ·Syscall6(SB),NOSPLIT,$0-80 JMP syscall·Syscall6(SB) TEXT ·Syscall9(SB),NOSPLIT,$0-104 JMP syscall·Syscall9(SB) TEXT ·RawSyscall(SB),NOSPLIT,$0-56 JMP syscall·RawSyscall(SB) TEXT ·RawSyscall6(SB),NOSPLIT,$0-80 JMP syscall·RawSyscall6(SB)	{ "language": "Assembly" }
; RUN: llc < %s -mtriple=i386-apple-darwin -no-integrated-as ; rdar://6781755 ; PR3934 %0 = type { i32, i32 } ; type %0 define void @bn_sqr_comba8(i32* nocapture %r, i32* %a) nounwind { entry: %asmtmp23 = tail call %0 asm "mulq $3", "={ax},={dx},{ax},m,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32 %a) nounwind ; <%0> [#uses=1] %asmresult25 = extractvalue %0 %asmtmp23, 1 ; <i32> [#uses=1] %asmtmp26 = tail call %0 asm "addq $0,$0; adcq $2,$1", "={dx},=r,imr,0,1,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32 %asmresult25, i32 0) nounwind ; <%0> [#uses=1] %asmresult27 = extractvalue %0 %asmtmp26, 0 ; <i32> [#uses=1] %asmtmp29 = tail call %0 asm "addq $0,$0; adcq $2,$1", "={ax},={dx},imr,0,1,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32 0, i32 %asmresult27) nounwind ; <%0> [#uses=0] ret void }	{ "language": "Assembly" }
#!/bin/bash # SPDX-License-Identifier: GPL-2.0 # # Test various interface configuration scenarios. Observe that configurations # deemed valid by mlxsw succeed, invalid configurations fail and that no traces # are produced. To prevent the test from passing in case traces are produced, # the user can set the 'kernel.panic_on_warn' and 'kernel.panic_on_oops' # sysctls in its environment. lib_dir=$(dirname $0)/../../../net/forwarding ALL_TESTS=" rif_set_addr_test rif_vrf_set_addr_test rif_inherit_bridge_addr_test rif_non_inherit_bridge_addr_test vlan_interface_deletion_test bridge_deletion_test bridge_vlan_flags_test vlan_1_test lag_bridge_upper_test duplicate_vlans_test vlan_rif_refcount_test subport_rif_refcount_test vlan_dev_deletion_test lag_unlink_slaves_test lag_dev_deletion_test vlan_interface_uppers_test bridge_extern_learn_test neigh_offload_test nexthop_offload_test devlink_reload_test " NUM_NETIFS=2 : ${TIMEOUT:=20000} # ms source $lib_dir/lib.sh source $lib_dir/devlink_lib.sh setup_prepare() { swp1=${NETIFS[p1]} swp2=${NETIFS[p2]} ip link set dev $swp1 up ip link set dev $swp2 up } cleanup() { pre_cleanup ip link set dev $swp2 down ip link set dev $swp1 down } rif_set_addr_test() { local swp1_mac=$(mac_get $swp1) local swp2_mac=$(mac_get $swp2) RET=0 # $swp1 and $swp2 likely got their IPv6 local addresses already, but # here we need to test the transition to RIF. ip addr flush dev $swp1 ip addr flush dev $swp2 sleep .1 ip addr add dev $swp1 192.0.2.1/28 check_err $? ip link set dev $swp1 addr 00:11:22:33:44:55 check_err $? # IP address enablement should be rejected if the MAC address prefix # doesn't match other RIFs. ip addr add dev $swp2 192.0.2.2/28 &>/dev/null check_fail $? "IP address addition passed for a device with a wrong MAC" ip addr add dev $swp2 192.0.2.2/28 2>&1 >/dev/null \ \| grep -q mlxsw_spectrum check_err $? "no extack for IP address addition" ip link set dev $swp2 addr 00:11:22:33:44:66 check_err $? ip addr add dev $swp2 192.0.2.2/28 &>/dev/null check_err $? # Change of MAC address of a RIF should be forbidden if the new MAC # doesn't share the prefix with other MAC addresses. ip link set dev $swp2 addr 00:11:22:33:00:66 &>/dev/null check_fail $? "change of MAC address passed for a wrong MAC" ip link set dev $swp2 addr 00:11:22:33:00:66 2>&1 >/dev/null \ \| grep -q mlxsw_spectrum check_err $? "no extack for MAC address change" log_test "RIF - bad MAC change" ip addr del dev $swp2 192.0.2.2/28 ip addr del dev $swp1 192.0.2.1/28 ip link set dev $swp2 addr $swp2_mac ip link set dev $swp1 addr $swp1_mac } rif_vrf_set_addr_test() { # Test that it is possible to set an IP address on a VRF upper despite # its random MAC address. RET=0 ip link add name vrf-test type vrf table 10 ip link set dev $swp1 master vrf-test ip -4 address add 192.0.2.1/24 dev vrf-test check_err $? "failed to set IPv4 address on VRF" ip -6 address add 2001:db8:1::1/64 dev vrf-test check_err $? "failed to set IPv6 address on VRF" log_test "RIF - setting IP address on VRF" ip link del dev vrf-test } rif_inherit_bridge_addr_test() { RET=0 # Create first RIF ip addr add dev $swp1 192.0.2.1/28 check_err $? # Create a FID RIF ip link add name br1 up type bridge vlan_filtering 0 ip link set dev $swp2 master br1 ip addr add dev br1 192.0.2.17/28 check_err $? # Prepare a device with a low MAC address ip link add name d up type dummy ip link set dev d addr 00:11:22:33:44:55 # Attach the device to br1. That prompts bridge address change, which # should be vetoed, thus preventing the attachment. ip link set dev d master br1 &>/dev/null check_fail $? "Device with low MAC was permitted to attach a bridge with RIF" ip link set dev d master br1 2>&1 >/dev/null \ \| grep -q mlxsw_spectrum check_err $? "no extack for bridge attach rejection" ip link set dev $swp2 addr 00:11:22:33:44:55 &>/dev/null check_fail $? "Changing swp2's MAC address permitted" ip link set dev $swp2 addr 00:11:22:33:44:55 2>&1 >/dev/null \ \| grep -q mlxsw_spectrum check_err $? "no extack for bridge port MAC address change rejection" log_test "RIF - attach port with bad MAC to bridge" ip link del dev d ip link del dev br1 ip addr del dev $swp1 192.0.2.1/28 } rif_non_inherit_bridge_addr_test() { local swp2_mac=$(mac_get $swp2) RET=0 # Create first RIF ip addr add dev $swp1 192.0.2.1/28 check_err $? # Create a FID RIF ip link add name br1 up type bridge vlan_filtering 0 ip link set dev br1 addr $swp2_mac ip link set dev $swp2 master br1 ip addr add dev br1 192.0.2.17/28 check_err $? # Prepare a device with a low MAC address ip link add name d up type dummy ip link set dev d addr 00:11:22:33:44:55 # Attach the device to br1. Since the bridge address was set, it should # work. ip link set dev d master br1 &>/dev/null check_err $? "Could not attach a device with low MAC to a bridge with RIF" # Port MAC address change should be allowed for a bridge with set MAC. ip link set dev $swp2 addr 00:11:22:33:44:55 check_err $? "Changing swp2's MAC address not permitted" log_test "RIF - attach port with bad MAC to bridge with set MAC" ip link set dev $swp2 addr $swp2_mac ip link del dev d ip link del dev br1 ip addr del dev $swp1 192.0.2.1/28 } vlan_interface_deletion_test() { # Test that when a VLAN interface is deleted, its associated router # interface (RIF) is correctly deleted and not leaked. See commit # c360867ec46a ("mlxsw: spectrum: Delete RIF when VLAN device is # removed") for more details RET=0 ip link add name br0 type bridge vlan_filtering 1 ip link set dev $swp1 master br0 ip link add link br0 name br0.10 type vlan id 10 ip -6 address add 2001:db8:1::1/64 dev br0.10 ip link del dev br0.10 # If we leaked the previous RIF, then this should produce a trace ip link add link br0 name br0.20 type vlan id 20 ip -6 address add 2001:db8:1::1/64 dev br0.20 ip link del dev br0.20 log_test "vlan interface deletion" ip link del dev br0 } bridge_deletion_test() { # Test that when a bridge with VLAN interfaces is deleted, we correctly # delete the associated RIFs. See commit 602b74eda813 ("mlxsw: # spectrum_switchdev: Do not leak RIFs when removing bridge") for more # details RET=0 ip link add name br0 type bridge vlan_filtering 1 ip link set dev $swp1 master br0 ip -6 address add 2001:db8::1/64 dev br0 ip link add link br0 name br0.10 type vlan id 10 ip -6 address add 2001:db8:1::1/64 dev br0.10 ip link add link br0 name br0.20 type vlan id 20 ip -6 address add 2001:db8:2::1/64 dev br0.20 ip link del dev br0 # If we leaked previous RIFs, then this should produce a trace ip -6 address add 2001:db8:1::1/64 dev $swp1 ip -6 address del 2001:db8:1::1/64 dev $swp1 log_test "bridge deletion" } bridge_vlan_flags_test() { # Test that when bridge VLAN flags are toggled, we do not take # unnecessary references on related structs. See commit 9e25826ffc94 # ("mlxsw: spectrum_switchdev: Fix port_vlan refcounting") for more # details RET=0 ip link add name br0 type bridge vlan_filtering 1 ip link set dev $swp1 master br0 bridge vlan add vid 10 dev $swp1 pvid untagged bridge vlan add vid 10 dev $swp1 untagged bridge vlan add vid 10 dev $swp1 pvid bridge vlan add vid 10 dev $swp1 ip link del dev br0 # If we did not handle references correctly, then this should produce a # trace devlink dev reload "$DEVLINK_DEV" # Allow netdevices to be re-created following the reload sleep 20 log_test "bridge vlan flags" } vlan_1_test() { # Test that VLAN 1 can be configured over mlxsw ports. In the past it # was used internally for untagged traffic. See commit 47bf9df2e820 # ("mlxsw: spectrum: Forbid creation of VLAN 1 over port/LAG") for more # details RET=0 ip link add link $swp1 name $swp1.1 type vlan id 1 check_err $? "did not manage to create vlan 1 when should" log_test "vlan 1" ip link del dev $swp1.1 } lag_bridge_upper_test() { # Test that ports cannot be enslaved to LAG devices that have uppers # and that failure is handled gracefully. See commit b3529af6bb0d # ("spectrum: Reference count VLAN entries") for more details RET=0 ip link add name bond1 type bond mode 802.3ad ip link add name br0 type bridge vlan_filtering 1 ip link set dev bond1 master br0 ip link set dev $swp1 down ip link set dev $swp1 master bond1 &> /dev/null check_fail $? "managed to enslave port to lag when should not" # This might generate a trace, if we did not handle the failure # correctly ip -6 address add 2001:db8:1::1/64 dev $swp1 ip -6 address del 2001:db8:1::1/64 dev $swp1 log_test "lag with bridge upper" ip link del dev br0 ip link del dev bond1 } duplicate_vlans_test() { # Test that on a given port a VLAN is only used once. Either as VLAN # in a VLAN-aware bridge or as a VLAN device RET=0 ip link add name br0 type bridge vlan_filtering 1 ip link set dev $swp1 master br0 bridge vlan add vid 10 dev $swp1 ip link add link $swp1 name $swp1.10 type vlan id 10 &> /dev/null check_fail $? "managed to create vlan device when should not" bridge vlan del vid 10 dev $swp1 ip link add link $swp1 name $swp1.10 type vlan id 10 check_err $? "did not manage to create vlan device when should" bridge vlan add vid 10 dev $swp1 &> /dev/null check_fail $? "managed to add bridge vlan when should not" log_test "duplicate vlans" ip link del dev $swp1.10 ip link del dev br0 } vlan_rif_refcount_test() { # Test that RIFs representing VLAN interfaces are not affected from # ports member in the VLAN. We use the offload indication on routes # configured on the RIF to understand if it was created / destroyed RET=0 ip link add name br0 type bridge vlan_filtering 1 ip link set dev $swp1 master br0 ip link set dev $swp1 up ip link set dev br0 up ip link add link br0 name br0.10 up type vlan id 10 ip -6 address add 2001:db8:1::1/64 dev br0.10 busywait "$TIMEOUT" wait_for_offload \ ip -6 route get fibmatch 2001:db8:1::2 dev br0.10 check_err $? "vlan rif was not created before adding port to vlan" bridge vlan add vid 10 dev $swp1 busywait "$TIMEOUT" wait_for_offload \ ip -6 route get fibmatch 2001:db8:1::2 dev br0.10 check_err $? "vlan rif was destroyed after adding port to vlan" bridge vlan del vid 10 dev $swp1 busywait "$TIMEOUT" wait_for_offload \ ip -6 route get fibmatch 2001:db8:1::2 dev br0.10 check_err $? "vlan rif was destroyed after removing port from vlan" ip link set dev $swp1 nomaster busywait "$TIMEOUT" not wait_for_offload \ ip -6 route get fibmatch 2001:db8:1::2 dev br0.10 check_err $? "vlan rif was not destroyed after unlinking port from bridge" log_test "vlan rif refcount" ip link del dev br0.10 ip link set dev $swp1 down ip link del dev br0 } subport_rif_refcount_test() { # Test that RIFs representing upper devices of physical ports are # reference counted correctly and destroyed when should. We use the # offload indication on routes configured on the RIF to understand if # it was created / destroyed RET=0 ip link add name bond1 type bond mode 802.3ad ip link set dev $swp1 down ip link set dev $swp2 down ip link set dev $swp1 master bond1 ip link set dev $swp2 master bond1 ip link set dev bond1 up ip link add link bond1 name bond1.10 up type vlan id 10 ip -6 address add 2001:db8:1::1/64 dev bond1 ip -6 address add 2001:db8:2::1/64 dev bond1.10 busywait "$TIMEOUT" wait_for_offload \ ip -6 route get fibmatch 2001:db8:1::2 dev bond1 check_err $? "subport rif was not created on lag device" busywait "$TIMEOUT" wait_for_offload \ ip -6 route get fibmatch 2001:db8:2::2 dev bond1.10 check_err $? "subport rif was not created on vlan device" ip link set dev $swp1 nomaster busywait "$TIMEOUT" wait_for_offload \ ip -6 route get fibmatch 2001:db8:1::2 dev bond1 check_err $? "subport rif of lag device was destroyed when should not" busywait "$TIMEOUT" wait_for_offload \ ip -6 route get fibmatch 2001:db8:2::2 dev bond1.10 check_err $? "subport rif of vlan device was destroyed when should not" ip link set dev $swp2 nomaster busywait "$TIMEOUT" not wait_for_offload \ ip -6 route get fibmatch 2001:db8:1::2 dev bond1 check_err $? "subport rif of lag device was not destroyed when should" busywait "$TIMEOUT" not wait_for_offload \ ip -6 route get fibmatch 2001:db8:2::2 dev bond1.10 check_err $? "subport rif of vlan device was not destroyed when should" log_test "subport rif refcount" ip link del dev bond1.10 ip link del dev bond1 } vlan_dev_deletion_test() { # Test that VLAN devices are correctly deleted / unlinked when enslaved # to bridge RET=0 ip link add name br10 type bridge ip link add name br20 type bridge ip link add name br30 type bridge ip link add link $swp1 name $swp1.10 type vlan id 10 ip link add link $swp1 name $swp1.20 type vlan id 20 ip link add link $swp1 name $swp1.30 type vlan id 30 ip link set dev $swp1.10 master br10 ip link set dev $swp1.20 master br20 ip link set dev $swp1.30 master br30 # If we did not handle the situation correctly, then these operations # might produce a trace ip link set dev $swp1.30 nomaster ip link del dev $swp1.20 # Deletion via ioctl uses different code paths from netlink vconfig rem $swp1.10 &> /dev/null log_test "vlan device deletion" ip link del dev $swp1.30 ip link del dev br30 ip link del dev br20 ip link del dev br10 } lag_create() { ip link add name bond1 type bond mode 802.3ad ip link set dev $swp1 down ip link set dev $swp2 down ip link set dev $swp1 master bond1 ip link set dev $swp2 master bond1 ip link add link bond1 name bond1.10 type vlan id 10 ip link add link bond1 name bond1.20 type vlan id 20 ip link add name br0 type bridge vlan_filtering 1 ip link set dev bond1 master br0 ip link add name br10 type bridge ip link set dev bond1.10 master br10 ip link add name br20 type bridge ip link set dev bond1.20 master br20 } lag_unlink_slaves_test() { # Test that ports are correctly unlinked from their LAG master, when # the LAG and its VLAN uppers are enslaved to bridges RET=0 lag_create ip link set dev $swp1 nomaster check_err $? "lag slave $swp1 was not unlinked from master" ip link set dev $swp2 nomaster check_err $? "lag slave $swp2 was not unlinked from master" # Try to configure corresponding VLANs as router interfaces ip -6 address add 2001:db8:1::1/64 dev $swp1 check_err $? "failed to configure ip address on $swp1" ip link add link $swp1 name $swp1.10 type vlan id 10 ip -6 address add 2001:db8:10::1/64 dev $swp1.10 check_err $? "failed to configure ip address on $swp1.10" ip link add link $swp1 name $swp1.20 type vlan id 20 ip -6 address add 2001:db8:20::1/64 dev $swp1.20 check_err $? "failed to configure ip address on $swp1.20" log_test "lag slaves unlinking" ip link del dev $swp1.20 ip link del dev $swp1.10 ip address flush dev $swp1 ip link del dev br20 ip link del dev br10 ip link del dev br0 ip link del dev bond1 } lag_dev_deletion_test() { # Test that LAG device is correctly deleted, when the LAG and its VLAN # uppers are enslaved to bridges RET=0 lag_create ip link del dev bond1 log_test "lag device deletion" ip link del dev br20 ip link del dev br10 ip link del dev br0 } vlan_interface_uppers_test() { # Test that uppers of a VLAN interface are correctly sanitized RET=0 ip link add name br0 type bridge vlan_filtering 1 ip link set dev $swp1 master br0 ip link add link br0 name br0.10 type vlan id 10 ip link add link br0.10 name macvlan0 \ type macvlan mode private &> /dev/null check_fail $? "managed to create a macvlan when should not" ip -6 address add 2001:db8:1::1/64 dev br0.10 ip link add link br0.10 name macvlan0 type macvlan mode private check_err $? "did not manage to create a macvlan when should" ip link del dev macvlan0 ip link add name vrf-test type vrf table 10 ip link set dev br0.10 master vrf-test check_err $? "did not manage to enslave vlan interface to vrf" ip link del dev vrf-test ip link add name br-test type bridge ip link set dev br0.10 master br-test &> /dev/null check_fail $? "managed to enslave vlan interface to bridge when should not" ip link del dev br-test log_test "vlan interface uppers" ip link del dev br0 } bridge_extern_learn_test() { # Test that externally learned entries added from user space are # marked as offloaded RET=0 ip link add name br0 type bridge ip link set dev $swp1 master br0 bridge fdb add de:ad:be:ef:13:37 dev $swp1 master extern_learn busywait "$TIMEOUT" wait_for_offload \ bridge fdb show brport $swp1 de:ad:be:ef:13:37 check_err $? "fdb entry not marked as offloaded when should" log_test "externally learned fdb entry" ip link del dev br0 } neigh_offload_test() { # Test that IPv4 and IPv6 neighbour entries are marked as offloaded RET=0 ip -4 address add 192.0.2.1/24 dev $swp1 ip -6 address add 2001:db8:1::1/64 dev $swp1 ip -4 neigh add 192.0.2.2 lladdr de:ad:be:ef:13:37 nud perm dev $swp1 ip -6 neigh add 2001:db8:1::2 lladdr de:ad:be:ef:13:37 nud perm \ dev $swp1 busywait "$TIMEOUT" wait_for_offload \ ip -4 neigh show dev $swp1 192.0.2.2 check_err $? "ipv4 neigh entry not marked as offloaded when should" busywait "$TIMEOUT" wait_for_offload \ ip -6 neigh show dev $swp1 2001:db8:1::2 check_err $? "ipv6 neigh entry not marked as offloaded when should" log_test "neighbour offload indication" ip -6 neigh del 2001:db8:1::2 dev $swp1 ip -4 neigh del 192.0.2.2 dev $swp1 ip -6 address del 2001:db8:1::1/64 dev $swp1 ip -4 address del 192.0.2.1/24 dev $swp1 } nexthop_offload_test() { # Test that IPv4 and IPv6 nexthops are marked as offloaded RET=0 sysctl_set net.ipv6.conf.$swp2.keep_addr_on_down 1 simple_if_init $swp1 192.0.2.1/24 2001:db8:1::1/64 simple_if_init $swp2 192.0.2.2/24 2001:db8:1::2/64 setup_wait ip -4 route add 198.51.100.0/24 vrf v$swp1 \ nexthop via 192.0.2.2 dev $swp1 ip -6 route add 2001:db8:2::/64 vrf v$swp1 \ nexthop via 2001:db8:1::2 dev $swp1 busywait "$TIMEOUT" wait_for_offload \ ip -4 route show 198.51.100.0/24 vrf v$swp1 check_err $? "ipv4 nexthop not marked as offloaded when should" busywait "$TIMEOUT" wait_for_offload \ ip -6 route show 2001:db8:2::/64 vrf v$swp1 check_err $? "ipv6 nexthop not marked as offloaded when should" ip link set dev $swp2 down sleep 1 busywait "$TIMEOUT" not wait_for_offload \ ip -4 route show 198.51.100.0/24 vrf v$swp1 check_err $? "ipv4 nexthop marked as offloaded when should not" busywait "$TIMEOUT" not wait_for_offload \ ip -6 route show 2001:db8:2::/64 vrf v$swp1 check_err $? "ipv6 nexthop marked as offloaded when should not" ip link set dev $swp2 up setup_wait busywait "$TIMEOUT" wait_for_offload \ ip -4 route show 198.51.100.0/24 vrf v$swp1 check_err $? "ipv4 nexthop not marked as offloaded after neigh add" busywait "$TIMEOUT" wait_for_offload \ ip -6 route show 2001:db8:2::/64 vrf v$swp1 check_err $? "ipv6 nexthop not marked as offloaded after neigh add" log_test "nexthop offload indication" ip -6 route del 2001:db8:2::/64 vrf v$swp1 ip -4 route del 198.51.100.0/24 vrf v$swp1 simple_if_fini $swp2 192.0.2.2/24 2001:db8:1::2/64 simple_if_fini $swp1 192.0.2.1/24 2001:db8:1::1/64 sysctl_restore net.ipv6.conf.$swp2.keep_addr_on_down } devlink_reload_test() { # Test that after executing all the above configuration tests, a # devlink reload can be performed without errors RET=0 devlink dev reload "$DEVLINK_DEV" check_err $? "devlink reload failed" log_test "devlink reload - last test" sleep 20 } trap cleanup EXIT setup_prepare setup_wait tests_run exit $EXIT_STATUS	{ "language": "Assembly" }
/* * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ / #include <asm-offsets.h> #include <config.h> #include <linux/linkage.h> #include <asm/arcregs.h> ENTRY(_start) ; ARCompact devices are not supposed to be SMP so master/slave check ; makes no sense. #ifdef CONFIG_ISA_ARCV2 ; Non-masters will be halted immediately, they might be kicked later ; by platform code right before passing control to the Linux kernel ; in bootm.c:boot_jump_linux(). lr r5, [identity] lsr r5, r5, 8 bmsk r5, r5, 7 cmp r5, 0 mov.nz r0, r5 bz .Lmaster_proceed flag 1 nop nop nop .Lmaster_proceed: #endif / Setup interrupt vector base that matches "__text_start" / sr __ivt_start, [ARC_AUX_INTR_VEC_BASE] ; Disable/enable I-cache according to configuration lr r5, [ARC_BCR_IC_BUILD] breq r5, 0, 1f ; I$ doesn't exist lr r5, [ARC_AUX_IC_CTRL] #ifndef CONFIG_SYS_ICACHE_OFF bclr r5, r5, 0 ; 0 - Enable, 1 is Disable #else bset r5, r5, 0 ; I$ exists, but is not used #endif sr r5, [ARC_AUX_IC_CTRL] 1: ; Disable/enable D-cache according to configuration lr r5, [ARC_BCR_DC_BUILD] breq r5, 0, 1f ; D$ doesn't exist lr r5, [ARC_AUX_DC_CTRL] bclr r5, r5, 6 ; Invalidate (discard w/o wback) #ifndef CONFIG_SYS_DCACHE_OFF bclr r5, r5, 0 ; Enable (+Inv) #else bset r5, r5, 0 ; Disable (+Inv) #endif sr r5, [ARC_AUX_DC_CTRL] 1: #ifdef CONFIG_ISA_ARCV2 ; Disable System-Level Cache (SLC) lr r5, [ARC_BCR_SLC] breq r5, 0, 1f ; SLC doesn't exist lr r5, [ARC_AUX_SLC_CTRL] bclr r5, r5, 6 ; Invalidate (discard w/o wback) bclr r5, r5, 0 ; Enable (+Inv) sr r5, [ARC_AUX_SLC_CTRL] 1: #endif / Establish C runtime stack and frame / mov %sp, CONFIG_SYS_INIT_SP_ADDR mov %fp, %sp / Allocate reserved area from current top of stack / mov %r0, %sp bl board_init_f_alloc_reserve / Set stack below reserved area, adjust frame pointer accordingly / mov %sp, %r0 mov %fp, %sp / Initialize reserved area - note: r0 already contains address / bl board_init_f_init_reserve / Zero the one and only argument of "board_init_f" / mov_s %r0, 0 j board_init_f ENDPROC(_start) / * void board_init_f_r_trampoline(stack-pointer address) * * This "function" does not return, instead it continues in RAM * after relocating the monitor code. * * r0 = new stack-pointer / ENTRY(board_init_f_r_trampoline) / Set up the stack- and frame-pointers / mov %sp, %r0 mov %fp, %sp / Update position of intterupt vector table / lr %r0, [ARC_AUX_INTR_VEC_BASE] ld %r1, [%r25, GD_RELOC_OFF] add %r0, %r0, %r1 sr %r0, [ARC_AUX_INTR_VEC_BASE] / Re-enter U-Boot by calling board_init_f_r */ j board_init_f_r ENDPROC(board_init_f_r_trampoline)	{ "language": "Assembly" }
; --------------------------------------------------------------------------- ; Object 11 - GHZ bridge ; --------------------------------------------------------------------------- Bridge: moveq #0,d0 move.b obRoutine(a0),d0 move.w Bri_Index(pc,d0.w),d1 jmp Bri_Index(pc,d1.w) ; =========================================================================== Bri_Index: dc.w Bri_Main-Bri_Index, Bri_Action-Bri_Index dc.w Bri_Platform-Bri_Index, Bri_Delete-Bri_Index dc.w Bri_Delete-Bri_Index, Bri_Display-Bri_Index ; =========================================================================== Bri_Main: ; Routine 0 addq.b #2,obRoutine(a0) move.l #Map_Bri,obMap(a0) move.w #$438E,obGfx(a0) move.b #4,obRender(a0) move.b #3,obPriority(a0) move.b #$80,obActWid(a0) move.w obY(a0),d2 move.w obX(a0),d3 move.b 0(a0),d4 ; copy object number ($11) to d4 lea obSubtype(a0),a2 moveq #0,d1 move.b (a2),d1 ; copy bridge length to d1 move.b #0,(a2)+ ; clear bridge length move.w d1,d0 lsr.w #1,d0 lsl.w #4,d0 sub.w d0,d3 ; d3 is position of leftmost log subq.b #2,d1 bcs.s Bri_Action ; don't make more if bridge has only 1 log @buildloop: bsr.w FindFreeObj bne.s Bri_Action addq.b #1,obSubtype(a0) cmp.w obX(a0),d3 ; is this log the leftmost one? bne.s @notleftmost ; if not, branch addi.w #$10,d3 move.w d2,obY(a0) move.w d2,$3C(a0) move.w a0,d5 subi.w #$D000,d5 lsr.w #6,d5 andi.w #$7F,d5 move.b d5,(a2)+ addq.b #1,obSubtype(a0) @notleftmost: move.w a1,d5 subi.w #$D000,d5 lsr.w #6,d5 andi.w #$7F,d5 move.b d5,(a2)+ move.b #$A,obRoutine(a1) move.b d4,0(a1) ; load bridge object (d4 = $11) move.w d2,obY(a1) move.w d2,$3C(a1) move.w d3,obX(a1) move.l #Map_Bri,obMap(a1) move.w #$438E,obGfx(a1) move.b #4,obRender(a1) move.b #3,obPriority(a1) move.b #8,obActWid(a1) addi.w #$10,d3 dbf d1,@buildloop ; repeat d1 times (length of bridge) Bri_Action: ; Routine 2 bsr.s Bri_Solid tst.b $3E(a0) beq.s @display subq.b #4,$3E(a0) bsr.w Bri_Bend @display: bsr.w DisplaySprite bra.w Bri_ChkDel ; \|\|\|\|\|\|\|\|\|\|\|\|\|\|\| S U B R O U T I N E \|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\| Bri_Solid: moveq #0,d1 move.b obSubtype(a0),d1 lsl.w #3,d1 move.w d1,d2 addq.w #8,d1 add.w d2,d2 lea (v_player).w,a1 tst.w obVelY(a1) bmi.w Plat_Exit move.w obX(a1),d0 sub.w obX(a0),d0 add.w d1,d0 bmi.w Plat_Exit cmp.w d2,d0 bcc.w Plat_Exit bra.s Plat_NoXCheck ; End of function Bri_Solid	{ "language": "Assembly" }
object_const_def const OLIVINETIMSHOUSE_TIM OlivineTimsHouse_MapScripts: def_scene_scripts def_callbacks Tim: faceplayer opentext trade NPC_TRADE_TIM waitbutton closetext end TimsHouseBookshelf: jumpstd MagazineBookshelfScript OlivineTimsHouse_MapEvents: db 0, 0 ; filler def_warp_events warp_event 2, 7, OLIVINE_CITY, 3 warp_event 3, 7, OLIVINE_CITY, 3 def_coord_events def_bg_events bg_event 0, 1, BGEVENT_READ, TimsHouseBookshelf bg_event 1, 1, BGEVENT_READ, TimsHouseBookshelf def_object_events object_event 2, 3, SPRITE_FISHING_GURU, SPRITEMOVEDATA_SPINRANDOM_SLOW, 0, 0, -1, -1, PAL_NPC_RED, OBJECTTYPE_SCRIPT, 0, Tim, -1	{ "language": "Assembly" }
// RUN: %sourcekitd-test -req=cursor -pos=1:8 %S/Inputs/multiple_ast1.swift -- %S/Inputs/multiple_ast1.swift == \ // RUN: -req=cursor -pos=1:8 %S/Inputs/multiple_ast2.swift -- %S/Inputs/multiple_ast2.swift \| %FileCheck -check-prefix=CHECK %s // CHECK: source.lang.swift.decl.function.free (1:6-1:20) // CHECK-NEXT: foo1 // CHECK: source.lang.swift.decl.function.free (1:6-1:20) // CHECK-NEXT: foo2	{ "language": "Assembly" }
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler Copyright (C) 2012-2019 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version. GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. Under Section 7 of GPL version 3, you are granted additional permissions described in the GCC Runtime Library Exception, version 3.1, as published by the Free Software Foundation. You should have received a copy of the GNU General Public License and a copy of the GCC Runtime Library Exception along with this program; see the files COPYING3 and COPYING.RUNTIME respectively. If not, see <http://www.gnu.org/licenses/>. */ .macro RESTORE_FPU_REGS_01 fldi.bi $fd0, [$sp], #8 fldi.bi $fd1, [$sp], #8 fldi.bi $fd2, [$sp], #8 fldi.bi $fd3, [$sp], #8 fldi.bi $fd4, [$sp], #8 fldi.bi $fd5, [$sp], #8 fldi.bi $fd6, [$sp], #8 fldi.bi $fd7, [$sp], #8 .endm	{ "language": "Assembly" }
/* LiCK Library for ChucK. Copyright (c) 2007-2020 held jointly by the individual authors. This file is part of LiCK. LiCK is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. LiCK is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with LiCK. If not, see <http://www.gnu.org/licenses/>. */ adc => Foldback f => dac; 0.9 => f.mix; <<<"ready">>>; 1::minute => now;	{ "language": "Assembly" }
Route16FlyHouse_h: db HOUSE ; tileset db ROUTE_16_FLY_HOUSE_HEIGHT, ROUTE_16_FLY_HOUSE_WIDTH ; dimensions (y, x) dw Route16FlyHouse_Blocks ; blocks dw Route16FlyHouse_TextPointers ; texts dw Route16FlyHouse_Script ; scripts db 0 ; connections dw Route16FlyHouse_Object ; objects	{ "language": "Assembly" }
#source: start.s #source: getaa.s #source: a.s #as: -no-expand #ld: -m elf64mmix #objdump: -dr .*: file format elf64-mmix Disassembly of section \.text: 0+ <_start>: 0+: e3fd0001 setl \$253,0x1 0+4 <getaa>: 4: e3fd0002 setl \$253,0x2 8: f47b0002 geta \$123,10 <a> c: e3fd0003 setl \$253,0x3 0+10 <a>: 10: e3fd0004 setl \$253,0x4	{ "language": "Assembly" }
; RUN: %lli %s > /dev/null define i32 @main() { %int1 = add i32 0, 0 ; <i32> [#uses=6] %int2 = add i32 0, 0 ; <i32> [#uses=6] %long1 = add i64 0, 0 ; <i64> [#uses=6] %long2 = add i64 0, 0 ; <i64> [#uses=6] %sbyte1 = add i8 0, 0 ; <i8> [#uses=6] %sbyte2 = add i8 0, 0 ; <i8> [#uses=6] %short1 = add i16 0, 0 ; <i16> [#uses=6] %short2 = add i16 0, 0 ; <i16> [#uses=6] %ubyte1 = add i8 0, 0 ; <i8> [#uses=6] %ubyte2 = add i8 0, 0 ; <i8> [#uses=6] %uint1 = add i32 0, 0 ; <i32> [#uses=6] %uint2 = add i32 0, 0 ; <i32> [#uses=6] %ulong1 = add i64 0, 0 ; <i64> [#uses=6] %ulong2 = add i64 0, 0 ; <i64> [#uses=6] %ushort1 = add i16 0, 0 ; <i16> [#uses=6] %ushort2 = add i16 0, 0 ; <i16> [#uses=6] %test1 = icmp eq i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] %test2 = icmp uge i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] %test3 = icmp ugt i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] %test4 = icmp ule i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] %test5 = icmp ult i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] %test6 = icmp ne i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] %test7 = icmp eq i16 %ushort1, %ushort2 ; <i1> [#uses=0] %test8 = icmp uge i16 %ushort1, %ushort2 ; <i1> [#uses=0] %test9 = icmp ugt i16 %ushort1, %ushort2 ; <i1> [#uses=0] %test10 = icmp ule i16 %ushort1, %ushort2 ; <i1> [#uses=0] %test11 = icmp ult i16 %ushort1, %ushort2 ; <i1> [#uses=0] %test12 = icmp ne i16 %ushort1, %ushort2 ; <i1> [#uses=0] %test13 = icmp eq i32 %uint1, %uint2 ; <i1> [#uses=0] %test14 = icmp uge i32 %uint1, %uint2 ; <i1> [#uses=0] %test15 = icmp ugt i32 %uint1, %uint2 ; <i1> [#uses=0] %test16 = icmp ule i32 %uint1, %uint2 ; <i1> [#uses=0] %test17 = icmp ult i32 %uint1, %uint2 ; <i1> [#uses=0] %test18 = icmp ne i32 %uint1, %uint2 ; <i1> [#uses=0] %test19 = icmp eq i64 %ulong1, %ulong2 ; <i1> [#uses=0] %test20 = icmp uge i64 %ulong1, %ulong2 ; <i1> [#uses=0] %test21 = icmp ugt i64 %ulong1, %ulong2 ; <i1> [#uses=0] %test22 = icmp ule i64 %ulong1, %ulong2 ; <i1> [#uses=0] %test23 = icmp ult i64 %ulong1, %ulong2 ; <i1> [#uses=0] %test24 = icmp ne i64 %ulong1, %ulong2 ; <i1> [#uses=0] %test25 = icmp eq i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] %test26 = icmp sge i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] %test27 = icmp sgt i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] %test28 = icmp sle i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] %test29 = icmp slt i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] %test30 = icmp ne i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] %test31 = icmp eq i16 %short1, %short2 ; <i1> [#uses=0] %test32 = icmp sge i16 %short1, %short2 ; <i1> [#uses=0] %test33 = icmp sgt i16 %short1, %short2 ; <i1> [#uses=0] %test34 = icmp sle i16 %short1, %short2 ; <i1> [#uses=0] %test35 = icmp slt i16 %short1, %short2 ; <i1> [#uses=0] %test36 = icmp ne i16 %short1, %short2 ; <i1> [#uses=0] %test37 = icmp eq i32 %int1, %int2 ; <i1> [#uses=0] %test38 = icmp sge i32 %int1, %int2 ; <i1> [#uses=0] %test39 = icmp sgt i32 %int1, %int2 ; <i1> [#uses=0] %test40 = icmp sle i32 %int1, %int2 ; <i1> [#uses=0] %test41 = icmp slt i32 %int1, %int2 ; <i1> [#uses=0] %test42 = icmp ne i32 %int1, %int2 ; <i1> [#uses=0] %test43 = icmp eq i64 %long1, %long2 ; <i1> [#uses=0] %test44 = icmp sge i64 %long1, %long2 ; <i1> [#uses=0] %test45 = icmp sgt i64 %long1, %long2 ; <i1> [#uses=0] %test46 = icmp sle i64 %long1, %long2 ; <i1> [#uses=0] %test47 = icmp slt i64 %long1, %long2 ; <i1> [#uses=0] %test48 = icmp ne i64 %long1, %long2 ; <i1> [#uses=0] ret i32 0 }	{ "language": "Assembly" }
/* * Copyright 2013 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Ben Skeggs / #ifdef INCLUDE_PROC process(PROC_HOST, #host_init, #host_recv) #endif /***************************************************************************** * HOST data segment ***************************************************************************/ #ifdef INCLUDE_DATA // HOST (R)FIFO packet format .equ #fifo_process 0x00 .equ #fifo_message 0x04 .equ #fifo_data0 0x08 .equ #fifo_data1 0x0c // HOST HOST->PWR queue description .equ #fifo_qlen 4 // log2(size of queue entry in bytes) .equ #fifo_qnum 3 // log2(max number of entries in queue) .equ #fifo_qmaskb (1 << #fifo_qnum) // max number of entries in queue .equ #fifo_qmaskp (#fifo_qmaskb - 1) .equ #fifo_qmaskf ((#fifo_qmaskb << 1) - 1) .equ #fifo_qsize (1 << (#fifo_qlen + #fifo_qnum)) fifo_queue: .skip 128 // #fifo_qsize // HOST PWR->HOST queue description .equ #rfifo_qlen 4 // log2(size of queue entry in bytes) .equ #rfifo_qnum 3 // log2(max number of entries in queue) .equ #rfifo_qmaskb (1 << #rfifo_qnum) // max number of entries in queue .equ #rfifo_qmaskp (#rfifo_qmaskb - 1) .equ #rfifo_qmaskf ((#rfifo_qmaskb << 1) - 1) .equ #rfifo_qsize (1 << (#rfifo_qlen + #rfifo_qnum)) rfifo_queue: .skip 128 // #rfifo_qsize #endif /**************************************************************************** * HOST code segment *****************************************************************************/ #ifdef INCLUDE_CODE // HOST->PWR comms - dequeue message(s) for process(es) from FIFO // // $r15 - current (host) // $r0 - zero host_send: nv_iord($r1, NV_PPWR_FIFO_GET(0)) nv_iord($r2, NV_PPWR_FIFO_PUT(0)) cmp b32 $r1 $r2 bra e #host_send_done // calculate address of message and $r14 $r1 #fifo_qmaskp shl b32 $r14 $r14 #fifo_qlen add b32 $r14 #fifo_queue // read message data, and pass to appropriate process ld b32 $r11 D[$r14 + #fifo_data1] ld b32 $r12 D[$r14 + #fifo_data0] ld b32 $r13 D[$r14 + #fifo_message] ld b32 $r14 D[$r14 + #fifo_process] call(send) // increment GET add b32 $r1 0x1 and $r14 $r1 #fifo_qmaskf nv_iowr(NV_PPWR_FIFO_GET(0), $r14) bra #host_send host_send_done: ret // PWR->HOST comms - enqueue message for HOST to RFIFO // // $r15 - current (host) // $r14 - process // $r13 - message // $r12 - message data 0 // $r11 - message data 1 // $r0 - zero host_recv: // message from intr handler == HOST->PWR comms pending imm32($r1, PROC_KERN) cmp b32 $r14 $r1 bra e #host_send // wait for space in RFIFO host_recv_wait: nv_iord($r1, NV_PPWR_RFIFO_GET) nv_iord($r2, NV_PPWR_RFIFO_PUT) xor $r1 #rfifo_qmaskb cmp b32 $r1 $r2 bra e #host_recv_wait and $r3 $r2 #rfifo_qmaskp shl b32 $r3 #rfifo_qlen add b32 $r3 #rfifo_queue // enqueue message st b32 D[$r3 + #fifo_data1] $r11 st b32 D[$r3 + #fifo_data0] $r12 st b32 D[$r3 + #fifo_message] $r13 st b32 D[$r3 + #fifo_process] $r14 add b32 $r2 0x1 and $r2 #rfifo_qmaskf nv_iowr(NV_PPWR_RFIFO_PUT, $r2) // notify host of pending message mov $r2 NV_PPWR_INTR_TRIGGER_USER0 nv_iowr(NV_PPWR_INTR_TRIGGER, $r2) ret // $r15 - current (host) // $r0 - zero host_init: // store each fifo's base/size in H2D/D2H scratch regs mov $r1 #fifo_qsize shl b32 $r1 16 or $r1 #fifo_queue nv_iowr(NV_PPWR_H2D, $r1); mov $r1 #rfifo_qsize shl b32 $r1 16 or $r1 #rfifo_queue nv_iowr(NV_PPWR_D2H, $r1); // enable fifo subintr for first fifo mov $r1 1 nv_iowr(NV_PPWR_FIFO_INTR_EN, $r1) ret #endif	{ "language": "Assembly" }
; binary emission of 32-bit code. test binemit set opt_level=best set allones_funcaddrs target i686 haswell ; The binary encodings can be verified with the command: ; ; sed -ne 's/^ ; asm: //p' filetests/isa/x86/allones_funcaddrs32.clif \| llvm-mc -show-encoding -triple=i386 ; ; Tests from binary32.clif affected by allones_funcaddrs. function %I32() { sig0 = () fn0 = %foo() ebb0: ; asm: movl $-1, %ecx [-,%rcx] v400 = func_addr.i32 fn0 ; bin: b9 Abs4(%foo) ffffffff ; asm: movl $-1, %esi [-,%rsi] v401 = func_addr.i32 fn0 ; bin: be Abs4(%foo) ffffffff return ; bin: c3 }	{ "language": "Assembly" }
config BR2_PACKAGE_GCONF bool "gconf" depends on BR2_TOOLCHAIN_HAS_THREADS # dbus, libglib2 depends on BR2_USE_MMU # dbus, libglib2 depends on BR2_USE_WCHAR # libglib2 depends on !BR2_STATIC_LIBS select BR2_PACKAGE_DBUS select BR2_PACKAGE_DBUS_GLIB select BR2_PACKAGE_LIBGLIB2 select BR2_PACKAGE_LIBXML2 help GConf was a system used by the GNOME desktop environment for storing configuration settings for the desktop and applications. It is similar to the Windows Registry. https://projects.gnome.org/gconf/ comment "gconf needs a toolchain w/ threads, wchar, dynamic library" depends on BR2_USE_MMU depends on !BR2_TOOLCHAIN_HAS_THREADS \|\| !BR2_USE_WCHAR \ \|\| BR2_STATIC_LIBS	{ "language": "Assembly" }
/* Copyright (C) 1991-2020 Free Software Foundation, Inc. This file is part of the GNU C Library. The GNU C Library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version. The GNU C Library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with the GNU C Library; if not, see <https://www.gnu.org/licenses/>. / #include <sys/stat.h> #include <errno.h> #include <sys/types.h> / Set the file creation mask to MASK, returning the old mask. */ mode_t __umask (mode_t mask) { __set_errno (ENOSYS); return -1; } stub_warning (umask) weak_alias (__umask, umask)	{ "language": "Assembly" }
/* * Copyright (C) 2008, Guennadi Liakhovetski <[email protected]> * * SPDX-License-Identifier: GPL-2.0+ / #include <asm/arch/imx-regs.h> .macro REG reg, val ldr r2, =\reg ldr r3, =\val str r3, [r2] .endm .macro REG8 reg, val ldr r2, =\reg ldr r3, =\val strb r3, [r2] .endm .macro DELAY loops ldr r2, =\loops 1: subs r2, r2, #1 nop bcs 1b .endm / RedBoot: AIPS setup - Only setup MPROTx registers. * The PACR default values are good./ .macro init_aips / * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. / ldr r0, =0x43F00000 ldr r1, =0x77777777 str r1, [r0, #0x00] str r1, [r0, #0x04] ldr r0, =0x53F00000 str r1, [r0, #0x00] str r1, [r0, #0x04] / * Clear the on and off peripheral modules Supervisor Protect bit * for SDMA to access them. Did not change the AIPS control registers * (offset 0x20) access type / ldr r0, =0x43F00000 ldr r1, =0x0 str r1, [r0, #0x40] str r1, [r0, #0x44] str r1, [r0, #0x48] str r1, [r0, #0x4C] ldr r1, [r0, #0x50] and r1, r1, #0x00FFFFFF str r1, [r0, #0x50] ldr r0, =0x53F00000 ldr r1, =0x0 str r1, [r0, #0x40] str r1, [r0, #0x44] str r1, [r0, #0x48] str r1, [r0, #0x4C] ldr r1, [r0, #0x50] and r1, r1, #0x00FFFFFF str r1, [r0, #0x50] .endm / init_aips / / RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup / .macro init_max ldr r0, =0x43F04000 / MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 / ldr r1, =0x00302154 str r1, [r0, #0x000] / for S0 / str r1, [r0, #0x100] / for S1 / str r1, [r0, #0x200] / for S2 / str r1, [r0, #0x300] / for S3 / str r1, [r0, #0x400] / for S4 / / SGPCR - always park on last master / ldr r1, =0x10 str r1, [r0, #0x010] / for S0 / str r1, [r0, #0x110] / for S1 / str r1, [r0, #0x210] / for S2 / str r1, [r0, #0x310] / for S3 / str r1, [r0, #0x410] / for S4 / / MGPCR - restore default values / ldr r1, =0x0 str r1, [r0, #0x800] / for M0 / str r1, [r0, #0x900] / for M1 / str r1, [r0, #0xA00] / for M2 / str r1, [r0, #0xB00] / for M3 / str r1, [r0, #0xC00] / for M4 / str r1, [r0, #0xD00] / for M5 / .endm / init_max / / RedBoot: M3IF setup / .macro init_m3if / Configure M3IF registers / ldr r1, =0xB8003000 / * M3IF Control Register (M3IFCTL) * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 * ------------ * 0x00000040 / ldr r0, =0x00000040 str r0, [r1] / M3IF control reg / .endm / init_m3if / / RedBoot: To support 133MHz DDR / .macro init_drive_strength / * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits * in SW_PAD_CTL registers / / SDCLK / ldr r1, =0x43FAC200 ldr r0, [r1, #0x6C] bic r0, r0, #(1 << 12) str r0, [r1, #0x6C] / CAS / ldr r0, [r1, #0x70] bic r0, r0, #(1 << 22) str r0, [r1, #0x70] / RAS / ldr r0, [r1, #0x74] bic r0, r0, #(1 << 2) str r0, [r1, #0x74] / CS2 (CSD0) / ldr r0, [r1, #0x7C] bic r0, r0, #(1 << 22) str r0, [r1, #0x7C] / DQM3 / ldr r0, [r1, #0x84] bic r0, r0, #(1 << 22) str r0, [r1, #0x84] / DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) / ldr r2, =22 / (0x2E0 - 0x288) / 4 = 22 / pad_loop: ldr r0, [r1, #0x88] bic r0, r0, #(1 << 22) bic r0, r0, #(1 << 12) bic r0, r0, #(1 << 2) str r0, [r1, #0x88] add r1, r1, #4 subs r2, r2, #0x1 bne pad_loop .endm / init_drive_strength / / CPLD on CS4 setup / .macro init_cs4 ldr r0, =WEIM_BASE ldr r1, =0x0000D843 str r1, [r0, #0x40] ldr r1, =0x22252521 str r1, [r0, #0x44] ldr r1, =0x22220A00 str r1, [r0, #0x48] .endm / init_cs4 / .globl lowlevel_init lowlevel_init: / Redboot initializes very early AIPS, what for? * Then it also initializes Multi-Layer AHB Crossbar Switch, * M3IF / / Also setup the Peripheral Port Remap register inside the core / ldr r0, =0x40000015 / start from AIPS 2GB region / mcr p15, 0, r0, c15, c2, 4 init_aips init_max init_m3if init_drive_strength init_cs4 / Image Processing Unit: / / Too early to switch display on? / REG IPU_CONF, IPU_CONF_DI_EN / Switch on Display Interface / / Clock Control Module: / REG CCM_CCMR, 0x074B0BF5 / Use CKIH, MCU PLL off / DELAY 0x40000 REG CCM_CCMR, 0x074B0BF5 \| CCMR_MPE / MCU PLL on / REG CCM_CCMR, (0x074B0BF5 \| CCMR_MPE) & ~CCMR_MDS / Switch to MCU PLL / / PBC CPLD on CS4 / mov r1, #CS4_BASE ldrh r1, [r1, #0x2] / Is 27MHz switch set? / ands r1, r1, #0x10 / 532-133-66.5 / ldr r0, =CCM_BASE ldr r1, =0xFF871D58 / PDR0 / str r1, [r0, #0x4] ldreq r1, MPCTL_PARAM_532 ldrne r1, MPCTL_PARAM_532_27 / MPCTL / str r1, [r0, #0x10] / Set UPLL=240MHz, USB=60MHz / ldr r1, =0x49FCFE7F / PDR1 / str r1, [r0, #0x8] ldreq r1, UPCTL_PARAM_240 ldrne r1, UPCTL_PARAM_240_27 / UPCTL / str r1, [r0, #0x14] / default CLKO to 1/8 of the ARM core / mov r1, #0x000002C0 add r1, r1, #0x00000006 / COSR / str r1, [r0, #0x1c] / RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 / / REG CCM_PDR0, PDR0_CSI_PODF(0x3f) \| PDR0_CSI_PRDF(7) \| PDR0_PER_PODF(7) \| PDR0_HSP_PODF(2) \| PDR0_NFC_PODF(6) \| PDR0_IPG_PODF(1) \| PDR0_MAX_PODF(2) \| PDR0_MCU_PODF(0)/ / Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 / / REG CCM_MPCTL, PLL_PD(0) \| PLL_MFD(0x33) \| PLL_MFI(7) \| PLL_MFN(0x23)/ / Default: 1, 4, 12, 1 / REG CCM_SPCTL, PLL_PD(1) \| PLL_MFD(4) \| PLL_MFI(12) \| PLL_MFN(1) / B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */ REG 0xB8001010, 0x00000004 REG 0xB8001004, 0x006ac73a REG 0xB8001000, 0x92100000 REG 0x80000f00, 0x12344321 REG 0xB8001000, 0xa2100000 REG 0x80000000, 0x12344321 REG 0x80000000, 0x12344321 REG 0xB8001000, 0xb2100000 REG8 0x80000033, 0xda REG8 0x81000000, 0xff REG 0xB8001000, 0x82226080 REG 0x80000000, 0xDEADBEEF REG 0xB8001010, 0x0000000c mov pc, lr MPCTL_PARAM_532: .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0)) MPCTL_PARAM_532_27: .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0)) UPCTL_PARAM_240: .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0)) UPCTL_PARAM_240_27: .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))	{ "language": "Assembly" }
0 SECTION 2 TABLES 0 LAYER 2 Background 62 1 0 ENDTAB 0 ENDSEC 0 SECTION 2 ENTITIES 0 ELLIPSE 8 Background 6 CONTINUOUS 10 8.325000 20 -3.550000 11 3.375000 40 0.370370 39 0 41 0.000000 42 6.280000 0 ELLIPSE 8 Background 6 CONTINUOUS 10 8.325000 20 -3.550000 11 3.375000 40 0.370370 39 0 41 0.000000 42 6.280000 0 ELLIPSE 8 Background 6 DASHDOT 10 5.150000 20 -6.100000 11 2.000000 40 1.700000 39 1 41 0.000000 42 6.280000 0 CIRCLE 8 Background 6 DASHDOT 10 8.475000 20 -6.625000 40 3.075000 39 1 0 CIRCLE 8 Background 6 DASH 10 8.475000 20 -6.625000 40 3.075000 39 0 0 ENDSEC 0 EOF	{ "language": "Assembly" }
Freescale esdhc-specific options - CONFIG_FSL_ESDHC_ADAPTER_IDENT Support Freescale adapter card type identification. This is implemented by operating Qixis FPGA relevant registers. The STAT_PRES1 register has SDHC Card ID[0:2] bits showing the type of card installed in the SDHC Adapter Slot. SDHC Card ID[0:2] Adapter Card Type 0b000 reserved 0b001 eMMC Card Rev4.5 0b010 SD/MMC Legacy Card 0b011 eMMC Card Rev4.4 0b100 reserved 0b101 MMC Card 0b110 SD Card Rev2.0/3.0 0b111 No card is present - CONFIG_SYS_FSL_ESDHC_LE ESDHC IP is in little-endian mode. Accessing ESDHC registers can be determined by ESDHC IP's endian mode or processor's endian mode. - CONFIG_SYS_FSL_ESDHC_BE ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined by ESDHC IP's endian mode or processor's endian mode.	{ "language": "Assembly" }
// RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32im -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32ima -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32imaf -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32imafd -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32ic -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32imc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32imac -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32imafc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32imafdc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32ia -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32iaf -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32iafd -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32iac -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32iafc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32iafdc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32g -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32gc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64im -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64ima -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64imaf -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64imafd -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64ic -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64imc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64imac -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64imafc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64imafdc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64ia -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64iaf -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64iafd -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64iac -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64iafc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64iafdc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64g -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64gc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck %s // CHECK-NOT: error: invalid arch name ' // RUN: %clang -target riscv32-unknown-elf -march=rv32 -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32 %s // RV32: error: invalid arch name 'rv32' // RUN: %clang -target riscv32-unknown-elf -march=rv32m -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32M %s // RV32M: error: invalid arch name 'rv32m' // RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32ID %s // RV32ID: error: invalid arch name 'rv32id' // RUN: %clang -target riscv32-unknown-elf -march=rv32l -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32L %s // RV32L: error: invalid arch name 'rv32l' // RUN: %clang -target riscv32-unknown-elf -march=rv32imadf -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32IMADF %s // RV32IMADF: error: invalid arch name 'rv32imadf' // RUN: %clang -target riscv32-unknown-elf -march=rv32imm -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32IMM %s // RV32IMM: error: invalid arch name 'rv32imm' // RUN: %clang -target riscv32-unknown-elf -march=RV32I -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32I-UPPER %s // RV32I-UPPER: error: invalid arch name 'RV32I' // RUN: %clang -target riscv64-unknown-elf -march=rv64 -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV64 %s // RV64: error: invalid arch name 'rv64' // RUN: %clang -target riscv64-unknown-elf -march=rv64m -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV64M %s // RV64M: error: invalid arch name 'rv64m' // RUN: %clang -target riscv64-unknown-elf -march=rv64id -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV64ID %s // RV64ID: error: invalid arch name 'rv64id' // RUN: %clang -target riscv64-unknown-elf -march=rv64l -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV64L %s // RV64L: error: invalid arch name 'rv64l' // RUN: %clang -target riscv64-unknown-elf -march=rv64imadf -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV64IMADF %s // RV64IMADF: error: invalid arch name 'rv64imadf' // RUN: %clang -target riscv64-unknown-elf -march=rv64imm -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV64IMM %s // RV64IMM: error: invalid arch name 'rv64imm' // RUN: %clang -target riscv64-unknown-elf -march=RV64I -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV64I-UPPER %s // RV64I-UPPER: error: invalid arch name 'RV64I' // Testing specific messages and unsupported extensions. // RUN: %clang -target riscv32-unknown-elf -march=rv32e -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32E %s // RV32E: error: invalid arch name 'rv32e', // RV32E: standard user-level extension 'e' // RUN: %clang -target riscv64-unknown-elf -march=rv64e -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV64E %s // RV64E: error: invalid arch name 'rv64e', // RV64E: standard user-level extension 'e' requires 'rv32' // RUN: %clang -target riscv32-unknown-elf -march=rv32imC -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-LOWER %s // RV32-LOWER: error: invalid arch name 'rv32imC', // RV32-LOWER: string must be lowercase // RUN: %clang -target riscv32-unknown-elf -march=rv32 -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-STR %s // RV32-STR: error: invalid arch name 'rv32', // RV32-STR: string must begin with rv32{i,e,g} or rv64{i,g} // RUN: %clang -target riscv32-unknown-elf -march=rv32q -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-LETTER %s // RV32-LETTER: error: invalid arch name 'rv32q', // RV32-LETTER: first letter should be 'e', 'i' or 'g' // RUN: %clang -target riscv32-unknown-elf -march=rv32imcq -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-ORDER %s // RV32-ORDER: error: invalid arch name 'rv32imcq', // RV32-ORDER: standard user-level extension not given in canonical order 'q' // RUN: %clang -target riscv32-unknown-elf -march=rv32imw -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-STD-INVAL %s // RV32-STD-INVAL: error: invalid arch name 'rv32imw', // RV32-STD-INVAL: invalid standard user-level extension 'w' // RUN: %clang -target riscv32-unknown-elf -march=rv32imqc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-STD %s // RV32-STD: error: invalid arch name 'rv32imqc', // RV32-STD: unsupported standard user-level extension 'q' // RUN: %clang -target riscv32-unknown-elf -march=rv32xabc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32X %s // RV32X: error: invalid arch name 'rv32xabc', // RV32X: first letter should be 'e', 'i' or 'g' // RUN: %clang -target riscv32-unknown-elf -march=rv32sxabc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32SX %s // RV32SX: error: invalid arch name 'rv32sxabc', // RV32SX: first letter should be 'e', 'i' or 'g' // RUN: %clang -target riscv32-unknown-elf -march=rv32sabc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32S %s // RV32S: error: invalid arch name 'rv32sabc', // RV32S: first letter should be 'e', 'i' or 'g' // RUN: %clang -target riscv32-unknown-elf -march=rv32ix -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32X-NAME %s // RV32X-NAME: error: invalid arch name 'rv32ix', // RV32X-NAME: non-standard user-level extension name missing after 'x' // RUN: %clang -target riscv32-unknown-elf -march=rv32isx -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32SX-NAME %s // RV32SX-NAME: error: invalid arch name 'rv32isx', // RV32SX-NAME: non-standard supervisor-level extension // RV32SX-NAME: name missing after 'sx' // RUN: %clang -target riscv32-unknown-elf -march=rv32is -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32S-NAME %s // RV32S-NAME: error: invalid arch name 'rv32is', // RV32S-NAME: standard supervisor-level extension // RV32S-NAME: name missing after 's' // RUN: %clang -target riscv32-unknown-elf -march=rv32ix_s_sx -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32ALL-NAME %s // RV32ALL-NAME: error: invalid arch name 'rv32ix_s_sx', // RV32ALL-NAME: non-standard user-level extension // RV32ALL-NAME: name missing after 'x' // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32X-UNS %s // RV32X-UNS: error: invalid arch name 'rv32ixabc', // RV32X-UNS: unsupported non-standard user-level extension 'xabc' // RUN: %clang -target riscv32-unknown-elf -march=rv32isa -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32S-UNS %s // RV32S-UNS: error: invalid arch name 'rv32isa', // RV32S-UNS: unsupported standard supervisor-level extension 'sa' // RUN: %clang -target riscv32-unknown-elf -march=rv32isxabc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32SX-UNS %s // RV32SX-UNS: error: invalid arch name 'rv32isxabc', // RV32SX-UNS: unsupported non-standard supervisor-level extension 'sxabc' // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc_sp_sxlw -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32ALL %s // RV32ALL: error: invalid arch name 'rv32ixabc_sp_sxlw', // RV32ALL: unsupported non-standard user-level extension 'xabc' // RUN: %clang -target riscv32-unknown-elf -march=rv32i20 -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-IVER %s // RV32-IVER: error: invalid arch name 'rv32i20', unsupported // RV32-IVER: version number 20 for extension 'i' // RUN: %clang -target riscv32-unknown-elf -march=rv32imc5 -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-CVER %s // RV32-CVER: error: invalid arch name 'rv32imc5', unsupported // RV32-CVER: version number 5 for extension 'c' // RUN: %clang -target riscv32-unknown-elf -march=rv32i2p -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-IMINOR-MISS %s // RV32-IMINOR-MISS: error: invalid arch name 'rv32i2p', // RV32-IMINOR-MISS: minor version number missing after 'p' for extension 'i' // RUN: %clang -target riscv32-unknown-elf -march=rv32i2p0 -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-IMINOR0 %s // RV32-IMINOR0: error: invalid arch name 'rv32i2p0', // RV32-IMINOR0: unsupported version number 2.0 for extension 'i' // RUN: %clang -target riscv32-unknown-elf -march=rv32i2p1 -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-IMINOR1 %s // RV32-IMINOR1: error: invalid arch name 'rv32i2p1', unsupported // RV32-IMINOR1: version number 2.1 for extension 'i' // RUN: %clang -target riscv32-unknown-elf -march=rv32ix2p -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-XMINOR-MISS %s // RV32-XMINOR-MISS: error: invalid arch name 'rv32ix2p', // RV32-XMINOR-MISS: minor version number missing after 'p' for extension 'x2p' // RUN: %clang -target riscv32-unknown-elf -march=rv32is2p0 -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-SMINOR0 %s // RV32-SMINOR0: error: invalid arch name 'rv32is2p0', // RV32-SMINOR0: unsupported version number 2.0 for extension 's2p0' // RUN: %clang -target riscv32-unknown-elf -march=rv32isx2p1 -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-SXMINOR1 %s // RV32-SXMINOR1: error: invalid arch name 'rv32isx2p1', unsupported // RV32-SXMINOR1: version number 2.1 for extension 'sx2p1' // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc_ -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-XSEP %s // RV32-XSEP: error: invalid arch name 'rv32ixabc_', // RV32-XSEP: extension name missing after separator '_' // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc_a -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-PREFIX %s // RV32-PREFIX: error: invalid arch name 'rv32ixabc_a', // RV32-PREFIX: invalid extension prefix 'a' // RUN: %clang -target riscv32-unknown-elf -march=rv32isabc_xdef -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-X-ORDER %s // RV32-X-ORDER: error: invalid arch name 'rv32isabc_xdef', // RV32-X-ORDER: non-standard user-level extension not given // RV32-X-ORDER: in canonical order 'xdef' // RUN: %clang -target riscv32-unknown-elf -march=rv32isxabc_sdef -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-S-ORDER %s // RV32-S-ORDER: error: invalid arch name 'rv32isxabc_sdef', // RV32-S-ORDER: standard supervisor-level extension not given // RV32-S-ORDER: in canonical order 'sdef' // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc_xabc -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-XDUP %s // RV32-XDUP: error: invalid arch name 'rv32ixabc_xabc', // RV32-XDUP: duplicated non-standard user-level extension 'xabc' // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc_xdef -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-X-X-INVAL %s // RV32-X-X-INVAL: error: invalid arch name 'rv32ixabc_xdef', unsupported // RV32-X-X-INVAL: non-standard user-level extension 'xabc' // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc_sdef_sxghi -### %s \ // RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-X-S-SX-INVAL %s // RV32-X-S-SX-INVAL: error: invalid arch name 'rv32ixabc_sdef_sxghi', // RV32-X-S-SX-INVAL: unsupported non-standard user-level extension 'xabc'	{ "language": "Assembly" }
// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - \| FileCheck %s --check-prefix LAMBDA --check-prefix LAMBDA-64 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - \| FileCheck %s --check-prefix LAMBDA --check-prefix LAMBDA-64 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - \| FileCheck %s --check-prefix LAMBDA --check-prefix LAMBDA-32 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - \| FileCheck %s --check-prefix LAMBDA --check-prefix LAMBDA-32 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - \| FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - \| FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - \| FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - \| FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc\|__tgt}} // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - \| FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - \| FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - \| FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - \| FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - \| FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - \| FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - \| FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - \| FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc\|__tgt}} // expected-no-diagnostics #ifndef HEADER #define HEADER template <class T> struct S { T f; S(T a) : f(a) {} S() : f() {} operator T() { return T(); } ~S() {} }; // CHECK: [[S_FLOAT_TY:%.+]] = type { float } // CHECK: [[S_INT_TY:%.+]] = type { i{{[0-9]+}} } template <typename T> T tmain() { S<T> test; T t_var = T(); T vec[] = {1, 2}; S<T> s_arr[] = {1, 2}; S<T> &var = test; #pragma omp target #pragma omp teams #pragma omp distribute private(t_var, vec, s_arr, s_arr, var, var) for (int i = 0; i < 2; ++i) { vec[i] = t_var; s_arr[i] = var; } return T(); } int main() { static int svar; volatile double g; volatile double &g1 = g; #ifdef LAMBDA // LAMBDA-LABEL: @main // LAMBDA: call{{.}} void [[OUTER_LAMBDA:@.+]]( [&]() { static float sfvar; // LAMBDA: define{{.}} internal{{.}} void [[OUTER_LAMBDA]]( // LAMBDA: call i{{[0-9]+}} @__tgt_target_teams( // LAMBDA: call void [[OFFLOADING_FUN:@.+]]( // LAMBDA: define{{.+}} void [[OFFLOADING_FUN]]() // LAMBDA: call {{.}}void {{.+}} @__kmpc_fork_teams({{.+}}, i32 0, {{.+}}* [[OMP_OUTLINED:@.+]] to {{.+}}) #pragma omp target #pragma omp teams #pragma omp distribute private(g, g1, svar, sfvar) for (int i = 0; i < 2; ++i) { // LAMBDA: define{{.}} internal{{.}} void [[OMP_OUTLINED]](i32* noalias %{{.+}}, i32* noalias %{{.+}}) // LAMBDA: [[G_PRIVATE_ADDR:%.+]] = alloca double, // LAMBDA: [[G1_PRIVATE_ADDR:%.+]] = alloca double, // LAMBDA: [[TMP_PRIVATE_ADDR:%.+]] = alloca double, // LAMBDA: [[SVAR_PRIVATE_ADDR:%.+]] = alloca i{{[0-9]+}}, // LAMBDA: [[SFVAR_PRIVATE_ADDR:%.+]] = alloca float, // LAMBDA: store double [[G1_PRIVATE_ADDR]], double** [[TMP_PRIVATE_ADDR]], g = 1; g1 = 1; svar = 3; sfvar = 4.0; // LAMBDA: call {{.}}void @__kmpc_for_static_init_4( // LAMBDA: store double 1.0{{.+}}, double [[G_PRIVATE_ADDR]], // LAMBDA: store i{{[0-9]+}} 3, i{{[0-9]+}}* [[SVAR_PRIVATE_ADDR]], // LAMBDA: store float 4.0{{.+}}, float* [[SFVAR_PRIVATE_ADDR]], // LAMBDA: [[G_PRIVATE_ADDR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 // LAMBDA: store double* [[G_PRIVATE_ADDR]], double** [[G_PRIVATE_ADDR_REF]], // LAMBDA: [[TMP_PRIVATE_ADDR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // LAMBDA: [[G1_PRIVATE_ADDR_FROM_TMP:%.+]] = load double, double* [[TMP_PRIVATE_ADDR]], // LAMBDA: store double* [[G1_PRIVATE_ADDR_FROM_TMP]], double** [[TMP_PRIVATE_ADDR_REF]], // LAMBDA: [[SVAR_PRIVATE_ADDR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // LAMBDA: store i{{[0-9]+}}* [[SVAR_PRIVATE_ADDR]], i{{[0-9]+}}** [[SVAR_PRIVATE_ADDR_REF]] // LAMBDA: [[SFVAR_PRIVATE_ADDR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 3 // LAMBDA: store float* [[SFVAR_PRIVATE_ADDR]], float** [[SFVAR_PRIVATE_ADDR_REF]] // LAMBDA: call{{.}} void [[INNER_LAMBDA:@.+]](%{{.+}} [[ARG]]) // LAMBDA: call {{.}}void @__kmpc_for_static_fini( [&]() { // LAMBDA: define {{.+}} void [[INNER_LAMBDA]](%{{.+}} [[ARG_PTR:%.+]]) // LAMBDA: store %{{.+}}* [[ARG_PTR]], %{{.+}}** [[ARG_PTR_REF:%.+]], g = 2; g1 = 2; svar = 4; sfvar = 8.0; // LAMBDA: [[ARG_PTR:%.+]] = load %{{.+}}, %{{.+}}* [[ARG_PTR_REF]] // LAMBDA: [[G_PTR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG_PTR]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 // LAMBDA: [[G_REF:%.+]] = load double, double* [[G_PTR_REF]] // LAMBDA: store double 2.0{{.+}}, double* [[G_REF]] // LAMBDA: [[TMP_PTR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG_PTR]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // LAMBDA: [[G1_REF:%.+]] = load double, double* [[TMP_PTR_REF]] // LAMBDA: store double 2.0{{.+}}, double* [[G1_REF]], // LAMBDA: [[SVAR_PTR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG_PTR]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // LAMBDA: [[SVAR_REF:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[SVAR_PTR_REF]] // LAMBDA: store i{{[0-9]+}} 4, i{{[0-9]+}}* [[SVAR_REF]] // LAMBDA: [[SFVAR_PTR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG_PTR]], i{{[0-9]+}} 0, i{{[0-9]+}} 3 // LAMBDA: [[SFVAR_REF:%.+]] = load float, float* [[SFVAR_PTR_REF]] // LAMBDA: store float 8.0{{.+}}, float* [[SFVAR_REF]] }(); } }(); return 0; #else S<float> test; int t_var = 0; int vec[] = {1, 2}; S<float> s_arr[] = {1, 2}; S<float> &var = test; #pragma omp target #pragma omp teams #pragma omp distribute private(t_var, vec, s_arr, s_arr, var, var, svar) for (int i = 0; i < 2; ++i) { vec[i] = t_var; s_arr[i] = var; } int i; #pragma omp target #pragma omp teams #pragma omp distribute private(i) for (i = 0; i < 2; ++i) { ; } return tmain<int>(); #endif } // CHECK: define{{.}} i{{[0-9]+}} @main() // CHECK: [[TEST:%.+]] = alloca [[S_FLOAT_TY]], // CHECK: call {{.}} [[S_FLOAT_TY_DEF_CONSTR:@.+]]([[S_FLOAT_TY]]* [[TEST]]) // CHECK: call i{{[0-9]+}} @__tgt_target_teams( // CHECK: call void [[OFFLOAD_FUN:@.+]]( // CHECK: ret // CHECK: define{{.+}} [[OFFLOAD_FUN]]() // CHECK: call void (%{{.+}}, i{{[0-9]+}}, void (i{{[0-9]+}}, i{{[0-9]+}}, ...), ...) @__kmpc_fork_teams(%{{.+}}* @{{.+}}, i{{[0-9]+}} 0, void (i{{[0-9]+}}, i{{[0-9]+}}, ...)* bitcast (void (i{{[0-9]+}}, i{{[0-9]+}})* [[OMP_OUTLINED:@.+]] to void // CHECK: ret // // CHECK: define internal void [[OMP_OUTLINED]](i{{[0-9]+}}* noalias [[GTID_ADDR:%.+]], i{{[0-9]+}}* noalias %{{.+}}) // CHECK: [[T_VAR_PRIV:%.+]] = alloca i{{[0-9]+}}, // CHECK: [[VEC_PRIV:%.+]] = alloca [2 x i{{[0-9]+}}], // CHECK: [[S_ARR_PRIV:%.+]] = alloca [2 x [[S_FLOAT_TY]]], // CHECK-NOT: alloca [2 x [[S_FLOAT_TY]]], // CHECK: [[VAR_PRIV:%.+]] = alloca [[S_FLOAT_TY]], // CHECK-NOT: alloca [[S_FLOAT_TY]], // CHECK: [[S_VAR_PRIV:%.+]] = alloca i{{[0-9]+}}, // CHECK: store i{{[0-9]+}}* [[GTID_ADDR]], i{{[0-9]+}}** [[GTID_ADDR_REF:%.+]] // CHECK-NOT: [[T_VAR_PRIV]] // CHECK-NOT: [[VEC_PRIV]] // CHECK: {{.+}}: // CHECK: [[S_ARR_PRIV_ITEM:%.+]] = phi [[S_FLOAT_TY]]* // CHECK: call {{.}} [[S_FLOAT_TY_DEF_CONSTR]]([[S_FLOAT_TY]] [[S_ARR_PRIV_ITEM]]) // CHECK-NOT: [[T_VAR_PRIV]] // CHECK-NOT: [[VEC_PRIV]] // CHECK: call {{.}} [[S_FLOAT_TY_DEF_CONSTR]]([[S_FLOAT_TY]] [[VAR_PRIV]]) // CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_fini( // CHECK: ret void // CHECK: define{{.}} i{{[0-9]+}} [[TMAIN_INT:@.+]]() // CHECK: [[TEST:%.+]] = alloca [[S_INT_TY]], // CHECK: call {{.}} [[S_INT_TY_DEF_CONSTR:@.+]]([[S_INT_TY]]* [[TEST]]) // CHECK: call i{{[0-9]+}} @__tgt_target_teams( // CHECK: call void [[OFFLOAD_FUN_1:@.+]]( // CHECK: ret // CHECK: define internal void [[OFFLOAD_FUN_1]]() // CHECK: call void (%{{.+}}, i{{[0-9]+}}, void (i{{[0-9]+}}, i{{[0-9]+}}, ...), ...) @__kmpc_fork_teams(%{{.+}}* @{{.+}}, i{{[0-9]+}} 0, void (i{{[0-9]+}}, i{{[0-9]+}}, ...)* bitcast (void (i{{[0-9]+}}, i{{[0-9]+}})* [[OMP_OUTLINED_1:@.+]] to void // CHECK: ret // // CHECK: define internal void [[OMP_OUTLINED_1]](i{{[0-9]+}}* noalias [[GTID_ADDR:%.+]], i{{[0-9]+}}* noalias %{{.+}}) // CHECK: [[T_VAR_PRIV:%.+]] = alloca i{{[0-9]+}}, // CHECK: [[VEC_PRIV:%.+]] = alloca [2 x i{{[0-9]+}}], // CHECK: [[S_ARR_PRIV:%.+]] = alloca [2 x [[S_INT_TY]]], // CHECK-NOT: alloca [2 x [[S_INT_TY]]], // CHECK: [[VAR_PRIV:%.+]] = alloca [[S_INT_TY]], // CHECK-NOT: alloca [[S_INT_TY]], // CHECK: store i{{[0-9]+}}* [[GTID_ADDR]], i{{[0-9]+}}** [[GTID_ADDR_REF:%.+]] // CHECK-NOT: [[T_VAR_PRIV]] // CHECK-NOT: [[VEC_PRIV]] // CHECK: {{.+}}: // CHECK: [[S_ARR_PRIV_ITEM:%.+]] = phi [[S_INT_TY]]* // CHECK: call {{.}} [[S_INT_TY_DEF_CONSTR]]([[S_INT_TY]] [[S_ARR_PRIV_ITEM]]) // CHECK-NOT: [[T_VAR_PRIV]] // CHECK-NOT: [[VEC_PRIV]] // CHECK: call {{.}} [[S_INT_TY_DEF_CONSTR]]([[S_INT_TY]] [[VAR_PRIV]]) // CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_fini( // CHECK: ret void #endif	{ "language": "Assembly" }
// Check that we extract -MD from '-Wp,-MD,FOO', which is used by a number of // major projects (e.g., FireFox and the Linux Kernel). // RUN: %clang -target i386-pc-linux-gnu -### \ // RUN: -Wp,-MD,FOO.d -fsyntax-only %s 2> %t // RUN: FileCheck < %t %s // // CHECK: "-cc1" // CHECK-NOT: -MD // CHECK: "-dependency-file" "FOO.d" // CHECK: "-MT" // // PR4062 // RUN: %clang -target i386-pc-linux-gnu -### \ // RUN: -Wp,-MMD -fsyntax-only %s 2> %t // RUN: FileCheck -check-prefix MMD < %t %s // MMD: "-cc1" // MMD-NOT: -MMD // MMD: "-dependency-file" "Wp-args.d"	{ "language": "Assembly" }
// Copyright 2009 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build !gccgo #include "textflag.h" // // System calls for AMD64, Linux // // Just jump to package syscall's implementation for all these functions. // The runtime may know about them. TEXT ·Syscall(SB),NOSPLIT,$0-56 JMP syscall·Syscall(SB) TEXT ·Syscall6(SB),NOSPLIT,$0-80 JMP syscall·Syscall6(SB) TEXT ·SyscallNoError(SB),NOSPLIT,$0-48 CALL runtime·entersyscall(SB) MOVQ a1+8(FP), DI MOVQ a2+16(FP), SI MOVQ a3+24(FP), DX MOVQ $0, R10 MOVQ $0, R8 MOVQ $0, R9 MOVQ trap+0(FP), AX // syscall entry SYSCALL MOVQ AX, r1+32(FP) MOVQ DX, r2+40(FP) CALL runtime·exitsyscall(SB) RET TEXT ·RawSyscall(SB),NOSPLIT,$0-56 JMP syscall·RawSyscall(SB) TEXT ·RawSyscall6(SB),NOSPLIT,$0-80 JMP syscall·RawSyscall6(SB) TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-48 MOVQ a1+8(FP), DI MOVQ a2+16(FP), SI MOVQ a3+24(FP), DX MOVQ $0, R10 MOVQ $0, R8 MOVQ $0, R9 MOVQ trap+0(FP), AX // syscall entry SYSCALL MOVQ AX, r1+32(FP) MOVQ DX, r2+40(FP) RET TEXT ·gettimeofday(SB),NOSPLIT,$0-16 JMP syscall·gettimeofday(SB)	{ "language": "Assembly" }
; RUN: opt < %s -instcombine \| llvm-dis ; rdar://5771353 define float @test(float %x, x86_fp80 %y) nounwind readonly { entry: %tmp67 = fcmp uno x86_fp80 %y, 0xK00000000000000000000 ; <i1> [#uses=1] %tmp71 = fcmp uno float %x, 0.000000e+00 ; <i1> [#uses=1] %bothcond = or i1 %tmp67, %tmp71 ; <i1> [#uses=1] br i1 %bothcond, label %bb74, label %bb80 bb74: ; preds = %entry ret float 0.000000e+00 bb80: ; preds = %entry ret float 0.000000e+00 }	{ "language": "Assembly" }
dnl AMD64 mpn_addmul_1 and mpn_submul_1 optimised for Intel Nehalem. dnl Contributed to the GNU project by Torbjörn Granlund. dnl Copyright 2003-2005, 2007, 2008, 2011-2013 Free Software Foundation, Inc. dnl This file is part of the GNU MP Library. dnl dnl The GNU MP Library is free software; you can redistribute it and/or modify dnl it under the terms of either: dnl dnl * the GNU Lesser General Public License as published by the Free dnl Software Foundation; either version 3 of the License, or (at your dnl option) any later version. dnl dnl or dnl dnl * the GNU General Public License as published by the Free Software dnl Foundation; either version 2 of the License, or (at your option) any dnl later version. dnl dnl or both in parallel, as here. dnl dnl The GNU MP Library is distributed in the hope that it will be useful, but dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License dnl for more details. dnl dnl You should have received copies of the GNU General Public License and the dnl GNU Lesser General Public License along with the GNU MP Library. If not, dnl see https://www.gnu.org/licenses/. include(`../config.m4') C cycles/limb C AMD K8,K9 4.0 C AMD K10 4.0 C AMD bull 5.0 C AMD pile 4.84 5.39 C AMD steam C AMD excavator C AMD bobcat 5.56 C AMD jaguar 5.30 C Intel P4 15.7 17.2 C Intel core2 5.15 C Intel NHM 4.56 C Intel SBR 3.44 C Intel HWL 3.03 C Intel BWL 2.77 C Intel SKL 2.76 C Intel atom 21 C Intel SLM 11 C VIA nano C The loop of this code is the result of running a code generation and C optimization tool suite written by David Harvey and Torbjorn Granlund. C N.B.: Be careful if editing, making sure the loop alignment padding does not C become large, as we currently fall into it. define(`rp', `%rdi') C rcx define(`up', `%rsi') C rdx define(`n_param', `%rdx') C r8 define(`v0', `%rcx') C r9 define(`n', `%rbx') ifdef(`OPERATION_addmul_1',` define(`ADDSUB', `add') define(`func', `mpn_addmul_1') ') ifdef(`OPERATION_submul_1',` define(`ADDSUB', `sub') define(`func', `mpn_submul_1') ') ABI_SUPPORT(DOS64) ABI_SUPPORT(STD64) MULFUNC_PROLOGUE(mpn_addmul_1 mpn_submul_1) ASM_START() TEXT ALIGN(32) PROLOGUE(func) FUNC_ENTRY(4) push %rbx mov (up), %rax lea -8(up,n_param,8), up mov (rp), %r8 lea -8(rp,n_param,8), rp test $1, R8(n_param) jnz L(bx1) L(bx0): test $2, R8(n_param) jnz L(b10) L(b00): mov $3, R32(n) sub n_param, n mul v0 mov $0, R32(%r11) mov %r8, %r10 ADDSUB %rax, %r10 mov -8(up,n,8), %rax adc %rdx, %r11 jmp L(lo0) L(b10): mov $1, R32(n) sub n_param, n mul v0 mov %r8, %r10 mov $0, R32(%r11) ADDSUB %rax, %r10 mov 8(up,n,8), %rax adc %rdx, %r11 jmp L(lo2) L(bx1): test $2, R8(n_param) jz L(b01) L(b11): mov $2, R32(n) sub n_param, n mul v0 ADDSUB %rax, %r8 mov $0, R32(%r9) mov (up,n,8), %rax adc %rdx, %r9 jmp L(lo3) L(b01): mov $0, R32(n) sub n_param, n xor %r11, %r11 add $4, n jc L(end) ALIGN(32) L(top): mul v0 ADDSUB %rax, %r8 mov $0, R32(%r9) mov -16(up,n,8), %rax adc %rdx, %r9 L(lo1): mul v0 ADDSUB %r11, %r8 mov $0, R32(%r11) mov -16(rp,n,8), %r10 adc $0, %r9 ADDSUB %rax, %r10 mov -8(up,n,8), %rax adc %rdx, %r11 mov %r8, -24(rp,n,8) ADDSUB %r9, %r10 adc $0, %r11 L(lo0): mov -8(rp,n,8), %r8 mul v0 ADDSUB %rax, %r8 mov $0, R32(%r9) mov (up,n,8), %rax adc %rdx, %r9 mov %r10, -16(rp,n,8) ADDSUB %r11, %r8 adc $0, %r9 L(lo3): mul v0 mov (rp,n,8), %r10 mov $0, R32(%r11) ADDSUB %rax, %r10 mov 8(up,n,8), %rax adc %rdx, %r11 mov %r8, -8(rp,n,8) ADDSUB %r9, %r10 adc $0, %r11 L(lo2): mov 8(rp,n,8), %r8 mov %r10, (rp,n,8) add $4, n jnc L(top) L(end): mul v0 ADDSUB %rax, %r8 mov $0, R32(%rax) adc %rdx, %rax ADDSUB %r11, %r8 adc $0, %rax mov %r8, (rp) pop %rbx FUNC_EXIT() ret EPILOGUE() ASM_END()	{ "language": "Assembly" }
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s \| FileCheck %s blendpd $11, %xmm0, %xmm2 blendpd $11, (%rax), %xmm2 blendps $11, %xmm0, %xmm2 blendps $11, (%rax), %xmm2 blendvpd %xmm0, %xmm2 blendvpd (%rax), %xmm2 blendvps %xmm0, %xmm2 blendvps (%rax), %xmm2 dppd $22, %xmm0, %xmm2 dppd $22, (%rax), %xmm2 dpps $22, %xmm0, %xmm2 dpps $22, (%rax), %xmm2 extractps $1, %xmm0, %rcx extractps $1, %xmm0, (%rax) insertps $1, %xmm0, %xmm2 insertps $1, (%rax), %xmm2 movntdqa (%rax), %xmm2 mpsadbw $1, %xmm0, %xmm2 mpsadbw $1, (%rax), %xmm2 packusdw %xmm0, %xmm2 packusdw (%rax), %xmm2 pblendvb %xmm0, %xmm2 pblendvb (%rax), %xmm2 pblendw $11, %xmm0, %xmm2 pblendw $11, (%rax), %xmm2 pcmpeqq %xmm0, %xmm2 pcmpeqq (%rax), %xmm2 pextrb $1, %xmm0, %ecx pextrb $1, %xmm0, (%rax) pextrd $1, %xmm0, %ecx pextrd $1, %xmm0, (%rax) pextrq $1, %xmm0, %rcx pextrq $1, %xmm0, (%rax) pextrw $1, %xmm0, (%rax) phminposuw %xmm0, %xmm2 phminposuw (%rax), %xmm2 pinsrb $1, %eax, %xmm1 pinsrb $1, (%rax), %xmm1 pinsrd $1, %eax, %xmm1 pinsrd $1, (%rax), %xmm1 pinsrq $1, %rax, %xmm1 pinsrq $1, (%rax), %xmm1 pmaxsb %xmm0, %xmm2 pmaxsb (%rax), %xmm2 pmaxsd %xmm0, %xmm2 pmaxsd (%rax), %xmm2 pmaxud %xmm0, %xmm2 pmaxud (%rax), %xmm2 pmaxuw %xmm0, %xmm2 pmaxuw (%rax), %xmm2 pminsb %xmm0, %xmm2 pminsb (%rax), %xmm2 pminsd %xmm0, %xmm2 pminsd (%rax), %xmm2 pminud %xmm0, %xmm2 pminud (%rax), %xmm2 pminuw %xmm0, %xmm2 pminuw (%rax), %xmm2 pmovsxbd %xmm0, %xmm2 pmovsxbd (%rax), %xmm2 pmovsxbq %xmm0, %xmm2 pmovsxbq (%rax), %xmm2 pmovsxbw %xmm0, %xmm2 pmovsxbw (%rax), %xmm2 pmovsxdq %xmm0, %xmm2 pmovsxdq (%rax), %xmm2 pmovsxwd %xmm0, %xmm2 pmovsxwd (%rax), %xmm2 pmovsxwq %xmm0, %xmm2 pmovsxwq (%rax), %xmm2 pmovzxbd %xmm0, %xmm2 pmovzxbd (%rax), %xmm2 pmovzxbq %xmm0, %xmm2 pmovzxbq (%rax), %xmm2 pmovzxbw %xmm0, %xmm2 pmovzxbw (%rax), %xmm2 pmovzxdq %xmm0, %xmm2 pmovzxdq (%rax), %xmm2 pmovzxwd %xmm0, %xmm2 pmovzxwd (%rax), %xmm2 pmovzxwq %xmm0, %xmm2 pmovzxwq (%rax), %xmm2 pmuldq %xmm0, %xmm2 pmuldq (%rax), %xmm2 pmulld %xmm0, %xmm2 pmulld (%rax), %xmm2 ptest %xmm0, %xmm1 ptest (%rax), %xmm1 roundpd $1, %xmm0, %xmm2 roundpd $1, (%rax), %xmm2 roundps $1, %xmm0, %xmm2 roundps $1, (%rax), %xmm2 roundsd $1, %xmm0, %xmm2 roundsd $1, (%rax), %xmm2 roundss $1, %xmm0, %xmm2 roundss $1, (%rax), %xmm2 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [2]: Latency # CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 1 0.50 blendpd $11, %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * blendpd $11, (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 blendps $11, %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * blendps $11, (%rax), %xmm2 # CHECK-NEXT: 2 2 1.00 blendvpd %xmm0, %xmm0, %xmm2 # CHECK-NEXT: 3 8 1.00 * blendvpd %xmm0, (%rax), %xmm2 # CHECK-NEXT: 2 2 1.00 blendvps %xmm0, %xmm0, %xmm2 # CHECK-NEXT: 3 8 1.00 * blendvps %xmm0, (%rax), %xmm2 # CHECK-NEXT: 3 9 1.00 dppd $22, %xmm0, %xmm2 # CHECK-NEXT: 4 15 1.00 * dppd $22, (%rax), %xmm2 # CHECK-NEXT: 4 12 2.00 dpps $22, %xmm0, %xmm2 # CHECK-NEXT: 5 18 2.00 * dpps $22, (%rax), %xmm2 # CHECK-NEXT: 2 3 1.00 extractps $1, %xmm0, %ecx # CHECK-NEXT: 3 5 1.00 * extractps $1, %xmm0, (%rax) # CHECK-NEXT: 1 1 1.00 insertps $1, %xmm0, %xmm2 # CHECK-NEXT: 2 7 1.00 * insertps $1, (%rax), %xmm2 # CHECK-NEXT: 1 6 0.50 * movntdqa (%rax), %xmm2 # CHECK-NEXT: 3 7 1.00 mpsadbw $1, %xmm0, %xmm2 # CHECK-NEXT: 4 13 1.00 * mpsadbw $1, (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 packusdw %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * packusdw (%rax), %xmm2 # CHECK-NEXT: 2 2 1.00 pblendvb %xmm0, %xmm0, %xmm2 # CHECK-NEXT: 3 8 1.00 * pblendvb %xmm0, (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pblendw $11, %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pblendw $11, (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pcmpeqq %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pcmpeqq (%rax), %xmm2 # CHECK-NEXT: 2 3 1.00 pextrb $1, %xmm0, %ecx # CHECK-NEXT: 3 5 1.00 * pextrb $1, %xmm0, (%rax) # CHECK-NEXT: 2 3 1.00 pextrd $1, %xmm0, %ecx # CHECK-NEXT: 4 5 1.00 * pextrd $1, %xmm0, (%rax) # CHECK-NEXT: 2 3 1.00 pextrq $1, %xmm0, %rcx # CHECK-NEXT: 4 5 1.00 * pextrq $1, %xmm0, (%rax) # CHECK-NEXT: 3 5 1.00 * pextrw $1, %xmm0, (%rax) # CHECK-NEXT: 1 5 1.00 phminposuw %xmm0, %xmm2 # CHECK-NEXT: 2 11 1.00 * phminposuw (%rax), %xmm2 # CHECK-NEXT: 2 2 1.00 pinsrb $1, %eax, %xmm1 # CHECK-NEXT: 2 7 0.50 * pinsrb $1, (%rax), %xmm1 # CHECK-NEXT: 2 2 1.00 pinsrd $1, %eax, %xmm1 # CHECK-NEXT: 2 7 0.50 * pinsrd $1, (%rax), %xmm1 # CHECK-NEXT: 2 2 1.00 pinsrq $1, %rax, %xmm1 # CHECK-NEXT: 2 7 0.50 * pinsrq $1, (%rax), %xmm1 # CHECK-NEXT: 1 1 0.50 pmaxsb %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmaxsb (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmaxsd %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmaxsd (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmaxud %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmaxud (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmaxuw %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmaxuw (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pminsb %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pminsb (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pminsd %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pminsd (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pminud %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pminud (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pminuw %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pminuw (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovsxbd %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovsxbd (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovsxbq %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovsxbq (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovsxbw %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovsxbw (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovsxdq %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovsxdq (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovsxwd %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovsxwd (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovsxwq %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovsxwq (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovzxbd %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovzxbd (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovzxbq %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovzxbq (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovzxbw %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovzxbw (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovzxdq %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovzxdq (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovzxwd %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovzxwd (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovzxwq %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovzxwq (%rax), %xmm2 # CHECK-NEXT: 1 5 1.00 pmuldq %xmm0, %xmm2 # CHECK-NEXT: 2 11 1.00 * pmuldq (%rax), %xmm2 # CHECK-NEXT: 1 5 1.00 pmulld %xmm0, %xmm2 # CHECK-NEXT: 2 11 1.00 * pmulld (%rax), %xmm2 # CHECK-NEXT: 2 2 1.00 ptest %xmm0, %xmm1 # CHECK-NEXT: 3 8 1.00 * ptest (%rax), %xmm1 # CHECK-NEXT: 1 3 1.00 roundpd $1, %xmm0, %xmm2 # CHECK-NEXT: 2 9 1.00 * roundpd $1, (%rax), %xmm2 # CHECK-NEXT: 1 3 1.00 roundps $1, %xmm0, %xmm2 # CHECK-NEXT: 2 9 1.00 * roundps $1, (%rax), %xmm2 # CHECK-NEXT: 1 3 1.00 roundsd $1, %xmm0, %xmm2 # CHECK-NEXT: 2 9 1.00 * roundsd $1, (%rax), %xmm2 # CHECK-NEXT: 1 3 1.00 roundss $1, %xmm0, %xmm2 # CHECK-NEXT: 2 9 1.00 * roundss $1, (%rax), %xmm2 # CHECK: Resources: # CHECK-NEXT: [0] - SBDivider # CHECK-NEXT: [1] - SBFPDivider # CHECK-NEXT: [2] - SBPort0 # CHECK-NEXT: [3] - SBPort1 # CHECK-NEXT: [4] - SBPort4 # CHECK-NEXT: [5] - SBPort5 # CHECK-NEXT: [6.0] - SBPort23 # CHECK-NEXT: [6.1] - SBPort23 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] # CHECK-NEXT: - - 26.00 47.50 5.00 52.50 24.50 24.50 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: # CHECK-NEXT: - - 0.50 - - 0.50 - - blendpd $11, %xmm0, %xmm2 # CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 blendpd $11, (%rax), %xmm2 # CHECK-NEXT: - - 0.50 - - 0.50 - - blendps $11, %xmm0, %xmm2 # CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 blendps $11, (%rax), %xmm2 # CHECK-NEXT: - - 1.00 - - 1.00 - - blendvpd %xmm0, %xmm0, %xmm2 # CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 blendvpd %xmm0, (%rax), %xmm2 # CHECK-NEXT: - - 1.00 - - 1.00 - - blendvps %xmm0, %xmm0, %xmm2 # CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 blendvps %xmm0, (%rax), %xmm2 # CHECK-NEXT: - - 1.00 1.00 - 1.00 - - dppd $22, %xmm0, %xmm2 # CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 dppd $22, (%rax), %xmm2 # CHECK-NEXT: - - 1.00 2.00 - 1.00 - - dpps $22, %xmm0, %xmm2 # CHECK-NEXT: - - 1.00 2.00 - 1.00 0.50 0.50 dpps $22, (%rax), %xmm2 # CHECK-NEXT: - - 1.00 - - 1.00 - - extractps $1, %xmm0, %ecx # CHECK-NEXT: - - - - 1.00 1.00 0.50 0.50 extractps $1, %xmm0, (%rax) # CHECK-NEXT: - - - - - 1.00 - - insertps $1, %xmm0, %xmm2 # CHECK-NEXT: - - - - - 1.00 0.50 0.50 insertps $1, (%rax), %xmm2 # CHECK-NEXT: - - - - - - 0.50 0.50 movntdqa (%rax), %xmm2 # CHECK-NEXT: - - 1.00 1.00 - 1.00 - - mpsadbw $1, %xmm0, %xmm2 # CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 mpsadbw $1, (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - packusdw %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 packusdw (%rax), %xmm2 # CHECK-NEXT: - - - 1.00 - 1.00 - - pblendvb %xmm0, %xmm0, %xmm2 # CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 pblendvb %xmm0, (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pblendw $11, %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pblendw $11, (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpeqq %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpeqq (%rax), %xmm2 # CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pextrb $1, %xmm0, %ecx # CHECK-NEXT: - - - 0.50 1.00 0.50 0.50 0.50 pextrb $1, %xmm0, (%rax) # CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pextrd $1, %xmm0, %ecx # CHECK-NEXT: - - 1.00 0.50 1.00 0.50 0.50 0.50 pextrd $1, %xmm0, (%rax) # CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pextrq $1, %xmm0, %rcx # CHECK-NEXT: - - 1.00 0.50 1.00 0.50 0.50 0.50 pextrq $1, %xmm0, (%rax) # CHECK-NEXT: - - - 0.50 1.00 0.50 0.50 0.50 pextrw $1, %xmm0, (%rax) # CHECK-NEXT: - - 1.00 - - - - - phminposuw %xmm0, %xmm2 # CHECK-NEXT: - - 1.00 - - - 0.50 0.50 phminposuw (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 1.50 - - pinsrb $1, %eax, %xmm1 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pinsrb $1, (%rax), %xmm1 # CHECK-NEXT: - - - 0.50 - 1.50 - - pinsrd $1, %eax, %xmm1 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pinsrd $1, (%rax), %xmm1 # CHECK-NEXT: - - - 0.50 - 1.50 - - pinsrq $1, %rax, %xmm1 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pinsrq $1, (%rax), %xmm1 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxsb %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxsb (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxsd %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxsd (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxud %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxud (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxuw %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxuw (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pminsb %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminsb (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pminsd %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminsd (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pminud %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminud (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pminuw %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminuw (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxbd %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxbd (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxbq %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxbq (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxbw %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxbw (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxdq %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxdq (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxwd %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxwd (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxwq %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxwq (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxbd %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxbd (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxbq %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxbq (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxbw %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxbw (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxdq %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxdq (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxwd %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxwd (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxwq %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxwq (%rax), %xmm2 # CHECK-NEXT: - - 1.00 - - - - - pmuldq %xmm0, %xmm2 # CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmuldq (%rax), %xmm2 # CHECK-NEXT: - - 1.00 - - - - - pmulld %xmm0, %xmm2 # CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulld (%rax), %xmm2 # CHECK-NEXT: - - 1.00 - - 1.00 - - ptest %xmm0, %xmm1 # CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 ptest (%rax), %xmm1 # CHECK-NEXT: - - - 1.00 - - - - roundpd $1, %xmm0, %xmm2 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 roundpd $1, (%rax), %xmm2 # CHECK-NEXT: - - - 1.00 - - - - roundps $1, %xmm0, %xmm2 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 roundps $1, (%rax), %xmm2 # CHECK-NEXT: - - - 1.00 - - - - roundsd $1, %xmm0, %xmm2 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 roundsd $1, (%rax), %xmm2 # CHECK-NEXT: - - - 1.00 - - - - roundss $1, %xmm0, %xmm2 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 roundss $1, (%rax), %xmm2	{ "language": "Assembly" }
## Test that yaml2obj emits .debug_info section. ## a) Generate the .debug_info section from the "DWARF" entry. ## Generate and verify a DWARF32 little endian .debug_info (DWARFv5) section. # RUN: yaml2obj --docnum=1 -DENDIAN=ELFDATA2LSB %s -o %t1.le.o # RUN: llvm-readobj --sections --section-data %t1.le.o \| \ # RUN: FileCheck -DINDEX=2 -DNAME=15 -DOFFSET=0x9B -DSIZE=179 -DADDRALIGN=1 %s --check-prefixes=SHDR,DWARF32-LE-CONTENT # SHDR: Index: [[INDEX]] # SHDR-NEXT: Name: .debug_info ([[NAME]]) # SHDR-NEXT: Type: SHT_PROGBITS (0x1) # SHDR-NEXT: Flags [ (0x0) # SHDR-NEXT: ] # SHDR-NEXT: Address: 0x0 # SHDR-NEXT: Offset: [[OFFSET]] # SHDR-NEXT: Size: [[SIZE]] # SHDR-NEXT: Link: 0 # SHDR-NEXT: Info: 0 # SHDR-NEXT: AddressAlignment: [[ADDRALIGN]] # SHDR-NEXT: EntrySize: 0 # DWARF32-LE-CONTENT-NEXT: SectionData ( # DWARF32-LE-CONTENT-NEXT: 0000: 34120000 05000204 34120000 01785634 ## ^------- unit_length (4-byte) ## ^--- version (2-byte) ## ^- unit_type (1-byte) DW_UT_type ## ^- address_size (1-byte) ## ^------- debug_abbrev_offset (4-byte) ## ^- abbreviation code (LEB128) 0x01 ## ^----- Form: DW_FORM_addr (4-byte) # DWARF32-LE-CONTENT-NEXT: 0010: 12020012 34020000 00123434 12785634 ## -- ## ^--- Form: DW_FORM_block2 size (2-byte) ## ^- ^- Form: DW_FORM_block2 body (2-byte) ## ^-------- Form: DW_FORM_block4 size (4-byte) ## ^-^- Form: DW_FORM_block4 body (2-byte) ## ^---- Form: DW_FORM_data2 (2-byte) ## ^----- Form: DW_FORM_data4 (4-byte) # DWARF32-LE-CONTENT-NEXT: 0020: 12F0DEBC 9A785634 12616263 64000212 ## -- ## ^----------------- Form: DW_FORM_data8 (8-byte) ## ^---------- Form: DW_FORM_string "abcd\0" ## ^- Form: DW_FORM_block size (ULEB128) ## ^- Form: DW_FORM_block body (2-byte) # DWARF32-LE-CONTENT-NEXT: 0030: 34021234 1201B424 78563412 B4247856 ## ^- Form: DW_FORM_block body ## ^- Form: DW_FORM_block1 size (1-byte) ## ^-^- Form: DW_FORM_block1 body (2-byte) ## ^- Form: DW_FORM_data1 (1-byte) ## ^- Form: DW_FORM_flag (1-byte) ## ^--- Form: DW_FORM_sdata (SLEB128) 0x1234 ## ^------- Form: DW_FORM_strp (4-byte) ## ^--- Form: DW_FORM_udata (ULEB128) 0x1234 ## ^--- Form: DW_FORM_ref_addr (4-byte) # DWARF32-LE-CONTENT-NEXT: 0040: 34121234 12785634 12F0DEBC 9A785634 ## ---- ## ^- Form: DW_FORM_ref1 (1-byte) ## ^---- Form: DW_FORM_ref2 (2-byte) ## ^-------- Form: DW_FORM_ref4 (4-byte) ## ^-------------- Form: DW_FORM_ref8 (8-byte) # DWARF32-LE-CONTENT-NEXT: 0050: 12B42408 65666768 00341200 00021234 ## -- ## ^--- Form: DW_FORM_ref_udata (ULEB128) 0x1234 ## ^- Form: DW_FORM_indirect (ULEB128) DW_FORM_string ## ^---------- "efgh\0" ## ^-------- Form: DW_FORM_sec_offset (4-byte) ## ^- Form: DW_FORM_exprloc size (ULEB128) 0x02 ## ^-^- Form: DW_FORM_exprloc body (2-byte) # DWARF32-LE-CONTENT-NEXT: 0060: B424B424 78563412 78563412 78563412 ## ^--- Form: DW_FORM_strx (ULEB128) ## ^--- Form: DW_FORM_addrx (ULEB128) ## ^------- Form: DW_FORM_ref_sup4 (4-byte) ## ^------- Form: DW_FORM_strp_sup (4-byte) ## ^------- Form: DW_FORM_line_strp (4-byte) # DWARF32-LE-CONTENT-NEXT: 0070: F0DEBC9A 78563412 B424B424 F0DEBC9A ## ^---------------- Form: DW_FORM_ref_sig8 (8-byte) ## ^--- Form: DW_FORM_loclistx (ULEB128) ## ^--- Form: DW_FORM_rnglistx (ULEB128) ## ^------- Form: DW_FORM_ref_sup8 (8-byte) # DWARF32-LE-CONTENT-NEXT: 0080: 78563412 12341278 56341212 34127856 ## -------- ## ^- Form: DW_FORM_strx1 (1-byte) ## ^--- Form: DW_FORM_strx2 (2-byte) ## ^-------- Form: DW_FORM_strx4 (4-byte) ## ^- Form: DW_FORM_addrx1 (1-byte) ## ^--- Form: DW_FORM_addrx2 (1-byte) ## ^--- Form: DW_FORM_addrx4 (4-byte) # DWARF32-LE-CONTENT-NEXT: 0090: 34123412 00000500 01043412 00000078 ## ---- ## ^-------- unit_length (4-byte) ## ^--- version (2-byte) ## ^- unit_type (1-byte) ## ^- address_size (1-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- abbrev code (ULEB128) 0x00 ## ^- unit_length (4-byte) # DWARF32-LE-CONTENT-NEXT: 00A0: 56000004 00785600 00040178 56341202 ## ------ ## ^---- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) ## ^- abbrev code (ULEB128) 0x01 ## ^-------- Form: DW_FORM_addr ## ^- Form: DW_FORM_block2 size (2-byte) # DWARF32-LE-CONTENT-NEXT: 00B0: 001234 ## -- ## ^-^- Form: DW_FORM_block2 body (2-byte) # DWARF32-LE-CONTENT-NEXT: ) --- !ELF FileHeader: Class: ELFCLASS64 Data: [[ENDIAN]] Type: ET_EXEC DWARF: debug_abbrev: - Table: - Code: 1 Tag: DW_TAG_compile_unit Children: DW_CHILDREN_no Attributes: - Attribute: 0x01 Form: DW_FORM_addr ## 0x01 - Attribute: 0x01 Form: DW_FORM_block2 ## 0x03 - Attribute: 0x01 Form: DW_FORM_block4 ## 0x04 - Attribute: 0x01 Form: DW_FORM_data2 ## 0x05 - Attribute: 0x01 Form: DW_FORM_data4 ## 0x06 - Attribute: 0x01 Form: DW_FORM_data8 ## 0x07 - Attribute: 0x01 Form: DW_FORM_string ## 0x08 - Attribute: 0x01 Form: DW_FORM_block ## 0x09 - Attribute: 0x01 Form: DW_FORM_block1 ## 0x0a - Attribute: 0x01 Form: DW_FORM_data1 ## 0x0b - Attribute: 0x01 Form: DW_FORM_flag ## 0x0c - Attribute: 0x01 Form: DW_FORM_sdata ## 0x0d - Attribute: 0x01 Form: DW_FORM_strp ## 0x0e - Attribute: 0x01 Form: DW_FORM_udata ## 0x0f - Attribute: 0x01 Form: DW_FORM_ref_addr ## 0x10 - Attribute: 0x01 Form: DW_FORM_ref1 ## 0x11 - Attribute: 0x01 Form: DW_FORM_ref2 ## 0x12 - Attribute: 0x01 Form: DW_FORM_ref4 ## 0x13 - Attribute: 0x01 Form: DW_FORM_ref8 ## 0x14 - Attribute: 0x01 Form: DW_FORM_ref_udata ## 0x15 - Attribute: 0x01 Form: DW_FORM_indirect ## 0x16 - Attribute: 0x01 Form: DW_FORM_sec_offset ## 0x17 - Attribute: 0x01 Form: DW_FORM_exprloc ## 0x18 - Attribute: 0x01 Form: DW_FORM_strx ## 0x1a - Attribute: 0x01 Form: DW_FORM_addrx ## 0x1b - Attribute: 0x01 Form: DW_FORM_ref_sup4 ## 0x1c - Attribute: 0x01 Form: DW_FORM_strp_sup ## 0x1d - Attribute: 0x01 Form: DW_FORM_data16 ## 0x1e - Attribute: 0x01 Form: DW_FORM_line_strp ## 0x1f - Attribute: 0x01 Form: DW_FORM_ref_sig8 ## 0x20 - Attribute: 0x01 Form: DW_FORM_implicit_const ## 0x21 Value: 0x01 - Attribute: 0x01 Form: DW_FORM_loclistx ## 0x22 - Attribute: 0x01 Form: DW_FORM_rnglistx ## 0x23 - Attribute: 0x01 Form: DW_FORM_ref_sup8 ## 0x24 - Attribute: 0x01 Form: DW_FORM_strx1 ## 0x25 - Attribute: 0x01 Form: DW_FORM_strx2 ## 0x26 - Attribute: 0x01 Form: DW_FORM_strx3 ## 0x27 - Attribute: 0x01 Form: DW_FORM_strx4 ## 0x28 - Attribute: 0x01 Form: DW_FORM_addrx1 ## 0x29 - Attribute: 0x01 Form: DW_FORM_addrx2 ## 0x2a - Attribute: 0x01 Form: DW_FORM_addrx3 ## 0x2b - Attribute: 0x01 Form: DW_FORM_addrx4 ## 0x2c debug_info: - Length: 0x1234 Version: 5 UnitType: DW_UT_type AbbrOffset: 0x1234 AddrSize: 4 Entries: - AbbrCode: 1 Values: - Value: 0x12345678 ## DW_FORM_addr - BlockData: ## DW_FORM_block2 - 0x12 - 0x34 - BlockData: ## DW_FORM_block4 - 0x12 - 0x34 - Value: 0x1234 ## DW_FORM_data2 - Value: 0x12345678 ## DW_FORM_data4 - Value: 0x123456789abcdef0 ## DW_FORM_data8 - CStr: abcd ## DW_FORM_string - BlockData: ## DW_FORM_block - 0x12 - 0x34 - BlockData: ## DW_FORM_block1 - 0x12 - 0x34 - Value: 0x12 ## DW_FORM_data1 - Value: 0x01 ## DW_FORM_flag - Value: 0x1234 ## DW_FORM_sdata - Value: 0x12345678 ## DW_FORM_strp - Value: 0x1234 ## DW_FORM_udata - Value: 0x12345678 ## DW_FORM_ref_addr - Value: 0x12 ## DW_FORM_ref1 - Value: 0x1234 ## DW_FORM_ref2 - Value: 0x12345678 ## DW_FORM_ref4 - Value: 0x123456789abcdef0 ## DW_FORM_ref8 - Value: 0x1234 ## DW_FORM_ref_udata - Value: 0x08 ## DW_FORM_indirect. The following value's form is 0x08, which is DW_FORM_string. - CStr: efgh - Value: 0x1234 ## DW_FORM_sec_offset - BlockData: ## DW_FORM_exprloc - 0x12 - 0x34 - Value: 0x1234 ## DW_FORM_strx - Value: 0x1234 ## DW_FORM_addrx - Value: 0x12345678 ## DW_FORM_ref_sup4 - Value: 0x12345678 ## DW_FORM_strp_sup - Value: 0x1234 ## DW_FORM_data16 (unimplemented) - Value: 0x12345678 ## DW_FORM_line_strp - Value: 0x123456789abcdef0 ## DW_FORM_ref_sig8 - Value: 0x1234 ## DW_FORM_implicit_const (unimplemented) - Value: 0x1234 ## DW_FORM_loclistx - Value: 0x1234 ## DW_FORM_rnglistx - Value: 0x123456789abcdef0 ## DW_FORM_ref_sup8 - Value: 0x12 ## DW_FORM_strx1 - Value: 0x1234 ## DW_FORM_strx2 - Value: 0x123456 ## DW_FORM_strx3 (unimplemented) - Value: 0x12345678 ## DW_FORM_strx4 - Value: 0x12 ## DW_FORM_addrx1 - Value: 0x1234 ## DW_FORM_addrx2 - Value: 0x123456 ## DW_FORM_addrx3 (unimplemented) - Value: 0x12345678 ## DW_FORM_addrx4 - Length: 0x1234 Version: 5 ## Test another unit type. UnitType: DW_UT_compile AbbrOffset: 0x1234 AddrSize: 4 Entries: - AbbrCode: 0 Values: [] - Length: 0x5678 ## Test DWARFv4 Version: 4 AbbrevTableID: 0 AbbrOffset: 0x5678 AddrSize: 4 Entries: - AbbrCode: 1 Values: - Value: 0x12345678 ## DW_FORM_addr - BlockData: ## DW_FORM_block2 - 0x12 - 0x34 ## Generate and verify a DWARF32 big endian .debug_info (DWARFv4) section. # RUN: yaml2obj --docnum=1 -DENDIAN=ELFDATA2MSB %s -o %t1.be.o # RUN: llvm-readobj --sections --section-data %t1.be.o \| \ # RUN: FileCheck -DINDEX=2 -DNAME=15 -DOFFSET=0x9B -DSIZE=179 -DADDRALIGN=1 %s --check-prefixes=SHDR,DWARF32-BE-CONTENT # DWARF32-BE-CONTENT-NEXT: SectionData ( # DWARF32-BE-CONTENT-NEXT: 0000: 00001234 00050204 00001234 01123456 ## ^------- unit_length (4-byte) ## ^--- version (2-byte) ## ^- unit_type (1-byte) DW_UT_type ## ^- address_size (1-byte) ## ^------- debug_abbrev_offset (4-byte) ## ^- abbreviation code (LEB128) 0x01 ## ^----- Form: DW_FORM_addr (4-byte) # DWARF32-BE-CONTENT-NEXT: 0010: 78000212 34000000 02123412 34123456 ## -- ## ^--- Form: DW_FORM_block2 size (2-byte) ## ^- ^- Form: DW_FORM_block2 body (2-byte) ## ^-------- Form: DW_FORM_block4 size (4-byte) ## ^-^- Form: DW_FORM_block4 body (2-byte) ## ^---- Form: DW_FORM_data2 (2-byte) ## ^----- Form: DW_FORM_data4 (4-byte) # DWARF32-BE-CONTENT-NEXT: 0020: 78123456 789ABCDE F0616263 64000212 ## -- ## ^----------------- Form: DW_FORM_data8 (8-byte) ## ^---------- Form: DW_FORM_string "abcd\0" ## ^- Form: DW_FORM_block size (ULEB128) ## ^- Form: DW_FORM_block body (2-byte) # DWARF32-BE-CONTENT-NEXT: 0030: 34021234 1201B424 12345678 B4241234 ## ^- Form: DW_FORM_block body ## ^- Form: DW_FORM_block1 size (1-byte) ## ^-^- Form: DW_FORM_block1 body (2-byte) ## ^- Form: DW_FORM_data1 (1-byte) ## ^- Form: DW_FORM_flag (1-byte) ## ^--- Form: DW_FORM_sdata (SLEB128) 0x1234 ## ^------- Form: DW_FORM_strp (4-byte) ## ^--- Form: DW_FORM_udata (ULEB128) 0x1234 ## ^--- Form: DW_FORM_ref_addr (4-byte) # DWARF32-BE-CONTENT-NEXT: 0040: 56781212 34123456 78123456 789ABCDE ## ---- ## ^- Form: DW_FORM_ref1 (1-byte) ## ^---- Form: DW_FORM_ref2 (2-byte) ## ^-------- Form: DW_FORM_ref4 (4-byte) ## ^-------------- Form: DW_FORM_ref8 (8-byte) # DWARF32-BE-CONTENT-NEXT: 0050: F0B42408 65666768 00000012 34021234 ## -- ## ^--- Form: DW_FORM_ref_udata (ULEB128) 0x1234 ## ^- Form: DW_FORM_indirect (ULEB128) DW_FORM_string ## ^---------- "efgh\0" ## ^-------- Form: DW_FORM_sec_offset (4-byte) ## ^- Form: DW_FORM_exprloc size (ULEB128) 0x02 ## ^-^- Form: DW_FORM_exprloc body (2-byte) # DWARF32-BE-CONTENT-NEXT: 0060: B424B424 12345678 12345678 12345678 ## ^--- Form: DW_FORM_strx (ULEB128) ## ^--- Form: DW_FORM_addrx (ULEB128) ## ^------- Form: DW_FORM_ref_sup4 (4-byte) ## ^------- Form: DW_FORM_strp_sup (4-byte) ## ^------- Form: DW_FORM_line_strp (4-byte) # DWARF32-BE-CONTENT-NEXT: 0070: 12345678 9ABCDEF0 B424B424 12345678 ## ^---------------- Form: DW_FORM_ref_sig8 (8-byte) ## ^--- Form: DW_FORM_loclistx (ULEB128) ## ^--- Form: DW_FORM_rnglistx (ULEB128) ## ^------- Form: DW_FORM_ref_sup8 (8-byte) # DWARF32-BE-CONTENT-NEXT: 0080: 9ABCDEF0 12123412 34567812 12341234 ## -------- ## ^- Form: DW_FORM_strx1 (1-byte) ## ^--- Form: DW_FORM_strx2 (2-byte) ## ^-------- Form: DW_FORM_strx4 (4-byte) ## ^- Form: DW_FORM_addrx1 (1-byte) ## ^--- Form: DW_FORM_addrx2 (1-byte) ## ^--- Form: DW_FORM_addrx4 (4-byte) # DWARF32-BE-CONTENT-NEXT: 0090: 56780000 12340005 01040000 12340000 ## ---- ## ^-------- unit_length (4-byte) ## ^--- version (2-byte) ## ^- unit_type (1-byte) ## ^- address_size (1-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- abbrev code (ULEB128) 0x00 ## ^- unit_length (4-byte) # DWARF32-BE-CONTENT-NEXT: 00A0: 00567800 04000056 78040112 34567800 ## ------ ## ^---- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) ## ^- abbrev code (ULEB128) 0x01 ## ^-------- Form: DW_FORM_addr ## ^- Form: DW_FORM_block2 size (2-byte) # DWARF32-BE-CONTENT-NEXT: 00B0: 021234 ## -- ## ^-^- Form: DW_FORM_block2 body (2-byte) # DWARF32-BE-CONTENT-NEXT: ) ## b) Generate the .debug_info section from raw section content. # RUN: yaml2obj --docnum=2 %s -o %t2.o # RUN: llvm-readobj --sections --section-data %t2.o \| \ # RUN: FileCheck -DINDEX=1 -DNAME=1 -DOFFSET=0x40 -DSIZE=3 -DADDRALIGN=0 %s --check-prefixes=SHDR,ARBITRARY-CONTENT # ARBITRARY-CONTENT-NEXT: SectionData ( # ARBITRARY-CONTENT-NEXT: 0000: 112233 # ARBITRARY-CONTENT-NEXT: ) --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC Sections: - Name: .debug_info Type: SHT_PROGBITS Content: "112233" ## c) Generate the .debug_info section when the "Size" is specified. # RUN: yaml2obj --docnum=3 %s -o %t3.o # RUN: llvm-readobj --sections --section-data %t3.o \| \ # RUN: FileCheck -DINDEX=1 -DNAME=1 -DOFFSET=0x40 -DSIZE=16 -DADDRALIGN=0 %s --check-prefixes=SHDR,SIZE # SIZE-NEXT: SectionData ( # SIZE-NEXT: 0000: 00000000 00000000 00000000 00000000 # SIZE-NEXT: ) --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC Sections: - Name: .debug_info Type: SHT_PROGBITS Size: 0x10 ## d) Test that yaml2obj emits an error message when both the "Size" and the ## "debug_info" entry are specified at the same time. # RUN: not yaml2obj --docnum=4 %s 2>&1 \| FileCheck %s --check-prefix=AMBIGUOUS-CONTENT # AMBIGUOUS-CONTENT: yaml2obj: error: cannot specify section '.debug_info' contents in the 'DWARF' entry and the 'Content' or 'Size' in the 'Sections' entry at the same time --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC Sections: - Name: .debug_info Type: SHT_PROGBITS Size: 0x10 DWARF: debug_abbrev: - Table: - Code: 1 Tag: DW_TAG_compile_unit Children: DW_CHILDREN_no debug_info: - Length: 0x1234 Version: 5 UnitType: DW_UT_type AbbrOffset: 0x1234 Entries: [] ## e) Test that yaml2obj emits an error message when both the "Content" and the ## "debug_info" entry are specified at the same time. # RUN: not yaml2obj --docnum=5 %s 2>&1 \| FileCheck %s --check-prefix=AMBIGUOUS-CONTENT --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC Sections: - Name: .debug_info Type: SHT_PROGBITS Content: "00" DWARF: debug_abbrev: - Table: - Code: 1 Tag: DW_TAG_compile_unit Children: DW_CHILDREN_no debug_info: - Length: 0x1234 Version: 5 UnitType: DW_UT_type AbbrOffset: 0x1234 Entries: [] ## f) Test that all the properties can be overridden by the section header when ## the "debug_info" entry doesn't exist. # RUN: yaml2obj --docnum=6 %s -o %t6.o # RUN: llvm-readelf --sections %t6.o \| FileCheck %s --check-prefix=OVERRIDDEN # OVERRIDDEN: [Nr] Name Type Address Off Size ES Flg Lk Inf Al # OVERRIDDEN: [ 1] .debug_info STRTAB 0000000000002020 000050 00000d 01 A 2 1 2 # OVERRIDDEN-NEXT: [ 2] .sec STRTAB 0000000000000000 00005d 000000 00 0 0 0 --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC Sections: - Name: .debug_info Type: SHT_STRTAB ## SHT_PROGBITS by default. Flags: [SHF_ALLOC] ## 0 by default. Link: .sec ## 0 by default. EntSize: 1 ## 0 by default. Info: 1 ## 0 by default. AddressAlign: 2 ## 0 by default. Address: 0x2020 ## 0x00 by default. Offset: 0x50 ## 0x40 for the first section. Size: 0x0d ## Set the "Size" so that we can reuse the check tag "OVERRIDDEN". - Name: .sec ## Linked by .debug_info. Type: SHT_STRTAB ## g) Test that all the properties can be overridden by the section header when ## the "debug_info" entry exists. # RUN: yaml2obj --docnum=7 %s -o %t7.o # RUN: llvm-readelf --sections %t7.o \| FileCheck %s --check-prefix=OVERRIDDEN --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC Sections: - Name: .debug_info Type: SHT_STRTAB ## SHT_PROGBITS by default. Flags: [SHF_ALLOC] ## 0 by default. Link: .sec ## 0 by default. EntSize: 1 ## 0 by default. Info: 1 ## 0 by default. AddressAlign: 2 ## 0 by default. Address: 0x2020 ## 0x00 by default. Offset: 0x50 ## 0x40 for the first section. - Name: .sec ## Linked by .debug_info. Type: SHT_STRTAB DWARF: debug_abbrev: - Table: - Code: 1 Tag: DW_TAG_compile_unit Children: DW_CHILDREN_no debug_info: - Length: 0x1234 Version: 5 UnitType: DW_UT_type AbbrOffset: 0x1234 Entries: - AbbrCode: 0 Values: [] ## h) Test that yaml2obj doesn't crash when the 'Entries' of a compilation unit is empty. # RUN: yaml2obj --docnum=8 %s -o %t8.o # RUN: llvm-readelf --hex-dump=.debug_info %t8.o \| \ # RUN: FileCheck %s --check-prefix=EMPTY-ENTRIES --match-full-lines # EMPTY-ENTRIES: Hex dump of section '.debug_info': # EMPTY-ENTRIES-NEXT: 0x00000000 34120000 05000204 34120000 4.......4... # EMPTY-ENTRIES-EMPTY: ## ^- 'Entries' is empty --- !ELF FileHeader: Class: ELFCLASS32 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_info: - Length: 0x1234 Version: 5 UnitType: DW_UT_type AbbrOffset: 0x1234 Entries: [] ## h) Test that yaml2obj emits values in the DIE according to the abbreviation whose ## index is equal to the value in 'AbbrevCode'. # RUN: yaml2obj --docnum=9 %s -o %t9.o # RUN: llvm-readelf --hex-dump=.debug_info %t9.o \| \ # RUN: FileCheck %s --check-prefix=FORM --match-full-lines # FORM: Hex dump of section '.debug_info': # FORM-NEXT: 0x00000000 34120000 05000204 34120000 02341221 4.......4....4.! ## ^------- unit_length (4-byte) ## ^- abbreviation code (ULEB128) ## ^--- Form: DW_FORM_data2 (2-byte) ## ^- Form: DW_FORM_data4 (4-byte) # FORM-NEXT: 0x00000010 43658701 21436587 341200 Ce..!Ce.4.. ## ------ ## ^- abbreviation code (ULEB128) ## ^------- Form: DW_FORM_data4 (4-byte) ## ^--- Form: DW_FORM_data2 (2-byte) ## ^- abbreviation code (ULEB128) # FORM-EMPTY: --- !ELF FileHeader: Class: ELFCLASS32 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_abbrev: - Table: - Tag: DW_TAG_compile_unit Children: DW_CHILDREN_yes Attributes: - Attribute: DW_AT_low_pc Form: DW_FORM_data4 - Attribute: DW_AT_high_pc Form: DW_FORM_data2 - Tag: DW_TAG_subprogram Children: DW_CHILDREN_no Attributes: - Attribute: DW_AT_low_pc Form: DW_FORM_data2 - Attribute: DW_AT_high_pc Form: DW_FORM_data4 debug_info: - Length: 0x1234 Version: 5 UnitType: DW_UT_type AbbrOffset: 0x1234 Entries: ## Test that yaml2obj emits values when the abbrev code is specified. - AbbrCode: 2 Values: - Value: 0x1234 - Value: 0x87654321 ## Test that yaml2obj emits values when the abbrev code is specified to ## be lower than the first abbrev. - AbbrCode: 1 Values: - Value: 0x87654321 - Value: 0x1234 ## Test that yaml2obj ignores the contents of entries with abbrev code 0. - AbbrCode: 0 Values: - Value: 0x1234 ## i) Test that yaml2obj reports an error when 'debug_info' has values in its ## entries but 'debug_abbrev' doesn't have enough attributes for them. # RUN: not yaml2obj --docnum=10 %s -o %t10.o 2>&1 \| \ # RUN: FileCheck %s --check-prefixes=ERROR # ERROR: yaml2obj: error: abbrev code must be less than or equal to the number of entries in abbreviation table --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_abbrev: - Table: [] debug_info: - Length: 0x1234 Version: 5 UnitType: DW_UT_type AbbrOffset: 0x1234 Entries: - AbbrCode: 1 Values: - Value: 0x1234 ## j) Test that yaml2obj emits the correct DWARF64 unit headers. ## DWARFv5 unit header. # RUN: yaml2obj --docnum=11 %s -o %t11.o # RUN: llvm-readelf --hex-dump=.debug_info %t11.o \| \ # RUN: FileCheck %s --check-prefix=DWARFV5-HEADER # DWARFV5-HEADER: Hex dump of section '.debug_info': # DWARFV5-HEADER-NEXT: 0x00000000 ffffffff 0c000000 00000000 05000208 ................ ## ^------------------------- unit_length (12-byte) ## ^--- version (2-byte) ## ^- unit_type (1-byte) ## ^- address_size (1-byte) # DWARFV5-HEADER-NEXT: 0x00000010 34120000 00000000 4....... ## ^---------------- debug_abbrev_offset (8-byte) --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_info: - Format: DWARF64 Length: 0x0c Version: 5 UnitType: DW_UT_type AbbrOffset: 0x1234 Entries: [] ## DWARFv4 unit header. # RUN: yaml2obj --docnum=12 %s -o %t12.o # RUN: llvm-readelf --hex-dump=.debug_info %t12.o \| \ # RUN: FileCheck %s --check-prefix=DWARFV4-HEADER # DWARFV4-HEADER: Hex dump of section '.debug_info': # DWARFV4-HEADER-NEXT: 0x00000000 ffffffff 0c000000 00000000 04003412 ..............4. ## ^------------------------- unit_length (12-byte) ## ^--- version (2-byte) ## ^--- debug_abbrev_offset (8-byte) # DWARFV4-HEADER-NEXT: 0x00000010 00000000 000008 ....... ## ------------- ## ^- address_size (1-byte) --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_info: - Format: DWARF64 Length: 0x0c Version: 4 AbbrOffset: 0x1234 Entries: [] ## k) Test that yaml2obj is able to emit a correct length for compilation units. # RUN: yaml2obj --docnum=13 %s -o %t13.o # RUN: llvm-readelf --hex-dump=.debug_info %t13.o \| \ # RUN: FileCheck %s --check-prefix=INFER-LENGTH # INFER-LENGTH: Hex dump of section '.debug_info': # INFER-LENGTH-NEXT: 0x00000000 37000000 04000000 00000801 00000000 7............... ## ^------- unit_length (0x37) ## ^--- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) ## ^- abbrev code (ULEB128) 0x01 ## ^------- Form: DW_FORM_strp (4-byte) # INFER-LENGTH-NEXT: 0x00000010 0c001600 00000000 00001e00 00002011 .............. . ## ^--- Form: DW_FORM_data2 (2-byte) ## ^-------- Form: DW_FORM_strp (4-byte) ## ^-------- Form: DW_FORM_sec_offset (4-byte) ## ^-------- Form: DW_FORM_strp (4-byte) ## ^--- Form: DW_FORM_addr (8-byte) # INFER-LENGTH-NEXT: 0x00000020 00000000 00003300 00000220 11000000 ......3.... .... ## ------------- ## ^-------- Form: DW_FORM_data4 (4-byte) ## ^- abbrev code (ULEB128) 0x02 ## ^---------- Form: DW_FORM_addr (8-byte) # INFER-LENGTH-NEXT: 0x00000030 00000006 00000038 000000 .......8... ## ------ ## ^-------- Form: DW_FORM_data4 (4-byte) ## ^-------- Form: DW_FORM_strp (4-byte) ## The handwritten DIEs should look like: ## 0x0000000b: DW_TAG_compile_unit [1] * ## DW_AT_producer [DW_FORM_strp] ( .debug_str[0x00000000] = "clang version 10.0.0 ") ## DW_AT_language [DW_FORM_data2] (DW_LANG_C99) ## DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000016] = "hello.c") ## DW_AT_stmt_list [DW_FORM_sec_offset] (0x00000000) ## DW_AT_comp_dir [DW_FORM_strp] ( .debug_str[0x0000001e] = "/home/v/x/llvm/playground") ## DW_AT_low_pc [DW_FORM_addr] (0x0000000000001120) ## DW_AT_high_pc [DW_FORM_data4] (0x00000033) ## ## 0x0000002a: DW_TAG_subprogram [2] ## DW_AT_low_pc [DW_FORM_addr] (0x0000000000001120) ## DW_AT_high_pc [DW_FORM_data4] (0x00000006) ## DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000038] = "main") --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_str: - "clang version 10.0.0 " - "hello.c" - "/home/v/x/llvm/playground" - "main" debug_abbrev: - Table: - Code: 1 Tag: DW_TAG_compile_unit Children: DW_CHILDREN_yes Attributes: - Attribute: DW_AT_producer Form: DW_FORM_strp - Attribute: DW_AT_language Form: DW_FORM_data2 - Attribute: DW_AT_name Form: DW_FORM_strp - Attribute: DW_AT_stmt_list Form: DW_FORM_sec_offset - Attribute: DW_AT_comp_dir Form: DW_FORM_strp - Attribute: DW_AT_low_pc Form: DW_FORM_addr - Attribute: DW_AT_high_pc Form: DW_FORM_data4 - Code: 2 Tag: DW_TAG_subprogram Children: DW_CHILDREN_no Attributes: - Attribute: DW_AT_low_pc Form: DW_FORM_addr - Attribute: DW_AT_high_pc Form: DW_FORM_data4 - Attribute: DW_AT_name Form: DW_FORM_strp debug_info: - Version: 4 AbbrOffset: 0x00 Entries: - AbbrCode: 1 Values: - Value: 0x00 ## DW_AT_producer [DW_FORM_strp] - Value: 0x0c ## DW_LANG_C99, DW_AT_language [DW_FORM_data2] - Value: 0x16 ## DW_AT_name [DW_FORM_strp] - Value: 0x00 ## DW_AT_stmt_list [DW_FORM_sec_offset] - Value: 0x1e ## DW_AT_comp_dir [DW_FORM_strp] - Value: 0x1120 ## DW_AT_low_pc [DW_FORM_addr] - Value: 0x33 ## DW_AT_high_pc [DW_FORM_data4] - AbbrCode: 2 Values: - Value: 0x1120 ## DW_AT_low_pc [DW_FORM_addr] - Value: 0x06 ## DW_AT_high_pc [DW_FORM_data4] - Value: 0x38 ## DW_AT_name [DW_FORM_strp] ## l) Test that if we don't specify the 'Values' key for an entry, yaml2obj will only emit the abbrev_code. # RUN: yaml2obj --docnum=14 %s -o %t14.o # RUN: llvm-readelf --hex-dump=.debug_info %t14.o \| \ # RUN: FileCheck %s --check-prefix=NO-VALUES # NO-VALUES: Hex dump of section '.debug_info': # NO-VALUES-NEXT: 0x00000000 0a000000 04000000 00000801 0002 .............. ## ^------- unit_length (4-byte) ## ^--- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) ## ^- abbrev_code (ULEB128) 0x01 ## ^- abbrev_code (ULEB128) 0x00 ## ^- abbrev_code (ULEB128) 0x02 --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_info: - Version: 4 AbbrOffset: 0x00 Entries: - AbbrCode: 1 - AbbrCode: 0 - AbbrCode: 2 ## m) Test that yaml2obj is able to infer the address size from the object file. # RUN: yaml2obj --docnum=15 -DBITS=64 %s -o %t15.64-bit.o # RUN: llvm-readelf --hex-dump=.debug_info %t15.64-bit.o \| \ # RUN: FileCheck %s --check-prefix=ADDRSIZE -DADDRSIZE=08 # ADDRSIZE: Hex dump of section '.debug_info': # ADDRSIZE-NEXT: 0x00000000 07000000 04000000 0000[[ADDRSIZE]] ........... # RUN: yaml2obj --docnum=15 -DBITS=32 %s -o %t15.32-bit.o # RUN: llvm-readelf --hex-dump=.debug_info %t15.32-bit.o \| \ # RUN: FileCheck %s --check-prefix=ADDRSIZE -DADDRSIZE=04 --- !ELF FileHeader: Class: ELFCLASS[[BITS]] Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_info: - Version: 4 AbbrOffset: 0x00 ## n) Test that yaml2obj emits an error message when a compilation unit has values but there is no associated abbrev table. ## RUN: not yaml2obj --docnum=16 %s 2>&1 \| FileCheck %s --check-prefix=NO-ABBREV # NO-ABBREV: yaml2obj: error: cannot find abbrev table whose ID is 0 for compilation unit with index 0 --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC Machine: EM_X86_64 DWARF: debug_info: - Version: 4 AbbrOffset: 0x00 Entries: - AbbrCode: 1 Values: - Value: 0x1234 ## o) Test that yaml2obj is able to generate compilation units according to the ## associated abbrev table that is referenced by the 'AbbrevTableID' and infer ## the value of the debug_abbrev_offset field. # RUN: yaml2obj --docnum=17 %s -o %t17.o # RUN: llvm-readelf --hex-dump=.debug_info %t17.o \| FileCheck %s --check-prefix=MULTI-TABLES # MULTI-TABLES: Hex dump of section '.debug_info': # MULTI-TABLES-NEXT: 0x00000000 0c000000 04000800 00000801 34120000 ............4... ## ^------- unit_length (4-byte) ## ^--- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) ## ^- abbrev_code (ULEB128) 0x01 ## ^------- Form: DW_FORM_data4 (4-byte) 0x1234 # MULTI-TABLES-NEXT: 0x00000010 0c000000 04000800 00000801 21430000 ............!C.. ## ^------- unit_length (4-byte) ## ^--- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) ## ^- abbrev_code (ULEB128) 0x01 ## ^------- Form: DW_FORM_data4 (4-byte) 0x4321 # MULTI-TABLES-NEXT: 0x00000020 10000000 04000000 00000801 78560000 ............xV.. ## ^------- unit_length (4-byte) ## ^--- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) ## ^- abbrev_code (ULEB128) 0x01 ## ^------- Form: DW_FORM_addr (8-byte) 0x5678 # MULTI-TABLES-NEXT: 0x00000030 00000000 0b000000 04001000 00000801 ................ ## -------- ## ^------- unit_length (4-byte) ## ^--- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) ## ^- abbrev_code (ULEB128) 0x01 # MULTI-TABLES-NEXT: 0x00000040 e58e02 ... ## ^----- Form: DW_FORM_udata (ULEB128) 0x8765 --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_abbrev: - Table: - Code: 1 Tag: DW_TAG_compile_unit Children: DW_CHILDREN_no Attributes: - Attribute: DW_AT_low_pc Form: DW_FORM_addr - ID: 2 Table: - Code: 1 Tag: DW_TAG_compile_unit Children: DW_CHILDREN_no Attributes: - Attribute: DW_AT_low_pc Form: DW_FORM_data4 - ID: 1 Table: - Code: 1 Tag: DW_TAG_compile_unit Children: DW_CHILDREN_no Attributes: - Attribute: DW_AT_low_pc Form: DW_FORM_udata debug_info: - Version: 4 AbbrevTableID: 2 Entries: - AbbrCode: 1 Values: - Value: 0x1234 - Version: 4 AbbrevTableID: 2 Entries: - AbbrCode: 1 Values: - Value: 0x4321 - Version: 4 AbbrevTableID: 0 Entries: - AbbrCode: 1 Values: - Value: 0x5678 - Version: 4 AbbrevTableID: 1 Entries: - AbbrCode: 1 Values: - Value: 0x8765 ## p) Test that when the debug_abbrev_offset field isn't specified and there is no associated ## abbrev table, yaml2obj will assign 0 to the debug_abbrev_offset field. # RUN: yaml2obj --docnum=18 %s -o %t18.o # RUN: llvm-readelf --hex-dump=.debug_info %t18.o \| FileCheck %s --check-prefix=ZERO-OFFSET # ZERO-OFFSET: Hex dump of section '.debug_info': # ZERO-OFFSET-NEXT: 0x00000000 07000000 04000000 000008 ........... ## ^------- unit_length (4-byte) ## ^--- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_info: - Version: 4 AbbrevTableID: [[ABBREVID=<none>]] ## q) Test that when we assign an invalid 'AbbrevTableID' that doesn't point to an abbrev table, ## yaml2obj will assign 0 to the debug_abbrev_offset field. # RUN: yaml2obj --docnum=18 -DABBREVID=2 %s -o %t18.o # RUN: llvm-readelf --hex-dump=.debug_info %t18.o \| FileCheck %s --check-prefix=ZERO-OFFSET	{ "language": "Assembly" }
.set LOCALID_STEVEN, 3 .set LOCALID_ARCHIE, 4 .set LOCALID_MAXIE, 5 Route128_MapScripts:: @ 81F6B38 map_script MAP_SCRIPT_ON_TRANSITION, Route128_OnTransition map_script MAP_SCRIPT_ON_FRAME_TABLE, Route128_OnFrame .byte 0 Route128_OnTransition: @ 81F6B43 call_if_set FLAG_SYS_WEATHER_CTRL, Common_EventScript_SetAbnormalWeather end Route128_OnFrame: @ 81F6B4D map_script_2 VAR_ROUTE128_STATE, 1, Route128_EventScript_KyogreAwakenedScene .2byte 0 Route128_EventScript_KyogreAwakenedScene:: @ 81F6B57 lockall delay 20 applymovement LOCALID_ARCHIE, Route128_Movement_ArchieLookAround waitmovement 0 msgbox Route128_Text_ArchieWhatHappened, MSGBOX_DEFAULT closemessage applymovement LOCALID_ARCHIE, Route128_Movement_ArchieBackUp waitmovement 0 msgbox Route128_Text_ArchieIOnlyWanted, MSGBOX_DEFAULT closemessage applymovement LOCALID_MAXIE, Route128_Movement_MaxieApproachArchie waitmovement 0 applymovement LOCALID_ARCHIE, Common_Movement_WalkInPlaceFastestUp waitmovement 0 msgbox Route128_Text_MaxieDoYouUnderstandNow, MSGBOX_DEFAULT closemessage applymovement LOCALID_MAXIE, Route128_Movement_MaxieApproachPlayer waitmovement 0 applymovement OBJ_EVENT_ID_PLAYER, Common_Movement_WalkInPlaceFastestUp waitmovement 0 msgbox Route128_Text_MaxieResposibilityFallsToArchieAndMe, MSGBOX_DEFAULT closemessage applymovement LOCALID_ARCHIE, Route128_Movement_ArchieRunLeft applymovement OBJ_EVENT_ID_PLAYER, Common_Movement_WalkInPlaceFastestLeft applymovement LOCALID_MAXIE, Route128_Movement_MaxieWalkLeft waitmovement 0 msgbox Route128_Text_MaxieThisDefiesBelief, MSGBOX_DEFAULT closemessage delay 40 applymovement LOCALID_MAXIE, Route128_Movement_MaxieExit applymovement LOCALID_ARCHIE, Route128_Movement_ArchieExit waitmovement 0 removeobject LOCALID_MAXIE removeobject LOCALID_ARCHIE delay 100 setfieldeffectargument 0, 1 dofieldeffect FLDEFF_NPCFLY_OUT waitfieldeffect FLDEFF_NPCFLY_OUT addobject LOCALID_STEVEN applymovement LOCALID_STEVEN, Route128_Movement_StevenApproachPlayer waitmovement 0 applymovement OBJ_EVENT_ID_PLAYER, Common_Movement_WalkInPlaceFastestRight waitmovement 0 msgbox Route128_Text_StevenWhatIsHappening, MSGBOX_DEFAULT closemessage applymovement LOCALID_STEVEN, Route128_Movement_StevenWalkUp applymovement OBJ_EVENT_ID_PLAYER, Common_Movement_WalkInPlaceFastestUp waitmovement 0 msgbox Route128_Text_StevenWholeWorldWillDrown, MSGBOX_DEFAULT applymovement LOCALID_STEVEN, Common_Movement_WalkInPlaceFastestDown waitmovement 0 msgbox Route128_Text_StevenImGoingToSootopolis, MSGBOX_DEFAULT closemessage applymovement LOCALID_STEVEN, Common_Movement_WalkInPlaceFastestDown waitmovement 0 delay 50 setfieldeffectargument 0, 1 dofieldeffect FLDEFF_NPCFLY_OUT delay 15 removeobject LOCALID_STEVEN waitfieldeffect FLDEFF_NPCFLY_OUT clearflag FLAG_HIDE_MAP_NAME_POPUP setvar VAR_ROUTE128_STATE, 2 releaseall end Route128_Movement_Unused1: @ 81F6C76 walk_fast_left step_end Route128_Movement_Unused2: @ 81F6C78 walk_left walk_left walk_left walk_left walk_left walk_left walk_up walk_up walk_up walk_up walk_up walk_up step_end Route128_Movement_StevenWalkUp: @ 81F6C85 walk_up step_end Route128_Movement_StevenApproachPlayer: @ 81F6C87 walk_fast_left step_end Route128_Movement_ArchieLookAround: @ 81F6C89 walk_fast_down walk_in_place_fastest_left delay_16 walk_in_place_fastest_right delay_16 delay_16 walk_in_place_fastest_down step_end Route128_Movement_ArchieBackUp: @ 81F6C91 lock_facing_direction walk_slow_up delay_16 unlock_facing_direction step_end Route128_Movement_ArchieRunLeft: @ 81F6C96 walk_fast_left walk_fast_left walk_fast_left walk_in_place_fastest_right step_end Route128_Movement_ArchieExit: @ 81F6C9B delay_16 delay_16 walk_fast_up walk_fast_left walk_fast_up walk_fast_up walk_fast_up walk_fast_up walk_fast_up walk_fast_up walk_fast_up walk_fast_up step_end Route128_Movement_MaxieWalkLeft: @ 81F6CA8 walk_left walk_left delay_8 delay_4 step_end Route128_Movement_MaxieApproachArchie: @ 81F6CAD walk_left walk_in_place_fastest_down step_end Route128_Movement_MaxieExit: @ 81F6CB0 walk_fast_left walk_fast_left walk_fast_left walk_fast_up walk_fast_up walk_fast_up walk_fast_up walk_fast_up walk_fast_up walk_fast_up step_end Route128_Movement_MaxieApproachPlayer: @ 81F6CBB walk_right walk_in_place_fastest_down step_end Route128_EventScript_Isaiah:: @ 81F6CBE trainerbattle_single TRAINER_ISAIAH_1, Route128_Text_IsaiahIntro, Route128_Text_IsaiahDefeat, Route128_EventScript_RegisterIsaiah specialvar VAR_RESULT, ShouldTryRematchBattle compare VAR_RESULT, TRUE goto_if_eq Route128_EventScript_RematchIsaiah msgbox Route128_Text_IsaiahPostBattle, MSGBOX_DEFAULT release end Route128_EventScript_RegisterIsaiah:: @ 81F6CEA special PlayerFaceTrainerAfterBattle waitmovement 0 msgbox Route128_Text_IsaiahRegister, MSGBOX_DEFAULT register_matchcall TRAINER_ISAIAH_1 release end Route128_EventScript_RematchIsaiah:: @ 81F6D09 trainerbattle_rematch TRAINER_ISAIAH_1, Route128_Text_IsaiahRematchIntro, Route128_Text_IsaiahRematchDefeat msgbox Route128_Text_IsaiahPostRematch, MSGBOX_AUTOCLOSE end Route128_EventScript_Katelyn:: @ 81F6D20 trainerbattle_single TRAINER_KATELYN_1, Route128_Text_KatelynIntro, Route128_Text_KatelynDefeat, Route128_EventScript_RegisterKatelyn specialvar VAR_RESULT, ShouldTryRematchBattle compare VAR_RESULT, TRUE goto_if_eq Route128_EventScript_RematchKatelyn msgbox Route128_Text_KatelynPostBattle, MSGBOX_DEFAULT release end Route128_EventScript_RegisterKatelyn:: @ 81F6D4C special PlayerFaceTrainerAfterBattle waitmovement 0 msgbox Route128_Text_KatelynRegister, MSGBOX_DEFAULT register_matchcall TRAINER_KATELYN_1 release end Route128_EventScript_RematchKatelyn:: @ 81F6D6B trainerbattle_rematch TRAINER_KATELYN_1, Route128_Text_KatelynRematchIntro, Route128_Text_KatelynRematchDefeat msgbox Route128_Text_KatelynPostRematch, MSGBOX_AUTOCLOSE end Route128_EventScript_Alexa:: @ 81F6D82 trainerbattle_single TRAINER_ALEXA, Route128_Text_AlexaIntro, Route128_Text_AlexaDefeat msgbox Route128_Text_AlexaPostBattle, MSGBOX_AUTOCLOSE end Route128_EventScript_Ruben:: @ 81F6D99 trainerbattle_single TRAINER_RUBEN, Route128_Text_RubenIntro, Route128_Text_RubenDefeat msgbox Route128_Text_RubenPostBattle, MSGBOX_AUTOCLOSE end Route128_EventScript_Wayne:: @ 81F6DB0 trainerbattle_single TRAINER_WAYNE, Route128_Text_WayneIntro, Route128_Text_WayneDefeat msgbox Route128_Text_WaynePostBattle, MSGBOX_AUTOCLOSE end Route128_EventScript_Harrison:: @ 81F6DC7 trainerbattle_single TRAINER_HARRISON, Route128_Text_HarrisonIntro, Route128_Text_HarrisonDefeat msgbox Route128_Text_HarrisonPostBattle, MSGBOX_AUTOCLOSE end Route128_EventScript_Carlee:: @ 81F6DDE trainerbattle_single TRAINER_CARLEE, Route128_Text_CarleeIntro, Route128_Text_CarleeDefeat msgbox Route128_Text_CarleePostBattle, MSGBOX_AUTOCLOSE end Route128_Text_ArchieWhatHappened: @ 81F6DF5 .string "ARCHIE: What happened…\n" .string "What is this wretched scene…\p" .string "Did I…make a horrible mistake?$" Route128_Text_ArchieIOnlyWanted: @ 81F6E48 .string "I…\n" .string "I only wanted…$" Route128_Text_MaxieDoYouUnderstandNow: @ 81F6E5A .string "MAXIE: Do you understand now,\n" .string "ARCHIE?\p" .string "Do you finally see how disastrous\n" .string "your dream turned out to be?\p" .string "We have to hurry! We have to do\n" .string "something before the situation goes\l" .string "completely out of control!$" Route128_Text_MaxieResposibilityFallsToArchieAndMe: @ 81F6F1E .string "MAXIE: {PLAYER}, don't say anything.\p" .string "I know that I have no right to be\n" .string "critical of ARCHIE…\p" .string "But the way things are now, I doubt\n" .string "that we humans will be capable of\l" .string "doing anything about it.\p" .string "But neither can we stand by and\n" .string "just watch helplessly.\p" .string "The responsibility for putting an end\n" .string "to this falls to ARCHIE and me…$" Route128_Text_MaxieThisDefiesBelief: @ 81F704F .string "MAXIE: This defies belief…\p" .string "Those super-ancient POKéMON…\p" .string "Their power is unbelievable.\n" .string "They've upset the balance of nature…$" Route128_Text_StevenWhatIsHappening: @ 81F70C9 .string "STEVEN: {PLAYER}{KUN}!\n" .string "What is happening?$" Route128_Text_StevenWholeWorldWillDrown: @ 81F70EA .string "This is terrible…\p" .string "After the scorching heat wave ended,\n" .string "this deluge began.\p" .string "If this doesn't stop, all of HOENN…\n" .string "No, the whole world will drown.\p" .string "This huge rain cloud is spreading\n" .string "from above SOOTOPOLIS…\p" .string "What in the world is taking place there?\p" .string "There's no point arguing here…\n" .string "SOOTOPOLIS might provide answers…$" Route128_Text_StevenImGoingToSootopolis: @ 81F721B .string "{PLAYER}{KUN}…\n" .string "I don't know what you intend to do,\l" .string "but don't do anything reckless.\p" .string "Okay.\n" .string "I'm going to SOOTOPOLIS.$"	{ "language": "Assembly" }
// RUN: echo "fun:foo" > %t.never-instrument // RUN: echo "src:xray-never-instrument.cpp" >> %t.never-instrument // RUN: echo "[never]" > %t.xray-attrlist // RUN: echo "fun:foo" >> %t.xray-attrlist // RUN: echo "src:xray-never-instrument.cpp" >> %t.xray-attrlist // RUN: %clang_cc1 -fxray-instrument -x c++ -std=c++11 \ // RUN: -fxray-never-instrument=%t.never-instrument -emit-llvm -o - %s \ // RUN: -triple x86_64-unknown-linux-gnu \| FileCheck %s // RUN: %clang_cc1 -fxray-instrument -x c++ -std=c++11 \ // RUN: -fxray-attr-list=%t.xray-attrlist -emit-llvm -o - %s \ // RUN: -triple x86_64-unknown-linux-gnu \| FileCheck %s void foo() {} [[clang::xray_always_instrument]] void bar() {} void baz() {} // CHECK: define void @_Z3foov() #[[NEVERATTR:[0-9]+]] { // CHECK: define void @_Z3barv() #[[ALWAYSATTR:[0-9]+]] { // CHECK: define void @_Z3bazv() #[[NEVERATTR:[0-9]+]] { // CHECK: attributes #[[NEVERATTR]] = {{.}} "function-instrument"="xray-never" {{.}} // CHECK: attributes #[[ALWAYSATTR]] = {{.}} "function-instrument"="xray-always" {{.}}	{ "language": "Assembly" }
# RUN: llvm-mc -triple=hexagon -disassemble < %s 2>&1 \| FileCheck %s #CHECK: warning: invalid instruction encoding 0x00 0x80 0x00 0x7f 0x00 0x80 0x00 0x7f 0x00 0x80 0x00 0x7f 0x00 0xc0 0x00 0x7f	{ "language": "Assembly" }
# Automatically Generated: do not edit this file # autoscan's mapping to Autoconf macros -- Makefile -- # Copyright (C) 1992, 1993, 1994, 1996, 1999, 2000, 2001, 2002, 2009 # Free Software Foundation, Inc. # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation, either version 3 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program. If not, see <http://www.gnu.org/licenses/>. function: __argz_count AC_CHECK_FUNCS function: __argz_next AC_CHECK_FUNCS function: __argz_stringify AC_CHECK_FUNCS function: __fpending AC_CHECK_FUNCS function: acl AC_CHECK_FUNCS function: alarm AC_CHECK_FUNCS function: alloca AC_FUNC_ALLOCA function: atexit AC_CHECK_FUNCS function: btowc AC_CHECK_FUNCS function: bzero AC_CHECK_FUNCS function: chown AC_FUNC_CHOWN function: clock_gettime AC_CHECK_FUNCS function: dcgettext AM_GNU_GETTEXT function: doprnt AC_CHECK_FUNCS function: dup2 AC_CHECK_FUNCS function: endgrent AC_CHECK_FUNCS function: endpwent AC_CHECK_FUNCS function: error AC_FUNC_ERROR_AT_LINE function: error_at_line AC_FUNC_ERROR_AT_LINE function: euidaccess AC_CHECK_FUNCS function: fchdir AC_CHECK_FUNCS function: fdatasync AC_CHECK_FUNCS function: fesetround AC_CHECK_FUNCS function: floor AC_CHECK_FUNCS function: fork AC_FUNC_FORK function: fs_stat_dev AC_CHECK_FUNCS function: fseeko AC_FUNC_FSEEKO function: ftello AC_FUNC_FSEEKO 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function: strtoumax AC_CHECK_FUNCS function: strverscmp AC_CHECK_FUNCS function: sysinfo AC_CHECK_FUNCS function: tzset AC_CHECK_FUNCS function: uname AC_CHECK_FUNCS function: utime AC_CHECK_FUNCS function: utmpname AC_CHECK_FUNCS function: utmpxname AC_CHECK_FUNCS function: vfork AC_FUNC_FORK function: wait3 AC_FUNC_WAIT3 function: wcwidth AC_CHECK_FUNCS header: OS.h AC_CHECK_HEADERS header: X11/Xlib.h AC_PATH_X header: alloca.h AC_FUNC_ALLOCA header: argz.h AC_CHECK_HEADERS header: arpa/inet.h AC_CHECK_HEADERS header: fcntl.h AC_CHECK_HEADERS header: fenv.h AC_CHECK_HEADERS header: float.h AC_CHECK_HEADERS header: fs_info.h AC_CHECK_HEADERS header: inttypes.h AC_CHECK_HEADERS header: langinfo.h AC_CHECK_HEADERS header: libintl.h AC_CHECK_HEADERS header: limits.h AC_CHECK_HEADERS header: locale.h AC_CHECK_HEADERS header: mach/mach.h AC_CHECK_HEADERS header: malloc.h AC_CHECK_HEADERS header: memory.h AC_CHECK_HEADERS header: mntent.h AC_CHECK_HEADERS header: mnttab.h AC_CHECK_HEADERS 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AC_CHECK_HEADERS header: sys/systeminfo.h AC_CHECK_HEADERS header: sys/time.h AC_CHECK_HEADERS header: sys/timeb.h AC_CHECK_HEADERS header: sys/vfs.h AC_CHECK_HEADERS header: sys/window.h AC_CHECK_HEADERS header: syslog.h AC_CHECK_HEADERS header: termio.h AC_CHECK_HEADERS header: termios.h AC_CHECK_HEADERS header: unistd.h AC_CHECK_HEADERS header: utime.h AC_CHECK_HEADERS header: utmp.h AC_CHECK_HEADERS header: utmpx.h AC_CHECK_HEADERS header: values.h AC_CHECK_HEADERS header: wchar.h AC_CHECK_HEADERS header: wctype.h AC_CHECK_HEADERS identifier: bool AC_HEADER_STDBOOL identifier: false AC_HEADER_STDBOOL identifier: gid_t AC_TYPE_UID_T identifier: inline AC_C_INLINE identifier: int16_t AC_TYPE_INT16_T identifier: int32_t AC_TYPE_INT32_T identifier: int64_t AC_TYPE_INT64_T identifier: int8_t AC_TYPE_INT8_T identifier: mode_t AC_TYPE_MODE_T identifier: obstack AC_FUNC_OBSTACK identifier: off_t AC_TYPE_OFF_T identifier: pid_t AC_TYPE_PID_T identifier: ptrdiff_t AC_CHECK_TYPES identifier: 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AC_PROG_CXX program: awk AC_PROG_AWK program: bison AC_PROG_YACC program: byacc AC_PROG_YACC program: c++ AC_PROG_CXX program: cc AC_PROG_CC program: cpp AC_PROG_CPP program: flex AC_PROG_LEX program: g++ AC_PROG_CXX program: gawk AC_PROG_AWK program: gcc AC_PROG_CC program: install AC_PROG_INSTALL program: lex AC_PROG_LEX program: ln AC_PROG_LN_S program: make AC_PROG_MAKE_SET program: mawk AC_PROG_AWK program: nawk AC_PROG_AWK program: objc AC_PROG_OBJC program: objcc AC_PROG_OBJC program: objcxx AC_PROG_OBJCXX program: ranlib AC_PROG_RANLIB program: yacc AC_PROG_YACC	{ "language": "Assembly" }
// Copyright 2016 Adrien Descamps // Distributed under BSD 3-Clause License /* You need to define the following macros before including this file: SSE_FUNCTION_NAME STD_FUNCTION_NAME YUV_FORMAT RGB_FORMAT / / You may define the following macro, which affects generated code: SSE_ALIGNED / #ifdef SSE_ALIGNED / Unaligned instructions seem faster, even on aligned data? / / #define LOAD_SI128 _mm_load_si128 #define SAVE_SI128 _mm_stream_si128 / #define LOAD_SI128 _mm_loadu_si128 #define SAVE_SI128 _mm_storeu_si128 #else #define LOAD_SI128 _mm_loadu_si128 #define SAVE_SI128 _mm_storeu_si128 #endif #define UV2RGB_16(U,V,R1,G1,B1,R2,G2,B2) \ r_tmp = _mm_mullo_epi16(V, _mm_set1_epi16(param->v_r_factor)); \ g_tmp = _mm_add_epi16( \ _mm_mullo_epi16(U, _mm_set1_epi16(param->u_g_factor)), \ _mm_mullo_epi16(V, _mm_set1_epi16(param->v_g_factor))); \ b_tmp = _mm_mullo_epi16(U, _mm_set1_epi16(param->u_b_factor)); \ R1 = _mm_unpacklo_epi16(r_tmp, r_tmp); \ G1 = _mm_unpacklo_epi16(g_tmp, g_tmp); \ B1 = _mm_unpacklo_epi16(b_tmp, b_tmp); \ R2 = _mm_unpackhi_epi16(r_tmp, r_tmp); \ G2 = _mm_unpackhi_epi16(g_tmp, g_tmp); \ B2 = _mm_unpackhi_epi16(b_tmp, b_tmp); \ #define ADD_Y2RGB_16(Y1,Y2,R1,G1,B1,R2,G2,B2) \ Y1 = _mm_mullo_epi16(_mm_sub_epi16(Y1, _mm_set1_epi16(param->y_shift)), _mm_set1_epi16(param->y_factor)); \ Y2 = _mm_mullo_epi16(_mm_sub_epi16(Y2, _mm_set1_epi16(param->y_shift)), _mm_set1_epi16(param->y_factor)); \ \ R1 = _mm_srai_epi16(_mm_add_epi16(R1, Y1), PRECISION); \ G1 = _mm_srai_epi16(_mm_add_epi16(G1, Y1), PRECISION); \ B1 = _mm_srai_epi16(_mm_add_epi16(B1, Y1), PRECISION); \ R2 = _mm_srai_epi16(_mm_add_epi16(R2, Y2), PRECISION); \ G2 = _mm_srai_epi16(_mm_add_epi16(G2, Y2), PRECISION); \ B2 = _mm_srai_epi16(_mm_add_epi16(B2, Y2), PRECISION); \ #define PACK_RGB565_32(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4) \ { \ __m128i red_mask, tmp1, tmp2, tmp3, tmp4; \ \ red_mask = _mm_set1_epi16((short)0xF800); \ RGB1 = _mm_and_si128(_mm_unpacklo_epi8(_mm_setzero_si128(), R1), red_mask); \ RGB2 = _mm_and_si128(_mm_unpackhi_epi8(_mm_setzero_si128(), R1), red_mask); \ RGB3 = _mm_and_si128(_mm_unpacklo_epi8(_mm_setzero_si128(), R2), red_mask); \ RGB4 = _mm_and_si128(_mm_unpackhi_epi8(_mm_setzero_si128(), R2), red_mask); \ tmp1 = _mm_slli_epi16(_mm_srli_epi16(_mm_unpacklo_epi8(G1, _mm_setzero_si128()), 2), 5); \ tmp2 = _mm_slli_epi16(_mm_srli_epi16(_mm_unpackhi_epi8(G1, _mm_setzero_si128()), 2), 5); \ tmp3 = _mm_slli_epi16(_mm_srli_epi16(_mm_unpacklo_epi8(G2, _mm_setzero_si128()), 2), 5); \ tmp4 = _mm_slli_epi16(_mm_srli_epi16(_mm_unpackhi_epi8(G2, _mm_setzero_si128()), 2), 5); \ RGB1 = _mm_or_si128(RGB1, tmp1); \ RGB2 = _mm_or_si128(RGB2, tmp2); \ RGB3 = _mm_or_si128(RGB3, tmp3); \ RGB4 = _mm_or_si128(RGB4, tmp4); \ tmp1 = _mm_srli_epi16(_mm_unpacklo_epi8(B1, _mm_setzero_si128()), 3); \ tmp2 = _mm_srli_epi16(_mm_unpackhi_epi8(B1, _mm_setzero_si128()), 3); \ tmp3 = _mm_srli_epi16(_mm_unpacklo_epi8(B2, _mm_setzero_si128()), 3); \ tmp4 = _mm_srli_epi16(_mm_unpackhi_epi8(B2, _mm_setzero_si128()), 3); \ RGB1 = _mm_or_si128(RGB1, tmp1); \ RGB2 = _mm_or_si128(RGB2, tmp2); \ RGB3 = _mm_or_si128(RGB3, tmp3); \ RGB4 = _mm_or_si128(RGB4, tmp4); \ } #define PACK_RGB24_32_STEP1(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6) \ RGB1 = _mm_packus_epi16(_mm_and_si128(R1,_mm_set1_epi16(0xFF)), _mm_and_si128(R2,_mm_set1_epi16(0xFF))); \ RGB2 = _mm_packus_epi16(_mm_and_si128(G1,_mm_set1_epi16(0xFF)), _mm_and_si128(G2,_mm_set1_epi16(0xFF))); \ RGB3 = _mm_packus_epi16(_mm_and_si128(B1,_mm_set1_epi16(0xFF)), _mm_and_si128(B2,_mm_set1_epi16(0xFF))); \ RGB4 = _mm_packus_epi16(_mm_srli_epi16(R1,8), _mm_srli_epi16(R2,8)); \ RGB5 = _mm_packus_epi16(_mm_srli_epi16(G1,8), _mm_srli_epi16(G2,8)); \ RGB6 = _mm_packus_epi16(_mm_srli_epi16(B1,8), _mm_srli_epi16(B2,8)); \ #define PACK_RGB24_32_STEP2(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6) \ R1 = _mm_packus_epi16(_mm_and_si128(RGB1,_mm_set1_epi16(0xFF)), _mm_and_si128(RGB2,_mm_set1_epi16(0xFF))); \ R2 = _mm_packus_epi16(_mm_and_si128(RGB3,_mm_set1_epi16(0xFF)), _mm_and_si128(RGB4,_mm_set1_epi16(0xFF))); \ G1 = _mm_packus_epi16(_mm_and_si128(RGB5,_mm_set1_epi16(0xFF)), _mm_and_si128(RGB6,_mm_set1_epi16(0xFF))); \ G2 = _mm_packus_epi16(_mm_srli_epi16(RGB1,8), _mm_srli_epi16(RGB2,8)); \ B1 = _mm_packus_epi16(_mm_srli_epi16(RGB3,8), _mm_srli_epi16(RGB4,8)); \ B2 = _mm_packus_epi16(_mm_srli_epi16(RGB5,8), _mm_srli_epi16(RGB6,8)); \ #define PACK_RGB24_32(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6) \ PACK_RGB24_32_STEP1(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6) \ PACK_RGB24_32_STEP2(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6) \ PACK_RGB24_32_STEP1(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6) \ PACK_RGB24_32_STEP2(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6) \ PACK_RGB24_32_STEP1(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6) \ #define PACK_RGBA_32(R1, R2, G1, G2, B1, B2, A1, A2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6, RGB7, RGB8) \ { \ __m128i lo_ab, hi_ab, lo_gr, hi_gr; \ \ lo_ab = _mm_unpacklo_epi8( A1, B1 ); \ hi_ab = _mm_unpackhi_epi8( A1, B1 ); \ lo_gr = _mm_unpacklo_epi8( G1, R1 ); \ hi_gr = _mm_unpackhi_epi8( G1, R1 ); \ RGB1 = _mm_unpacklo_epi16( lo_ab, lo_gr ); \ RGB2 = _mm_unpackhi_epi16( lo_ab, lo_gr ); \ RGB3 = _mm_unpacklo_epi16( hi_ab, hi_gr ); \ RGB4 = _mm_unpackhi_epi16( hi_ab, hi_gr ); \ \ lo_ab = _mm_unpacklo_epi8( A2, B2 ); \ hi_ab = _mm_unpackhi_epi8( A2, B2 ); \ lo_gr = _mm_unpacklo_epi8( G2, R2 ); \ hi_gr = _mm_unpackhi_epi8( G2, R2 ); \ RGB5 = _mm_unpacklo_epi16( lo_ab, lo_gr ); \ RGB6 = _mm_unpackhi_epi16( lo_ab, lo_gr ); \ RGB7 = _mm_unpacklo_epi16( hi_ab, hi_gr ); \ RGB8 = _mm_unpackhi_epi16( hi_ab, hi_gr ); \ } #if RGB_FORMAT == RGB_FORMAT_RGB565 #define PACK_PIXEL \ __m128i rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8; \ \ PACK_RGB565_32(r_8_11, r_8_12, g_8_11, g_8_12, b_8_11, b_8_12, rgb_1, rgb_2, rgb_3, rgb_4) \ \ PACK_RGB565_32(r_8_21, r_8_22, g_8_21, g_8_22, b_8_21, b_8_22, rgb_5, rgb_6, rgb_7, rgb_8) \ #elif RGB_FORMAT == RGB_FORMAT_RGB24 #define PACK_PIXEL \ __m128i rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6; \ __m128i rgb_7, rgb_8, rgb_9, rgb_10, rgb_11, rgb_12; \ \ PACK_RGB24_32(r_8_11, r_8_12, g_8_11, g_8_12, b_8_11, b_8_12, rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6) \ \ PACK_RGB24_32(r_8_21, r_8_22, g_8_21, g_8_22, b_8_21, b_8_22, rgb_7, rgb_8, rgb_9, rgb_10, rgb_11, rgb_12) \ #elif RGB_FORMAT == RGB_FORMAT_RGBA #define PACK_PIXEL \ __m128i rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8; \ __m128i rgb_9, rgb_10, rgb_11, rgb_12, rgb_13, rgb_14, rgb_15, rgb_16; \ __m128i a = _mm_set1_epi8((char)0xFF); \ \ PACK_RGBA_32(r_8_11, r_8_12, g_8_11, g_8_12, b_8_11, b_8_12, a, a, rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8) \ \ PACK_RGBA_32(r_8_21, r_8_22, g_8_21, g_8_22, b_8_21, b_8_22, a, a, rgb_9, rgb_10, rgb_11, rgb_12, rgb_13, rgb_14, rgb_15, rgb_16) \ #elif RGB_FORMAT == RGB_FORMAT_BGRA #define PACK_PIXEL \ __m128i rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8; \ __m128i rgb_9, rgb_10, rgb_11, rgb_12, rgb_13, rgb_14, rgb_15, rgb_16; \ __m128i a = _mm_set1_epi8((char)0xFF); \ \ PACK_RGBA_32(b_8_11, b_8_12, g_8_11, g_8_12, r_8_11, r_8_12, a, a, rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8) \ \ PACK_RGBA_32(b_8_21, b_8_22, g_8_21, g_8_22, r_8_21, r_8_22, a, a, rgb_9, rgb_10, rgb_11, rgb_12, rgb_13, rgb_14, rgb_15, rgb_16) \ #elif RGB_FORMAT == RGB_FORMAT_ARGB #define PACK_PIXEL \ __m128i rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8; \ __m128i rgb_9, rgb_10, rgb_11, rgb_12, rgb_13, rgb_14, rgb_15, rgb_16; \ __m128i a = _mm_set1_epi8((char)0xFF); \ \ PACK_RGBA_32(a, a, r_8_11, r_8_12, g_8_11, g_8_12, b_8_11, b_8_12, rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8) \ \ PACK_RGBA_32(a, a, r_8_21, r_8_22, g_8_21, g_8_22, b_8_21, b_8_22, rgb_9, rgb_10, rgb_11, rgb_12, rgb_13, rgb_14, rgb_15, rgb_16) \ #elif RGB_FORMAT == RGB_FORMAT_ABGR #define PACK_PIXEL \ __m128i rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8; \ __m128i rgb_9, rgb_10, rgb_11, rgb_12, rgb_13, rgb_14, rgb_15, rgb_16; \ __m128i a = _mm_set1_epi8((char)0xFF); \ \ PACK_RGBA_32(a, a, b_8_11, b_8_12, g_8_11, g_8_12, r_8_11, r_8_12, rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8) \ \ PACK_RGBA_32(a, a, b_8_21, b_8_22, g_8_21, g_8_22, r_8_21, r_8_22, rgb_9, rgb_10, rgb_11, rgb_12, rgb_13, rgb_14, rgb_15, rgb_16) \ #else #error PACK_PIXEL unimplemented #endif #if RGB_FORMAT == RGB_FORMAT_RGB565 #define SAVE_LINE1 \ SAVE_SI128((__m128i)(rgb_ptr1), rgb_1); \ SAVE_SI128((__m128i)(rgb_ptr1+16), rgb_2); \ SAVE_SI128((__m128i)(rgb_ptr1+32), rgb_3); \ SAVE_SI128((__m128i)(rgb_ptr1+48), rgb_4); \ #define SAVE_LINE2 \ SAVE_SI128((__m128i)(rgb_ptr2), rgb_5); \ SAVE_SI128((__m128i)(rgb_ptr2+16), rgb_6); \ SAVE_SI128((__m128i)(rgb_ptr2+32), rgb_7); \ SAVE_SI128((__m128i)(rgb_ptr2+48), rgb_8); \ #elif RGB_FORMAT == RGB_FORMAT_RGB24 #define SAVE_LINE1 \ SAVE_SI128((__m128i)(rgb_ptr1), rgb_1); \ SAVE_SI128((__m128i)(rgb_ptr1+16), rgb_2); \ SAVE_SI128((__m128i)(rgb_ptr1+32), rgb_3); \ SAVE_SI128((__m128i)(rgb_ptr1+48), rgb_4); \ SAVE_SI128((__m128i)(rgb_ptr1+64), rgb_5); \ SAVE_SI128((__m128i)(rgb_ptr1+80), rgb_6); \ #define SAVE_LINE2 \ SAVE_SI128((__m128i)(rgb_ptr2), rgb_7); \ SAVE_SI128((__m128i)(rgb_ptr2+16), rgb_8); \ SAVE_SI128((__m128i)(rgb_ptr2+32), rgb_9); \ SAVE_SI128((__m128i)(rgb_ptr2+48), rgb_10); \ SAVE_SI128((__m128i)(rgb_ptr2+64), rgb_11); \ SAVE_SI128((__m128i)(rgb_ptr2+80), rgb_12); \ #elif RGB_FORMAT == RGB_FORMAT_RGBA \|\| RGB_FORMAT == RGB_FORMAT_BGRA \|\| \ RGB_FORMAT == RGB_FORMAT_ARGB \|\| RGB_FORMAT == RGB_FORMAT_ABGR #define SAVE_LINE1 \ SAVE_SI128((__m128i)(rgb_ptr1), rgb_1); \ SAVE_SI128((__m128i)(rgb_ptr1+16), rgb_2); \ SAVE_SI128((__m128i)(rgb_ptr1+32), rgb_3); \ SAVE_SI128((__m128i)(rgb_ptr1+48), rgb_4); \ SAVE_SI128((__m128i)(rgb_ptr1+64), rgb_5); \ SAVE_SI128((__m128i)(rgb_ptr1+80), rgb_6); \ SAVE_SI128((__m128i)(rgb_ptr1+96), rgb_7); \ SAVE_SI128((__m128i)(rgb_ptr1+112), rgb_8); \ #define SAVE_LINE2 \ SAVE_SI128((__m128i)(rgb_ptr2), rgb_9); \ SAVE_SI128((__m128i)(rgb_ptr2+16), rgb_10); \ SAVE_SI128((__m128i)(rgb_ptr2+32), rgb_11); \ SAVE_SI128((__m128i)(rgb_ptr2+48), rgb_12); \ SAVE_SI128((__m128i)(rgb_ptr2+64), rgb_13); \ SAVE_SI128((__m128i)(rgb_ptr2+80), rgb_14); \ SAVE_SI128((__m128i)(rgb_ptr2+96), rgb_15); \ SAVE_SI128((__m128i)(rgb_ptr2+112), rgb_16); \ #else #error SAVE_LINE unimplemented #endif #if YUV_FORMAT == YUV_FORMAT_420 #define READ_Y(y_ptr) \ y = LOAD_SI128((const __m128i)(y_ptr)); \ #define READ_UV \ u = LOAD_SI128((const __m128i)(u_ptr)); \ v = LOAD_SI128((const __m128i)(v_ptr)); \ #elif YUV_FORMAT == YUV_FORMAT_422 #define READ_Y(y_ptr) \ { \ __m128i y1, y2; \ y1 = _mm_srli_epi16(_mm_slli_epi16(LOAD_SI128((const __m128i)(y_ptr)), 8), 8); \ y2 = _mm_srli_epi16(_mm_slli_epi16(LOAD_SI128((const __m128i)(y_ptr+16)), 8), 8); \ y = _mm_packus_epi16(y1, y2); \ } #define READ_UV \ { \ __m128i u1, u2, u3, u4, v1, v2, v3, v4; \ u1 = _mm_srli_epi32(_mm_slli_epi32(LOAD_SI128((const __m128i)(u_ptr)), 24), 24); \ u2 = _mm_srli_epi32(_mm_slli_epi32(LOAD_SI128((const __m128i)(u_ptr+16)), 24), 24); \ u3 = _mm_srli_epi32(_mm_slli_epi32(LOAD_SI128((const __m128i)(u_ptr+32)), 24), 24); \ u4 = _mm_srli_epi32(_mm_slli_epi32(LOAD_SI128((const __m128i)(u_ptr+48)), 24), 24); \ u = _mm_packus_epi16(_mm_packs_epi32(u1, u2), _mm_packs_epi32(u3, u4)); \ v1 = _mm_srli_epi32(_mm_slli_epi32(LOAD_SI128((const __m128i)(v_ptr)), 24), 24); \ v2 = _mm_srli_epi32(_mm_slli_epi32(LOAD_SI128((const __m128i)(v_ptr+16)), 24), 24); \ v3 = _mm_srli_epi32(_mm_slli_epi32(LOAD_SI128((const __m128i)(v_ptr+32)), 24), 24); \ v4 = _mm_srli_epi32(_mm_slli_epi32(LOAD_SI128((const __m128i)(v_ptr+48)), 24), 24); \ v = _mm_packus_epi16(_mm_packs_epi32(v1, v2), _mm_packs_epi32(v3, v4)); \ } #elif YUV_FORMAT == YUV_FORMAT_NV12 #define READ_Y(y_ptr) \ y = LOAD_SI128((const __m128i)(y_ptr)); \ #define READ_UV \ { \ __m128i u1, u2, v1, v2; \ u1 = _mm_srli_epi16(_mm_slli_epi16(LOAD_SI128((const __m128i)(u_ptr)), 8), 8); \ u2 = _mm_srli_epi16(_mm_slli_epi16(LOAD_SI128((const __m128i)(u_ptr+16)), 8), 8); \ u = _mm_packus_epi16(u1, u2); \ v1 = _mm_srli_epi16(_mm_slli_epi16(LOAD_SI128((const __m128i)(v_ptr)), 8), 8); \ v2 = _mm_srli_epi16(_mm_slli_epi16(LOAD_SI128((const __m128i)(v_ptr+16)), 8), 8); \ v = _mm_packus_epi16(v1, v2); \ } #else #error READ_UV unimplemented #endif #define YUV2RGB_32 \ __m128i r_tmp, g_tmp, b_tmp; \ __m128i r_16_1, g_16_1, b_16_1, r_16_2, g_16_2, b_16_2; \ __m128i r_uv_16_1, g_uv_16_1, b_uv_16_1, r_uv_16_2, g_uv_16_2, b_uv_16_2; \ __m128i y_16_1, y_16_2; \ __m128i y, u, v, u_16, v_16; \ __m128i r_8_11, g_8_11, b_8_11, r_8_21, g_8_21, b_8_21; \ __m128i r_8_12, g_8_12, b_8_12, r_8_22, g_8_22, b_8_22; \ \ READ_UV \ \ / process first 16 pixels of first line /\ u_16 = _mm_unpacklo_epi8(u, _mm_setzero_si128()); \ v_16 = _mm_unpacklo_epi8(v, _mm_setzero_si128()); \ u_16 = _mm_add_epi16(u_16, _mm_set1_epi16(-128)); \ v_16 = _mm_add_epi16(v_16, _mm_set1_epi16(-128)); \ \ UV2RGB_16(u_16, v_16, r_16_1, g_16_1, b_16_1, r_16_2, g_16_2, b_16_2) \ r_uv_16_1=r_16_1; g_uv_16_1=g_16_1; b_uv_16_1=b_16_1; \ r_uv_16_2=r_16_2; g_uv_16_2=g_16_2; b_uv_16_2=b_16_2; \ \ READ_Y(y_ptr1) \ y_16_1 = _mm_unpacklo_epi8(y, _mm_setzero_si128()); \ y_16_2 = _mm_unpackhi_epi8(y, _mm_setzero_si128()); \ \ ADD_Y2RGB_16(y_16_1, y_16_2, r_16_1, g_16_1, b_16_1, r_16_2, g_16_2, b_16_2) \ \ r_8_11 = _mm_packus_epi16(r_16_1, r_16_2); \ g_8_11 = _mm_packus_epi16(g_16_1, g_16_2); \ b_8_11 = _mm_packus_epi16(b_16_1, b_16_2); \ \ / process first 16 pixels of second line /\ r_16_1=r_uv_16_1; g_16_1=g_uv_16_1; b_16_1=b_uv_16_1; \ r_16_2=r_uv_16_2; g_16_2=g_uv_16_2; b_16_2=b_uv_16_2; \ \ READ_Y(y_ptr2) \ y_16_1 = _mm_unpacklo_epi8(y, _mm_setzero_si128()); \ y_16_2 = _mm_unpackhi_epi8(y, _mm_setzero_si128()); \ \ ADD_Y2RGB_16(y_16_1, y_16_2, r_16_1, g_16_1, b_16_1, r_16_2, g_16_2, b_16_2) \ \ r_8_21 = _mm_packus_epi16(r_16_1, r_16_2); \ g_8_21 = _mm_packus_epi16(g_16_1, g_16_2); \ b_8_21 = _mm_packus_epi16(b_16_1, b_16_2); \ \ / process last 16 pixels of first line /\ u_16 = _mm_unpackhi_epi8(u, _mm_setzero_si128()); \ v_16 = _mm_unpackhi_epi8(v, _mm_setzero_si128()); \ u_16 = _mm_add_epi16(u_16, _mm_set1_epi16(-128)); \ v_16 = _mm_add_epi16(v_16, _mm_set1_epi16(-128)); \ \ UV2RGB_16(u_16, v_16, r_16_1, g_16_1, b_16_1, r_16_2, g_16_2, b_16_2) \ r_uv_16_1=r_16_1; g_uv_16_1=g_16_1; b_uv_16_1=b_16_1; \ r_uv_16_2=r_16_2; g_uv_16_2=g_16_2; b_uv_16_2=b_16_2; \ \ READ_Y(y_ptr1+16y_pixel_stride) \ y_16_1 = _mm_unpacklo_epi8(y, _mm_setzero_si128()); \ y_16_2 = _mm_unpackhi_epi8(y, _mm_setzero_si128()); \ \ ADD_Y2RGB_16(y_16_1, y_16_2, r_16_1, g_16_1, b_16_1, r_16_2, g_16_2, b_16_2) \ \ r_8_12 = _mm_packus_epi16(r_16_1, r_16_2); \ g_8_12 = _mm_packus_epi16(g_16_1, g_16_2); \ b_8_12 = _mm_packus_epi16(b_16_1, b_16_2); \ \ /* process last 16 pixels of second line /\ r_16_1=r_uv_16_1; g_16_1=g_uv_16_1; b_16_1=b_uv_16_1; \ r_16_2=r_uv_16_2; g_16_2=g_uv_16_2; b_16_2=b_uv_16_2; \ \ READ_Y(y_ptr2+16y_pixel_stride) \ y_16_1 = _mm_unpacklo_epi8(y, _mm_setzero_si128()); \ y_16_2 = _mm_unpackhi_epi8(y, _mm_setzero_si128()); \ \ ADD_Y2RGB_16(y_16_1, y_16_2, r_16_1, g_16_1, b_16_1, r_16_2, g_16_2, b_16_2) \ \ r_8_22 = _mm_packus_epi16(r_16_1, r_16_2); \ g_8_22 = _mm_packus_epi16(g_16_1, g_16_2); \ b_8_22 = _mm_packus_epi16(b_16_1, b_16_2); \ \ void SSE_FUNCTION_NAME(uint32_t width, uint32_t height, const uint8_t Y, const uint8_t U, const uint8_t V, uint32_t Y_stride, uint32_t UV_stride, uint8_t RGB, uint32_t RGB_stride, YCbCrType yuv_type) { const YUV2RGBParam const param = &(YUV2RGB[yuv_type]); #if YUV_FORMAT == YUV_FORMAT_420 const int y_pixel_stride = 1; const int uv_pixel_stride = 1; const int uv_x_sample_interval = 2; const int uv_y_sample_interval = 2; #elif YUV_FORMAT == YUV_FORMAT_422 const int y_pixel_stride = 2; const int uv_pixel_stride = 4; const int uv_x_sample_interval = 2; const int uv_y_sample_interval = 1; #elif YUV_FORMAT == YUV_FORMAT_NV12 const int y_pixel_stride = 1; const int uv_pixel_stride = 2; const int uv_x_sample_interval = 2; const int uv_y_sample_interval = 2; #endif #if RGB_FORMAT == RGB_FORMAT_RGB565 const int rgb_pixel_stride = 2; #elif RGB_FORMAT == RGB_FORMAT_RGB24 const int rgb_pixel_stride = 3; #elif RGB_FORMAT == RGB_FORMAT_RGBA \|\| RGB_FORMAT == RGB_FORMAT_BGRA \|\| \ RGB_FORMAT == RGB_FORMAT_ARGB \|\| RGB_FORMAT == RGB_FORMAT_ABGR const int rgb_pixel_stride = 4; #else #error Unknown RGB pixel size #endif if (width >= 32) { uint32_t xpos, ypos; for(ypos=0; ypos<(height-(uv_y_sample_interval-1)); ypos+=uv_y_sample_interval) { const uint8_t y_ptr1=Y+yposY_stride, y_ptr2=Y+(ypos+1)Y_stride, u_ptr=U+(ypos/uv_y_sample_interval)UV_stride, v_ptr=V+(ypos/uv_y_sample_interval)UV_stride; uint8_t rgb_ptr1=RGB+yposRGB_stride, rgb_ptr2=RGB+(ypos+1)RGB_stride; for(xpos=0; xpos<(width-31); xpos+=32) { YUV2RGB_32 { PACK_PIXEL SAVE_LINE1 if (uv_y_sample_interval > 1) { SAVE_LINE2 } } y_ptr1+=32y_pixel_stride; y_ptr2+=32y_pixel_stride; u_ptr+=32uv_pixel_stride/uv_x_sample_interval; v_ptr+=32uv_pixel_stride/uv_x_sample_interval; rgb_ptr1+=32rgb_pixel_stride; rgb_ptr2+=32rgb_pixel_stride; } } / Catch the last line, if needed / if (uv_y_sample_interval == 2 && ypos == (height-1)) { const uint8_t y_ptr=Y+yposY_stride, u_ptr=U+(ypos/uv_y_sample_interval)UV_stride, v_ptr=V+(ypos/uv_y_sample_interval)UV_stride; uint8_t rgb_ptr=RGB+yposRGB_stride; STD_FUNCTION_NAME(width, 1, y_ptr, u_ptr, v_ptr, Y_stride, UV_stride, rgb_ptr, RGB_stride, yuv_type); } } / Catch the right column, if needed / { int converted = (width & ~31); if (converted != width) { const uint8_t y_ptr=Y+convertedy_pixel_stride, u_ptr=U+converteduv_pixel_stride/uv_x_sample_interval, v_ptr=V+converteduv_pixel_stride/uv_x_sample_interval; uint8_t rgb_ptr=RGB+converted*rgb_pixel_stride; STD_FUNCTION_NAME(width-converted, height, y_ptr, u_ptr, v_ptr, Y_stride, UV_stride, rgb_ptr, RGB_stride, yuv_type); } } } #undef SSE_FUNCTION_NAME #undef STD_FUNCTION_NAME #undef YUV_FORMAT #undef RGB_FORMAT #undef SSE_ALIGNED #undef LOAD_SI128 #undef SAVE_SI128 #undef UV2RGB_16 #undef ADD_Y2RGB_16 #undef PACK_RGB24_32_STEP1 #undef PACK_RGB24_32_STEP2 #undef PACK_RGB24_32 #undef PACK_RGBA_32 #undef PACK_PIXEL #undef SAVE_LINE1 #undef SAVE_LINE2 #undef READ_Y #undef READ_UV #undef YUV2RGB_32	{ "language": "Assembly" }
#include "z_boss_ganon2.h" #define FLAGS 0x00000035 #define THIS ((BossGanon2)thisx) void BossGanon2_Init(Actor thisx, GlobalContext* globalCtx); void BossGanon2_Destroy(Actor* thisx, GlobalContext* globalCtx); void BossGanon2_Update(Actor* thisx, GlobalContext* globalCtx); void BossGanon2_Draw(Actor* thisx, GlobalContext* globalCtx); /* const ActorInit Boss_Ganon2_InitVars = { ACTOR_BOSS_GANON2, ACTORTYPE_BOSS, FLAGS, OBJECT_GANON2, sizeof(BossGanon2), (ActorFunc)BossGanon2_Init, (ActorFunc)BossGanon2_Destroy, (ActorFunc)BossGanon2_Update, (ActorFunc)BossGanon2_Draw, }; */ #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FCF40.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FCF5C.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FD080.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FD108.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FD210.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FD27C.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/BossGanon2_Init.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/BossGanon2_Destroy.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FD4D4.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FD5C4.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FD5F4.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FF898.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFA24.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFAC8.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFBBC.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFC84.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFCFC.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFDB0.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFEBC.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFF90.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFFE0.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_809000A0.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80900104.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80900210.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_8090026C.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_809002CC.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80900344.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80900580.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80900650.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80900818.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80900890.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80901020.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_8090109C.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_8090120C.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80902348.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80902524.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/BossGanon2_Update.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_809034E4.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80903F38.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80904108.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80904340.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_8090464C.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80904818.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_809049A0.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80904D88.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80904FC8.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_8090523C.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80905508.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80905674.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/BossGanon2_Draw.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80905DA8.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_809060E8.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80906538.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_809069F8.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80906AB0.s")	{ "language": "Assembly" }
# Copyright 2013 the V8 project authors. All rights reserved. # Copyright (C) 2005, 2006, 2007, 2008, 2009 Apple Inc. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY APPLE INC. AND ITS CONTRIBUTORS ``AS IS'' AND ANY # EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE # DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR ITS CONTRIBUTORS BE LIABLE FOR ANY # DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON # ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. This test checks that the Function constructor places a newline after the opening brace, for compatibility reasons. It passes if there are no syntax error exceptions. On success, you will see a series of "PASS" messages, followed by "TEST COMPLETE". PASS successfullyParsed is true TEST COMPLETE	{ "language": "Assembly" }
; RUN: opt < %s -gvn \| llvm-dis %struct.TypHeader = type { i32, %struct.TypHeader*, [3 x i8], i8 } define %struct.TypHeader @LtRec(%struct.TypHeader* %hdL, %struct.TypHeader* %hdR) { entry: br i1 false, label %bb556.preheader, label %bb534.preheader bb534.preheader: ; preds = %entry ret %struct.TypHeader* null bb556.preheader: ; preds = %entry %tmp56119 = getelementptr %struct.TypHeader* %hdR, i32 0, i32 0 ; <i32> [#uses=1] %tmp56220 = load i32 %tmp56119 ; <i32> [#uses=0] br i1 false, label %bb.nph23, label %bb675.preheader bb.nph23: ; preds = %bb556.preheader ret %struct.TypHeader* null bb656: ; preds = %bb675.outer, %bb656 %tmp678 = load i32* %tmp677 ; <i32> [#uses=0] br i1 false, label %bb684, label %bb656 bb684: ; preds = %bb675.outer, %bb656 br i1 false, label %bb924.preheader, label %bb675.outer bb675.outer: ; preds = %bb675.preheader, %bb684 %tmp67812 = load i32* %tmp67711 ; <i32> [#uses=0] br i1 false, label %bb684, label %bb656 bb675.preheader: ; preds = %bb556.preheader %tmp67711 = getelementptr %struct.TypHeader* %hdR, i32 0, i32 0 ; <i32> [#uses=1] %tmp677 = getelementptr %struct.TypHeader %hdR, i32 0, i32 0 ; <i32> [#uses=1] br label %bb675.outer bb924.preheader: ; preds = %bb684 ret %struct.TypHeader null }	{ "language": "Assembly" }
[GLOBAL asm_powoff] asm_powoff: mov ax, 5301h xor bx, bx int 15h mov ax, 530Fh mov bx, 1 mov cx, 1 int 15h mov ax, 5307h mov bx, 1 mov cx, 3 int 15h	{ "language": "Assembly" }
/***************************************************************************** * asm.S: arm utility macros ***************************************************************************** * Copyright (C) 2008-2016 x264 project * * Authors: Mans Rullgard <[email protected]> * David Conrad <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111, USA. * * This program is also available under a commercial proprietary license. * For more information, contact us at [email protected]. *****************************************************************************/ #include "config.h" .syntax unified #if HAVE_NEON .arch armv7-a #elif HAVE_ARMV6T2 .arch armv6t2 #elif HAVE_ARMV6 .arch armv6 #endif .fpu neon #ifdef PREFIX # define EXTERN_ASM _ #else # define EXTERN_ASM #endif #ifdef __ELF__ # define ELF #else # define ELF @ #endif #if HAVE_AS_FUNC # define FUNC #else # define FUNC @ #endif #if SYS_LINUX #define HAVE_SECTION_DATA_REL_RO 1 #else #define HAVE_SECTION_DATA_REL_RO 0 #endif .macro require8, val=1 ELF .eabi_attribute 24, \val .endm .macro preserve8, val=1 ELF .eabi_attribute 25, \val .endm .macro function name, export=1 .macro endfunc ELF .size \name, . - \name FUNC .endfunc .purgem endfunc .endm .align 2 .if \export == 1 .global EXTERN_ASM\name ELF .hidden EXTERN_ASM\name ELF .type EXTERN_ASM\name, %function FUNC .func EXTERN_ASM\name EXTERN_ASM\name: .else ELF .hidden \name ELF .type \name, %function FUNC .func \name \name: .endif .endm .macro const name, align=2, relocate=0 .macro endconst ELF .size \name, . - \name .purgem endconst .endm .if HAVE_SECTION_DATA_REL_RO && \relocate .section .data.rel.ro .else .section .rodata .endif .align \align \name: .endm .macro movrel rd, val #if defined(PIC) ldr \rd, 1f b 2f 1: @ FIXME: thumb .word \val - (2f + 8) 2: add \rd, \rd, pc #elif HAVE_ARMV6T2 movw \rd, #:lower16:\val movt \rd, #:upper16:\val #else ldr \rd, =\val #endif .endm .macro movrelx rd, val, got #if defined(PIC) && defined(__ELF__) ldr \got, 2f ldr \rd, 1f b 3f 1: @ FIXME: thumb .word \val(GOT) 2: .word _GLOBAL_OFFSET_TABLE_ - (3f + 8) 3: add \got, \got, pc ldr \rd, [\got, \rd] #elif defined(PIC) && defined(__APPLE__) ldr \rd, 1f b 2f 1: @ FIXME: thumb .word 3f - (2f + 8) 2: ldr \rd, [pc, \rd] .non_lazy_symbol_pointer 3: .indirect_symbol \val .word 0 .text #else movrel \rd, \val #endif .endm .macro movconst rd, val #if HAVE_ARMV6T2 movw \rd, #:lower16:\val .if \val >> 16 movt \rd, #:upper16:\val .endif #else ldr \rd, =\val #endif .endm #define GLUE(a, b) a ## b #define JOIN(a, b) GLUE(a, b) #define X(s) JOIN(EXTERN_ASM, s) #define FENC_STRIDE 16 #define FDEC_STRIDE 32 .macro HORIZ_ADD dest, a, b .ifnb \b vadd.u16 \a, \a, \b .endif vpaddl.u16 \a, \a vpaddl.u32 \dest, \a .endm .macro SUMSUB_AB sum, diff, a, b vadd.s16 \sum, \a, \b vsub.s16 \diff, \a, \b .endm .macro SUMSUB_ABCD s1, d1, s2, d2, a, b, c, d SUMSUB_AB \s1, \d1, \a, \b SUMSUB_AB \s2, \d2, \c, \d .endm .macro ABS2 a b vabs.s16 \a, \a vabs.s16 \b, \b .endm // dist = distance in elements (0 for vertical pass, 1/2 for horizontal passes) // op = sumsub/amax (sum and diff / maximum of absolutes) // d1/2 = destination registers // s1/2 = source registers .macro HADAMARD dist, op, d1, d2, s1, s2 .if \dist == 1 vtrn.16 \s1, \s2 .else vtrn.32 \s1, \s2 .endif .ifc \op, sumsub SUMSUB_AB \d1, \d2, \s1, \s2 .else vabs.s16 \s1, \s1 vabs.s16 \s2, \s2 vmax.s16 \d1, \s1, \s2 .endif .endm .macro TRANSPOSE8x8 r0 r1 r2 r3 r4 r5 r6 r7 vtrn.32 \r0, \r4 vtrn.32 \r1, \r5 vtrn.32 \r2, \r6 vtrn.32 \r3, \r7 vtrn.16 \r0, \r2 vtrn.16 \r1, \r3 vtrn.16 \r4, \r6 vtrn.16 \r5, \r7 vtrn.8 \r0, \r1 vtrn.8 \r2, \r3 vtrn.8 \r4, \r5 vtrn.8 \r6, \r7 .endm .macro TRANSPOSE4x4 r0 r1 r2 r3 vtrn.16 \r0, \r2 vtrn.16 \r1, \r3 vtrn.8 \r0, \r1 vtrn.8 \r2, \r3 .endm .macro TRANSPOSE4x4_16 d0 d1 d2 d3 vtrn.32 \d0, \d2 vtrn.32 \d1, \d3 vtrn.16 \d0, \d1 vtrn.16 \d2, \d3 .endm	{ "language": "Assembly" }
#ifndef CAPSTONE_X86_H #define CAPSTONE_X86_H /* Capstone Disassembly Engine / / By Nguyen Anh Quynh <[email protected]>, 2013-2015 / #ifdef __cplusplus extern "C" { #endif #include "platform.h" // Calculate relative address for X86-64, given cs_insn structure #define X86_REL_ADDR(insn) (insn.address + insn.size + insn.detail->x86.disp) //> X86 registers typedef enum x86_reg { X86_REG_INVALID = 0, X86_REG_AH, X86_REG_AL, X86_REG_AX, X86_REG_BH, X86_REG_BL, X86_REG_BP, X86_REG_BPL, X86_REG_BX, X86_REG_CH, X86_REG_CL, X86_REG_CS, X86_REG_CX, X86_REG_DH, X86_REG_DI, X86_REG_DIL, X86_REG_DL, X86_REG_DS, X86_REG_DX, X86_REG_EAX, X86_REG_EBP, X86_REG_EBX, X86_REG_ECX, X86_REG_EDI, X86_REG_EDX, X86_REG_EFLAGS, X86_REG_EIP, X86_REG_EIZ, X86_REG_ES, X86_REG_ESI, X86_REG_ESP, X86_REG_FPSW, X86_REG_FS, X86_REG_GS, X86_REG_IP, X86_REG_RAX, X86_REG_RBP, X86_REG_RBX, X86_REG_RCX, X86_REG_RDI, X86_REG_RDX, X86_REG_RIP, X86_REG_RIZ, X86_REG_RSI, X86_REG_RSP, X86_REG_SI, X86_REG_SIL, X86_REG_SP, X86_REG_SPL, X86_REG_SS, X86_REG_CR0, X86_REG_CR1, X86_REG_CR2, X86_REG_CR3, X86_REG_CR4, X86_REG_CR5, X86_REG_CR6, X86_REG_CR7, X86_REG_CR8, X86_REG_CR9, X86_REG_CR10, X86_REG_CR11, X86_REG_CR12, X86_REG_CR13, X86_REG_CR14, X86_REG_CR15, X86_REG_DR0, X86_REG_DR1, X86_REG_DR2, X86_REG_DR3, X86_REG_DR4, X86_REG_DR5, X86_REG_DR6, X86_REG_DR7, X86_REG_DR8, X86_REG_DR9, X86_REG_DR10, X86_REG_DR11, X86_REG_DR12, X86_REG_DR13, X86_REG_DR14, X86_REG_DR15, X86_REG_FP0, X86_REG_FP1, X86_REG_FP2, X86_REG_FP3, X86_REG_FP4, X86_REG_FP5, X86_REG_FP6, X86_REG_FP7, X86_REG_K0, X86_REG_K1, X86_REG_K2, X86_REG_K3, X86_REG_K4, X86_REG_K5, X86_REG_K6, X86_REG_K7, X86_REG_MM0, X86_REG_MM1, X86_REG_MM2, X86_REG_MM3, X86_REG_MM4, X86_REG_MM5, X86_REG_MM6, X86_REG_MM7, X86_REG_R8, X86_REG_R9, X86_REG_R10, X86_REG_R11, X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15, X86_REG_ST0, X86_REG_ST1, X86_REG_ST2, X86_REG_ST3, X86_REG_ST4, X86_REG_ST5, X86_REG_ST6, X86_REG_ST7, X86_REG_XMM0, X86_REG_XMM1, X86_REG_XMM2, X86_REG_XMM3, X86_REG_XMM4, X86_REG_XMM5, X86_REG_XMM6, X86_REG_XMM7, X86_REG_XMM8, X86_REG_XMM9, X86_REG_XMM10, X86_REG_XMM11, X86_REG_XMM12, X86_REG_XMM13, X86_REG_XMM14, X86_REG_XMM15, X86_REG_XMM16, X86_REG_XMM17, X86_REG_XMM18, X86_REG_XMM19, X86_REG_XMM20, X86_REG_XMM21, X86_REG_XMM22, X86_REG_XMM23, X86_REG_XMM24, X86_REG_XMM25, X86_REG_XMM26, X86_REG_XMM27, X86_REG_XMM28, X86_REG_XMM29, X86_REG_XMM30, X86_REG_XMM31, X86_REG_YMM0, X86_REG_YMM1, X86_REG_YMM2, X86_REG_YMM3, X86_REG_YMM4, X86_REG_YMM5, X86_REG_YMM6, X86_REG_YMM7, X86_REG_YMM8, X86_REG_YMM9, X86_REG_YMM10, X86_REG_YMM11, X86_REG_YMM12, X86_REG_YMM13, X86_REG_YMM14, X86_REG_YMM15, X86_REG_YMM16, X86_REG_YMM17, X86_REG_YMM18, X86_REG_YMM19, X86_REG_YMM20, X86_REG_YMM21, X86_REG_YMM22, X86_REG_YMM23, X86_REG_YMM24, X86_REG_YMM25, X86_REG_YMM26, X86_REG_YMM27, X86_REG_YMM28, X86_REG_YMM29, X86_REG_YMM30, X86_REG_YMM31, X86_REG_ZMM0, X86_REG_ZMM1, X86_REG_ZMM2, X86_REG_ZMM3, X86_REG_ZMM4, X86_REG_ZMM5, X86_REG_ZMM6, X86_REG_ZMM7, X86_REG_ZMM8, X86_REG_ZMM9, X86_REG_ZMM10, X86_REG_ZMM11, X86_REG_ZMM12, X86_REG_ZMM13, X86_REG_ZMM14, X86_REG_ZMM15, X86_REG_ZMM16, X86_REG_ZMM17, X86_REG_ZMM18, X86_REG_ZMM19, X86_REG_ZMM20, X86_REG_ZMM21, X86_REG_ZMM22, X86_REG_ZMM23, X86_REG_ZMM24, X86_REG_ZMM25, X86_REG_ZMM26, X86_REG_ZMM27, X86_REG_ZMM28, X86_REG_ZMM29, X86_REG_ZMM30, X86_REG_ZMM31, X86_REG_R8B, X86_REG_R9B, X86_REG_R10B, X86_REG_R11B, X86_REG_R12B, X86_REG_R13B, X86_REG_R14B, X86_REG_R15B, X86_REG_R8D, X86_REG_R9D, X86_REG_R10D, X86_REG_R11D, X86_REG_R12D, X86_REG_R13D, X86_REG_R14D, X86_REG_R15D, X86_REG_R8W, X86_REG_R9W, X86_REG_R10W, X86_REG_R11W, X86_REG_R12W, X86_REG_R13W, X86_REG_R14W, X86_REG_R15W, X86_REG_ENDING // <-- mark the end of the list of registers } x86_reg; //> Sub-flags of EFLAGS #define X86_EFLAGS_MODIFY_AF (1ULL << 0) #define X86_EFLAGS_MODIFY_CF (1ULL << 1) #define X86_EFLAGS_MODIFY_SF (1ULL << 2) #define X86_EFLAGS_MODIFY_ZF (1ULL << 3) #define X86_EFLAGS_MODIFY_PF (1ULL << 4) #define X86_EFLAGS_MODIFY_OF (1ULL << 5) #define X86_EFLAGS_MODIFY_TF (1ULL << 6) #define X86_EFLAGS_MODIFY_IF (1ULL << 7) #define X86_EFLAGS_MODIFY_DF (1ULL << 8) #define X86_EFLAGS_MODIFY_NT (1ULL << 9) #define X86_EFLAGS_MODIFY_RF (1ULL << 10) #define X86_EFLAGS_PRIOR_OF (1ULL << 11) #define X86_EFLAGS_PRIOR_SF (1ULL << 12) #define X86_EFLAGS_PRIOR_ZF (1ULL << 13) #define X86_EFLAGS_PRIOR_AF (1ULL << 14) #define X86_EFLAGS_PRIOR_PF (1ULL << 15) #define X86_EFLAGS_PRIOR_CF (1ULL << 16) #define X86_EFLAGS_PRIOR_TF (1ULL << 17) #define X86_EFLAGS_PRIOR_IF (1ULL << 18) #define X86_EFLAGS_PRIOR_DF (1ULL << 19) #define X86_EFLAGS_PRIOR_NT (1ULL << 20) #define X86_EFLAGS_RESET_OF (1ULL << 21) #define X86_EFLAGS_RESET_CF (1ULL << 22) #define X86_EFLAGS_RESET_DF (1ULL << 23) #define X86_EFLAGS_RESET_IF (1ULL << 24) #define X86_EFLAGS_RESET_SF (1ULL << 25) #define X86_EFLAGS_RESET_AF (1ULL << 26) #define X86_EFLAGS_RESET_TF (1ULL << 27) #define X86_EFLAGS_RESET_NT (1ULL << 28) #define X86_EFLAGS_RESET_PF (1ULL << 29) #define X86_EFLAGS_SET_CF (1ULL << 30) #define X86_EFLAGS_SET_DF (1ULL << 31) #define X86_EFLAGS_SET_IF (1ULL << 32) #define X86_EFLAGS_TEST_OF (1ULL << 33) #define X86_EFLAGS_TEST_SF (1ULL << 34) #define X86_EFLAGS_TEST_ZF (1ULL << 35) #define X86_EFLAGS_TEST_PF (1ULL << 36) #define X86_EFLAGS_TEST_CF (1ULL << 37) #define X86_EFLAGS_TEST_NT (1ULL << 38) #define X86_EFLAGS_TEST_DF (1ULL << 39) #define X86_EFLAGS_UNDEFINED_OF (1ULL << 40) #define X86_EFLAGS_UNDEFINED_SF (1ULL << 41) #define X86_EFLAGS_UNDEFINED_ZF (1ULL << 42) #define X86_EFLAGS_UNDEFINED_PF (1ULL << 43) #define X86_EFLAGS_UNDEFINED_AF (1ULL << 44) #define X86_EFLAGS_UNDEFINED_CF (1ULL << 45) //> Operand type for instruction's operands typedef enum x86_op_type { X86_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). X86_OP_REG, // = CS_OP_REG (Register operand). X86_OP_IMM, // = CS_OP_IMM (Immediate operand). X86_OP_MEM, // = CS_OP_MEM (Memory operand). } x86_op_type; //> XOP Code Condition type typedef enum x86_xop_cc { X86_XOP_CC_INVALID = 0, // Uninitialized. X86_XOP_CC_LT, X86_XOP_CC_LE, X86_XOP_CC_GT, X86_XOP_CC_GE, X86_XOP_CC_EQ, X86_XOP_CC_NEQ, X86_XOP_CC_FALSE, X86_XOP_CC_TRUE, } x86_xop_cc; //> AVX broadcast type typedef enum x86_avx_bcast { X86_AVX_BCAST_INVALID = 0, // Uninitialized. X86_AVX_BCAST_2, // AVX512 broadcast type {1to2} X86_AVX_BCAST_4, // AVX512 broadcast type {1to4} X86_AVX_BCAST_8, // AVX512 broadcast type {1to8} X86_AVX_BCAST_16, // AVX512 broadcast type {1to16} } x86_avx_bcast; //> SSE Code Condition type typedef enum x86_sse_cc { X86_SSE_CC_INVALID = 0, // Uninitialized. X86_SSE_CC_EQ, X86_SSE_CC_LT, X86_SSE_CC_LE, X86_SSE_CC_UNORD, X86_SSE_CC_NEQ, X86_SSE_CC_NLT, X86_SSE_CC_NLE, X86_SSE_CC_ORD, } x86_sse_cc; //> AVX Code Condition type typedef enum x86_avx_cc { X86_AVX_CC_INVALID = 0, // Uninitialized. X86_AVX_CC_EQ, X86_AVX_CC_LT, X86_AVX_CC_LE, X86_AVX_CC_UNORD, X86_AVX_CC_NEQ, X86_AVX_CC_NLT, X86_AVX_CC_NLE, X86_AVX_CC_ORD, X86_AVX_CC_EQ_UQ, X86_AVX_CC_NGE, X86_AVX_CC_NGT, X86_AVX_CC_FALSE, X86_AVX_CC_NEQ_OQ, X86_AVX_CC_GE, X86_AVX_CC_GT, X86_AVX_CC_TRUE, X86_AVX_CC_EQ_OS, X86_AVX_CC_LT_OQ, X86_AVX_CC_LE_OQ, X86_AVX_CC_UNORD_S, X86_AVX_CC_NEQ_US, X86_AVX_CC_NLT_UQ, X86_AVX_CC_NLE_UQ, X86_AVX_CC_ORD_S, X86_AVX_CC_EQ_US, X86_AVX_CC_NGE_UQ, X86_AVX_CC_NGT_UQ, X86_AVX_CC_FALSE_OS, X86_AVX_CC_NEQ_OS, X86_AVX_CC_GE_OQ, X86_AVX_CC_GT_OQ, X86_AVX_CC_TRUE_US, } x86_avx_cc; //> AVX static rounding mode type typedef enum x86_avx_rm { X86_AVX_RM_INVALID = 0, // Uninitialized. X86_AVX_RM_RN, // Round to nearest X86_AVX_RM_RD, // Round down X86_AVX_RM_RU, // Round up X86_AVX_RM_RZ, // Round toward zero } x86_avx_rm; //> Instruction prefixes - to be used in cs_x86.prefix[] typedef enum x86_prefix { X86_PREFIX_LOCK = 0xf0, // lock (cs_x86.prefix[0] X86_PREFIX_REP = 0xf3, // rep (cs_x86.prefix[0] X86_PREFIX_REPE = 0xf3, // repe/repz (cs_x86.prefix[0] X86_PREFIX_REPNE = 0xf2, // repne/repnz (cs_x86.prefix[0] X86_PREFIX_CS = 0x2e, // segment override CS (cs_x86.prefix[1] X86_PREFIX_SS = 0x36, // segment override SS (cs_x86.prefix[1] X86_PREFIX_DS = 0x3e, // segment override DS (cs_x86.prefix[1] X86_PREFIX_ES = 0x26, // segment override ES (cs_x86.prefix[1] X86_PREFIX_FS = 0x64, // segment override FS (cs_x86.prefix[1] X86_PREFIX_GS = 0x65, // segment override GS (cs_x86.prefix[1] X86_PREFIX_OPSIZE = 0x66, // operand-size override (cs_x86.prefix[2] X86_PREFIX_ADDRSIZE = 0x67, // address-size override (cs_x86.prefix[3] } x86_prefix; // Instruction's operand referring to memory // This is associated with X86_OP_MEM operand type above typedef struct x86_op_mem { x86_reg segment; // segment register (or X86_REG_INVALID if irrelevant) x86_reg base; // base register (or X86_REG_INVALID if irrelevant) x86_reg index; // index register (or X86_REG_INVALID if irrelevant) int scale; // scale for index register int64_t disp; // displacement value } x86_op_mem; // Instruction operand typedef struct cs_x86_op { x86_op_type type; // operand type union { x86_reg reg; // register value for REG operand int64_t imm; // immediate value for IMM operand x86_op_mem mem; // base/index/scale/disp value for MEM operand }; // size of this operand (in bytes). uint8_t size; // How is this operand accessed? (READ, WRITE or READ\|WRITE) // This field is combined of cs_ac_type. // NOTE: this field is irrelevant if engine is compiled in DIET mode. uint8_t access; // AVX broadcast type, or 0 if irrelevant x86_avx_bcast avx_bcast; // AVX zero opmask {z} bool avx_zero_opmask; } cs_x86_op; // Instruction structure typedef struct cs_x86 { // Instruction prefix, which can be up to 4 bytes. // A prefix byte gets value 0 when irrelevant. // prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above) // prefix[1] indicates segment override (irrelevant for x86_64): // See X86_PREFIX_CS/SS/DS/ES/FS/GS above. // prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE) // prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE) uint8_t prefix[4]; // Instruction opcode, wich can be from 1 to 4 bytes in size. // This contains VEX opcode as well. // An trailing opcode byte gets value 0 when irrelevant. uint8_t opcode[4]; // REX prefix: only a non-zero value is relavant for x86_64 uint8_t rex; // Address size, which can be overrided with above prefix[5]. uint8_t addr_size; // ModR/M byte uint8_t modrm; // SIB value, or 0 when irrelevant. uint8_t sib; // Displacement value, or 0 when irrelevant. int32_t disp; / SIB state / // SIB index register, or X86_REG_INVALID when irrelevant. x86_reg sib_index; // SIB scale. only applicable if sib_index is relavant. int8_t sib_scale; // SIB base register, or X86_REG_INVALID when irrelevant. x86_reg sib_base; // XOP Code Condition x86_xop_cc xop_cc; // SSE Code Condition x86_sse_cc sse_cc; // AVX Code Condition x86_avx_cc avx_cc; // AVX Suppress all Exception bool avx_sae; // AVX static rounding mode x86_avx_rm avx_rm; // EFLAGS updated by this instruction. // This can be formed from OR combination of X86_EFLAGS_ symbols in x86.h uint64_t eflags; // Number of operands of this instruction, // or 0 when instruction has no operand. uint8_t op_count; cs_x86_op operands[8]; // operands for this instruction. } cs_x86; //> X86 instructions typedef enum x86_insn { X86_INS_INVALID = 0, X86_INS_AAA, X86_INS_AAD, X86_INS_AAM, X86_INS_AAS, X86_INS_FABS, X86_INS_ADC, X86_INS_ADCX, X86_INS_ADD, X86_INS_ADDPD, X86_INS_ADDPS, X86_INS_ADDSD, X86_INS_ADDSS, X86_INS_ADDSUBPD, X86_INS_ADDSUBPS, X86_INS_FADD, X86_INS_FIADD, X86_INS_FADDP, X86_INS_ADOX, X86_INS_AESDECLAST, X86_INS_AESDEC, X86_INS_AESENCLAST, X86_INS_AESENC, X86_INS_AESIMC, X86_INS_AESKEYGENASSIST, X86_INS_AND, X86_INS_ANDN, X86_INS_ANDNPD, X86_INS_ANDNPS, X86_INS_ANDPD, X86_INS_ANDPS, X86_INS_ARPL, X86_INS_BEXTR, X86_INS_BLCFILL, X86_INS_BLCI, X86_INS_BLCIC, X86_INS_BLCMSK, X86_INS_BLCS, X86_INS_BLENDPD, X86_INS_BLENDPS, X86_INS_BLENDVPD, X86_INS_BLENDVPS, X86_INS_BLSFILL, X86_INS_BLSI, X86_INS_BLSIC, X86_INS_BLSMSK, X86_INS_BLSR, X86_INS_BOUND, X86_INS_BSF, X86_INS_BSR, X86_INS_BSWAP, X86_INS_BT, X86_INS_BTC, X86_INS_BTR, X86_INS_BTS, X86_INS_BZHI, X86_INS_CALL, X86_INS_CBW, X86_INS_CDQ, X86_INS_CDQE, X86_INS_FCHS, X86_INS_CLAC, X86_INS_CLC, X86_INS_CLD, X86_INS_CLFLUSH, X86_INS_CLFLUSHOPT, X86_INS_CLGI, X86_INS_CLI, X86_INS_CLTS, X86_INS_CLWB, X86_INS_CMC, X86_INS_CMOVA, X86_INS_CMOVAE, X86_INS_CMOVB, X86_INS_CMOVBE, X86_INS_FCMOVBE, X86_INS_FCMOVB, X86_INS_CMOVE, X86_INS_FCMOVE, X86_INS_CMOVG, X86_INS_CMOVGE, X86_INS_CMOVL, X86_INS_CMOVLE, X86_INS_FCMOVNBE, X86_INS_FCMOVNB, X86_INS_CMOVNE, X86_INS_FCMOVNE, X86_INS_CMOVNO, X86_INS_CMOVNP, X86_INS_FCMOVNU, X86_INS_CMOVNS, X86_INS_CMOVO, X86_INS_CMOVP, X86_INS_FCMOVU, X86_INS_CMOVS, X86_INS_CMP, X86_INS_CMPPD, X86_INS_CMPPS, X86_INS_CMPSB, X86_INS_CMPSD, X86_INS_CMPSQ, X86_INS_CMPSS, X86_INS_CMPSW, X86_INS_CMPXCHG16B, X86_INS_CMPXCHG, X86_INS_CMPXCHG8B, X86_INS_COMISD, X86_INS_COMISS, X86_INS_FCOMP, X86_INS_FCOMPI, X86_INS_FCOMI, X86_INS_FCOM, X86_INS_FCOS, X86_INS_CPUID, X86_INS_CQO, X86_INS_CRC32, X86_INS_CVTDQ2PD, X86_INS_CVTDQ2PS, X86_INS_CVTPD2DQ, X86_INS_CVTPD2PS, X86_INS_CVTPS2DQ, X86_INS_CVTPS2PD, X86_INS_CVTSD2SI, X86_INS_CVTSD2SS, X86_INS_CVTSI2SD, X86_INS_CVTSI2SS, X86_INS_CVTSS2SD, X86_INS_CVTSS2SI, X86_INS_CVTTPD2DQ, X86_INS_CVTTPS2DQ, X86_INS_CVTTSD2SI, X86_INS_CVTTSS2SI, X86_INS_CWD, X86_INS_CWDE, X86_INS_DAA, X86_INS_DAS, X86_INS_DATA16, X86_INS_DEC, X86_INS_DIV, X86_INS_DIVPD, X86_INS_DIVPS, X86_INS_FDIVR, X86_INS_FIDIVR, X86_INS_FDIVRP, X86_INS_DIVSD, X86_INS_DIVSS, X86_INS_FDIV, X86_INS_FIDIV, X86_INS_FDIVP, X86_INS_DPPD, X86_INS_DPPS, X86_INS_RET, X86_INS_ENCLS, X86_INS_ENCLU, X86_INS_ENTER, X86_INS_EXTRACTPS, X86_INS_EXTRQ, X86_INS_F2XM1, X86_INS_LCALL, X86_INS_LJMP, X86_INS_FBLD, X86_INS_FBSTP, X86_INS_FCOMPP, X86_INS_FDECSTP, X86_INS_FEMMS, X86_INS_FFREE, X86_INS_FICOM, X86_INS_FICOMP, X86_INS_FINCSTP, X86_INS_FLDCW, X86_INS_FLDENV, X86_INS_FLDL2E, X86_INS_FLDL2T, X86_INS_FLDLG2, X86_INS_FLDLN2, X86_INS_FLDPI, X86_INS_FNCLEX, X86_INS_FNINIT, X86_INS_FNOP, X86_INS_FNSTCW, X86_INS_FNSTSW, X86_INS_FPATAN, X86_INS_FPREM, X86_INS_FPREM1, X86_INS_FPTAN, X86_INS_FFREEP, X86_INS_FRNDINT, X86_INS_FRSTOR, X86_INS_FNSAVE, X86_INS_FSCALE, X86_INS_FSETPM, X86_INS_FSINCOS, X86_INS_FNSTENV, X86_INS_FXAM, X86_INS_FXRSTOR, X86_INS_FXRSTOR64, X86_INS_FXSAVE, X86_INS_FXSAVE64, X86_INS_FXTRACT, X86_INS_FYL2X, X86_INS_FYL2XP1, X86_INS_MOVAPD, X86_INS_MOVAPS, X86_INS_ORPD, X86_INS_ORPS, X86_INS_VMOVAPD, X86_INS_VMOVAPS, X86_INS_XORPD, X86_INS_XORPS, X86_INS_GETSEC, X86_INS_HADDPD, X86_INS_HADDPS, X86_INS_HLT, X86_INS_HSUBPD, X86_INS_HSUBPS, X86_INS_IDIV, X86_INS_FILD, X86_INS_IMUL, X86_INS_IN, X86_INS_INC, X86_INS_INSB, X86_INS_INSERTPS, X86_INS_INSERTQ, X86_INS_INSD, X86_INS_INSW, X86_INS_INT, X86_INS_INT1, X86_INS_INT3, X86_INS_INTO, X86_INS_INVD, X86_INS_INVEPT, X86_INS_INVLPG, X86_INS_INVLPGA, X86_INS_INVPCID, X86_INS_INVVPID, X86_INS_IRET, X86_INS_IRETD, X86_INS_IRETQ, X86_INS_FISTTP, X86_INS_FIST, X86_INS_FISTP, X86_INS_UCOMISD, X86_INS_UCOMISS, X86_INS_VCOMISD, X86_INS_VCOMISS, X86_INS_VCVTSD2SS, X86_INS_VCVTSI2SD, X86_INS_VCVTSI2SS, X86_INS_VCVTSS2SD, X86_INS_VCVTTSD2SI, X86_INS_VCVTTSD2USI, X86_INS_VCVTTSS2SI, X86_INS_VCVTTSS2USI, X86_INS_VCVTUSI2SD, X86_INS_VCVTUSI2SS, X86_INS_VUCOMISD, X86_INS_VUCOMISS, X86_INS_JAE, X86_INS_JA, X86_INS_JBE, X86_INS_JB, X86_INS_JCXZ, X86_INS_JECXZ, X86_INS_JE, X86_INS_JGE, X86_INS_JG, X86_INS_JLE, X86_INS_JL, X86_INS_JMP, X86_INS_JNE, X86_INS_JNO, X86_INS_JNP, X86_INS_JNS, X86_INS_JO, X86_INS_JP, X86_INS_JRCXZ, X86_INS_JS, X86_INS_KANDB, X86_INS_KANDD, X86_INS_KANDNB, X86_INS_KANDND, X86_INS_KANDNQ, X86_INS_KANDNW, X86_INS_KANDQ, X86_INS_KANDW, X86_INS_KMOVB, X86_INS_KMOVD, X86_INS_KMOVQ, X86_INS_KMOVW, X86_INS_KNOTB, X86_INS_KNOTD, X86_INS_KNOTQ, X86_INS_KNOTW, X86_INS_KORB, X86_INS_KORD, X86_INS_KORQ, X86_INS_KORTESTB, X86_INS_KORTESTD, X86_INS_KORTESTQ, X86_INS_KORTESTW, X86_INS_KORW, X86_INS_KSHIFTLB, X86_INS_KSHIFTLD, X86_INS_KSHIFTLQ, X86_INS_KSHIFTLW, X86_INS_KSHIFTRB, X86_INS_KSHIFTRD, X86_INS_KSHIFTRQ, X86_INS_KSHIFTRW, X86_INS_KUNPCKBW, X86_INS_KXNORB, X86_INS_KXNORD, X86_INS_KXNORQ, X86_INS_KXNORW, X86_INS_KXORB, X86_INS_KXORD, X86_INS_KXORQ, X86_INS_KXORW, X86_INS_LAHF, X86_INS_LAR, X86_INS_LDDQU, X86_INS_LDMXCSR, X86_INS_LDS, X86_INS_FLDZ, X86_INS_FLD1, X86_INS_FLD, X86_INS_LEA, X86_INS_LEAVE, X86_INS_LES, X86_INS_LFENCE, X86_INS_LFS, X86_INS_LGDT, X86_INS_LGS, X86_INS_LIDT, X86_INS_LLDT, X86_INS_LMSW, X86_INS_OR, X86_INS_SUB, X86_INS_XOR, X86_INS_LODSB, X86_INS_LODSD, X86_INS_LODSQ, X86_INS_LODSW, X86_INS_LOOP, X86_INS_LOOPE, X86_INS_LOOPNE, X86_INS_RETF, X86_INS_RETFQ, X86_INS_LSL, X86_INS_LSS, X86_INS_LTR, X86_INS_XADD, X86_INS_LZCNT, X86_INS_MASKMOVDQU, X86_INS_MAXPD, X86_INS_MAXPS, X86_INS_MAXSD, X86_INS_MAXSS, X86_INS_MFENCE, X86_INS_MINPD, X86_INS_MINPS, X86_INS_MINSD, X86_INS_MINSS, X86_INS_CVTPD2PI, X86_INS_CVTPI2PD, X86_INS_CVTPI2PS, X86_INS_CVTPS2PI, X86_INS_CVTTPD2PI, X86_INS_CVTTPS2PI, X86_INS_EMMS, X86_INS_MASKMOVQ, X86_INS_MOVD, X86_INS_MOVDQ2Q, X86_INS_MOVNTQ, X86_INS_MOVQ2DQ, X86_INS_MOVQ, X86_INS_PABSB, X86_INS_PABSD, X86_INS_PABSW, X86_INS_PACKSSDW, X86_INS_PACKSSWB, X86_INS_PACKUSWB, X86_INS_PADDB, X86_INS_PADDD, X86_INS_PADDQ, X86_INS_PADDSB, X86_INS_PADDSW, X86_INS_PADDUSB, X86_INS_PADDUSW, X86_INS_PADDW, X86_INS_PALIGNR, X86_INS_PANDN, X86_INS_PAND, X86_INS_PAVGB, X86_INS_PAVGW, X86_INS_PCMPEQB, X86_INS_PCMPEQD, X86_INS_PCMPEQW, X86_INS_PCMPGTB, X86_INS_PCMPGTD, X86_INS_PCMPGTW, X86_INS_PEXTRW, X86_INS_PHADDSW, X86_INS_PHADDW, X86_INS_PHADDD, X86_INS_PHSUBD, X86_INS_PHSUBSW, X86_INS_PHSUBW, X86_INS_PINSRW, X86_INS_PMADDUBSW, X86_INS_PMADDWD, X86_INS_PMAXSW, X86_INS_PMAXUB, X86_INS_PMINSW, X86_INS_PMINUB, X86_INS_PMOVMSKB, X86_INS_PMULHRSW, X86_INS_PMULHUW, X86_INS_PMULHW, X86_INS_PMULLW, X86_INS_PMULUDQ, X86_INS_POR, X86_INS_PSADBW, X86_INS_PSHUFB, X86_INS_PSHUFW, X86_INS_PSIGNB, X86_INS_PSIGND, X86_INS_PSIGNW, X86_INS_PSLLD, X86_INS_PSLLQ, X86_INS_PSLLW, X86_INS_PSRAD, X86_INS_PSRAW, X86_INS_PSRLD, X86_INS_PSRLQ, X86_INS_PSRLW, X86_INS_PSUBB, X86_INS_PSUBD, X86_INS_PSUBQ, X86_INS_PSUBSB, X86_INS_PSUBSW, X86_INS_PSUBUSB, X86_INS_PSUBUSW, X86_INS_PSUBW, X86_INS_PUNPCKHBW, X86_INS_PUNPCKHDQ, X86_INS_PUNPCKHWD, X86_INS_PUNPCKLBW, X86_INS_PUNPCKLDQ, X86_INS_PUNPCKLWD, X86_INS_PXOR, X86_INS_MONITOR, X86_INS_MONTMUL, X86_INS_MOV, X86_INS_MOVABS, X86_INS_MOVBE, X86_INS_MOVDDUP, X86_INS_MOVDQA, X86_INS_MOVDQU, X86_INS_MOVHLPS, X86_INS_MOVHPD, X86_INS_MOVHPS, X86_INS_MOVLHPS, X86_INS_MOVLPD, X86_INS_MOVLPS, X86_INS_MOVMSKPD, X86_INS_MOVMSKPS, X86_INS_MOVNTDQA, X86_INS_MOVNTDQ, X86_INS_MOVNTI, X86_INS_MOVNTPD, X86_INS_MOVNTPS, X86_INS_MOVNTSD, X86_INS_MOVNTSS, X86_INS_MOVSB, X86_INS_MOVSD, X86_INS_MOVSHDUP, X86_INS_MOVSLDUP, X86_INS_MOVSQ, X86_INS_MOVSS, X86_INS_MOVSW, X86_INS_MOVSX, X86_INS_MOVSXD, X86_INS_MOVUPD, X86_INS_MOVUPS, X86_INS_MOVZX, X86_INS_MPSADBW, X86_INS_MUL, X86_INS_MULPD, X86_INS_MULPS, X86_INS_MULSD, X86_INS_MULSS, X86_INS_MULX, X86_INS_FMUL, X86_INS_FIMUL, X86_INS_FMULP, X86_INS_MWAIT, X86_INS_NEG, X86_INS_NOP, X86_INS_NOT, X86_INS_OUT, X86_INS_OUTSB, X86_INS_OUTSD, X86_INS_OUTSW, X86_INS_PACKUSDW, X86_INS_PAUSE, X86_INS_PAVGUSB, X86_INS_PBLENDVB, X86_INS_PBLENDW, X86_INS_PCLMULQDQ, X86_INS_PCMPEQQ, X86_INS_PCMPESTRI, X86_INS_PCMPESTRM, X86_INS_PCMPGTQ, X86_INS_PCMPISTRI, X86_INS_PCMPISTRM, X86_INS_PCOMMIT, X86_INS_PDEP, X86_INS_PEXT, X86_INS_PEXTRB, X86_INS_PEXTRD, X86_INS_PEXTRQ, X86_INS_PF2ID, X86_INS_PF2IW, X86_INS_PFACC, X86_INS_PFADD, X86_INS_PFCMPEQ, X86_INS_PFCMPGE, X86_INS_PFCMPGT, X86_INS_PFMAX, X86_INS_PFMIN, X86_INS_PFMUL, X86_INS_PFNACC, X86_INS_PFPNACC, X86_INS_PFRCPIT1, X86_INS_PFRCPIT2, X86_INS_PFRCP, X86_INS_PFRSQIT1, X86_INS_PFRSQRT, X86_INS_PFSUBR, X86_INS_PFSUB, X86_INS_PHMINPOSUW, X86_INS_PI2FD, X86_INS_PI2FW, X86_INS_PINSRB, X86_INS_PINSRD, X86_INS_PINSRQ, X86_INS_PMAXSB, X86_INS_PMAXSD, X86_INS_PMAXUD, X86_INS_PMAXUW, X86_INS_PMINSB, X86_INS_PMINSD, X86_INS_PMINUD, X86_INS_PMINUW, X86_INS_PMOVSXBD, X86_INS_PMOVSXBQ, X86_INS_PMOVSXBW, X86_INS_PMOVSXDQ, X86_INS_PMOVSXWD, X86_INS_PMOVSXWQ, X86_INS_PMOVZXBD, X86_INS_PMOVZXBQ, X86_INS_PMOVZXBW, X86_INS_PMOVZXDQ, X86_INS_PMOVZXWD, X86_INS_PMOVZXWQ, X86_INS_PMULDQ, X86_INS_PMULHRW, X86_INS_PMULLD, X86_INS_POP, X86_INS_POPAW, X86_INS_POPAL, X86_INS_POPCNT, X86_INS_POPF, X86_INS_POPFD, X86_INS_POPFQ, X86_INS_PREFETCH, X86_INS_PREFETCHNTA, X86_INS_PREFETCHT0, X86_INS_PREFETCHT1, X86_INS_PREFETCHT2, X86_INS_PREFETCHW, X86_INS_PSHUFD, X86_INS_PSHUFHW, X86_INS_PSHUFLW, X86_INS_PSLLDQ, X86_INS_PSRLDQ, X86_INS_PSWAPD, X86_INS_PTEST, X86_INS_PUNPCKHQDQ, X86_INS_PUNPCKLQDQ, X86_INS_PUSH, X86_INS_PUSHAW, X86_INS_PUSHAL, X86_INS_PUSHF, X86_INS_PUSHFD, X86_INS_PUSHFQ, X86_INS_RCL, X86_INS_RCPPS, X86_INS_RCPSS, X86_INS_RCR, X86_INS_RDFSBASE, X86_INS_RDGSBASE, X86_INS_RDMSR, X86_INS_RDPMC, X86_INS_RDRAND, X86_INS_RDSEED, X86_INS_RDTSC, X86_INS_RDTSCP, X86_INS_ROL, X86_INS_ROR, X86_INS_RORX, X86_INS_ROUNDPD, X86_INS_ROUNDPS, X86_INS_ROUNDSD, X86_INS_ROUNDSS, X86_INS_RSM, X86_INS_RSQRTPS, X86_INS_RSQRTSS, X86_INS_SAHF, X86_INS_SAL, X86_INS_SALC, X86_INS_SAR, X86_INS_SARX, X86_INS_SBB, X86_INS_SCASB, X86_INS_SCASD, X86_INS_SCASQ, X86_INS_SCASW, X86_INS_SETAE, X86_INS_SETA, X86_INS_SETBE, X86_INS_SETB, X86_INS_SETE, X86_INS_SETGE, X86_INS_SETG, X86_INS_SETLE, X86_INS_SETL, X86_INS_SETNE, X86_INS_SETNO, X86_INS_SETNP, X86_INS_SETNS, X86_INS_SETO, X86_INS_SETP, X86_INS_SETS, X86_INS_SFENCE, X86_INS_SGDT, X86_INS_SHA1MSG1, X86_INS_SHA1MSG2, X86_INS_SHA1NEXTE, X86_INS_SHA1RNDS4, X86_INS_SHA256MSG1, X86_INS_SHA256MSG2, X86_INS_SHA256RNDS2, X86_INS_SHL, X86_INS_SHLD, X86_INS_SHLX, X86_INS_SHR, X86_INS_SHRD, X86_INS_SHRX, X86_INS_SHUFPD, X86_INS_SHUFPS, X86_INS_SIDT, X86_INS_FSIN, X86_INS_SKINIT, X86_INS_SLDT, X86_INS_SMSW, X86_INS_SQRTPD, X86_INS_SQRTPS, X86_INS_SQRTSD, X86_INS_SQRTSS, X86_INS_FSQRT, X86_INS_STAC, X86_INS_STC, X86_INS_STD, X86_INS_STGI, X86_INS_STI, X86_INS_STMXCSR, X86_INS_STOSB, X86_INS_STOSD, X86_INS_STOSQ, X86_INS_STOSW, X86_INS_STR, X86_INS_FST, X86_INS_FSTP, X86_INS_FSTPNCE, X86_INS_FXCH, X86_INS_SUBPD, X86_INS_SUBPS, X86_INS_FSUBR, X86_INS_FISUBR, X86_INS_FSUBRP, X86_INS_SUBSD, X86_INS_SUBSS, X86_INS_FSUB, X86_INS_FISUB, X86_INS_FSUBP, X86_INS_SWAPGS, X86_INS_SYSCALL, X86_INS_SYSENTER, X86_INS_SYSEXIT, X86_INS_SYSRET, X86_INS_T1MSKC, X86_INS_TEST, X86_INS_UD2, X86_INS_FTST, X86_INS_TZCNT, X86_INS_TZMSK, X86_INS_FUCOMPI, X86_INS_FUCOMI, X86_INS_FUCOMPP, X86_INS_FUCOMP, X86_INS_FUCOM, X86_INS_UD2B, X86_INS_UNPCKHPD, X86_INS_UNPCKHPS, X86_INS_UNPCKLPD, X86_INS_UNPCKLPS, X86_INS_VADDPD, X86_INS_VADDPS, X86_INS_VADDSD, X86_INS_VADDSS, X86_INS_VADDSUBPD, X86_INS_VADDSUBPS, X86_INS_VAESDECLAST, X86_INS_VAESDEC, X86_INS_VAESENCLAST, X86_INS_VAESENC, X86_INS_VAESIMC, X86_INS_VAESKEYGENASSIST, X86_INS_VALIGND, X86_INS_VALIGNQ, X86_INS_VANDNPD, X86_INS_VANDNPS, X86_INS_VANDPD, X86_INS_VANDPS, X86_INS_VBLENDMPD, X86_INS_VBLENDMPS, X86_INS_VBLENDPD, X86_INS_VBLENDPS, X86_INS_VBLENDVPD, X86_INS_VBLENDVPS, X86_INS_VBROADCASTF128, X86_INS_VBROADCASTI32X4, X86_INS_VBROADCASTI64X4, X86_INS_VBROADCASTSD, X86_INS_VBROADCASTSS, X86_INS_VCMPPD, X86_INS_VCMPPS, X86_INS_VCMPSD, X86_INS_VCMPSS, X86_INS_VCOMPRESSPD, X86_INS_VCOMPRESSPS, X86_INS_VCVTDQ2PD, X86_INS_VCVTDQ2PS, X86_INS_VCVTPD2DQX, X86_INS_VCVTPD2DQ, X86_INS_VCVTPD2PSX, X86_INS_VCVTPD2PS, X86_INS_VCVTPD2UDQ, X86_INS_VCVTPH2PS, X86_INS_VCVTPS2DQ, X86_INS_VCVTPS2PD, X86_INS_VCVTPS2PH, X86_INS_VCVTPS2UDQ, X86_INS_VCVTSD2SI, X86_INS_VCVTSD2USI, X86_INS_VCVTSS2SI, X86_INS_VCVTSS2USI, X86_INS_VCVTTPD2DQX, X86_INS_VCVTTPD2DQ, X86_INS_VCVTTPD2UDQ, X86_INS_VCVTTPS2DQ, X86_INS_VCVTTPS2UDQ, X86_INS_VCVTUDQ2PD, X86_INS_VCVTUDQ2PS, X86_INS_VDIVPD, X86_INS_VDIVPS, X86_INS_VDIVSD, X86_INS_VDIVSS, X86_INS_VDPPD, X86_INS_VDPPS, X86_INS_VERR, X86_INS_VERW, X86_INS_VEXP2PD, X86_INS_VEXP2PS, X86_INS_VEXPANDPD, X86_INS_VEXPANDPS, X86_INS_VEXTRACTF128, X86_INS_VEXTRACTF32X4, X86_INS_VEXTRACTF64X4, X86_INS_VEXTRACTI128, X86_INS_VEXTRACTI32X4, X86_INS_VEXTRACTI64X4, X86_INS_VEXTRACTPS, X86_INS_VFMADD132PD, X86_INS_VFMADD132PS, X86_INS_VFMADDPD, X86_INS_VFMADD213PD, X86_INS_VFMADD231PD, X86_INS_VFMADDPS, X86_INS_VFMADD213PS, X86_INS_VFMADD231PS, X86_INS_VFMADDSD, X86_INS_VFMADD213SD, X86_INS_VFMADD132SD, X86_INS_VFMADD231SD, X86_INS_VFMADDSS, X86_INS_VFMADD213SS, X86_INS_VFMADD132SS, X86_INS_VFMADD231SS, X86_INS_VFMADDSUB132PD, X86_INS_VFMADDSUB132PS, X86_INS_VFMADDSUBPD, X86_INS_VFMADDSUB213PD, X86_INS_VFMADDSUB231PD, X86_INS_VFMADDSUBPS, X86_INS_VFMADDSUB213PS, X86_INS_VFMADDSUB231PS, X86_INS_VFMSUB132PD, X86_INS_VFMSUB132PS, X86_INS_VFMSUBADD132PD, X86_INS_VFMSUBADD132PS, X86_INS_VFMSUBADDPD, X86_INS_VFMSUBADD213PD, X86_INS_VFMSUBADD231PD, X86_INS_VFMSUBADDPS, X86_INS_VFMSUBADD213PS, X86_INS_VFMSUBADD231PS, X86_INS_VFMSUBPD, X86_INS_VFMSUB213PD, X86_INS_VFMSUB231PD, X86_INS_VFMSUBPS, X86_INS_VFMSUB213PS, X86_INS_VFMSUB231PS, X86_INS_VFMSUBSD, X86_INS_VFMSUB213SD, X86_INS_VFMSUB132SD, X86_INS_VFMSUB231SD, X86_INS_VFMSUBSS, X86_INS_VFMSUB213SS, X86_INS_VFMSUB132SS, X86_INS_VFMSUB231SS, X86_INS_VFNMADD132PD, X86_INS_VFNMADD132PS, X86_INS_VFNMADDPD, X86_INS_VFNMADD213PD, X86_INS_VFNMADD231PD, X86_INS_VFNMADDPS, X86_INS_VFNMADD213PS, X86_INS_VFNMADD231PS, X86_INS_VFNMADDSD, X86_INS_VFNMADD213SD, X86_INS_VFNMADD132SD, X86_INS_VFNMADD231SD, X86_INS_VFNMADDSS, X86_INS_VFNMADD213SS, X86_INS_VFNMADD132SS, X86_INS_VFNMADD231SS, X86_INS_VFNMSUB132PD, X86_INS_VFNMSUB132PS, X86_INS_VFNMSUBPD, X86_INS_VFNMSUB213PD, X86_INS_VFNMSUB231PD, X86_INS_VFNMSUBPS, X86_INS_VFNMSUB213PS, X86_INS_VFNMSUB231PS, X86_INS_VFNMSUBSD, X86_INS_VFNMSUB213SD, X86_INS_VFNMSUB132SD, X86_INS_VFNMSUB231SD, X86_INS_VFNMSUBSS, X86_INS_VFNMSUB213SS, X86_INS_VFNMSUB132SS, X86_INS_VFNMSUB231SS, X86_INS_VFRCZPD, X86_INS_VFRCZPS, X86_INS_VFRCZSD, X86_INS_VFRCZSS, X86_INS_VORPD, X86_INS_VORPS, X86_INS_VXORPD, X86_INS_VXORPS, X86_INS_VGATHERDPD, X86_INS_VGATHERDPS, X86_INS_VGATHERPF0DPD, X86_INS_VGATHERPF0DPS, X86_INS_VGATHERPF0QPD, X86_INS_VGATHERPF0QPS, X86_INS_VGATHERPF1DPD, X86_INS_VGATHERPF1DPS, X86_INS_VGATHERPF1QPD, X86_INS_VGATHERPF1QPS, X86_INS_VGATHERQPD, X86_INS_VGATHERQPS, X86_INS_VHADDPD, X86_INS_VHADDPS, X86_INS_VHSUBPD, X86_INS_VHSUBPS, X86_INS_VINSERTF128, X86_INS_VINSERTF32X4, X86_INS_VINSERTF32X8, X86_INS_VINSERTF64X2, X86_INS_VINSERTF64X4, X86_INS_VINSERTI128, X86_INS_VINSERTI32X4, X86_INS_VINSERTI32X8, X86_INS_VINSERTI64X2, X86_INS_VINSERTI64X4, X86_INS_VINSERTPS, X86_INS_VLDDQU, X86_INS_VLDMXCSR, X86_INS_VMASKMOVDQU, X86_INS_VMASKMOVPD, X86_INS_VMASKMOVPS, X86_INS_VMAXPD, X86_INS_VMAXPS, X86_INS_VMAXSD, X86_INS_VMAXSS, X86_INS_VMCALL, X86_INS_VMCLEAR, X86_INS_VMFUNC, X86_INS_VMINPD, X86_INS_VMINPS, X86_INS_VMINSD, X86_INS_VMINSS, X86_INS_VMLAUNCH, X86_INS_VMLOAD, X86_INS_VMMCALL, X86_INS_VMOVQ, X86_INS_VMOVDDUP, X86_INS_VMOVD, X86_INS_VMOVDQA32, X86_INS_VMOVDQA64, X86_INS_VMOVDQA, X86_INS_VMOVDQU16, X86_INS_VMOVDQU32, X86_INS_VMOVDQU64, X86_INS_VMOVDQU8, X86_INS_VMOVDQU, X86_INS_VMOVHLPS, X86_INS_VMOVHPD, X86_INS_VMOVHPS, X86_INS_VMOVLHPS, X86_INS_VMOVLPD, X86_INS_VMOVLPS, X86_INS_VMOVMSKPD, X86_INS_VMOVMSKPS, X86_INS_VMOVNTDQA, X86_INS_VMOVNTDQ, X86_INS_VMOVNTPD, X86_INS_VMOVNTPS, X86_INS_VMOVSD, X86_INS_VMOVSHDUP, X86_INS_VMOVSLDUP, X86_INS_VMOVSS, X86_INS_VMOVUPD, X86_INS_VMOVUPS, X86_INS_VMPSADBW, X86_INS_VMPTRLD, X86_INS_VMPTRST, X86_INS_VMREAD, X86_INS_VMRESUME, X86_INS_VMRUN, X86_INS_VMSAVE, X86_INS_VMULPD, X86_INS_VMULPS, X86_INS_VMULSD, X86_INS_VMULSS, X86_INS_VMWRITE, X86_INS_VMXOFF, X86_INS_VMXON, X86_INS_VPABSB, X86_INS_VPABSD, X86_INS_VPABSQ, X86_INS_VPABSW, X86_INS_VPACKSSDW, X86_INS_VPACKSSWB, X86_INS_VPACKUSDW, X86_INS_VPACKUSWB, X86_INS_VPADDB, X86_INS_VPADDD, X86_INS_VPADDQ, X86_INS_VPADDSB, X86_INS_VPADDSW, X86_INS_VPADDUSB, X86_INS_VPADDUSW, X86_INS_VPADDW, X86_INS_VPALIGNR, X86_INS_VPANDD, X86_INS_VPANDND, X86_INS_VPANDNQ, X86_INS_VPANDN, X86_INS_VPANDQ, X86_INS_VPAND, X86_INS_VPAVGB, X86_INS_VPAVGW, X86_INS_VPBLENDD, X86_INS_VPBLENDMB, X86_INS_VPBLENDMD, X86_INS_VPBLENDMQ, X86_INS_VPBLENDMW, X86_INS_VPBLENDVB, X86_INS_VPBLENDW, X86_INS_VPBROADCASTB, X86_INS_VPBROADCASTD, X86_INS_VPBROADCASTMB2Q, X86_INS_VPBROADCASTMW2D, X86_INS_VPBROADCASTQ, X86_INS_VPBROADCASTW, X86_INS_VPCLMULQDQ, X86_INS_VPCMOV, X86_INS_VPCMPB, X86_INS_VPCMPD, X86_INS_VPCMPEQB, X86_INS_VPCMPEQD, X86_INS_VPCMPEQQ, X86_INS_VPCMPEQW, X86_INS_VPCMPESTRI, X86_INS_VPCMPESTRM, X86_INS_VPCMPGTB, X86_INS_VPCMPGTD, X86_INS_VPCMPGTQ, X86_INS_VPCMPGTW, X86_INS_VPCMPISTRI, X86_INS_VPCMPISTRM, X86_INS_VPCMPQ, X86_INS_VPCMPUB, X86_INS_VPCMPUD, X86_INS_VPCMPUQ, X86_INS_VPCMPUW, X86_INS_VPCMPW, X86_INS_VPCOMB, X86_INS_VPCOMD, X86_INS_VPCOMPRESSD, X86_INS_VPCOMPRESSQ, X86_INS_VPCOMQ, X86_INS_VPCOMUB, X86_INS_VPCOMUD, X86_INS_VPCOMUQ, X86_INS_VPCOMUW, X86_INS_VPCOMW, X86_INS_VPCONFLICTD, X86_INS_VPCONFLICTQ, X86_INS_VPERM2F128, X86_INS_VPERM2I128, X86_INS_VPERMD, X86_INS_VPERMI2D, X86_INS_VPERMI2PD, X86_INS_VPERMI2PS, X86_INS_VPERMI2Q, X86_INS_VPERMIL2PD, X86_INS_VPERMIL2PS, X86_INS_VPERMILPD, X86_INS_VPERMILPS, X86_INS_VPERMPD, X86_INS_VPERMPS, X86_INS_VPERMQ, X86_INS_VPERMT2D, X86_INS_VPERMT2PD, X86_INS_VPERMT2PS, X86_INS_VPERMT2Q, X86_INS_VPEXPANDD, X86_INS_VPEXPANDQ, X86_INS_VPEXTRB, X86_INS_VPEXTRD, X86_INS_VPEXTRQ, X86_INS_VPEXTRW, X86_INS_VPGATHERDD, X86_INS_VPGATHERDQ, X86_INS_VPGATHERQD, X86_INS_VPGATHERQQ, X86_INS_VPHADDBD, X86_INS_VPHADDBQ, X86_INS_VPHADDBW, X86_INS_VPHADDDQ, X86_INS_VPHADDD, X86_INS_VPHADDSW, X86_INS_VPHADDUBD, X86_INS_VPHADDUBQ, X86_INS_VPHADDUBW, X86_INS_VPHADDUDQ, X86_INS_VPHADDUWD, X86_INS_VPHADDUWQ, X86_INS_VPHADDWD, X86_INS_VPHADDWQ, X86_INS_VPHADDW, X86_INS_VPHMINPOSUW, X86_INS_VPHSUBBW, X86_INS_VPHSUBDQ, X86_INS_VPHSUBD, X86_INS_VPHSUBSW, X86_INS_VPHSUBWD, X86_INS_VPHSUBW, X86_INS_VPINSRB, X86_INS_VPINSRD, X86_INS_VPINSRQ, X86_INS_VPINSRW, X86_INS_VPLZCNTD, X86_INS_VPLZCNTQ, X86_INS_VPMACSDD, X86_INS_VPMACSDQH, X86_INS_VPMACSDQL, X86_INS_VPMACSSDD, X86_INS_VPMACSSDQH, X86_INS_VPMACSSDQL, X86_INS_VPMACSSWD, X86_INS_VPMACSSWW, X86_INS_VPMACSWD, X86_INS_VPMACSWW, X86_INS_VPMADCSSWD, X86_INS_VPMADCSWD, X86_INS_VPMADDUBSW, X86_INS_VPMADDWD, X86_INS_VPMASKMOVD, X86_INS_VPMASKMOVQ, X86_INS_VPMAXSB, X86_INS_VPMAXSD, X86_INS_VPMAXSQ, X86_INS_VPMAXSW, X86_INS_VPMAXUB, X86_INS_VPMAXUD, X86_INS_VPMAXUQ, X86_INS_VPMAXUW, X86_INS_VPMINSB, X86_INS_VPMINSD, X86_INS_VPMINSQ, X86_INS_VPMINSW, X86_INS_VPMINUB, X86_INS_VPMINUD, X86_INS_VPMINUQ, X86_INS_VPMINUW, X86_INS_VPMOVDB, X86_INS_VPMOVDW, X86_INS_VPMOVM2B, X86_INS_VPMOVM2D, X86_INS_VPMOVM2Q, X86_INS_VPMOVM2W, X86_INS_VPMOVMSKB, X86_INS_VPMOVQB, X86_INS_VPMOVQD, X86_INS_VPMOVQW, X86_INS_VPMOVSDB, X86_INS_VPMOVSDW, X86_INS_VPMOVSQB, X86_INS_VPMOVSQD, X86_INS_VPMOVSQW, X86_INS_VPMOVSXBD, X86_INS_VPMOVSXBQ, X86_INS_VPMOVSXBW, X86_INS_VPMOVSXDQ, X86_INS_VPMOVSXWD, X86_INS_VPMOVSXWQ, X86_INS_VPMOVUSDB, X86_INS_VPMOVUSDW, X86_INS_VPMOVUSQB, X86_INS_VPMOVUSQD, X86_INS_VPMOVUSQW, X86_INS_VPMOVZXBD, X86_INS_VPMOVZXBQ, X86_INS_VPMOVZXBW, X86_INS_VPMOVZXDQ, X86_INS_VPMOVZXWD, X86_INS_VPMOVZXWQ, X86_INS_VPMULDQ, X86_INS_VPMULHRSW, X86_INS_VPMULHUW, X86_INS_VPMULHW, X86_INS_VPMULLD, X86_INS_VPMULLQ, X86_INS_VPMULLW, X86_INS_VPMULUDQ, X86_INS_VPORD, X86_INS_VPORQ, X86_INS_VPOR, X86_INS_VPPERM, X86_INS_VPROTB, X86_INS_VPROTD, X86_INS_VPROTQ, X86_INS_VPROTW, X86_INS_VPSADBW, X86_INS_VPSCATTERDD, X86_INS_VPSCATTERDQ, X86_INS_VPSCATTERQD, X86_INS_VPSCATTERQQ, X86_INS_VPSHAB, X86_INS_VPSHAD, X86_INS_VPSHAQ, X86_INS_VPSHAW, X86_INS_VPSHLB, X86_INS_VPSHLD, X86_INS_VPSHLQ, X86_INS_VPSHLW, X86_INS_VPSHUFB, X86_INS_VPSHUFD, X86_INS_VPSHUFHW, X86_INS_VPSHUFLW, X86_INS_VPSIGNB, X86_INS_VPSIGND, X86_INS_VPSIGNW, X86_INS_VPSLLDQ, X86_INS_VPSLLD, X86_INS_VPSLLQ, X86_INS_VPSLLVD, X86_INS_VPSLLVQ, X86_INS_VPSLLW, X86_INS_VPSRAD, X86_INS_VPSRAQ, X86_INS_VPSRAVD, X86_INS_VPSRAVQ, X86_INS_VPSRAW, X86_INS_VPSRLDQ, X86_INS_VPSRLD, X86_INS_VPSRLQ, X86_INS_VPSRLVD, X86_INS_VPSRLVQ, X86_INS_VPSRLW, X86_INS_VPSUBB, X86_INS_VPSUBD, X86_INS_VPSUBQ, X86_INS_VPSUBSB, X86_INS_VPSUBSW, X86_INS_VPSUBUSB, X86_INS_VPSUBUSW, X86_INS_VPSUBW, X86_INS_VPTESTMD, X86_INS_VPTESTMQ, X86_INS_VPTESTNMD, X86_INS_VPTESTNMQ, X86_INS_VPTEST, X86_INS_VPUNPCKHBW, X86_INS_VPUNPCKHDQ, X86_INS_VPUNPCKHQDQ, X86_INS_VPUNPCKHWD, X86_INS_VPUNPCKLBW, X86_INS_VPUNPCKLDQ, X86_INS_VPUNPCKLQDQ, X86_INS_VPUNPCKLWD, X86_INS_VPXORD, X86_INS_VPXORQ, X86_INS_VPXOR, X86_INS_VRCP14PD, X86_INS_VRCP14PS, X86_INS_VRCP14SD, X86_INS_VRCP14SS, X86_INS_VRCP28PD, X86_INS_VRCP28PS, X86_INS_VRCP28SD, X86_INS_VRCP28SS, X86_INS_VRCPPS, X86_INS_VRCPSS, X86_INS_VRNDSCALEPD, X86_INS_VRNDSCALEPS, X86_INS_VRNDSCALESD, X86_INS_VRNDSCALESS, X86_INS_VROUNDPD, X86_INS_VROUNDPS, X86_INS_VROUNDSD, X86_INS_VROUNDSS, X86_INS_VRSQRT14PD, X86_INS_VRSQRT14PS, X86_INS_VRSQRT14SD, X86_INS_VRSQRT14SS, X86_INS_VRSQRT28PD, X86_INS_VRSQRT28PS, X86_INS_VRSQRT28SD, X86_INS_VRSQRT28SS, X86_INS_VRSQRTPS, X86_INS_VRSQRTSS, X86_INS_VSCATTERDPD, X86_INS_VSCATTERDPS, X86_INS_VSCATTERPF0DPD, X86_INS_VSCATTERPF0DPS, X86_INS_VSCATTERPF0QPD, X86_INS_VSCATTERPF0QPS, X86_INS_VSCATTERPF1DPD, X86_INS_VSCATTERPF1DPS, X86_INS_VSCATTERPF1QPD, X86_INS_VSCATTERPF1QPS, X86_INS_VSCATTERQPD, X86_INS_VSCATTERQPS, X86_INS_VSHUFPD, X86_INS_VSHUFPS, X86_INS_VSQRTPD, X86_INS_VSQRTPS, X86_INS_VSQRTSD, X86_INS_VSQRTSS, X86_INS_VSTMXCSR, X86_INS_VSUBPD, X86_INS_VSUBPS, X86_INS_VSUBSD, X86_INS_VSUBSS, X86_INS_VTESTPD, X86_INS_VTESTPS, X86_INS_VUNPCKHPD, X86_INS_VUNPCKHPS, X86_INS_VUNPCKLPD, X86_INS_VUNPCKLPS, X86_INS_VZEROALL, X86_INS_VZEROUPPER, X86_INS_WAIT, X86_INS_WBINVD, X86_INS_WRFSBASE, X86_INS_WRGSBASE, X86_INS_WRMSR, X86_INS_XABORT, X86_INS_XACQUIRE, X86_INS_XBEGIN, X86_INS_XCHG, X86_INS_XCRYPTCBC, X86_INS_XCRYPTCFB, X86_INS_XCRYPTCTR, X86_INS_XCRYPTECB, X86_INS_XCRYPTOFB, X86_INS_XEND, X86_INS_XGETBV, X86_INS_XLATB, X86_INS_XRELEASE, X86_INS_XRSTOR, X86_INS_XRSTOR64, X86_INS_XRSTORS, X86_INS_XRSTORS64, X86_INS_XSAVE, X86_INS_XSAVE64, X86_INS_XSAVEC, X86_INS_XSAVEC64, X86_INS_XSAVEOPT, X86_INS_XSAVEOPT64, X86_INS_XSAVES, X86_INS_XSAVES64, X86_INS_XSETBV, X86_INS_XSHA1, X86_INS_XSHA256, X86_INS_XSTORE, X86_INS_XTEST, X86_INS_FDISI8087_NOP, X86_INS_FENI8087_NOP, X86_INS_ENDING, // mark the end of the list of insn } x86_insn; //> Group of X86 instructions typedef enum x86_insn_group { X86_GRP_INVALID = 0, // = CS_GRP_INVALID //> Generic groups // all jump instructions (conditional+direct+indirect jumps) X86_GRP_JUMP, // = CS_GRP_JUMP // all call instructions X86_GRP_CALL, // = CS_GRP_CALL // all return instructions X86_GRP_RET, // = CS_GRP_RET // all interrupt instructions (int+syscall) X86_GRP_INT, // = CS_GRP_INT // all interrupt return instructions X86_GRP_IRET, // = CS_GRP_IRET // all privileged instructions X86_GRP_PRIVILEGE, // = CS_GRP_PRIVILEGE //> Architecture-specific groups X86_GRP_VM = 128, // all virtualization instructions (VT-x + AMD-V) X86_GRP_3DNOW, X86_GRP_AES, X86_GRP_ADX, X86_GRP_AVX, X86_GRP_AVX2, X86_GRP_AVX512, X86_GRP_BMI, X86_GRP_BMI2, X86_GRP_CMOV, X86_GRP_F16C, X86_GRP_FMA, X86_GRP_FMA4, X86_GRP_FSGSBASE, X86_GRP_HLE, X86_GRP_MMX, X86_GRP_MODE32, X86_GRP_MODE64, X86_GRP_RTM, X86_GRP_SHA, X86_GRP_SSE1, X86_GRP_SSE2, X86_GRP_SSE3, X86_GRP_SSE41, X86_GRP_SSE42, X86_GRP_SSE4A, X86_GRP_SSSE3, X86_GRP_PCLMUL, X86_GRP_XOP, X86_GRP_CDI, X86_GRP_ERI, X86_GRP_TBM, X86_GRP_16BITMODE, X86_GRP_NOT64BITMODE, X86_GRP_SGX, X86_GRP_DQI, X86_GRP_BWI, X86_GRP_PFI, X86_GRP_VLX, X86_GRP_SMAP, X86_GRP_NOVLX, X86_GRP_ENDING } x86_insn_group; #ifdef __cplusplus } #endif #endif	{ "language": "Assembly" }
/* SPDX-License-Identifier: BSD-2-Clause / / * Copyright (c) 2019, Linaro Limited / #include <asm.S> / * This function is the bottom of the user call stack. Mark it as such so that * the unwinding code won't try to go further down. * We need an assembly wrapper because Clang does not accept asm(".cantunwind") * in a C function: * * user_ta_header.c:44:6: error: .fnstart must precede .cantunwind directive * asm(".cantunwind"); * ^ */ FUNC __ta_entry, : UNWIND( .cantunwind) bl __ta_entry_c END_FUNC __ta_entry	{ "language": "Assembly" }
/* * Copyright 2015 The LibYuv Project Authors. All rights reserved. * * Use of this source code is governed by a BSD-style license * that can be found in the LICENSE file in the root of the source * tree. An additional intellectual property rights grant can be found * in the file PATENTS. All contributing project authors may * be found in the AUTHORS file in the root of the source tree. / #include "libyuv/row.h" #include "libyuv/rotate_row.h" #ifdef __cplusplus namespace libyuv { extern "C" { #endif // This module is for GCC x86 and x64. #if !defined(LIBYUV_DISABLE_X86) && \ (defined(__x86_64__) \|\| (defined(__i386__) && !defined(_MSC_VER))) // Transpose 8x8. 32 or 64 bit, but not NaCL for 64 bit. #if defined(HAS_TRANSPOSEWX8_SSSE3) void TransposeWx8_SSSE3(const uint8 src, int src_stride, uint8* dst, int dst_stride, int width) { asm volatile ( // Read in the data from the source pointer. // First round of bit swap. LABELALIGN "1: \n" "movq (%0),%%xmm0 \n" "movq (%0,%3),%%xmm1 \n" "lea (%0,%3,2),%0 \n" "punpcklbw %%xmm1,%%xmm0 \n" "movq (%0),%%xmm2 \n" "movdqa %%xmm0,%%xmm1 \n" "palignr $0x8,%%xmm1,%%xmm1 \n" "movq (%0,%3),%%xmm3 \n" "lea (%0,%3,2),%0 \n" "punpcklbw %%xmm3,%%xmm2 \n" "movdqa %%xmm2,%%xmm3 \n" "movq (%0),%%xmm4 \n" "palignr $0x8,%%xmm3,%%xmm3 \n" "movq (%0,%3),%%xmm5 \n" "lea (%0,%3,2),%0 \n" "punpcklbw %%xmm5,%%xmm4 \n" "movdqa %%xmm4,%%xmm5 \n" "movq (%0),%%xmm6 \n" "palignr $0x8,%%xmm5,%%xmm5 \n" "movq (%0,%3),%%xmm7 \n" "lea (%0,%3,2),%0 \n" "punpcklbw %%xmm7,%%xmm6 \n" "neg %3 \n" "movdqa %%xmm6,%%xmm7 \n" "lea 0x8(%0,%3,8),%0 \n" "palignr $0x8,%%xmm7,%%xmm7 \n" "neg %3 \n" // Second round of bit swap. "punpcklwd %%xmm2,%%xmm0 \n" "punpcklwd %%xmm3,%%xmm1 \n" "movdqa %%xmm0,%%xmm2 \n" "movdqa %%xmm1,%%xmm3 \n" "palignr $0x8,%%xmm2,%%xmm2 \n" "palignr $0x8,%%xmm3,%%xmm3 \n" "punpcklwd %%xmm6,%%xmm4 \n" "punpcklwd %%xmm7,%%xmm5 \n" "movdqa %%xmm4,%%xmm6 \n" "movdqa %%xmm5,%%xmm7 \n" "palignr $0x8,%%xmm6,%%xmm6 \n" "palignr $0x8,%%xmm7,%%xmm7 \n" // Third round of bit swap. // Write to the destination pointer. "punpckldq %%xmm4,%%xmm0 \n" "movq %%xmm0,(%1) \n" "movdqa %%xmm0,%%xmm4 \n" "palignr $0x8,%%xmm4,%%xmm4 \n" "movq %%xmm4,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "punpckldq %%xmm6,%%xmm2 \n" "movdqa %%xmm2,%%xmm6 \n" "movq %%xmm2,(%1) \n" "palignr $0x8,%%xmm6,%%xmm6 \n" "punpckldq %%xmm5,%%xmm1 \n" "movq %%xmm6,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "movdqa %%xmm1,%%xmm5 \n" "movq %%xmm1,(%1) \n" "palignr $0x8,%%xmm5,%%xmm5 \n" "movq %%xmm5,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "punpckldq %%xmm7,%%xmm3 \n" "movq %%xmm3,(%1) \n" "movdqa %%xmm3,%%xmm7 \n" "palignr $0x8,%%xmm7,%%xmm7 \n" "sub $0x8,%2 \n" "movq %%xmm7,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "jg 1b \n" : "+r"(src), // %0 "+r"(dst), // %1 "+r"(width) // %2 : "r"((intptr_t)(src_stride)), // %3 "r"((intptr_t)(dst_stride)) // %4 : "memory", "cc", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" ); } #endif // defined(HAS_TRANSPOSEWX8_SSSE3) // Transpose 16x8. 64 bit #if defined(HAS_TRANSPOSEWX8_FAST_SSSE3) void TransposeWx8_Fast_SSSE3(const uint8* src, int src_stride, uint8* dst, int dst_stride, int width) { asm volatile ( // Read in the data from the source pointer. // First round of bit swap. LABELALIGN "1: \n" "movdqu (%0),%%xmm0 \n" "movdqu (%0,%3),%%xmm1 \n" "lea (%0,%3,2),%0 \n" "movdqa %%xmm0,%%xmm8 \n" "punpcklbw %%xmm1,%%xmm0 \n" "punpckhbw %%xmm1,%%xmm8 \n" "movdqu (%0),%%xmm2 \n" "movdqa %%xmm0,%%xmm1 \n" "movdqa %%xmm8,%%xmm9 \n" "palignr $0x8,%%xmm1,%%xmm1 \n" "palignr $0x8,%%xmm9,%%xmm9 \n" "movdqu (%0,%3),%%xmm3 \n" "lea (%0,%3,2),%0 \n" "movdqa %%xmm2,%%xmm10 \n" "punpcklbw %%xmm3,%%xmm2 \n" "punpckhbw %%xmm3,%%xmm10 \n" "movdqa %%xmm2,%%xmm3 \n" "movdqa %%xmm10,%%xmm11 \n" "movdqu (%0),%%xmm4 \n" "palignr $0x8,%%xmm3,%%xmm3 \n" "palignr $0x8,%%xmm11,%%xmm11 \n" "movdqu (%0,%3),%%xmm5 \n" "lea (%0,%3,2),%0 \n" "movdqa %%xmm4,%%xmm12 \n" "punpcklbw %%xmm5,%%xmm4 \n" "punpckhbw %%xmm5,%%xmm12 \n" "movdqa %%xmm4,%%xmm5 \n" "movdqa %%xmm12,%%xmm13 \n" "movdqu (%0),%%xmm6 \n" "palignr $0x8,%%xmm5,%%xmm5 \n" "palignr $0x8,%%xmm13,%%xmm13 \n" "movdqu (%0,%3),%%xmm7 \n" "lea (%0,%3,2),%0 \n" "movdqa %%xmm6,%%xmm14 \n" "punpcklbw %%xmm7,%%xmm6 \n" "punpckhbw %%xmm7,%%xmm14 \n" "neg %3 \n" "movdqa %%xmm6,%%xmm7 \n" "movdqa %%xmm14,%%xmm15 \n" "lea 0x10(%0,%3,8),%0 \n" "palignr $0x8,%%xmm7,%%xmm7 \n" "palignr $0x8,%%xmm15,%%xmm15 \n" "neg %3 \n" // Second round of bit swap. "punpcklwd %%xmm2,%%xmm0 \n" "punpcklwd %%xmm3,%%xmm1 \n" "movdqa %%xmm0,%%xmm2 \n" "movdqa %%xmm1,%%xmm3 \n" "palignr $0x8,%%xmm2,%%xmm2 \n" "palignr $0x8,%%xmm3,%%xmm3 \n" "punpcklwd %%xmm6,%%xmm4 \n" "punpcklwd %%xmm7,%%xmm5 \n" "movdqa %%xmm4,%%xmm6 \n" "movdqa %%xmm5,%%xmm7 \n" "palignr $0x8,%%xmm6,%%xmm6 \n" "palignr $0x8,%%xmm7,%%xmm7 \n" "punpcklwd %%xmm10,%%xmm8 \n" "punpcklwd %%xmm11,%%xmm9 \n" "movdqa %%xmm8,%%xmm10 \n" "movdqa %%xmm9,%%xmm11 \n" "palignr $0x8,%%xmm10,%%xmm10 \n" "palignr $0x8,%%xmm11,%%xmm11 \n" "punpcklwd %%xmm14,%%xmm12 \n" "punpcklwd %%xmm15,%%xmm13 \n" "movdqa %%xmm12,%%xmm14 \n" "movdqa %%xmm13,%%xmm15 \n" "palignr $0x8,%%xmm14,%%xmm14 \n" "palignr $0x8,%%xmm15,%%xmm15 \n" // Third round of bit swap. // Write to the destination pointer. "punpckldq %%xmm4,%%xmm0 \n" "movq %%xmm0,(%1) \n" "movdqa %%xmm0,%%xmm4 \n" "palignr $0x8,%%xmm4,%%xmm4 \n" "movq %%xmm4,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "punpckldq %%xmm6,%%xmm2 \n" "movdqa %%xmm2,%%xmm6 \n" "movq %%xmm2,(%1) \n" "palignr $0x8,%%xmm6,%%xmm6 \n" "punpckldq %%xmm5,%%xmm1 \n" "movq %%xmm6,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "movdqa %%xmm1,%%xmm5 \n" "movq %%xmm1,(%1) \n" "palignr $0x8,%%xmm5,%%xmm5 \n" "movq %%xmm5,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "punpckldq %%xmm7,%%xmm3 \n" "movq %%xmm3,(%1) \n" "movdqa %%xmm3,%%xmm7 \n" "palignr $0x8,%%xmm7,%%xmm7 \n" "movq %%xmm7,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "punpckldq %%xmm12,%%xmm8 \n" "movq %%xmm8,(%1) \n" "movdqa %%xmm8,%%xmm12 \n" "palignr $0x8,%%xmm12,%%xmm12 \n" "movq %%xmm12,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "punpckldq %%xmm14,%%xmm10 \n" "movdqa %%xmm10,%%xmm14 \n" "movq %%xmm10,(%1) \n" "palignr $0x8,%%xmm14,%%xmm14 \n" "punpckldq %%xmm13,%%xmm9 \n" "movq %%xmm14,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "movdqa %%xmm9,%%xmm13 \n" "movq %%xmm9,(%1) \n" "palignr $0x8,%%xmm13,%%xmm13 \n" "movq %%xmm13,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "punpckldq %%xmm15,%%xmm11 \n" "movq %%xmm11,(%1) \n" "movdqa %%xmm11,%%xmm15 \n" "palignr $0x8,%%xmm15,%%xmm15 \n" "sub $0x10,%2 \n" "movq %%xmm15,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "jg 1b \n" : "+r"(src), // %0 "+r"(dst), // %1 "+r"(width) // %2 : "r"((intptr_t)(src_stride)), // %3 "r"((intptr_t)(dst_stride)) // %4 : "memory", "cc", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15" ); } #endif // defined(HAS_TRANSPOSEWX8_FAST_SSSE3) // Transpose UV 8x8. 64 bit. #if defined(HAS_TRANSPOSEUVWX8_SSE2) void TransposeUVWx8_SSE2(const uint8* src, int src_stride, uint8* dst_a, int dst_stride_a, uint8* dst_b, int dst_stride_b, int width) { asm volatile ( // Read in the data from the source pointer. // First round of bit swap. LABELALIGN "1: \n" "movdqu (%0),%%xmm0 \n" "movdqu (%0,%4),%%xmm1 \n" "lea (%0,%4,2),%0 \n" "movdqa %%xmm0,%%xmm8 \n" "punpcklbw %%xmm1,%%xmm0 \n" "punpckhbw %%xmm1,%%xmm8 \n" "movdqa %%xmm8,%%xmm1 \n" "movdqu (%0),%%xmm2 \n" "movdqu (%0,%4),%%xmm3 \n" "lea (%0,%4,2),%0 \n" "movdqa %%xmm2,%%xmm8 \n" "punpcklbw %%xmm3,%%xmm2 \n" "punpckhbw %%xmm3,%%xmm8 \n" "movdqa %%xmm8,%%xmm3 \n" "movdqu (%0),%%xmm4 \n" "movdqu (%0,%4),%%xmm5 \n" "lea (%0,%4,2),%0 \n" "movdqa %%xmm4,%%xmm8 \n" "punpcklbw %%xmm5,%%xmm4 \n" "punpckhbw %%xmm5,%%xmm8 \n" "movdqa %%xmm8,%%xmm5 \n" "movdqu (%0),%%xmm6 \n" "movdqu (%0,%4),%%xmm7 \n" "lea (%0,%4,2),%0 \n" "movdqa %%xmm6,%%xmm8 \n" "punpcklbw %%xmm7,%%xmm6 \n" "neg %4 \n" "lea 0x10(%0,%4,8),%0 \n" "punpckhbw %%xmm7,%%xmm8 \n" "movdqa %%xmm8,%%xmm7 \n" "neg %4 \n" // Second round of bit swap. "movdqa %%xmm0,%%xmm8 \n" "movdqa %%xmm1,%%xmm9 \n" "punpckhwd %%xmm2,%%xmm8 \n" "punpckhwd %%xmm3,%%xmm9 \n" "punpcklwd %%xmm2,%%xmm0 \n" "punpcklwd %%xmm3,%%xmm1 \n" "movdqa %%xmm8,%%xmm2 \n" "movdqa %%xmm9,%%xmm3 \n" "movdqa %%xmm4,%%xmm8 \n" "movdqa %%xmm5,%%xmm9 \n" "punpckhwd %%xmm6,%%xmm8 \n" "punpckhwd %%xmm7,%%xmm9 \n" "punpcklwd %%xmm6,%%xmm4 \n" "punpcklwd %%xmm7,%%xmm5 \n" "movdqa %%xmm8,%%xmm6 \n" "movdqa %%xmm9,%%xmm7 \n" // Third round of bit swap. // Write to the destination pointer. "movdqa %%xmm0,%%xmm8 \n" "punpckldq %%xmm4,%%xmm0 \n" "movlpd %%xmm0,(%1) \n" // Write back U channel "movhpd %%xmm0,(%2) \n" // Write back V channel "punpckhdq %%xmm4,%%xmm8 \n" "movlpd %%xmm8,(%1,%5) \n" "lea (%1,%5,2),%1 \n" "movhpd %%xmm8,(%2,%6) \n" "lea (%2,%6,2),%2 \n" "movdqa %%xmm2,%%xmm8 \n" "punpckldq %%xmm6,%%xmm2 \n" "movlpd %%xmm2,(%1) \n" "movhpd %%xmm2,(%2) \n" "punpckhdq %%xmm6,%%xmm8 \n" "movlpd %%xmm8,(%1,%5) \n" "lea (%1,%5,2),%1 \n" "movhpd %%xmm8,(%2,%6) \n" "lea (%2,%6,2),%2 \n" "movdqa %%xmm1,%%xmm8 \n" "punpckldq %%xmm5,%%xmm1 \n" "movlpd %%xmm1,(%1) \n" "movhpd %%xmm1,(%2) \n" "punpckhdq %%xmm5,%%xmm8 \n" "movlpd %%xmm8,(%1,%5) \n" "lea (%1,%5,2),%1 \n" "movhpd %%xmm8,(%2,%6) \n" "lea (%2,%6,2),%2 \n" "movdqa %%xmm3,%%xmm8 \n" "punpckldq %%xmm7,%%xmm3 \n" "movlpd %%xmm3,(%1) \n" "movhpd %%xmm3,(%2) \n" "punpckhdq %%xmm7,%%xmm8 \n" "sub $0x8,%3 \n" "movlpd %%xmm8,(%1,%5) \n" "lea (%1,%5,2),%1 \n" "movhpd %%xmm8,(%2,%6) \n" "lea (%2,%6,2),%2 \n" "jg 1b \n" : "+r"(src), // %0 "+r"(dst_a), // %1 "+r"(dst_b), // %2 "+r"(width) // %3 : "r"((intptr_t)(src_stride)), // %4 "r"((intptr_t)(dst_stride_a)), // %5 "r"((intptr_t)(dst_stride_b)) // %6 : "memory", "cc", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8", "xmm9" ); } #endif // defined(HAS_TRANSPOSEUVWX8_SSE2) #endif // defined(__x86_64__) \|\| defined(__i386__) #ifdef __cplusplus } // extern "C" } // namespace libyuv #endif	{ "language": "Assembly" }
.code16 .globl code16_start .globl code16_end CS_SEG = 0xf code16_start: .globl code16_func1 /* basic test / code16_func1 = . - code16_start mov $1, %eax data32 lret / test push/pop in 16 bit mode / .globl code16_func2 code16_func2 = . - code16_start xor %eax, %eax mov $0x12345678, %ebx movl %esp, %ecx push %bx subl %esp, %ecx pop %ax data32 lret / test various jmp opcodes / .globl code16_func3 code16_func3 = . - code16_start jmp 1f nop 1: mov $4, %eax mov $0x12345678, %ebx xor %bx, %bx jz 2f add $2, %ax 2: call myfunc lcall $CS_SEG, $(myfunc2 - code16_start) ljmp $CS_SEG, $(myjmp1 - code16_start) myjmp1_next: cs lcall myfunc2_addr - code16_start cs ljmp *myjmp2_addr - code16_start myjmp2_next: data32 lret myfunc2_addr: .short myfunc2 - code16_start .short CS_SEG myjmp2_addr: .short myjmp2 - code16_start .short CS_SEG myjmp1: add $8, %ax jmp myjmp1_next myjmp2: add $16, %ax jmp myjmp2_next myfunc: add $1, %ax ret myfunc2: add $4, %ax lret code16_end:	{ "language": "Assembly" }
### FILE="Main.annotation" ## Copyright: Public domain. ## Filename: LEM_GEOMETRY.agc ## Purpose: Part of the reconstructed source code for LMY99 Rev 0, ## otherwise known as Luminary Rev 99, the second release ## of the Apollo Guidance Computer (AGC) software for Apollo 11. ## It differs from LMY99 Rev 1 (the flown version) only in the ## placement of a single label. The corrections shown here have ## been verified to have the same bank checksums as AGC developer ## Allan Klumpp's copy of Luminary Rev 99, and so are believed ## to be accurate. This file is intended to be a faithful ## recreation, except that the code format has been changed to ## conform to the requirements of the yaYUL assembler rather than ## the original YUL assembler. ## ## Assembler: yaYUL ## Contact: Ron Burkey <[email protected]>. ## Website: www.ibiblio.org/apollo. ## Pages: 320-325 ## Mod history: 2009-05-16 RSB Adapted from the corresponding ## Luminary131 file, using page ## images from Luminary 1A. ## 2016-12-13 RSB Proofed text comments with octopus/ProoferComments ## and corrected the errors found. ## 2017-03-07 RSB Fixed comment-text error noticed while proofing ## Luminary 116. ## 2017-08-01 MAS Created from LMY99 Rev 1. ## This source code has been transcribed or otherwise adapted from ## digitized images of a hardcopy from the MIT Museum. The digitization ## was performed by Paul Fjeld, and arranged for by Deborah Douglas of ## the Museum. Many thanks to both. The images (with suitable reduction ## in storage size and consequent reduction in image quality as well) are ## available online at www.ibiblio.org/apollo. If for some reason you ## find that the images are illegible, contact me at [email protected] ## about getting access to the (much) higher-quality images which Paul ## actually created. ## ## The code has been modified to match LMY99 Revision 0, otherwise ## known as Luminary Revision 99, the Apollo 11 software release preceeding ## the listing from which it was transcribed. It has been verified to ## contain the same bank checksums as AGC developer Allan Klumpp's listing ## of Luminary Revision 99 (for which we do not have scans). ## ## Notations on Allan Klumpp's listing read, in part: ## ## ASSEMBLE REVISION 099 OF AGC PROGRAM LUMINARY BY NASA 2021112-51 ## Page 320 BANK 23 SETLOC LEMGEOM BANK SBANK= LOWSUPER EBANK= XSM # THESE TWO ROUTINES COMPUTE THE ACTUAL STATE VECTOR FOR LM,CSM BY ADDING # THE CONIC R,V AND THE DEVIATIONS R,V. THE STATE VECTORS ARE CONVERTED TO # METERS B-29 AND METERS/CSEC B-7 AND STORED APPROPRIATELY IN RN,VN OR # R-OTHER,V-OTHER FOR DOWNLINK. THE ROUTINES NAMES ARE SWITCHED IN THE # OTHER VEHICLES COMPUTER. # # INPUT # STATE VECTOR IN TEMPORARY STORAGE AREA # IF STATE VECTOR IS SCALED POS B27 AND VEL B5 # SET X2 TO +2 # IF STATE VECTOR IS SCALED POS B29 AND VEL B7 # SET X2 TO 0 # # OUTPUT # R(T) IN RN, V(T) IN VN, T IN PIPTIME # OR # R(T) IN R-OTHER, V(T) IN V-OTHER (T IS DEFINED BY T-OTHER) COUNT* $$/GEOM SVDWN2 BOF RVQ # SW=1=AVETOMID DOING W-MATRIX INTEG. AVEMIDSW +1 VLOAD VSL* TDELTAV 0 -7,2 VAD VSL* RCV 0,2 STOVL RN TNUV VSL* VAD 0 -4,2 VCV VSL* 0,2 STODL VN TET STORE PIPTIME RVQ ## Page 321 SVDWN1 VLOAD VSL* TDELTAV 0 -7,2 VAD VSL* RCV 0,2 STOVL R-OTHER TNUV VSL* VAD 0 -4,2 VCV VSL* 0,2 STORE V-OTHER RVQ ## Page 322 # THE FOLLOWING ROUTINE TAKES A HALF UNIT TARGET VECTOR REFERRED TO NAV BASE COORDINATES AND FINDS BOTH # GIMBAL ORIENTATIONS AT WHICH THE RR MIGHT SIGHT THE TARGET. THE GIMBAL ANGLES CORRESPONDING TO THE PRESENT MODE # ARE LEFT IN MODEA AND THOSE WHICH WOULD BE USED AFTER A REMODE IN MODEB. THIS ROUTINE ASSUMES MODE 1 IS TRUNNION # ANGLE LESS THAN 90 DEGS IN ABS VALUE WITH ARBITRARY SHAFT, WITH A CORRESPONDING DEFINITION FOR MODE 2. MODE # SELECTION AND LIMIT CHECKING ARE DONE ELSEWHERE. # # THE MODE 1 CONFIGURATION IS CALCULATED FROM THE VECTOR AND THEN MODE 2 IS FOUND USING THE RELATIONS # # S(2) = 180 + S(1) # T(2) = 180 - T(1) # # THE VECTOR ARRIVES IN MPAC WHERE TRGSMNG OR SMNB* WILL HAVE LEFT IT. RRANGLES STORE 32D DLOAD DCOMP # SINCE WE WILL FIND THE MODE 1 SHAFT 34D # ANGLE LATER, WE CAN FIND THE MODE 1 SETPD ASIN # TRUNNION BY SIMPLY TAKING THE ARCSIN OF 0 # THE Y COMPONENT, THE ASIN GIVING AN PUSH BDSU # ANSWER WHOSE ABS VAL IS LESS THAN 90 DEG LODPHALF STODL 4 # MODE 2 TRUNNION TO 4. LO6ZEROS STOVL 34D # UNIT THE PROJECTION OF THE VECTOR 32D # IN THE X-Z PLANE UNIT BOVB # IF OVERFLOW, TARGET VECTOR IS ALONG Y LUNDESCH # CALL FOR MANEUVER UNLESS ON LUNAR SURF STODL 32D # PROJECTION VECTOR. 32D SR1 STQ S2 STODL SINTH # USE ARCTRIG SINCE SHAFT COULD BE ARB. 36D SR1 STCALL COSTH ARCTRIG ## Page 323 PUSH DAD # MODE 1 SHAFT TO 2. LODPHALF STOVL 6 4 RTB # FIND MODE 2 CDU ANGLES. 2V1STO2S STOVL MODEB 0 RTB # MODE 1 ANGLES TO MODE A. 2V1STO2S STORE MODEA EXIT CS RADMODES # SWAP MODEA AND MODEB IF RR IN MODE 2. MASK ANTENBIT CCS A TCF +4 DXCH MODEA DXCH MODEB DXCH MODEA TC INTPRET GOTO S2 ## Page 324 # GIVEN RR TRUNNION AND SHAFT (T,S) IN TANGNB,+1, FIND THE ASSOCIATED # LINE OF SIGHT IN NAV BASE AXES. THE HALF UNIT VECTOR, .5(SIN(S)COS(T), # -SIN(T),COS(S)COS(T)) IS LEFT IN MPAC AND 32D. SETLOC INFLIGHT BANK COUNT* $$/GEOM RRNB SLOAD RTB TANGNB CDULOGIC SETPD PUSH # TRUNNION ANGLE TO 0 0 SIN DCOMP STODL 34D # Y COMPONENT COS PUSH # .5 COS(T) TO 0 SLOAD RTB TANGNB +1 CDULOGIC RRNB1 PUSH COS # SHAFT ANGLE TO 2 DMP SL1 0 STODL 36D # Z COMPONENT SIN DMP SL1 STOVL 32D 32D RVQ # THIS ENTRY TO RRNB REQUIRES THE TRUNNION AND SHAFT ANGLES IN MPAC AND MPAC +1 RESPECTIVELY RRNBMPAC STODL 20D # SAVE SHAFT CDU IN 21. MPAC # SET MODE TO DP. (THE PRECEEDING STORE # MAY BE DP, TP OR VECTOR.) RTB SETPD CDULOGIC 0 PUSH SIN # TRUNNION ANGLE TO 0 DCOMP STODL 34D # Y COMPONENT COS PUSH # .5COS(T) TO 0 SLOAD RTB # PICK UP CDU'S. 21D CDULOGIC GOTO RRNB1 ## Page 325 ## <br>This page has nothing on it.	{ "language": "Assembly" }
/* * Copyright (C) 2010 Google Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY APPLE AND ITS CONTRIBUTORS "AS IS" AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL APPLE OR ITS CONTRIBUTORS BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef OptionsObject_h #define OptionsObject_h // FIXME: Implement. #endif // OptionsObject_h	{ "language": "Assembly" }
.text .globl target .type target, @function #! file-offset 0 #! rip-offset 0 #! capacity 5 bytes # Text # Line RIP Bytes Opcode .target: # 0 0 OPC=<label> vmovsldup %xmm2, %xmm12 # 1 0 4 OPC=vmovsldup_xmm_xmm movdqa %xmm12, %xmm1 # 2 0x4 5 OPC=movdqa_xmm_xmm retq # 3 0x9 1 OPC=retq .size target, .-target	{ "language": "Assembly" }
#------------------------------------------------------------------------------ # $File: bsdi,v 1.7 2014/03/29 15:40:34 christos Exp $ # bsdi: file(1) magic for BSD/OS (from BSDI) objects # Some object/executable formats use the same magic numbers as are used # in other OSes; those are handled by entries in aout. # 0 lelong 0314 386 compact demand paged pure executable >16 lelong >0 not stripped >32 byte 0x6a (uses shared libs) # same as in SunOS 4.x, except for static shared libraries 0 belong&077777777 0600413 SPARC demand paged >0 byte &0x80 >>20 belong <4096 shared library >>20 belong =4096 dynamically linked executable >>20 belong >4096 dynamically linked executable >0 byte ^0x80 executable >16 belong >0 not stripped >36 belong 0xb4100001 (uses shared libs) 0 belong&077777777 0600410 SPARC pure >0 byte &0x80 dynamically linked executable >0 byte ^0x80 executable >16 belong >0 not stripped >36 belong 0xb4100001 (uses shared libs) 0 belong&077777777 0600407 SPARC >0 byte &0x80 dynamically linked executable >0 byte ^0x80 executable >16 belong >0 not stripped >36 belong 0xb4100001 (uses shared libs)	{ "language": "Assembly" }
// RUN: %clang -target x86_64-apple-darwin -fsyntax-only %s -no-integrated-as -### 2>&1 \| FileCheck %s // Test that the autolinking feature is disabled with not using the // integrated assembler. // CHECK: -fno-autolink	{ "language": "Assembly" }
namespace N { struct A { }; namespace M { struct C { }; }; } namespace N { struct B { }; } N:: // RUN: %clang_cc1 -fsyntax-only -code-completion-at=%s:12:4 %s -o - \| FileCheck -check-prefix=CHECK-CC1 %s // CHECK-CC1: A // CHECK-CC1: B // CHECK-CC1: M	{ "language": "Assembly" }
; RUN: llc %s -filetype=obj -o - \| llvm-dwarfdump -v - \| FileCheck %s ; Test that DW_OP_piece is emitted for constants. ; ; // Generated from: ; typedef struct { int a, b; } I; ; I i(int i) { ; I r = {i, 0}; ; return r; ; } ; ; typedef struct { float a, b; } F; ; F f(float f) { ; F r = {f, 0}; ; return r; ; } ; CHECK: .debug_info contents: ; CHECK: DW_TAG_subprogram ; CHECK: DW_AT_name {{.}} "i" ; CHECK: DW_TAG_variable ; CHECK-NEXT: DW_AT_location {{.}} ([[I:.]] ; CHECK-NEXT: [{{.}}, {{.}}): DW_OP_reg5 RDI, DW_OP_piece 0x4, DW_OP_lit0, DW_OP_stack_value, DW_OP_piece 0x4) ; CHECK-NEXT: DW_AT_name {{.}} "r" ; ; CHECK: DW_TAG_subprogram ; CHECK: DW_AT_name {{.}} "f" ; CHECK: DW_TAG_variable ; CHECK-NEXT: DW_AT_location {{.}} ([[F:.]] ; CHECK-NEXT: [{{.}}, {{.}}): DW_OP_reg17 XMM0, DW_OP_piece 0x4, DW_OP_lit0, DW_OP_stack_value, DW_OP_piece 0x4 ; CHECK-NEXT: [{{.}}, {{.}}): DW_OP_piece 0x4, DW_OP_lit0, DW_OP_stack_value, DW_OP_piece 0x4) ; CHECK-NEXT: DW_AT_name {{.}} "r" ; ; CHECK: .debug_loc contents: ; CHECK: [[I]]: ; CHECK-NEXT: [{{.}}, {{.}}): DW_OP_reg5 RDI, DW_OP_piece 0x4, DW_OP_lit0, DW_OP_stack_value, DW_OP_piece 0x4 ; CHECK: [[F]]: ; CHECK-NEXT: [{{.}}, {{.}}): DW_OP_reg17 XMM0, DW_OP_piece 0x4, DW_OP_lit0, DW_OP_stack_value, DW_OP_piece 0x4 source_filename = "stack-value-piece.c" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.12.0" %struct.I = type { i32, i32 } %struct.F = type { float, float } ; Function Attrs: nounwind readnone ssp uwtable define i64 @i(i32 %i) local_unnamed_addr #0 !dbg !7 { entry: tail call void @llvm.dbg.value(metadata i32 %i, metadata !18, metadata !22), !dbg !21 tail call void @llvm.dbg.value(metadata i32 0, metadata !18, metadata !23), !dbg !21 %retval.sroa.0.0.insert.ext = zext i32 %i to i64, !dbg !24 ret i64 %retval.sroa.0.0.insert.ext, !dbg !24 } ; Function Attrs: nounwind readnone declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 ; Function Attrs: nounwind readnone ssp uwtable define <2 x float> @f(float %f) local_unnamed_addr #0 !dbg !25 { entry: tail call void @llvm.dbg.value(metadata float %f, metadata !36, metadata !22), !dbg !38 tail call void @llvm.dbg.value(metadata float 0.000000e+00, metadata !36, metadata !23), !dbg !38 %retval.sroa.0.0.vec.insert = insertelement <2 x float> undef, float %f, i32 0, !dbg !39 %retval.sroa.0.4.vec.insert = insertelement <2 x float> %retval.sroa.0.0.vec.insert, float 0.000000e+00, i32 1, !dbg !39 ret <2 x float> %retval.sroa.0.4.vec.insert, !dbg !40 } ; Function Attrs: nounwind readnone declare void @llvm.dbg.value(metadata, metadata, metadata) #1 attributes #0 = { nounwind readnone ssp uwtable } attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3, !4, !5} !llvm.ident = !{!6} !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 4.0.0 (trunk 285655) (llvm/trunk 285654)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) !1 = !DIFile(filename: "stack-value-piece.c", directory: "/") !2 = !{} !3 = !{i32 2, !"Dwarf Version", i32 4} !4 = !{i32 2, !"Debug Info Version", i32 3} !5 = !{i32 1, !"PIC Level", i32 2} !6 = !{!"clang version 4.0.0 (trunk 285655) (llvm/trunk 285654)"} !7 = distinct !DISubprogram(name: "i", scope: !1, file: !1, line: 2, type: !8, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0) !8 = !DISubroutineType(types: !9) !9 = !{!10, !14} !10 = !DIDerivedType(tag: DW_TAG_typedef, name: "I", file: !1, line: 1, baseType: !11) !11 = distinct !DICompositeType(tag: DW_TAG_structure_type, file: !1, line: 1, size: 64, elements: !12) !12 = !{!13, !15} !13 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !11, file: !1, line: 1, baseType: !14, size: 32) !14 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) !15 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !11, file: !1, line: 1, baseType: !14, size: 32, offset: 32) !18 = !DILocalVariable(name: "r", scope: !7, file: !1, line: 3, type: !10) !19 = !DIExpression() !20 = !DILocation(line: 2, column: 9, scope: !7) !21 = !DILocation(line: 3, column: 5, scope: !7) !22 = !DIExpression(DW_OP_LLVM_fragment, 0, 32) !23 = !DIExpression(DW_OP_LLVM_fragment, 32, 32) !24 = !DILocation(line: 5, column: 1, scope: !7) !25 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 8, type: !26, isLocal: false, isDefinition: true, scopeLine: 8, flags: DIFlagPrototyped, isOptimized: true, unit: !0) !26 = !DISubroutineType(types: !27) !27 = !{!28, !32} !28 = !DIDerivedType(tag: DW_TAG_typedef, name: "F", file: !1, line: 7, baseType: !29) !29 = distinct !DICompositeType(tag: DW_TAG_structure_type, file: !1, line: 7, size: 64, elements: !30) !30 = !{!31, !33} !31 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !29, file: !1, line: 7, baseType: !32, size: 32) !32 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float) !33 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !29, file: !1, line: 7, baseType: !32, size: 32, offset: 32) !36 = !DILocalVariable(name: "r", scope: !25, file: !1, line: 9, type: !28) !37 = !DILocation(line: 8, column: 11, scope: !25) !38 = !DILocation(line: 9, column: 5, scope: !25) !39 = !DILocation(line: 10, column: 10, scope: !25) !40 = !DILocation(line: 11, column: 1, scope: !25)	{ "language": "Assembly" }
BEGIN:VEVENT DTSTART :20001104T150000 DTEND :20001104T160000 END:VEVENT BEGIN:VEVENT DTSTART :20001104T153000 DTEND :20001104T163000 END:VEVENT BEGIN:VEVENT DTSTART :20001104T160000 DTEND :20001104T170000 END:VEVENT BEGIN:VEVENT DTSTART :20001104T163000 DTEND :20001104T173000 END:VEVENT BEGIN:VEVENT DTSTART :20001104T170000 DTEND :20001104T180000 END:VEVENT	{ "language": "Assembly" }
/***************************************************************** \| \| Neptune - Trust Anchors \| \| This file is automatically generated by a script, do not edit! \| \| Copyright (c) 2002-2010, Axiomatic Systems, LLC. \| All rights reserved. \| \| Redistribution and use in source and binary forms, with or without \| modification, are permitted provided that the following conditions are met: \| * Redistributions of source code must retain the above copyright \| notice, this list of conditions and the following disclaimer. \| * Redistributions in binary form must reproduce the above copyright \| notice, this list of conditions and the following disclaimer in the \| documentation and/or other materials provided with the distribution. \| * Neither the name of Axiomatic Systems nor the \| names of its contributors may be used to endorse or promote products \| derived from this software without specific prior written permission. \| \| THIS SOFTWARE IS PROVIDED BY AXIOMATIC SYSTEMS ''AS IS'' AND ANY \| EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED \| WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \| DISCLAIMED. IN NO EVENT SHALL AXIOMATIC SYSTEMS BE LIABLE FOR ANY \| DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES \| (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \| LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \| ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \| (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS \| SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \| ***************************************************************/ / ApplicationCA - Japanese Government */ const unsigned char NptTlsTrustAnchor_Base_0132_Data[932] = { 0x30,0x82,0x03,0xa0,0x30,0x82,0x02,0x88 ,0xa0,0x03,0x02,0x01,0x02,0x02,0x01,0x31 ,0x30,0x0d,0x06,0x09,0x2a,0x86,0x48,0x86 ,0xf7,0x0d,0x01,0x01,0x05,0x05,0x00,0x30 ,0x43,0x31,0x0b,0x30,0x09,0x06,0x03,0x55 ,0x04,0x06,0x13,0x02,0x4a,0x50,0x31,0x1c ,0x30,0x1a,0x06,0x03,0x55,0x04,0x0a,0x13 ,0x13,0x4a,0x61,0x70,0x61,0x6e,0x65,0x73 ,0x65,0x20,0x47,0x6f,0x76,0x65,0x72,0x6e ,0x6d,0x65,0x6e,0x74,0x31,0x16,0x30,0x14 ,0x06,0x03,0x55,0x04,0x0b,0x13,0x0d,0x41 ,0x70,0x70,0x6c,0x69,0x63,0x61,0x74,0x69 ,0x6f,0x6e,0x43,0x41,0x30,0x1e,0x17,0x0d ,0x30,0x37,0x31,0x32,0x31,0x32,0x31,0x35 ,0x30,0x30,0x30,0x30,0x5a,0x17,0x0d,0x31 ,0x37,0x31,0x32,0x31,0x32,0x31,0x35,0x30 ,0x30,0x30,0x30,0x5a,0x30,0x43,0x31,0x0b ,0x30,0x09,0x06,0x03,0x55,0x04,0x06,0x13 ,0x02,0x4a,0x50,0x31,0x1c,0x30,0x1a,0x06 ,0x03,0x55,0x04,0x0a,0x13,0x13,0x4a,0x61 ,0x70,0x61,0x6e,0x65,0x73,0x65,0x20,0x47 ,0x6f,0x76,0x65,0x72,0x6e,0x6d,0x65,0x6e ,0x74,0x31,0x16,0x30,0x14,0x06,0x03,0x55 ,0x04,0x0b,0x13,0x0d,0x41,0x70,0x70,0x6c ,0x69,0x63,0x61,0x74,0x69,0x6f,0x6e,0x43 ,0x41,0x30,0x82,0x01,0x22,0x30,0x0d,0x06 ,0x09,0x2a,0x86,0x48,0x86,0xf7,0x0d,0x01 ,0x01,0x01,0x05,0x00,0x03,0x82,0x01,0x0f ,0x00,0x30,0x82,0x01,0x0a,0x02,0x82,0x01 ,0x01,0x00,0xa7,0x6d,0xe0,0x74,0x4e,0x87 ,0x8f,0xa5,0x06,0xde,0x68,0xa2,0xdb,0x86 ,0x99,0x4b,0x64,0x0d,0x71,0xf0,0x0a,0x05 ,0x9b,0x8e,0xaa,0xe1,0xcc,0x2e,0xd2,0x6a ,0x3b,0xc1,0x7a,0xb4,0x97,0x61,0x8d,0x8a ,0xbe,0xc6,0x9a,0x9c,0x06,0xb4,0x86,0x51 ,0xe4,0x37,0x0e,0x74,0x78,0x7e,0x5f,0x8a ,0x7f,0x94,0xa4,0xd7,0x47,0x08,0xfd,0x50 ,0x5a,0x56,0xe4,0x68,0xac,0x28,0x73,0xa0 ,0x7b,0xe9,0x7f,0x18,0x92,0x40,0x4f,0x2d ,0x9d,0xf5,0xae,0x44,0x48,0x73,0x36,0x06 ,0x9e,0x64,0x2c,0x3b,0x34,0x23,0xdb,0x5c ,0x26,0xe4,0x71,0x79,0x8f,0xd4,0x6e,0x79 ,0x22,0xb9,0x93,0xc1,0xca,0xcd,0xc1,0x56 ,0xed,0x88,0x6a,0xd7,0xa0,0x39,0x21,0x04 ,0x57,0x2c,0xa2,0xf5,0xbc,0x47,0x41,0x4f ,0x5e,0x34,0x22,0x95,0xb5,0x1f,0x29,0x6d ,0x5e,0x4a,0xf3,0x4d,0x72,0xbe,0x41,0x56 ,0x20,0x87,0xfc,0xe9,0x50,0x47,0xd7,0x30 ,0x14,0xee,0x5c,0x8c,0x55,0xba,0x59,0x8d ,0x87,0xfc,0x23,0xde,0x93,0xd0,0x04,0x8c ,0xfd,0xef,0x6d,0xbd,0xd0,0x7a,0xc9,0xa5 ,0x3a,0x6a,0x72,0x33,0xc6,0x4a,0x0d,0x05 ,0x17,0x2a,0x2d,0x7b,0xb1,0xa7,0xd8,0xd6 ,0xf0,0xbe,0xf4,0x3f,0xea,0x0e,0x28,0x6d ,0x41,0x61,0x23,0x76,0x78,0xc3,0xb8,0x65 ,0xa4,0xf3,0x5a,0xae,0xcc,0xc2,0xaa,0xd9 ,0xe7,0x58,0xde,0xb6,0x7e,0x9d,0x85,0x6e ,0x9f,0x2a,0x0a,0x6f,0x9f,0x03,0x29,0x30 ,0x97,0x28,0x1d,0xbc,0xb7,0xcf,0x54,0x29 ,0x4e,0x51,0x31,0xf9,0x27,0xb6,0x28,0x26 ,0xfe,0xa2,0x63,0xe6,0x41,0x16,0xf0,0x33 ,0x98,0x47,0x02,0x03,0x01,0x00,0x01,0xa3 ,0x81,0x9e,0x30,0x81,0x9b,0x30,0x1d,0x06 ,0x03,0x55,0x1d,0x0e,0x04,0x16,0x04,0x14 ,0x54,0x5a,0xcb,0x26,0x3f,0x71,0xcc,0x94 ,0x46,0x0d,0x96,0x53,0xea,0x6b,0x48,0xd0 ,0x93,0xfe,0x42,0x75,0x30,0x0e,0x06,0x03 ,0x55,0x1d,0x0f,0x01,0x01,0xff,0x04,0x04 ,0x03,0x02,0x01,0x06,0x30,0x59,0x06,0x03 ,0x55,0x1d,0x11,0x04,0x52,0x30,0x50,0xa4 ,0x4e,0x30,0x4c,0x31,0x0b,0x30,0x09,0x06 ,0x03,0x55,0x04,0x06,0x13,0x02,0x4a,0x50 ,0x31,0x18,0x30,0x16,0x06,0x03,0x55,0x04 ,0x0a,0x0c,0x0f,0xe6,0x97,0xa5,0xe6,0x9c ,0xac,0xe5,0x9b,0xbd,0xe6,0x94,0xbf,0xe5 ,0xba,0x9c,0x31,0x23,0x30,0x21,0x06,0x03 ,0x55,0x04,0x0b,0x0c,0x1a,0xe3,0x82,0xa2 ,0xe3,0x83,0x97,0xe3,0x83,0xaa,0xe3,0x82 ,0xb1,0xe3,0x83,0xbc,0xe3,0x82,0xb7,0xe3 ,0x83,0xa7,0xe3,0x83,0xb3,0x43,0x41,0x30 ,0x0f,0x06,0x03,0x55,0x1d,0x13,0x01,0x01 ,0xff,0x04,0x05,0x30,0x03,0x01,0x01,0xff ,0x30,0x0d,0x06,0x09,0x2a,0x86,0x48,0x86 ,0xf7,0x0d,0x01,0x01,0x05,0x05,0x00,0x03 ,0x82,0x01,0x01,0x00,0x39,0x6a,0x44,0x76 ,0x77,0x38,0x3a,0xec,0xa3,0x67,0x46,0x0f ,0xf9,0x8b,0x06,0xa8,0xfb,0x6a,0x90,0x31 ,0xce,0x7e,0xec,0xda,0xd1,0x89,0x7c,0x7a ,0xeb,0x2e,0x0c,0xbd,0x99,0x32,0xe7,0xb0 ,0x24,0xd6,0xc3,0xff,0xf5,0xb2,0x88,0x09 ,0x87,0x2c,0xe3,0x54,0xe1,0xa3,0xa6,0xb2 ,0x08,0x0b,0xc0,0x85,0xa8,0xc8,0xd2,0x9c ,0x71,0xf6,0x1d,0x9f,0x60,0xfc,0x38,0x33 ,0x13,0xe1,0x9e,0xdc,0x0b,0x5f,0xda,0x16 ,0x50,0x29,0x7b,0x2f,0x70,0x91,0x0f,0x99 ,0xba,0x34,0x34,0x8d,0x95,0x74,0xc5,0x7e ,0x78,0xa9,0x66,0x5d,0xbd,0xca,0x21,0x77 ,0x42,0x10,0xac,0x66,0x26,0x3d,0xde,0x91 ,0xab,0xfd,0x15,0xf0,0x6f,0xed,0x6c,0x5f ,0x10,0xf8,0xf3,0x16,0xf6,0x03,0x8a,0x8f ,0xa7,0x12,0x11,0x0c,0xcb,0xfd,0x3f,0x79 ,0xc1,0x9c,0xfd,0x62,0xee,0xa3,0xcf,0x54 ,0x0c,0xd1,0x2b,0x5f,0x17,0x3e,0xe3,0x3e ,0xbf,0xc0,0x2b,0x3e,0x09,0x9b,0xfe,0x88 ,0xa6,0x7e,0xb4,0x92,0x17,0xfc,0x23,0x94 ,0x81,0xbd,0x6e,0xa7,0xc5,0x8c,0xc2,0xeb ,0x11,0x45,0xdb,0xf8,0x41,0xc9,0x96,0x76 ,0xea,0x70,0x5f,0x79,0x12,0x6b,0xe4,0xa3 ,0x07,0x5a,0x05,0xef,0x27,0x49,0xcf,0x21 ,0x9f,0x8a,0x4c,0x09,0x70,0x66,0xa9,0x26 ,0xc1,0x2b,0x11,0x4e,0x33,0xd2,0x0e,0xfc ,0xd6,0x6c,0xd2,0x0e,0x32,0x64,0x68,0xff ,0xad,0x05,0x78,0x5f,0x03,0x1d,0xa8,0xe3 ,0x90,0xac,0x24,0xe0,0x0f,0x40,0xa7,0x4b ,0xae,0x8b,0x28,0xb7,0x82,0xca,0x18,0x07 ,0xe6,0xb7,0x5b,0x74,0xe9,0x20,0x19,0x7f ,0xb2,0x1b,0x89,0x54}; const unsigned int NptTlsTrustAnchor_Base_0132_Size = 932;	{ "language": "Assembly" }
Qualcomm MSM8998 TLMM block This binding describes the Top Level Mode Multiplexer block found in the MSM8998 platform. - compatible: Usage: required Value type: <string> Definition: must be "qcom,msm8998-pinctrl" - reg: Usage: required Value type: <prop-encoded-array> Definition: the base address and size of the TLMM register space. - interrupts: Usage: required Value type: <prop-encoded-array> Definition: should specify the TLMM summary IRQ. - interrupt-controller: Usage: required Value type: <none> Definition: identifies this node as an interrupt controller - #interrupt-cells: Usage: required Value type: <u32> Definition: must be 2. Specifying the pin number and flags, as defined in <dt-bindings/interrupt-controller/irq.h> - gpio-controller: Usage: required Value type: <none> Definition: identifies this node as a gpio controller - #gpio-cells: Usage: required Value type: <u32> Definition: must be 2. Specifying the pin number and flags, as defined in <dt-bindings/gpio/gpio.h> - gpio-ranges: Usage: required Definition: see ../gpio/gpio.txt - gpio-reserved-ranges: Usage: optional Definition: see ../gpio/gpio.txt Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. Please refer to pinctrl-bindings.txt in this directory for details of the common pinctrl bindings used by client devices, including the meaning of the phrase "pin configuration node". The pin configuration nodes act as a container for an arbitrary number of subnodes. Each of these subnodes represents some desired configuration for a pin, a group, or a list of pins or groups. This configuration can include the mux function to select on those pin(s)/group(s), and various pin configuration parameters, such as pull-up, drive strength, etc. PIN CONFIGURATION NODES: The name of each subnode is not important; all subnodes should be enumerated and processed purely based on their content. Each subnode only affects those parameters that are explicitly listed. In other words, a subnode that lists a mux function but no pin configuration parameters implies no information about any pin configuration parameters. Similarly, a pin subnode that describes a pullup parameter implies no information about e.g. the mux function. The following generic properties as defined in pinctrl-bindings.txt are valid to specify in a pin configuration subnode: - pins: Usage: required Value type: <string-array> Definition: List of gpio pins affected by the properties specified in this subnode. Valid pins are: gpio0-gpio149 Supports mux, bias and drive-strength sdc2_clk, sdc2_cmd, sdc2_data Supports bias and drive-strength ufs_reset Supports bias and drive-strength - function: Usage: required Value type: <string> Definition: Specify the alternative function to be configured for the specified pins. Functions are only valid for gpio pins. Valid values are: gpio, adsp_ext, agera_pll, atest_char, atest_gpsadc0, atest_gpsadc1, atest_tsens, atest_tsens2, atest_usb1, atest_usb10, atest_usb11, atest_usb12, atest_usb13, audio_ref, bimc_dte0, bimc_dte1, blsp10_spi, blsp10_spi_a, blsp10_spi_b, blsp11_i2c, blsp1_spi, blsp1_spi_a, blsp1_spi_b, blsp2_spi, blsp9_spi, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10, blsp_spi11, blsp_spi12, blsp_uart1_a, blsp_uart1_b, blsp_uart2_a, blsp_uart2_b, blsp_uart3_a, blsp_uart3_b, blsp_uart7_a, blsp_uart7_b, blsp_uart8, blsp_uart8_a, blsp_uart8_b, blsp_uart9_a, blsp_uart9_b, blsp_uim1_a, blsp_uim1_b, blsp_uim2_a, blsp_uim2_b, blsp_uim3_a, blsp_uim3_b, blsp_uim7_a, blsp_uim7_b, blsp_uim8_a, blsp_uim8_b, blsp_uim9_a, blsp_uim9_b, bt_reset, btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, edp_hot, edp_lcd, gcc_gp1_a, gcc_gp1_b, gcc_gp2_a, gcc_gp2_b, gcc_gp3_a, gcc_gp3_b, hdmi_cec, hdmi_ddc, hdmi_hot, hdmi_rcv, isense_dbg, jitter_bist, ldo_en, ldo_update, lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync_a, mdp_vsync_b, modem_tsync, mss_lte, nav_dr, nav_pps, pa_indicator, pci_e0, phase_flag, pll_bypassnl, pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, pwr_crypto, pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b, qdss_cti1_a, qdss_cti1_b, qdss, qlink_enable, qlink_request, qua_mi2s, sd_card, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ssbi1, ssc_irq, ter_mi2s, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, tsif0, tsif1, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1, vsense_clkout, vsense_data0, vsense_data1, vsense_mode, wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, - bias-disable: Usage: optional Value type: <none> Definition: The specified pins should be configured as no pull. - bias-pull-down: Usage: optional Value type: <none> Definition: The specified pins should be configured as pull down. - bias-pull-up: Usage: optional Value type: <none> Definition: The specified pins should be configured as pull up. - output-high: Usage: optional Value type: <none> Definition: The specified pins are configured in output mode, driven high. Not valid for sdc pins. - output-low: Usage: optional Value type: <none> Definition: The specified pins are configured in output mode, driven low. Not valid for sdc pins. - drive-strength: Usage: optional Value type: <u32> Definition: Selects the drive strength for the specified pins, in mA. Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 Example: tlmm: pinctrl@03400000 { compatible = "qcom,msm8998-pinctrl"; reg = <0x03400000 0xc00000>; interrupts = <0 208 0>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&tlmm 0 0 175>; gpio-reserved-ranges = <0 4>, <81 4>; interrupt-controller; #interrupt-cells = <2>; uart_console_active: uart_console_active { mux { pins = "gpio4", "gpio5"; function = "blsp_uart8_a"; }; config { pins = "gpio4", "gpio5"; drive-strength = <2>; bias-disable; }; }; };	{ "language": "Assembly" }
/ **************************************************************************** * @file startup_stm32f429xx.s * @author MCD Application Team * @brief STM32F429xx Devices vector table for GCC based toolchains. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** / .syntax unified .cpu cortex-m4 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler / start address for the initialization values of the .data section. defined in linker script / .word _sidata / start address for the .data section. defined in linker script / .word _sdata / end address for the .data section. defined in linker script / .word _edata / start address for the .bss section. defined in linker script / .word _sbss / end address for the .bss section. defined in linker script / .word _ebss / stack used for SystemInit_ExtMemCtl; always internal RAM used / /* * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None / .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack / set stack pointer / / Copy the data segment initializers from flash to SRAM / movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss / Zero fill the bss segment. / FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss / Call the clock system intitialization function./ bl SystemInit / Call static constructors / bl __libc_init_array / Call the application's entry point./ bl main bx lr .size Reset_Handler, .-Reset_Handler /* * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None / .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /***************************************************************************** * * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler / External Interrupts / .word WWDG_IRQHandler / Window WatchDog / .word PVD_IRQHandler / PVD through EXTI Line detection / .word TAMP_STAMP_IRQHandler / Tamper and TimeStamps through the EXTI line / .word RTC_WKUP_IRQHandler / RTC Wakeup through the EXTI line / .word FLASH_IRQHandler / FLASH / .word RCC_IRQHandler / RCC / .word EXTI0_IRQHandler / EXTI Line0 / .word EXTI1_IRQHandler / EXTI Line1 / .word EXTI2_IRQHandler / EXTI Line2 / .word EXTI3_IRQHandler / EXTI Line3 / .word EXTI4_IRQHandler / EXTI Line4 / .word DMA1_Stream0_IRQHandler / DMA1 Stream 0 / .word DMA1_Stream1_IRQHandler / DMA1 Stream 1 / .word DMA1_Stream2_IRQHandler / DMA1 Stream 2 / .word DMA1_Stream3_IRQHandler / DMA1 Stream 3 / .word DMA1_Stream4_IRQHandler / DMA1 Stream 4 / .word DMA1_Stream5_IRQHandler / DMA1 Stream 5 / .word DMA1_Stream6_IRQHandler / DMA1 Stream 6 / .word ADC_IRQHandler / ADC1, ADC2 and ADC3s / .word CAN1_TX_IRQHandler / CAN1 TX / .word CAN1_RX0_IRQHandler / CAN1 RX0 / .word CAN1_RX1_IRQHandler / CAN1 RX1 / .word CAN1_SCE_IRQHandler / CAN1 SCE / .word EXTI9_5_IRQHandler / External Line[9:5]s / .word TIM1_BRK_TIM9_IRQHandler / TIM1 Break and TIM9 / .word TIM1_UP_TIM10_IRQHandler / TIM1 Update and TIM10 / .word TIM1_TRG_COM_TIM11_IRQHandler / TIM1 Trigger and Commutation and TIM11 / .word TIM1_CC_IRQHandler / TIM1 Capture Compare / .word TIM2_IRQHandler / TIM2 / .word TIM3_IRQHandler / TIM3 / .word TIM4_IRQHandler / TIM4 / .word I2C1_EV_IRQHandler / I2C1 Event / .word I2C1_ER_IRQHandler / I2C1 Error / .word I2C2_EV_IRQHandler / I2C2 Event / .word I2C2_ER_IRQHandler / I2C2 Error / .word SPI1_IRQHandler / SPI1 / .word SPI2_IRQHandler / SPI2 / .word USART1_IRQHandler / USART1 / .word USART2_IRQHandler / USART2 / .word USART3_IRQHandler / USART3 / .word EXTI15_10_IRQHandler / External Line[15:10]s / .word RTC_Alarm_IRQHandler / RTC Alarm (A and B) through EXTI Line / .word OTG_FS_WKUP_IRQHandler / USB OTG FS Wakeup through EXTI line / .word TIM8_BRK_TIM12_IRQHandler / TIM8 Break and TIM12 / .word TIM8_UP_TIM13_IRQHandler / TIM8 Update and TIM13 / .word TIM8_TRG_COM_TIM14_IRQHandler / TIM8 Trigger and Commutation and TIM14 / .word TIM8_CC_IRQHandler / TIM8 Capture Compare / .word DMA1_Stream7_IRQHandler / DMA1 Stream7 / .word FMC_IRQHandler / FMC / .word SDIO_IRQHandler / SDIO / .word TIM5_IRQHandler / TIM5 / .word SPI3_IRQHandler / SPI3 / .word UART4_IRQHandler / UART4 / .word UART5_IRQHandler / UART5 / .word TIM6_DAC_IRQHandler / TIM6 and DAC1&2 underrun errors / .word TIM7_IRQHandler / TIM7 / .word DMA2_Stream0_IRQHandler / DMA2 Stream 0 / .word DMA2_Stream1_IRQHandler / DMA2 Stream 1 / .word DMA2_Stream2_IRQHandler / DMA2 Stream 2 / .word DMA2_Stream3_IRQHandler / DMA2 Stream 3 / .word DMA2_Stream4_IRQHandler / DMA2 Stream 4 / .word ETH_IRQHandler / Ethernet / .word ETH_WKUP_IRQHandler / Ethernet Wakeup through EXTI line / .word CAN2_TX_IRQHandler / CAN2 TX / .word CAN2_RX0_IRQHandler / CAN2 RX0 / .word CAN2_RX1_IRQHandler / CAN2 RX1 / .word CAN2_SCE_IRQHandler / CAN2 SCE / .word OTG_FS_IRQHandler / USB OTG FS / .word DMA2_Stream5_IRQHandler / DMA2 Stream 5 / .word DMA2_Stream6_IRQHandler / DMA2 Stream 6 / .word DMA2_Stream7_IRQHandler / DMA2 Stream 7 / .word USART6_IRQHandler / USART6 / .word I2C3_EV_IRQHandler / I2C3 event / .word I2C3_ER_IRQHandler / I2C3 error / .word OTG_HS_EP1_OUT_IRQHandler / USB OTG HS End Point 1 Out / .word OTG_HS_EP1_IN_IRQHandler / USB OTG HS End Point 1 In / .word OTG_HS_WKUP_IRQHandler / USB OTG HS Wakeup through EXTI / .word OTG_HS_IRQHandler / USB OTG HS / .word DCMI_IRQHandler / DCMI / .word 0 / Reserved / .word HASH_RNG_IRQHandler / Hash and Rng / .word FPU_IRQHandler / FPU / .word UART7_IRQHandler / UART7 / .word UART8_IRQHandler / UART8 / .word SPI4_IRQHandler / SPI4 / .word SPI5_IRQHandler / SPI5 / .word SPI6_IRQHandler / SPI6 / .word SAI1_IRQHandler / SAI1 / .word LTDC_IRQHandler / LTDC_IRQHandler / .word LTDC_ER_IRQHandler / LTDC_ER_IRQHandler / .word DMA2D_IRQHandler / DMA2D / /****************************************************************************** * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *****************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak CAN1_TX_IRQHandler .thumb_set CAN1_TX_IRQHandler,Default_Handler .weak CAN1_RX0_IRQHandler .thumb_set CAN1_RX0_IRQHandler,Default_Handler .weak CAN1_RX1_IRQHandler .thumb_set CAN1_RX1_IRQHandler,Default_Handler .weak CAN1_SCE_IRQHandler .thumb_set CAN1_SCE_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM9_IRQHandler .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler .weak TIM1_UP_TIM10_IRQHandler .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM11_IRQHandler .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak TIM8_BRK_TIM12_IRQHandler .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler .weak TIM8_UP_TIM13_IRQHandler .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler .weak TIM8_TRG_COM_TIM14_IRQHandler .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak FMC_IRQHandler .thumb_set FMC_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak ETH_IRQHandler .thumb_set ETH_IRQHandler,Default_Handler .weak ETH_WKUP_IRQHandler .thumb_set ETH_WKUP_IRQHandler,Default_Handler .weak CAN2_TX_IRQHandler .thumb_set CAN2_TX_IRQHandler,Default_Handler .weak CAN2_RX0_IRQHandler .thumb_set CAN2_RX0_IRQHandler,Default_Handler .weak CAN2_RX1_IRQHandler .thumb_set CAN2_RX1_IRQHandler,Default_Handler .weak CAN2_SCE_IRQHandler .thumb_set CAN2_SCE_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak OTG_HS_EP1_OUT_IRQHandler .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_HS_EP1_IN_IRQHandler .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler .weak OTG_HS_WKUP_IRQHandler .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler .weak OTG_HS_IRQHandler .thumb_set OTG_HS_IRQHandler,Default_Handler .weak DCMI_IRQHandler .thumb_set DCMI_IRQHandler,Default_Handler .weak HASH_RNG_IRQHandler .thumb_set HASH_RNG_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler .weak UART7_IRQHandler .thumb_set UART7_IRQHandler,Default_Handler .weak UART8_IRQHandler .thumb_set UART8_IRQHandler,Default_Handler .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler .weak SPI5_IRQHandler .thumb_set SPI5_IRQHandler,Default_Handler .weak SPI6_IRQHandler .thumb_set SPI6_IRQHandler,Default_Handler .weak SAI1_IRQHandler .thumb_set SAI1_IRQHandler,Default_Handler .weak LTDC_IRQHandler .thumb_set LTDC_IRQHandler,Default_Handler .weak LTDC_ER_IRQHandler .thumb_set LTDC_ER_IRQHandler,Default_Handler .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler /******************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/	{ "language": "Assembly" }
; RUN: opt < %s -basicaa -globalsmodref-aa -gvn -instcombine -S \| FileCheck %s @G = internal global i32* null ; <i32*> [#uses=3] declare i8 @malloc(i32) define void @test() { %a = call i8* @malloc(i32 4) %A = bitcast i8* %a to i32* store i32* %A, i32** @G ret void } define i32 @test1(i32* %P) { ; CHECK: ret i32 0 %g1 = load i32** @G ; <i32> [#uses=2] %h1 = load i32 %g1 ; <i32> [#uses=1] store i32 123, i32* %P %g2 = load i32** @G ; <i32> [#uses=0] %h2 = load i32 %g1 ; <i32> [#uses=1] %X = sub i32 %h1, %h2 ; <i32> [#uses=1] ret i32 %X }	{ "language": "Assembly" }
;**************************************************************************** ; ; grlib_driver_test.sct - Linker configuration file for grlib_driver_test. ; ; Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. ; Software License Agreement ; ; Texas Instruments (TI) is supplying this software for use solely and ; exclusively on TI's microcontroller products. The software is owned by ; TI and/or its suppliers, and is protected under applicable copyright ; laws. You may not combine this software with "viral" open-source ; software in order to form a larger program. ; ; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. ; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT ; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY ; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL ; DAMAGES, FOR ANY REASON WHATSOEVER. ; ; This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. ; ;**************************************************************************** LR_IROM 0x00000000 0x00100000 { ; ; Specify the Execution Address of the code and the size. ; ER_IROM 0x00000000 0x00100000 { .o (RESET, +First) (InRoot$$Sections, +RO) } ; ; Specify the Execution Address of the data area. ; RW_IRAM 0x20000000 0x00040000 { ; ; Uncomment the following line in order to use IntRegister(). ; ;* (vtable, +First) * (+RW, +ZI) } }	{ "language": "Assembly" }
/* Multiple versions of sincosf. Copyright (C) 2017 Free Software Foundation, Inc. This file is part of the GNU C Library. The GNU C Library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version. The GNU C Library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with the GNU C Library; if not, see <http://www.gnu.org/licenses/>. / #include <libm-alias-float.h> extern void __redirect_sincosf (float, float , float *); #define SYMBOL_NAME sincosf #include "ifunc-fma.h" libc_ifunc_redirected (__redirect_sincosf, __sincosf, IFUNC_SELECTOR ()); libm_alias_float (__sincos, sincos)	{ "language": "Assembly" }
// Copyright 2014 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build !gccgo #include "textflag.h" // // System calls for amd64, Solaris are implemented in runtime/syscall_solaris.go // TEXT ·sysvicall6(SB),NOSPLIT,$0-88 JMP syscall·sysvicall6(SB) TEXT ·rawSysvicall6(SB),NOSPLIT,$0-88 JMP syscall·rawSysvicall6(SB)	{ "language": "Assembly" }
; RUN: not llvm-as -disable-output <%s 2>&1 \| FileCheck %s ; CHECK: invalid llvm.dbg.declare intrinsic variable ; CHECK-NEXT: call void @llvm.dbg.declare({{.}}) ; CHECK-NEXT: !"" define void @foo(i32 %a) { entry: %s = alloca i32 call void @llvm.dbg.declare(metadata i32 %s, metadata !"", metadata !DIExpression()), !dbg !DILocation(scope: !1) ret void } declare void @llvm.dbg.declare(metadata, metadata, metadata) !llvm.module.flags = !{!0} !0 = !{i32 2, !"Debug Info Version", i32 3} !1 = distinct !DISubprogram()	{ "language": "Assembly" }
TEXT sin(SB), $0 FMOVD a+0(FP), F0 FSIN RET TEXT cos(SB), $0 FMOVD a+0(FP), F0 FCOS RET	{ "language": "Assembly" }
/* SPDX-License-Identifier: GPL-2.0 / #ifndef _SELFTESTS_POWERPC_BASIC_ASM_H #define _SELFTESTS_POWERPC_BASIC_ASM_H #include <ppc-asm.h> #include <asm/unistd.h> #define LOAD_REG_IMMEDIATE(reg, expr) \ lis reg, (expr)@highest; \ ori reg, reg, (expr)@higher; \ rldicr reg, reg, 32, 31; \ oris reg, reg, (expr)@high; \ ori reg, reg, (expr)@l; / * Note: These macros assume that variables being stored on the stack are * doublewords, while this is usually the case it may not always be the * case for each use case. / #if defined(_CALL_ELF) && _CALL_ELF == 2 #define STACK_FRAME_MIN_SIZE 32 #define STACK_FRAME_TOC_POS 24 #define __STACK_FRAME_PARAM(_param) (32 + ((_param)8)) #define __STACK_FRAME_LOCAL(_num_params, _var_num) \ ((STACK_FRAME_PARAM(_num_params)) + ((_var_num)8)) #else #define STACK_FRAME_MIN_SIZE 112 #define STACK_FRAME_TOC_POS 40 #define __STACK_FRAME_PARAM(i) (48 + ((i)8)) /* * Caveat: if a function passed more than 8 doublewords, the caller will have * made more space... which would render the 112 incorrect. / #define __STACK_FRAME_LOCAL(_num_params, _var_num) \ (112 + ((_var_num)8)) #endif /* Parameter x saved to the stack / #define STACK_FRAME_PARAM(var) __STACK_FRAME_PARAM(var) / Local variable x saved to the stack after x parameters / #define STACK_FRAME_LOCAL(num_params, var) \ __STACK_FRAME_LOCAL(num_params, var) #define STACK_FRAME_LR_POS 16 #define STACK_FRAME_CR_POS 8 / * It is very important to note here that _extra is the extra amount of * stack space needed. This space can be accessed using STACK_FRAME_PARAM() * or STACK_FRAME_LOCAL() macros. * * r1 and r2 are not defined in ppc-asm.h (instead they are defined as sp * and toc). Kernel programmers tend to prefer rX even for r1 and r2, hence * %1 and %r2. r0 is defined in ppc-asm.h and therefore %r0 gets * preprocessed incorrectly, hence r0. / #define PUSH_BASIC_STACK(_extra) \ mflr r0; \ std r0, STACK_FRAME_LR_POS(%r1); \ stdu %r1, -(_extra + STACK_FRAME_MIN_SIZE)(%r1); \ mfcr r0; \ stw r0, STACK_FRAME_CR_POS(%r1); \ std %r2, STACK_FRAME_TOC_POS(%r1); #define POP_BASIC_STACK(_extra) \ ld %r2, STACK_FRAME_TOC_POS(%r1); \ lwz r0, STACK_FRAME_CR_POS(%r1); \ mtcr r0; \ addi %r1, %r1, (_extra + STACK_FRAME_MIN_SIZE); \ ld r0, STACK_FRAME_LR_POS(%r1); \ mtlr r0; #endif / _SELFTESTS_POWERPC_BASIC_ASM_H */	{ "language": "Assembly" }
; RUN: opt < %s -argpromotion -S \| FileCheck %s ; RUN: opt < %s -passes=argpromotion -S \| FileCheck %s %T = type { i32, i32, i32, i32 } @G = constant %T { i32 0, i32 0, i32 17, i32 25 } define internal i32 @test(%T* %p) { ; CHECK-LABEL: define internal i32 @test( ; CHECK: i32 %{{.}}, i32 %{{.}}) entry: %a.gep = getelementptr %T, %T* %p, i64 0, i32 3 %b.gep = getelementptr %T, %T* %p, i64 0, i32 2 %a = load i32, i32* %a.gep %b = load i32, i32* %b.gep ; CHECK-NOT: load %v = add i32 %a, %b ret i32 %v ; CHECK: ret i32 } define i32 @caller() { ; CHECK-LABEL: define i32 @caller( entry: %v = call i32 @test(%T* @G) ; CHECK: %[[B_GEP:.]] = getelementptr %T, %T @G, i64 0, i32 2 ; CHECK: %[[B:.]] = load i32, i32 %[[B_GEP]] ; CHECK: %[[A_GEP:.]] = getelementptr %T, %T @G, i64 0, i32 3 ; CHECK: %[[A:.]] = load i32, i32 %[[A_GEP]] ; CHECK: call i32 @test(i32 %[[B]], i32 %[[A]]) ret i32 %v }	{ "language": "Assembly" }
/* * Moniker generated from PCX/deskicon.pcx with pixel 13 masked out / start AppIconAreaSCMonikerResource, data; visMoniker DisconnectButtonSCMoniker = { size = standard; style = icon; aspectRatio = normal; color = color4; cachedSize = 48, 30; gstring { GSBeginString GSDrawBitmapAtCP 906 Bitmap <48,30,0,BMF_4BIT or mask BMT_MASK> db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x80, 0x21, 0x08, 0x02, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0x0d, 0xdd, 0xdd, 0xdd, 0xdd, 0xed, 0xdd, 0xde, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xdd, 0xdd, 0x0d, 0xdd, 0xdd, 0xdd, 0xdd db 0x01, 0xc0, 0x11, 0x10, 0x03, 0x00 db 0xdd, 0xdd, 0xdd, 0xd0, 0x08, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x00, 0xdd, 0xdd, 0xdd, 0xdd db 0x03, 0xc0, 0x11, 0x10, 0x03, 0x80 db 0xdd, 0xdd, 0xdd, 0x0f, 0x08, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0x0d, 0xdd, 0xdd, 0xdd db 0x07, 0xc0, 0x08, 0x20, 0x03, 0xc0 db 0xdd, 0xdd, 0xd0, 0xff, 0x08, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0xf0, 0xdd, 0xdd, 0xdd db 0x0f, 0xc0, 0x08, 0x20, 0x03, 0xe0 db 0xdd, 0xdd, 0x0f, 0xff, 0x08, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0xff, 0x0d, 0xdd, 0xdd db 0x1f, 0xff, 0xc4, 0x4f, 0xff, 0xf0 db 0xdd, 0xd0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xf0, 0xdd, 0xdd db 0x3f, 0xff, 0xe0, 0x0f, 0xff, 0xf8 db 0xdd, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x8d, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0d, 0xdd db 0x7f, 0xff, 0xe0, 0x0f, 0xff, 0xfc db 0xd0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x8d, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xdd db 0xff, 0xff, 0xe0, 0x0f, 0xff, 0xfe db 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x8d, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0d db 0x7f, 0xff, 0xe0, 0x0f, 0xff, 0xff db 0xd0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x8d, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x88 db 0x3f, 0xff, 0xe0, 0x0f, 0xff, 0xfe db 0xdd, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x8d, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x08, 0x8d db 0x1f, 0xff, 0xe0, 0x0f, 0xff, 0xfc db 0xdd, 0xd0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8d, 0xdd, 0xdd, 0xdd, 0xdd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xf0, 0x88, 0xdd db 0x0f, 0xff, 0xe4, 0x47, 0xff, 0xf8 db 0xdd, 0xdd, 0x0f, 0xff, 0x08, 0x88, 0x88, 0x88, 0x88, 0x8d, 0xde, 0xdd, 0xde, 0xdd, 0xd8, 0x88, 0x88, 0x88, 0x88, 0x0f, 0xff, 0x08, 0x8d, 0xdd db 0x07, 0xc0, 0x08, 0x20, 0x03, 0xf0 db 0xdd, 0xdd, 0xd0, 0xff, 0x08, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0xf0, 0x88, 0xdd, 0xdd db 0x03, 0xc0, 0x08, 0x20, 0x03, 0xe0 db 0xdd, 0xdd, 0xdd, 0x0f, 0x08, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0x08, 0x8d, 0xdd, 0xdd db 0x01, 0xc0, 0x11, 0x10, 0x03, 0xc0 db 0xdd, 0xdd, 0xdd, 0xd0, 0x08, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x00, 0x88, 0xdd, 0xdd, 0xdd db 0x00, 0xc0, 0x11, 0x10, 0x03, 0x80 db 0xdd, 0xdd, 0xdd, 0xdd, 0x08, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x08, 0x8d, 0xdd, 0xdd, 0xdd db 0x00, 0x40, 0x21, 0x08, 0x01, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xd8, 0xdd, 0xdd, 0xdd, 0xdd, 0xed, 0xdd, 0xde, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xdd, 0xdd, 0xd8, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd GSEndString } } end AppIconAreaSCMonikerResource; / * Moniker generated from PCX/deskicon.pcx with pixel 13 masked out / start AppIconAreaSMMonikerResource, data; visMoniker DisconnectButtonSMMoniker = { size = standard; style = icon; aspectRatio = normal; color = gray1; cachedSize = 48, 30; gstring { GSBeginString GSFillBitmapAtCP 186 Bitmap <48,30,0,BMF_MONO> db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 db 0x00, 0x80, 0x21, 0x08, 0x02, 0x00 db 0x01, 0xc0, 0x11, 0x10, 0x03, 0x00 db 0x02, 0xc0, 0x11, 0x10, 0x02, 0x80 db 0x04, 0xc0, 0x08, 0x20, 0x02, 0x40 db 0x08, 0xc0, 0x08, 0x20, 0x02, 0x20 db 0x10, 0xff, 0xc4, 0x4f, 0xfe, 0x10 db 0x20, 0x00, 0x60, 0x08, 0x00, 0x08 db 0x40, 0x00, 0x60, 0x08, 0x00, 0x04 db 0x80, 0x00, 0x60, 0x08, 0x00, 0x02 db 0x40, 0x00, 0x60, 0x08, 0x00, 0x07 db 0x20, 0x00, 0x60, 0x08, 0x00, 0x0e db 0x10, 0xff, 0xe0, 0x0f, 0xfe, 0x1c db 0x08, 0xff, 0xe4, 0x47, 0xfe, 0x38 db 0x04, 0xc0, 0x08, 0x20, 0x02, 0x70 db 0x02, 0xc0, 0x08, 0x20, 0x02, 0xe0 db 0x01, 0xc0, 0x11, 0x10, 0x03, 0xc0 db 0x00, 0xc0, 0x11, 0x10, 0x03, 0x80 db 0x00, 0x40, 0x21, 0x08, 0x01, 0x00 db 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 GSEndString } } end AppIconAreaSMMonikerResource; / * Moniker generated from PCX/deskicon.pcx with pixel 13 masked out */ start AppIconAreaSCGAMonikerResource, data; visMoniker DisconnectButtonSCGAMoniker = { size = tiny; style = icon; aspectRatio = verySquished; color = gray1; cachedSize = 48, 14; gstring { GSBeginString GSFillBitmapAtCP 90 Bitmap <48,14,0,BMF_MONO> db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x81, 0x81, 0x00, 0x00 db 0x00, 0xc0, 0x61, 0x86, 0x06, 0x00 db 0x03, 0x70, 0x19, 0x98, 0x05, 0x80 db 0x0c, 0x7f, 0x84, 0x23, 0xfc, 0x60 db 0x30, 0x00, 0xe0, 0x02, 0x00, 0x18 db 0xc0, 0x00, 0xe0, 0x02, 0x00, 0x07 db 0x30, 0x00, 0xe0, 0x02, 0x00, 0x1f db 0x0c, 0x7f, 0xe0, 0x03, 0xfc, 0x7c db 0x03, 0x7f, 0xe4, 0x21, 0xfd, 0xf0 db 0x00, 0xf0, 0x19, 0x98, 0x07, 0xc0 db 0x00, 0x30, 0x61, 0x86, 0x01, 0x00 db 0x00, 0x00, 0x81, 0x81, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 GSEndString } } end AppIconAreaSCGAMonikerResource;	{ "language": "Assembly" }
test compile target x86_64 function u0:51(i64, i64) system_v { ss0 = explicit_slot 0 ss1 = explicit_slot 1 ss2 = explicit_slot 1 ss3 = explicit_slot 1 block0(v0: i64, v1: i64): v2 = stack_addr.i64 ss1 v3 = load.i8 v1 store v3, v2 v4 = stack_addr.i64 ss2 v5 = stack_addr.i64 ss3 jump block1 block1: v6 = load.i8 v2 store v6, v5 v7 = load.i8 v5 v8 = bnot v7 store v8, v4 v9 = load.i8 v4 store v9, v0 return }	{ "language": "Assembly" }
/* -- Mode: C; indent-tabs-mode: t; c-basic-offset: 8; tab-width: 8 -- eel-lib-self-check-functions.h: Wrapper and prototypes for all self-check functions in libeel. Copyright (C) 2000 Eazel, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU Library General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Library General Public License for more details. You should have received a copy of the GNU Library General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Suite 500, Boston, MA 02110-1335, USA. Author: Darin Adler <[email protected]> / #include "eel-self-checks.h" void eel_run_lib_self_checks (void); / Putting the prototypes for these self-check functions in each header file for the files they are defined in would make compiling the self-check framework take way too long (since one file would have to include everything). So we put the list of functions here instead. Instead of just putting prototypes here, we put this macro that can be used to do operations on the whole list of functions. / #define EEL_LIB_FOR_EACH_SELF_CHECK_FUNCTION(macro) \ macro (eel_self_check_glib_extensions) \ macro (eel_self_check_string) \ / Add new self-check functions to the list above this line. / / Generate prototypes for all the functions. */ EEL_LIB_FOR_EACH_SELF_CHECK_FUNCTION (EEL_SELF_CHECK_FUNCTION_PROTOTYPE)	{ "language": "Assembly" }
/* This linker script generated from xt-genldscripts.tpp for LSP . / / Linker Script for ld -N / MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 iram1_0_seg : org = 0x40100000, len = 0x8000 irom0_0_seg : org = 0x40208000 + 0x1000, len = 0x33000 } PHDRS { dport0_0_phdr PT_LOAD; dram0_0_phdr PT_LOAD; dram0_0_bss_phdr PT_LOAD; iram1_0_phdr PT_LOAD; irom0_0_phdr PT_LOAD; } / Default entry point: / ENTRY(call_user_start) EXTERN(_DebugExceptionVector) EXTERN(_DoubleExceptionVector) EXTERN(_KernelExceptionVector) EXTERN(_NMIExceptionVector) EXTERN(_UserExceptionVector) PROVIDE(_memmap_vecbase_reset = 0x40000000); / Various memory-map dependent cache attribute settings: / _memmap_cacheattr_wb_base = 0x00000110; _memmap_cacheattr_wt_base = 0x00000110; _memmap_cacheattr_bp_base = 0x00000220; _memmap_cacheattr_unused_mask = 0xFFFFF00F; _memmap_cacheattr_wb_trapnull = 0x2222211F; _memmap_cacheattr_wba_trapnull = 0x2222211F; _memmap_cacheattr_wbna_trapnull = 0x2222211F; _memmap_cacheattr_wt_trapnull = 0x2222211F; _memmap_cacheattr_bp_trapnull = 0x2222222F; _memmap_cacheattr_wb_strict = 0xFFFFF11F; _memmap_cacheattr_wt_strict = 0xFFFFF11F; _memmap_cacheattr_bp_strict = 0xFFFFF22F; _memmap_cacheattr_wb_allvalid = 0x22222112; _memmap_cacheattr_wt_allvalid = 0x22222112; _memmap_cacheattr_bp_allvalid = 0x22222222; PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); SECTIONS { .dport0.rodata : ALIGN(4) { _dport0_rodata_start = ABSOLUTE(.); (.dport0.rodata) (.dport.rodata) _dport0_rodata_end = ABSOLUTE(.); } >dport0_0_seg :dport0_0_phdr .dport0.literal : ALIGN(4) { _dport0_literal_start = ABSOLUTE(.); (.dport0.literal) (.dport.literal) _dport0_literal_end = ABSOLUTE(.); } >dport0_0_seg :dport0_0_phdr .dport0.data : ALIGN(4) { _dport0_data_start = ABSOLUTE(.); (.dport0.data) (.dport.data) _dport0_data_end = ABSOLUTE(.); } >dport0_0_seg :dport0_0_phdr .data : ALIGN(4) { _data_start = ABSOLUTE(.); (.data) (.data.) (.gnu.linkonce.d.) (.data1) (.sdata) (.sdata.) (.gnu.linkonce.s.) (.sdata2) (.sdata2.) (.gnu.linkonce.s2.) (.jcr) _data_end = ABSOLUTE(.); } >dram0_0_seg :dram0_0_phdr .rodata : ALIGN(4) { _rodata_start = ABSOLUTE(.); (.sdk.version) (.rodata) (.rodata.) (.gnu.linkonce.r.) (.rodata1) __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); (.xt_except_table) (.gcc_except_table) (.gnu.linkonce.e.) (.gnu.version_r) (.eh_frame) / C++ constructor and destructor tables, properly ordered: / KEEP (crtbegin.o(.ctors)) KEEP ((EXCLUDE_FILE (crtend.o) .ctors)) KEEP ((SORT(.ctors.))) KEEP ((.ctors)) KEEP (crtbegin.o(.dtors)) KEEP ((EXCLUDE_FILE (crtend.o) .dtors)) KEEP ((SORT(.dtors.))) KEEP ((.dtors)) / C++ exception handlers table: / __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); (.xt_except_desc) (.gnu.linkonce.h.) __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); (.xt_except_desc_end) (.dynamic) (.gnu.version_d) . = ALIGN(4); / this table MUST be 4-byte aligned / _bss_table_start = ABSOLUTE(.); LONG(_bss_start) LONG(_bss_end) _bss_table_end = ABSOLUTE(.); _rodata_end = ABSOLUTE(.); } >dram0_0_seg :dram0_0_phdr .bss ALIGN(8) (NOLOAD) : ALIGN(4) { . = ALIGN (8); _bss_start = ABSOLUTE(.); (.dynsbss) (.sbss) (.sbss.) (.gnu.linkonce.sb.) (.scommon) (.sbss2) (.sbss2.) (.gnu.linkonce.sb2.) (.dynbss) (.bss) (.bss.) (.gnu.linkonce.b.) (COMMON) . = ALIGN (8); _bss_end = ABSOLUTE(.); _heap_start = ABSOLUTE(.); /* _stack_sentry = ALIGN(0x8); / } >dram0_0_seg :dram0_0_bss_phdr / __stack = 0x3ffc8000; / .irom0.text : ALIGN(4) { _irom0_text_start = ABSOLUTE(.); libmbedtls.a:(.literal .text .literal.* .text.) /libaxtls.a:(.literal, .text) main.o(.literal, .text) /ota.o(.literal, .text)/ (.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text) _irom0_text_end = ABSOLUTE(.); } >irom0_0_seg :irom0_0_phdr .text : ALIGN(4) { _stext = .; _text_start = ABSOLUTE(.); (.UserEnter.text) . = ALIGN(16); (.DebugExceptionVector.text) . = ALIGN(16); (.NMIExceptionVector.text) . = ALIGN(16); (.KernelExceptionVector.text) LONG(0) LONG(0) LONG(0) LONG(0) . = ALIGN(16); (.UserExceptionVector.text) LONG(0) LONG(0) LONG(0) LONG(0) . = ALIGN(16); (.DoubleExceptionVector.text) LONG(0) LONG(0) LONG(0) LONG(0) . = ALIGN (16); (.entry.text) (.init.literal) (.init) (.literal .text .literal. .text.* .iram0.literal .iram0.text .iram0.text..literal .iram0.text.) (.stub .gnu.warning .gnu.linkonce.literal. .gnu.linkonce.t..literal .gnu.linkonce.t.) (.fini.literal) (.fini) (.gnu.version) _text_end = ABSOLUTE(.); _etext = .; } >iram1_0_seg :iram1_0_phdr .lit4 : ALIGN(4) { _lit4_start = ABSOLUTE(.); (.lit4) (.lit4.) (.gnu.linkonce.lit4.) _lit4_end = ABSOLUTE(.); } >iram1_0_seg :iram1_0_phdr } / get ROM code address */ INCLUDE "../boot8266/eagle.rom.addr.v6.ld"	{ "language": "Assembly" }
# RUN: llvm-mc -triple i386-unknown-unknown %s \| FileCheck %s # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifc foo, foo .byte 1 .else .byte 0 .endif # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifc "foo space", "foo space" .byte 1 .else .byte 0 .endif # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifc foo space, foo space .byte 1 .else .byte 0 .endif # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifc unequal, unEqual .byte 0 .else .byte 1 .endif # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifnc foo, foo .byte 0 .else .byte 1 .endif # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifnc "foo space", "foo space" .byte 0 .else .byte 1 .endif # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifnc foo space, foo space .byte 0 .else .byte 1 .endif # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifnc unequal, unEqual .byte 1 .else .byte 0 .endif # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifnc equal, equal ; .byte 0 ; .else ; .byte 1 ; .endif	{ "language": "Assembly" }
// RUN: %clang_cc1 -O0 -triple spir -emit-llvm %s -o - \| FileCheck %s // RUN: %clang_cc1 -O0 -triple spir64 -emit-llvm %s -o - \| FileCheck %s // RUN: %clang_cc1 -O0 -triple spir -fexperimental-new-pass-manager -emit-llvm %s -o - \| FileCheck %s // RUN: %clang_cc1 -O0 -triple spir64 -fexperimental-new-pass-manager -emit-llvm %s -o - \| FileCheck %s // This file tests that using the _Float16 type with the spir target will not // use the llvm intrinsics but instead will use the half arithmetic // instructions directly. // Previously attempting to use a constant _Float16 with a comparison // instruction when the target is spir or spir64 lead to an assert being hit. bool fcmp_const() { _Float16 a = 0.0f16; const _Float16 b = 1.0f16; // CHECK-NOT: llvm.convert.to.fp16 // CHECK-NOT: llvm.convert.from.fp16 // CHECK: [[REG1:%.]] = load half, half %a, align 2 // CHECK-NEXT: fcmp olt half [[REG1]], 0xH3C00 // CHECK: [[REG2:%.]] = load half, half %a, align 2 // CHECK-NEXT: fcmp olt half [[REG2]], 0xH4000 // CHECK: [[REG3:%.]] = load half, half %a, align 2 // CHECK-NEXT: fcmp ogt half [[REG3]], 0xH3C00 // CHECK: [[REG4:%.]] = load half, half %a, align 2 // CHECK-NEXT: fcmp ogt half [[REG4]], 0xH4200 // CHECK: [[REG5:%.]] = load half, half %a, align 2 // CHECK-NEXT: fcmp oeq half [[REG5]], 0xH3C00 // CHECK: [[REG7:%.]] = load half, half %a, align 2 // CHECK-NEXT: fcmp oeq half [[REG7]], 0xH4400 // CHECK: [[REG8:%.]] = load half, half %a, align 2 // CHECK-NEXT: fcmp une half [[REG8]], 0xH3C00 // CHECK: [[REG9:%.]] = load half, half %a, align 2 // CHECK-NEXT: fcmp une half [[REG9]], 0xH4500 // CHECK: [[REG10:%.]] = load half, half %a, align 2 // CHECK-NEXT: fcmp ole half [[REG10]], 0xH3C00 // CHECK: [[REG11:%.]] = load half, half %a, align 2 // CHECK-NEXT: fcmp ole half [[REG11]], 0xH4600 // CHECK: [[REG12:%.]] = load half, half %a, align 2 // CHECK-NEXT: fcmp oge half [[REG12]], 0xH3C00 // CHECK: [[REG13:%.]] = load half, half %a, align 2 // CHECK-NEXT: fcmp oge half [[REG13]], 0xH4700 return a < b \|\| a < 2.0f16 \|\| a > b \|\| a > 3.0f16 \|\| a == b \|\| a == 4.0f16 \|\| a != b \|\| a != 5.0f16 \|\| a <= b \|\| a <= 6.0f16 \|\| a >= b \|\| a >= 7.0f16; } bool fcmp() { _Float16 a = 0.0f16; _Float16 b = 1.0f16; // CHECK-NOT: llvm.convert.to.fp16 // CHECK-NOT: llvm.convert.from.fp16 // CHECK: [[REG1:%.]] = load half, half %a, align 2 // CHECK-NEXT: [[REG2:%.]] = load half, half %b, align 2 // CHECK-NEXT: fcmp olt half [[REG1]], [[REG2]] // CHECK: [[REG3:%.]] = load half, half %a, align 2 // CHECK-NEXT: [[REG4:%.]] = load half, half %b, align 2 // CHECK-NEXT: fcmp ogt half [[REG3]], [[REG4]] // CHECK: [[REG5:%.]] = load half, half %a, align 2 // CHECK-NEXT: [[REG6:%.]] = load half, half %b, align 2 // CHECK-NEXT: fcmp oeq half [[REG5]], [[REG6]] // CHECK: [[REG7:%.]] = load half, half %a, align 2 // CHECK-NEXT: [[REG8:%.]] = load half, half %b, align 2 // CHECK-NEXT: fcmp une half [[REG7]], [[REG8]] // CHECK: [[REG7:%.]] = load half, half %a, align 2 // CHECK-NEXT: [[REG8:%.]] = load half, half %b, align 2 // CHECK-NEXT: fcmp ole half [[REG7]], [[REG8]] // CHECK: [[REG7:%.]] = load half, half %a, align 2 // CHECK-NEXT: [[REG8:%.]] = load half, half %b, align 2 // CHECK-NEXT: fcmp oge half [[REG7]], [[REG8]] return a < b \|\| a > b \|\| a == b \|\| a != b \|\| a <= b \|\| a >= b; } _Float16 fadd() { _Float16 a = 1.0f16; const _Float16 b = 2.0f16; // CHECK-NOT: llvm.convert.to.fp16 // CHECK-NOT: llvm.convert.from.fp16 // CHECK: [[REG1:%.]] = load half, half %a, align 2 // CHECK-NEXT: [[REG2:%.]] = fadd half [[REG1]], 0xH4000 // CHECK-NEXT: [[REG3:%.]] = fadd half [[REG2]], 0xH4200 // CHECK-NEXT: ret half [[REG3]] return a + b + 3.0f16; } _Float16 fsub() { _Float16 a = 1.0f16; const _Float16 b = 2.0f16; // CHECK-NOT: llvm.convert.to.fp16 // CHECK-NOT: llvm.convert.from.fp16 // CHECK: [[REG1:%.]] = load half, half %a, align 2 // CHECK-NEXT: [[REG2:%.]] = fsub half [[REG1]], 0xH4000 // CHECK-NEXT: [[REG3:%.]] = fsub half [[REG2]], 0xH4200 // CHECK-NEXT: ret half [[REG3]] return a - b - 3.0f16; } // CHECK: define spir_func half @_Z4fmulDF16_(half %arg) _Float16 fmul(_Float16 arg) { _Float16 a = 1.0f16; const _Float16 b = 2.0f16; // CHECK-NOT: llvm.convert.to.fp16 // CHECK-NOT: llvm.convert.from.fp16 // CHECK: [[REG1:%.]] = load half, half %a, align 2 // CHECK-NEXT: [[REG2:%.]] = load half, half %arg.addr, align 2 // CHECK-NEXT: [[REG3:%.]] = fmul half [[REG1]], [[REG2]] // CHECK-NEXT: [[REG4:%.]] = fmul half [[REG3]], 0xH4000 // CHECK-NEXT: [[REG5:%.]] = fmul half [[REG4]], 0xH4200 // CHECK-NEXT: ret half [[REG5]] return a arg * b * 3.0f16; } _Float16 fdiv() { _Float16 a = 1.0f16; const _Float16 b = 2.0f16; // CHECK-NOT: llvm.convert.to.fp16 // CHECK-NOT: llvm.convert.from.fp16 // CHECK: [[REG1:%.]] = load half, half %a, align 2 // CHECK-NEXT: [[REG2:%.]] = fdiv half [[REG1]], 0xH4000 // CHECK-NEXT: [[REG3:%.]] = fdiv half [[REG2]], 0xH4200 // CHECK-NEXT: ret half [[REG3]] return a / b / 3.0f16; }	{ "language": "Assembly" }
@ RUN: llvm-mc -n -triple armv7-apple-darwin10 %s -filetype=obj -o %t.obj @ RUN: macho-dump --dump-section-data < %t.obj > %t.dump @ RUN: FileCheck < %t.dump %s .syntax unified .text _f0: bl _printf _f1: bl _f0 .data _d0: Ld0_0: .long Lsc0_0 - Ld0_0 .section __TEXT,__cstring,cstring_literals Lsc0_0: .long 0 .subsections_via_symbols @ CHECK: ('cputype', 12) @ CHECK: ('cpusubtype', 9) @ CHECK: ('filetype', 1) @ CHECK: ('num_load_commands', 3) @ CHECK: ('load_commands_size', 364) @ CHECK: ('flag', 8192) @ CHECK: ('load_commands', [ @ CHECK: # Load Command 0 @ CHECK: (('command', 1) @ CHECK: ('size', 260) @ CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @ CHECK: ('vm_addr', 0) @ CHECK: ('vm_size', 16) @ CHECK: ('file_offset', 392) @ CHECK: ('file_size', 16) @ CHECK: ('maxprot', 7) @ CHECK: ('initprot', 7) @ CHECK: ('num_sections', 3) @ CHECK: ('flags', 0) @ CHECK: ('sections', [ @ CHECK: # Section 0 @ CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @ CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @ CHECK: ('address', 0) @ CHECK: ('size', 8) @ CHECK: ('offset', 392) @ CHECK: ('alignment', 0) @ CHECK: ('reloc_offset', 408) @ CHECK: ('num_reloc', 2) @ CHECK: ('flags', 0x80000400) @ CHECK: ('reserved1', 0) @ CHECK: ('reserved2', 0) @ CHECK: ), @ CHECK: ('_relocations', [ @ CHECK: # Relocation 0 @ CHECK: (('word-0', 0x4), @ CHECK: ('word-1', 0x55000001)), @ CHECK: # Relocation 1 @ CHECK: (('word-0', 0x0), @ CHECK: ('word-1', 0x5d000003)), @ CHECK: ]) @ CHECK: ('_section_data', 'feffffeb fdffffeb') @ CHECK: # Section 1 @ CHECK: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @ CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @ CHECK: ('address', 8) @ CHECK: ('size', 4) @ CHECK: ('offset', 400) @ CHECK: ('alignment', 0) @ CHECK: ('reloc_offset', 424) @ CHECK: ('num_reloc', 2) @ CHECK: ('flags', 0x0) @ CHECK: ('reserved1', 0) @ CHECK: ('reserved2', 0) @ CHECK: ), @ CHECK: ('_relocations', [ @ CHECK: # Relocation 0 @ CHECK: (('word-0', 0xa2000000), @ CHECK: ('word-1', 0xc)), @ CHECK: # Relocation 1 @ CHECK: (('word-0', 0xa1000000), @ CHECK: ('word-1', 0x8)), @ CHECK: ]) @ CHECK: ('_section_data', '04000000') @ CHECK: # Section 2 @ CHECK: (('section_name', '__cstring\x00\x00\x00\x00\x00\x00\x00') @ CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @ CHECK: ('address', 12) @ CHECK: ('size', 4) @ CHECK: ('offset', 404) @ CHECK: ('alignment', 0) @ CHECK: ('reloc_offset', 0) @ CHECK: ('num_reloc', 0) @ CHECK: ('flags', 0x2) @ CHECK: ('reserved1', 0) @ CHECK: ('reserved2', 0) @ CHECK: ), @ CHECK: ('_relocations', [ @ CHECK: ]) @ CHECK: ('_section_data', '00000000') @ CHECK: ]) @ CHECK: ), @ CHECK: # Load Command 1 @ CHECK: (('command', 2) @ CHECK: ('size', 24) @ CHECK: ('symoff', 440) @ CHECK: ('nsyms', 4) @ CHECK: ('stroff', 488) @ CHECK: ('strsize', 24) @ CHECK: ('_string_data', '\x00_printf\x00_f1\x00_f0\x00_d0\x00\x00\x00\x00') @ CHECK: ('_symbols', [ @ CHECK: # Symbol 0 @ CHECK: (('n_strx', 13) @ CHECK: ('n_type', 0xe) @ CHECK: ('n_sect', 1) @ CHECK: ('n_desc', 0) @ CHECK: ('n_value', 0) @ CHECK: ('_string', '_f0') @ CHECK: ), @ CHECK: # Symbol 1 @ CHECK: (('n_strx', 9) @ CHECK: ('n_type', 0xe) @ CHECK: ('n_sect', 1) @ CHECK: ('n_desc', 0) @ CHECK: ('n_value', 4) @ CHECK: ('_string', '_f1') @ CHECK: ), @ CHECK: # Symbol 2 @ CHECK: (('n_strx', 17) @ CHECK: ('n_type', 0xe) @ CHECK: ('n_sect', 2) @ CHECK: ('n_desc', 0) @ CHECK: ('n_value', 8) @ CHECK: ('_string', '_d0') @ CHECK: ), @ CHECK: # Symbol 3 @ CHECK: (('n_strx', 1) @ CHECK: ('n_type', 0x1) @ CHECK: ('n_sect', 0) @ CHECK: ('n_desc', 0) @ CHECK: ('n_value', 0) @ CHECK: ('_string', '_printf') @ CHECK: ), @ CHECK: ]) @ CHECK: ), @ CHECK: # Load Command 2 @ CHECK: (('command', 11) @ CHECK: ('size', 80) @ CHECK: ('ilocalsym', 0) @ CHECK: ('nlocalsym', 3) @ CHECK: ('iextdefsym', 3) @ CHECK: ('nextdefsym', 0) @ CHECK: ('iundefsym', 3) @ CHECK: ('nundefsym', 1) @ CHECK: ('tocoff', 0) @ CHECK: ('ntoc', 0) @ CHECK: ('modtaboff', 0) @ CHECK: ('nmodtab', 0) @ CHECK: ('extrefsymoff', 0) @ CHECK: ('nextrefsyms', 0) @ CHECK: ('indirectsymoff', 0) @ CHECK: ('nindirectsyms', 0) @ CHECK: ('extreloff', 0) @ CHECK: ('nextrel', 0) @ CHECK: ('locreloff', 0) @ CHECK: ('nlocrel', 0) @ CHECK: ('_indirect_symbols', [ @ CHECK: ]) @ CHECK: ), @ CHECK: ])	{ "language": "Assembly" }
# xalloc.m4 serial 18 dnl Copyright (C) 2002-2006, 2009-2015 Free Software Foundation, Inc. dnl This file is free software; the Free Software Foundation dnl gives unlimited permission to copy and/or distribute it, dnl with or without modifications, as long as this notice is preserved. AC_DEFUN([gl_XALLOC], [:])	{ "language": "Assembly" }
#! /usr/bin/env perl # Copyright 2016-2020 The OpenSSL Project Authors. All Rights Reserved. # # Licensed under the OpenSSL license (the "License"). You may not use # this file except in compliance with the License. You can obtain a copy # in the file LICENSE in the source distribution or at # https://www.openssl.org/source/license.html # # ==================================================================== # Written by Andy Polyakov <[email protected]> for the OpenSSL # project. The module is, however, dual licensed under OpenSSL and # CRYPTOGAMS licenses depending on where you obtain it. For further # details see http://www.openssl.org/~appro/cryptogams/. # ==================================================================== # # ChaCha20 for C64x+. # # October 2015 # # Performance is 3.54 cycles per processed byte, which is ~4.3 times # faster than code generated by TI compiler. Compiler also disables # interrupts for some reason, thus making interrupt response time # dependent on input length. This module on the other hand is free # from such limitation. $output=pop; open STDOUT,">$output"; ($OUT,$INP,$LEN,$KEYB,$COUNTERA)=("A4","B4","A6","B6","A8"); ($KEYA,$COUNTERB,$STEP)=("A7","B7","A3"); @X= ("A16","B16","A17","B17","A18","B18","A19","B19", "A20","B20","A21","B21","A22","B22","A23","B23"); @Y= ("A24","B24","A25","B25","A26","B26","A27","B27", "A28","B28","A29","B29","A30","B30","A31","B31"); @DAT=("A6", "A7", "B6", "B7", "A8", "A9", "B8", "B9", "A10","A11","B10","B11","A12","A13","B12","B13"); # yes, overlaps with @DAT, used only in 2x interleave code path... @K2x=("A6", "B6", "A7", "B7", "A8", "B8", "A9", "B9", "A10","B10","A11","B11","A2", "B2", "A13","B13"); $code.=<<___; .text .if .ASSEMBLER_VERSION<7000000 .asg 0,__TI_EABI__ .endif .if __TI_EABI__ .asg ChaCha20_ctr32,_ChaCha20_ctr32 .endif .asg B3,RA .asg A15,FP .asg B15,SP .global _ChaCha20_ctr32 .align 32 _ChaCha20_ctr32: .asmfunc stack_usage(40+64) MV $LEN,A0 ; reassign [!A0] BNOP RA ; no data \|\| [A0] STW FP,SP--(40+64) ; save frame pointer and alloca(40+64) \|\| [A0] MV SP,FP [A0] STDW B13:B12,SP[4+8] ; ABI says so \|\| [A0] MV $KEYB,$KEYA \|\| [A0] MV $COUNTERA,$COUNTERB [A0] STDW B11:B10,SP[3+8] \|\| [A0] STDW A13:A12,FP[-3] [A0] STDW A11:A10,FP[-4] \|\| [A0] MVK 128,$STEP ; 2 input block size [A0] LDW ${KEYA}[0],@Y[4] ; load key \|\| [A0] LDW ${KEYB}[1],@Y[5] \|\| [A0] MVK 0x00007865,@Y[0] ; synthesize sigma \|\| [A0] MVK 0x0000646e,@Y[1] [A0] LDW ${KEYA}[2],@Y[6] \|\| [A0] LDW ${KEYB}[3],@Y[7] \|\| [A0] MVKH 0x61700000,@Y[0] \|\| [A0] MVKH 0x33200000,@Y[1] LDW ${KEYA}[4],@Y[8] \|\| LDW ${KEYB}[5],@Y[9] \|\| MVK 0x00002d32,@Y[2] \|\| MVK 0x00006574,@Y[3] LDW ${KEYA}[6],@Y[10] \|\| LDW ${KEYB}[7],@Y[11] \|\| MVKH 0x79620000,@Y[2] \|\| MVKH 0x6b200000,@Y[3] LDW ${COUNTERA}[0],@Y[12] ; load counter\|\|nonce \|\| LDW ${COUNTERB}[1],@Y[13] \|\| CMPLTU A0,$STEP,A1 ; is length < 2blocks? LDW ${COUNTERA}[2],@Y[14] \|\| LDW ${COUNTERB}[3],@Y[15] \|\| [A1] BNOP top1x? [A1] MVK 64,$STEP ; input block size \|\| MVK 10,B0 ; inner loop counter DMV @Y[2],@Y[0],@X[2]:@X[0] ; copy block \|\| DMV @Y[3],@Y[1],@X[3]:@X[1] \|\|[!A1] STDW @Y[2]:@Y[0],FP[-12] ; offload key material to stack \|\|[!A1] STDW @Y[3]:@Y[1],SP[2] DMV @Y[6],@Y[4],@X[6]:@X[4] \|\| DMV @Y[7],@Y[5],@X[7]:@X[5] \|\|[!A1] STDW @Y[6]:@Y[4],FP[-10] \|\|[!A1] STDW @Y[7]:@Y[5],SP[4] DMV @Y[10],@Y[8],@X[10]:@X[8] \|\| DMV @Y[11],@Y[9],@X[11]:@X[9] \|\|[!A1] STDW @Y[10]:@Y[8],FP[-8] \|\|[!A1] STDW @Y[11]:@Y[9],SP[6] DMV @Y[14],@Y[12],@X[14]:@X[12] \|\| DMV @Y[15],@Y[13],@X[15]:@X[13] \|\|[!A1] MV @Y[12],@K2x[12] ; counter \|\|[!A1] MV @Y[13],@K2x[13] \|\|[!A1] STW @Y[14],FP[-62] \|\|[!A1] STW @Y[15],SP[82] ___ { ################################################################ # 2x interleave gives 50% performance improvement # my ($a0,$a1,$a2,$a3) = (0..3); my ($b0,$b1,$b2,$b3) = (4..7); my ($c0,$c1,$c2,$c3) = (8..11); my ($d0,$d1,$d2,$d3) = (12..15); $code.=<<___; outer2x?: ADD @X[$b1],@X[$a1],@X[$a1] \|\| ADD @X[$b2],@X[$a2],@X[$a2] \|\| ADD @X[$b0],@X[$a0],@X[$a0] \|\| ADD @X[$b3],@X[$a3],@X[$a3] \|\| DMV @Y[2],@Y[0],@K2x[2]:@K2x[0] \|\| DMV @Y[3],@Y[1],@K2x[3]:@K2x[1] XOR @X[$a1],@X[$d1],@X[$d1] \|\| XOR @X[$a2],@X[$d2],@X[$d2] \|\| XOR @X[$a0],@X[$d0],@X[$d0] \|\| XOR @X[$a3],@X[$d3],@X[$d3] \|\| DMV @Y[6],@Y[4],@K2x[6]:@K2x[4] \|\| DMV @Y[7],@Y[5],@K2x[7]:@K2x[5] SWAP2 @X[$d1],@X[$d1] ; rotate by 16 \|\| SWAP2 @X[$d2],@X[$d2] \|\| SWAP2 @X[$d0],@X[$d0] \|\| SWAP2 @X[$d3],@X[$d3] ADD @X[$d1],@X[$c1],@X[$c1] \|\| ADD @X[$d2],@X[$c2],@X[$c2] \|\| ADD @X[$d0],@X[$c0],@X[$c0] \|\| ADD @X[$d3],@X[$c3],@X[$c3] \|\| DMV @Y[10],@Y[8],@K2x[10]:@K2x[8] \|\| DMV @Y[11],@Y[9],@K2x[11]:@K2x[9] XOR @X[$c1],@X[$b1],@X[$b1] \|\| XOR @X[$c2],@X[$b2],@X[$b2] \|\| XOR @X[$c0],@X[$b0],@X[$b0] \|\| XOR @X[$c3],@X[$b3],@X[$b3] \|\| ADD 1,@Y[12],@Y[12] ; adjust counter for 2nd block ROTL @X[$b1],12,@X[$b1] \|\| ROTL @X[$b2],12,@X[$b2] \|\| MV @Y[14],@K2x[14] \|\| MV @Y[15],@K2x[15] top2x?: ROTL @X[$b0],12,@X[$b0] \|\| ROTL @X[$b3],12,@X[$b3] \|\| ADD @Y[$b1],@Y[$a1],@Y[$a1] \|\| ADD @Y[$b2],@Y[$a2],@Y[$a2] ADD @Y[$b0],@Y[$a0],@Y[$a0] \|\| ADD @Y[$b3],@Y[$a3],@Y[$a3] \|\| ADD @X[$b1],@X[$a1],@X[$a1] \|\| ADD @X[$b2],@X[$a2],@X[$a2] \|\| XOR @Y[$a1],@Y[$d1],@Y[$d1] \|\| XOR @Y[$a2],@Y[$d2],@Y[$d2] XOR @Y[$a0],@Y[$d0],@Y[$d0] \|\| XOR @Y[$a3],@Y[$d3],@Y[$d3] \|\| ADD @X[$b0],@X[$a0],@X[$a0] \|\| ADD @X[$b3],@X[$a3],@X[$a3] \|\| XOR @X[$a1],@X[$d1],@X[$d1] \|\| XOR @X[$a2],@X[$d2],@X[$d2] XOR @X[$a0],@X[$d0],@X[$d0] \|\| XOR @X[$a3],@X[$d3],@X[$d3] \|\| ROTL @X[$d1],8,@X[$d1] \|\| ROTL @X[$d2],8,@X[$d2] \|\| SWAP2 @Y[$d1],@Y[$d1] ; rotate by 16 \|\| SWAP2 @Y[$d2],@Y[$d2] \|\| SWAP2 @Y[$d0],@Y[$d0] \|\| SWAP2 @Y[$d3],@Y[$d3] ROTL @X[$d0],8,@X[$d0] \|\| ROTL @X[$d3],8,@X[$d3] \|\| ADD @Y[$d1],@Y[$c1],@Y[$c1] \|\| ADD @Y[$d2],@Y[$c2],@Y[$c2] \|\| ADD @Y[$d0],@Y[$c0],@Y[$c0] \|\| ADD @Y[$d3],@Y[$c3],@Y[$c3] \|\| BNOP middle2x1? ; protect from interrupt ADD @X[$d1],@X[$c1],@X[$c1] \|\| ADD @X[$d2],@X[$c2],@X[$c2] \|\| XOR @Y[$c1],@Y[$b1],@Y[$b1] \|\| XOR @Y[$c2],@Y[$b2],@Y[$b2] \|\| XOR @Y[$c0],@Y[$b0],@Y[$b0] \|\| XOR @Y[$c3],@Y[$b3],@Y[$b3] ADD @X[$d0],@X[$c0],@X[$c0] \|\| ADD @X[$d3],@X[$c3],@X[$c3] \|\| XOR @X[$c1],@X[$b1],@X[$b1] \|\| XOR @X[$c2],@X[$b2],@X[$b2] \|\| ROTL @X[$d1],0,@X[$d2] ; moved to avoid cross-path stall \|\| ROTL @X[$d2],0,@X[$d3] XOR @X[$c0],@X[$b0],@X[$b0] \|\| XOR @X[$c3],@X[$b3],@X[$b3] \|\| MV @X[$d0],@X[$d1] \|\| MV @X[$d3],@X[$d0] \|\| ROTL @Y[$b1],12,@Y[$b1] \|\| ROTL @Y[$b2],12,@Y[$b2] ROTL @X[$b1],7,@X[$b0] ; avoided cross-path stall \|\| ROTL @X[$b2],7,@X[$b1] ROTL @X[$b0],7,@X[$b3] \|\| ROTL @X[$b3],7,@X[$b2] middle2x1?: ROTL @Y[$b0],12,@Y[$b0] \|\| ROTL @Y[$b3],12,@Y[$b3] \|\| ADD @X[$b0],@X[$a0],@X[$a0] \|\| ADD @X[$b1],@X[$a1],@X[$a1] ADD @X[$b2],@X[$a2],@X[$a2] \|\| ADD @X[$b3],@X[$a3],@X[$a3] \|\| ADD @Y[$b1],@Y[$a1],@Y[$a1] \|\| ADD @Y[$b2],@Y[$a2],@Y[$a2] \|\| XOR @X[$a0],@X[$d0],@X[$d0] \|\| XOR @X[$a1],@X[$d1],@X[$d1] XOR @X[$a2],@X[$d2],@X[$d2] \|\| XOR @X[$a3],@X[$d3],@X[$d3] \|\| ADD @Y[$b0],@Y[$a0],@Y[$a0] \|\| ADD @Y[$b3],@Y[$a3],@Y[$a3] \|\| XOR @Y[$a1],@Y[$d1],@Y[$d1] \|\| XOR @Y[$a2],@Y[$d2],@Y[$d2] XOR @Y[$a0],@Y[$d0],@Y[$d0] \|\| XOR @Y[$a3],@Y[$d3],@Y[$d3] \|\| ROTL @Y[$d1],8,@Y[$d1] \|\| ROTL @Y[$d2],8,@Y[$d2] \|\| SWAP2 @X[$d0],@X[$d0] ; rotate by 16 \|\| SWAP2 @X[$d1],@X[$d1] \|\| SWAP2 @X[$d2],@X[$d2] \|\| SWAP2 @X[$d3],@X[$d3] ROTL @Y[$d0],8,@Y[$d0] \|\| ROTL @Y[$d3],8,@Y[$d3] \|\| ADD @X[$d0],@X[$c2],@X[$c2] \|\| ADD @X[$d1],@X[$c3],@X[$c3] \|\| ADD @X[$d2],@X[$c0],@X[$c0] \|\| ADD @X[$d3],@X[$c1],@X[$c1] \|\| BNOP middle2x2? ; protect from interrupt ADD @Y[$d1],@Y[$c1],@Y[$c1] \|\| ADD @Y[$d2],@Y[$c2],@Y[$c2] \|\| XOR @X[$c2],@X[$b0],@X[$b0] \|\| XOR @X[$c3],@X[$b1],@X[$b1] \|\| XOR @X[$c0],@X[$b2],@X[$b2] \|\| XOR @X[$c1],@X[$b3],@X[$b3] ADD @Y[$d0],@Y[$c0],@Y[$c0] \|\| ADD @Y[$d3],@Y[$c3],@Y[$c3] \|\| XOR @Y[$c1],@Y[$b1],@Y[$b1] \|\| XOR @Y[$c2],@Y[$b2],@Y[$b2] \|\| ROTL @Y[$d1],0,@Y[$d2] ; moved to avoid cross-path stall \|\| ROTL @Y[$d2],0,@Y[$d3] XOR @Y[$c0],@Y[$b0],@Y[$b0] \|\| XOR @Y[$c3],@Y[$b3],@Y[$b3] \|\| MV @Y[$d0],@Y[$d1] \|\| MV @Y[$d3],@Y[$d0] \|\| ROTL @X[$b0],12,@X[$b0] \|\| ROTL @X[$b1],12,@X[$b1] ROTL @Y[$b1],7,@Y[$b0] ; avoided cross-path stall \|\| ROTL @Y[$b2],7,@Y[$b1] ROTL @Y[$b0],7,@Y[$b3] \|\| ROTL @Y[$b3],7,@Y[$b2] middle2x2?: ROTL @X[$b2],12,@X[$b2] \|\| ROTL @X[$b3],12,@X[$b3] \|\| ADD @Y[$b0],@Y[$a0],@Y[$a0] \|\| ADD @Y[$b1],@Y[$a1],@Y[$a1] ADD @Y[$b2],@Y[$a2],@Y[$a2] \|\| ADD @Y[$b3],@Y[$a3],@Y[$a3] \|\| ADD @X[$b0],@X[$a0],@X[$a0] \|\| ADD @X[$b1],@X[$a1],@X[$a1] \|\| XOR @Y[$a0],@Y[$d0],@Y[$d0] \|\| XOR @Y[$a1],@Y[$d1],@Y[$d1] XOR @Y[$a2],@Y[$d2],@Y[$d2] \|\| XOR @Y[$a3],@Y[$d3],@Y[$d3] \|\| ADD @X[$b2],@X[$a2],@X[$a2] \|\| ADD @X[$b3],@X[$a3],@X[$a3] \|\| XOR @X[$a0],@X[$d0],@X[$d0] \|\| XOR @X[$a1],@X[$d1],@X[$d1] XOR @X[$a2],@X[$d2],@X[$d2] \|\| XOR @X[$a3],@X[$d3],@X[$d3] \|\| ROTL @X[$d0],8,@X[$d0] \|\| ROTL @X[$d1],8,@X[$d1] \|\| SWAP2 @Y[$d0],@Y[$d0] ; rotate by 16 \|\| SWAP2 @Y[$d1],@Y[$d1] \|\| SWAP2 @Y[$d2],@Y[$d2] \|\| SWAP2 @Y[$d3],@Y[$d3] ROTL @X[$d2],8,@X[$d2] \|\| ROTL @X[$d3],8,@X[$d3] \|\| ADD @Y[$d0],@Y[$c2],@Y[$c2] \|\| ADD @Y[$d1],@Y[$c3],@Y[$c3] \|\| ADD @Y[$d2],@Y[$c0],@Y[$c0] \|\| ADD @Y[$d3],@Y[$c1],@Y[$c1] \|\| BNOP bottom2x1? ; protect from interrupt ADD @X[$d0],@X[$c2],@X[$c2] \|\| ADD @X[$d1],@X[$c3],@X[$c3] \|\| XOR @Y[$c2],@Y[$b0],@Y[$b0] \|\| XOR @Y[$c3],@Y[$b1],@Y[$b1] \|\| XOR @Y[$c0],@Y[$b2],@Y[$b2] \|\| XOR @Y[$c1],@Y[$b3],@Y[$b3] ADD @X[$d2],@X[$c0],@X[$c0] \|\| ADD @X[$d3],@X[$c1],@X[$c1] \|\| XOR @X[$c2],@X[$b0],@X[$b0] \|\| XOR @X[$c3],@X[$b1],@X[$b1] \|\| ROTL @X[$d0],0,@X[$d3] ; moved to avoid cross-path stall \|\| ROTL @X[$d1],0,@X[$d0] XOR @X[$c0],@X[$b2],@X[$b2] \|\| XOR @X[$c1],@X[$b3],@X[$b3] \|\| MV @X[$d2],@X[$d1] \|\| MV @X[$d3],@X[$d2] \|\| ROTL @Y[$b0],12,@Y[$b0] \|\| ROTL @Y[$b1],12,@Y[$b1] ROTL @X[$b0],7,@X[$b1] ; avoided cross-path stall \|\| ROTL @X[$b1],7,@X[$b2] ROTL @X[$b2],7,@X[$b3] \|\| ROTL @X[$b3],7,@X[$b0] \|\| [B0] SUB B0,1,B0 ; decrement inner loop counter bottom2x1?: ROTL @Y[$b2],12,@Y[$b2] \|\| ROTL @Y[$b3],12,@Y[$b3] \|\| [B0] ADD @X[$b1],@X[$a1],@X[$a1] ; modulo-scheduled \|\| [B0] ADD @X[$b2],@X[$a2],@X[$a2] [B0] ADD @X[$b0],@X[$a0],@X[$a0] \|\| [B0] ADD @X[$b3],@X[$a3],@X[$a3] \|\| ADD @Y[$b0],@Y[$a0],@Y[$a0] \|\| ADD @Y[$b1],@Y[$a1],@Y[$a1] \|\| [B0] XOR @X[$a1],@X[$d1],@X[$d1] \|\| [B0] XOR @X[$a2],@X[$d2],@X[$d2] [B0] XOR @X[$a0],@X[$d0],@X[$d0] \|\| [B0] XOR @X[$a3],@X[$d3],@X[$d3] \|\| ADD @Y[$b2],@Y[$a2],@Y[$a2] \|\| ADD @Y[$b3],@Y[$a3],@Y[$a3] \|\| XOR @Y[$a0],@Y[$d0],@Y[$d0] \|\| XOR @Y[$a1],@Y[$d1],@Y[$d1] XOR @Y[$a2],@Y[$d2],@Y[$d2] \|\| XOR @Y[$a3],@Y[$d3],@Y[$d3] \|\| ROTL @Y[$d0],8,@Y[$d0] \|\| ROTL @Y[$d1],8,@Y[$d1] \|\| [B0] SWAP2 @X[$d1],@X[$d1] ; rotate by 16 \|\| [B0] SWAP2 @X[$d2],@X[$d2] \|\| [B0] SWAP2 @X[$d0],@X[$d0] \|\| [B0] SWAP2 @X[$d3],@X[$d3] ROTL @Y[$d2],8,@Y[$d2] \|\| ROTL @Y[$d3],8,@Y[$d3] \|\| [B0] ADD @X[$d1],@X[$c1],@X[$c1] \|\| [B0] ADD @X[$d2],@X[$c2],@X[$c2] \|\| [B0] ADD @X[$d0],@X[$c0],@X[$c0] \|\| [B0] ADD @X[$d3],@X[$c3],@X[$c3] \|\| [B0] BNOP top2x? ; even protects from interrupt ADD @Y[$d0],@Y[$c2],@Y[$c2] \|\| ADD @Y[$d1],@Y[$c3],@Y[$c3] \|\| [B0] XOR @X[$c1],@X[$b1],@X[$b1] \|\| [B0] XOR @X[$c2],@X[$b2],@X[$b2] \|\| [B0] XOR @X[$c0],@X[$b0],@X[$b0] \|\| [B0] XOR @X[$c3],@X[$b3],@X[$b3] ADD @Y[$d2],@Y[$c0],@Y[$c0] \|\| ADD @Y[$d3],@Y[$c1],@Y[$c1] \|\| XOR @Y[$c2],@Y[$b0],@Y[$b0] \|\| XOR @Y[$c3],@Y[$b1],@Y[$b1] \|\| ROTL @Y[$d0],0,@Y[$d3] ; moved to avoid cross-path stall \|\| ROTL @Y[$d1],0,@Y[$d0] XOR @Y[$c0],@Y[$b2],@Y[$b2] \|\| XOR @Y[$c1],@Y[$b3],@Y[$b3] \|\| MV @Y[$d2],@Y[$d1] \|\| MV @Y[$d3],@Y[$d2] \|\| [B0] ROTL @X[$b1],12,@X[$b1] \|\| [B0] ROTL @X[$b2],12,@X[$b2] ROTL @Y[$b0],7,@Y[$b1] ; avoided cross-path stall \|\| ROTL @Y[$b1],7,@Y[$b2] ROTL @Y[$b2],7,@Y[$b3] \|\| ROTL @Y[$b3],7,@Y[$b0] bottom2x2?: ___ } $code.=<<___; ADD @K2x[0],@X[0],@X[0] ; accumulate key material \|\| ADD @K2x[1],@X[1],@X[1] \|\| ADD @K2x[2],@X[2],@X[2] \|\| ADD @K2x[3],@X[3],@X[3] ADD @K2x[0],@Y[0],@Y[0] \|\| ADD @K2x[1],@Y[1],@Y[1] \|\| ADD @K2x[2],@Y[2],@Y[2] \|\| ADD @K2x[3],@Y[3],@Y[3] \|\| LDNDW ${INP}++[8],@DAT[1]:@DAT[0] ADD @K2x[4],@X[4],@X[4] \|\| ADD @K2x[5],@X[5],@X[5] \|\| ADD @K2x[6],@X[6],@X[6] \|\| ADD @K2x[7],@X[7],@X[7] \|\| LDNDW ${INP}[-7],@DAT[3]:@DAT[2] ADD @K2x[4],@Y[4],@Y[4] \|\| ADD @K2x[5],@Y[5],@Y[5] \|\| ADD @K2x[6],@Y[6],@Y[6] \|\| ADD @K2x[7],@Y[7],@Y[7] \|\| LDNDW ${INP}[-6],@DAT[5]:@DAT[4] ADD @K2x[8],@X[8],@X[8] \|\| ADD @K2x[9],@X[9],@X[9] \|\| ADD @K2x[10],@X[10],@X[10] \|\| ADD @K2x[11],@X[11],@X[11] \|\| LDNDW ${INP}[-5],@DAT[7]:@DAT[6] ADD @K2x[8],@Y[8],@Y[8] \|\| ADD @K2x[9],@Y[9],@Y[9] \|\| ADD @K2x[10],@Y[10],@Y[10] \|\| ADD @K2x[11],@Y[11],@Y[11] \|\| LDNDW ${INP}[-4],@DAT[9]:@DAT[8] ADD @K2x[12],@X[12],@X[12] \|\| ADD @K2x[13],@X[13],@X[13] \|\| ADD @K2x[14],@X[14],@X[14] \|\| ADD @K2x[15],@X[15],@X[15] \|\| LDNDW ${INP}[-3],@DAT[11]:@DAT[10] ADD @K2x[12],@Y[12],@Y[12] \|\| ADD @K2x[13],@Y[13],@Y[13] \|\| ADD @K2x[14],@Y[14],@Y[14] \|\| ADD @K2x[15],@Y[15],@Y[15] \|\| LDNDW ${INP}[-2],@DAT[13]:@DAT[12] ADD 1,@Y[12],@Y[12] ; adjust counter for 2nd block \|\| ADD 2,@K2x[12],@K2x[12] ; increment counter \|\| LDNDW ${INP}[-1],@DAT[15]:@DAT[14] .if .BIG_ENDIAN SWAP2 @X[0],@X[0] \|\| SWAP2 @X[1],@X[1] \|\| SWAP2 @X[2],@X[2] \|\| SWAP2 @X[3],@X[3] SWAP2 @X[4],@X[4] \|\| SWAP2 @X[5],@X[5] \|\| SWAP2 @X[6],@X[6] \|\| SWAP2 @X[7],@X[7] SWAP2 @X[8],@X[8] \|\| SWAP2 @X[9],@X[9] \|\| SWAP4 @X[0],@X[1] \|\| SWAP4 @X[1],@X[0] SWAP2 @X[10],@X[10] \|\| SWAP2 @X[11],@X[11] \|\| SWAP4 @X[2],@X[3] \|\| SWAP4 @X[3],@X[2] SWAP2 @X[12],@X[12] \|\| SWAP2 @X[13],@X[13] \|\| SWAP4 @X[4],@X[5] \|\| SWAP4 @X[5],@X[4] SWAP2 @X[14],@X[14] \|\| SWAP2 @X[15],@X[15] \|\| SWAP4 @X[6],@X[7] \|\| SWAP4 @X[7],@X[6] SWAP4 @X[8],@X[9] \|\| SWAP4 @X[9],@X[8] \|\| SWAP2 @Y[0],@Y[0] \|\| SWAP2 @Y[1],@Y[1] SWAP4 @X[10],@X[11] \|\| SWAP4 @X[11],@X[10] \|\| SWAP2 @Y[2],@Y[2] \|\| SWAP2 @Y[3],@Y[3] SWAP4 @X[12],@X[13] \|\| SWAP4 @X[13],@X[12] \|\| SWAP2 @Y[4],@Y[4] \|\| SWAP2 @Y[5],@Y[5] SWAP4 @X[14],@X[15] \|\| SWAP4 @X[15],@X[14] \|\| SWAP2 @Y[6],@Y[6] \|\| SWAP2 @Y[7],@Y[7] SWAP2 @Y[8],@Y[8] \|\| SWAP2 @Y[9],@Y[9] \|\| SWAP4 @Y[0],@Y[1] \|\| SWAP4 @Y[1],@Y[0] SWAP2 @Y[10],@Y[10] \|\| SWAP2 @Y[11],@Y[11] \|\| SWAP4 @Y[2],@Y[3] \|\| SWAP4 @Y[3],@Y[2] SWAP2 @Y[12],@Y[12] \|\| SWAP2 @Y[13],@Y[13] \|\| SWAP4 @Y[4],@Y[5] \|\| SWAP4 @Y[5],@Y[4] SWAP2 @Y[14],@Y[14] \|\| SWAP2 @Y[15],@Y[15] \|\| SWAP4 @Y[6],@Y[7] \|\| SWAP4 @Y[7],@Y[6] SWAP4 @Y[8],@Y[9] \|\| SWAP4 @Y[9],@Y[8] SWAP4 @Y[10],@Y[11] \|\| SWAP4 @Y[11],@Y[10] SWAP4 @Y[12],@Y[13] \|\| SWAP4 @Y[13],@Y[12] SWAP4 @Y[14],@Y[15] \|\| SWAP4 @Y[15],@Y[14] .endif XOR @DAT[0],@X[0],@X[0] ; xor 1st block \|\| XOR @DAT[3],@X[3],@X[3] \|\| XOR @DAT[2],@X[2],@X[1] \|\| XOR @DAT[1],@X[1],@X[2] \|\| LDNDW ${INP}++[8],@DAT[1]:@DAT[0] XOR @DAT[4],@X[4],@X[4] \|\| XOR @DAT[7],@X[7],@X[7] \|\| LDNDW ${INP}[-7],@DAT[3]:@DAT[2] XOR @DAT[6],@X[6],@X[5] \|\| XOR @DAT[5],@X[5],@X[6] \|\| LDNDW ${INP}[-6],@DAT[5]:@DAT[4] XOR @DAT[8],@X[8],@X[8] \|\| XOR @DAT[11],@X[11],@X[11] \|\| LDNDW ${INP}[-5],@DAT[7]:@DAT[6] XOR @DAT[10],@X[10],@X[9] \|\| XOR @DAT[9],@X[9],@X[10] \|\| LDNDW ${INP}[-4],@DAT[9]:@DAT[8] XOR @DAT[12],@X[12],@X[12] \|\| XOR @DAT[15],@X[15],@X[15] \|\| LDNDW ${INP}[-3],@DAT[11]:@DAT[10] XOR @DAT[14],@X[14],@X[13] \|\| XOR @DAT[13],@X[13],@X[14] \|\| LDNDW ${INP}[-2],@DAT[13]:@DAT[12] [A0] SUB A0,$STEP,A0 ; SUB A0,128,A0 \|\| LDNDW ${INP}[-1],@DAT[15]:@DAT[14] XOR @Y[0],@DAT[0],@DAT[0] ; xor 2nd block \|\| XOR @Y[1],@DAT[1],@DAT[1] \|\| STNDW @X[2]:@X[0],${OUT}++[8] XOR @Y[2],@DAT[2],@DAT[2] \|\| XOR @Y[3],@DAT[3],@DAT[3] \|\| STNDW @X[3]:@X[1],${OUT}[-7] XOR @Y[4],@DAT[4],@DAT[4] \|\| [A0] LDDW FP[-12],@X[2]:@X[0] ; re-load key material from stack \|\| [A0] LDDW SP[2], @X[3]:@X[1] XOR @Y[5],@DAT[5],@DAT[5] \|\| STNDW @X[6]:@X[4],${OUT}[-6] XOR @Y[6],@DAT[6],@DAT[6] \|\| XOR @Y[7],@DAT[7],@DAT[7] \|\| STNDW @X[7]:@X[5],${OUT}[-5] XOR @Y[8],@DAT[8],@DAT[8] \|\| [A0] LDDW FP[-10],@X[6]:@X[4] \|\| [A0] LDDW SP[4], @X[7]:@X[5] XOR @Y[9],@DAT[9],@DAT[9] \|\| STNDW @X[10]:@X[8],${OUT}[-4] XOR @Y[10],@DAT[10],@DAT[10] \|\| XOR @Y[11],@DAT[11],@DAT[11] \|\| STNDW @X[11]:@X[9],${OUT}[-3] XOR @Y[12],@DAT[12],@DAT[12] \|\| [A0] LDDW FP[-8], @X[10]:@X[8] \|\| [A0] LDDW SP[6], @X[11]:@X[9] XOR @Y[13],@DAT[13],@DAT[13] \|\| STNDW @X[14]:@X[12],${OUT}[-2] XOR @Y[14],@DAT[14],@DAT[14] \|\| XOR @Y[15],@DAT[15],@DAT[15] \|\| STNDW @X[15]:@X[13],${OUT}[-1] [A0] MV @K2x[12],@X[12] \|\| [A0] MV @K2x[13],@X[13] \|\| [A0] LDW FP[-62], @X[14] \|\| [A0] LDW SP[82], @X[15] [A0] DMV @X[2],@X[0],@Y[2]:@Y[0] ; duplicate key material \|\| STNDW @DAT[1]:@DAT[0],${OUT}++[8] [A0] DMV @X[3],@X[1],@Y[3]:@Y[1] \|\| STNDW @DAT[3]:@DAT[2],${OUT}[-7] [A0] DMV @X[6],@X[4],@Y[6]:@Y[4] \|\| STNDW @DAT[5]:@DAT[4],${OUT}[-6] \|\| CMPLTU A0,$STEP,A1 ; is remaining length < 2blocks? \|\|[!A0] BNOP epilogue? [A0] DMV @X[7],@X[5],@Y[7]:@Y[5] \|\| STNDW @DAT[7]:@DAT[6],${OUT}[-5] \|\|[!A1] BNOP outer2x? [A0] DMV @X[10],@X[8],@Y[10]:@Y[8] \|\| STNDW @DAT[9]:@DAT[8],${OUT}[-4] [A0] DMV @X[11],@X[9],@Y[11]:@Y[9] \|\| STNDW @DAT[11]:@DAT[10],${OUT}[-3] [A0] DMV @X[14],@X[12],@Y[14]:@Y[12] \|\| STNDW @DAT[13]:@DAT[12],${OUT}[-2] [A0] DMV @X[15],@X[13],@Y[15]:@Y[13] \|\| STNDW @DAT[15]:@DAT[14],${OUT}[-1] ;;===== branch to epilogue? is taken here [A1] MVK 64,$STEP \|\| [A0] MVK 10,B0 ; inner loop counter ;;===== branch to outer2x? is taken here ___ { my ($a0,$a1,$a2,$a3) = (0..3); my ($b0,$b1,$b2,$b3) = (4..7); my ($c0,$c1,$c2,$c3) = (8..11); my ($d0,$d1,$d2,$d3) = (12..15); $code.=<<___; top1x?: ADD @X[$b1],@X[$a1],@X[$a1] \|\| ADD @X[$b2],@X[$a2],@X[$a2] ADD @X[$b0],@X[$a0],@X[$a0] \|\| ADD @X[$b3],@X[$a3],@X[$a3] \|\| XOR @X[$a1],@X[$d1],@X[$d1] \|\| XOR @X[$a2],@X[$d2],@X[$d2] XOR @X[$a0],@X[$d0],@X[$d0] \|\| XOR @X[$a3],@X[$d3],@X[$d3] \|\| SWAP2 @X[$d1],@X[$d1] ; rotate by 16 \|\| SWAP2 @X[$d2],@X[$d2] SWAP2 @X[$d0],@X[$d0] \|\| SWAP2 @X[$d3],@X[$d3] \|\| ADD @X[$d1],@X[$c1],@X[$c1] \|\| ADD @X[$d2],@X[$c2],@X[$c2] ADD @X[$d0],@X[$c0],@X[$c0] \|\| ADD @X[$d3],@X[$c3],@X[$c3] \|\| XOR @X[$c1],@X[$b1],@X[$b1] \|\| XOR @X[$c2],@X[$b2],@X[$b2] XOR @X[$c0],@X[$b0],@X[$b0] \|\| XOR @X[$c3],@X[$b3],@X[$b3] \|\| ROTL @X[$b1],12,@X[$b1] \|\| ROTL @X[$b2],12,@X[$b2] ROTL @X[$b0],12,@X[$b0] \|\| ROTL @X[$b3],12,@X[$b3] ADD @X[$b1],@X[$a1],@X[$a1] \|\| ADD @X[$b2],@X[$a2],@X[$a2] ADD @X[$b0],@X[$a0],@X[$a0] \|\| ADD @X[$b3],@X[$a3],@X[$a3] \|\| XOR @X[$a1],@X[$d1],@X[$d1] \|\| XOR @X[$a2],@X[$d2],@X[$d2] XOR @X[$a0],@X[$d0],@X[$d0] \|\| XOR @X[$a3],@X[$d3],@X[$d3] \|\| ROTL @X[$d1],8,@X[$d1] \|\| ROTL @X[$d2],8,@X[$d2] ROTL @X[$d0],8,@X[$d0] \|\| ROTL @X[$d3],8,@X[$d3] \|\| BNOP middle1x? ; protect from interrupt ADD @X[$d1],@X[$c1],@X[$c1] \|\| ADD @X[$d2],@X[$c2],@X[$c2] ADD @X[$d0],@X[$c0],@X[$c0] \|\| ADD @X[$d3],@X[$c3],@X[$c3] \|\| XOR @X[$c1],@X[$b1],@X[$b1] \|\| XOR @X[$c2],@X[$b2],@X[$b2] \|\| ROTL @X[$d1],0,@X[$d2] ; moved to avoid cross-path stall \|\| ROTL @X[$d2],0,@X[$d3] XOR @X[$c0],@X[$b0],@X[$b0] \|\| XOR @X[$c3],@X[$b3],@X[$b3] \|\| ROTL @X[$d0],0,@X[$d1] \|\| ROTL @X[$d3],0,@X[$d0] ROTL @X[$b1],7,@X[$b0] ; avoided cross-path stall \|\| ROTL @X[$b2],7,@X[$b1] ROTL @X[$b0],7,@X[$b3] \|\| ROTL @X[$b3],7,@X[$b2] middle1x?: ADD @X[$b0],@X[$a0],@X[$a0] \|\| ADD @X[$b1],@X[$a1],@X[$a1] ADD @X[$b2],@X[$a2],@X[$a2] \|\| ADD @X[$b3],@X[$a3],@X[$a3] \|\| XOR @X[$a0],@X[$d0],@X[$d0] \|\| XOR @X[$a1],@X[$d1],@X[$d1] XOR @X[$a2],@X[$d2],@X[$d2] \|\| XOR @X[$a3],@X[$d3],@X[$d3] \|\| SWAP2 @X[$d0],@X[$d0] ; rotate by 16 \|\| SWAP2 @X[$d1],@X[$d1] SWAP2 @X[$d2],@X[$d2] \|\| SWAP2 @X[$d3],@X[$d3] \|\| ADD @X[$d0],@X[$c2],@X[$c2] \|\| ADD @X[$d1],@X[$c3],@X[$c3] ADD @X[$d2],@X[$c0],@X[$c0] \|\| ADD @X[$d3],@X[$c1],@X[$c1] \|\| XOR @X[$c2],@X[$b0],@X[$b0] \|\| XOR @X[$c3],@X[$b1],@X[$b1] XOR @X[$c0],@X[$b2],@X[$b2] \|\| XOR @X[$c1],@X[$b3],@X[$b3] \|\| ROTL @X[$b0],12,@X[$b0] \|\| ROTL @X[$b1],12,@X[$b1] ROTL @X[$b2],12,@X[$b2] \|\| ROTL @X[$b3],12,@X[$b3] ADD @X[$b0],@X[$a0],@X[$a0] \|\| ADD @X[$b1],@X[$a1],@X[$a1] \|\| [B0] SUB B0,1,B0 ; decrement inner loop counter ADD @X[$b2],@X[$a2],@X[$a2] \|\| ADD @X[$b3],@X[$a3],@X[$a3] \|\| XOR @X[$a0],@X[$d0],@X[$d0] \|\| XOR @X[$a1],@X[$d1],@X[$d1] XOR @X[$a2],@X[$d2],@X[$d2] \|\| XOR @X[$a3],@X[$d3],@X[$d3] \|\| ROTL @X[$d0],8,@X[$d0] \|\| ROTL @X[$d1],8,@X[$d1] ROTL @X[$d2],8,@X[$d2] \|\| ROTL @X[$d3],8,@X[$d3] \|\| [B0] BNOP top1x? ; even protects from interrupt ADD @X[$d0],@X[$c2],@X[$c2] \|\| ADD @X[$d1],@X[$c3],@X[$c3] ADD @X[$d2],@X[$c0],@X[$c0] \|\| ADD @X[$d3],@X[$c1],@X[$c1] \|\| XOR @X[$c2],@X[$b0],@X[$b0] \|\| XOR @X[$c3],@X[$b1],@X[$b1] \|\| ROTL @X[$d0],0,@X[$d3] ; moved to avoid cross-path stall \|\| ROTL @X[$d1],0,@X[$d0] XOR @X[$c0],@X[$b2],@X[$b2] \|\| XOR @X[$c1],@X[$b3],@X[$b3] \|\| ROTL @X[$d2],0,@X[$d1] \|\| ROTL @X[$d3],0,@X[$d2] ROTL @X[$b0],7,@X[$b1] ; avoided cross-path stall \|\| ROTL @X[$b1],7,@X[$b2] ROTL @X[$b2],7,@X[$b3] \|\| ROTL @X[$b3],7,@X[$b0] \|\|[!B0] CMPLTU A0,$STEP,A1 ; less than 64 bytes left? bottom1x?: ___ } $code.=<<___; ADD @Y[0],@X[0],@X[0] ; accumulate key material \|\| ADD @Y[1],@X[1],@X[1] \|\| ADD @Y[2],@X[2],@X[2] \|\| ADD @Y[3],@X[3],@X[3] \|\|[!A1] LDNDW ${INP}++[8],@DAT[1]:@DAT[0] \|\| [A1] BNOP tail? ADD @Y[4],@X[4],@X[4] \|\| ADD @Y[5],@X[5],@X[5] \|\| ADD @Y[6],@X[6],@X[6] \|\| ADD @Y[7],@X[7],@X[7] \|\|[!A1] LDNDW ${INP}[-7],@DAT[3]:@DAT[2] ADD @Y[8],@X[8],@X[8] \|\| ADD @Y[9],@X[9],@X[9] \|\| ADD @Y[10],@X[10],@X[10] \|\| ADD @Y[11],@X[11],@X[11] \|\|[!A1] LDNDW ${INP}[-6],@DAT[5]:@DAT[4] ADD @Y[12],@X[12],@X[12] \|\| ADD @Y[13],@X[13],@X[13] \|\| ADD @Y[14],@X[14],@X[14] \|\| ADD @Y[15],@X[15],@X[15] \|\|[!A1] LDNDW ${INP}[-5],@DAT[7]:@DAT[6] [!A1] LDNDW ${INP}[-4],@DAT[9]:@DAT[8] [!A1] LDNDW ${INP}[-3],@DAT[11]:@DAT[10] LDNDW ${INP}[-2],@DAT[13]:@DAT[12] LDNDW ${INP}[-1],@DAT[15]:@DAT[14] .if .BIG_ENDIAN SWAP2 @X[0],@X[0] \|\| SWAP2 @X[1],@X[1] \|\| SWAP2 @X[2],@X[2] \|\| SWAP2 @X[3],@X[3] SWAP2 @X[4],@X[4] \|\| SWAP2 @X[5],@X[5] \|\| SWAP2 @X[6],@X[6] \|\| SWAP2 @X[7],@X[7] SWAP2 @X[8],@X[8] \|\| SWAP2 @X[9],@X[9] \|\| SWAP4 @X[0],@X[1] \|\| SWAP4 @X[1],@X[0] SWAP2 @X[10],@X[10] \|\| SWAP2 @X[11],@X[11] \|\| SWAP4 @X[2],@X[3] \|\| SWAP4 @X[3],@X[2] SWAP2 @X[12],@X[12] \|\| SWAP2 @X[13],@X[13] \|\| SWAP4 @X[4],@X[5] \|\| SWAP4 @X[5],@X[4] SWAP2 @X[14],@X[14] \|\| SWAP2 @X[15],@X[15] \|\| SWAP4 @X[6],@X[7] \|\| SWAP4 @X[7],@X[6] SWAP4 @X[8],@X[9] \|\| SWAP4 @X[9],@X[8] SWAP4 @X[10],@X[11] \|\| SWAP4 @X[11],@X[10] SWAP4 @X[12],@X[13] \|\| SWAP4 @X[13],@X[12] SWAP4 @X[14],@X[15] \|\| SWAP4 @X[15],@X[14] .else NOP 1 .endif XOR @X[0],@DAT[0],@DAT[0] ; xor with input \|\| XOR @X[1],@DAT[1],@DAT[1] \|\| XOR @X[2],@DAT[2],@DAT[2] \|\| XOR @X[3],@DAT[3],@DAT[3] \|\| [A0] SUB A0,$STEP,A0 ; SUB A0,64,A0 XOR @X[4],@DAT[4],@DAT[4] \|\| XOR @X[5],@DAT[5],@DAT[5] \|\| XOR @X[6],@DAT[6],@DAT[6] \|\| XOR @X[7],@DAT[7],@DAT[7] \|\| STNDW @DAT[1]:@DAT[0],${OUT}++[8] XOR @X[8],@DAT[8],@DAT[8] \|\| XOR @X[9],@DAT[9],@DAT[9] \|\| XOR @X[10],@DAT[10],@DAT[10] \|\| XOR @X[11],@DAT[11],@DAT[11] \|\| STNDW @DAT[3]:@DAT[2],${OUT}[-7] XOR @X[12],@DAT[12],@DAT[12] \|\| XOR @X[13],@DAT[13],@DAT[13] \|\| XOR @X[14],@DAT[14],@DAT[14] \|\| XOR @X[15],@DAT[15],@DAT[15] \|\| STNDW @DAT[5]:@DAT[4],${OUT}[-6] \|\| [A0] BNOP top1x? [A0] DMV @Y[2],@Y[0],@X[2]:@X[0] ; duplicate key material \|\| [A0] DMV @Y[3],@Y[1],@X[3]:@X[1] \|\| STNDW @DAT[7]:@DAT[6],${OUT}[-5] [A0] DMV @Y[6],@Y[4],@X[6]:@X[4] \|\| [A0] DMV @Y[7],@Y[5],@X[7]:@X[5] \|\| STNDW @DAT[9]:@DAT[8],${OUT}[-4] [A0] DMV @Y[10],@Y[8],@X[10]:@X[8] \|\| [A0] DMV @Y[11],@Y[9],@X[11]:@X[9] \|\| [A0] ADD 1,@Y[12],@Y[12] ; increment counter \|\| STNDW @DAT[11]:@DAT[10],${OUT}[-3] [A0] DMV @Y[14],@Y[12],@X[14]:@X[12] \|\| [A0] DMV @Y[15],@Y[13],@X[15]:@X[13] \|\| STNDW @DAT[13]:@DAT[12],${OUT}[-2] [A0] MVK 10,B0 ; inner loop counter \|\| STNDW @DAT[15]:@DAT[14],${OUT}[-1] ;;===== branch to top1x? is taken here epilogue?: LDDW FP[-4],A11:A10 ; ABI says so LDDW FP[-3],A13:A12 \|\| LDDW SP[3+8],B11:B10 LDDW SP[4+8],B13:B12 \|\| BNOP RA LDW ++SP(40+64),FP ; restore frame pointer NOP 4 tail?: LDBU ${INP}++[1],B24 ; load byte by byte \|\| SUB A0,1,A0 \|\| SUB A0,1,B1 [!B1] BNOP epilogue? ; interrupts are disabled for whole time \|\| [A0] LDBU ${INP}++[1],B24 \|\| [A0] SUB A0,1,A0 \|\| SUB B1,1,B1 [!B1] BNOP epilogue? \|\| [A0] LDBU ${INP}++[1],B24 \|\| [A0] SUB A0,1,A0 \|\| SUB B1,1,B1 [!B1] BNOP epilogue? \|\| ROTL @X[0],0,A24 \|\| [A0] LDBU ${INP}++[1],B24 \|\| [A0] SUB A0,1,A0 \|\| SUB B1,1,B1 [!B1] BNOP epilogue? \|\| ROTL @X[0],24,A24 \|\| [A0] LDBU ${INP}++[1],A24 \|\| [A0] SUB A0,1,A0 \|\| SUB B1,1,B1 [!B1] BNOP epilogue? \|\| ROTL @X[0],16,A24 \|\| [A0] LDBU ${INP}++[1],A24 \|\| [A0] SUB A0,1,A0 \|\| SUB B1,1,B1 \|\| XOR A24,B24,B25 STB B25,${OUT}++[1] ; store byte by byte \|\|[!B1] BNOP epilogue? \|\| ROTL @X[0],8,A24 \|\| [A0] LDBU ${INP}++[1],A24 \|\| [A0] SUB A0,1,A0 \|\| SUB B1,1,B1 \|\| XOR A24,B24,B25 STB B25,${OUT}++[1] ___ sub TAIL_STEP { my $Xi= shift; my $T = ($Xi=~/^B/?"B24":"A24"); # match @X[i] to avoid cross path my $D = $T; $D=~tr/AB/BA/; my $O = $D; $O=~s/24/25/; $code.=<<___; \|\|[!B1] BNOP epilogue? \|\| ROTL $Xi,0,$T \|\| [A0] LDBU ${INP}++[1],$D \|\| [A0] SUB A0,1,A0 \|\| SUB B1,1,B1 \|\| XOR A24,B24,$O STB $O,${OUT}++[1] \|\|[!B1] BNOP epilogue? \|\| ROTL $Xi,24,$T \|\| [A0] LDBU ${INP}++[1],$T \|\| [A0] SUB A0,1,A0 \|\| SUB B1,1,B1 \|\| XOR A24,B24,$O STB $O,${OUT}++[1] \|\|[!B1] BNOP epilogue? \|\| ROTL $Xi,16,$T \|\| [A0] LDBU ${INP}++[1],$T \|\| [A0] SUB A0,1,A0 \|\| SUB B1,1,B1 \|\| XOR A24,B24,$O STB $O,${OUT}++[1] \|\|[!B1] BNOP epilogue? \|\| ROTL $Xi,8,$T \|\| [A0] LDBU ${INP}++[1],$T \|\| [A0] SUB A0,1,A0 \|\| SUB B1,1,B1 \|\| XOR A24,B24,$O STB $O,${OUT}++[1] ___ } foreach (1..14) { TAIL_STEP(@X[$_]); } $code.=<<___; \|\|[!B1] BNOP epilogue? \|\| ROTL @X[15],0,B24 \|\| XOR A24,B24,A25 STB A25,${OUT}++[1] \|\| ROTL @X[15],24,B24 \|\| XOR A24,B24,A25 STB A25,${OUT}++[1] \|\| ROTL @X[15],16,B24 \|\| XOR A24,B24,A25 STB A25,${OUT}++[1] \|\| XOR A24,B24,A25 STB A25,${OUT}++[1] \|\| XOR A24,B24,B25 STB B25,*${OUT}++[1] .endasmfunc .sect .const .cstring "ChaCha20 for C64x+, CRYPTOGAMS by <appro\@openssl.org>" .align 4 ___ print $code; close STDOUT or die "error closing STDOUT: $!";	{ "language": "Assembly" }
/********************************************************************/ / Copyright 2009, 2010 The University of Texas at Austin. / / All rights reserved. / / / / Redistribution and use in source and binary forms, with or / / without modification, are permitted provided that the following / / conditions are met: / / / / 1. Redistributions of source code must retain the above / / copyright notice, this list of conditions and the following / / disclaimer. / / / / 2. Redistributions in binary form must reproduce the above / / copyright notice, this list of conditions and the following / / disclaimer in the documentation and/or other materials / / provided with the distribution. / / / / THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT / / AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, / / INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF / / MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE / / DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT / / AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, / / INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES / / (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE / / GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR / / BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF / / LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT / / (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT / / OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE / / POSSIBILITY OF SUCH DAMAGE. / / / / The views and conclusions contained in the software and / / documentation are those of the authors and should not be / / interpreted as representing official policies, either expressed / / or implied, of The University of Texas at Austin. / /*******************************************************************/ #define ASSEMBLER #include "common.h" #include "version.h" #define PREFETCHSIZE 88 #define N $16 #define X $17 #define INCX $18 #define I $19 #define s0 $f0 #define s1 $f1 #define s2 $f10 #define s3 $f11 #define a0 $f12 #define a1 $f13 #define a2 $f14 #define a3 $f15 #define a4 $f16 #define a5 $f17 #define a6 $f18 #define a7 $f19 #define t0 $f20 #define t1 $f21 #define t2 $f22 #define t3 $f23 PROLOGUE PROFCODE fclr s0 unop fclr t0 addq INCX, INCX, INCX fclr s1 unop fclr t1 ble N, $L999 fclr s2 sra N, 2, I fclr s3 ble I, $L15 LD a0, 0 SIZE(X) fclr t2 LD a1, 1 * SIZE(X) SXADDQ INCX, X, X LD a2, 0 * SIZE(X) fclr t3 LD a3, 1 * SIZE(X) SXADDQ INCX, X, X LD a4, 0 * SIZE(X) LD a5, 1 * SIZE(X) SXADDQ INCX, X, X lda I, -1(I) ble I, $L13 .align 4 $L12: ADD s0, t0, s0 ldl $31, PREFETCHSIZE * SIZE(X) fmov a0, t0 lda I, -1(I) ADD s1, t1, s1 LD a6, 0 * SIZE(X) fmov a1, t1 unop ADD s2, t2, s2 LD a7, 1 * SIZE(X) fmov a2, t2 SXADDQ INCX, X, X ADD s3, t3, s3 LD a0, 0 * SIZE(X) fmov a3, t3 unop ADD s0, t0, s0 LD a1, 1 * SIZE(X) fmov a4, t0 SXADDQ INCX, X, X ADD s1, t1, s1 LD a2, 0 * SIZE(X) fmov a5, t1 unop ADD s2, t2, s2 LD a3, 1 * SIZE(X) fmov a6, t2 SXADDQ INCX, X, X ADD s3, t3, s3 LD a4, 0 * SIZE(X) fmov a7, t3 unop LD a5, 1 * SIZE(X) unop SXADDQ INCX, X, X bne I, $L12 .align 4 $L13: ADD s0, t0, s0 LD a6, 0 * SIZE(X) fmov a0, t0 ADD s1, t1, s1 LD a7, 1 * SIZE(X) fmov a1, t1 SXADDQ INCX, X, X ADD s2, t2, s2 fmov a2, t2 ADD s3, t3, s3 fmov a3, t3 ADD s0, t0, s0 fmov a4, t0 ADD s1, t1, s1 fmov a5, t1 ADD s2, t2, s2 fmov a6, t2 ADD s3, t3, s3 fmov a7, t3 ADD s2, t2, s2 ADD s3, t3, s3 .align 4 $L15: ADD s0, s2, s0 and N, 3, I ADD s1, s3, s1 ble I, $L999 .align 4 $L17: ADD s0, t0, s0 LD a0, 0 * SIZE(X) fmov a0, t0 lda I, -1(I) ADD s1, t1, s1 LD a1, 1 * SIZE(X) fmov a1, t1 SXADDQ INCX, X, X bne I, $L17 .align 4 $L999: ADD s0, t0, s0 ADD s1, t1, s1 ADD s0, s1, s0 ret EPILOGUE	{ "language": "Assembly" }
; RUN: llc < %s -march=x86-64 \| grep call ; PR4688 ; Return types can be empty structs, which can be awkward. target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-unknown-linux-gnu" define void @_ZN15QtSharedPointer22internalSafetyCheckAddEPVKv(i8* %ptr) { entry: %0 = call { } @_ZNK5QHashIPv15QHashDummyValueE5valueERKS0_(i8 undef) ; <{ }> [#uses=0] ret void } declare hidden { } @_ZNK5QHashIPv15QHashDummyValueE5valueERKS0_(i8 nocapture) nounwind	{ "language": "Assembly" }
// RUN: %clang_cc1 -E -frewrite-includes -I %S/Inputs %s \| FileCheck %s --check-prefix=GNU // RUN: %clang_cc1 -E -frewrite-includes -fuse-line-directives -I %S/Inputs %s \| FileCheck %s --check-prefix=LINE #include "test.h" int f() { return x; } #include "empty.h" // GNU: {{^}}# 1 "{{.}}rewrite-includes-line-markers.c" // GNU: {{^}}#include "test.h" // GNU: {{^}}# 1 "{{.}}test.h" // GNU: {{^}}#include "test2.h" // GNU: {{^}}# 1 "{{.}}test2.h" // GNU: {{^}}int x; // GNU: {{^}}# 4 "{{.}}rewrite-includes-line-markers.c" 2 // GNU: {{^}}int f() { return x; } // GNU: {{^}} // GNU: {{^}}# 1 "{{.}}empty.h" 1 // GNU: {{^}}# 7 "{{.}}rewrite-includes-line-markers.c" 2 // LINE: {{^}}#line 1 "{{.}}rewrite-includes-line-markers.c" // LINE: {{^}}#include "test.h" // LINE: {{^}}#line 1 "{{.}}test.h" // LINE: {{^}}#include "test2.h" // LINE: {{^}}#line 1 "{{.}}test2.h" // LINE: {{^}}int x; // LINE: {{^}}#line 4 "{{.}}rewrite-includes-line-markers.c" // LINE: {{^}}int f() { return x; } // LINE: {{^}} // LINE: {{^}}#line 1 "{{.}}empty.h" // LINE: {{^}}#line 7 "{{.}}rewrite-includes-line-markers.c"	{ "language": "Assembly" }
--- gcc/config/avr/avr.c.old 2008-11-04 14:14:27.405669400 -0700 +++ gcc/config/avr/avr.c 2008-11-04 14:14:55.772086800 -0700 @@ -283,6 +283,7 @@ static const struct mcu_type_s avr_mcu_t { "atmega32m1", ARCH_AVR5, "__AVR_ATmega32M1__" }, { "atmega32c1", ARCH_AVR5, "__AVR_ATmega32C1__" }, { "atmega32u4", ARCH_AVR5, "__AVR_ATmega32U4__" }, + { "atmega32u6", ARCH_AVR5, "__AVR_ATmega32U6__" }, { "at90usb646", ARCH_AVR5, "__AVR_AT90USB646__" }, { "at90usb647", ARCH_AVR5, "__AVR_AT90USB647__" }, { "at94k", ARCH_AVR5, "__AVR_AT94K__" }, --- gcc/config/avr/avr.h.old 2008-11-04 14:15:07.629280600 -0700 +++ gcc/config/avr/avr.h 2008-11-04 14:16:11.692586600 -0700 @@ -871,7 +871,7 @@ mmcu=:-mmcu=%}" mmcu=at90pwm316\|\ mmcu=atmega32c1\|\ mmcu=atmega32m1\|\ - mmcu=atmega32u4\|\ + mmcu=atmega32u\|\ mmcu=at90usb64\|\ mmcu=at90usb128\|\ mmcu=at94k: -m avr5}\ @@ -908,7 +908,7 @@ mmcu=:-mmcu=%}" mmcu=at90pwm\|\ mmcu=atmega32c1\|\ mmcu=atmega32m1\|\ - mmcu=atmega32u4\|\ + mmcu=atmega32u\|\ mmcu=at90usb: -Tdata 0x800100}\ %{mmcu=atmega640\|\ mmcu=atmega1280\|\ --- gcc/config/avr/t-avr.old 2008-11-04 14:17:13.610006800 -0700 +++ gcc/config/avr/t-avr 2008-11-04 14:17:24.793674400 -0700 @@ -118,6 +118,7 @@ MULTILIB_MATCHES = \ mmcu?avr5=mmcu?atmega32c1 \ mmcu?avr5=mmcu?atmega32m1 \ mmcu?avr5=mmcu?atmega32u4 \ + mmcu?avr5=mmcu?atmega32u6 \ mmcu?avr5=mmcu?at90usb646 \ mmcu?avr5=mmcu?at90usb647 \ mmcu?avr5=mmcu?at94k \	{ "language": "Assembly" }
// Copyright 2009 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build !gccgo #include "textflag.h" // // System calls for 386, Linux // // See ../runtime/sys_linux_386.s for the reason why we always use int 0x80 // instead of the glibc-specific "CALL 0x10(GS)". #define INVOKE_SYSCALL INT $0x80 // Just jump to package syscall's implementation for all these functions. // The runtime may know about them. TEXT ·Syscall(SB),NOSPLIT,$0-28 JMP syscall·Syscall(SB) TEXT ·Syscall6(SB),NOSPLIT,$0-40 JMP syscall·Syscall6(SB) TEXT ·SyscallNoError(SB),NOSPLIT,$0-24 CALL runtime·entersyscall(SB) MOVL trap+0(FP), AX // syscall entry MOVL a1+4(FP), BX MOVL a2+8(FP), CX MOVL a3+12(FP), DX MOVL $0, SI MOVL $0, DI INVOKE_SYSCALL MOVL AX, r1+16(FP) MOVL DX, r2+20(FP) CALL runtime·exitsyscall(SB) RET TEXT ·RawSyscall(SB),NOSPLIT,$0-28 JMP syscall·RawSyscall(SB) TEXT ·RawSyscall6(SB),NOSPLIT,$0-40 JMP syscall·RawSyscall6(SB) TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-24 MOVL trap+0(FP), AX // syscall entry MOVL a1+4(FP), BX MOVL a2+8(FP), CX MOVL a3+12(FP), DX MOVL $0, SI MOVL $0, DI INVOKE_SYSCALL MOVL AX, r1+16(FP) MOVL DX, r2+20(FP) RET TEXT ·socketcall(SB),NOSPLIT,$0-36 JMP syscall·socketcall(SB) TEXT ·rawsocketcall(SB),NOSPLIT,$0-36 JMP syscall·rawsocketcall(SB) TEXT ·seek(SB),NOSPLIT,$0-28 JMP syscall·seek(SB)	{ "language": "Assembly" }
1d0 < line 0 2a2 > line between 1 and 2 4,5c4,5 < line 3 < line 4 --- > adjusted line 3 > adjusted line 4 7,8d6 < line 6 < line 7	{ "language": "Assembly" }
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// 0.315809 0x3ea1b1c5 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.303457 0x3e9b5ec4 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.291207 0x3e95191a // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.279054 0x3e8ee025 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.266993 0x3e88b343 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.255019 0x3e8291d9 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.243128 0x3e78f6a0 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.231316 0x3e6cde27 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.219578 0x3e60d927 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.207911 0x3e54e687 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.196309 0x3e490531 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.184769 0x3e3d3419 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.173287 0x3e317235 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.161860 0x3e25be82 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.150482 0x3e1a1801 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.139151 0x3e0e7db7 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.127864 0x3e02eeae // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.116615 0x3deed3e1 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.105402 0x3dd7dd22 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.094222 0x3dc0f742 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.083070 0x3daa206d // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.071943 0x3d9356d3 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.060838 0x3d793152 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.049752 0x3d4bc84b // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.038680 0x3d1e6f08 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.027620 0x3ce24403 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.016569 0x3c87bb6d // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // 0.005522 0x3bb4f540 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.005522 0xbbb4f540 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.016569 0xbc87bb6d // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.027620 0xbce24403 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.038680 0xbd1e6f08 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.049752 0xbd4bc84b // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.060838 0xbd793152 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.071943 0xbd9356d3 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.083070 0xbdaa206d // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.094222 0xbdc0f742 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.105402 0xbdd7dd22 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.116615 0xbdeed3e1 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.127864 0xbe02eeae // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.139151 0xbe0e7db7 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.150482 0xbe1a1801 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.161860 0xbe25be82 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.173287 0xbe317235 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.184769 0xbe3d3419 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.196309 0xbe490531 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.207911 0xbe54e687 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.219578 0xbe60d927 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.231316 0xbe6cde27 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.243128 0xbe78f6a0 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.255019 0xbe8291d9 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.266993 0xbe88b343 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.279054 0xbe8ee025 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.291207 0xbe95191a // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.303457 0xbe9b5ec4 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.315809 0xbea1b1c5 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.328268 0xbea812c7 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.340839 0xbeae8279 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.353527 0xbeb5018e // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.366339 0xbebb90bf // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.379279 0xbec230ce // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.392353 0xbec8e27e // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.405568 0xbecfa69e // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.418930 0xbed67e02 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.432446 0xbedd6986 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.446122 0xbee46a0e // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.459965 0xbeeb8088 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.473983 0xbef2ade9 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.488184 0xbef9f332 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.502574 0xbf00a8b6 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.517164 0xbf0464d8 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.531960 0xbf082e8f // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.546973 0xbf0c0671 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.562212 0xbf0fed1d // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.577686 0xbf13e337 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.593405 0xbf17e96b // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.609382 0xbf1c006f // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.625625 0xbf2028fe // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.642149 0xbf2463df // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.658964 0xbf28b1e2 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.676085 0xbf2d13e1 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.693523 0xbf318ac2 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.711295 0xbf361774 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.729415 0xbf3abaf8 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.747899 0xbf3f7657 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.766764 0xbf444aae // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.786028 0xbf493924 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.805709 0xbf4e42f6 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.825828 0xbf53696f // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.846404 0xbf58adf2 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.867461 0xbf5e11f2 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.889023 0xbf6396fb // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.911113 0xbf693eb3 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.933759 0xbf6f0ad8 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.956990 0xbf74fd45 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -0.980834 0xbf7b17f5 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.005325 0xbf80ae81 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.030497 0xbf83e757 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.056387 0xbf8737b0 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.083033 0xbf8aa0d5 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.110478 0xbf8e2427 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.138767 0xbf91c321 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.167949 0xbf957f59 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.198075 0xbf995a85 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.229202 0xbf9d567b // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.261390 0xbfa17537 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.294704 0xbfa5b8df // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.329216 0xbfaa23c3 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.365003 0xbfaeb868 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.402146 0xbfb37988 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.440738 0xbfb86a1c // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.480877 0xbfbd8d5e // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.522670 0xbfc2e6d7 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.566235 0xbfc87a64 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.611702 0xbfce4c3f // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.659212 0xbfd4610f // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.708922 0xbfdabdf3 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.761004 0xbfe16891 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.815648 0xbfe8672a // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.873068 0xbfefc0ad // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.933497 0xbff77cd2 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.997199 0xbfffa435 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.064467 0xc004203c // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.135633 0xc008ae38 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.211069 0xc00d8226 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.291194 0xc012a2ec // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.376487 0xc018185f // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.467494 0xc01deb6c // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.564838 0xc024264f // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.669238 0xc02ad4cd // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.781525 0xc0320482 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.902666 0xc039c547 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -3.033791 0xc04229a3 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -3.176234 0xc04b476c // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -3.331574 0xc0553884 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -3.501700 0xc0601bdc // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -3.688888 0xc06c16bd // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -3.895905 0xc0795680 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -4.126151 0xc084096e // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -4.383851 0xc08c4882 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -4.674320 0xc0959408 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -5.004339 0xc0a0238b // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -5.382697 0xc0ac3f0d // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -5.820996 0xc0ba4599 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -6.334875 0xc0cab74c // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -6.945929 0xc0de450d // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -7.684846 0xc0f5ea42 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -8.596754 0xc1098c4e // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -9.750852 0xc11c037e // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -11.258921 0xc134248a // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -13.314036 0xc155064a // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -16.280896 0xc1823f46 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -20.940998 0xc1a7872a // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -29.326235 0xc1ea9c21 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -48.886876 0xc2438c29 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -146.675355 0xc312ace4	{ "language": "Assembly" }
/* Copyright (c) 2011 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rl78-sys.h" .global _isatty .weak _isatty _isatty: RET(_isatty,1)	{ "language": "Assembly" }
%include print_eax.vm start: mov eax, 42 call print_eax mov eax, 23 call print_eax	{ "language": "Assembly" }
// Copyright 2009 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build !gccgo #include "textflag.h" // // System calls for AMD64, Linux // // Just jump to package syscall's implementation for all these functions. // The runtime may know about them. TEXT ·Syscall(SB),NOSPLIT,$0-56 JMP syscall·Syscall(SB) TEXT ·Syscall6(SB),NOSPLIT,$0-80 JMP syscall·Syscall6(SB) TEXT ·SyscallNoError(SB),NOSPLIT,$0-48 CALL runtime·entersyscall(SB) MOVQ a1+8(FP), DI MOVQ a2+16(FP), SI MOVQ a3+24(FP), DX MOVQ $0, R10 MOVQ $0, R8 MOVQ $0, R9 MOVQ trap+0(FP), AX // syscall entry SYSCALL MOVQ AX, r1+32(FP) MOVQ DX, r2+40(FP) CALL runtime·exitsyscall(SB) RET TEXT ·RawSyscall(SB),NOSPLIT,$0-56 JMP syscall·RawSyscall(SB) TEXT ·RawSyscall6(SB),NOSPLIT,$0-80 JMP syscall·RawSyscall6(SB) TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-48 MOVQ a1+8(FP), DI MOVQ a2+16(FP), SI MOVQ a3+24(FP), DX MOVQ $0, R10 MOVQ $0, R8 MOVQ $0, R9 MOVQ trap+0(FP), AX // syscall entry SYSCALL MOVQ AX, r1+32(FP) MOVQ DX, r2+40(FP) RET TEXT ·gettimeofday(SB),NOSPLIT,$0-16 JMP syscall·gettimeofday(SB)	{ "language": "Assembly" }
; RUN: opt < %s -argpromotion -S \| FileCheck %s ; RUN: opt < %s -passes=argpromotion -S \| FileCheck %s ; CHECK: load i32, i32* %A target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" define internal i32 @callee(i1 %C, i32* %P) { br i1 %C, label %T, label %F T: ; preds = %0 ret i32 17 F: ; preds = %0 %X = load i32, i32* %P ; <i32> [#uses=1] ret i32 %X } define i32 @foo() { %A = alloca i32 ; <i32> [#uses=2] store i32 17, i32 %A %X = call i32 @callee( i1 false, i32* %A ) ; <i32> [#uses=1] ret i32 %X }	{ "language": "Assembly" }
# CS_ARCH_ARM, CS_MODE_ARM, None 0xd2,0x10,0xb0,0xe0 = ldrsbt r1, [r0], r2 0xd4,0x10,0xf0,0xe0 = ldrsbt r1, [r0], #4 0xf2,0x10,0xb0,0xe0 = ldrsht r1, [r0], r2 0xf4,0x10,0xf0,0xe0 = ldrsht r1, [r0], #4 0xb2,0x10,0xb0,0xe0 = ldrht r1, [r0], r2 0xb4,0x10,0xf0,0xe0 = ldrht r1, [r0], #4 0xb2,0x10,0xa0,0xe0 = strht r1, [r0], r2 0xb4,0x10,0xe0,0xe0 = strht r1, [r0], #4	{ "language": "Assembly" }
; RUN: %lli %s > /dev/null define i32 @main() { entry: br label %endif then: ; No predecessors! br label %endif endif: ; preds = %then, %entry %x = phi i32 [ 4, %entry ], [ 27, %then ] ; <i32> [#uses=0] %result = phi i32 [ 32, %then ], [ 0, %entry ] ; <i32> [#uses=0] ret i32 0 }	{ "language": "Assembly" }
// go run mkasm_darwin.go arm64 // Code generated by the command above; DO NOT EDIT. // +build go1.12 #include "textflag.h" TEXT ·libc_getgroups_trampoline(SB),NOSPLIT,$0-0 JMP libc_getgroups(SB) TEXT ·libc_setgroups_trampoline(SB),NOSPLIT,$0-0 JMP libc_setgroups(SB) TEXT ·libc_wait4_trampoline(SB),NOSPLIT,$0-0 JMP libc_wait4(SB) TEXT ·libc_accept_trampoline(SB),NOSPLIT,$0-0 JMP libc_accept(SB) TEXT ·libc_bind_trampoline(SB),NOSPLIT,$0-0 JMP libc_bind(SB) TEXT ·libc_connect_trampoline(SB),NOSPLIT,$0-0 JMP libc_connect(SB) TEXT ·libc_socket_trampoline(SB),NOSPLIT,$0-0 JMP libc_socket(SB) TEXT ·libc_getsockopt_trampoline(SB),NOSPLIT,$0-0 JMP libc_getsockopt(SB) TEXT ·libc_setsockopt_trampoline(SB),NOSPLIT,$0-0 JMP libc_setsockopt(SB) TEXT ·libc_getpeername_trampoline(SB),NOSPLIT,$0-0 JMP libc_getpeername(SB) TEXT ·libc_getsockname_trampoline(SB),NOSPLIT,$0-0 JMP libc_getsockname(SB) TEXT ·libc_shutdown_trampoline(SB),NOSPLIT,$0-0 JMP libc_shutdown(SB) TEXT ·libc_socketpair_trampoline(SB),NOSPLIT,$0-0 JMP libc_socketpair(SB) TEXT ·libc_recvfrom_trampoline(SB),NOSPLIT,$0-0 JMP libc_recvfrom(SB) TEXT ·libc_sendto_trampoline(SB),NOSPLIT,$0-0 JMP libc_sendto(SB) TEXT ·libc_recvmsg_trampoline(SB),NOSPLIT,$0-0 JMP libc_recvmsg(SB) TEXT ·libc_sendmsg_trampoline(SB),NOSPLIT,$0-0 JMP libc_sendmsg(SB) TEXT ·libc_kevent_trampoline(SB),NOSPLIT,$0-0 JMP libc_kevent(SB) TEXT ·libc_utimes_trampoline(SB),NOSPLIT,$0-0 JMP libc_utimes(SB) TEXT ·libc_futimes_trampoline(SB),NOSPLIT,$0-0 JMP libc_futimes(SB) TEXT ·libc_poll_trampoline(SB),NOSPLIT,$0-0 JMP libc_poll(SB) TEXT ·libc_madvise_trampoline(SB),NOSPLIT,$0-0 JMP libc_madvise(SB) TEXT ·libc_mlock_trampoline(SB),NOSPLIT,$0-0 JMP libc_mlock(SB) TEXT ·libc_mlockall_trampoline(SB),NOSPLIT,$0-0 JMP libc_mlockall(SB) TEXT ·libc_mprotect_trampoline(SB),NOSPLIT,$0-0 JMP libc_mprotect(SB) TEXT ·libc_msync_trampoline(SB),NOSPLIT,$0-0 JMP libc_msync(SB) TEXT ·libc_munlock_trampoline(SB),NOSPLIT,$0-0 JMP libc_munlock(SB) TEXT ·libc_munlockall_trampoline(SB),NOSPLIT,$0-0 JMP libc_munlockall(SB) TEXT ·libc_getattrlist_trampoline(SB),NOSPLIT,$0-0 JMP libc_getattrlist(SB) TEXT ·libc_pipe_trampoline(SB),NOSPLIT,$0-0 JMP libc_pipe(SB) TEXT ·libc_getxattr_trampoline(SB),NOSPLIT,$0-0 JMP libc_getxattr(SB) TEXT ·libc_fgetxattr_trampoline(SB),NOSPLIT,$0-0 JMP libc_fgetxattr(SB) TEXT ·libc_setxattr_trampoline(SB),NOSPLIT,$0-0 JMP libc_setxattr(SB) TEXT ·libc_fsetxattr_trampoline(SB),NOSPLIT,$0-0 JMP libc_fsetxattr(SB) TEXT ·libc_removexattr_trampoline(SB),NOSPLIT,$0-0 JMP libc_removexattr(SB) TEXT ·libc_fremovexattr_trampoline(SB),NOSPLIT,$0-0 JMP libc_fremovexattr(SB) TEXT ·libc_listxattr_trampoline(SB),NOSPLIT,$0-0 JMP libc_listxattr(SB) TEXT ·libc_flistxattr_trampoline(SB),NOSPLIT,$0-0 JMP libc_flistxattr(SB) TEXT ·libc_setattrlist_trampoline(SB),NOSPLIT,$0-0 JMP libc_setattrlist(SB) TEXT ·libc_fcntl_trampoline(SB),NOSPLIT,$0-0 JMP libc_fcntl(SB) TEXT ·libc_kill_trampoline(SB),NOSPLIT,$0-0 JMP libc_kill(SB) TEXT ·libc_ioctl_trampoline(SB),NOSPLIT,$0-0 JMP libc_ioctl(SB) TEXT ·libc_sysctl_trampoline(SB),NOSPLIT,$0-0 JMP libc_sysctl(SB) TEXT ·libc_sendfile_trampoline(SB),NOSPLIT,$0-0 JMP libc_sendfile(SB) TEXT ·libc_access_trampoline(SB),NOSPLIT,$0-0 JMP libc_access(SB) TEXT ·libc_adjtime_trampoline(SB),NOSPLIT,$0-0 JMP libc_adjtime(SB) TEXT ·libc_chdir_trampoline(SB),NOSPLIT,$0-0 JMP libc_chdir(SB) TEXT ·libc_chflags_trampoline(SB),NOSPLIT,$0-0 JMP libc_chflags(SB) TEXT ·libc_chmod_trampoline(SB),NOSPLIT,$0-0 JMP libc_chmod(SB) TEXT ·libc_chown_trampoline(SB),NOSPLIT,$0-0 JMP libc_chown(SB) TEXT ·libc_chroot_trampoline(SB),NOSPLIT,$0-0 JMP libc_chroot(SB) TEXT ·libc_clock_gettime_trampoline(SB),NOSPLIT,$0-0 JMP libc_clock_gettime(SB) TEXT ·libc_close_trampoline(SB),NOSPLIT,$0-0 JMP libc_close(SB) TEXT ·libc_dup_trampoline(SB),NOSPLIT,$0-0 JMP libc_dup(SB) TEXT ·libc_dup2_trampoline(SB),NOSPLIT,$0-0 JMP libc_dup2(SB) TEXT ·libc_exchangedata_trampoline(SB),NOSPLIT,$0-0 JMP libc_exchangedata(SB) TEXT ·libc_exit_trampoline(SB),NOSPLIT,$0-0 JMP libc_exit(SB) TEXT ·libc_faccessat_trampoline(SB),NOSPLIT,$0-0 JMP libc_faccessat(SB) TEXT ·libc_fchdir_trampoline(SB),NOSPLIT,$0-0 JMP libc_fchdir(SB) TEXT ·libc_fchflags_trampoline(SB),NOSPLIT,$0-0 JMP libc_fchflags(SB) TEXT ·libc_fchmod_trampoline(SB),NOSPLIT,$0-0 JMP libc_fchmod(SB) TEXT ·libc_fchmodat_trampoline(SB),NOSPLIT,$0-0 JMP libc_fchmodat(SB) TEXT ·libc_fchown_trampoline(SB),NOSPLIT,$0-0 JMP libc_fchown(SB) TEXT ·libc_fchownat_trampoline(SB),NOSPLIT,$0-0 JMP libc_fchownat(SB) TEXT ·libc_flock_trampoline(SB),NOSPLIT,$0-0 JMP libc_flock(SB) TEXT ·libc_fpathconf_trampoline(SB),NOSPLIT,$0-0 JMP libc_fpathconf(SB) TEXT ·libc_fsync_trampoline(SB),NOSPLIT,$0-0 JMP libc_fsync(SB) TEXT ·libc_ftruncate_trampoline(SB),NOSPLIT,$0-0 JMP libc_ftruncate(SB) TEXT ·libc_getdtablesize_trampoline(SB),NOSPLIT,$0-0 JMP libc_getdtablesize(SB) TEXT ·libc_getegid_trampoline(SB),NOSPLIT,$0-0 JMP libc_getegid(SB) TEXT ·libc_geteuid_trampoline(SB),NOSPLIT,$0-0 JMP libc_geteuid(SB) TEXT ·libc_getgid_trampoline(SB),NOSPLIT,$0-0 JMP libc_getgid(SB) TEXT ·libc_getpgid_trampoline(SB),NOSPLIT,$0-0 JMP libc_getpgid(SB) TEXT ·libc_getpgrp_trampoline(SB),NOSPLIT,$0-0 JMP libc_getpgrp(SB) TEXT ·libc_getpid_trampoline(SB),NOSPLIT,$0-0 JMP libc_getpid(SB) TEXT ·libc_getppid_trampoline(SB),NOSPLIT,$0-0 JMP libc_getppid(SB) TEXT ·libc_getpriority_trampoline(SB),NOSPLIT,$0-0 JMP libc_getpriority(SB) TEXT ·libc_getrlimit_trampoline(SB),NOSPLIT,$0-0 JMP libc_getrlimit(SB) TEXT ·libc_getrusage_trampoline(SB),NOSPLIT,$0-0 JMP libc_getrusage(SB) TEXT ·libc_getsid_trampoline(SB),NOSPLIT,$0-0 JMP libc_getsid(SB) TEXT ·libc_getuid_trampoline(SB),NOSPLIT,$0-0 JMP libc_getuid(SB) TEXT ·libc_issetugid_trampoline(SB),NOSPLIT,$0-0 JMP libc_issetugid(SB) TEXT ·libc_kqueue_trampoline(SB),NOSPLIT,$0-0 JMP libc_kqueue(SB) TEXT ·libc_lchown_trampoline(SB),NOSPLIT,$0-0 JMP libc_lchown(SB) TEXT ·libc_link_trampoline(SB),NOSPLIT,$0-0 JMP libc_link(SB) TEXT ·libc_linkat_trampoline(SB),NOSPLIT,$0-0 JMP libc_linkat(SB) TEXT ·libc_listen_trampoline(SB),NOSPLIT,$0-0 JMP libc_listen(SB) TEXT ·libc_mkdir_trampoline(SB),NOSPLIT,$0-0 JMP libc_mkdir(SB) TEXT ·libc_mkdirat_trampoline(SB),NOSPLIT,$0-0 JMP libc_mkdirat(SB) TEXT ·libc_mkfifo_trampoline(SB),NOSPLIT,$0-0 JMP libc_mkfifo(SB) TEXT ·libc_mknod_trampoline(SB),NOSPLIT,$0-0 JMP libc_mknod(SB) TEXT ·libc_open_trampoline(SB),NOSPLIT,$0-0 JMP libc_open(SB) TEXT ·libc_openat_trampoline(SB),NOSPLIT,$0-0 JMP libc_openat(SB) TEXT ·libc_pathconf_trampoline(SB),NOSPLIT,$0-0 JMP libc_pathconf(SB) TEXT ·libc_pread_trampoline(SB),NOSPLIT,$0-0 JMP libc_pread(SB) TEXT ·libc_pwrite_trampoline(SB),NOSPLIT,$0-0 JMP libc_pwrite(SB) TEXT ·libc_read_trampoline(SB),NOSPLIT,$0-0 JMP libc_read(SB) TEXT ·libc_readlink_trampoline(SB),NOSPLIT,$0-0 JMP libc_readlink(SB) TEXT ·libc_readlinkat_trampoline(SB),NOSPLIT,$0-0 JMP libc_readlinkat(SB) TEXT ·libc_rename_trampoline(SB),NOSPLIT,$0-0 JMP libc_rename(SB) TEXT ·libc_renameat_trampoline(SB),NOSPLIT,$0-0 JMP libc_renameat(SB) TEXT ·libc_revoke_trampoline(SB),NOSPLIT,$0-0 JMP libc_revoke(SB) TEXT ·libc_rmdir_trampoline(SB),NOSPLIT,$0-0 JMP libc_rmdir(SB) TEXT ·libc_lseek_trampoline(SB),NOSPLIT,$0-0 JMP libc_lseek(SB) TEXT ·libc_select_trampoline(SB),NOSPLIT,$0-0 JMP libc_select(SB) TEXT ·libc_setegid_trampoline(SB),NOSPLIT,$0-0 JMP libc_setegid(SB) TEXT ·libc_seteuid_trampoline(SB),NOSPLIT,$0-0 JMP libc_seteuid(SB) TEXT ·libc_setgid_trampoline(SB),NOSPLIT,$0-0 JMP libc_setgid(SB) TEXT ·libc_setlogin_trampoline(SB),NOSPLIT,$0-0 JMP libc_setlogin(SB) TEXT ·libc_setpgid_trampoline(SB),NOSPLIT,$0-0 JMP libc_setpgid(SB) TEXT ·libc_setpriority_trampoline(SB),NOSPLIT,$0-0 JMP libc_setpriority(SB) TEXT ·libc_setprivexec_trampoline(SB),NOSPLIT,$0-0 JMP libc_setprivexec(SB) TEXT ·libc_setregid_trampoline(SB),NOSPLIT,$0-0 JMP libc_setregid(SB) TEXT ·libc_setreuid_trampoline(SB),NOSPLIT,$0-0 JMP libc_setreuid(SB) TEXT ·libc_setrlimit_trampoline(SB),NOSPLIT,$0-0 JMP libc_setrlimit(SB) TEXT ·libc_setsid_trampoline(SB),NOSPLIT,$0-0 JMP libc_setsid(SB) TEXT ·libc_settimeofday_trampoline(SB),NOSPLIT,$0-0 JMP libc_settimeofday(SB) TEXT ·libc_setuid_trampoline(SB),NOSPLIT,$0-0 JMP libc_setuid(SB) TEXT ·libc_symlink_trampoline(SB),NOSPLIT,$0-0 JMP libc_symlink(SB) TEXT ·libc_symlinkat_trampoline(SB),NOSPLIT,$0-0 JMP libc_symlinkat(SB) TEXT ·libc_sync_trampoline(SB),NOSPLIT,$0-0 JMP libc_sync(SB) TEXT ·libc_truncate_trampoline(SB),NOSPLIT,$0-0 JMP libc_truncate(SB) TEXT ·libc_umask_trampoline(SB),NOSPLIT,$0-0 JMP libc_umask(SB) TEXT ·libc_undelete_trampoline(SB),NOSPLIT,$0-0 JMP libc_undelete(SB) TEXT ·libc_unlink_trampoline(SB),NOSPLIT,$0-0 JMP libc_unlink(SB) TEXT ·libc_unlinkat_trampoline(SB),NOSPLIT,$0-0 JMP libc_unlinkat(SB) TEXT ·libc_unmount_trampoline(SB),NOSPLIT,$0-0 JMP libc_unmount(SB) TEXT ·libc_write_trampoline(SB),NOSPLIT,$0-0 JMP libc_write(SB) TEXT ·libc_mmap_trampoline(SB),NOSPLIT,$0-0 JMP libc_mmap(SB) TEXT ·libc_munmap_trampoline(SB),NOSPLIT,$0-0 JMP libc_munmap(SB) TEXT ·libc_gettimeofday_trampoline(SB),NOSPLIT,$0-0 JMP libc_gettimeofday(SB) TEXT ·libc_fstat_trampoline(SB),NOSPLIT,$0-0 JMP libc_fstat(SB) TEXT ·libc_fstatat_trampoline(SB),NOSPLIT,$0-0 JMP libc_fstatat(SB) TEXT ·libc_fstatfs_trampoline(SB),NOSPLIT,$0-0 JMP libc_fstatfs(SB) TEXT ·libc_getfsstat_trampoline(SB),NOSPLIT,$0-0 JMP libc_getfsstat(SB) TEXT ·libc_lstat_trampoline(SB),NOSPLIT,$0-0 JMP libc_lstat(SB) TEXT ·libc_stat_trampoline(SB),NOSPLIT,$0-0 JMP libc_stat(SB) TEXT ·libc_statfs_trampoline(SB),NOSPLIT,$0-0 JMP libc_statfs(SB)	{ "language": "Assembly" }
COMMENT @----------------------------------------------------------------------- Copyright (c) Geoworks 1991 -- All Rights Reserved PROJECT: PC GEOS MODULE: FILE: uiChooseName.asm AUTHOR: Cheng, 7/92 ROUTINES: Name Description ---- ----------- REVISION HISTORY: Name Date Description ---- ---- ----------- Cheng 7/92 Initial revision DESCRIPTION: $Id: uiChooseName.asm,v 1.1 97/04/07 11:12:40 newdeal Exp $ -------------------------------------------------------------------------------@ ;--------------------------------------------------- SpreadsheetClassStructures segment resource SSChooseNameControlClass ;declare the class record SpreadsheetClassStructures ends ;--------------------------------------------------- ChooseNameControlCode segment resource COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% SSCNGetInfo %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% SYNOPSIS: Get GenControl info for the SSChooseNameControl CALLED BY: MSG_GEN_CONTROL_GET_INFO PASS: ds:si - instance data ds:di - ds:si es - seg addr of SSChooseNameControlClass ax - the message cx:dx - GenControlBuildInfo structure to fill in RETURN: cx:dx - filled in DESTROYED: bx, si, di, ds, es (method handler) PSEUDO CODE/STRATEGY: KNOWN BUGS/SIDE EFFECTS/IDEAS: REVISION HISTORY: Name Date Description ---- ---- ----------- cheng 7/92 Initial version %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@ SSCNGetInfo method dynamic SSChooseNameControlClass, \ MSG_GEN_CONTROL_GET_INFO mov si, offset SSCN_dupInfo mov es, cx mov di, dx ;es:di = dest segmov ds, cs mov cx, size GenControlBuildInfo rep movsb ret SSCNGetInfo endm SSCN_dupInfo GenControlBuildInfo < mask GCBF_SUSPEND_ON_APPLY, ; GCBI_flags SSCN_IniFileKey, ; GCBI_initFileKey SSCN_gcnList, ; GCBI_gcnList length SSCN_gcnList, ; GCBI_gcnCount SSCN_notifyTypeList, ; GCBI_notificationList length SSCN_notifyTypeList, ; GCBI_notificationCount SSCNName, ; GCBI_controllerName handle SSChooseNameControlUI, ; GCBI_dupBlock SSCN_childList, ; GCBI_childList length SSCN_childList, ; GCBI_childCount SSCN_featuresList, ; GCBI_featuresList length SSCN_featuresList, ; GCBI_featuresCount SSCN_DEFAULT_FEATURES, ; GCBI_features 0, ; GCBI_toolBlock 0, ; GCBI_toolList 0, ; GCBI_toolCount 0, ; GCBI_toolFeaturesList 0, ; GCBI_toolFeaturesCount 0, ; GCBI_toolFeatures SSCN_helpContext> ; GCBI_helpContext if FULL_EXECUTE_IN_PLACE SpreadsheetControlInfoXIP segment resource endif SSCN_helpContext char "dbInsName", 0 SSCN_IniFileKey char "ssChooseName", 0 SSCN_gcnList GCNListType \ <MANUFACTURER_ID_GEOWORKS, GAGCNLT_APP_TARGET_NOTIFY_SPREADSHEET_NAME_CHANGE> SSCN_notifyTypeList NotificationType \ <MANUFACTURER_ID_GEOWORKS, GWNT_SPREADSHEET_NAME_CHANGE> ;--- SSCN_childList GenControlChildInfo \ <offset ChooseNameDB, mask SSCNF_CHOOSE_NAME, mask GCCF_IS_DIRECTLY_A_FEATURE> ; Careful, this table is in the opposite order as the record which ; it corresponds to. SSCN_featuresList GenControlFeaturesInfo \ <offset ChooseNameList, ChooseNameName, 0> if FULL_EXECUTE_IN_PLACE SpreadsheetControlInfoXIP ends endif COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% SSCNUpdateUI %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% SYNOPSIS: Update UI for SSChooseNameControl CALLED BY: MSG_GEN_CONTROL_UPDATE_UI PASS: ds:si - instance data ds:di - ds:si es - seg addr of SSChooseNameControlClass ax - the message RETURN: none DESTROYED: ax, bx, cx, dx, bp, si (method handler) PSEUDO CODE/STRATEGY: KNOWN BUGS/SIDE EFFECTS/IDEAS: REVISION HISTORY: Name Date Description ---- ---- ----------- cheng 7/92 Initial version %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@ SSCNUpdateUI method dynamic SSChooseNameControlClass, \ MSG_GEN_CONTROL_UPDATE_UI call SSCGetChildBlockAndFeatures mov ax, MSG_SPREADSHEET_INIT_CHOOSE_NAME_LIST mov cx, ds:LMBH_handle mov dx, si call SSCSendToSpreadsheet ret SSCNUpdateUI endm COMMENT @----------------------------------------------------------------------- FUNCTION: SSCNUpdateUIWithNumNames DESCRIPTION: CALLED BY: INTERNAL (MSG_CNC_UPDATE_UI_WITH_NUM_NAMES) PASS: cx - number of names RETURN: DESTROYED: REGISTER/STACK USAGE: PSEUDO CODE/STRATEGY: KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS: REVISION HISTORY: Name Date Description ---- ---- ----------- Cheng 6/92 Initial version -------------------------------------------------------------------------------@ SSCNUpdateUIWithNumNames method dynamic SSChooseNameControlClass, \ MSG_CNC_UPDATE_UI_WITH_NUM_NAMES call SSCNEnableDisableUI call SSCGetChildBlockAndFeatures mov si, offset ChooseNameList mov ax, MSG_GEN_DYNAMIC_LIST_INITIALIZE clr di call ObjMessage ret SSCNUpdateUIWithNumNames endm COMMENT @----------------------------------------------------------------------- FUNCTION: SSCNEnableDisableUI DESCRIPTION: CALLED BY: INTERNAL () PASS: cx - number of names RETURN: DESTROYED: REGISTER/STACK USAGE: PSEUDO CODE/STRATEGY: KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS: REVISION HISTORY: Name Date Description ---- ---- ----------- Cheng 6/92 Initial version -------------------------------------------------------------------------------@ SSCNEnableDisableUI proc near uses ax,bx,cx,dx,di,si,bp .enter call SSCGetChildBlockAndFeatures ; bx <- child block ; ; We want to enable/disable the Paste trigger ; depending on whether or not there are any items ; mov ax, MSG_GEN_SET_ENABLED tst cx ; Check for items jnz enableDisable ; Branch if has items mov ax, MSG_GEN_SET_NOT_ENABLED enableDisable: ; ; If there are no entries in the list we disable the Paste triggers ; push bx mov si, offset ChooseNameTrigger mov di, mask MF_CALL mov dl, VUM_NOW call ObjMessage pop bx .leave ret SSCNEnableDisableUI endp COMMENT @----------------------------------------------------------------------- FUNCTION: SSCNRequestMoniker DESCRIPTION: CALLED BY: INTERNAL () PASS: cx:dx GenDynamicList OD bp - entry # RETURN: DESTROYED: REGISTER/STACK USAGE: PSEUDO CODE/STRATEGY: KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS: REVISION HISTORY: Name Date Description ---- ---- ----------- Cheng 6/92 Initial version -------------------------------------------------------------------------------@ SSCNRequestMoniker method dynamic SSChooseNameControlClass, MSG_CHOOSE_NAME_REQUEST_MONIKER .enter call SSCGetChildBlockAndFeatures mov ax, MSG_SPREADSHEET_NAME_REQUEST_ENTRY_MONIKER mov cx, bx mov dx, offset ChooseNameList ;^lcx:dx <- OD of list call SSCSendToSpreadsheet .leave ret SSCNRequestMoniker endm COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% SSCNChooseName %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% SYNOPSIS: Change the function that is selected CALLED BY: MSG_SS_CHOOSE_NAME PASS: ds:si - instance data ds:di - ds:si es - seg addr of SSChooseNameControlClass ax - the message cx - index of the function in the list RETURN: none DESTROYED: bx, si, di, ds, es (method handler) PSEUDO CODE/STRATEGY: KNOWN BUGS/SIDE EFFECTS/IDEAS: REVISION HISTORY: Name Date Description ---- ---- ----------- gene 9/27/92 Initial version %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@ SSCNChooseName method dynamic SSChooseNameControlClass, MSG_SS_CHOOSE_NAME if not KEYBOARD_ONLY_UI mov ax, MSG_META_RELEASE_FOCUS_EXCL call ObjCallInstanceNoLock mov ax, MSG_META_ENSURE_ACTIVE_FT call GenCallApplication endif push si call SSCGetChildBlockAndFeatures mov si, offset ChooseNameList ;^lbx:si <- OD of list mov ax, MSG_GEN_ITEM_GROUP_GET_SELECTION call SSCNObjMessageCall ; ax <- cur selection, carry if none jc donePop ;branch if none selected mov cx, ax ; cx <- item to get mov ax, MSG_GEN_ITEM_GROUP_GET_ITEM_OPTR call SSCNObjMessageCall ; ^lcx:dx <- selected item jnc donePop ;branch if none selected movdw bxsi, cxdx mov ax, MSG_GEN_GET_VIS_MONIKER call SSCNObjMessageCall ; ^lax <- VisMoniker chunk ; ; allocate a block of memory for the string and copy the string over ; push bx, ds mov si, ax call ObjLockObjBlock mov ds, ax mov si, ds:[si] ChunkSizePtr ds, si, cx add si, (offset VM_data + offset VMT_text) ; ds:si <- text string sub cx, (offset VM_data + offset VMT_text) ; cx <- text size push cx mov ax, cx ;ax <- # bytes to allocate mov cx, (mask HAF_LOCK shl 8) call MemAlloc ;ax <- seg; bx <- handle mov es, ax clr di ;es:di <- dest pop cx ;cx <- # of bytes to copy rep movsb call MemUnlock mov dx, bx ;dx <- handle of string pop bx, ds call MemUnlock pop si ;*ds:si <- controller ; ; dx = mem handle ; ; clr cx ; string is null-terminated clr bp ;bp.low <- offset; bp.high <- md mov ax, MSG_SPREADSHEET_REPLACE_TEXT_SELECTION clr bx, di call GenControlOutputActionRegs ret donePop: add sp, 2 ;clear si from stack ret SSCNChooseName endm SSCNObjMessageCall proc near uses di .enter mov di, mask MF_FIXUP_DS or mask MF_CALL call ObjMessage .leave ret SSCNObjMessageCall endp ChooseNameControlCode ends	{ "language": "Assembly" }
/++ Copyright (c) 2013 Minoca Corp. This file is licensed under the terms of the GNU General Public License version 3. Alternative licensing terms are available. Contact [email protected] for details. See the LICENSE file at the root of this project for complete licensing information. Module Name: entry.S Abstract: This module implements the entry point for the loader. Author: Evan Green 18-Aug-2013 Environment: Kernel mode --/ // // ------------------------------------------------------------------ Includes // #include <minoca/kernel/x86.inc> // // ---------------------------------------------------------------------- Code // // // .text specifies that this code belongs in the executable section. // // .code32 specifies that this is 32-bit protected mode code. // .text .code32 // // Stick this in the .init section so it ends up at the front of the binary. // .section .init // // .globl allows this label to be visible to the linker. // .globl _start // // void // start ( // ) // /++ Routine Description: This routine implements the entry point for the firmware. It jumps to the main C routine. It is called by the file system specific boot code. Arguments: None. Return Value: TRUE if interrupts are enabled in the processor. FALSE if interrupts are globally disabled. --/ _start: jmp EfiBiosMain # Just do it. // // --------------------------------------------------------- Internal Functions //	{ "language": "Assembly" }
#RUN: llvm-xray graph %s -o - -m %S/Inputs/simple-instrmap.yaml -d \ #RUN: \| FileCheck %s -check-prefix=EMPTY #RUN: llvm-xray graph %s -o - -m %S/Inputs/simple-instrmap.yaml -d -e count \ #RUN: \| FileCheck %s -check-prefix=COUNT # #RUN: llvm-xray graph %s -o - -m %S/Inputs/simple-instrmap.yaml -d -e min \ #RUN: \| FileCheck %s -check-prefix=TIME #RUN: llvm-xray graph %s -o - -m %S/Inputs/simple-instrmap.yaml -d -e med \ #RUN: \| FileCheck %s -check-prefix=TIME #RUN: llvm-xray graph %s -o - -m %S/Inputs/simple-instrmap.yaml -d -e 90p \ #RUN: \| FileCheck %s -check-prefix=TIME #RUN: llvm-xray graph %s -o - -m %S/Inputs/simple-instrmap.yaml -d -e 99p \ #RUN: \| FileCheck %s -check-prefix=TIME #RUN: llvm-xray graph %s -o - -m %S/Inputs/simple-instrmap.yaml -d -e max \ #RUN: \| FileCheck %s -check-prefix=TIME #RUN: llvm-xray graph %s -o - -m %S/Inputs/simple-instrmap.yaml -d -e sum \ #RUN: \| FileCheck %s -check-prefix=TIME # --- header: version: 1 type: 0 constant-tsc: true nonstop-tsc: true cycle-frequency: 0 records: # Here we reconstruct the following call trace: # # f1() # f2() # f3() # # But we find that we're missing an exit record for f2() because it's # tail-called f3(). We make sure that if we see a trace like this that we can # deduce tail calls, and account the time (potentially wrongly) to f2() when # f1() exits. That is because we don't go back to f3()'s entry record to # properly do the math on the timing of f2(). # # Note that by default, tail/sibling call deduction is disabled, and is enabled # with a flag "-d" or "-deduce-sibling-calls". # - { type: 0, func-id: 1, cpu: 1, thread: 111, kind: function-enter, tsc: 10000 } - { type: 0, func-id: 2, cpu: 1, thread: 111, kind: function-enter, tsc: 10001 } - { type: 0, func-id: 3, cpu: 1, thread: 111, kind: function-enter, tsc: 10002 } - { type: 0, func-id: 3, cpu: 1, thread: 111, kind: function-exit, tsc: 10003 } - { type: 0, func-id: 1, cpu: 1, thread: 111, kind: function-exit, tsc: 10004 } ... #EMPTY: digraph xray { #EMPTY-DAG: F0 -> F1 [label=""]; #EMPTY-DAG: F1 -> F2 [label=""]; #EMPTY-DAG: F2 -> F3 [label=""]; #EMPTY-DAG: F1 [label="@(1)"]; #EMPTY-DAG: F2 [label="@(2)"]; #EMPTY-DAG: F3 [label="@(3)"]; #EMPTY-NEXT: } #COUNT: digraph xray { #COUNT-DAG: F0 -> F1 [label="1"]; #COUNT-DAG: F1 -> F2 [label="1"]; #COUNT-DAG: F2 -> F3 [label="1"]; #COUNT-DAG: F1 [label="@(1)"]; #COUNT-DAG: F2 [label="@(2)"]; #COUNT-DAG: F3 [label="@(3)"]; #COUNT-NEXT: } #TIME: digraph xray { #TIME-DAG: F0 -> F1 [label="4.{{.}}"]; #TIME-DAG: F1 -> F2 [label="3.{{.}}"]; #TIME-DAG: F2 -> F3 [label="1.{{.*}}"]; #TIME-DAG: F1 [label="@(1)"]; #TIME-DAG: F2 [label="@(2)"]; #TIME-DAG: F3 [label="@(3)"]; #TIME-NEXT: }	{ "language": "Assembly" }
// REQUIRES: x86 // This is a test for R_X86_64_PC8 and R_X86_64_PC16. // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t1.o // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/x86-64-pcrel.s -o %t2.o // RUN: ld.lld -o %t.exe %t1.o %t2.o // RUN: llvm-objdump -s %t.exe \| FileCheck %s // CHECK: Contents of section .text: // CHECK-NEXT: 2000cccc cccccccc cccccccc cccccccc // CHECK-NEXT: 20cccccc cccccccc cccccccc cccccccc // CHECK-NEXT: e0ffcccc cccccccc cccccccc cccccccc // CHECK-NEXT: e0cccccc cccccccc cccccccc cccccccc .globl _start _start: .word foo - _start .fill 14,1,0xcc .byte foo - _start .fill 15,1,0xcc	{ "language": "Assembly" }

.setcpu "65c02" .org $C000 ; Set to the version of Apple //c ROM you want to build. Typically ; done on the command line. ;ROMVER = 255 ;ROMVER = 0 ;ROMVER = 3 ;ROMVER = 4 .if ROMVER = 255 .elseif ROMVER = 0 .elseif ROMVER = 3 .elseif ROMVER = 4 .else .error "ROMVER not set correctly." .endif ; This file is not part of the version 255 ROM. .if .not ROMVER = 255 .res 256 lda #$0E .byte $1C .byte $7F .byte $07 sec lda $C019 bpl $C136 sta $C079 lda #$0C bit $07FF bne $C118 sta $C05A ora #$02 sta $C078 bit $067F bne $C124 lda #$0C bit $C063 bpl $C12B eor #$04 and $07FF .byte $0C .byte $7F .byte $07 .byte $1C .byte $7F asl $69 inc $FFAD,x .byte $07 bmi $C1AD lda $C015 ora $C017 bpl $C1AD txa ldx #$00 bit $C015 bmi $C155 tya eor #$80 ldx #$80 bit $C017 bpl $C18E asl a lda $047F,x bcs $C175 cmp $047D,x bne $C168 lda $057F,x cmp $057D,x beq $C18A lda $047F,x bne $C170 dec $057F,x dec $047F,x bra $C18A cmp $067D,x bne $C182 lda $057F,x cmp $077D,x beq $C18A inc $047F,x bne $C18A inc $057F,x cpx #$00 beq $C14B sta $C048 lda #$02 and $07FF beq $C1A1 sta $C079 sta $C05B sta $C078 ora #$20 .byte $0C .byte $7F asl $A9 asl $7F2D .byte $07 adc #$FE bcs $C1B4 jmp $C784 sec rts jsr $C1BA jmp $C784 ldx #$C2 jsr $C1C2 bcc $C1B3 dex ldy $C142,x lda #$04 eor $BFFA,y and #$0C beq $C1B2 lda $BFF9,y sta $0438,x bpl $C1B2 cpx #$C2 bcs $C1DC eor #$40 bit $0538,x bvs $C20A bpl $C208 bcc $C208 bit #$40 beq $C20A lda $C000 ldy #$80 jsr $C228 cmp #$98 bne $C200 lda $C062 bpl $C200 stx $05FC .if ROMVER = 255 stx $06FF .elseif ROMVER = 0 stx $06FF .elseif ROMVER = 3 stx $06FF .elseif ROMVER = 4 stx $06FC .endif lda $C010 ldy #$B0 lda $BFF9,y and #$BF asl a asl a and #$20 beq $C24E lda $BFFA,y eor #$01 and #$03 bne $C24E txa eor $04FC bne $C1B2 php jsr $C322 bcc $C24D ldy #$00 bne $C231 phx pha lda $057C,y tax inc a bit #$7F bne $C235 tya cmp $067C,y beq $C23D sta $057C,y pla bit $C014 sta $C005 sta $0800,x bmi $C24C sta $C004 plx plp rts jsr $C255 jmp $C784 pha bit $C2AB beq $C25E inc $0738,x jsr $C2B2 and #$30 cmp #$10 bne $C25E lda $06B8,x bit #$20 beq $C28D cpx $04FC beq $C286 jsr $C2E9 bcc $C286 ldy $C234,x sta $05FE,y lda $06B8,x ora #$04 sta $06B8,x lda $06B8,x and #$02 bne $C25E ldy $C142,x pla pha sta $BFF8,y bit $06B8,x eor #$0D asl a bne $C2AA bvc $C2A5 lda #$14 ror a jsr $C255 stz $24 stz $0738,x pla rts jsr $C2B2 jmp $C784 php sei ldy $C142,x lda $BFF9,y bpl $C2C1 jsr $C1D6 bra $C2B4 plp rts jsr $C2C9 jmp $C784 cpx $04FC bne $C2D5 ldy #$00 jsr $C2FD bcs $C2F4 lda $06B8,x bit #$04 beq $C2E9 and #$FB sta $06B8,x ldy $C234,x lda $05FE,y sec rts jsr $C2B2 and #$08 clc beq $C2F4 jsr $C322 rts brk bra $C318 sbc $4CC2,x sty $C7 lda $067C,y cmp $057C,y clc beq $C321 pha inc a bit #$7F bne $C30D tya sta $067C,y ply lda $C013 asl a sta $C003 lda $0800,y bcs $C321 sta $C002 sec rts lda $BFF8,y pha ora #$80 tay lda $06B8,x bit #$08 bne $C334 cpy #$8A beq $C346 bit #$20 beq $C348 cpy #$91 bne $C340 and #$FD bra $C346 cpy #$93 bne $C348 ora #$02 clc bcs $C381 sta $06B8,x pla rts pha lda $C013 pha lda $C014 pha bcc $C361 sta $C002 sta $C005 bcs $C367 sta $C004 sta $C003 lda ($3C) sta ($42) inc $42 bne $C371 inc $43 lda $3C cmp $3E lda $3D sbc $3F inc $3C bne $C37F inc $3D bcc $C367 sta $C004 pla bpl $C38A sta $C005 sta $C002 pla bpl $C393 sta $C003 pla jmp $C784 pha lda $03ED pha lda $03EE pha bcc $C3AA sta $C003 sta $C005 bcs $C3B0 sta $C002 sta $C004 pla sta $03EE pla sta $03ED pla bvs $C3C0 sta $C008 bvc $C3C3 sta $C009 jmp $C7EB stx $01 stx $02 stx $03 ldx #$04 stx $04 sta $05 ldx #$04 stz $01 inc $01 tay sta $C083 sta $C083 lda $01 and #$F0 cmp #$C0 bne $C3F3 lda $C08B lda $C08B lda $01 adc #$0F bne $C3F5 lda $01 sta $03 tya ldy #$00 clc adc $C82A,x sta ($02),y dex bpl $C405 ldx #$04 iny bne $C3FA inc $01 bne $C3D8 inc $01 ldx #$04 lda $05 tay lda $C083 lda $C083 lda $01 and #$F0 cmp #$C0 bne $C42A lda $C08B lda $01 adc #$0F bne $C42C lda $01 sta $03 tya ldy #$00 clc adc $C82A,x eor ($02),y bne $C472 lda ($02),y dex bpl $C440 ldx #$04 iny bne $C431 inc $01 bne $C412 ror a bit $C019 bpl $C44F eor #$A5 dec $04 bmi $C456 jmp $C3D0 tax bit $C013 bmi $C46C txa sta $C005 sta $C003 sta $C009 sta $C081 jmp $D497 sta $C008 jmp $C4EF sec tax lda $C013 clv bpl $C47D bit $C82A lda #$A0 ldy #$06 sta $BFFE,y sta $C006,y dey dey bne $C481 sta $C051 sta $C054 sta $0400,y sta $0500,y sta $0600,y sta $0700,y iny bne $C491 txa beq $C4CA ldy #$03 bcs $C4A9 ldy #$05 lda #$AA bvc $C4B0 sta $05B0 lda $C866,y sta $05B1,y dey bpl $C4B0 ldy #$10 txa lsr a tax lda #$58 rol a sta $05B6,y dey dey bne $C4BB beq $C4C8 ldx #$02 ply php lda $C86C,x plp php bcc $C4D8 lda $C86F,x cpy #$06 bcc $C4E7 cpy #$08 bcc $C4E4 cpy #$11 bcc $C4E7 lda $C872,x sta $05B8,x dex bpl $C4CE bmi $C4ED ldy #$01 lda #$7F ror a ldx $C82F,y beq $C508 bcc $C4FE ldx $C841,y sta $BFFF,x iny bne $C4F3 ldx $C030 rol a dey ldx $C853,y beq $C521 bmi $C504 rol a bcc $C51A asl $C000,x bcc $C537 bcs $C508 asl $C000,x bcs $C537 bcc $C508 rol a iny sec sbc #$01 bcs $C4F3 dey beq $C533 cpy #$08 bne $C53F ldy #$11 bne $C4F1 ldy #$09 bne $C4F1 phy ldx #$00 cpy #$0A jmp $C47D lsr $80 bne $C4EF lda #$A0 ldy #$00 sta $0400,y sta $0500,y sta $0600,y sta $0700,y iny bne $C547 lda $C061 and $C062 asl a inc $FF lda $FF bcc $C566 jmp $D48E lda $C051 ldy #$08 lda $C875,y sta $05B8,y dey bpl $C56B bmi $C556 .res 10 phx ldx $0678 inc $C000,x plx lda $49 sta $BFF8,x lda $4A sta $BFF9,x lda $4B and #$7F cmp $03B8,y bcs $C5EE sta $BFFA,x bit $C014 php sta $C004 bit $4B bpl $C5AC sta $C005 ldy #$00 lda $48 sta $05F8 beq $C5C9 lda $BFFB,x sta ($45),y iny lda $BFFB,x sta ($45),y iny bne $C5B5 inc $46 dec $48 bne $C5B5 lda $47 beq $C5E3 sta $0578 lsr a bcs $C5D9 lda $BFFB,x sta ($45),y iny lda $BFFB,x sta ($45),y iny cpy $47 bne $C5D3 sta $C004 plp bpl $C5EC sta $C005 bra $C5F3 lda #$2D sta $04F8 sta $C081 rts phx ldx $0678 inc $C000,x plx lda $49 sta $BFF8,x lda $4A sta $BFF9,x lda $4B and #$7F cmp $03B8,y bcs $C5EE sta $BFFA,x bit $C013 php sta $C002 bit $4B bpl $C623 sta $C003 ldy #$00 lda $48 sta $05F8 beq $C640 lda ($45),y sta $BFFB,x iny lda ($45),y sta $BFFB,x iny bne $C62C inc $46 dec $48 bne $C62C lda $47 sta $0578 beq $C65A lsr a bcs $C650 lda ($45),y sta $BFFB,x iny lda ($45),y sta $BFFB,x iny cpy $47 bne $C64A sta $C002 plp bpl $C663 sta $C003 sta $C081 rts sed brk brk brk .byte $07 eor ($41) eor $4143 eor ($44) jsr $2020 jsr $2020 jsr $2020 brk brk .if ROMVER = 255 .byte $01 .elseif ROMVER = 0 .byte $01 .elseif ROMVER = 3 .byte $01 .elseif ROMVER = 4 .byte $02 .endif .byte $01 .byte $03 .byte $03 .byte $03 .byte $03 .byte $03 .byte $03 ora ($01,x) .byte $03 .byte $03 ora ($01,x) ora ($01,x) ora ($01,x) .byte $04 .byte $04 .byte $04 .byte $04 .byte $FF .byte $FF .byte $FF .byte $FF .byte $FF .byte $FF .byte $52 .if ROMVER = 255 .byte $73 .elseif ROMVER = 0 .byte $73 .elseif ROMVER = 3 .byte $73 .elseif ROMVER = 4 .byte $7D .endif .byte $2F .if ROMVER = 255 .byte $B8 .elseif ROMVER = 0 .byte $B8 .elseif ROMVER = 3 .byte $B8 .elseif ROMVER = 4 .byte $C2 .endif .byte $2F .if ROMVER = 255 .byte $BC .elseif ROMVER = 0 .byte $BC .elseif ROMVER = 3 .byte $BC .elseif ROMVER = 4 .byte $C6 .endif .byte $2F sec .if ROMVER = 255 .byte $69 .byte $69 .elseif ROMVER = 0 .byte $69 .byte $69 .elseif ROMVER = 3 .byte $69 .byte $69 .elseif ROMVER = 4 .byte $73 .byte $73 .endif sec sec .byte $2F .byte $2F .byte $2F .byte $2F .byte $2F and $3C2F,y .byte $45 .if ROMVER = 255 .byte $9D .elseif ROMVER = 0 .byte $9D .elseif ROMVER = 3 .byte $9D .elseif ROMVER = 4 .byte $A7 .endif .byte $AB sec .byte $3F .byte 'B' phx jsr $C816 phy sty $0678 jsr $D8F9 jmp $C80E phx jsr $C816 phy jsr $D621 jmp $C80E phx jsr $C816 phy jsr $D6C2 jmp $C80E phx jsr $C816 phy jsr $D679 jmp $C80E phx jsr $C816 phy jsr $D668 jmp $C80E phx jsr $C816 phy jsr $D6A3 jmp $C80E phx jsr $C816 phy jsr $D651 jmp $C80E phx jsr $C816 phy jsr $D600 jmp $C80E .res 13 sta $C028 jmp $C6C2 sta $C028 jmp $C6CD sta $C028 jmp $C6D8 sta $C028 jmp $C6E3 sta $C028 jmp $C6EE sta $C028 jmp $C6F9 sta $C028 jmp $C704 sta $C028 jmp $CF9A sta $C028 jmp $C6B4 sta $C028 phx jsr $C816 phy sty $0678 jsr $D800 jmp $C80E .res 29 sta $C028 rti sta $C028 rts sta $C028 jmp $FA62 sta $C028 bit $C787 jmp $C804 sta $C028 jmp $C880 sta $C028 jmp $D400 sta $C028 jmp $C7F1 sta $C028 jmp $C806 sta $C028 jmp $C34E sta $C028 jmp $C397 sta $C028 jmp $C100 sta $C028 jmp $D48E sta $C028 jmp $C580 sta $C028 jmp $C24F sta $C028 jmp $C2AC sta $C028 jmp $C2C3 sta $C028 jmp $C2F7 sta $C028 jmp $D4C5 sta $C028 jmp ($03ED) phx jsr $C816 phy jsr $D1A0 bra $C80E .res 8 jmp $C78E phx jsr $C816 phy jsr $D000 plx inc $C000,x plx jmp $C784 ldy #$81 bit $C012 bpl $C829 ldy #$8B bit $C011 bpl $C826 ldy #$83 sta $C081 rts .byte 'S' .byte 'C' .byte $2B and #$07 brk bit #$03 ora $09 ora ($7F,x) .byte '_' brk .byte $83 eor ($53),y eor $57,x .byte $0F ora $8000 brk sta ($04,x) asl $0A .byte $02 .byte $7F rts brk sty $52 .byte 'T' lsr $58,x bpl $C85F brk .byte $7F brk ora ($13),y .byte $14 asl $18,x .byte $FF .byte $7F brk ora ($1A) .byte $1B .byte $1C ora $1F1E,x brk ror $D200,x cmp ($CD,x) ldy #$DA bne $C83A cmp $C9D5 .byte $CF cmp $C7,x cpy $D3D5 sbc $F4F3,y sbc $ED ldy #$CF .byte $CB brk brk jmp $CD4C jsr $CB61 jsr $CA7D ldy #$07 jsr $CC20 lda $C08B,x lda $C089,x ldy #$32 lda $C08E,x bmi $C8A2 dey bne $C896 sec jmp $C9CC lda $C081,x ldy #$05 lda #$FF sta $C08F,x lda $C9D3,y asl $C08C,x bcc $C8AF sta $C08D,x dey bpl $C8AC lda $5A ora #$80 jsr $CA50 jsr $CA4E lda $5B jsr $CA50 jsr $CA4E jsr $CA4E lda $4C ora #$80 jsr $CA50 lda $4B ora #$80 jsr $CA50 lda $4C beq $C8F6 ldy #$FF lda $59 asl $C08C,x bcc $C8E5 sta $C08D,x iny lda ($54),y ora #$80 cpy $4C bcc $C8E5 lda $4B bne $C8FD jmp $C996 nop ldy #$00 lda $41 sta $C08D,x lda $4D ora #$80 sty $59 ldy $C08C,x bpl $C90B sta $C08D,x ldy $59 lda ($56),y sta $4D asl a rol $41 iny bne $C924 inc $57 jmp $C926 pha pla lda #$02 ora $41 sta $41 lda $4E ora #$80 sta $C08D,x lda ($56),y sta $4E asl a rol $41 iny lda $4F ora #$80 sta $C08D,x lda ($56),y sta $4F asl a rol $41 iny lda $50 ora #$80 sta $C08D,x lda ($56),y sta $50 asl a rol $41 iny bne $C960 inc $57 jmp $C962 pha pla lda $51 ora #$80 sta $C08D,x lda ($56),y sta $51 asl a rol $41 iny lda $52 ora #$80 sta $C08D,x lda ($56),y sta $52 asl a rol $41 iny lda $53 ora #$80 sta $C08D,x lda ($56),y sta $53 asl a rol $41 iny dec $4B beq $C996 jmp $C900 lda $40 ora #$AA ldy $C08C,x bpl $C99A sta $C08D,x lda $40 lsr a ora #$AA jsr $CA50 lda #$C8 jsr $CA50 lda $C08C,x and #$40 bne $C9AF sta $C08D,x ldy #$0A dey bne $C9C6 lda #$01 jsr $CA97 sec bcs $C9CC lda $C08E,x bmi $C9BB clc lda $C080,x lda $C08C,x rts .byte $C3 .byte $FF .byte $FC .byte $F3 .byte $CF .byte $3F jsr $C9DE nop nop nop rts jmp $C9C0 lda #$00 sta $40 lda $54 sta $56 lda $55 sta $57 jsr $CA7D lda $C08D,x lda $C08E,x bpl $C9F5 lda $C081,x ldy #$1E lda $C08C,x bpl $C9FF dey bmi $C9E0 cmp #$C3 bne $C9FF ldy #$06 lda $C08C,x bpl $CA0D and #$7F sta $004B,y eor #$80 eor $40 sta $40 dey bpl $CA0D lda $4C beq $CA4B clc adc $54 sta $56 lda $55 adc #$00 sta $57 ldy #$00 lda $C08C,x bpl $CA31 asl a sta $41 lda $C08C,x bpl $CA39 asl $41 bcs $CA44 eor #$80 sta ($54),y iny cpy $4C bcc $CA39 jmp $CC73 lda #$80 ldy $C08C,x bpl $CA50 sta $C08D,x eor $40 sta $40 rts jsr $CA87 lda $C081,x lda $C085,x ldy #$50 jsr $CA70 jsr $CA87 ldy #$0A jsr $CA77 dey bne $CA70 rts ldx #$C8 dex bne $CA79 rts jsr $CA97 lda $C083,x lda $C087,x rts jsr $CA97 lda $C080,x lda $C082,x lda $C084,x lda $C086,x rts ldx #$60 rts bra $CA1C bra $CA1E bra $CA20 bra $CA22 brk brk brk brk brk brk brk brk bra $CA2C bra $CA2E brk brk brk brk bra $CA34 bra $CA36 brk brk brk brk bra $CA3C brk brk bra $CA40 brk brk bra $CA44 brk brk bra $CA48 brk brk bra $CACC bra $CACE bra $CAD0 bra $CAD2 bra $CAD4 bra $CAD6 bra $CAD8 bra $CADA lda #$05 ldy #$00 jsr $CAFD bcc $CAE8 lda #$80 jsr $CF98 rts jsr $CAFD bcc $CAE8 lda #$80 jsr $CF98 lda $06F8 sta $4D lda $0778 sta $4E lda #$B8 ldy #$0B ldx $58 sta $04F3,x tya sta $0573,x lda $4D sta $06F8 lda $4E sta $0778 jsr $C883 lda $06F8 sta $4D lda $0778 sta $4E bcc $CB2F ldx $58 dec $04F3,x bne $CB0A dec $0573,x bpl $CB0A rts ldy $58 lda #$05 sta $04F3,y jsr $C9E3 bcc $CB4B ldy #$01 jsr $CA70 jsr $C9C0 ldx $58 dec $04F3,x bne $CB37 rts brk bit $49 brk .byte $04 ora ($00,x) ora ($02,x) .byte $04 ora #$12 brk ora ($02,x) .byte $04 ora ($02,x) brk .byte $7F .byte $FF ldx $4E beq $CB7C lda $55 sta $57 lda #$80 cpx #$01 beq $CB73 inc $57 lda #$00 clc adc $54 sta $56 bcc $CB7C inc $57 lda $CB4C,x sta $4B lda $CB4F,x sta $4C ldx #$05 lda $4D sta $59 and #$07 tay asl $59 bcc $CBA8 lda $CB58,x clc adc $4C cmp #$07 bcc $CB9F sbc #$07 sta $4C lda $CB52,x adc $4B sta $4B dex bmi $CBB1 bne $CB8F tya jmp $CB96 lda $55 pha lda #$00 ldx $4E beq $CBD0 ldy $CB5E,x eor ($54),y eor ($56),y dey bne $CBBD eor ($54),y eor ($56),y cpx #$01 beq $CBCE inc $55 inc $55 ldy $4D beq $CBDD eor ($54),y eor ($54),y dey bne $CBD6 eor ($54),y sta $40 pla sta $55 ldy $4C dey lda #$00 sta $59 lda ($54),y asl a ror $59 dey bpl $CBE9 sec ror $59 lda $4C clc adc $54 sta $56 lda $55 adc #$00 sta $57 ldy #$06 sec lda ($56),y sta $004D,y bmi $CC0C clc ror $41 dey bpl $CC03 sec ror $41 lda $56 clc adc #$07 sta $56 bcc $CC1F inc $57 rts lda $C088,x lda $C08D,x jmp $CC2D tya sta $C08F,x tya eor $C08E,x and #$1F bne $CC29 rts jsr $CA97 lda $C08E,x lda $C08D,x lda $C08E,x and #$20 bne $CC3F lda $C08C,x phy ldy #$8C dey bne $CC4C ply rts lda $4B tay ldx #$00 stx $4B ldx #$03 asl a rol $4B dex bne $CC5A clc adc $4C bcc $CC67 inc $4B sty $4C sec sbc $4C bcs $CC70 dec $4B ldy $4B rts ldy #$00 lda $4B pha bne $CC7D jmp $CD0A lda $C0EC bpl $CC7D sta $59 lsr a lsr a lsr a and #$0F tax lda $59 and #$07 sta $59 lda $C0EC bpl $CC90 eor $CA9A,x sta ($56),y eor $40 sta $40 iny bne $CCA3 inc $57 lda $C0EC bpl $CCA3 eor $CAAA,x sta ($56),y eor $40 sta $40 iny lda $C0EC bpl $CCB2 eor $CABA,x sta ($56),y eor $40 sta $40 iny lda $C0EC bpl $CCC1 eor $CACA,x sta ($56),y eor $40 sta $40 iny bne $CCD4 inc $57 ldx $59 lda $C0EC bpl $CCD6 eor $CAAA,x sta ($56),y eor $40 sta $40 iny lda $C0EC bpl $CCE5 eor $CABA,x sta ($56),y eor $40 sta $40 iny lda $C0EC bpl $CCF4 eor $CACA,x sta ($56),y eor $40 sta $40 iny dec $4B beq $CD0A jmp $CC7D lda $C0EC bpl $CD0A sta $59 pla sta $4B lda $C0EC bpl $CD14 sec rol a and $59 eor $40 ldy $C0EC bpl $CD1F cpy #$C8 bne $CD44 ldx $4C beq $CD34 ldy #$00 eor ($54),y iny dex bne $CD2E tax bne $CD48 lda $C0ED lda $C0EE bmi $CD3A lda $C0E0 clc rts lda #$20 bne $CD4A lda #$10 sec rts bcc $CD51 jmp $C523 lda #$40 .byte $1C sei .byte $04 cld txa tay lda $0473,y bmi $CD6F pla sta $05F3,y clc adc #$03 tax pla sta $0673,y adc #$00 pha txa pha jsr $CC36 php sei ldx #$1B lda $40,x pha dex bpl $CD76 sty $58 lda $43 rol a php rol a rol a plp rol a and #$03 eor #$02 cpy #$04 bcs $CD90 eor #$02 tax inx stx $43 lda $0473,y bpl $CD9C jmp $CE40 lda $05F3,y sta $54 lda $0673,y sta $55 ldy #$01 lda ($54),y sta $42 iny lda ($54),y tax iny lda ($54),y sta $55 stx $54 lda #$01 ldx $42 cpx #$0A bcc $CDC2 jmp $CF17 ldy #$00 lda ($54),y sta $5A ldy #$08 lda ($54),y sta $0042,y dey bne $CDCA lda $43 bne $CE40 ldx $42 lda $CF8E,x and #$7F tay lda #$04 cpy $5A bne $CDBF cpx #$05 bne $CDF2 lda #$00 jsr $CF98 lda #$00 jmp $CF39 txa bne $CE19 lda #$21 ldx $46 bne $CDBF txa ldx $58 ldy #$07 sta ($44),y dey bne $CE00 lda $06F9,x sta ($44),y iny lda $04F9 sta ($44),y lda #$08 dey jsr $CFF0 jmp $CDED cmp #$04 bne $CE28 ldx $46 beq $CE2C dex beq $CE38 lda #$21 bne $CDBF lda #$11 bne $CDBF lda #$C0 sta $05F9 lda #$0F .byte $0C txs cpy #$D0 ora $A9 ora ($1C,x) txs cpy #$4C sbc $A9CD plp ldy $58 ldx $06F9,y cpx $43 bcc $CE26 lda #$09 sta $4D lda #$00 sta $4E sta $55 lda #$42 sta $54 ldx $58 lda $0473,x bpl $CE73 ldx $42 lda $CF8E,x and #$7F sta $5A lda #$00 sta $48 lda $42 bne $CE73 sta $46 lda $5A ldx $43 stx $5A sta $43 lda #$80 sta $5B jsr $CA87 jsr $CAE9 bcs $CECD lda $44 sta $54 lda $45 sta $55 ldx $42 lda $CF8E,x bpl $CED1 cpx #$04 bne $CEB2 ldy #$01 lda ($54),y tax dey lda ($54),y pha clc lda #$02 adc $54 sta $54 pla bcc $CEC0 inc $55 jmp $CEC0 cpx #$02 bne $CEBC lda #$00 ldx #$02 bne $CEC0 ldx $47 lda $46 stx $4E sta $4D lda #$82 sta $5B jsr $CADA bcc $CED1 lda #$06 bne $CF17 ldy $58 lda $0473,y bpl $CEE4 lda $42 bne $CEE4 lda #$45 ldx #$00 sta $54 stx $55 jsr $CB30 bcs $CECD jsr $CC51 jsr $CFF0 lda $42 bne $CF15 ldx $58 lda $0473,x bpl $CF15 lda $46 sta $05F3,x lda $47 sta $0673,x lda $45 lsr a lsr a lsr a bcc $CF0F lda #$2B bra $CF17 lsr a lsr a lda #$2F bcc $CF17 lda $4D ldy $58 sta $04F3,y tax beq $CF39 ldx $0473,y bpl $CF39 ldx #$00 cmp #$40 bcs $CF38 ldx #$27 cmp #$2B beq $CF39 cmp #$28 beq $CF39 cmp #$2F beq $CF39 txa ldy $58 sta $0573,y lda $C0E8 bit $C0ED lda #$2B sta $C0EF nop nop nop nop lda $C0EE and #$20 bne $CF4D ldy #$00 ldx #$60 jsr $CC20 lda $C0EC lda $C0E2 lda $C0E6 ldy $58 ldx #$00 pla sta $40,x inx cpx #$1C bcc $CF68 plp lda $05F3,y tax lda $0573,y pha lda $0673,y tay clc pla beq $CF82 sec php bit $0478 bvs $CF8C plp jmp $C784 plp rts .byte $03 .byte $03 .byte $83 ora ($83,x) ora ($01,x) ora ($03,x) .byte $83 pha jsr $CA5D pla tax lda $42 pha lda $43 pha lda $46 pha stx $46 lda #$05 sta $42 lda #$00 sta $5A lda #$02 sta $43 lda #$42 sta $54 lda #$00 sta $55 lda #$80 sta $5B jsr $CA87 inc $5A lda #$09 sta $4D lda #$00 sta $4E jsr $C883 bcc $CFD8 dec $5A jmp $CFDF jsr $C9E3 lda $4D beq $CFC4 lda $5A ldy $58 sta $06F9,y pla sta $46 pla sta $43 pla sta $42 rts ldx $58 sta $05F3,x tya sta $0673,x rts brk brk brk brk brk brk pha bit $03B8,x bmi $D022 ldy $0638,x beq $D01F eor $0638,x asl a bne $D01F ldy $07FB sty $0679 ldy #$BF sty $07FB jmp $D0B5 sec pla rts ldy $C142,x and #$5F pha lda $03B8,x bit #$08 bne $D032 pla bra $D084 pla pha cmp #$00 bne $D03C clc pla bra $D020 lda $03B8,x pha and #$07 sta $06F8 pla and #$F0 sta $03B8,x pla phx ldx $06F8 cmp #$45 beq $D0C5 cmp #$44 beq $D0C7 plx phx cmp $0638,x php ldx $06F8 plp beq $D077 cmp #$0D beq $D07F plx lda $0679 sta $07FB asl $03B8,x lsr $03B8,x bra $D01F plx phx inc $03B8,x ldx $06F8 lda $D225,x bra $D08F phx ldx #$04 cmp $D225,x beq $D0FD dex bpl $D087 ldx #$0C cmp $D218,x beq $D10A dex bpl $D091 plx pla pha and #$7F cmp #$20 bcs $D0A5 sta $0638,x eor #$30 cmp #$0A bcs $D0DE ldy #$0A adc $077E dey bne $D0AD bra $D0BF lda $03B8,x and #$C0 sta $03B8,x lda #$00 sta $077E sec bra $D0EA sec bcc $D0E0 php cpx #$00 beq $D0F4 cpx #$04 beq $D112 txa clc asl a adc #$03 tax plp bcs $D0DB inx jmp $D139 lda $03B8,x lsr a bcs $D0B5 lda $0679 sta $07FB php asl $03B8,x plp ror $03B8,x pla rts lda #$4C plp bcs $D08F lda #$4B bra $D08F txa plx ora $03B8,x ora #$08 sta $03B8,x sec bra $D0EA lda #$D1 pha lda $D1F5,x pha rts plp plx bcs $D11B stz $04B8,x bra $D0DE ldy $D186,x jsr $D22A sta $04B8,x bra $D0DE plx stz $04B8,x lda #$00 jmp $D0A2 ply lda $077E beq $D13A sta $04B8,y beq $D1B4 lda $06B8,y and $D202,x ora $D20D,x sta $06B8,y tya tax jmp $D0DE dey lda #$1F sec bcc $D0FA beq $D16B and $BFFB,y sta $06F8 plx lda $077E and #$0F bcc $D166 asl a asl a asl a asl a asl a ora $06F8 iny bra $D183 lda $BFFA,y pha ora #$0C sta $BFFA,y lda #$E9 ldx #$53 pha pla dex bne $D179 dec a bne $D177 pla plx sta $BFFA,y bra $D148 sta $BFF9,y lda $067B asl a jsr $C797 bcc $D197 jsr $C79D clc bcs $D1D2 plx jsr $D1A0 bra $D148 lda $03B8,x bit #$40 bcc $D1B9 bne $D1C9 cpx $39 bne $D1F4 ora #$40 ldy $0679 sty $067A ldy #$DF bra $D1C0 beq $D1C9 and #$BF ldy $067A sta $03B8,x sty $0679 sty $07FB ldy $C142,x cli php sei lda $BFFA,y ora #$02 bcc $D1D8 and #$FD sta $BFFA,y lda #$00 ror a sta $05FA bpl $D1EA stz $057C stz $067C txa sta $04FC plp stx $05FC stx $06FC rts sec sec sec rol $4F2E .byte 'K' lsr a stx $87,y .byte 'k' tya and $7F .byte $BF .byte $BF .byte $7F .byte $FF .byte $DF .byte $DF .byte $EF .byte $EF .byte $F7 .byte $F7 bra $D20F rti brk brk jsr $0000 bpl $D217 php eor #$4B jmp $0D4E .byte 'B' .byte 'D' bvc $D272 eor ($53) .byte 'T' phy jmp $4658 eor $AD43 .byte $13 cpy #$0A lda $C018 php sta $C000 sta $C003 lda $0478,y plp bcs $D241 sta $C002 bpl $D246 sta $C001 rts .byte $03 .byte $07 .res 439 sta ($28),y lda #$05 sta $38 lda $C000 asl a php sei jsr $D679 ldy #$05 ldx $057F lda $047F jsr $D441 ldy #$0C ldx $05FF lda $04FF jsr $D441 lda $077F rol a rol a rol a and #$03 eor #$03 inc a plp ldy #$10 jsr $D452 ply ldx #$11 lda #$8D sta $0200,x jmp $C784 cpx #$80 bcc $D452 eor #$FF adc #$00 pha txa eor #$FF adc #$00 tax pla sec sta $0214 stx $0215 lda #$2B bcc $D45E lda #$2D pha lda #$2C sta $0201,y ldx #$11 lda #$00 clc rol a cmp #$0A bcc $D470 sbc #$0A rol $0214 rol $0215 dex bne $D469 ora #$30 sta $0200,y dey beq $D489 cpy #$07 beq $D489 cpy #$0E bne $D464 pla sta $0200,y rts sta $C050 sta $C078 sta $C05F ldy #$04 ldx #$00 clc adc $C82A,y sta $00,x inx bne $D49B clc adc $C82A,y cmp $00,x bne $D4BC inx bne $D4A4 ror a bit $C019 bpl $D4B7 eor #$A5 dey bpl $D49B bmi $D4C2 eor $00,x clc jmp $C473 jmp $C3C6 jsr $C79D pla ply pla lda #$FF tax inx eor $D4DA,x sta $0200,x bpl $D4CE jmp $C784 lda $0A3B .byte $0B pha .byte 'w' rol a:$0005,x ora $08 .byte $0C asl $6553,x .byte $37 .byte $1C .byte $07 .byte $0C eor $62 .byte $27 brk .byte $17 .byte $1C .byte $07 .byte $07 ora $4B adc $0224 asl $6145 and ($18) .byte $02 .byte $07 ora $6A53,x .byte $2B .byte $0C php asl $53,x pla and $0706,x .byte $1B ora ($E3,x) .res 240 stz $077F ldx #$80 ldy #$01 stz $047D,x stz $057D,x lda #$FF sta $067D,x lda #$03 sta $077D,x ldx #$00 dey bpl $D607 jsr $D651 lda #$00 tax jsr $C746 txa sta $0478 lsr a ora $0478 cmp #$10 bcs $D650 and #$05 beq $D636 cli adc #$55 php sei stx $07FF sta $C079 ldx #$08 dex asl a bcc $D649 sta $C058,x bne $D642 sta $C078 plp clc rts ldx #$80 bra $D657 ldx #$00 lda $047D,x sta $047F,x lda $057D,x sta $057F,x dex bpl $D655 bra $D674 stz $047F stz $057F stz $04FF stz $05FF stz $067F clc rts lda #$20 .byte $1C .byte $7F .byte $07 and $067F .byte $1C .byte $7F asl $2C .byte $FF .byte $07 bmi $D69C bit $C063 bmi $D690 ora #$80 bit $077F bpl $D697 ora #$40 sta $077F clc rts ora $077F and #$E0 bra $D697 ror a ror a and #$80 tax lda $0478 sta $047D,x lda $0578 sta $057D,x lda $04F8 sta $067D,x lda $05F8 sta $077D,x clc rts pha clc lda #$0E and $077F bne $D6CC sec pla rts .res 306 sta $42 ldy #$C4 sty $07F8 ldx #$C8 stx $0778 lda #$00 sta $04F8 jsr $D9DD ldy $42 lda $C680,y bmi $D81F cmp $43 bne $D834 lda #$D8 bra $D824 brk pha lda $C69A,y pha ldy $07F8 ldx $0778 rts lda #$01 bne $D836 lda #$04 sta $04F8 rts jmp $C580 jmp $C5F7 jmp $D959 jmp $DB3A lda $03B8,y lsr a sta $05F8 lda #$00 sta $0578 rts lda $47 bne $D878 sta $05F8 ldy #$08 sty $0578 dey sta ($45),y dey bne $D860 phy ldy $07F8 lda $03B8,y beq $D870 lda #$01 ply sta ($45),y rts lda $47 beq $D87D lda #$21 sta $04F8 rts lda #$04 ldx $47 beq $D88A cpx #$03 bne $D878 lda #$19 sta $0578 ldx #$00 stx $05F8 tay dey lda $C667,y sta ($45),y dey bpl $D894 ldy $07F8 lda $03B8,y lsr a ldy #$02 sta ($45),y rts bit $D839 bvc $D865 lda $47 sta $48 lda $46 sta $47 lda $45 sta $46 lda $44 sta $45 lda #$00 sta $49 beq $D8C8 bit $D839 bvc $D880 lda $47 asl a sta $4A lda $48 rol a sta $4B bcs $D8F3 lda $49 bne $D8F3 sta $49 sta $47 lda #$02 sta $48 lda $C014 bvs $D8E8 lda $C013 and #$80 ora $4B sta $4B bvs $D8F6 jmp $C5F7 jmp $C5EE jmp $C580 ldy #$C4 sty $07F8 ldx #$C8 stx $0778 cmp $07F8 bne $D911 lda $BF00 beq $D911 cmp #$4C bne $D931 stz $0801 lda $06B8,y cmp #$A5 bne $D92C ldy #$03 lda $D92D,y sta $0044,y dey bpl $D91D ldy $07F8 jsr $D8A8 rts brk php brk brk lda #$4C sta $BD00 lda #$D1 sta $BD01 sty $BD02 lda #$C3 sta $9D1E lda #$A6 sta $9D1F pla pla plx inc $C000,x plx pla pla ldx #$00 lda #$98 jmp $C784 rts ldy #$02 lda ($48),y cmp #$01 beq $D964 jmp $D830 ldy #$04 lda ($48),y lsr a ror $4A lsr a ror $4A lsr a sta $4B lda $4A ror a and #$E0 iny ora ($48),y sta $4A ldy #$08 lda ($48),y sta $45 iny lda ($48),y sta $46 ldy #$0C lda ($48),y beq $D958 and #$03 beq $D961 ora #$11 tay ldx #$00 stx $47 stx $49 inx stx $48 jmp $D81F lda #$00 sta $BFF8,x sta $BFF9,x lda #$10 sec sbc #$01 sta $BFFA,x lda $BFFB,x pha dec $BFF8,x lda #$A5 sta $BFFB,x dec $BFF8,x eor $BFFB,x dec $BFF8,x cmp #$01 pla sta $BFFB,x lda $BFFA,x and #$0F beq $D9D5 bcs $D9AA adc #$01 sta $03B8,y lsr a sta $0478 rts ldy $07F8 lda #$A5 cmp $06B8,y beq $DA12 sta $06B8,y cmp #$05 php jsr $D99F plp beq $DA12 lda $BF00 beq $DA13 cmp #$4C bne $DA19 ldy #$FF jsr $DA43 lda #$01 ldy #$20 sta $BFFB,x ora #$FF dey bne $DA05 dec $0478 bne $DA03 rts ldy #$78 jsr $DA43 rts ldy #$2C jsr $DA43 lda #$44 sta $BFF8,x lda $0478 ldy #$72 cmp #$04 bcc $DA2E ldy #$BA lda $BFF8,x cmp #$7C bne $DA3A lda #$7E sta $BFF8,x lda #$FF sta $BFFB,x dey bne $DA2E rts lda #$00 sta $BFF8,x sta $BFF9,x sta $BFFA,x sta $BFFB,x lda $BFF9,x and #$F0 beq $DA4E lda #$04 sta $BFF9,x iny lda $DAB1,y cmp #$FD beq $DA81 cmp #$FE beq $DA87 cmp #$FC bne $DA72 lda $0478 bne $DA7B cmp #$AA bne $DA7B lda $07F8 eor #$F0 sta $BFFB,x jmp $DA5D iny lda $DAB1,y beq $DA98 pha lda #$00 sta $BFFB,x pla sec sbc #$01 bne $DA87 beq $DA5D sta $BFFB,x cmp $BFF8,x bne $DA95 iny lda $DAB1,y beq $DAB0 sta $BFF9,x iny lda $DAB1,y sta $BFFA,x jmp $DA5D rts brk brk .byte $03 brk .byte $F4 eor ($41) eor $FDAA ora $27C3,y ora a:$0000 asl $00 brk .byte $FC sbc $FED7,x .byte $02 brk .byte $04 brk inc $03FE,x brk ora $00 inc $04FE,x brk brk inc a:$00FD,x brk brk brk brk sbc $2000,x .byte $02 .byte $02 ora ($0F),y .byte $04 brk brk .byte $FB sbc $7A20,x sbc $FF08,x .byte $FF .byte $FF .byte $FF and ($20) brk ora ($FD,x) .byte $CB inc $0111,x inc $0211,x inc $0311,x inc $0411,x inc $0511,x inc $0611,x inc $0711,x inc $0811,x inc $0911,x inc $0A11,x inc $0B11,x inc $0C11,x inc $0D11,x inc $0E11,x inc a:$00FD,x jsr $FD02 brk brk brk brk asl $FD .byte $03 .byte $04 eor ($41) eor $FDAA .byte $04 .byte $FC sbc a:$0000,x ldx #$00 lda $DC00,x sta $2000,x lda $DD00,x sta $2100,x lda $DE00,x sta $2200,x lda $DF00,x sta $2300,x inx bne $DB3C ldx $0778 lda #$1F pha lda #$FF pha jmp $C784 .res 157 lda #$00 sta $49 sta $4A sta $0438,y sta $04B8,y lda $03B8,y and #$0F sta $46 jsr $FC58 lda #$08 jsr $221D lda $46 lsr a lsr a pha ora #$04 jsr $221D lda #$09 jsr $221D pla jsr $221D jsr $FD8E lda #$05 sta $25 jsr $FD8E lda #$10 jsr $221D lda $4A jsr $FDDA lda $49 jsr $FDDA jsr $220B lda #$01 sta $00 ldy #$05 lda $22F4,y jsr $2213 cmp $BFF8,x bne $DC6C cmp $BFF9,x bne $DC6C ora #$F0 cmp $BFFA,x bne $DC6C dey bpl $DC50 bmi $DC6F jmp $2197 inc $00 dec $BFF8,x lda $BFFB,x sta $BFFB,x lda $BFFA,x and #$0F ora $BFF9,x ora $BFF8,x beq $DC8A jmp $2197 inc $00 lda #$01 sta $45 txa clc adc #$F8 sta $42 lda #$C0 sta $43 lda $46 beq $DCA2 cmp #$0C bne $DCA4 lda #$10 lsr a pha ldy #$02 pha jsr $2211 pla sta ($42),y pha lda $45 sta $BFFB,x inc $45 pla lsr a bne $DCA8 sta ($42),y ror a dey bpl $DCA8 lda #$01 sta $45 pla ldy #$02 pha jsr $2211 pla sta ($42),y sta $47 lda $BFFB,x cmp $45 bne $DCE7 inc $45 lda $47 lsr a bne $DCC8 sta ($42),y ror a dey bpl $DCC8 bmi $DCEA jmp $2197 jsr $2211 inc $00 sta $45 lda $45 sta $BFFB,x sta $BFFB,x sta $BFFB,x sta $BFFB,x lda $BFF8,x bne $DCF1 ora $BFF9,x bne $DCF1 jsr $21E4 bne $DCF1 jsr $220B lda $BFFB,x cmp $45 bne $DCE7 lda $BFFB,x cmp $45 bne $DCE7 lda $BFF8,x bne $DD11 ora $BFF9,x bne $DD11 jsr $21E4 bne $DD11 jsr $220B lda $45 eor #$FF bne $DCED inc $00 lda #$55 sta $45 jsr $21FD clc adc $47 adc $45 sta $BFFB,x sta $45 lda $BFF8,x bne $DD40 lda $BFF9,x bne $DD3D jsr $21E4 bne $DD3D jsr $220B lda #$55 sta $45 jsr $21FD clc adc $47 adc $45 sta $45 lda $BFFB,x cmp $45 bne $DD97 lda $BFF8,x bne $DD63 lda $BFF9,x bne $DD60 jsr $21E4 bne $DD60 lda #$0B jsr $221D sed lda $49 clc adc #$01 sta $49 lda $4A adc #$00 sta $4A cld jmp $2031 pha jsr $FC42 lda #$0A jsr $221D lda $00 cmp #$03 bcs $DDAF pla lda #$0C jsr $221D jmp $21DE lda #$0D jsr $221D sec lda $BFF8,x sbc #$01 pha lda $BFF9,x sbc #$00 pha lda $BFFA,x and #$0F sbc #$00 jsr $FDDA pla jsr $FDDA pla jsr $FDDA lda #$0E jsr $221D pla eor $45 jsr $FDDA lda #$0F jsr $221D rts lda #$AE jsr $FDED lda $C000 cmp #$9B bne $DDF5 pla pla sta $C010 lda $BFFA,x and #$0F cmp $46 rts clc lda $BFF9,x adc $BFFA,x adc #$55 sta $47 lda #$00 rts jsr $FD8E jsr $FC9C lda #$00 sta $BFF8,x sta $BFF9,x sta $BFFA,x rts tay lda $2230,y tay lda $2241,y pha ora #$80 jsr $FDED iny pla bpl $DE22 rts brk ora $09 ora $1411 asl $18,x .byte $1B .byte 'G' .byte '\' adc $8477 .byte $8F sta ($AA) and ($20),y eor $C745 and ($35) rol $CB,x and $31,x and ($CB) .byte $37 rol $38,x .byte $CB and ($38),y bcs $DE8A lda $39,x bcs $DE8B .byte $33 lda $4D,x eor $4D .byte 'O' eor ($59) jsr $4143 eor ($44) jsr $4554 .byte 'S' .byte 'T' ora $5345 .byte 'C' jsr $4F54 jsr $5845 eor #$54 ora $4554 .byte 'S' .byte 'T' jsr $4957 jmp $204C .byte 'T' eor ($4B,x) eor $A0 jsr $4553 .byte 'C' .byte 'O' lsr $5344 ora $4143 eor ($44) jsr $4953 phy eor $20 and $0DA0,x ora $4143 eor ($44) jsr $4146 eor #$4C eor $44 ora $0707 .byte $87 ora $430D eor ($52,x) .byte 'D' jsr $4B4F sta $4441 .byte 'D' eor ($45) .byte 'S' .byte 'S' jsr $5245 eor ($4F) cmp ($44) eor ($54,x) eor ($20,x) eor $52 eor ($4F) eor ($A0) jsr $A02D ora $4553 eor $20 .byte 'D' eor $41 jmp $5245 jsr $4F46 eor ($20) .byte 'S' eor $52 lsr $49,x .byte 'C' eor $8D bvc $DF2E .byte 'S' .byte 'S' eor $53 jsr $A03D .byte $FF cpy $55AA .byte $33 brk eor ($69) .byte 'c' pla jsr $6957 jmp ($696C) adc ($6D,x) .byte 's' .byte 'c' .byte 'o' bvs $DF84 adc ($69) .byte 'g' pla stz $20,x and ($39),y sec rol $20,x eor ($70,x) bvs $DF86 adc $20 .byte 'C' .byte 'o' adc $7570 stz $65,x adc ($20) eor #$6E .byte 'c' rol $6C61 jmp ($7220) adc #$67 pla stz $73,x jsr $6572 .byte 's' adc $72 ror $65,x stz $00 .res 8381 .word $C788 .word $C788 .word $C78E .endif ; .if ROMVER = 255

{ "language": "Assembly" }

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{ "language": "Assembly" }

/// /// Perform several driver tests for OpenMP offloading /// // REQUIRES: clang-driver // REQUIRES: x86-registered-target // REQUIRES: powerpc-registered-target // REQUIRES: nvptx-registered-target /// ########################################################################### /// Check whether an invalid OpenMP target is specified: // RUN: %clang -### -fopenmp=libomp -fopenmp-targets=aaa-bbb-ccc-ddd %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-INVALID-TARGET %s // CHK-INVALID-TARGET: error: OpenMP target is invalid: 'aaa-bbb-ccc-ddd' /// ########################################################################### /// Check warning for empty -fopenmp-targets // RUN: %clang -### -fopenmp=libomp -fopenmp-targets= %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-EMPTY-OMPTARGETS %s // CHK-EMPTY-OMPTARGETS: warning: joined argument expects additional value: '-fopenmp-targets=' /// ########################################################################### /// Check error for no -fopenmp option // RUN: %clang -### -fopenmp-targets=powerpc64le-ibm-linux-gnu %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-NO-FOPENMP %s // RUN: %clang -### -fopenmp=libgomp -fopenmp-targets=powerpc64le-ibm-linux-gnu %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-NO-FOPENMP %s // CHK-NO-FOPENMP: error: The option -fopenmp-targets must be used in conjunction with a -fopenmp option compatible with offloading, please use -fopenmp=libomp or -fopenmp=libiomp5. /// ########################################################################### /// Check warning for duplicate offloading targets. // RUN: %clang -### -ccc-print-phases -fopenmp=libomp -fopenmp-targets=powerpc64le-ibm-linux-gnu,powerpc64le-ibm-linux-gnu %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-DUPLICATES %s // CHK-DUPLICATES: warning: The OpenMP offloading target 'powerpc64le-ibm-linux-gnu' is similar to target 'powerpc64le-ibm-linux-gnu' already specified - will be ignored. /// ########################################################################### /// Check -Xopenmp-target=powerpc64le-ibm-linux-gnu -mcpu=pwr7 is passed when compiling for the device. // RUN: %clang -### -no-canonical-prefixes -fopenmp=libomp -fopenmp-targets=powerpc64le-ibm-linux-gnu -Xopenmp-target=powerpc64le-ibm-linux-gnu -mcpu=pwr7 %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FOPENMP-EQ-TARGET %s // CHK-FOPENMP-EQ-TARGET: clang{{.*}} "-target-cpu" "pwr7" {{.*}}"-fopenmp-is-device" /// ########################################################################### /// Check -Xopenmp-target -mcpu=pwr7 is passed when compiling for the device. // RUN: %clang -### -no-canonical-prefixes -fopenmp=libomp -fopenmp-targets=powerpc64le-ibm-linux-gnu -Xopenmp-target -mcpu=pwr7 %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FOPENMP-TARGET %s // CHK-FOPENMP-TARGET: clang{{.*}} "-target-cpu" "pwr7" {{.*}}"-fopenmp-is-device" /// ########################################################################## /// Check -mcpu=pwr7 is passed to the same triple. // RUN: %clang -### -no-canonical-prefixes -fopenmp=libomp -fopenmp-targets=powerpc64le-ibm-linux-gnu -target powerpc64le-ibm-linux-gnu -mcpu=pwr7 %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FOPENMP-MCPU-TO-SAME-TRIPLE %s // CHK-FOPENMP-MCPU-TO-SAME-TRIPLE: clang{{.*}} "-target-cpu" "pwr7" {{.*}}"-fopenmp-is-device" /// ########################################################################## /// Check -march=pwr7 is NOT passed to nvptx64-nvidia-cuda. // RUN: %clang -### -no-canonical-prefixes -fopenmp=libomp -fopenmp-targets=nvptx64-nvidia-cuda -target powerpc64le-ibm-linux-gnu -march=pwr7 %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FOPENMP-MARCH-TO-GPU %s // CHK-FOPENMP-MARCH-TO-GPU-NOT: clang{{.*}} "-target-cpu" "pwr7" {{.*}}"-fopenmp-is-device" /// ########################################################################### /// Check -march=pwr7 is NOT passed to x86_64-unknown-linux-gnu. // RUN: %clang -### -no-canonical-prefixes -fopenmp=libomp -fopenmp-targets=x86_64-unknown-linux-gnu -target powerpc64le-ibm-linux-gnu -march=pwr7 %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FOPENMP-MARCH-TO-X86 %s // CHK-FOPENMP-MARCH-TO-X86-NOT: clang{{.*}} "-target-cpu" "pwr7" {{.*}}"-fopenmp-is-device" /// ########################################################################### /// Check -Xopenmp-target triggers error when multiple triples are used. // RUN: %clang -### -no-canonical-prefixes -fopenmp=libomp -fopenmp-targets=powerpc64le-ibm-linux-gnu,powerpc64le-unknown-linux-gnu -Xopenmp-target -mcpu=pwr8 %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FOPENMP-TARGET-AMBIGUOUS-ERROR %s // CHK-FOPENMP-TARGET-AMBIGUOUS-ERROR: clang{{.*}} error: cannot deduce implicit triple value for -Xopenmp-target, specify triple using -Xopenmp-target=<triple> /// ########################################################################### /// Check -Xopenmp-target triggers error when an option requiring arguments is passed to it. // RUN: %clang -### -no-canonical-prefixes -fopenmp=libomp -fopenmp-targets=powerpc64le-ibm-linux-gnu -Xopenmp-target -Xopenmp-target -mcpu=pwr8 %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FOPENMP-TARGET-NESTED-ERROR %s // CHK-FOPENMP-TARGET-NESTED-ERROR: clang{{.*}} error: invalid -Xopenmp-target argument: '-Xopenmp-target -Xopenmp-target', options requiring arguments are unsupported /// ########################################################################### /// Check the phases graph when using a single target, different from the host. /// We should have an offload action joining the host compile and device /// preprocessor and another one joining the device linking outputs to the host /// action. // RUN: %clang -ccc-print-phases -fopenmp=libomp -target powerpc64le-ibm-linux-gnu -fopenmp-targets=x86_64-pc-linux-gnu %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-PHASES %s // CHK-PHASES: 0: input, "[[INPUT:.+\.c]]", c, (host-openmp) // CHK-PHASES: 1: preprocessor, {0}, cpp-output, (host-openmp) // CHK-PHASES: 2: compiler, {1}, ir, (host-openmp) // CHK-PHASES: 3: backend, {2}, assembler, (host-openmp) // CHK-PHASES: 4: assembler, {3}, object, (host-openmp) // CHK-PHASES: 5: linker, {4}, image, (host-openmp) // CHK-PHASES: 6: input, "[[INPUT]]", c, (device-openmp) // CHK-PHASES: 7: preprocessor, {6}, cpp-output, (device-openmp) // CHK-PHASES: 8: compiler, {7}, ir, (device-openmp) // CHK-PHASES: 9: offload, "host-openmp (powerpc64le-ibm-linux-gnu)" {2}, "device-openmp (x86_64-pc-linux-gnu)" {8}, ir // CHK-PHASES: 10: backend, {9}, assembler, (device-openmp) // CHK-PHASES: 11: assembler, {10}, object, (device-openmp) // CHK-PHASES: 12: linker, {11}, image, (device-openmp) // CHK-PHASES: 13: offload, "host-openmp (powerpc64le-ibm-linux-gnu)" {5}, "device-openmp (x86_64-pc-linux-gnu)" {12}, image /// ########################################################################### /// Check the phases when using multiple targets. Here we also add a library to /// make sure it is treated as input by the device. // RUN: %clang -ccc-print-phases -lsomelib -fopenmp=libomp -target powerpc64-ibm-linux-gnu -fopenmp-targets=x86_64-pc-linux-gnu,powerpc64-ibm-linux-gnu %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-PHASES-LIB %s // CHK-PHASES-LIB: 0: input, "somelib", object, (host-openmp) // CHK-PHASES-LIB: 1: input, "[[INPUT:.+\.c]]", c, (host-openmp) // CHK-PHASES-LIB: 2: preprocessor, {1}, cpp-output, (host-openmp) // CHK-PHASES-LIB: 3: compiler, {2}, ir, (host-openmp) // CHK-PHASES-LIB: 4: backend, {3}, assembler, (host-openmp) // CHK-PHASES-LIB: 5: assembler, {4}, object, (host-openmp) // CHK-PHASES-LIB: 6: linker, {0, 5}, image, (host-openmp) // CHK-PHASES-LIB: 7: input, "somelib", object, (device-openmp) // CHK-PHASES-LIB: 8: input, "[[INPUT]]", c, (device-openmp) // CHK-PHASES-LIB: 9: preprocessor, {8}, cpp-output, (device-openmp) // CHK-PHASES-LIB: 10: compiler, {9}, ir, (device-openmp) // CHK-PHASES-LIB: 11: offload, "host-openmp (powerpc64-ibm-linux-gnu)" {3}, "device-openmp (x86_64-pc-linux-gnu)" {10}, ir // CHK-PHASES-LIB: 12: backend, {11}, assembler, (device-openmp) // CHK-PHASES-LIB: 13: assembler, {12}, object, (device-openmp) // CHK-PHASES-LIB: 14: linker, {7, 13}, image, (device-openmp) // CHK-PHASES-LIB: 15: input, "somelib", object, (device-openmp) // CHK-PHASES-LIB: 16: input, "[[INPUT]]", c, (device-openmp) // CHK-PHASES-LIB: 17: preprocessor, {16}, cpp-output, (device-openmp) // CHK-PHASES-LIB: 18: compiler, {17}, ir, (device-openmp) // CHK-PHASES-LIB: 19: offload, "host-openmp (powerpc64-ibm-linux-gnu)" {3}, "device-openmp (powerpc64-ibm-linux-gnu)" {18}, ir // CHK-PHASES-LIB: 20: backend, {19}, assembler, (device-openmp) // CHK-PHASES-LIB: 21: assembler, {20}, object, (device-openmp) // CHK-PHASES-LIB: 22: linker, {15, 21}, image, (device-openmp) // CHK-PHASES-LIB: 23: offload, "host-openmp (powerpc64-ibm-linux-gnu)" {6}, "device-openmp (x86_64-pc-linux-gnu)" {14}, "device-openmp (powerpc64-ibm-linux-gnu)" {22}, image /// ########################################################################### /// Check the phases when using multiple targets and multiple source files // RUN: echo " " > %t.c // RUN: %clang -ccc-print-phases -lsomelib -fopenmp=libomp -target powerpc64-ibm-linux-gnu -fopenmp-targets=x86_64-pc-linux-gnu,powerpc64-ibm-linux-gnu %s %t.c 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-PHASES-FILES %s // CHK-PHASES-FILES: 0: input, "somelib", object, (host-openmp) // CHK-PHASES-FILES: 1: input, "[[INPUT1:.+\.c]]", c, (host-openmp) // CHK-PHASES-FILES: 2: preprocessor, {1}, cpp-output, (host-openmp) // CHK-PHASES-FILES: 3: compiler, {2}, ir, (host-openmp) // CHK-PHASES-FILES: 4: backend, {3}, assembler, (host-openmp) // CHK-PHASES-FILES: 5: assembler, {4}, object, (host-openmp) // CHK-PHASES-FILES: 6: input, "[[INPUT2:.+\.c]]", c, (host-openmp) // CHK-PHASES-FILES: 7: preprocessor, {6}, cpp-output, (host-openmp) // CHK-PHASES-FILES: 8: compiler, {7}, ir, (host-openmp) // CHK-PHASES-FILES: 9: backend, {8}, assembler, (host-openmp) // CHK-PHASES-FILES: 10: assembler, {9}, object, (host-openmp) // CHK-PHASES-FILES: 11: linker, {0, 5, 10}, image, (host-openmp) // CHK-PHASES-FILES: 12: input, "somelib", object, (device-openmp) // CHK-PHASES-FILES: 13: input, "[[INPUT1]]", c, (device-openmp) // CHK-PHASES-FILES: 14: preprocessor, {13}, cpp-output, (device-openmp) // CHK-PHASES-FILES: 15: compiler, {14}, ir, (device-openmp) // CHK-PHASES-FILES: 16: offload, "host-openmp (powerpc64-ibm-linux-gnu)" {3}, "device-openmp (x86_64-pc-linux-gnu)" {15}, ir // CHK-PHASES-FILES: 17: backend, {16}, assembler, (device-openmp) // CHK-PHASES-FILES: 18: assembler, {17}, object, (device-openmp) // CHK-PHASES-FILES: 19: input, "[[INPUT2]]", c, (device-openmp) // CHK-PHASES-FILES: 20: preprocessor, {19}, cpp-output, (device-openmp) // CHK-PHASES-FILES: 21: compiler, {20}, ir, (device-openmp) // CHK-PHASES-FILES: 22: offload, "host-openmp (powerpc64-ibm-linux-gnu)" {8}, "device-openmp (x86_64-pc-linux-gnu)" {21}, ir // CHK-PHASES-FILES: 23: backend, {22}, assembler, (device-openmp) // CHK-PHASES-FILES: 24: assembler, {23}, object, (device-openmp) // CHK-PHASES-FILES: 25: linker, {12, 18, 24}, image, (device-openmp) // CHK-PHASES-FILES: 26: input, "somelib", object, (device-openmp) // CHK-PHASES-FILES: 27: input, "[[INPUT1]]", c, (device-openmp) // CHK-PHASES-FILES: 28: preprocessor, {27}, cpp-output, (device-openmp) // CHK-PHASES-FILES: 29: compiler, {28}, ir, (device-openmp) // CHK-PHASES-FILES: 30: offload, "host-openmp (powerpc64-ibm-linux-gnu)" {3}, "device-openmp (powerpc64-ibm-linux-gnu)" {29}, ir // CHK-PHASES-FILES: 31: backend, {30}, assembler, (device-openmp) // CHK-PHASES-FILES: 32: assembler, {31}, object, (device-openmp) // CHK-PHASES-FILES: 33: input, "[[INPUT2]]", c, (device-openmp) // CHK-PHASES-FILES: 34: preprocessor, {33}, cpp-output, (device-openmp) // CHK-PHASES-FILES: 35: compiler, {34}, ir, (device-openmp) // CHK-PHASES-FILES: 36: offload, "host-openmp (powerpc64-ibm-linux-gnu)" {8}, "device-openmp (powerpc64-ibm-linux-gnu)" {35}, ir // CHK-PHASES-FILES: 37: backend, {36}, assembler, (device-openmp) // CHK-PHASES-FILES: 38: assembler, {37}, object, (device-openmp) // CHK-PHASES-FILES: 39: linker, {26, 32, 38}, image, (device-openmp) // CHK-PHASES-FILES: 40: offload, "host-openmp (powerpc64-ibm-linux-gnu)" {11}, "device-openmp (x86_64-pc-linux-gnu)" {25}, "device-openmp (powerpc64-ibm-linux-gnu)" {39}, image /// ########################################################################### /// Check the phases graph when using a single GPU target, and check the OpenMP /// and CUDA phases are articulated correctly. // RUN: %clang -ccc-print-phases -fopenmp=libomp -target powerpc64le-ibm-linux-gnu -fopenmp-targets=nvptx64-nvidia-cuda -x cuda %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-PHASES-WITH-CUDA %s // CHK-PHASES-WITH-CUDA: 0: input, "[[INPUT:.+\.c]]", cuda, (host-cuda-openmp) // CHK-PHASES-WITH-CUDA: 1: preprocessor, {0}, cuda-cpp-output, (host-cuda-openmp) // CHK-PHASES-WITH-CUDA: 2: compiler, {1}, ir, (host-cuda-openmp) // CHK-PHASES-WITH-CUDA: 3: input, "[[INPUT]]", cuda, (device-cuda, sm_20) // CHK-PHASES-WITH-CUDA: 4: preprocessor, {3}, cuda-cpp-output, (device-cuda, sm_20) // CHK-PHASES-WITH-CUDA: 5: compiler, {4}, ir, (device-cuda, sm_20) // CHK-PHASES-WITH-CUDA: 6: backend, {5}, assembler, (device-cuda, sm_20) // CHK-PHASES-WITH-CUDA: 7: assembler, {6}, object, (device-cuda, sm_20) // CHK-PHASES-WITH-CUDA: 8: offload, "device-cuda (nvptx64-nvidia-cuda:sm_20)" {7}, object // CHK-PHASES-WITH-CUDA: 9: offload, "device-cuda (nvptx64-nvidia-cuda:sm_20)" {6}, assembler // CHK-PHASES-WITH-CUDA: 10: linker, {8, 9}, cuda-fatbin, (device-cuda) // CHK-PHASES-WITH-CUDA: 11: offload, "host-cuda-openmp (powerpc64le-ibm-linux-gnu)" {2}, "device-cuda (nvptx64-nvidia-cuda)" {10}, ir // CHK-PHASES-WITH-CUDA: 12: backend, {11}, assembler, (host-cuda-openmp) // CHK-PHASES-WITH-CUDA: 13: assembler, {12}, object, (host-cuda-openmp) // CHK-PHASES-WITH-CUDA: 14: linker, {13}, image, (host-cuda-openmp) // CHK-PHASES-WITH-CUDA: 15: input, "[[INPUT]]", cuda, (device-openmp) // CHK-PHASES-WITH-CUDA: 16: preprocessor, {15}, cuda-cpp-output, (device-openmp) // CHK-PHASES-WITH-CUDA: 17: compiler, {16}, ir, (device-openmp) // CHK-PHASES-WITH-CUDA: 18: offload, "host-cuda-openmp (powerpc64le-ibm-linux-gnu)" {2}, "device-openmp (nvptx64-nvidia-cuda)" {17}, ir // CHK-PHASES-WITH-CUDA: 19: backend, {18}, assembler, (device-openmp) // CHK-PHASES-WITH-CUDA: 20: assembler, {19}, object, (device-openmp) // CHK-PHASES-WITH-CUDA: 21: linker, {20}, image, (device-openmp) // CHK-PHASES-WITH-CUDA: 22: offload, "host-cuda-openmp (powerpc64le-ibm-linux-gnu)" {14}, "device-openmp (nvptx64-nvidia-cuda)" {21}, image /// ########################################################################### /// Check of the commands passed to each tool when using valid OpenMP targets. /// Here we also check that offloading does not break the use of integrated /// assembler. It does however preclude the merge of the host compile and /// backend phases. There are also two offloading specific options: /// -fopenmp-is-device: will tell the frontend that it will generate code for a /// target. /// -fopenmp-host-ir-file-path: specifies the host IR file that can be loaded by /// the target code generation to gather information about which declaration /// really need to be emitted. /// We use -fopenmp-dump-offload-linker-script to dump the linker script and /// check its contents. /// // RUN: %clang -### -fopenmp=libomp -o %t.out -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %s -fopenmp-dump-offload-linker-script -no-canonical-prefixes 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-COMMANDS -check-prefix=CHK-LKS -check-prefix=CHK-LKS-REG %s // RUN: %clang -### -fopenmp=libomp -o %t.out -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %s -save-temps -fopenmp-dump-offload-linker-script -no-canonical-prefixes 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-COMMANDS-ST -check-prefix=CHK-LKS -check-prefix=CHK-LKS-ST %s // Make sure we are not dumping the script unless the user requested it. // RUN: %clang -### -fopenmp=libomp -o %t.out -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %s -no-canonical-prefixes 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-LKS-NODUMP %s // RUN: %clang -### -fopenmp=libomp -o %t.out -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %s -save-temps -no-canonical-prefixes 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-LKS-NODUMP %s // // Check the linker script contains what we expect. // // CHK-LKS: /* // CHK-LKS: OpenMP Offload Linker Script // CHK-LKS: *** Automatically generated by Clang *** // CHK-LKS-NODUMP-NOT: OpenMP Offload Linker Script. // CHK-LKS: */ // CHK-LKS: TARGET(binary) // CHK-LKS-REG: INPUT([[T1BIN:.+\.out]]) // CHK-LKS-REG: INPUT([[T2BIN:.+\.out]]) // CHK-LKS-ST: INPUT([[T1BIN:.+\.out-openmp-powerpc64le-ibm-linux-gnu]]) // CHK-LKS-ST: INPUT([[T2BIN:.+\.out-openmp-x86_64-pc-linux-gnu]]) // CHK-LKS: SECTIONS // CHK-LKS: { // CHK-LKS: .omp_offloading.powerpc64le-ibm-linux-gnu : // CHK-LKS: ALIGN(0x10) // CHK-LKS: { // CHK-LKS: PROVIDE_HIDDEN(.omp_offloading.img_start.powerpc64le-ibm-linux-gnu = .); // CHK-LKS: [[T1BIN]] // CHK-LKS: PROVIDE_HIDDEN(.omp_offloading.img_end.powerpc64le-ibm-linux-gnu = .); // CHK-LKS: } // CHK-LKS: .omp_offloading.x86_64-pc-linux-gnu : // CHK-LKS: ALIGN(0x10) // CHK-LKS: { // CHK-LKS: PROVIDE_HIDDEN(.omp_offloading.img_start.x86_64-pc-linux-gnu = .); // CHK-LKS: [[T2BIN]] // CHK-LKS: PROVIDE_HIDDEN(.omp_offloading.img_end.x86_64-pc-linux-gnu = .); // CHK-LKS: } // CHK-LKS: .omp_offloading.entries : // CHK-LKS: ALIGN(0x10) // CHK-LKS: SUBALIGN(0x01) // CHK-LKS: { // CHK-LKS: PROVIDE_HIDDEN(.omp_offloading.entries_begin = .); // CHK-LKS: *(.omp_offloading.entries) // CHK-LKS: PROVIDE_HIDDEN(.omp_offloading.entries_end = .); // CHK-LKS: } // CHK-LKS: } // CHK-LKS: INSERT BEFORE .data // // Generate host BC file. // // CHK-COMMANDS: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.*}}"-o" " // CHK-COMMANDS-SAME: [[HOSTBC:[^\\/]+\.bc]]" "-x" "c" " // CHK-COMMANDS-SAME: [[INPUT:[^\\/]+\.c]]" "-fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu" // CHK-COMMANDS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-E" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-COMMANDS-ST-SAME: [[HOSTPP:[^\\/]+\.i]]" "-x" "c" " // CHK-COMMANDS-ST-SAME: [[INPUT:[^\\/]+\.c]]" // CHK-COMMANDS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-COMMANDS-ST-SAME: [[HOSTBC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.*}}[[HOSTPP]]" "-fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu" // // Compile for the powerpc device. // // CHK-COMMANDS: clang{{.*}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-obj" {{.*}}"-pic-level" "2" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-COMMANDS-SAME: [[T1OBJ:[^\\/]+\.o]]" "-x" "c" "{{.*}}[[INPUT]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.*}}[[HOSTBC]]" // CHK-COMMANDS: ld{{(\.exe)?}}" {{.*}}"-o" " // CHK-COMMANDS-SAME: [[T1BIN:[^\\/]+\.out]]" {{.*}}"{{.*}}[[T1OBJ]]" // CHK-COMMANDS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-E" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-COMMANDS-ST-SAME: [[T1PP:[^\\/]+\.i]]" "-x" "c" "{{.*}}[[INPUT]]" // CHK-COMMANDS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.*}}"-pic-level" "2" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-COMMANDS-ST-SAME: [[T1BC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.*}}[[T1PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.*}}[[HOSTBC]]" // CHK-COMMANDS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-S" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-COMMANDS-ST-SAME: [[T1ASM:[^\\/]+\.s]]" "-x" "ir" "{{.*}}[[T1BC]]" // CHK-COMMANDS-ST: clang{{.*}}" "-cc1as" "-triple" "powerpc64le-ibm-linux-gnu" "-filetype" "obj" {{.*}}"-o" " // CHK-COMMANDS-ST-SAME: [[T1OBJ:[^\\/]+\.o]]" "{{.*}}[[T1ASM]]" // CHK-COMMANDS-ST: ld{{(\.exe)?}}" {{.*}}"-shared" {{.*}}"-o" " // CHK-COMMANDS-ST-SAME: [[T1BIN:[^\\/]+\.out-openmp-powerpc64le-ibm-linux-gnu]]" {{.*}}"{{.*}}[[T1OBJ]]" // // Compile for the x86 device. // // CHK-COMMANDS: clang{{.*}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-obj" {{.*}}"-pic-level" "2" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-COMMANDS-SAME: [[T2OBJ:[^\\/]+\.o]]" "-x" "c" "{{.*}}[[INPUT]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.*}}[[HOSTBC]]" // CHK-COMMANDS: ld{{(\.exe)?}}" {{.*}}"-o" " // CHK-COMMANDS-SAME: [[T2BIN:[^\\/]+\.out]]" {{.*}}"{{.*}}[[T2OBJ]]" // CHK-COMMANDS-ST: clang{{.*}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-E" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-COMMANDS-ST-SAME: [[T2PP:[^\\/]+\.i]]" "-x" "c" "{{.*}}[[INPUT]]" // CHK-COMMANDS-ST: clang{{.*}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.*}}"-pic-level" "2" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-COMMANDS-ST-SAME: [[T2BC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.*}}[[T2PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.*}}[[HOSTBC]]" // CHK-COMMANDS-ST: clang{{.*}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-S" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-COMMANDS-ST-SAME: [[T2ASM:[^\\/]+\.s]]" "-x" "ir" "{{.*}}[[T2BC]]" // CHK-COMMANDS-ST: clang{{.*}}" "-cc1as" "-triple" "x86_64-pc-linux-gnu" "-filetype" "obj" {{.*}}"-o" " // CHK-COMMANDS-ST-SAME: [[T2OBJ:[^\\/]+\.o]]" "{{.*}}[[T2ASM]]" // CHK-COMMANDS-ST: ld{{(\.exe)?}}" {{.*}}"-shared" {{.*}}"-o" " // CHK-COMMANDS-ST-SAME: [[T2BIN:[^\\/]+\.out-openmp-x86_64-pc-linux-gnu]]" {{.*}}"{{.*}}[[T2OBJ]]" // // Generate host object from the BC file and link using the linker script. // // CHK-COMMANDS: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-obj" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-COMMANDS-SAME: [[HOSTOBJ:[^\\/]+\.o]]" "-x" "ir" "{{.*}}[[HOSTBC]]" // CHK-COMMANDS: ld{{(\.exe)?}}" {{.*}}"-o" " // CHK-COMMANDS-SAME: [[HOSTBIN:[^\\/]+\.out]]" {{.*}}"-lomptarget" {{.*}}"-T" " // CHK-COMMANDS-SAME: [[HOSTLK:[^\\/]+\.lk]]" // CHK-COMMANDS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-S" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-COMMANDS-ST-SAME: [[HOSTASM:[^\\/]+\.s]]" "-x" "ir" "{{.*}}[[HOSTBC]]" // CHK-COMMANDS-ST: clang{{.*}}" "-cc1as" "-triple" "powerpc64le--linux" "-filetype" "obj" {{.*}}"-o" " // CHK-COMMANDS-ST-SAME: [[HOSTOBJ:[^\\/]+\.o]]" "{{.*}}[[HOSTASM]]" // CHK-COMMANDS-ST: ld{{(\.exe)?}}" {{.*}}"-o" " // CHK-COMMANDS-ST-SAME: [[HOSTBIN:[^\\/]+\.out]]" {{.*}}"-lomptarget" {{.*}}"-T" " // CHK-COMMANDS-ST-SAME: [[HOSTLK:[^\\/]+\.lk]]" /// ########################################################################### /// Check separate compilation with offloading - bundling actions // RUN: %clang -### -ccc-print-phases -fopenmp=libomp -c -o %t.o -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %s -no-canonical-prefixes 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-BUACTIONS %s // CHK-BUACTIONS: 0: input, "[[INPUT:.+\.c]]", c, (host-openmp) // CHK-BUACTIONS: 1: preprocessor, {0}, cpp-output, (host-openmp) // CHK-BUACTIONS: 2: compiler, {1}, ir, (host-openmp) // CHK-BUACTIONS: 3: input, "[[INPUT]]", c, (device-openmp) // CHK-BUACTIONS: 4: preprocessor, {3}, cpp-output, (device-openmp) // CHK-BUACTIONS: 5: compiler, {4}, ir, (device-openmp) // CHK-BUACTIONS: 6: offload, "host-openmp (powerpc64le--linux)" {2}, "device-openmp (powerpc64le-ibm-linux-gnu)" {5}, ir // CHK-BUACTIONS: 7: backend, {6}, assembler, (device-openmp) // CHK-BUACTIONS: 8: assembler, {7}, object, (device-openmp) // CHK-BUACTIONS: 9: offload, "device-openmp (powerpc64le-ibm-linux-gnu)" {8}, object // CHK-BUACTIONS: 10: input, "[[INPUT]]", c, (device-openmp) // CHK-BUACTIONS: 11: preprocessor, {10}, cpp-output, (device-openmp) // CHK-BUACTIONS: 12: compiler, {11}, ir, (device-openmp) // CHK-BUACTIONS: 13: offload, "host-openmp (powerpc64le--linux)" {2}, "device-openmp (x86_64-pc-linux-gnu)" {12}, ir // CHK-BUACTIONS: 14: backend, {13}, assembler, (device-openmp) // CHK-BUACTIONS: 15: assembler, {14}, object, (device-openmp) // CHK-BUACTIONS: 16: offload, "device-openmp (x86_64-pc-linux-gnu)" {15}, object // CHK-BUACTIONS: 17: backend, {2}, assembler, (host-openmp) // CHK-BUACTIONS: 18: assembler, {17}, object, (host-openmp) // CHK-BUACTIONS: 19: clang-offload-bundler, {9, 16, 18}, object, (host-openmp) /// ########################################################################### /// Check separate compilation with offloading - unbundling actions // RUN: touch %t.i // RUN: %clang -### -ccc-print-phases -fopenmp=libomp -o %t.out -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %t.i -no-canonical-prefixes 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-UBACTIONS %s // CHK-UBACTIONS: 0: input, "somelib", object, (host-openmp) // CHK-UBACTIONS: 1: input, "[[INPUT:.+\.i]]", cpp-output, (host-openmp) // CHK-UBACTIONS: 2: clang-offload-unbundler, {1}, cpp-output, (host-openmp) // CHK-UBACTIONS: 3: compiler, {2}, ir, (host-openmp) // CHK-UBACTIONS: 4: backend, {3}, assembler, (host-openmp) // CHK-UBACTIONS: 5: assembler, {4}, object, (host-openmp) // CHK-UBACTIONS: 6: linker, {0, 5}, image, (host-openmp) // CHK-UBACTIONS: 7: input, "somelib", object, (device-openmp) // CHK-UBACTIONS: 8: compiler, {2}, ir, (device-openmp) // CHK-UBACTIONS: 9: offload, "host-openmp (powerpc64le--linux)" {3}, "device-openmp (powerpc64le-ibm-linux-gnu)" {8}, ir // CHK-UBACTIONS: 10: backend, {9}, assembler, (device-openmp) // CHK-UBACTIONS: 11: assembler, {10}, object, (device-openmp) // CHK-UBACTIONS: 12: linker, {7, 11}, image, (device-openmp) // CHK-UBACTIONS: 13: input, "somelib", object, (device-openmp) // CHK-UBACTIONS: 14: compiler, {2}, ir, (device-openmp) // CHK-UBACTIONS: 15: offload, "host-openmp (powerpc64le--linux)" {3}, "device-openmp (x86_64-pc-linux-gnu)" {14}, ir // CHK-UBACTIONS: 16: backend, {15}, assembler, (device-openmp) // CHK-UBACTIONS: 17: assembler, {16}, object, (device-openmp) // CHK-UBACTIONS: 18: linker, {13, 17}, image, (device-openmp) // CHK-UBACTIONS: 19: offload, "host-openmp (powerpc64le--linux)" {6}, "device-openmp (powerpc64le-ibm-linux-gnu)" {12}, "device-openmp (x86_64-pc-linux-gnu)" {18}, image /// ########################################################################### /// Check separate compilation with offloading - unbundling/bundling actions // RUN: touch %t.i // RUN: %clang -### -ccc-print-phases -fopenmp=libomp -c -o %t.o -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %t.i -no-canonical-prefixes 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-UBUACTIONS %s // CHK-UBUACTIONS: 0: input, "[[INPUT:.+\.i]]", cpp-output, (host-openmp) // CHK-UBUACTIONS: 1: clang-offload-unbundler, {0}, cpp-output, (host-openmp) // CHK-UBUACTIONS: 2: compiler, {1}, ir, (host-openmp) // CHK-UBUACTIONS: 3: compiler, {1}, ir, (device-openmp) // CHK-UBUACTIONS: 4: offload, "host-openmp (powerpc64le--linux)" {2}, "device-openmp (powerpc64le-ibm-linux-gnu)" {3}, ir // CHK-UBUACTIONS: 5: backend, {4}, assembler, (device-openmp) // CHK-UBUACTIONS: 6: assembler, {5}, object, (device-openmp) // CHK-UBUACTIONS: 7: offload, "device-openmp (powerpc64le-ibm-linux-gnu)" {6}, object // CHK-UBUACTIONS: 8: compiler, {1}, ir, (device-openmp) // CHK-UBUACTIONS: 9: offload, "host-openmp (powerpc64le--linux)" {2}, "device-openmp (x86_64-pc-linux-gnu)" {8}, ir // CHK-UBUACTIONS: 10: backend, {9}, assembler, (device-openmp) // CHK-UBUACTIONS: 11: assembler, {10}, object, (device-openmp) // CHK-UBUACTIONS: 12: offload, "device-openmp (x86_64-pc-linux-gnu)" {11}, object // CHK-UBUACTIONS: 13: backend, {2}, assembler, (host-openmp) // CHK-UBUACTIONS: 14: assembler, {13}, object, (host-openmp) // CHK-UBUACTIONS: 15: clang-offload-bundler, {7, 12, 14}, object, (host-openmp) /// ########################################################################### /// Check separate compilation with offloading - bundling jobs construct // RUN: %clang -### -fopenmp=libomp -c -o %t.o -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %s -no-canonical-prefixes 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-BUJOBS %s // RUN: %clang -### -fopenmp=libomp -c -o %t.o -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %s -save-temps -no-canonical-prefixes 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-BUJOBS-ST %s // Create host BC. // CHK-BUJOBS: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-BUJOBS-SAME: [[HOSTBC:[^\\/]+\.bc]]" "-x" "c" " // CHK-BUJOBS-SAME: [[INPUT:[^\\/]+\.c]]" "-fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu" // CHK-BUJOBS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-E" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-BUJOBS-ST-SAME: [[HOSTPP:[^\\/]+\.i]]" "-x" "c" " // CHK-BUJOBS-ST-SAME: [[INPUT:[^\\/]+\.c]]" // CHK-BUJOBS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-BUJOBS-ST-SAME: [[HOSTBC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.*}}[[HOSTPP]]" "-fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu" // Create target 1 object. // CHK-BUJOBS: clang{{.*}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-obj" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-BUJOBS-SAME: [[T1OBJ:[^\\/]+\.o]]" "-x" "c" "{{.*}}[[INPUT]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.*}}[[HOSTBC]]" // CHK-BUJOBS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-E" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-BUJOBS-ST-SAME: [[T1PP:[^\\/]+\.i]]" "-x" "c" "{{.*}}[[INPUT]]" // CHK-BUJOBS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-BUJOBS-ST-SAME: [[T1BC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.*}}[[T1PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.*}}[[HOSTBC]]" // CHK-BUJOBS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-S" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-BUJOBS-ST-SAME: [[T1ASM:[^\\/]+\.s]]" "-x" "ir" "{{.*}}[[T1BC]]" // CHK-BUJOBS-ST: clang{{.*}}" "-cc1as" "-triple" "powerpc64le-ibm-linux-gnu" "-filetype" "obj" {{.*}}"-o" " // CHK-BUJOBS-ST-SAME: [[T1OBJ:[^\\/]+\.o]]" "{{.*}}[[T1ASM]]" // Create target 2 object. // CHK-BUJOBS: clang{{.*}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-obj" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-BUJOBS-SAME: [[T2OBJ:[^\\/]+\.o]]" "-x" "c" "{{.*}}[[INPUT]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.*}}[[HOSTBC]]" // CHK-BUJOBS-ST: clang{{.*}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-E" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-BUJOBS-ST-SAME: [[T2PP:[^\\/]+\.i]]" "-x" "c" "{{.*}}[[INPUT]]" // CHK-BUJOBS-ST: clang{{.*}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-BUJOBS-ST-SAME: [[T2BC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.*}}[[T2PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.*}}[[HOSTBC]]" // CHK-BUJOBS-ST: clang{{.*}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-S" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-BUJOBS-ST-SAME: [[T2ASM:[^\\/]+\.s]]" "-x" "ir" "{{.*}}[[T2BC]]" // CHK-BUJOBS-ST: clang{{.*}}" "-cc1as" "-triple" "x86_64-pc-linux-gnu" "-filetype" "obj" {{.*}}"-o" " // CHK-BUJOBS-ST-SAME: [[T2OBJ:[^\\/]+\.o]]" "{{.*}}[[T2ASM]]" // Create host object and bundle. // CHK-BUJOBS: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-obj" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-BUJOBS-SAME: [[HOSTOBJ:[^\\/]+\.o]]" "-x" "ir" "{{.*}}[[HOSTBC]]" // CHK-BUJOBS: clang-offload-bundler{{.*}}" "-type=o" "-targets=openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu,host-powerpc64le--linux" "-outputs= // CHK-BUJOBS-SAME: [[RES:[^\\/]+\.o]]" "-inputs={{.*}}[[T1OBJ]],{{.*}}[[T2OBJ]],{{.*}}[[HOSTOBJ]]" // CHK-BUJOBS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-S" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-BUJOBS-ST-SAME: [[HOSTASM:[^\\/]+\.s]]" "-x" "ir" "{{.*}}[[HOSTBC]]" // CHK-BUJOBS-ST: clang{{.*}}" "-cc1as" "-triple" "powerpc64le--linux" "-filetype" "obj" {{.*}}"-o" " // CHK-BUJOBS-ST-SAME: [[HOSTOBJ:[^\\/]+\.o]]" "{{.*}}[[HOSTASM]]" // CHK-BUJOBS-ST: clang-offload-bundler{{.*}}" "-type=o" "-targets=openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu,host-powerpc64le--linux" "-outputs= // CHK-BUJOBS-ST-SAME: [[RES:[^\\/]+\.o]]" "-inputs={{.*}}[[T1OBJ]],{{.*}}[[T2OBJ]],{{.*}}[[HOSTOBJ]]" /// ########################################################################### /// Check separate compilation with offloading - unbundling jobs construct // RUN: touch %t.i // RUN: %clang -### -fopenmp=libomp -o %t.out -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %t.i -no-canonical-prefixes 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-UBJOBS %s // RUN: %clang -### -fopenmp=libomp -o %t.out -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %t.i -save-temps -no-canonical-prefixes 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-UBJOBS-ST %s // RUN: touch %t.o // RUN: %clang -### -fopenmp=libomp -o %t.out -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %t.o -no-canonical-prefixes 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-UBJOBS2 %s // RUN: %clang -### -fopenmp=libomp -o %t.out -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %t.o -save-temps -no-canonical-prefixes 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-UBJOBS2-ST %s // Unbundle and create host BC. // CHK-UBJOBS: clang-offload-bundler{{.*}}" "-type=i" "-targets=host-powerpc64le--linux,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu" "-inputs= // CHK-UBJOBS-SAME: [[INPUT:[^\\/]+\.i]]" "-outputs= // CHK-UBJOBS-SAME: [[HOSTPP:[^\\/]+\.i]], // CHK-UBJOBS-SAME: [[T1PP:[^\\/]+\.i]], // CHK-UBJOBS-SAME: [[T2PP:[^\\/]+\.i]]" "-unbundle" // CHK-UBJOBS: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBJOBS-SAME: [[HOSTBC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.*}}[[HOSTPP]]" "-fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu" // CHK-UBJOBS-ST: clang-offload-bundler{{.*}}" "-type=i" "-targets=host-powerpc64le--linux,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu" "-inputs= // CHK-UBJOBS-ST-SAME: [[INPUT:[^\\/]+\.i]]" "-outputs= // CHK-UBJOBS-ST-SAME: [[HOSTPP:[^\\/,]+\.i]], // CHK-UBJOBS-ST-SAME: [[T1PP:[^\\/,]+\.i]], // CHK-UBJOBS-ST-SAME: [[T2PP:[^\\/,]+\.i]]" "-unbundle" // CHK-UBJOBS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBJOBS-ST-SAME: [[HOSTBC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.*}}[[HOSTPP]]" "-fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu" // Create target 1 object. // CHK-UBJOBS: clang{{.*}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-obj" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBJOBS-SAME: [[T1OBJ:[^\\/]+\.o]]" "-x" "cpp-output" "{{.*}}[[T1PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.*}}[[HOSTBC]]" // CHK-UBJOBS: ld{{(\.exe)?}}" {{.*}}"-o" " // CHK-UBJOBS-SAME: [[T1BIN:[^\\/]+\.out]]" {{.*}}"{{.*}}[[T1OBJ]]" // CHK-UBJOBS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBJOBS-ST-SAME: [[T1BC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.*}}[[T1PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.*}}[[HOSTBC]]" // CHK-UBJOBS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-S" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBJOBS-ST-SAME: [[T1ASM:[^\\/]+\.s]]" "-x" "ir" "{{.*}}[[T1BC]]" // CHK-UBJOBS-ST: clang{{.*}}" "-cc1as" "-triple" "powerpc64le-ibm-linux-gnu" "-filetype" "obj" {{.*}}"-o" " // CHK-UBJOBS-ST-SAME: [[T1OBJ:[^\\/]+\.o]]" "{{.*}}[[T1ASM]]" // CHK-UBJOBS-ST: ld{{(\.exe)?}}" {{.*}}"-o" " // CHK-UBJOBS-ST-SAME: [[T1BIN:[^\\/]+\.out-openmp-powerpc64le-ibm-linux-gnu]]" {{.*}}"{{.*}}[[T1OBJ]]" // Create target 2 object. // CHK-UBJOBS: clang{{.*}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-obj" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBJOBS-SAME: [[T2OBJ:[^\\/]+\.o]]" "-x" "cpp-output" "{{.*}}[[T2PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.*}}[[HOSTBC]]" // CHK-UBJOBS: ld{{(\.exe)?}}" {{.*}}"-o" " // CHK-UBJOBS-SAME: [[T2BIN:[^\\/]+\.out]]" {{.*}}"{{.*}}[[T2OBJ]]" // CHK-UBJOBS-ST: clang{{.*}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBJOBS-ST-SAME: [[T2BC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.*}}[[T2PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.*}}[[HOSTBC]]" // CHK-UBJOBS-ST: clang{{.*}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-S" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBJOBS-ST-SAME: [[T2ASM:[^\\/]+\.s]]" "-x" "ir" "{{.*}}[[T2BC]]" // CHK-UBJOBS-ST: clang{{.*}}" "-cc1as" "-triple" "x86_64-pc-linux-gnu" "-filetype" "obj" {{.*}}"-o" " // CHK-UBJOBS-ST-SAME: [[T2OBJ:[^\\/]+\.o]]" "{{.*}}[[T2ASM]]" // CHK-UBJOBS-ST: ld{{(\.exe)?}}" {{.*}}"-o" " // CHK-UBJOBS-ST-SAME: [[T2BIN:[^\\/]+\.out-openmp-x86_64-pc-linux-gnu]]" {{.*}}"{{.*}}[[T2OBJ]]" // Create binary. // CHK-UBJOBS: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-obj" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBJOBS-SAME: [[HOSTOBJ:[^\\/]+\.o]]" "-x" "ir" "{{.*}}[[HOSTBC]]" // CHK-UBJOBS: ld{{(\.exe)?}}" {{.*}}"-o" " // CHK-UBJOBS-SAME: [[HOSTBIN:[^\\/]+\.out]]" {{.*}}"{{.*}}[[HOSTOBJ]]" {{.*}}"-T" " // CHK-UBJOBS-SAME: [[LKS:[^\\/]+\.lk]]" // CHK-UBJOBS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-S" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBJOBS-ST-SAME: [[HOSTASM:[^\\/]+\.s]]" "-x" "ir" "{{.*}}[[HOSTBC]]" // CHK-UBJOBS-ST: clang{{.*}}" "-cc1as" "-triple" "powerpc64le--linux" "-filetype" "obj" {{.*}}"-o" " // CHK-UBJOBS-ST-SAME: [[HOSTOBJ:[^\\/]+\.o]]" "{{.*}}[[HOSTASM]]" // CHK-UBJOBS-ST: ld{{(\.exe)?}}" {{.*}}"-o" " // CHK-UBJOBS-ST-SAME: [[HOSTBIN:[^\\/]+\.out]]" {{.*}}"{{.*}}[[HOSTOBJ]]" {{.*}}"-T" " // CHK-UBJOBS-ST-SAME: [[LKS:[^\\/]+\.lk]]" // Unbundle object file. // CHK-UBJOBS2: clang-offload-bundler{{.*}}" "-type=o" "-targets=host-powerpc64le--linux,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu" "-inputs= // CHK-UBJOBS2-SAME: [[INPUT:[^\\/]+\.o]]" "-outputs= // CHK-UBJOBS2-SAME: [[HOSTOBJ:[^\\/]+\.o]], // CHK-UBJOBS2-SAME: [[T1OBJ:[^\\/]+\.o]], // CHK-UBJOBS2-SAME: [[T2OBJ:[^\\/]+\.o]]" "-unbundle" // CHK-UBJOBS2: ld{{(\.exe)?}}" {{.*}}"-o" " // CHK-UBJOBS2-SAME: [[T1BIN:[^\\/]+\.out]]" {{.*}}"{{.*}}[[T1OBJ]]" // CHK-UBJOBS2: ld{{(\.exe)?}}" {{.*}}"-o" " // CHK-UBJOBS2-SAME: [[T2BIN:[^\\/]+\.out]]" {{.*}}"{{.*}}[[T2OBJ]]" // CHK-UBJOBS2: ld{{(\.exe)?}}" {{.*}}"-o" " // CHK-UBJOBS2-SAME: [[HOSTBIN:[^\\/]+\.out]]" {{.*}}"{{.*}}[[HOSTOBJ]]" {{.*}}"-T" " // CHK-UBJOBS2-SAME: [[LKS:[^\\/]+\.lk]]" // CHK-UBJOBS2-ST: clang-offload-bundler{{.*}}" "-type=o" "-targets=host-powerpc64le--linux,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu" "-inputs= // CHK-UBJOBS2-ST-SAME: [[INPUT:[^\\/]+\.o]]" "-outputs= // CHK-UBJOBS2-ST-SAME: [[HOSTOBJ:[^\\/,]+\.o]], // CHK-UBJOBS2-ST-SAME: [[T1OBJ:[^\\/,]+\.o]], // CHK-UBJOBS2-ST-SAME: [[T2OBJ:[^\\/,]+\.o]]" "-unbundle" // CHK-UBJOBS2-ST: ld{{(\.exe)?}}" {{.*}}"-o" " // CHK-UBJOBS2-ST-SAME: [[T1BIN:[^\\/]+\.out-openmp-powerpc64le-ibm-linux-gnu]]" {{.*}}"{{.*}}[[T1OBJ]]" // CHK-UBJOBS2-ST: ld{{(\.exe)?}}" {{.*}}"-o" " // CHK-UBJOBS2-ST-SAME: [[T2BIN:[^\\/]+\.out-openmp-x86_64-pc-linux-gnu]]" {{.*}}"{{.*}}[[T2OBJ]]" // CHK-UBJOBS2-ST: ld{{(\.exe)?}}" {{.*}}"-o" " // CHK-UBJOBS2-ST-SAME: [[HOSTBIN:[^\\/]+\.out]]" {{.*}}"{{.*}}[[HOSTOBJ]]" {{.*}}"-T" " // CHK-UBJOBS2-ST-SAME: [[LKS:[^\\/]+\.lk]]" /// ########################################################################### /// Check separate compilation with offloading - unbundling/bundling jobs /// construct // RUN: touch %t.i // RUN: %clang -### -fopenmp=libomp -c %t.o -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %t.i -no-canonical-prefixes 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-UBUJOBS %s // RUN: %clang -### -fopenmp=libomp -c %t.o -lsomelib -target powerpc64le-linux -fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu %t.i -save-temps -no-canonical-prefixes 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-UBUJOBS-ST %s // Unbundle and create host BC. // CHK-UBUJOBS: clang-offload-bundler{{.*}}" "-type=i" "-targets=host-powerpc64le--linux,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu" "-inputs= // CHK-UBUJOBS-SAME: [[INPUT:[^\\/]+\.i]]" "-outputs= // CHK-UBUJOBS-SAME: [[HOSTPP:[^\\/]+\.i]], // CHK-UBUJOBS-SAME: [[T1PP:[^\\/]+\.i]], // CHK-UBUJOBS-SAME: [[T2PP:[^\\/]+\.i]]" "-unbundle" // CHK-UBUJOBS: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBUJOBS-SAME: [[HOSTBC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.*}}[[HOSTPP]]" "-fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu" // CHK-UBUJOBS-ST: clang-offload-bundler{{.*}}" "-type=i" "-targets=host-powerpc64le--linux,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu" "-inputs= // CHK-UBUJOBS-ST-SAME: [[INPUT:[^\\/]+\.i]]" "-outputs= // CHK-UBUJOBS-ST-SAME: [[HOSTPP:[^\\/,]+\.i]], // CHK-UBUJOBS-ST-SAME: [[T1PP:[^\\/,]+\.i]], // CHK-UBUJOBS-ST-SAME: [[T2PP:[^\\/,]+\.i]]" "-unbundle" // CHK-UBUJOBS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBUJOBS-ST-SAME: [[HOSTBC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.*}}[[HOSTPP]]" "-fopenmp-targets=powerpc64le-ibm-linux-gnu,x86_64-pc-linux-gnu" // Create target 1 object. // CHK-UBUJOBS: clang{{.*}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-obj" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBUJOBS-SAME: [[T1OBJ:[^\\/]+\.o]]" "-x" "cpp-output" "{{.*}}[[T1PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.*}}[[HOSTBC]]" // CHK-UBUJOBS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBUJOBS-ST-SAME: [[T1BC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.*}}[[T1PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.*}}[[HOSTBC]]" // CHK-UBUJOBS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le-ibm-linux-gnu" "-aux-triple" "powerpc64le--linux" "-S" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBUJOBS-ST-SAME: [[T1ASM:[^\\/]+\.s]]" "-x" "ir" "{{.*}}[[T1BC]]" // CHK-UBUJOBS-ST: clang{{.*}}" "-cc1as" "-triple" "powerpc64le-ibm-linux-gnu" "-filetype" "obj" {{.*}}"-o" " // CHK-UBUJOBS-ST-SAME: [[T1OBJ:[^\\/]+\.o]]" "{{.*}}[[T1ASM]]" // Create target 2 object. // CHK-UBUJOBS: clang{{.*}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-obj" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBUJOBS-SAME: [[T2OBJ:[^\\/]+\.o]]" "-x" "cpp-output" "{{.*}}[[T2PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.*}}[[HOSTBC]]" // CHK-UBUJOBS-ST: clang{{.*}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-emit-llvm-bc" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBUJOBS-ST-SAME: [[T2BC:[^\\/]+\.bc]]" "-x" "cpp-output" "{{.*}}[[T2PP]]" "-fopenmp-is-device" "-fopenmp-host-ir-file-path" "{{.*}}[[HOSTBC]]" // CHK-UBUJOBS-ST: clang{{.*}}" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-aux-triple" "powerpc64le--linux" "-S" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBUJOBS-ST-SAME: [[T2ASM:[^\\/]+\.s]]" "-x" "ir" "{{.*}}[[T2BC]]" // CHK-UBUJOBS-ST: clang{{.*}}" "-cc1as" "-triple" "x86_64-pc-linux-gnu" "-filetype" "obj" {{.*}}"-o" " // CHK-UBUJOBS-ST-SAME: [[T2OBJ:[^\\/]+\.o]]" "{{.*}}[[T2ASM]]" // Create binary. // CHK-UBUJOBS: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-emit-obj" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBUJOBS-SAME: [[HOSTOBJ:[^\\/]+\.o]]" "-x" "ir" "{{.*}}[[HOSTBC]]" // CHK-UBUJOBS: clang-offload-bundler{{.*}}" "-type=o" "-targets=openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu,host-powerpc64le--linux" "-outputs= // CHK-UBUJOBS-SAME: [[RES:[^\\/]+\.o]]" "-inputs={{.*}}[[T1OBJ]],{{.*}}[[T2OBJ]],{{.*}}[[HOSTOBJ]]" // CHK-UBUJOBS-ST: clang{{.*}}" "-cc1" "-triple" "powerpc64le--linux" "-S" {{.*}}"-fopenmp" {{.*}}"-o" " // CHK-UBUJOBS-ST-SAME: [[HOSTASM:[^\\/]+\.s]]" "-x" "ir" "{{.*}}[[HOSTBC]]" // CHK-UBUJOBS-ST: clang{{.*}}" "-cc1as" "-triple" "powerpc64le--linux" "-filetype" "obj" {{.*}}"-o" " // CHK-UBUJOBS-ST-SAME: [[HOSTOBJ:[^\\/]+\.o]]" "{{.*}}[[HOSTASM]]" // CHK-UBUJOBS-ST: clang-offload-bundler{{.*}}" "-type=o" "-targets=openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu,host-powerpc64le--linux" "-outputs= // CHK-UBUJOBS-ST-SAME: [[RES:[^\\/]+\.o]]" "-inputs={{.*}}[[T1OBJ]],{{.*}}[[T2OBJ]],{{.*}}[[HOSTOBJ]]" /// ########################################################################### /// Check -fopenmp-is-device is passed when compiling for the device. // RUN: %clang -### -no-canonical-prefixes -target powerpc64le-linux -fopenmp=libomp -fopenmp-targets=powerpc64le-ibm-linux-gnu %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FOPENMP-IS-DEVICE %s // CHK-FOPENMP-IS-DEVICE: clang{{.*}} "-aux-triple" "powerpc64le--linux" {{.*}}.c" "-fopenmp-is-device" "-fopenmp-host-ir-file-path"

{ "language": "Assembly" }

// RUN: %clangxx -fsycl-device-only -c -fno-color-diagnostics -Xclang -ast-dump %s -I %sycl_include -Wno-sycl-strict | FileCheck %s // UNSUPPORTED: windows #include <CL/sycl/accessor.hpp> typedef cl::sycl::accessor<int, 1, cl::sycl::access::mode::read> dummy; // AccessorImplDevice must have MemRange and Offset fields // CHECK: CXXRecordDecl {{.*}} class AccessorImplDevice definition // CHECK-NOT: CXXRecordDecl {{.*}} definition // CHECK: FieldDecl {{.*}} referenced Offset // CHECK-NOT: CXXRecordDecl {{.*}} definition // CHECK: FieldDecl {{.*}} referenced MemRange // accessor.impl must be present and of AccessorImplDevice type // CHECK: CXXRecordDecl {{.*}} class accessor definition // CHECK-NOT: CXXRecordDecl {{.*}} definition // CHECK: FieldDecl {{.*}} referenced impl 'detail::AccessorImplDevice<AdjustedDim>'

{ "language": "Assembly" }

# REQUIRES: zlib # RUN: yaml2obj %p/Inputs/compress-debug-sections.yaml -o %t.o # RUN: llvm-objcopy --compress-debug-sections=zlib-gnu %t.o %t-compressed.o # RUN: llvm-objcopy --decompress-debug-sections %t-compressed.o %t-decompressed.o # RUN: llvm-objdump -s %t.o --section=.debug_foo | FileCheck %s # RUN: llvm-objdump -s %t-compressed.o | FileCheck %s --check-prefix=CHECK-COMPRESSED # RUN: llvm-readobj --relocations -S %t-compressed.o | FileCheck %s --check-prefix=CHECK-FLAGS # RUN: llvm-readobj --relocations -S %t-decompressed.o | FileCheck %s --check-prefix=CHECK-HEADER # RUN: llvm-readobj --relocations -S %t.o | FileCheck %s --check-prefix=CHECK-HEADER # RUN: llvm-objdump -s %t-decompressed.o --section=.debug_foo | FileCheck %s # CHECK: .debug_foo: # CHECK-NEXT: 0000 00000000 00000000 # CHECK-HEADER: Name: .debug_foo # CHECK-HEADER-NEXT: Type: SHT_PROGBITS # CHECK-HEADER-NEXT: Flags [ # CHECK-HEADER-NEXT: ] # CHECK-HEADER-NEXT: Address: # CHECK-HEADER-NEXT: Offset: # CHECK-HEADER-NEXT: Size: 8 # CHECK-COMPRESSED: .zdebug_foo: # CHECK-COMPRESSED: ZLIB # CHECK-COMPRESSED: .notdebug_foo: # CHECK-FLAGS-NOT: Name: .debug_foo # CHECK-FLAGS: Name: .zdebug_foo # CHECK-FLAGS-NEXT: Type: SHT_PROGBITS # CHECK-FLAGS-NEXT: Flags [ # CHECK-FLAGS-NEXT: ] # CHECK-FLAGS-NEXT: Address: # CHECK-FLAGS-NEXT: Offset: # CHECK-FLAGS-NEXT: Size: 23 # CHECK-FLAGS: Name: .notdebug_foo # CHECK-FLAGS-NEXT: Type: SHT_PROGBITS # CHECK-FLAGS-NEXT: Flags [ # CHECK-FLAGS-NEXT: ] # CHECK-FLAGS-NEXT: Address: # CHECK-FLAGS-NEXT: Offset: # CHECK-FLAGS-NEXT: Size: 8 # CHECK-FLAGS: Name: .rela.debug_foo # CHECK-FLAGS-NEXT: Type: SHT_RELA # CHECK-FLAGS-NEXT: Flags [ # CHECK-FLAGS-NEXT: ] # CHECK-FLAGS: Relocations [ # CHECK-FLAGS-NEXT: .rela.debug_foo { # CHECK-FLAGS-NEXT: 0x1 R_X86_64_32 .zdebug_foo 0x0 # CHECK-FLAGS-NEXT: 0x2 R_X86_64_32 .notdebug_foo 0x0 # CHECK-FLAGS-NEXT: } # CHECK-FLAGS-NEXT: ]

{ "language": "Assembly" }

diff -u -r a/usr/lib/libc.so b/usr/lib/libc.so --- a/usr/lib/libc.so 2016-12-30 23:00:08.284951863 +0900 +++ b/usr/lib/libc.so 2016-12-30 23:00:32.140951815 +0900 @@ -2,4 +2,4 @@ Use the shared library, but some functions are only in the static library, so try that secondarily. */ OUTPUT_FORMAT(elf32-littlearm) -GROUP ( /lib/libc.so.6 /usr/lib/libc_nonshared.a AS_NEEDED ( /lib/ld-linux.so.3 ) ) +GROUP ( libc.so.6 libc_nonshared.a AS_NEEDED ( ld-linux.so.3 ) )

{ "language": "Assembly" }

;Flag tables for normal and extended Intel opcodes ;(c) sars [HI-TECH] 2003 ;[email protected] ; ;Version: ;01-test version ;02-added: TableEXT ;03-added: new flags ;04-added: support for MMX, SSE, SSE2, 3DNOW ; ;Description: ;Size of table element is 4 bits. ;0h-one byte instruction ;1h-ModRM byte ;2h-imm8,rel8 etc ;4h-ptr16 etc ;8h-imm16/32,rel16/32 etc ;0Fh-prefix ;0Eh-unsupported opcodes ;3DNOW-Supported ;SSE-Supported ;SSE2-Supported ;MMX-Supported ;================NORMAL OPCODES================ c_Table: ; 01 23 45 67 89 AB CD EF db 011h,011h,028h,000h,011h,011h,028h,000h;0Fh db 011h,011h,028h,000h,011h,011h,028h,000h;1Fh db 011h,011h,028h,0F0h,011h,011h,028h,0F0h;2Fh db 011h,011h,028h,0F0h,011h,011h,028h,0F0h;3Fh db 000h,000h,000h,000h,000h,000h,000h,000h;4Fh db 000h,000h,000h,000h,000h,000h,000h,000h;5Fh db 000h,011h,0FFh,0FFh,089h,023h,000h,000h;6Fh db 022h,022h,022h,022h,022h,022h,022h,022h;7Fh db 039h,033h,011h,011h,011h,011h,011h,011h;8Fh db 000h,000h,000h,000h,000h,0C0h,000h,000h;9Fh db 088h,088h,000h,000h,028h,000h,000h,000h;AFh db 022h,022h,022h,022h,088h,088h,088h,088h;BFh db 033h,040h,011h,039h,060h,040h,002h,000h;CFh db 011h,011h,022h,000h,011h,011h,011h,011h;DFh db 022h,022h,022h,022h,088h,0C2h,000h,000h;EFh db 0F0h,0FFh,000h,011h,000h,000h,000h,011h;FFh ;============================================== Lentable equ $-c_Table ;===============EXTENDED OPCODES=============== c_TableEXT: ; 01 23 45 67 89 AB CD EF db 011h,011h,0E0h,000h,000h,0EEh,0E1h,003h;0Fh db 011h,011h,011h,011h,01Eh,0EEh,0EEh,0EEh;1Fh db 011h,011h,01Eh,01Eh,011h,011h,011h,011h;2Fh db 000h,000h,000h,0EEh,0EEh,0EEh,0EEh,0EEh;3Fh db 011h,011h,011h,011h,011h,011h,011h,011h;4Fh db 011h,011h,011h,011h,011h,011h,011h,011h;5Fh db 011h,011h,011h,011h,011h,011h,011h,011h;6Fh db 033h,033h,011h,010h,011h,011h,011h,011h;7Fh db 088h,088h,088h,088h,088h,088h,088h,088h;8Fh db 011h,011h,011h,011h,011h,011h,011h,011h;9Fh db 000h,001h,031h,011h,000h,001h,031h,011h;AFh db 011h,011h,011h,011h,0EEh,031h,011h,011h;BFh db 011h,031h,033h,031h,000h,000h,000h,000h;CFh db 0E1h,011h,011h,011h,011h,011h,011h,011h;DFh db 011h,011h,011h,011h,011h,011h,011h,011h;EFh db 0E1h,011h,011h,011h,011h,011h,011h,01Eh;FFh ;==============================================

{ "language": "Assembly" }

;/*---------------------------------------------------------------------------------------------------------*/ ;/* Holtek Semiconductor Inc. */ ;/* */ ;/* Copyright (C) Holtek Semiconductor Inc. */ ;/* All rights reserved. */ ;/* */ ;/*----------------------------------------------------------------------------------------------------------- ; File Name : startup_ht32f5xxxx_iar_03_iap.s ; Version : $Rev:: 4151 $ ; Date : $Date:: 2019-07-24 #$ ; Description : Startup code. ;-----------------------------------------------------------------------------------------------------------*/ ; Supported Device ; ======================================== ; HT32F0008 ; HT32F52142 ; HT32F52344, HT32F52354 ; HT32F52357, HT32F52367 ;/* <<< Use Configuration Wizard in Context Menu >>> */ ;// <o> HT32 Device ;// <0=> By Project Asm Define ;// <6=> HT32F0008 ;// <6=> HT32F52142 ;// <9=> HT32F52344/54 ;// <11=> HT32F52357/67 USE_HT32_CHIP_SET EQU 0 _HT32FWID EQU 0xFFFFFFFF ;_HT32FWID EQU 0x00000008 ;_HT32FWID EQU 0x00052142 ;_HT32FWID EQU 0x00052344 ;_HT32FWID EQU 0x00052354 ;_HT32FWID EQU 0x00052357 ;_HT32FWID EQU 0x00052367 HT32F0008 EQU 6 HT32F52142 EQU 6 HT32F52344_54 EQU 9 HT32F52357_67 EQU 11 IF USE_HT32_CHIP_SET=0 ELSE #undef USE_HT32_CHIP #define USE_HT32_CHIP USE_HT32_CHIP_SET ENDIF MODULE ?cstartup ;; Forward declaration of sections. SECTION CSTACKIAP:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) EXTERN __iar_program_start EXTERN SystemInit PUBLIC __vector_table ;******************************************************************************* ; Fill-up the Vector Table entries with the exceptions ISR address ;******************************************************************************* DATA _RESERVED EQU 0xFFFFFFFF __vector_table DCD sfe(CSTACKIAP) ; ---, 00, 0x000, Top address of Stack DCD Reset_Handler ; ---, 01, 0x004, Reset Handler DCD NMI_Handler ; -14, 02, 0x008, NMI Handler DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler DCD _RESERVED ; ---, 04, 0x010, Reserved DCD _RESERVED ; ---, 05, 0x014, Reserved DCD _RESERVED ; ---, 06, 0x018, Reserved DCD _RESERVED ; ---, 07, 0x01C, Reserved DCD _HT32FWID ; ---, 08, 0x020, Reserved DCD _RESERVED ; ---, 09, 0x024, Reserved DCD _RESERVED ; ---, 10, 0x028, Reserved DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler DCD _RESERVED ; ---, 12, 0x030, Reserved DCD _RESERVED ; ---, 13, 0x034, Reserved DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler SECTION .usartisr:CODE:ROOT(2) EXTERN UxART_IRQHandler DATA DCD UxART_IRQHandler THUMB PUBWEAK Reset_Handler SECTION .text:CODE:REORDER:NOROOT(2) Reset_Handler LDR R0, =BootProcess BLX R0 LDR R0, =SystemInit BLX R0 LDR R0, =__iar_program_start BX R0 BootProcess LDR R0, =0x40080300 LDR R1,[R0, #0x10] CMP R1, #0 BNE BP1 LDR R1,[R0, #0x14] CMP R1, #0 BNE BP1 LDR R1,[R0, #0x18] CMP R1, #0 BNE BP1 LDR R1,[R0, #0x1C] CMP R1, #0 BEQ BP2 BP1 LDR R0, =0x40080180 LDR R1,[R0, #0xC] LSLS R1, R1, #4 LSRS R1, R1, #20 CMP R1, #0 BEQ BP3 CMP R1, #5 BEQ BP3 CMP R1, #6 BEQ BP3 BP2 DSB LDR R0, =0x20000000 LDR R1, =0x05fa0004 STR R1, [R0] LDR R1, =0xe000ed00 LDR R0, =0x05fa0004 STR R0, [R1, #0xC] DSB B . BP3 LDR R0, =0x20000000 LDR R1, [R0] LDR R0, =0x05fa0004 CMP R0, R1 BEQ BP4 BX LR BP4 LDR R0, =0x40088100 LDR R1, =0x00000001 STR R1, [R0] LDR R0, =0x20000000 LDR R1, =0x0 STR R1, [R0] BX LR PUBWEAK NMI_Handler SECTION .text:CODE:REORDER:NOROOT(1) NMI_Handler B . PUBWEAK HardFault_Handler SECTION .text:CODE:REORDER:NOROOT(1) HardFault_Handler B . PUBWEAK SVC_Handler SECTION .text:CODE:REORDER:NOROOT(1) SVC_Handler B . PUBWEAK PendSV_Handler SECTION .text:CODE:REORDER:NOROOT(1) PendSV_Handler B . PUBWEAK SysTick_Handler SECTION .text:CODE:REORDER:NOROOT(1) SysTick_Handler B . PUBWEAK LVD_BOD_IRQHandler PUBWEAK RTC_IRQHandler PUBWEAK FLASH_IRQHandler PUBWEAK EVWUP_IRQHandler PUBWEAK EXTI0_1_IRQHandler PUBWEAK EXTI2_3_IRQHandler PUBWEAK EXTI4_15_IRQHandler PUBWEAK COMP_IRQHandler PUBWEAK COMP_DAC_IRQHandler PUBWEAK ADC_IRQHandler PUBWEAK MCTM0_IRQHandler PUBWEAK GPTM0_IRQHandler PUBWEAK SCTM0_IRQHandler PUBWEAK SCTM1_IRQHandler PUBWEAK PWM0_IRQHandler PUBWEAK PWM1_IRQHandler PUBWEAK BFTM0_IRQHandler PUBWEAK BFTM1_IRQHandler PUBWEAK I2C0_IRQHandler PUBWEAK I2C1_IRQHandler PUBWEAK SPI0_IRQHandler PUBWEAK SPI1_IRQHandler PUBWEAK QSPI_IRQHandler PUBWEAK USART0_IRQHandler PUBWEAK USART1_IRQHandler PUBWEAK UART0_IRQHandler PUBWEAK UART1_IRQHandler PUBWEAK UART0_UART2_IRQHandler PUBWEAK UART1_UART3_IRQHandler PUBWEAK SCI_IRQHandler PUBWEAK I2S_IRQHandler PUBWEAK AES_IRQHandler PUBWEAK USB_IRQHandler PUBWEAK PDMA_CH0_1_IRQHandler PUBWEAK PDMA_CH2_5_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) LVD_BOD_IRQHandler RTC_IRQHandler FLASH_IRQHandler EVWUP_IRQHandler EXTI0_1_IRQHandler EXTI2_3_IRQHandler EXTI4_15_IRQHandler COMP_IRQHandler COMP_DAC_IRQHandler ADC_IRQHandler MCTM0_IRQHandler GPTM0_IRQHandler SCTM0_IRQHandler SCTM1_IRQHandler PWM0_IRQHandler PWM1_IRQHandler BFTM0_IRQHandler BFTM1_IRQHandler I2C0_IRQHandler I2C1_IRQHandler SPI0_IRQHandler SPI1_IRQHandler QSPI_IRQHandler USART0_IRQHandler USART1_IRQHandler UART0_IRQHandler UART1_IRQHandler UART0_UART2_IRQHandler UART1_UART3_IRQHandler SCI_IRQHandler I2S_IRQHandler AES_IRQHandler USB_IRQHandler PDMA_CH0_1_IRQHandler PDMA_CH2_5_IRQHandler B . END

{ "language": "Assembly" }

.TH libssh2_channel_ignore_extended_data 3 "20 Feb 2010" "libssh2 1.2.4" "libssh2 manual" .SH NAME libssh2_channel_ignore_extended_data - convenience macro for \fIlibssh2_channel_handle_extended_data(3)\fP calls .SH SYNOPSIS #include <libssh2.h> libssh2_channel_ignore_extended_data(arguments) .SH DESCRIPTION This function is deprecated. Use the \fIlibssh2_channel_handle_extended_data2(3)\fP function instead! This is a macro defined in a public libssh2 header file that is using the underlying function \fIlibssh2_channel_handle_extended_data(3)\fP. .SH RETURN VALUE See \fIlibssh2_channel_handle_extended_data(3)\fP .SH ERRORS See \fIlibssh2_channel_handle_extended_data(3)\fP .SH SEE ALSO .BR libssh2_channel_handle_extended_data(3)

{ "language": "Assembly" }

# . $ . '' . -LRB- . -RRB- . , . . . : . ADD X AFX PRT CC CONJ CD NUM DT DET EX DET FW X GW X HYPH . IN ADP JJ ADJ JJR ADJ JJS ADJ LS X MD VERB NFP . NN NOUN NNP NOUN NNPS NOUN NNS NOUN PDT DET POS PRT PRP PRON PRP$ PRON RB ADV RBR ADV RBS ADV RP PRT SYM X TO PRT UH X VB VERB VBD VERB VBG VERB VBN VERB VBP VERB VBZ VERB WDT DET WP PRON WP$ PRON WRB ADV `` . X X XX X

{ "language": "Assembly" }

rv32uf-p-fcmp: file format elf32-littleriscv Disassembly of section .text.init: 80000000 <_start>: 80000000: 04c0006f j 8000004c <reset_vector> 80000004 <trap_vector>: 80000004: 34202f73 csrr t5,mcause 80000008: 00800f93 li t6,8 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> 80000010: 00900f93 li t6,9 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> 80000018: 00b00f93 li t6,11 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> 80000020: 80000f17 auipc t5,0x80000 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> 8000002c: 000f0067 jr t5 80000030: 34202f73 csrr t5,mcause 80000034: 000f5463 bgez t5,8000003c <handle_exception> 80000038: 0040006f j 8000003c <handle_exception> 8000003c <handle_exception>: 8000003c: 5391e193 ori gp,gp,1337 80000040 <write_tohost>: 80000040: 00001f17 auipc t5,0x1 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> 80000048: ff9ff06f j 80000040 <write_tohost> 8000004c <reset_vector>: 8000004c: f1402573 csrr a0,mhartid 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> 80000054: 00000297 auipc t0,0x0 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> 8000005c: 30529073 csrw mtvec,t0 80000060: 18005073 csrwi satp,0 80000064: 00000297 auipc t0,0x0 80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38> 8000006c: 30529073 csrw mtvec,t0 80000070: 800002b7 lui t0,0x80000 80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdf0f> 80000078: 3b029073 csrw pmpaddr0,t0 8000007c: 01f00293 li t0,31 80000080: 3a029073 csrw pmpcfg0,t0 80000084: 00000297 auipc t0,0x0 80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50> 8000008c: 30529073 csrw mtvec,t0 80000090: 30205073 csrwi medeleg,0 80000094: 30305073 csrwi mideleg,0 80000098: 30405073 csrwi mie,0 8000009c: 00000193 li gp,0 800000a0: 00000297 auipc t0,0x0 800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector> 800000a8: 30529073 csrw mtvec,t0 800000ac: 00100513 li a0,1 800000b0: 01f51513 slli a0,a0,0x1f 800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78> 800000b8: 0ff0000f fence 800000bc: 00100193 li gp,1 800000c0: 00000073 ecall 800000c4: 80000297 auipc t0,0x80000 800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000> 800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c> 800000d0: 10529073 csrw stvec,t0 800000d4: 0000b2b7 lui t0,0xb 800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> 800000dc: 30229073 csrw medeleg,t0 800000e0: 30202373 csrr t1,medeleg 800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception> 800000e8: 30005073 csrwi mstatus,0 800000ec: 00002537 lui a0,0x2 800000f0: 30052073 csrs mstatus,a0 800000f4: 00305073 csrwi fcsr,0 800000f8: 00000297 auipc t0,0x0 800000fc: 01428293 addi t0,t0,20 # 8000010c <test_2> 80000100: 34129073 csrw mepc,t0 80000104: f1402573 csrr a0,mhartid 80000108: 30200073 mret 8000010c <test_2>: 8000010c: 00200193 li gp,2 80000110: 00002517 auipc a0,0x2 80000114: ef050513 addi a0,a0,-272 # 80002000 <test_2_data> 80000118: 00052007 flw ft0,0(a0) 8000011c: 00452087 flw ft1,4(a0) 80000120: 00852107 flw ft2,8(a0) 80000124: 00c52683 lw a3,12(a0) 80000128: a0102553 feq.s a0,ft0,ft1 8000012c: 001015f3 fsflags a1,zero 80000130: 00000613 li a2,0 80000134: 2ad51663 bne a0,a3,800003e0 <fail> 80000138: 2ac59463 bne a1,a2,800003e0 <fail> 8000013c <test_3>: 8000013c: 00300193 li gp,3 80000140: 00002517 auipc a0,0x2 80000144: ed050513 addi a0,a0,-304 # 80002010 <test_3_data> 80000148: 00052007 flw ft0,0(a0) 8000014c: 00452087 flw ft1,4(a0) 80000150: 00852107 flw ft2,8(a0) 80000154: 00c52683 lw a3,12(a0) 80000158: a0100553 fle.s a0,ft0,ft1 8000015c: 001015f3 fsflags a1,zero 80000160: 00000613 li a2,0 80000164: 26d51e63 bne a0,a3,800003e0 <fail> 80000168: 26c59c63 bne a1,a2,800003e0 <fail> 8000016c <test_4>: 8000016c: 00400193 li gp,4 80000170: 00002517 auipc a0,0x2 80000174: eb050513 addi a0,a0,-336 # 80002020 <test_4_data> 80000178: 00052007 flw ft0,0(a0) 8000017c: 00452087 flw ft1,4(a0) 80000180: 00852107 flw ft2,8(a0) 80000184: 00c52683 lw a3,12(a0) 80000188: a0101553 flt.s a0,ft0,ft1 8000018c: 001015f3 fsflags a1,zero 80000190: 00000613 li a2,0 80000194: 24d51663 bne a0,a3,800003e0 <fail> 80000198: 24c59463 bne a1,a2,800003e0 <fail> 8000019c <test_5>: 8000019c: 00500193 li gp,5 800001a0: 00002517 auipc a0,0x2 800001a4: e9050513 addi a0,a0,-368 # 80002030 <test_5_data> 800001a8: 00052007 flw ft0,0(a0) 800001ac: 00452087 flw ft1,4(a0) 800001b0: 00852107 flw ft2,8(a0) 800001b4: 00c52683 lw a3,12(a0) 800001b8: a0102553 feq.s a0,ft0,ft1 800001bc: 001015f3 fsflags a1,zero 800001c0: 00000613 li a2,0 800001c4: 20d51e63 bne a0,a3,800003e0 <fail> 800001c8: 20c59c63 bne a1,a2,800003e0 <fail> 800001cc <test_6>: 800001cc: 00600193 li gp,6 800001d0: 00002517 auipc a0,0x2 800001d4: e7050513 addi a0,a0,-400 # 80002040 <test_6_data> 800001d8: 00052007 flw ft0,0(a0) 800001dc: 00452087 flw ft1,4(a0) 800001e0: 00852107 flw ft2,8(a0) 800001e4: 00c52683 lw a3,12(a0) 800001e8: a0100553 fle.s a0,ft0,ft1 800001ec: 001015f3 fsflags a1,zero 800001f0: 00000613 li a2,0 800001f4: 1ed51663 bne a0,a3,800003e0 <fail> 800001f8: 1ec59463 bne a1,a2,800003e0 <fail> 800001fc <test_7>: 800001fc: 00700193 li gp,7 80000200: 00002517 auipc a0,0x2 80000204: e5050513 addi a0,a0,-432 # 80002050 <test_7_data> 80000208: 00052007 flw ft0,0(a0) 8000020c: 00452087 flw ft1,4(a0) 80000210: 00852107 flw ft2,8(a0) 80000214: 00c52683 lw a3,12(a0) 80000218: a0101553 flt.s a0,ft0,ft1 8000021c: 001015f3 fsflags a1,zero 80000220: 00000613 li a2,0 80000224: 1ad51e63 bne a0,a3,800003e0 <fail> 80000228: 1ac59c63 bne a1,a2,800003e0 <fail> 8000022c <test_8>: 8000022c: 00800193 li gp,8 80000230: 00002517 auipc a0,0x2 80000234: e3050513 addi a0,a0,-464 # 80002060 <test_8_data> 80000238: 00052007 flw ft0,0(a0) 8000023c: 00452087 flw ft1,4(a0) 80000240: 00852107 flw ft2,8(a0) 80000244: 00c52683 lw a3,12(a0) 80000248: a0102553 feq.s a0,ft0,ft1 8000024c: 001015f3 fsflags a1,zero 80000250: 00000613 li a2,0 80000254: 18d51663 bne a0,a3,800003e0 <fail> 80000258: 18c59463 bne a1,a2,800003e0 <fail> 8000025c <test_9>: 8000025c: 00900193 li gp,9 80000260: 00002517 auipc a0,0x2 80000264: e1050513 addi a0,a0,-496 # 80002070 <test_9_data> 80000268: 00052007 flw ft0,0(a0) 8000026c: 00452087 flw ft1,4(a0) 80000270: 00852107 flw ft2,8(a0) 80000274: 00c52683 lw a3,12(a0) 80000278: a0102553 feq.s a0,ft0,ft1 8000027c: 001015f3 fsflags a1,zero 80000280: 00000613 li a2,0 80000284: 14d51e63 bne a0,a3,800003e0 <fail> 80000288: 14c59c63 bne a1,a2,800003e0 <fail> 8000028c <test_10>: 8000028c: 00a00193 li gp,10 80000290: 00002517 auipc a0,0x2 80000294: df050513 addi a0,a0,-528 # 80002080 <test_10_data> 80000298: 00052007 flw ft0,0(a0) 8000029c: 00452087 flw ft1,4(a0) 800002a0: 00852107 flw ft2,8(a0) 800002a4: 00c52683 lw a3,12(a0) 800002a8: a0102553 feq.s a0,ft0,ft1 800002ac: 001015f3 fsflags a1,zero 800002b0: 01000613 li a2,16 800002b4: 12d51663 bne a0,a3,800003e0 <fail> 800002b8: 12c59463 bne a1,a2,800003e0 <fail> 800002bc <test_11>: 800002bc: 00b00193 li gp,11 800002c0: 00002517 auipc a0,0x2 800002c4: dd050513 addi a0,a0,-560 # 80002090 <test_11_data> 800002c8: 00052007 flw ft0,0(a0) 800002cc: 00452087 flw ft1,4(a0) 800002d0: 00852107 flw ft2,8(a0) 800002d4: 00c52683 lw a3,12(a0) 800002d8: a0101553 flt.s a0,ft0,ft1 800002dc: 001015f3 fsflags a1,zero 800002e0: 01000613 li a2,16 800002e4: 0ed51e63 bne a0,a3,800003e0 <fail> 800002e8: 0ec59c63 bne a1,a2,800003e0 <fail> 800002ec <test_12>: 800002ec: 00c00193 li gp,12 800002f0: 00002517 auipc a0,0x2 800002f4: db050513 addi a0,a0,-592 # 800020a0 <test_12_data> 800002f8: 00052007 flw ft0,0(a0) 800002fc: 00452087 flw ft1,4(a0) 80000300: 00852107 flw ft2,8(a0) 80000304: 00c52683 lw a3,12(a0) 80000308: a0101553 flt.s a0,ft0,ft1 8000030c: 001015f3 fsflags a1,zero 80000310: 01000613 li a2,16 80000314: 0cd51663 bne a0,a3,800003e0 <fail> 80000318: 0cc59463 bne a1,a2,800003e0 <fail> 8000031c <test_13>: 8000031c: 00d00193 li gp,13 80000320: 00002517 auipc a0,0x2 80000324: d9050513 addi a0,a0,-624 # 800020b0 <test_13_data> 80000328: 00052007 flw ft0,0(a0) 8000032c: 00452087 flw ft1,4(a0) 80000330: 00852107 flw ft2,8(a0) 80000334: 00c52683 lw a3,12(a0) 80000338: a0101553 flt.s a0,ft0,ft1 8000033c: 001015f3 fsflags a1,zero 80000340: 01000613 li a2,16 80000344: 08d51e63 bne a0,a3,800003e0 <fail> 80000348: 08c59c63 bne a1,a2,800003e0 <fail> 8000034c <test_14>: 8000034c: 00e00193 li gp,14 80000350: 00002517 auipc a0,0x2 80000354: d7050513 addi a0,a0,-656 # 800020c0 <test_14_data> 80000358: 00052007 flw ft0,0(a0) 8000035c: 00452087 flw ft1,4(a0) 80000360: 00852107 flw ft2,8(a0) 80000364: 00c52683 lw a3,12(a0) 80000368: a0100553 fle.s a0,ft0,ft1 8000036c: 001015f3 fsflags a1,zero 80000370: 01000613 li a2,16 80000374: 06d51663 bne a0,a3,800003e0 <fail> 80000378: 06c59463 bne a1,a2,800003e0 <fail> 8000037c <test_15>: 8000037c: 00f00193 li gp,15 80000380: 00002517 auipc a0,0x2 80000384: d5050513 addi a0,a0,-688 # 800020d0 <test_15_data> 80000388: 00052007 flw ft0,0(a0) 8000038c: 00452087 flw ft1,4(a0) 80000390: 00852107 flw ft2,8(a0) 80000394: 00c52683 lw a3,12(a0) 80000398: a0100553 fle.s a0,ft0,ft1 8000039c: 001015f3 fsflags a1,zero 800003a0: 01000613 li a2,16 800003a4: 02d51e63 bne a0,a3,800003e0 <fail> 800003a8: 02c59c63 bne a1,a2,800003e0 <fail> 800003ac <test_16>: 800003ac: 01000193 li gp,16 800003b0: 00002517 auipc a0,0x2 800003b4: d3050513 addi a0,a0,-720 # 800020e0 <test_16_data> 800003b8: 00052007 flw ft0,0(a0) 800003bc: 00452087 flw ft1,4(a0) 800003c0: 00852107 flw ft2,8(a0) 800003c4: 00c52683 lw a3,12(a0) 800003c8: a0100553 fle.s a0,ft0,ft1 800003cc: 001015f3 fsflags a1,zero 800003d0: 01000613 li a2,16 800003d4: 00d51663 bne a0,a3,800003e0 <fail> 800003d8: 00c59463 bne a1,a2,800003e0 <fail> 800003dc: 00301c63 bne zero,gp,800003f4 <pass> 800003e0 <fail>: 800003e0: 0ff0000f fence 800003e4: 00018063 beqz gp,800003e4 <fail+0x4> 800003e8: 00119193 slli gp,gp,0x1 800003ec: 0011e193 ori gp,gp,1 800003f0: 00000073 ecall 800003f4 <pass>: 800003f4: 0ff0000f fence 800003f8: 00100193 li gp,1 800003fc: 00000073 ecall 80000400: c0001073 unimp Disassembly of section .data: 80002000 <test_2_data>: 80002000: bfae147b 0xbfae147b 80002004: bfae147b 0xbfae147b 80002008: 0000 unimp 8000200a: 0000 unimp 8000200c: 0001 nop 8000200e: 0000 unimp 80002010 <test_3_data>: 80002010: bfae147b 0xbfae147b 80002014: bfae147b 0xbfae147b 80002018: 0000 unimp 8000201a: 0000 unimp 8000201c: 0001 nop 8000201e: 0000 unimp 80002020 <test_4_data>: 80002020: bfae147b 0xbfae147b 80002024: bfae147b 0xbfae147b 80002028: 0000 unimp 8000202a: 0000 unimp 8000202c: 0000 unimp 8000202e: 0000 unimp 80002030 <test_5_data>: 80002030: 5c29 li s8,-22 80002032: 147bbfaf 0x147bbfaf 80002036: bfae fsd fa1,504(sp) 80002038: 0000 unimp 8000203a: 0000 unimp 8000203c: 0000 unimp 8000203e: 0000 unimp 80002040 <test_6_data>: 80002040: 5c29 li s8,-22 80002042: 147bbfaf 0x147bbfaf 80002046: bfae fsd fa1,504(sp) 80002048: 0000 unimp 8000204a: 0000 unimp 8000204c: 0001 nop 8000204e: 0000 unimp 80002050 <test_7_data>: 80002050: 5c29 li s8,-22 80002052: 147bbfaf 0x147bbfaf 80002056: bfae fsd fa1,504(sp) 80002058: 0000 unimp 8000205a: 0000 unimp 8000205c: 0001 nop 8000205e: 0000 unimp 80002060 <test_8_data>: 80002060: ffff 0xffff 80002062: 7fff 0x7fff 80002064: 0000 unimp 80002066: 0000 unimp 80002068: 0000 unimp 8000206a: 0000 unimp 8000206c: 0000 unimp 8000206e: 0000 unimp 80002070 <test_9_data>: 80002070: ffff 0xffff 80002072: 7fff 0x7fff 80002074: ffff 0xffff 80002076: 7fff 0x7fff 80002078: 0000 unimp 8000207a: 0000 unimp 8000207c: 0000 unimp 8000207e: 0000 unimp 80002080 <test_10_data>: 80002080: 0001 nop 80002082: 7f80 flw fs0,56(a5) 80002084: 0000 unimp 80002086: 0000 unimp 80002088: 0000 unimp 8000208a: 0000 unimp 8000208c: 0000 unimp 8000208e: 0000 unimp 80002090 <test_11_data>: 80002090: ffff 0xffff 80002092: 7fff 0x7fff 80002094: 0000 unimp 80002096: 0000 unimp 80002098: 0000 unimp 8000209a: 0000 unimp 8000209c: 0000 unimp 8000209e: 0000 unimp 800020a0 <test_12_data>: 800020a0: ffff 0xffff 800020a2: 7fff 0x7fff 800020a4: ffff 0xffff 800020a6: 7fff 0x7fff 800020a8: 0000 unimp 800020aa: 0000 unimp 800020ac: 0000 unimp 800020ae: 0000 unimp 800020b0 <test_13_data>: 800020b0: 0001 nop 800020b2: 7f80 flw fs0,56(a5) 800020b4: 0000 unimp 800020b6: 0000 unimp 800020b8: 0000 unimp 800020ba: 0000 unimp 800020bc: 0000 unimp 800020be: 0000 unimp 800020c0 <test_14_data>: 800020c0: ffff 0xffff 800020c2: 7fff 0x7fff 800020c4: 0000 unimp 800020c6: 0000 unimp 800020c8: 0000 unimp 800020ca: 0000 unimp 800020cc: 0000 unimp 800020ce: 0000 unimp 800020d0 <test_15_data>: 800020d0: ffff 0xffff 800020d2: 7fff 0x7fff 800020d4: ffff 0xffff 800020d6: 7fff 0x7fff 800020d8: 0000 unimp 800020da: 0000 unimp 800020dc: 0000 unimp 800020de: 0000 unimp 800020e0 <test_16_data>: 800020e0: 0001 nop 800020e2: 7f80 flw fs0,56(a5) 800020e4: 0000 unimp 800020e6: 0000 unimp 800020e8: 0000 unimp 800020ea: 0000 unimp 800020ec: 0000 unimp 800020ee: 0000 unimp

{ "language": "Assembly" }

vasm is a portable and retargetable assembler to create linkable objects in various formats or absolute code. Currently the following CPUs are officially supported: M680x0 family (including M6888x, M68851 and CPU32) ColdFire family (all models of V2, V3, V4, V4e) 80x86 family (IA32 8/16/32 bit, using MIT-syntax) PowerPC family (POWER, 40x, 440, 460, 6xx, 7xx, 860, Book-E, e300 and e500) ARM (architecture ARMv1 to ARMv4, including THUMB mode) Jaguar RISC (GPU and DSP instruction sets) Z80 family (Z80, 8080, GBZ80, 64180, RCM2/3/4k) C16x/ST10 6502 & 6800 family (6800, 6801, 6803, 68HC11) QNICE (elegant 16-bit FPGA CPU) TR3200 (virtual CPU from 0x10c) Raspberry-Pi VideoCore IV These syntax flavours are supported: Standard MIT (GNU-as style) syntax Motorola/Freescale 68k syntax (Devpac compatible) Atari MadMac syntax (6502, 68k, Jaguar) Old 8-bit style syntax WWW: http://sun.hasenbraten.de/vasm/

{ "language": "Assembly" }

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{ "language": "Assembly" }

// Copyright 2009 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build !gccgo #include "textflag.h" // // System call support for AMD64, DragonFly // // Just jump to package syscall's implementation for all these functions. // The runtime may know about them. TEXT ·Syscall(SB),NOSPLIT,$0-56 JMP syscall·Syscall(SB) TEXT ·Syscall6(SB),NOSPLIT,$0-80 JMP syscall·Syscall6(SB) TEXT ·Syscall9(SB),NOSPLIT,$0-104 JMP syscall·Syscall9(SB) TEXT ·RawSyscall(SB),NOSPLIT,$0-56 JMP syscall·RawSyscall(SB) TEXT ·RawSyscall6(SB),NOSPLIT,$0-80 JMP syscall·RawSyscall6(SB)

{ "language": "Assembly" }

; RUN: llc < %s -mtriple=i386-apple-darwin -no-integrated-as ; rdar://6781755 ; PR3934 %0 = type { i32, i32 } ; type %0 define void @bn_sqr_comba8(i32* nocapture %r, i32* %a) nounwind { entry: %asmtmp23 = tail call %0 asm "mulq $3", "={ax},={dx},{ax},*m,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32* %a) nounwind ; <%0> [#uses=1] %asmresult25 = extractvalue %0 %asmtmp23, 1 ; <i32> [#uses=1] %asmtmp26 = tail call %0 asm "addq $0,$0; adcq $2,$1", "={dx},=r,imr,0,1,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32 %asmresult25, i32 0) nounwind ; <%0> [#uses=1] %asmresult27 = extractvalue %0 %asmtmp26, 0 ; <i32> [#uses=1] %asmtmp29 = tail call %0 asm "addq $0,$0; adcq $2,$1", "={ax},={dx},imr,0,1,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32 0, i32 %asmresult27) nounwind ; <%0> [#uses=0] ret void }

{ "language": "Assembly" }

#!/bin/bash # SPDX-License-Identifier: GPL-2.0 # # Test various interface configuration scenarios. Observe that configurations # deemed valid by mlxsw succeed, invalid configurations fail and that no traces # are produced. To prevent the test from passing in case traces are produced, # the user can set the 'kernel.panic_on_warn' and 'kernel.panic_on_oops' # sysctls in its environment. lib_dir=$(dirname $0)/../../../net/forwarding ALL_TESTS=" rif_set_addr_test rif_vrf_set_addr_test rif_inherit_bridge_addr_test rif_non_inherit_bridge_addr_test vlan_interface_deletion_test bridge_deletion_test bridge_vlan_flags_test vlan_1_test lag_bridge_upper_test duplicate_vlans_test vlan_rif_refcount_test subport_rif_refcount_test vlan_dev_deletion_test lag_unlink_slaves_test lag_dev_deletion_test vlan_interface_uppers_test bridge_extern_learn_test neigh_offload_test nexthop_offload_test devlink_reload_test " NUM_NETIFS=2 : ${TIMEOUT:=20000} # ms source $lib_dir/lib.sh source $lib_dir/devlink_lib.sh setup_prepare() { swp1=${NETIFS[p1]} swp2=${NETIFS[p2]} ip link set dev $swp1 up ip link set dev $swp2 up } cleanup() { pre_cleanup ip link set dev $swp2 down ip link set dev $swp1 down } rif_set_addr_test() { local swp1_mac=$(mac_get $swp1) local swp2_mac=$(mac_get $swp2) RET=0 # $swp1 and $swp2 likely got their IPv6 local addresses already, but # here we need to test the transition to RIF. ip addr flush dev $swp1 ip addr flush dev $swp2 sleep .1 ip addr add dev $swp1 192.0.2.1/28 check_err $? ip link set dev $swp1 addr 00:11:22:33:44:55 check_err $? # IP address enablement should be rejected if the MAC address prefix # doesn't match other RIFs. ip addr add dev $swp2 192.0.2.2/28 &>/dev/null check_fail $? "IP address addition passed for a device with a wrong MAC" ip addr add dev $swp2 192.0.2.2/28 2>&1 >/dev/null \ | grep -q mlxsw_spectrum check_err $? "no extack for IP address addition" ip link set dev $swp2 addr 00:11:22:33:44:66 check_err $? ip addr add dev $swp2 192.0.2.2/28 &>/dev/null check_err $? # Change of MAC address of a RIF should be forbidden if the new MAC # doesn't share the prefix with other MAC addresses. ip link set dev $swp2 addr 00:11:22:33:00:66 &>/dev/null check_fail $? "change of MAC address passed for a wrong MAC" ip link set dev $swp2 addr 00:11:22:33:00:66 2>&1 >/dev/null \ | grep -q mlxsw_spectrum check_err $? "no extack for MAC address change" log_test "RIF - bad MAC change" ip addr del dev $swp2 192.0.2.2/28 ip addr del dev $swp1 192.0.2.1/28 ip link set dev $swp2 addr $swp2_mac ip link set dev $swp1 addr $swp1_mac } rif_vrf_set_addr_test() { # Test that it is possible to set an IP address on a VRF upper despite # its random MAC address. RET=0 ip link add name vrf-test type vrf table 10 ip link set dev $swp1 master vrf-test ip -4 address add 192.0.2.1/24 dev vrf-test check_err $? "failed to set IPv4 address on VRF" ip -6 address add 2001:db8:1::1/64 dev vrf-test check_err $? "failed to set IPv6 address on VRF" log_test "RIF - setting IP address on VRF" ip link del dev vrf-test } rif_inherit_bridge_addr_test() { RET=0 # Create first RIF ip addr add dev $swp1 192.0.2.1/28 check_err $? # Create a FID RIF ip link add name br1 up type bridge vlan_filtering 0 ip link set dev $swp2 master br1 ip addr add dev br1 192.0.2.17/28 check_err $? # Prepare a device with a low MAC address ip link add name d up type dummy ip link set dev d addr 00:11:22:33:44:55 # Attach the device to br1. That prompts bridge address change, which # should be vetoed, thus preventing the attachment. ip link set dev d master br1 &>/dev/null check_fail $? "Device with low MAC was permitted to attach a bridge with RIF" ip link set dev d master br1 2>&1 >/dev/null \ | grep -q mlxsw_spectrum check_err $? "no extack for bridge attach rejection" ip link set dev $swp2 addr 00:11:22:33:44:55 &>/dev/null check_fail $? "Changing swp2's MAC address permitted" ip link set dev $swp2 addr 00:11:22:33:44:55 2>&1 >/dev/null \ | grep -q mlxsw_spectrum check_err $? "no extack for bridge port MAC address change rejection" log_test "RIF - attach port with bad MAC to bridge" ip link del dev d ip link del dev br1 ip addr del dev $swp1 192.0.2.1/28 } rif_non_inherit_bridge_addr_test() { local swp2_mac=$(mac_get $swp2) RET=0 # Create first RIF ip addr add dev $swp1 192.0.2.1/28 check_err $? # Create a FID RIF ip link add name br1 up type bridge vlan_filtering 0 ip link set dev br1 addr $swp2_mac ip link set dev $swp2 master br1 ip addr add dev br1 192.0.2.17/28 check_err $? # Prepare a device with a low MAC address ip link add name d up type dummy ip link set dev d addr 00:11:22:33:44:55 # Attach the device to br1. Since the bridge address was set, it should # work. ip link set dev d master br1 &>/dev/null check_err $? "Could not attach a device with low MAC to a bridge with RIF" # Port MAC address change should be allowed for a bridge with set MAC. ip link set dev $swp2 addr 00:11:22:33:44:55 check_err $? "Changing swp2's MAC address not permitted" log_test "RIF - attach port with bad MAC to bridge with set MAC" ip link set dev $swp2 addr $swp2_mac ip link del dev d ip link del dev br1 ip addr del dev $swp1 192.0.2.1/28 } vlan_interface_deletion_test() { # Test that when a VLAN interface is deleted, its associated router # interface (RIF) is correctly deleted and not leaked. See commit # c360867ec46a ("mlxsw: spectrum: Delete RIF when VLAN device is # removed") for more details RET=0 ip link add name br0 type bridge vlan_filtering 1 ip link set dev $swp1 master br0 ip link add link br0 name br0.10 type vlan id 10 ip -6 address add 2001:db8:1::1/64 dev br0.10 ip link del dev br0.10 # If we leaked the previous RIF, then this should produce a trace ip link add link br0 name br0.20 type vlan id 20 ip -6 address add 2001:db8:1::1/64 dev br0.20 ip link del dev br0.20 log_test "vlan interface deletion" ip link del dev br0 } bridge_deletion_test() { # Test that when a bridge with VLAN interfaces is deleted, we correctly # delete the associated RIFs. See commit 602b74eda813 ("mlxsw: # spectrum_switchdev: Do not leak RIFs when removing bridge") for more # details RET=0 ip link add name br0 type bridge vlan_filtering 1 ip link set dev $swp1 master br0 ip -6 address add 2001:db8::1/64 dev br0 ip link add link br0 name br0.10 type vlan id 10 ip -6 address add 2001:db8:1::1/64 dev br0.10 ip link add link br0 name br0.20 type vlan id 20 ip -6 address add 2001:db8:2::1/64 dev br0.20 ip link del dev br0 # If we leaked previous RIFs, then this should produce a trace ip -6 address add 2001:db8:1::1/64 dev $swp1 ip -6 address del 2001:db8:1::1/64 dev $swp1 log_test "bridge deletion" } bridge_vlan_flags_test() { # Test that when bridge VLAN flags are toggled, we do not take # unnecessary references on related structs. See commit 9e25826ffc94 # ("mlxsw: spectrum_switchdev: Fix port_vlan refcounting") for more # details RET=0 ip link add name br0 type bridge vlan_filtering 1 ip link set dev $swp1 master br0 bridge vlan add vid 10 dev $swp1 pvid untagged bridge vlan add vid 10 dev $swp1 untagged bridge vlan add vid 10 dev $swp1 pvid bridge vlan add vid 10 dev $swp1 ip link del dev br0 # If we did not handle references correctly, then this should produce a # trace devlink dev reload "$DEVLINK_DEV" # Allow netdevices to be re-created following the reload sleep 20 log_test "bridge vlan flags" } vlan_1_test() { # Test that VLAN 1 can be configured over mlxsw ports. In the past it # was used internally for untagged traffic. See commit 47bf9df2e820 # ("mlxsw: spectrum: Forbid creation of VLAN 1 over port/LAG") for more # details RET=0 ip link add link $swp1 name $swp1.1 type vlan id 1 check_err $? "did not manage to create vlan 1 when should" log_test "vlan 1" ip link del dev $swp1.1 } lag_bridge_upper_test() { # Test that ports cannot be enslaved to LAG devices that have uppers # and that failure is handled gracefully. See commit b3529af6bb0d # ("spectrum: Reference count VLAN entries") for more details RET=0 ip link add name bond1 type bond mode 802.3ad ip link add name br0 type bridge vlan_filtering 1 ip link set dev bond1 master br0 ip link set dev $swp1 down ip link set dev $swp1 master bond1 &> /dev/null check_fail $? "managed to enslave port to lag when should not" # This might generate a trace, if we did not handle the failure # correctly ip -6 address add 2001:db8:1::1/64 dev $swp1 ip -6 address del 2001:db8:1::1/64 dev $swp1 log_test "lag with bridge upper" ip link del dev br0 ip link del dev bond1 } duplicate_vlans_test() { # Test that on a given port a VLAN is only used once. Either as VLAN # in a VLAN-aware bridge or as a VLAN device RET=0 ip link add name br0 type bridge vlan_filtering 1 ip link set dev $swp1 master br0 bridge vlan add vid 10 dev $swp1 ip link add link $swp1 name $swp1.10 type vlan id 10 &> /dev/null check_fail $? "managed to create vlan device when should not" bridge vlan del vid 10 dev $swp1 ip link add link $swp1 name $swp1.10 type vlan id 10 check_err $? "did not manage to create vlan device when should" bridge vlan add vid 10 dev $swp1 &> /dev/null check_fail $? "managed to add bridge vlan when should not" log_test "duplicate vlans" ip link del dev $swp1.10 ip link del dev br0 } vlan_rif_refcount_test() { # Test that RIFs representing VLAN interfaces are not affected from # ports member in the VLAN. We use the offload indication on routes # configured on the RIF to understand if it was created / destroyed RET=0 ip link add name br0 type bridge vlan_filtering 1 ip link set dev $swp1 master br0 ip link set dev $swp1 up ip link set dev br0 up ip link add link br0 name br0.10 up type vlan id 10 ip -6 address add 2001:db8:1::1/64 dev br0.10 busywait "$TIMEOUT" wait_for_offload \ ip -6 route get fibmatch 2001:db8:1::2 dev br0.10 check_err $? "vlan rif was not created before adding port to vlan" bridge vlan add vid 10 dev $swp1 busywait "$TIMEOUT" wait_for_offload \ ip -6 route get fibmatch 2001:db8:1::2 dev br0.10 check_err $? "vlan rif was destroyed after adding port to vlan" bridge vlan del vid 10 dev $swp1 busywait "$TIMEOUT" wait_for_offload \ ip -6 route get fibmatch 2001:db8:1::2 dev br0.10 check_err $? "vlan rif was destroyed after removing port from vlan" ip link set dev $swp1 nomaster busywait "$TIMEOUT" not wait_for_offload \ ip -6 route get fibmatch 2001:db8:1::2 dev br0.10 check_err $? "vlan rif was not destroyed after unlinking port from bridge" log_test "vlan rif refcount" ip link del dev br0.10 ip link set dev $swp1 down ip link del dev br0 } subport_rif_refcount_test() { # Test that RIFs representing upper devices of physical ports are # reference counted correctly and destroyed when should. We use the # offload indication on routes configured on the RIF to understand if # it was created / destroyed RET=0 ip link add name bond1 type bond mode 802.3ad ip link set dev $swp1 down ip link set dev $swp2 down ip link set dev $swp1 master bond1 ip link set dev $swp2 master bond1 ip link set dev bond1 up ip link add link bond1 name bond1.10 up type vlan id 10 ip -6 address add 2001:db8:1::1/64 dev bond1 ip -6 address add 2001:db8:2::1/64 dev bond1.10 busywait "$TIMEOUT" wait_for_offload \ ip -6 route get fibmatch 2001:db8:1::2 dev bond1 check_err $? "subport rif was not created on lag device" busywait "$TIMEOUT" wait_for_offload \ ip -6 route get fibmatch 2001:db8:2::2 dev bond1.10 check_err $? "subport rif was not created on vlan device" ip link set dev $swp1 nomaster busywait "$TIMEOUT" wait_for_offload \ ip -6 route get fibmatch 2001:db8:1::2 dev bond1 check_err $? "subport rif of lag device was destroyed when should not" busywait "$TIMEOUT" wait_for_offload \ ip -6 route get fibmatch 2001:db8:2::2 dev bond1.10 check_err $? "subport rif of vlan device was destroyed when should not" ip link set dev $swp2 nomaster busywait "$TIMEOUT" not wait_for_offload \ ip -6 route get fibmatch 2001:db8:1::2 dev bond1 check_err $? "subport rif of lag device was not destroyed when should" busywait "$TIMEOUT" not wait_for_offload \ ip -6 route get fibmatch 2001:db8:2::2 dev bond1.10 check_err $? "subport rif of vlan device was not destroyed when should" log_test "subport rif refcount" ip link del dev bond1.10 ip link del dev bond1 } vlan_dev_deletion_test() { # Test that VLAN devices are correctly deleted / unlinked when enslaved # to bridge RET=0 ip link add name br10 type bridge ip link add name br20 type bridge ip link add name br30 type bridge ip link add link $swp1 name $swp1.10 type vlan id 10 ip link add link $swp1 name $swp1.20 type vlan id 20 ip link add link $swp1 name $swp1.30 type vlan id 30 ip link set dev $swp1.10 master br10 ip link set dev $swp1.20 master br20 ip link set dev $swp1.30 master br30 # If we did not handle the situation correctly, then these operations # might produce a trace ip link set dev $swp1.30 nomaster ip link del dev $swp1.20 # Deletion via ioctl uses different code paths from netlink vconfig rem $swp1.10 &> /dev/null log_test "vlan device deletion" ip link del dev $swp1.30 ip link del dev br30 ip link del dev br20 ip link del dev br10 } lag_create() { ip link add name bond1 type bond mode 802.3ad ip link set dev $swp1 down ip link set dev $swp2 down ip link set dev $swp1 master bond1 ip link set dev $swp2 master bond1 ip link add link bond1 name bond1.10 type vlan id 10 ip link add link bond1 name bond1.20 type vlan id 20 ip link add name br0 type bridge vlan_filtering 1 ip link set dev bond1 master br0 ip link add name br10 type bridge ip link set dev bond1.10 master br10 ip link add name br20 type bridge ip link set dev bond1.20 master br20 } lag_unlink_slaves_test() { # Test that ports are correctly unlinked from their LAG master, when # the LAG and its VLAN uppers are enslaved to bridges RET=0 lag_create ip link set dev $swp1 nomaster check_err $? "lag slave $swp1 was not unlinked from master" ip link set dev $swp2 nomaster check_err $? "lag slave $swp2 was not unlinked from master" # Try to configure corresponding VLANs as router interfaces ip -6 address add 2001:db8:1::1/64 dev $swp1 check_err $? "failed to configure ip address on $swp1" ip link add link $swp1 name $swp1.10 type vlan id 10 ip -6 address add 2001:db8:10::1/64 dev $swp1.10 check_err $? "failed to configure ip address on $swp1.10" ip link add link $swp1 name $swp1.20 type vlan id 20 ip -6 address add 2001:db8:20::1/64 dev $swp1.20 check_err $? "failed to configure ip address on $swp1.20" log_test "lag slaves unlinking" ip link del dev $swp1.20 ip link del dev $swp1.10 ip address flush dev $swp1 ip link del dev br20 ip link del dev br10 ip link del dev br0 ip link del dev bond1 } lag_dev_deletion_test() { # Test that LAG device is correctly deleted, when the LAG and its VLAN # uppers are enslaved to bridges RET=0 lag_create ip link del dev bond1 log_test "lag device deletion" ip link del dev br20 ip link del dev br10 ip link del dev br0 } vlan_interface_uppers_test() { # Test that uppers of a VLAN interface are correctly sanitized RET=0 ip link add name br0 type bridge vlan_filtering 1 ip link set dev $swp1 master br0 ip link add link br0 name br0.10 type vlan id 10 ip link add link br0.10 name macvlan0 \ type macvlan mode private &> /dev/null check_fail $? "managed to create a macvlan when should not" ip -6 address add 2001:db8:1::1/64 dev br0.10 ip link add link br0.10 name macvlan0 type macvlan mode private check_err $? "did not manage to create a macvlan when should" ip link del dev macvlan0 ip link add name vrf-test type vrf table 10 ip link set dev br0.10 master vrf-test check_err $? "did not manage to enslave vlan interface to vrf" ip link del dev vrf-test ip link add name br-test type bridge ip link set dev br0.10 master br-test &> /dev/null check_fail $? "managed to enslave vlan interface to bridge when should not" ip link del dev br-test log_test "vlan interface uppers" ip link del dev br0 } bridge_extern_learn_test() { # Test that externally learned entries added from user space are # marked as offloaded RET=0 ip link add name br0 type bridge ip link set dev $swp1 master br0 bridge fdb add de:ad:be:ef:13:37 dev $swp1 master extern_learn busywait "$TIMEOUT" wait_for_offload \ bridge fdb show brport $swp1 de:ad:be:ef:13:37 check_err $? "fdb entry not marked as offloaded when should" log_test "externally learned fdb entry" ip link del dev br0 } neigh_offload_test() { # Test that IPv4 and IPv6 neighbour entries are marked as offloaded RET=0 ip -4 address add 192.0.2.1/24 dev $swp1 ip -6 address add 2001:db8:1::1/64 dev $swp1 ip -4 neigh add 192.0.2.2 lladdr de:ad:be:ef:13:37 nud perm dev $swp1 ip -6 neigh add 2001:db8:1::2 lladdr de:ad:be:ef:13:37 nud perm \ dev $swp1 busywait "$TIMEOUT" wait_for_offload \ ip -4 neigh show dev $swp1 192.0.2.2 check_err $? "ipv4 neigh entry not marked as offloaded when should" busywait "$TIMEOUT" wait_for_offload \ ip -6 neigh show dev $swp1 2001:db8:1::2 check_err $? "ipv6 neigh entry not marked as offloaded when should" log_test "neighbour offload indication" ip -6 neigh del 2001:db8:1::2 dev $swp1 ip -4 neigh del 192.0.2.2 dev $swp1 ip -6 address del 2001:db8:1::1/64 dev $swp1 ip -4 address del 192.0.2.1/24 dev $swp1 } nexthop_offload_test() { # Test that IPv4 and IPv6 nexthops are marked as offloaded RET=0 sysctl_set net.ipv6.conf.$swp2.keep_addr_on_down 1 simple_if_init $swp1 192.0.2.1/24 2001:db8:1::1/64 simple_if_init $swp2 192.0.2.2/24 2001:db8:1::2/64 setup_wait ip -4 route add 198.51.100.0/24 vrf v$swp1 \ nexthop via 192.0.2.2 dev $swp1 ip -6 route add 2001:db8:2::/64 vrf v$swp1 \ nexthop via 2001:db8:1::2 dev $swp1 busywait "$TIMEOUT" wait_for_offload \ ip -4 route show 198.51.100.0/24 vrf v$swp1 check_err $? "ipv4 nexthop not marked as offloaded when should" busywait "$TIMEOUT" wait_for_offload \ ip -6 route show 2001:db8:2::/64 vrf v$swp1 check_err $? "ipv6 nexthop not marked as offloaded when should" ip link set dev $swp2 down sleep 1 busywait "$TIMEOUT" not wait_for_offload \ ip -4 route show 198.51.100.0/24 vrf v$swp1 check_err $? "ipv4 nexthop marked as offloaded when should not" busywait "$TIMEOUT" not wait_for_offload \ ip -6 route show 2001:db8:2::/64 vrf v$swp1 check_err $? "ipv6 nexthop marked as offloaded when should not" ip link set dev $swp2 up setup_wait busywait "$TIMEOUT" wait_for_offload \ ip -4 route show 198.51.100.0/24 vrf v$swp1 check_err $? "ipv4 nexthop not marked as offloaded after neigh add" busywait "$TIMEOUT" wait_for_offload \ ip -6 route show 2001:db8:2::/64 vrf v$swp1 check_err $? "ipv6 nexthop not marked as offloaded after neigh add" log_test "nexthop offload indication" ip -6 route del 2001:db8:2::/64 vrf v$swp1 ip -4 route del 198.51.100.0/24 vrf v$swp1 simple_if_fini $swp2 192.0.2.2/24 2001:db8:1::2/64 simple_if_fini $swp1 192.0.2.1/24 2001:db8:1::1/64 sysctl_restore net.ipv6.conf.$swp2.keep_addr_on_down } devlink_reload_test() { # Test that after executing all the above configuration tests, a # devlink reload can be performed without errors RET=0 devlink dev reload "$DEVLINK_DEV" check_err $? "devlink reload failed" log_test "devlink reload - last test" sleep 20 } trap cleanup EXIT setup_prepare setup_wait tests_run exit $EXIT_STATUS

{ "language": "Assembly" }

/* * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ #include <asm-offsets.h> #include <config.h> #include <linux/linkage.h> #include <asm/arcregs.h> ENTRY(_start) ; ARCompact devices are not supposed to be SMP so master/slave check ; makes no sense. #ifdef CONFIG_ISA_ARCV2 ; Non-masters will be halted immediately, they might be kicked later ; by platform code right before passing control to the Linux kernel ; in bootm.c:boot_jump_linux(). lr r5, [identity] lsr r5, r5, 8 bmsk r5, r5, 7 cmp r5, 0 mov.nz r0, r5 bz .Lmaster_proceed flag 1 nop nop nop .Lmaster_proceed: #endif /* Setup interrupt vector base that matches "__text_start" */ sr __ivt_start, [ARC_AUX_INTR_VEC_BASE] ; Disable/enable I-cache according to configuration lr r5, [ARC_BCR_IC_BUILD] breq r5, 0, 1f ; I$ doesn't exist lr r5, [ARC_AUX_IC_CTRL] #ifndef CONFIG_SYS_ICACHE_OFF bclr r5, r5, 0 ; 0 - Enable, 1 is Disable #else bset r5, r5, 0 ; I$ exists, but is not used #endif sr r5, [ARC_AUX_IC_CTRL] 1: ; Disable/enable D-cache according to configuration lr r5, [ARC_BCR_DC_BUILD] breq r5, 0, 1f ; D$ doesn't exist lr r5, [ARC_AUX_DC_CTRL] bclr r5, r5, 6 ; Invalidate (discard w/o wback) #ifndef CONFIG_SYS_DCACHE_OFF bclr r5, r5, 0 ; Enable (+Inv) #else bset r5, r5, 0 ; Disable (+Inv) #endif sr r5, [ARC_AUX_DC_CTRL] 1: #ifdef CONFIG_ISA_ARCV2 ; Disable System-Level Cache (SLC) lr r5, [ARC_BCR_SLC] breq r5, 0, 1f ; SLC doesn't exist lr r5, [ARC_AUX_SLC_CTRL] bclr r5, r5, 6 ; Invalidate (discard w/o wback) bclr r5, r5, 0 ; Enable (+Inv) sr r5, [ARC_AUX_SLC_CTRL] 1: #endif /* Establish C runtime stack and frame */ mov %sp, CONFIG_SYS_INIT_SP_ADDR mov %fp, %sp /* Allocate reserved area from current top of stack */ mov %r0, %sp bl board_init_f_alloc_reserve /* Set stack below reserved area, adjust frame pointer accordingly */ mov %sp, %r0 mov %fp, %sp /* Initialize reserved area - note: r0 already contains address */ bl board_init_f_init_reserve /* Zero the one and only argument of "board_init_f" */ mov_s %r0, 0 j board_init_f ENDPROC(_start) /* * void board_init_f_r_trampoline(stack-pointer address) * * This "function" does not return, instead it continues in RAM * after relocating the monitor code. * * r0 = new stack-pointer */ ENTRY(board_init_f_r_trampoline) /* Set up the stack- and frame-pointers */ mov %sp, %r0 mov %fp, %sp /* Update position of intterupt vector table */ lr %r0, [ARC_AUX_INTR_VEC_BASE] ld %r1, [%r25, GD_RELOC_OFF] add %r0, %r0, %r1 sr %r0, [ARC_AUX_INTR_VEC_BASE] /* Re-enter U-Boot by calling board_init_f_r */ j board_init_f_r ENDPROC(board_init_f_r_trampoline)

{ "language": "Assembly" }

; --------------------------------------------------------------------------- ; Object 11 - GHZ bridge ; --------------------------------------------------------------------------- Bridge: moveq #0,d0 move.b obRoutine(a0),d0 move.w Bri_Index(pc,d0.w),d1 jmp Bri_Index(pc,d1.w) ; =========================================================================== Bri_Index: dc.w Bri_Main-Bri_Index, Bri_Action-Bri_Index dc.w Bri_Platform-Bri_Index, Bri_Delete-Bri_Index dc.w Bri_Delete-Bri_Index, Bri_Display-Bri_Index ; =========================================================================== Bri_Main: ; Routine 0 addq.b #2,obRoutine(a0) move.l #Map_Bri,obMap(a0) move.w #$438E,obGfx(a0) move.b #4,obRender(a0) move.b #3,obPriority(a0) move.b #$80,obActWid(a0) move.w obY(a0),d2 move.w obX(a0),d3 move.b 0(a0),d4 ; copy object number ($11) to d4 lea obSubtype(a0),a2 moveq #0,d1 move.b (a2),d1 ; copy bridge length to d1 move.b #0,(a2)+ ; clear bridge length move.w d1,d0 lsr.w #1,d0 lsl.w #4,d0 sub.w d0,d3 ; d3 is position of leftmost log subq.b #2,d1 bcs.s Bri_Action ; don't make more if bridge has only 1 log @buildloop: bsr.w FindFreeObj bne.s Bri_Action addq.b #1,obSubtype(a0) cmp.w obX(a0),d3 ; is this log the leftmost one? bne.s @notleftmost ; if not, branch addi.w #$10,d3 move.w d2,obY(a0) move.w d2,$3C(a0) move.w a0,d5 subi.w #$D000,d5 lsr.w #6,d5 andi.w #$7F,d5 move.b d5,(a2)+ addq.b #1,obSubtype(a0) @notleftmost: move.w a1,d5 subi.w #$D000,d5 lsr.w #6,d5 andi.w #$7F,d5 move.b d5,(a2)+ move.b #$A,obRoutine(a1) move.b d4,0(a1) ; load bridge object (d4 = $11) move.w d2,obY(a1) move.w d2,$3C(a1) move.w d3,obX(a1) move.l #Map_Bri,obMap(a1) move.w #$438E,obGfx(a1) move.b #4,obRender(a1) move.b #3,obPriority(a1) move.b #8,obActWid(a1) addi.w #$10,d3 dbf d1,@buildloop ; repeat d1 times (length of bridge) Bri_Action: ; Routine 2 bsr.s Bri_Solid tst.b $3E(a0) beq.s @display subq.b #4,$3E(a0) bsr.w Bri_Bend @display: bsr.w DisplaySprite bra.w Bri_ChkDel ; ||||||||||||||| S U B R O U T I N E ||||||||||||||||||||||||||||||||||||||| Bri_Solid: moveq #0,d1 move.b obSubtype(a0),d1 lsl.w #3,d1 move.w d1,d2 addq.w #8,d1 add.w d2,d2 lea (v_player).w,a1 tst.w obVelY(a1) bmi.w Plat_Exit move.w obX(a1),d0 sub.w obX(a0),d0 add.w d1,d0 bmi.w Plat_Exit cmp.w d2,d0 bcc.w Plat_Exit bra.s Plat_NoXCheck ; End of function Bri_Solid

{ "language": "Assembly" }

object_const_def const OLIVINETIMSHOUSE_TIM OlivineTimsHouse_MapScripts: def_scene_scripts def_callbacks Tim: faceplayer opentext trade NPC_TRADE_TIM waitbutton closetext end TimsHouseBookshelf: jumpstd MagazineBookshelfScript OlivineTimsHouse_MapEvents: db 0, 0 ; filler def_warp_events warp_event 2, 7, OLIVINE_CITY, 3 warp_event 3, 7, OLIVINE_CITY, 3 def_coord_events def_bg_events bg_event 0, 1, BGEVENT_READ, TimsHouseBookshelf bg_event 1, 1, BGEVENT_READ, TimsHouseBookshelf def_object_events object_event 2, 3, SPRITE_FISHING_GURU, SPRITEMOVEDATA_SPINRANDOM_SLOW, 0, 0, -1, -1, PAL_NPC_RED, OBJECTTYPE_SCRIPT, 0, Tim, -1

{ "language": "Assembly" }

// RUN: %sourcekitd-test -req=cursor -pos=1:8 %S/Inputs/multiple_ast1.swift -- %S/Inputs/multiple_ast1.swift == \ // RUN: -req=cursor -pos=1:8 %S/Inputs/multiple_ast2.swift -- %S/Inputs/multiple_ast2.swift | %FileCheck -check-prefix=CHECK %s // CHECK: source.lang.swift.decl.function.free (1:6-1:20) // CHECK-NEXT: foo1 // CHECK: source.lang.swift.decl.function.free (1:6-1:20) // CHECK-NEXT: foo2

{ "language": "Assembly" }

/* c-isr library stuff of Andes NDS32 cpu for GNU compiler Copyright (C) 2012-2019 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version. GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. Under Section 7 of GPL version 3, you are granted additional permissions described in the GCC Runtime Library Exception, version 3.1, as published by the Free Software Foundation. You should have received a copy of the GNU General Public License and a copy of the GCC Runtime Library Exception along with this program; see the files COPYING3 and COPYING.RUNTIME respectively. If not, see <http://www.gnu.org/licenses/>. */ .macro RESTORE_FPU_REGS_01 fldi.bi $fd0, [$sp], #8 fldi.bi $fd1, [$sp], #8 fldi.bi $fd2, [$sp], #8 fldi.bi $fd3, [$sp], #8 fldi.bi $fd4, [$sp], #8 fldi.bi $fd5, [$sp], #8 fldi.bi $fd6, [$sp], #8 fldi.bi $fd7, [$sp], #8 .endm

{ "language": "Assembly" }

/* LiCK Library for ChucK. Copyright (c) 2007-2020 held jointly by the individual authors. This file is part of LiCK. LiCK is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. LiCK is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with LiCK. If not, see <http://www.gnu.org/licenses/>. */ adc => Foldback f => dac; 0.9 => f.mix; <<<"ready">>>; 1::minute => now;

{ "language": "Assembly" }

Route16FlyHouse_h: db HOUSE ; tileset db ROUTE_16_FLY_HOUSE_HEIGHT, ROUTE_16_FLY_HOUSE_WIDTH ; dimensions (y, x) dw Route16FlyHouse_Blocks ; blocks dw Route16FlyHouse_TextPointers ; texts dw Route16FlyHouse_Script ; scripts db 0 ; connections dw Route16FlyHouse_Object ; objects

{ "language": "Assembly" }

#source: start.s #source: getaa.s #source: a.s #as: -no-expand #ld: -m elf64mmix #objdump: -dr .*: file format elf64-mmix Disassembly of section \.text: 0+ <_start>: 0+: e3fd0001 setl \$253,0x1 0+4 <getaa>: 4: e3fd0002 setl \$253,0x2 8: f47b0002 geta \$123,10 <a> c: e3fd0003 setl \$253,0x3 0+10 <a>: 10: e3fd0004 setl \$253,0x4

{ "language": "Assembly" }

; RUN: %lli %s > /dev/null define i32 @main() { %int1 = add i32 0, 0 ; <i32> [#uses=6] %int2 = add i32 0, 0 ; <i32> [#uses=6] %long1 = add i64 0, 0 ; <i64> [#uses=6] %long2 = add i64 0, 0 ; <i64> [#uses=6] %sbyte1 = add i8 0, 0 ; <i8> [#uses=6] %sbyte2 = add i8 0, 0 ; <i8> [#uses=6] %short1 = add i16 0, 0 ; <i16> [#uses=6] %short2 = add i16 0, 0 ; <i16> [#uses=6] %ubyte1 = add i8 0, 0 ; <i8> [#uses=6] %ubyte2 = add i8 0, 0 ; <i8> [#uses=6] %uint1 = add i32 0, 0 ; <i32> [#uses=6] %uint2 = add i32 0, 0 ; <i32> [#uses=6] %ulong1 = add i64 0, 0 ; <i64> [#uses=6] %ulong2 = add i64 0, 0 ; <i64> [#uses=6] %ushort1 = add i16 0, 0 ; <i16> [#uses=6] %ushort2 = add i16 0, 0 ; <i16> [#uses=6] %test1 = icmp eq i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] %test2 = icmp uge i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] %test3 = icmp ugt i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] %test4 = icmp ule i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] %test5 = icmp ult i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] %test6 = icmp ne i8 %ubyte1, %ubyte2 ; <i1> [#uses=0] %test7 = icmp eq i16 %ushort1, %ushort2 ; <i1> [#uses=0] %test8 = icmp uge i16 %ushort1, %ushort2 ; <i1> [#uses=0] %test9 = icmp ugt i16 %ushort1, %ushort2 ; <i1> [#uses=0] %test10 = icmp ule i16 %ushort1, %ushort2 ; <i1> [#uses=0] %test11 = icmp ult i16 %ushort1, %ushort2 ; <i1> [#uses=0] %test12 = icmp ne i16 %ushort1, %ushort2 ; <i1> [#uses=0] %test13 = icmp eq i32 %uint1, %uint2 ; <i1> [#uses=0] %test14 = icmp uge i32 %uint1, %uint2 ; <i1> [#uses=0] %test15 = icmp ugt i32 %uint1, %uint2 ; <i1> [#uses=0] %test16 = icmp ule i32 %uint1, %uint2 ; <i1> [#uses=0] %test17 = icmp ult i32 %uint1, %uint2 ; <i1> [#uses=0] %test18 = icmp ne i32 %uint1, %uint2 ; <i1> [#uses=0] %test19 = icmp eq i64 %ulong1, %ulong2 ; <i1> [#uses=0] %test20 = icmp uge i64 %ulong1, %ulong2 ; <i1> [#uses=0] %test21 = icmp ugt i64 %ulong1, %ulong2 ; <i1> [#uses=0] %test22 = icmp ule i64 %ulong1, %ulong2 ; <i1> [#uses=0] %test23 = icmp ult i64 %ulong1, %ulong2 ; <i1> [#uses=0] %test24 = icmp ne i64 %ulong1, %ulong2 ; <i1> [#uses=0] %test25 = icmp eq i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] %test26 = icmp sge i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] %test27 = icmp sgt i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] %test28 = icmp sle i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] %test29 = icmp slt i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] %test30 = icmp ne i8 %sbyte1, %sbyte2 ; <i1> [#uses=0] %test31 = icmp eq i16 %short1, %short2 ; <i1> [#uses=0] %test32 = icmp sge i16 %short1, %short2 ; <i1> [#uses=0] %test33 = icmp sgt i16 %short1, %short2 ; <i1> [#uses=0] %test34 = icmp sle i16 %short1, %short2 ; <i1> [#uses=0] %test35 = icmp slt i16 %short1, %short2 ; <i1> [#uses=0] %test36 = icmp ne i16 %short1, %short2 ; <i1> [#uses=0] %test37 = icmp eq i32 %int1, %int2 ; <i1> [#uses=0] %test38 = icmp sge i32 %int1, %int2 ; <i1> [#uses=0] %test39 = icmp sgt i32 %int1, %int2 ; <i1> [#uses=0] %test40 = icmp sle i32 %int1, %int2 ; <i1> [#uses=0] %test41 = icmp slt i32 %int1, %int2 ; <i1> [#uses=0] %test42 = icmp ne i32 %int1, %int2 ; <i1> [#uses=0] %test43 = icmp eq i64 %long1, %long2 ; <i1> [#uses=0] %test44 = icmp sge i64 %long1, %long2 ; <i1> [#uses=0] %test45 = icmp sgt i64 %long1, %long2 ; <i1> [#uses=0] %test46 = icmp sle i64 %long1, %long2 ; <i1> [#uses=0] %test47 = icmp slt i64 %long1, %long2 ; <i1> [#uses=0] %test48 = icmp ne i64 %long1, %long2 ; <i1> [#uses=0] ret i32 0 }

{ "language": "Assembly" }

/* * Copyright 2013 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Ben Skeggs */ #ifdef INCLUDE_PROC process(PROC_HOST, #host_init, #host_recv) #endif /****************************************************************************** * HOST data segment *****************************************************************************/ #ifdef INCLUDE_DATA // HOST (R)FIFO packet format .equ #fifo_process 0x00 .equ #fifo_message 0x04 .equ #fifo_data0 0x08 .equ #fifo_data1 0x0c // HOST HOST->PWR queue description .equ #fifo_qlen 4 // log2(size of queue entry in bytes) .equ #fifo_qnum 3 // log2(max number of entries in queue) .equ #fifo_qmaskb (1 << #fifo_qnum) // max number of entries in queue .equ #fifo_qmaskp (#fifo_qmaskb - 1) .equ #fifo_qmaskf ((#fifo_qmaskb << 1) - 1) .equ #fifo_qsize (1 << (#fifo_qlen + #fifo_qnum)) fifo_queue: .skip 128 // #fifo_qsize // HOST PWR->HOST queue description .equ #rfifo_qlen 4 // log2(size of queue entry in bytes) .equ #rfifo_qnum 3 // log2(max number of entries in queue) .equ #rfifo_qmaskb (1 << #rfifo_qnum) // max number of entries in queue .equ #rfifo_qmaskp (#rfifo_qmaskb - 1) .equ #rfifo_qmaskf ((#rfifo_qmaskb << 1) - 1) .equ #rfifo_qsize (1 << (#rfifo_qlen + #rfifo_qnum)) rfifo_queue: .skip 128 // #rfifo_qsize #endif /****************************************************************************** * HOST code segment *****************************************************************************/ #ifdef INCLUDE_CODE // HOST->PWR comms - dequeue message(s) for process(es) from FIFO // // $r15 - current (host) // $r0 - zero host_send: nv_iord($r1, NV_PPWR_FIFO_GET(0)) nv_iord($r2, NV_PPWR_FIFO_PUT(0)) cmp b32 $r1 $r2 bra e #host_send_done // calculate address of message and $r14 $r1 #fifo_qmaskp shl b32 $r14 $r14 #fifo_qlen add b32 $r14 #fifo_queue // read message data, and pass to appropriate process ld b32 $r11 D[$r14 + #fifo_data1] ld b32 $r12 D[$r14 + #fifo_data0] ld b32 $r13 D[$r14 + #fifo_message] ld b32 $r14 D[$r14 + #fifo_process] call(send) // increment GET add b32 $r1 0x1 and $r14 $r1 #fifo_qmaskf nv_iowr(NV_PPWR_FIFO_GET(0), $r14) bra #host_send host_send_done: ret // PWR->HOST comms - enqueue message for HOST to RFIFO // // $r15 - current (host) // $r14 - process // $r13 - message // $r12 - message data 0 // $r11 - message data 1 // $r0 - zero host_recv: // message from intr handler == HOST->PWR comms pending imm32($r1, PROC_KERN) cmp b32 $r14 $r1 bra e #host_send // wait for space in RFIFO host_recv_wait: nv_iord($r1, NV_PPWR_RFIFO_GET) nv_iord($r2, NV_PPWR_RFIFO_PUT) xor $r1 #rfifo_qmaskb cmp b32 $r1 $r2 bra e #host_recv_wait and $r3 $r2 #rfifo_qmaskp shl b32 $r3 #rfifo_qlen add b32 $r3 #rfifo_queue // enqueue message st b32 D[$r3 + #fifo_data1] $r11 st b32 D[$r3 + #fifo_data0] $r12 st b32 D[$r3 + #fifo_message] $r13 st b32 D[$r3 + #fifo_process] $r14 add b32 $r2 0x1 and $r2 #rfifo_qmaskf nv_iowr(NV_PPWR_RFIFO_PUT, $r2) // notify host of pending message mov $r2 NV_PPWR_INTR_TRIGGER_USER0 nv_iowr(NV_PPWR_INTR_TRIGGER, $r2) ret // $r15 - current (host) // $r0 - zero host_init: // store each fifo's base/size in H2D/D2H scratch regs mov $r1 #fifo_qsize shl b32 $r1 16 or $r1 #fifo_queue nv_iowr(NV_PPWR_H2D, $r1); mov $r1 #rfifo_qsize shl b32 $r1 16 or $r1 #rfifo_queue nv_iowr(NV_PPWR_D2H, $r1); // enable fifo subintr for first fifo mov $r1 1 nv_iowr(NV_PPWR_FIFO_INTR_EN, $r1) ret #endif

{ "language": "Assembly" }

; binary emission of 32-bit code. test binemit set opt_level=best set allones_funcaddrs target i686 haswell ; The binary encodings can be verified with the command: ; ; sed -ne 's/^ *; asm: *//p' filetests/isa/x86/allones_funcaddrs32.clif | llvm-mc -show-encoding -triple=i386 ; ; Tests from binary32.clif affected by allones_funcaddrs. function %I32() { sig0 = () fn0 = %foo() ebb0: ; asm: movl $-1, %ecx [-,%rcx] v400 = func_addr.i32 fn0 ; bin: b9 Abs4(%foo) ffffffff ; asm: movl $-1, %esi [-,%rsi] v401 = func_addr.i32 fn0 ; bin: be Abs4(%foo) ffffffff return ; bin: c3 }

{ "language": "Assembly" }

config BR2_PACKAGE_GCONF bool "gconf" depends on BR2_TOOLCHAIN_HAS_THREADS # dbus, libglib2 depends on BR2_USE_MMU # dbus, libglib2 depends on BR2_USE_WCHAR # libglib2 depends on !BR2_STATIC_LIBS select BR2_PACKAGE_DBUS select BR2_PACKAGE_DBUS_GLIB select BR2_PACKAGE_LIBGLIB2 select BR2_PACKAGE_LIBXML2 help GConf was a system used by the GNOME desktop environment for storing configuration settings for the desktop and applications. It is similar to the Windows Registry. https://projects.gnome.org/gconf/ comment "gconf needs a toolchain w/ threads, wchar, dynamic library" depends on BR2_USE_MMU depends on !BR2_TOOLCHAIN_HAS_THREADS || !BR2_USE_WCHAR \ || BR2_STATIC_LIBS

{ "language": "Assembly" }

/* Copyright (C) 1991-2020 Free Software Foundation, Inc. This file is part of the GNU C Library. The GNU C Library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version. The GNU C Library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with the GNU C Library; if not, see <https://www.gnu.org/licenses/>. */ #include <sys/stat.h> #include <errno.h> #include <sys/types.h> /* Set the file creation mask to MASK, returning the old mask. */ mode_t __umask (mode_t mask) { __set_errno (ENOSYS); return -1; } stub_warning (umask) weak_alias (__umask, umask)

{ "language": "Assembly" }

/* * Copyright (C) 2008, Guennadi Liakhovetski <[email protected]> * * SPDX-License-Identifier: GPL-2.0+ */ #include <asm/arch/imx-regs.h> .macro REG reg, val ldr r2, =\reg ldr r3, =\val str r3, [r2] .endm .macro REG8 reg, val ldr r2, =\reg ldr r3, =\val strb r3, [r2] .endm .macro DELAY loops ldr r2, =\loops 1: subs r2, r2, #1 nop bcs 1b .endm /* RedBoot: AIPS setup - Only setup MPROTx registers. * The PACR default values are good.*/ .macro init_aips /* * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. */ ldr r0, =0x43F00000 ldr r1, =0x77777777 str r1, [r0, #0x00] str r1, [r0, #0x04] ldr r0, =0x53F00000 str r1, [r0, #0x00] str r1, [r0, #0x04] /* * Clear the on and off peripheral modules Supervisor Protect bit * for SDMA to access them. Did not change the AIPS control registers * (offset 0x20) access type */ ldr r0, =0x43F00000 ldr r1, =0x0 str r1, [r0, #0x40] str r1, [r0, #0x44] str r1, [r0, #0x48] str r1, [r0, #0x4C] ldr r1, [r0, #0x50] and r1, r1, #0x00FFFFFF str r1, [r0, #0x50] ldr r0, =0x53F00000 ldr r1, =0x0 str r1, [r0, #0x40] str r1, [r0, #0x44] str r1, [r0, #0x48] str r1, [r0, #0x4C] ldr r1, [r0, #0x50] and r1, r1, #0x00FFFFFF str r1, [r0, #0x50] .endm /* init_aips */ /* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */ .macro init_max ldr r0, =0x43F04000 /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ ldr r1, =0x00302154 str r1, [r0, #0x000] /* for S0 */ str r1, [r0, #0x100] /* for S1 */ str r1, [r0, #0x200] /* for S2 */ str r1, [r0, #0x300] /* for S3 */ str r1, [r0, #0x400] /* for S4 */ /* SGPCR - always park on last master */ ldr r1, =0x10 str r1, [r0, #0x010] /* for S0 */ str r1, [r0, #0x110] /* for S1 */ str r1, [r0, #0x210] /* for S2 */ str r1, [r0, #0x310] /* for S3 */ str r1, [r0, #0x410] /* for S4 */ /* MGPCR - restore default values */ ldr r1, =0x0 str r1, [r0, #0x800] /* for M0 */ str r1, [r0, #0x900] /* for M1 */ str r1, [r0, #0xA00] /* for M2 */ str r1, [r0, #0xB00] /* for M3 */ str r1, [r0, #0xC00] /* for M4 */ str r1, [r0, #0xD00] /* for M5 */ .endm /* init_max */ /* RedBoot: M3IF setup */ .macro init_m3if /* Configure M3IF registers */ ldr r1, =0xB8003000 /* * M3IF Control Register (M3IFCTL) * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 * ------------ * 0x00000040 */ ldr r0, =0x00000040 str r0, [r1] /* M3IF control reg */ .endm /* init_m3if */ /* RedBoot: To support 133MHz DDR */ .macro init_drive_strength /* * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits * in SW_PAD_CTL registers */ /* SDCLK */ ldr r1, =0x43FAC200 ldr r0, [r1, #0x6C] bic r0, r0, #(1 << 12) str r0, [r1, #0x6C] /* CAS */ ldr r0, [r1, #0x70] bic r0, r0, #(1 << 22) str r0, [r1, #0x70] /* RAS */ ldr r0, [r1, #0x74] bic r0, r0, #(1 << 2) str r0, [r1, #0x74] /* CS2 (CSD0) */ ldr r0, [r1, #0x7C] bic r0, r0, #(1 << 22) str r0, [r1, #0x7C] /* DQM3 */ ldr r0, [r1, #0x84] bic r0, r0, #(1 << 22) str r0, [r1, #0x84] /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */ pad_loop: ldr r0, [r1, #0x88] bic r0, r0, #(1 << 22) bic r0, r0, #(1 << 12) bic r0, r0, #(1 << 2) str r0, [r1, #0x88] add r1, r1, #4 subs r2, r2, #0x1 bne pad_loop .endm /* init_drive_strength */ /* CPLD on CS4 setup */ .macro init_cs4 ldr r0, =WEIM_BASE ldr r1, =0x0000D843 str r1, [r0, #0x40] ldr r1, =0x22252521 str r1, [r0, #0x44] ldr r1, =0x22220A00 str r1, [r0, #0x48] .endm /* init_cs4 */ .globl lowlevel_init lowlevel_init: /* Redboot initializes very early AIPS, what for? * Then it also initializes Multi-Layer AHB Crossbar Switch, * M3IF */ /* Also setup the Peripheral Port Remap register inside the core */ ldr r0, =0x40000015 /* start from AIPS 2GB region */ mcr p15, 0, r0, c15, c2, 4 init_aips init_max init_m3if init_drive_strength init_cs4 /* Image Processing Unit: */ /* Too early to switch display on? */ REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */ /* Clock Control Module: */ REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */ DELAY 0x40000 REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */ REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */ /* PBC CPLD on CS4 */ mov r1, #CS4_BASE ldrh r1, [r1, #0x2] /* Is 27MHz switch set? */ ands r1, r1, #0x10 /* 532-133-66.5 */ ldr r0, =CCM_BASE ldr r1, =0xFF871D58 /* PDR0 */ str r1, [r0, #0x4] ldreq r1, MPCTL_PARAM_532 ldrne r1, MPCTL_PARAM_532_27 /* MPCTL */ str r1, [r0, #0x10] /* Set UPLL=240MHz, USB=60MHz */ ldr r1, =0x49FCFE7F /* PDR1 */ str r1, [r0, #0x8] ldreq r1, UPCTL_PARAM_240 ldrne r1, UPCTL_PARAM_240_27 /* UPCTL */ str r1, [r0, #0x14] /* default CLKO to 1/8 of the ARM core */ mov r1, #0x000002C0 add r1, r1, #0x00000006 /* COSR */ str r1, [r0, #0x1c] /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */ /* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/ /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */ /* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/ /* Default: 1, 4, 12, 1 */ REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */ REG 0xB8001010, 0x00000004 REG 0xB8001004, 0x006ac73a REG 0xB8001000, 0x92100000 REG 0x80000f00, 0x12344321 REG 0xB8001000, 0xa2100000 REG 0x80000000, 0x12344321 REG 0x80000000, 0x12344321 REG 0xB8001000, 0xb2100000 REG8 0x80000033, 0xda REG8 0x81000000, 0xff REG 0xB8001000, 0x82226080 REG 0x80000000, 0xDEADBEEF REG 0xB8001010, 0x0000000c mov pc, lr MPCTL_PARAM_532: .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0)) MPCTL_PARAM_532_27: .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0)) UPCTL_PARAM_240: .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0)) UPCTL_PARAM_240_27: .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))

{ "language": "Assembly" }

0 SECTION 2 TABLES 0 LAYER 2 Background 62 1 0 ENDTAB 0 ENDSEC 0 SECTION 2 ENTITIES 0 ELLIPSE 8 Background 6 CONTINUOUS 10 8.325000 20 -3.550000 11 3.375000 40 0.370370 39 0 41 0.000000 42 6.280000 0 ELLIPSE 8 Background 6 CONTINUOUS 10 8.325000 20 -3.550000 11 3.375000 40 0.370370 39 0 41 0.000000 42 6.280000 0 ELLIPSE 8 Background 6 DASHDOT 10 5.150000 20 -6.100000 11 2.000000 40 1.700000 39 1 41 0.000000 42 6.280000 0 CIRCLE 8 Background 6 DASHDOT 10 8.475000 20 -6.625000 40 3.075000 39 1 0 CIRCLE 8 Background 6 DASH 10 8.475000 20 -6.625000 40 3.075000 39 0 0 ENDSEC 0 EOF

{ "language": "Assembly" }

Freescale esdhc-specific options - CONFIG_FSL_ESDHC_ADAPTER_IDENT Support Freescale adapter card type identification. This is implemented by operating Qixis FPGA relevant registers. The STAT_PRES1 register has SDHC Card ID[0:2] bits showing the type of card installed in the SDHC Adapter Slot. SDHC Card ID[0:2] Adapter Card Type 0b000 reserved 0b001 eMMC Card Rev4.5 0b010 SD/MMC Legacy Card 0b011 eMMC Card Rev4.4 0b100 reserved 0b101 MMC Card 0b110 SD Card Rev2.0/3.0 0b111 No card is present - CONFIG_SYS_FSL_ESDHC_LE ESDHC IP is in little-endian mode. Accessing ESDHC registers can be determined by ESDHC IP's endian mode or processor's endian mode. - CONFIG_SYS_FSL_ESDHC_BE ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined by ESDHC IP's endian mode or processor's endian mode.

{ "language": "Assembly" }

// RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32im -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32ima -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32imaf -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32imafd -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32ic -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32imc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32imac -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32imafc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32imafdc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32ia -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32iaf -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32iafd -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32iac -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32iafc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32iafdc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32g -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv32-unknown-elf -march=rv32gc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64im -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64ima -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64imaf -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64imafd -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64ic -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64imc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64imac -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64imafc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64imafdc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64ia -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64iaf -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64iafd -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64iac -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64iafc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64iafdc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64g -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target riscv64-unknown-elf -march=rv64gc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck %s // CHECK-NOT: error: invalid arch name ' // RUN: %clang -target riscv32-unknown-elf -march=rv32 -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32 %s // RV32: error: invalid arch name 'rv32' // RUN: %clang -target riscv32-unknown-elf -march=rv32m -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32M %s // RV32M: error: invalid arch name 'rv32m' // RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32ID %s // RV32ID: error: invalid arch name 'rv32id' // RUN: %clang -target riscv32-unknown-elf -march=rv32l -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s // RV32L: error: invalid arch name 'rv32l' // RUN: %clang -target riscv32-unknown-elf -march=rv32imadf -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s // RV32IMADF: error: invalid arch name 'rv32imadf' // RUN: %clang -target riscv32-unknown-elf -march=rv32imm -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMM %s // RV32IMM: error: invalid arch name 'rv32imm' // RUN: %clang -target riscv32-unknown-elf -march=RV32I -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32I-UPPER %s // RV32I-UPPER: error: invalid arch name 'RV32I' // RUN: %clang -target riscv64-unknown-elf -march=rv64 -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64 %s // RV64: error: invalid arch name 'rv64' // RUN: %clang -target riscv64-unknown-elf -march=rv64m -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64M %s // RV64M: error: invalid arch name 'rv64m' // RUN: %clang -target riscv64-unknown-elf -march=rv64id -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64ID %s // RV64ID: error: invalid arch name 'rv64id' // RUN: %clang -target riscv64-unknown-elf -march=rv64l -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64L %s // RV64L: error: invalid arch name 'rv64l' // RUN: %clang -target riscv64-unknown-elf -march=rv64imadf -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMADF %s // RV64IMADF: error: invalid arch name 'rv64imadf' // RUN: %clang -target riscv64-unknown-elf -march=rv64imm -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMM %s // RV64IMM: error: invalid arch name 'rv64imm' // RUN: %clang -target riscv64-unknown-elf -march=RV64I -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64I-UPPER %s // RV64I-UPPER: error: invalid arch name 'RV64I' // Testing specific messages and unsupported extensions. // RUN: %clang -target riscv32-unknown-elf -march=rv32e -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32E %s // RV32E: error: invalid arch name 'rv32e', // RV32E: standard user-level extension 'e' // RUN: %clang -target riscv64-unknown-elf -march=rv64e -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64E %s // RV64E: error: invalid arch name 'rv64e', // RV64E: standard user-level extension 'e' requires 'rv32' // RUN: %clang -target riscv32-unknown-elf -march=rv32imC -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-LOWER %s // RV32-LOWER: error: invalid arch name 'rv32imC', // RV32-LOWER: string must be lowercase // RUN: %clang -target riscv32-unknown-elf -march=rv32 -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-STR %s // RV32-STR: error: invalid arch name 'rv32', // RV32-STR: string must begin with rv32{i,e,g} or rv64{i,g} // RUN: %clang -target riscv32-unknown-elf -march=rv32q -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-LETTER %s // RV32-LETTER: error: invalid arch name 'rv32q', // RV32-LETTER: first letter should be 'e', 'i' or 'g' // RUN: %clang -target riscv32-unknown-elf -march=rv32imcq -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ORDER %s // RV32-ORDER: error: invalid arch name 'rv32imcq', // RV32-ORDER: standard user-level extension not given in canonical order 'q' // RUN: %clang -target riscv32-unknown-elf -march=rv32imw -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-STD-INVAL %s // RV32-STD-INVAL: error: invalid arch name 'rv32imw', // RV32-STD-INVAL: invalid standard user-level extension 'w' // RUN: %clang -target riscv32-unknown-elf -march=rv32imqc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-STD %s // RV32-STD: error: invalid arch name 'rv32imqc', // RV32-STD: unsupported standard user-level extension 'q' // RUN: %clang -target riscv32-unknown-elf -march=rv32xabc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s // RV32X: error: invalid arch name 'rv32xabc', // RV32X: first letter should be 'e', 'i' or 'g' // RUN: %clang -target riscv32-unknown-elf -march=rv32sxabc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32SX %s // RV32SX: error: invalid arch name 'rv32sxabc', // RV32SX: first letter should be 'e', 'i' or 'g' // RUN: %clang -target riscv32-unknown-elf -march=rv32sabc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32S %s // RV32S: error: invalid arch name 'rv32sabc', // RV32S: first letter should be 'e', 'i' or 'g' // RUN: %clang -target riscv32-unknown-elf -march=rv32ix -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X-NAME %s // RV32X-NAME: error: invalid arch name 'rv32ix', // RV32X-NAME: non-standard user-level extension name missing after 'x' // RUN: %clang -target riscv32-unknown-elf -march=rv32isx -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32SX-NAME %s // RV32SX-NAME: error: invalid arch name 'rv32isx', // RV32SX-NAME: non-standard supervisor-level extension // RV32SX-NAME: name missing after 'sx' // RUN: %clang -target riscv32-unknown-elf -march=rv32is -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32S-NAME %s // RV32S-NAME: error: invalid arch name 'rv32is', // RV32S-NAME: standard supervisor-level extension // RV32S-NAME: name missing after 's' // RUN: %clang -target riscv32-unknown-elf -march=rv32ix_s_sx -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32ALL-NAME %s // RV32ALL-NAME: error: invalid arch name 'rv32ix_s_sx', // RV32ALL-NAME: non-standard user-level extension // RV32ALL-NAME: name missing after 'x' // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X-UNS %s // RV32X-UNS: error: invalid arch name 'rv32ixabc', // RV32X-UNS: unsupported non-standard user-level extension 'xabc' // RUN: %clang -target riscv32-unknown-elf -march=rv32isa -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32S-UNS %s // RV32S-UNS: error: invalid arch name 'rv32isa', // RV32S-UNS: unsupported standard supervisor-level extension 'sa' // RUN: %clang -target riscv32-unknown-elf -march=rv32isxabc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32SX-UNS %s // RV32SX-UNS: error: invalid arch name 'rv32isxabc', // RV32SX-UNS: unsupported non-standard supervisor-level extension 'sxabc' // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc_sp_sxlw -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32ALL %s // RV32ALL: error: invalid arch name 'rv32ixabc_sp_sxlw', // RV32ALL: unsupported non-standard user-level extension 'xabc' // RUN: %clang -target riscv32-unknown-elf -march=rv32i20 -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-IVER %s // RV32-IVER: error: invalid arch name 'rv32i20', unsupported // RV32-IVER: version number 20 for extension 'i' // RUN: %clang -target riscv32-unknown-elf -march=rv32imc5 -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-CVER %s // RV32-CVER: error: invalid arch name 'rv32imc5', unsupported // RV32-CVER: version number 5 for extension 'c' // RUN: %clang -target riscv32-unknown-elf -march=rv32i2p -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-IMINOR-MISS %s // RV32-IMINOR-MISS: error: invalid arch name 'rv32i2p', // RV32-IMINOR-MISS: minor version number missing after 'p' for extension 'i' // RUN: %clang -target riscv32-unknown-elf -march=rv32i2p0 -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-IMINOR0 %s // RV32-IMINOR0: error: invalid arch name 'rv32i2p0', // RV32-IMINOR0: unsupported version number 2.0 for extension 'i' // RUN: %clang -target riscv32-unknown-elf -march=rv32i2p1 -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-IMINOR1 %s // RV32-IMINOR1: error: invalid arch name 'rv32i2p1', unsupported // RV32-IMINOR1: version number 2.1 for extension 'i' // RUN: %clang -target riscv32-unknown-elf -march=rv32ix2p -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XMINOR-MISS %s // RV32-XMINOR-MISS: error: invalid arch name 'rv32ix2p', // RV32-XMINOR-MISS: minor version number missing after 'p' for extension 'x2p' // RUN: %clang -target riscv32-unknown-elf -march=rv32is2p0 -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-SMINOR0 %s // RV32-SMINOR0: error: invalid arch name 'rv32is2p0', // RV32-SMINOR0: unsupported version number 2.0 for extension 's2p0' // RUN: %clang -target riscv32-unknown-elf -march=rv32isx2p1 -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-SXMINOR1 %s // RV32-SXMINOR1: error: invalid arch name 'rv32isx2p1', unsupported // RV32-SXMINOR1: version number 2.1 for extension 'sx2p1' // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc_ -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XSEP %s // RV32-XSEP: error: invalid arch name 'rv32ixabc_', // RV32-XSEP: extension name missing after separator '_' // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc_a -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-PREFIX %s // RV32-PREFIX: error: invalid arch name 'rv32ixabc_a', // RV32-PREFIX: invalid extension prefix 'a' // RUN: %clang -target riscv32-unknown-elf -march=rv32isabc_xdef -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s // RV32-X-ORDER: error: invalid arch name 'rv32isabc_xdef', // RV32-X-ORDER: non-standard user-level extension not given // RV32-X-ORDER: in canonical order 'xdef' // RUN: %clang -target riscv32-unknown-elf -march=rv32isxabc_sdef -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-S-ORDER %s // RV32-S-ORDER: error: invalid arch name 'rv32isxabc_sdef', // RV32-S-ORDER: standard supervisor-level extension not given // RV32-S-ORDER: in canonical order 'sdef' // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc_xabc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XDUP %s // RV32-XDUP: error: invalid arch name 'rv32ixabc_xabc', // RV32-XDUP: duplicated non-standard user-level extension 'xabc' // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc_xdef -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-X-INVAL %s // RV32-X-X-INVAL: error: invalid arch name 'rv32ixabc_xdef', unsupported // RV32-X-X-INVAL: non-standard user-level extension 'xabc' // RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc_sdef_sxghi -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-S-SX-INVAL %s // RV32-X-S-SX-INVAL: error: invalid arch name 'rv32ixabc_sdef_sxghi', // RV32-X-S-SX-INVAL: unsupported non-standard user-level extension 'xabc'

{ "language": "Assembly" }

// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix LAMBDA --check-prefix LAMBDA-64 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix LAMBDA --check-prefix LAMBDA-64 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix LAMBDA --check-prefix LAMBDA-32 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix LAMBDA --check-prefix LAMBDA-32 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics #ifndef HEADER #define HEADER template <class T> struct S { T f; S(T a) : f(a) {} S() : f() {} operator T() { return T(); } ~S() {} }; // CHECK: [[S_FLOAT_TY:%.+]] = type { float } // CHECK: [[S_INT_TY:%.+]] = type { i{{[0-9]+}} } template <typename T> T tmain() { S<T> test; T t_var = T(); T vec[] = {1, 2}; S<T> s_arr[] = {1, 2}; S<T> &var = test; #pragma omp target #pragma omp teams #pragma omp distribute private(t_var, vec, s_arr, s_arr, var, var) for (int i = 0; i < 2; ++i) { vec[i] = t_var; s_arr[i] = var; } return T(); } int main() { static int svar; volatile double g; volatile double &g1 = g; #ifdef LAMBDA // LAMBDA-LABEL: @main // LAMBDA: call{{.*}} void [[OUTER_LAMBDA:@.+]]( [&]() { static float sfvar; // LAMBDA: define{{.*}} internal{{.*}} void [[OUTER_LAMBDA]]( // LAMBDA: call i{{[0-9]+}} @__tgt_target_teams( // LAMBDA: call void [[OFFLOADING_FUN:@.+]]( // LAMBDA: define{{.+}} void [[OFFLOADING_FUN]]() // LAMBDA: call {{.*}}void {{.+}} @__kmpc_fork_teams({{.+}}, i32 0, {{.+}}* [[OMP_OUTLINED:@.+]] to {{.+}}) #pragma omp target #pragma omp teams #pragma omp distribute private(g, g1, svar, sfvar) for (int i = 0; i < 2; ++i) { // LAMBDA: define{{.*}} internal{{.*}} void [[OMP_OUTLINED]](i32* noalias %{{.+}}, i32* noalias %{{.+}}) // LAMBDA: [[G_PRIVATE_ADDR:%.+]] = alloca double, // LAMBDA: [[G1_PRIVATE_ADDR:%.+]] = alloca double, // LAMBDA: [[TMP_PRIVATE_ADDR:%.+]] = alloca double*, // LAMBDA: [[SVAR_PRIVATE_ADDR:%.+]] = alloca i{{[0-9]+}}, // LAMBDA: [[SFVAR_PRIVATE_ADDR:%.+]] = alloca float, // LAMBDA: store double* [[G1_PRIVATE_ADDR]], double** [[TMP_PRIVATE_ADDR]], g = 1; g1 = 1; svar = 3; sfvar = 4.0; // LAMBDA: call {{.*}}void @__kmpc_for_static_init_4( // LAMBDA: store double 1.0{{.+}}, double* [[G_PRIVATE_ADDR]], // LAMBDA: store i{{[0-9]+}} 3, i{{[0-9]+}}* [[SVAR_PRIVATE_ADDR]], // LAMBDA: store float 4.0{{.+}}, float* [[SFVAR_PRIVATE_ADDR]], // LAMBDA: [[G_PRIVATE_ADDR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 // LAMBDA: store double* [[G_PRIVATE_ADDR]], double** [[G_PRIVATE_ADDR_REF]], // LAMBDA: [[TMP_PRIVATE_ADDR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // LAMBDA: [[G1_PRIVATE_ADDR_FROM_TMP:%.+]] = load double*, double** [[TMP_PRIVATE_ADDR]], // LAMBDA: store double* [[G1_PRIVATE_ADDR_FROM_TMP]], double** [[TMP_PRIVATE_ADDR_REF]], // LAMBDA: [[SVAR_PRIVATE_ADDR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // LAMBDA: store i{{[0-9]+}}* [[SVAR_PRIVATE_ADDR]], i{{[0-9]+}}** [[SVAR_PRIVATE_ADDR_REF]] // LAMBDA: [[SFVAR_PRIVATE_ADDR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 3 // LAMBDA: store float* [[SFVAR_PRIVATE_ADDR]], float** [[SFVAR_PRIVATE_ADDR_REF]] // LAMBDA: call{{.*}} void [[INNER_LAMBDA:@.+]](%{{.+}}* [[ARG]]) // LAMBDA: call {{.*}}void @__kmpc_for_static_fini( [&]() { // LAMBDA: define {{.+}} void [[INNER_LAMBDA]](%{{.+}}* [[ARG_PTR:%.+]]) // LAMBDA: store %{{.+}}* [[ARG_PTR]], %{{.+}}** [[ARG_PTR_REF:%.+]], g = 2; g1 = 2; svar = 4; sfvar = 8.0; // LAMBDA: [[ARG_PTR:%.+]] = load %{{.+}}*, %{{.+}}** [[ARG_PTR_REF]] // LAMBDA: [[G_PTR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG_PTR]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 // LAMBDA: [[G_REF:%.+]] = load double*, double** [[G_PTR_REF]] // LAMBDA: store double 2.0{{.+}}, double* [[G_REF]] // LAMBDA: [[TMP_PTR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG_PTR]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // LAMBDA: [[G1_REF:%.+]] = load double*, double** [[TMP_PTR_REF]] // LAMBDA: store double 2.0{{.+}}, double* [[G1_REF]], // LAMBDA: [[SVAR_PTR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG_PTR]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // LAMBDA: [[SVAR_REF:%.+]] = load i{{[0-9]+}}*, i{{[0-9]+}}** [[SVAR_PTR_REF]] // LAMBDA: store i{{[0-9]+}} 4, i{{[0-9]+}}* [[SVAR_REF]] // LAMBDA: [[SFVAR_PTR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG_PTR]], i{{[0-9]+}} 0, i{{[0-9]+}} 3 // LAMBDA: [[SFVAR_REF:%.+]] = load float*, float** [[SFVAR_PTR_REF]] // LAMBDA: store float 8.0{{.+}}, float* [[SFVAR_REF]] }(); } }(); return 0; #else S<float> test; int t_var = 0; int vec[] = {1, 2}; S<float> s_arr[] = {1, 2}; S<float> &var = test; #pragma omp target #pragma omp teams #pragma omp distribute private(t_var, vec, s_arr, s_arr, var, var, svar) for (int i = 0; i < 2; ++i) { vec[i] = t_var; s_arr[i] = var; } int i; #pragma omp target #pragma omp teams #pragma omp distribute private(i) for (i = 0; i < 2; ++i) { ; } return tmain<int>(); #endif } // CHECK: define{{.*}} i{{[0-9]+}} @main() // CHECK: [[TEST:%.+]] = alloca [[S_FLOAT_TY]], // CHECK: call {{.*}} [[S_FLOAT_TY_DEF_CONSTR:@.+]]([[S_FLOAT_TY]]* [[TEST]]) // CHECK: call i{{[0-9]+}} @__tgt_target_teams( // CHECK: call void [[OFFLOAD_FUN:@.+]]( // CHECK: ret // CHECK: define{{.+}} [[OFFLOAD_FUN]]() // CHECK: call void (%{{.+}}*, i{{[0-9]+}}, void (i{{[0-9]+}}*, i{{[0-9]+}}*, ...)*, ...) @__kmpc_fork_teams(%{{.+}}* @{{.+}}, i{{[0-9]+}} 0, void (i{{[0-9]+}}*, i{{[0-9]+}}*, ...)* bitcast (void (i{{[0-9]+}}*, i{{[0-9]+}}*)* [[OMP_OUTLINED:@.+]] to void // CHECK: ret // // CHECK: define internal void [[OMP_OUTLINED]](i{{[0-9]+}}* noalias [[GTID_ADDR:%.+]], i{{[0-9]+}}* noalias %{{.+}}) // CHECK: [[T_VAR_PRIV:%.+]] = alloca i{{[0-9]+}}, // CHECK: [[VEC_PRIV:%.+]] = alloca [2 x i{{[0-9]+}}], // CHECK: [[S_ARR_PRIV:%.+]] = alloca [2 x [[S_FLOAT_TY]]], // CHECK-NOT: alloca [2 x [[S_FLOAT_TY]]], // CHECK: [[VAR_PRIV:%.+]] = alloca [[S_FLOAT_TY]], // CHECK-NOT: alloca [[S_FLOAT_TY]], // CHECK: [[S_VAR_PRIV:%.+]] = alloca i{{[0-9]+}}, // CHECK: store i{{[0-9]+}}* [[GTID_ADDR]], i{{[0-9]+}}** [[GTID_ADDR_REF:%.+]] // CHECK-NOT: [[T_VAR_PRIV]] // CHECK-NOT: [[VEC_PRIV]] // CHECK: {{.+}}: // CHECK: [[S_ARR_PRIV_ITEM:%.+]] = phi [[S_FLOAT_TY]]* // CHECK: call {{.*}} [[S_FLOAT_TY_DEF_CONSTR]]([[S_FLOAT_TY]]* [[S_ARR_PRIV_ITEM]]) // CHECK-NOT: [[T_VAR_PRIV]] // CHECK-NOT: [[VEC_PRIV]] // CHECK: call {{.*}} [[S_FLOAT_TY_DEF_CONSTR]]([[S_FLOAT_TY]]* [[VAR_PRIV]]) // CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_fini( // CHECK: ret void // CHECK: define{{.*}} i{{[0-9]+}} [[TMAIN_INT:@.+]]() // CHECK: [[TEST:%.+]] = alloca [[S_INT_TY]], // CHECK: call {{.*}} [[S_INT_TY_DEF_CONSTR:@.+]]([[S_INT_TY]]* [[TEST]]) // CHECK: call i{{[0-9]+}} @__tgt_target_teams( // CHECK: call void [[OFFLOAD_FUN_1:@.+]]( // CHECK: ret // CHECK: define internal void [[OFFLOAD_FUN_1]]() // CHECK: call void (%{{.+}}*, i{{[0-9]+}}, void (i{{[0-9]+}}*, i{{[0-9]+}}*, ...)*, ...) @__kmpc_fork_teams(%{{.+}}* @{{.+}}, i{{[0-9]+}} 0, void (i{{[0-9]+}}*, i{{[0-9]+}}*, ...)* bitcast (void (i{{[0-9]+}}*, i{{[0-9]+}}*)* [[OMP_OUTLINED_1:@.+]] to void // CHECK: ret // // CHECK: define internal void [[OMP_OUTLINED_1]](i{{[0-9]+}}* noalias [[GTID_ADDR:%.+]], i{{[0-9]+}}* noalias %{{.+}}) // CHECK: [[T_VAR_PRIV:%.+]] = alloca i{{[0-9]+}}, // CHECK: [[VEC_PRIV:%.+]] = alloca [2 x i{{[0-9]+}}], // CHECK: [[S_ARR_PRIV:%.+]] = alloca [2 x [[S_INT_TY]]], // CHECK-NOT: alloca [2 x [[S_INT_TY]]], // CHECK: [[VAR_PRIV:%.+]] = alloca [[S_INT_TY]], // CHECK-NOT: alloca [[S_INT_TY]], // CHECK: store i{{[0-9]+}}* [[GTID_ADDR]], i{{[0-9]+}}** [[GTID_ADDR_REF:%.+]] // CHECK-NOT: [[T_VAR_PRIV]] // CHECK-NOT: [[VEC_PRIV]] // CHECK: {{.+}}: // CHECK: [[S_ARR_PRIV_ITEM:%.+]] = phi [[S_INT_TY]]* // CHECK: call {{.*}} [[S_INT_TY_DEF_CONSTR]]([[S_INT_TY]]* [[S_ARR_PRIV_ITEM]]) // CHECK-NOT: [[T_VAR_PRIV]] // CHECK-NOT: [[VEC_PRIV]] // CHECK: call {{.*}} [[S_INT_TY_DEF_CONSTR]]([[S_INT_TY]]* [[VAR_PRIV]]) // CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_fini( // CHECK: ret void #endif

{ "language": "Assembly" }

// Check that we extract -MD from '-Wp,-MD,FOO', which is used by a number of // major projects (e.g., FireFox and the Linux Kernel). // RUN: %clang -target i386-pc-linux-gnu -### \ // RUN: -Wp,-MD,FOO.d -fsyntax-only %s 2> %t // RUN: FileCheck < %t %s // // CHECK: "-cc1" // CHECK-NOT: -MD // CHECK: "-dependency-file" "FOO.d" // CHECK: "-MT" // // PR4062 // RUN: %clang -target i386-pc-linux-gnu -### \ // RUN: -Wp,-MMD -fsyntax-only %s 2> %t // RUN: FileCheck -check-prefix MMD < %t %s // MMD: "-cc1" // MMD-NOT: -MMD // MMD: "-dependency-file" "Wp-args.d"

{ "language": "Assembly" }

// Copyright 2009 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build !gccgo #include "textflag.h" // // System calls for AMD64, Linux // // Just jump to package syscall's implementation for all these functions. // The runtime may know about them. TEXT ·Syscall(SB),NOSPLIT,$0-56 JMP syscall·Syscall(SB) TEXT ·Syscall6(SB),NOSPLIT,$0-80 JMP syscall·Syscall6(SB) TEXT ·SyscallNoError(SB),NOSPLIT,$0-48 CALL runtime·entersyscall(SB) MOVQ a1+8(FP), DI MOVQ a2+16(FP), SI MOVQ a3+24(FP), DX MOVQ $0, R10 MOVQ $0, R8 MOVQ $0, R9 MOVQ trap+0(FP), AX // syscall entry SYSCALL MOVQ AX, r1+32(FP) MOVQ DX, r2+40(FP) CALL runtime·exitsyscall(SB) RET TEXT ·RawSyscall(SB),NOSPLIT,$0-56 JMP syscall·RawSyscall(SB) TEXT ·RawSyscall6(SB),NOSPLIT,$0-80 JMP syscall·RawSyscall6(SB) TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-48 MOVQ a1+8(FP), DI MOVQ a2+16(FP), SI MOVQ a3+24(FP), DX MOVQ $0, R10 MOVQ $0, R8 MOVQ $0, R9 MOVQ trap+0(FP), AX // syscall entry SYSCALL MOVQ AX, r1+32(FP) MOVQ DX, r2+40(FP) RET TEXT ·gettimeofday(SB),NOSPLIT,$0-16 JMP syscall·gettimeofday(SB)

{ "language": "Assembly" }

; RUN: opt < %s -instcombine | llvm-dis ; rdar://5771353 define float @test(float %x, x86_fp80 %y) nounwind readonly { entry: %tmp67 = fcmp uno x86_fp80 %y, 0xK00000000000000000000 ; <i1> [#uses=1] %tmp71 = fcmp uno float %x, 0.000000e+00 ; <i1> [#uses=1] %bothcond = or i1 %tmp67, %tmp71 ; <i1> [#uses=1] br i1 %bothcond, label %bb74, label %bb80 bb74: ; preds = %entry ret float 0.000000e+00 bb80: ; preds = %entry ret float 0.000000e+00 }

{ "language": "Assembly" }

dnl AMD64 mpn_addmul_1 and mpn_submul_1 optimised for Intel Nehalem. dnl Contributed to the GNU project by Torbjörn Granlund. dnl Copyright 2003-2005, 2007, 2008, 2011-2013 Free Software Foundation, Inc. dnl This file is part of the GNU MP Library. dnl dnl The GNU MP Library is free software; you can redistribute it and/or modify dnl it under the terms of either: dnl dnl * the GNU Lesser General Public License as published by the Free dnl Software Foundation; either version 3 of the License, or (at your dnl option) any later version. dnl dnl or dnl dnl * the GNU General Public License as published by the Free Software dnl Foundation; either version 2 of the License, or (at your option) any dnl later version. dnl dnl or both in parallel, as here. dnl dnl The GNU MP Library is distributed in the hope that it will be useful, but dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License dnl for more details. dnl dnl You should have received copies of the GNU General Public License and the dnl GNU Lesser General Public License along with the GNU MP Library. If not, dnl see https://www.gnu.org/licenses/. include(`../config.m4') C cycles/limb C AMD K8,K9 4.0 C AMD K10 4.0 C AMD bull 5.0 C AMD pile 4.84 5.39 C AMD steam C AMD excavator C AMD bobcat 5.56 C AMD jaguar 5.30 C Intel P4 15.7 17.2 C Intel core2 5.15 C Intel NHM 4.56 C Intel SBR 3.44 C Intel HWL 3.03 C Intel BWL 2.77 C Intel SKL 2.76 C Intel atom 21 C Intel SLM 11 C VIA nano C The loop of this code is the result of running a code generation and C optimization tool suite written by David Harvey and Torbjorn Granlund. C N.B.: Be careful if editing, making sure the loop alignment padding does not C become large, as we currently fall into it. define(`rp', `%rdi') C rcx define(`up', `%rsi') C rdx define(`n_param', `%rdx') C r8 define(`v0', `%rcx') C r9 define(`n', `%rbx') ifdef(`OPERATION_addmul_1',` define(`ADDSUB', `add') define(`func', `mpn_addmul_1') ') ifdef(`OPERATION_submul_1',` define(`ADDSUB', `sub') define(`func', `mpn_submul_1') ') ABI_SUPPORT(DOS64) ABI_SUPPORT(STD64) MULFUNC_PROLOGUE(mpn_addmul_1 mpn_submul_1) ASM_START() TEXT ALIGN(32) PROLOGUE(func) FUNC_ENTRY(4) push %rbx mov (up), %rax lea -8(up,n_param,8), up mov (rp), %r8 lea -8(rp,n_param,8), rp test $1, R8(n_param) jnz L(bx1) L(bx0): test $2, R8(n_param) jnz L(b10) L(b00): mov $3, R32(n) sub n_param, n mul v0 mov $0, R32(%r11) mov %r8, %r10 ADDSUB %rax, %r10 mov -8(up,n,8), %rax adc %rdx, %r11 jmp L(lo0) L(b10): mov $1, R32(n) sub n_param, n mul v0 mov %r8, %r10 mov $0, R32(%r11) ADDSUB %rax, %r10 mov 8(up,n,8), %rax adc %rdx, %r11 jmp L(lo2) L(bx1): test $2, R8(n_param) jz L(b01) L(b11): mov $2, R32(n) sub n_param, n mul v0 ADDSUB %rax, %r8 mov $0, R32(%r9) mov (up,n,8), %rax adc %rdx, %r9 jmp L(lo3) L(b01): mov $0, R32(n) sub n_param, n xor %r11, %r11 add $4, n jc L(end) ALIGN(32) L(top): mul v0 ADDSUB %rax, %r8 mov $0, R32(%r9) mov -16(up,n,8), %rax adc %rdx, %r9 L(lo1): mul v0 ADDSUB %r11, %r8 mov $0, R32(%r11) mov -16(rp,n,8), %r10 adc $0, %r9 ADDSUB %rax, %r10 mov -8(up,n,8), %rax adc %rdx, %r11 mov %r8, -24(rp,n,8) ADDSUB %r9, %r10 adc $0, %r11 L(lo0): mov -8(rp,n,8), %r8 mul v0 ADDSUB %rax, %r8 mov $0, R32(%r9) mov (up,n,8), %rax adc %rdx, %r9 mov %r10, -16(rp,n,8) ADDSUB %r11, %r8 adc $0, %r9 L(lo3): mul v0 mov (rp,n,8), %r10 mov $0, R32(%r11) ADDSUB %rax, %r10 mov 8(up,n,8), %rax adc %rdx, %r11 mov %r8, -8(rp,n,8) ADDSUB %r9, %r10 adc $0, %r11 L(lo2): mov 8(rp,n,8), %r8 mov %r10, (rp,n,8) add $4, n jnc L(top) L(end): mul v0 ADDSUB %rax, %r8 mov $0, R32(%rax) adc %rdx, %rax ADDSUB %r11, %r8 adc $0, %rax mov %r8, (rp) pop %rbx FUNC_EXIT() ret EPILOGUE() ASM_END()

{ "language": "Assembly" }

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s blendpd $11, %xmm0, %xmm2 blendpd $11, (%rax), %xmm2 blendps $11, %xmm0, %xmm2 blendps $11, (%rax), %xmm2 blendvpd %xmm0, %xmm2 blendvpd (%rax), %xmm2 blendvps %xmm0, %xmm2 blendvps (%rax), %xmm2 dppd $22, %xmm0, %xmm2 dppd $22, (%rax), %xmm2 dpps $22, %xmm0, %xmm2 dpps $22, (%rax), %xmm2 extractps $1, %xmm0, %rcx extractps $1, %xmm0, (%rax) insertps $1, %xmm0, %xmm2 insertps $1, (%rax), %xmm2 movntdqa (%rax), %xmm2 mpsadbw $1, %xmm0, %xmm2 mpsadbw $1, (%rax), %xmm2 packusdw %xmm0, %xmm2 packusdw (%rax), %xmm2 pblendvb %xmm0, %xmm2 pblendvb (%rax), %xmm2 pblendw $11, %xmm0, %xmm2 pblendw $11, (%rax), %xmm2 pcmpeqq %xmm0, %xmm2 pcmpeqq (%rax), %xmm2 pextrb $1, %xmm0, %ecx pextrb $1, %xmm0, (%rax) pextrd $1, %xmm0, %ecx pextrd $1, %xmm0, (%rax) pextrq $1, %xmm0, %rcx pextrq $1, %xmm0, (%rax) pextrw $1, %xmm0, (%rax) phminposuw %xmm0, %xmm2 phminposuw (%rax), %xmm2 pinsrb $1, %eax, %xmm1 pinsrb $1, (%rax), %xmm1 pinsrd $1, %eax, %xmm1 pinsrd $1, (%rax), %xmm1 pinsrq $1, %rax, %xmm1 pinsrq $1, (%rax), %xmm1 pmaxsb %xmm0, %xmm2 pmaxsb (%rax), %xmm2 pmaxsd %xmm0, %xmm2 pmaxsd (%rax), %xmm2 pmaxud %xmm0, %xmm2 pmaxud (%rax), %xmm2 pmaxuw %xmm0, %xmm2 pmaxuw (%rax), %xmm2 pminsb %xmm0, %xmm2 pminsb (%rax), %xmm2 pminsd %xmm0, %xmm2 pminsd (%rax), %xmm2 pminud %xmm0, %xmm2 pminud (%rax), %xmm2 pminuw %xmm0, %xmm2 pminuw (%rax), %xmm2 pmovsxbd %xmm0, %xmm2 pmovsxbd (%rax), %xmm2 pmovsxbq %xmm0, %xmm2 pmovsxbq (%rax), %xmm2 pmovsxbw %xmm0, %xmm2 pmovsxbw (%rax), %xmm2 pmovsxdq %xmm0, %xmm2 pmovsxdq (%rax), %xmm2 pmovsxwd %xmm0, %xmm2 pmovsxwd (%rax), %xmm2 pmovsxwq %xmm0, %xmm2 pmovsxwq (%rax), %xmm2 pmovzxbd %xmm0, %xmm2 pmovzxbd (%rax), %xmm2 pmovzxbq %xmm0, %xmm2 pmovzxbq (%rax), %xmm2 pmovzxbw %xmm0, %xmm2 pmovzxbw (%rax), %xmm2 pmovzxdq %xmm0, %xmm2 pmovzxdq (%rax), %xmm2 pmovzxwd %xmm0, %xmm2 pmovzxwd (%rax), %xmm2 pmovzxwq %xmm0, %xmm2 pmovzxwq (%rax), %xmm2 pmuldq %xmm0, %xmm2 pmuldq (%rax), %xmm2 pmulld %xmm0, %xmm2 pmulld (%rax), %xmm2 ptest %xmm0, %xmm1 ptest (%rax), %xmm1 roundpd $1, %xmm0, %xmm2 roundpd $1, (%rax), %xmm2 roundps $1, %xmm0, %xmm2 roundps $1, (%rax), %xmm2 roundsd $1, %xmm0, %xmm2 roundsd $1, (%rax), %xmm2 roundss $1, %xmm0, %xmm2 roundss $1, (%rax), %xmm2 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [2]: Latency # CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 1 0.50 blendpd $11, %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * blendpd $11, (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 blendps $11, %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * blendps $11, (%rax), %xmm2 # CHECK-NEXT: 2 2 1.00 blendvpd %xmm0, %xmm0, %xmm2 # CHECK-NEXT: 3 8 1.00 * blendvpd %xmm0, (%rax), %xmm2 # CHECK-NEXT: 2 2 1.00 blendvps %xmm0, %xmm0, %xmm2 # CHECK-NEXT: 3 8 1.00 * blendvps %xmm0, (%rax), %xmm2 # CHECK-NEXT: 3 9 1.00 dppd $22, %xmm0, %xmm2 # CHECK-NEXT: 4 15 1.00 * dppd $22, (%rax), %xmm2 # CHECK-NEXT: 4 12 2.00 dpps $22, %xmm0, %xmm2 # CHECK-NEXT: 5 18 2.00 * dpps $22, (%rax), %xmm2 # CHECK-NEXT: 2 3 1.00 extractps $1, %xmm0, %ecx # CHECK-NEXT: 3 5 1.00 * extractps $1, %xmm0, (%rax) # CHECK-NEXT: 1 1 1.00 insertps $1, %xmm0, %xmm2 # CHECK-NEXT: 2 7 1.00 * insertps $1, (%rax), %xmm2 # CHECK-NEXT: 1 6 0.50 * movntdqa (%rax), %xmm2 # CHECK-NEXT: 3 7 1.00 mpsadbw $1, %xmm0, %xmm2 # CHECK-NEXT: 4 13 1.00 * mpsadbw $1, (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 packusdw %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * packusdw (%rax), %xmm2 # CHECK-NEXT: 2 2 1.00 pblendvb %xmm0, %xmm0, %xmm2 # CHECK-NEXT: 3 8 1.00 * pblendvb %xmm0, (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pblendw $11, %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pblendw $11, (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pcmpeqq %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pcmpeqq (%rax), %xmm2 # CHECK-NEXT: 2 3 1.00 pextrb $1, %xmm0, %ecx # CHECK-NEXT: 3 5 1.00 * pextrb $1, %xmm0, (%rax) # CHECK-NEXT: 2 3 1.00 pextrd $1, %xmm0, %ecx # CHECK-NEXT: 4 5 1.00 * pextrd $1, %xmm0, (%rax) # CHECK-NEXT: 2 3 1.00 pextrq $1, %xmm0, %rcx # CHECK-NEXT: 4 5 1.00 * pextrq $1, %xmm0, (%rax) # CHECK-NEXT: 3 5 1.00 * pextrw $1, %xmm0, (%rax) # CHECK-NEXT: 1 5 1.00 phminposuw %xmm0, %xmm2 # CHECK-NEXT: 2 11 1.00 * phminposuw (%rax), %xmm2 # CHECK-NEXT: 2 2 1.00 pinsrb $1, %eax, %xmm1 # CHECK-NEXT: 2 7 0.50 * pinsrb $1, (%rax), %xmm1 # CHECK-NEXT: 2 2 1.00 pinsrd $1, %eax, %xmm1 # CHECK-NEXT: 2 7 0.50 * pinsrd $1, (%rax), %xmm1 # CHECK-NEXT: 2 2 1.00 pinsrq $1, %rax, %xmm1 # CHECK-NEXT: 2 7 0.50 * pinsrq $1, (%rax), %xmm1 # CHECK-NEXT: 1 1 0.50 pmaxsb %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmaxsb (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmaxsd %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmaxsd (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmaxud %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmaxud (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmaxuw %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmaxuw (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pminsb %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pminsb (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pminsd %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pminsd (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pminud %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pminud (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pminuw %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pminuw (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovsxbd %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovsxbd (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovsxbq %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovsxbq (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovsxbw %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovsxbw (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovsxdq %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovsxdq (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovsxwd %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovsxwd (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovsxwq %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovsxwq (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovzxbd %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovzxbd (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovzxbq %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovzxbq (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovzxbw %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovzxbw (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovzxdq %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovzxdq (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovzxwd %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovzxwd (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmovzxwq %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmovzxwq (%rax), %xmm2 # CHECK-NEXT: 1 5 1.00 pmuldq %xmm0, %xmm2 # CHECK-NEXT: 2 11 1.00 * pmuldq (%rax), %xmm2 # CHECK-NEXT: 1 5 1.00 pmulld %xmm0, %xmm2 # CHECK-NEXT: 2 11 1.00 * pmulld (%rax), %xmm2 # CHECK-NEXT: 2 2 1.00 ptest %xmm0, %xmm1 # CHECK-NEXT: 3 8 1.00 * ptest (%rax), %xmm1 # CHECK-NEXT: 1 3 1.00 roundpd $1, %xmm0, %xmm2 # CHECK-NEXT: 2 9 1.00 * roundpd $1, (%rax), %xmm2 # CHECK-NEXT: 1 3 1.00 roundps $1, %xmm0, %xmm2 # CHECK-NEXT: 2 9 1.00 * roundps $1, (%rax), %xmm2 # CHECK-NEXT: 1 3 1.00 roundsd $1, %xmm0, %xmm2 # CHECK-NEXT: 2 9 1.00 * roundsd $1, (%rax), %xmm2 # CHECK-NEXT: 1 3 1.00 roundss $1, %xmm0, %xmm2 # CHECK-NEXT: 2 9 1.00 * roundss $1, (%rax), %xmm2 # CHECK: Resources: # CHECK-NEXT: [0] - SBDivider # CHECK-NEXT: [1] - SBFPDivider # CHECK-NEXT: [2] - SBPort0 # CHECK-NEXT: [3] - SBPort1 # CHECK-NEXT: [4] - SBPort4 # CHECK-NEXT: [5] - SBPort5 # CHECK-NEXT: [6.0] - SBPort23 # CHECK-NEXT: [6.1] - SBPort23 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] # CHECK-NEXT: - - 26.00 47.50 5.00 52.50 24.50 24.50 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: # CHECK-NEXT: - - 0.50 - - 0.50 - - blendpd $11, %xmm0, %xmm2 # CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 blendpd $11, (%rax), %xmm2 # CHECK-NEXT: - - 0.50 - - 0.50 - - blendps $11, %xmm0, %xmm2 # CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 blendps $11, (%rax), %xmm2 # CHECK-NEXT: - - 1.00 - - 1.00 - - blendvpd %xmm0, %xmm0, %xmm2 # CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 blendvpd %xmm0, (%rax), %xmm2 # CHECK-NEXT: - - 1.00 - - 1.00 - - blendvps %xmm0, %xmm0, %xmm2 # CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 blendvps %xmm0, (%rax), %xmm2 # CHECK-NEXT: - - 1.00 1.00 - 1.00 - - dppd $22, %xmm0, %xmm2 # CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 dppd $22, (%rax), %xmm2 # CHECK-NEXT: - - 1.00 2.00 - 1.00 - - dpps $22, %xmm0, %xmm2 # CHECK-NEXT: - - 1.00 2.00 - 1.00 0.50 0.50 dpps $22, (%rax), %xmm2 # CHECK-NEXT: - - 1.00 - - 1.00 - - extractps $1, %xmm0, %ecx # CHECK-NEXT: - - - - 1.00 1.00 0.50 0.50 extractps $1, %xmm0, (%rax) # CHECK-NEXT: - - - - - 1.00 - - insertps $1, %xmm0, %xmm2 # CHECK-NEXT: - - - - - 1.00 0.50 0.50 insertps $1, (%rax), %xmm2 # CHECK-NEXT: - - - - - - 0.50 0.50 movntdqa (%rax), %xmm2 # CHECK-NEXT: - - 1.00 1.00 - 1.00 - - mpsadbw $1, %xmm0, %xmm2 # CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 mpsadbw $1, (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - packusdw %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 packusdw (%rax), %xmm2 # CHECK-NEXT: - - - 1.00 - 1.00 - - pblendvb %xmm0, %xmm0, %xmm2 # CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 pblendvb %xmm0, (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pblendw $11, %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pblendw $11, (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpeqq %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpeqq (%rax), %xmm2 # CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pextrb $1, %xmm0, %ecx # CHECK-NEXT: - - - 0.50 1.00 0.50 0.50 0.50 pextrb $1, %xmm0, (%rax) # CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pextrd $1, %xmm0, %ecx # CHECK-NEXT: - - 1.00 0.50 1.00 0.50 0.50 0.50 pextrd $1, %xmm0, (%rax) # CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pextrq $1, %xmm0, %rcx # CHECK-NEXT: - - 1.00 0.50 1.00 0.50 0.50 0.50 pextrq $1, %xmm0, (%rax) # CHECK-NEXT: - - - 0.50 1.00 0.50 0.50 0.50 pextrw $1, %xmm0, (%rax) # CHECK-NEXT: - - 1.00 - - - - - phminposuw %xmm0, %xmm2 # CHECK-NEXT: - - 1.00 - - - 0.50 0.50 phminposuw (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 1.50 - - pinsrb $1, %eax, %xmm1 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pinsrb $1, (%rax), %xmm1 # CHECK-NEXT: - - - 0.50 - 1.50 - - pinsrd $1, %eax, %xmm1 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pinsrd $1, (%rax), %xmm1 # CHECK-NEXT: - - - 0.50 - 1.50 - - pinsrq $1, %rax, %xmm1 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pinsrq $1, (%rax), %xmm1 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxsb %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxsb (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxsd %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxsd (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxud %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxud (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxuw %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxuw (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pminsb %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminsb (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pminsd %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminsd (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pminud %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminud (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pminuw %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminuw (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxbd %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxbd (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxbq %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxbq (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxbw %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxbw (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxdq %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxdq (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxwd %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxwd (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxwq %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxwq (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxbd %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxbd (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxbq %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxbq (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxbw %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxbw (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxdq %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxdq (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxwd %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxwd (%rax), %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxwq %xmm0, %xmm2 # CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxwq (%rax), %xmm2 # CHECK-NEXT: - - 1.00 - - - - - pmuldq %xmm0, %xmm2 # CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmuldq (%rax), %xmm2 # CHECK-NEXT: - - 1.00 - - - - - pmulld %xmm0, %xmm2 # CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulld (%rax), %xmm2 # CHECK-NEXT: - - 1.00 - - 1.00 - - ptest %xmm0, %xmm1 # CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 ptest (%rax), %xmm1 # CHECK-NEXT: - - - 1.00 - - - - roundpd $1, %xmm0, %xmm2 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 roundpd $1, (%rax), %xmm2 # CHECK-NEXT: - - - 1.00 - - - - roundps $1, %xmm0, %xmm2 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 roundps $1, (%rax), %xmm2 # CHECK-NEXT: - - - 1.00 - - - - roundsd $1, %xmm0, %xmm2 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 roundsd $1, (%rax), %xmm2 # CHECK-NEXT: - - - 1.00 - - - - roundss $1, %xmm0, %xmm2 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 roundss $1, (%rax), %xmm2

{ "language": "Assembly" }

## Test that yaml2obj emits .debug_info section. ## a) Generate the .debug_info section from the "DWARF" entry. ## Generate and verify a DWARF32 little endian .debug_info (DWARFv5) section. # RUN: yaml2obj --docnum=1 -DENDIAN=ELFDATA2LSB %s -o %t1.le.o # RUN: llvm-readobj --sections --section-data %t1.le.o | \ # RUN: FileCheck -DINDEX=2 -DNAME=15 -DOFFSET=0x9B -DSIZE=179 -DADDRALIGN=1 %s --check-prefixes=SHDR,DWARF32-LE-CONTENT # SHDR: Index: [[INDEX]] # SHDR-NEXT: Name: .debug_info ([[NAME]]) # SHDR-NEXT: Type: SHT_PROGBITS (0x1) # SHDR-NEXT: Flags [ (0x0) # SHDR-NEXT: ] # SHDR-NEXT: Address: 0x0 # SHDR-NEXT: Offset: [[OFFSET]] # SHDR-NEXT: Size: [[SIZE]] # SHDR-NEXT: Link: 0 # SHDR-NEXT: Info: 0 # SHDR-NEXT: AddressAlignment: [[ADDRALIGN]] # SHDR-NEXT: EntrySize: 0 # DWARF32-LE-CONTENT-NEXT: SectionData ( # DWARF32-LE-CONTENT-NEXT: 0000: 34120000 05000204 34120000 01785634 ## ^------- unit_length (4-byte) ## ^--- version (2-byte) ## ^- unit_type (1-byte) DW_UT_type ## ^- address_size (1-byte) ## ^------- debug_abbrev_offset (4-byte) ## ^- abbreviation code (LEB128) 0x01 ## ^----- Form: DW_FORM_addr (4-byte) # DWARF32-LE-CONTENT-NEXT: 0010: 12020012 34020000 00123434 12785634 ## -- ## ^--- Form: DW_FORM_block2 size (2-byte) ## ^- ^- Form: DW_FORM_block2 body (2-byte) ## ^-------- Form: DW_FORM_block4 size (4-byte) ## ^-^- Form: DW_FORM_block4 body (2-byte) ## ^---- Form: DW_FORM_data2 (2-byte) ## ^----- Form: DW_FORM_data4 (4-byte) # DWARF32-LE-CONTENT-NEXT: 0020: 12F0DEBC 9A785634 12616263 64000212 ## -- ## ^----------------- Form: DW_FORM_data8 (8-byte) ## ^---------- Form: DW_FORM_string "abcd\0" ## ^- Form: DW_FORM_block size (ULEB128) ## ^- Form: DW_FORM_block body (2-byte) # DWARF32-LE-CONTENT-NEXT: 0030: 34021234 1201B424 78563412 B4247856 ## ^- Form: DW_FORM_block body ## ^- Form: DW_FORM_block1 size (1-byte) ## ^-^- Form: DW_FORM_block1 body (2-byte) ## ^- Form: DW_FORM_data1 (1-byte) ## ^- Form: DW_FORM_flag (1-byte) ## ^--- Form: DW_FORM_sdata (SLEB128) 0x1234 ## ^------- Form: DW_FORM_strp (4-byte) ## ^--- Form: DW_FORM_udata (ULEB128) 0x1234 ## ^--- Form: DW_FORM_ref_addr (4-byte) # DWARF32-LE-CONTENT-NEXT: 0040: 34121234 12785634 12F0DEBC 9A785634 ## ---- ## ^- Form: DW_FORM_ref1 (1-byte) ## ^---- Form: DW_FORM_ref2 (2-byte) ## ^-------- Form: DW_FORM_ref4 (4-byte) ## ^-------------- Form: DW_FORM_ref8 (8-byte) # DWARF32-LE-CONTENT-NEXT: 0050: 12B42408 65666768 00341200 00021234 ## -- ## ^--- Form: DW_FORM_ref_udata (ULEB128) 0x1234 ## ^- Form: DW_FORM_indirect (ULEB128) DW_FORM_string ## ^---------- "efgh\0" ## ^-------- Form: DW_FORM_sec_offset (4-byte) ## ^- Form: DW_FORM_exprloc size (ULEB128) 0x02 ## ^-^- Form: DW_FORM_exprloc body (2-byte) # DWARF32-LE-CONTENT-NEXT: 0060: B424B424 78563412 78563412 78563412 ## ^--- Form: DW_FORM_strx (ULEB128) ## ^--- Form: DW_FORM_addrx (ULEB128) ## ^------- Form: DW_FORM_ref_sup4 (4-byte) ## ^------- Form: DW_FORM_strp_sup (4-byte) ## ^------- Form: DW_FORM_line_strp (4-byte) # DWARF32-LE-CONTENT-NEXT: 0070: F0DEBC9A 78563412 B424B424 F0DEBC9A ## ^---------------- Form: DW_FORM_ref_sig8 (8-byte) ## ^--- Form: DW_FORM_loclistx (ULEB128) ## ^--- Form: DW_FORM_rnglistx (ULEB128) ## ^------- Form: DW_FORM_ref_sup8 (8-byte) # DWARF32-LE-CONTENT-NEXT: 0080: 78563412 12341278 56341212 34127856 ## -------- ## ^- Form: DW_FORM_strx1 (1-byte) ## ^--- Form: DW_FORM_strx2 (2-byte) ## ^-------- Form: DW_FORM_strx4 (4-byte) ## ^- Form: DW_FORM_addrx1 (1-byte) ## ^--- Form: DW_FORM_addrx2 (1-byte) ## ^--- Form: DW_FORM_addrx4 (4-byte) # DWARF32-LE-CONTENT-NEXT: 0090: 34123412 00000500 01043412 00000078 ## ---- ## ^-------- unit_length (4-byte) ## ^--- version (2-byte) ## ^- unit_type (1-byte) ## ^- address_size (1-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- abbrev code (ULEB128) 0x00 ## ^- unit_length (4-byte) # DWARF32-LE-CONTENT-NEXT: 00A0: 56000004 00785600 00040178 56341202 ## ------ ## ^---- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) ## ^- abbrev code (ULEB128) 0x01 ## ^-------- Form: DW_FORM_addr ## ^- Form: DW_FORM_block2 size (2-byte) # DWARF32-LE-CONTENT-NEXT: 00B0: 001234 ## -- ## ^-^- Form: DW_FORM_block2 body (2-byte) # DWARF32-LE-CONTENT-NEXT: ) --- !ELF FileHeader: Class: ELFCLASS64 Data: [[ENDIAN]] Type: ET_EXEC DWARF: debug_abbrev: - Table: - Code: 1 Tag: DW_TAG_compile_unit Children: DW_CHILDREN_no Attributes: - Attribute: 0x01 Form: DW_FORM_addr ## 0x01 - Attribute: 0x01 Form: DW_FORM_block2 ## 0x03 - Attribute: 0x01 Form: DW_FORM_block4 ## 0x04 - Attribute: 0x01 Form: DW_FORM_data2 ## 0x05 - Attribute: 0x01 Form: DW_FORM_data4 ## 0x06 - Attribute: 0x01 Form: DW_FORM_data8 ## 0x07 - Attribute: 0x01 Form: DW_FORM_string ## 0x08 - Attribute: 0x01 Form: DW_FORM_block ## 0x09 - Attribute: 0x01 Form: DW_FORM_block1 ## 0x0a - Attribute: 0x01 Form: DW_FORM_data1 ## 0x0b - Attribute: 0x01 Form: DW_FORM_flag ## 0x0c - Attribute: 0x01 Form: DW_FORM_sdata ## 0x0d - Attribute: 0x01 Form: DW_FORM_strp ## 0x0e - Attribute: 0x01 Form: DW_FORM_udata ## 0x0f - Attribute: 0x01 Form: DW_FORM_ref_addr ## 0x10 - Attribute: 0x01 Form: DW_FORM_ref1 ## 0x11 - Attribute: 0x01 Form: DW_FORM_ref2 ## 0x12 - Attribute: 0x01 Form: DW_FORM_ref4 ## 0x13 - Attribute: 0x01 Form: DW_FORM_ref8 ## 0x14 - Attribute: 0x01 Form: DW_FORM_ref_udata ## 0x15 - Attribute: 0x01 Form: DW_FORM_indirect ## 0x16 - Attribute: 0x01 Form: DW_FORM_sec_offset ## 0x17 - Attribute: 0x01 Form: DW_FORM_exprloc ## 0x18 - Attribute: 0x01 Form: DW_FORM_strx ## 0x1a - Attribute: 0x01 Form: DW_FORM_addrx ## 0x1b - Attribute: 0x01 Form: DW_FORM_ref_sup4 ## 0x1c - Attribute: 0x01 Form: DW_FORM_strp_sup ## 0x1d - Attribute: 0x01 Form: DW_FORM_data16 ## 0x1e - Attribute: 0x01 Form: DW_FORM_line_strp ## 0x1f - Attribute: 0x01 Form: DW_FORM_ref_sig8 ## 0x20 - Attribute: 0x01 Form: DW_FORM_implicit_const ## 0x21 Value: 0x01 - Attribute: 0x01 Form: DW_FORM_loclistx ## 0x22 - Attribute: 0x01 Form: DW_FORM_rnglistx ## 0x23 - Attribute: 0x01 Form: DW_FORM_ref_sup8 ## 0x24 - Attribute: 0x01 Form: DW_FORM_strx1 ## 0x25 - Attribute: 0x01 Form: DW_FORM_strx2 ## 0x26 - Attribute: 0x01 Form: DW_FORM_strx3 ## 0x27 - Attribute: 0x01 Form: DW_FORM_strx4 ## 0x28 - Attribute: 0x01 Form: DW_FORM_addrx1 ## 0x29 - Attribute: 0x01 Form: DW_FORM_addrx2 ## 0x2a - Attribute: 0x01 Form: DW_FORM_addrx3 ## 0x2b - Attribute: 0x01 Form: DW_FORM_addrx4 ## 0x2c debug_info: - Length: 0x1234 Version: 5 UnitType: DW_UT_type AbbrOffset: 0x1234 AddrSize: 4 Entries: - AbbrCode: 1 Values: - Value: 0x12345678 ## DW_FORM_addr - BlockData: ## DW_FORM_block2 - 0x12 - 0x34 - BlockData: ## DW_FORM_block4 - 0x12 - 0x34 - Value: 0x1234 ## DW_FORM_data2 - Value: 0x12345678 ## DW_FORM_data4 - Value: 0x123456789abcdef0 ## DW_FORM_data8 - CStr: abcd ## DW_FORM_string - BlockData: ## DW_FORM_block - 0x12 - 0x34 - BlockData: ## DW_FORM_block1 - 0x12 - 0x34 - Value: 0x12 ## DW_FORM_data1 - Value: 0x01 ## DW_FORM_flag - Value: 0x1234 ## DW_FORM_sdata - Value: 0x12345678 ## DW_FORM_strp - Value: 0x1234 ## DW_FORM_udata - Value: 0x12345678 ## DW_FORM_ref_addr - Value: 0x12 ## DW_FORM_ref1 - Value: 0x1234 ## DW_FORM_ref2 - Value: 0x12345678 ## DW_FORM_ref4 - Value: 0x123456789abcdef0 ## DW_FORM_ref8 - Value: 0x1234 ## DW_FORM_ref_udata - Value: 0x08 ## DW_FORM_indirect. The following value's form is 0x08, which is DW_FORM_string. - CStr: efgh - Value: 0x1234 ## DW_FORM_sec_offset - BlockData: ## DW_FORM_exprloc - 0x12 - 0x34 - Value: 0x1234 ## DW_FORM_strx - Value: 0x1234 ## DW_FORM_addrx - Value: 0x12345678 ## DW_FORM_ref_sup4 - Value: 0x12345678 ## DW_FORM_strp_sup - Value: 0x1234 ## DW_FORM_data16 (unimplemented) - Value: 0x12345678 ## DW_FORM_line_strp - Value: 0x123456789abcdef0 ## DW_FORM_ref_sig8 - Value: 0x1234 ## DW_FORM_implicit_const (unimplemented) - Value: 0x1234 ## DW_FORM_loclistx - Value: 0x1234 ## DW_FORM_rnglistx - Value: 0x123456789abcdef0 ## DW_FORM_ref_sup8 - Value: 0x12 ## DW_FORM_strx1 - Value: 0x1234 ## DW_FORM_strx2 - Value: 0x123456 ## DW_FORM_strx3 (unimplemented) - Value: 0x12345678 ## DW_FORM_strx4 - Value: 0x12 ## DW_FORM_addrx1 - Value: 0x1234 ## DW_FORM_addrx2 - Value: 0x123456 ## DW_FORM_addrx3 (unimplemented) - Value: 0x12345678 ## DW_FORM_addrx4 - Length: 0x1234 Version: 5 ## Test another unit type. UnitType: DW_UT_compile AbbrOffset: 0x1234 AddrSize: 4 Entries: - AbbrCode: 0 Values: [] - Length: 0x5678 ## Test DWARFv4 Version: 4 AbbrevTableID: 0 AbbrOffset: 0x5678 AddrSize: 4 Entries: - AbbrCode: 1 Values: - Value: 0x12345678 ## DW_FORM_addr - BlockData: ## DW_FORM_block2 - 0x12 - 0x34 ## Generate and verify a DWARF32 big endian .debug_info (DWARFv4) section. # RUN: yaml2obj --docnum=1 -DENDIAN=ELFDATA2MSB %s -o %t1.be.o # RUN: llvm-readobj --sections --section-data %t1.be.o | \ # RUN: FileCheck -DINDEX=2 -DNAME=15 -DOFFSET=0x9B -DSIZE=179 -DADDRALIGN=1 %s --check-prefixes=SHDR,DWARF32-BE-CONTENT # DWARF32-BE-CONTENT-NEXT: SectionData ( # DWARF32-BE-CONTENT-NEXT: 0000: 00001234 00050204 00001234 01123456 ## ^------- unit_length (4-byte) ## ^--- version (2-byte) ## ^- unit_type (1-byte) DW_UT_type ## ^- address_size (1-byte) ## ^------- debug_abbrev_offset (4-byte) ## ^- abbreviation code (LEB128) 0x01 ## ^----- Form: DW_FORM_addr (4-byte) # DWARF32-BE-CONTENT-NEXT: 0010: 78000212 34000000 02123412 34123456 ## -- ## ^--- Form: DW_FORM_block2 size (2-byte) ## ^- ^- Form: DW_FORM_block2 body (2-byte) ## ^-------- Form: DW_FORM_block4 size (4-byte) ## ^-^- Form: DW_FORM_block4 body (2-byte) ## ^---- Form: DW_FORM_data2 (2-byte) ## ^----- Form: DW_FORM_data4 (4-byte) # DWARF32-BE-CONTENT-NEXT: 0020: 78123456 789ABCDE F0616263 64000212 ## -- ## ^----------------- Form: DW_FORM_data8 (8-byte) ## ^---------- Form: DW_FORM_string "abcd\0" ## ^- Form: DW_FORM_block size (ULEB128) ## ^- Form: DW_FORM_block body (2-byte) # DWARF32-BE-CONTENT-NEXT: 0030: 34021234 1201B424 12345678 B4241234 ## ^- Form: DW_FORM_block body ## ^- Form: DW_FORM_block1 size (1-byte) ## ^-^- Form: DW_FORM_block1 body (2-byte) ## ^- Form: DW_FORM_data1 (1-byte) ## ^- Form: DW_FORM_flag (1-byte) ## ^--- Form: DW_FORM_sdata (SLEB128) 0x1234 ## ^------- Form: DW_FORM_strp (4-byte) ## ^--- Form: DW_FORM_udata (ULEB128) 0x1234 ## ^--- Form: DW_FORM_ref_addr (4-byte) # DWARF32-BE-CONTENT-NEXT: 0040: 56781212 34123456 78123456 789ABCDE ## ---- ## ^- Form: DW_FORM_ref1 (1-byte) ## ^---- Form: DW_FORM_ref2 (2-byte) ## ^-------- Form: DW_FORM_ref4 (4-byte) ## ^-------------- Form: DW_FORM_ref8 (8-byte) # DWARF32-BE-CONTENT-NEXT: 0050: F0B42408 65666768 00000012 34021234 ## -- ## ^--- Form: DW_FORM_ref_udata (ULEB128) 0x1234 ## ^- Form: DW_FORM_indirect (ULEB128) DW_FORM_string ## ^---------- "efgh\0" ## ^-------- Form: DW_FORM_sec_offset (4-byte) ## ^- Form: DW_FORM_exprloc size (ULEB128) 0x02 ## ^-^- Form: DW_FORM_exprloc body (2-byte) # DWARF32-BE-CONTENT-NEXT: 0060: B424B424 12345678 12345678 12345678 ## ^--- Form: DW_FORM_strx (ULEB128) ## ^--- Form: DW_FORM_addrx (ULEB128) ## ^------- Form: DW_FORM_ref_sup4 (4-byte) ## ^------- Form: DW_FORM_strp_sup (4-byte) ## ^------- Form: DW_FORM_line_strp (4-byte) # DWARF32-BE-CONTENT-NEXT: 0070: 12345678 9ABCDEF0 B424B424 12345678 ## ^---------------- Form: DW_FORM_ref_sig8 (8-byte) ## ^--- Form: DW_FORM_loclistx (ULEB128) ## ^--- Form: DW_FORM_rnglistx (ULEB128) ## ^------- Form: DW_FORM_ref_sup8 (8-byte) # DWARF32-BE-CONTENT-NEXT: 0080: 9ABCDEF0 12123412 34567812 12341234 ## -------- ## ^- Form: DW_FORM_strx1 (1-byte) ## ^--- Form: DW_FORM_strx2 (2-byte) ## ^-------- Form: DW_FORM_strx4 (4-byte) ## ^- Form: DW_FORM_addrx1 (1-byte) ## ^--- Form: DW_FORM_addrx2 (1-byte) ## ^--- Form: DW_FORM_addrx4 (4-byte) # DWARF32-BE-CONTENT-NEXT: 0090: 56780000 12340005 01040000 12340000 ## ---- ## ^-------- unit_length (4-byte) ## ^--- version (2-byte) ## ^- unit_type (1-byte) ## ^- address_size (1-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- abbrev code (ULEB128) 0x00 ## ^- unit_length (4-byte) # DWARF32-BE-CONTENT-NEXT: 00A0: 00567800 04000056 78040112 34567800 ## ------ ## ^---- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) ## ^- abbrev code (ULEB128) 0x01 ## ^-------- Form: DW_FORM_addr ## ^- Form: DW_FORM_block2 size (2-byte) # DWARF32-BE-CONTENT-NEXT: 00B0: 021234 ## -- ## ^-^- Form: DW_FORM_block2 body (2-byte) # DWARF32-BE-CONTENT-NEXT: ) ## b) Generate the .debug_info section from raw section content. # RUN: yaml2obj --docnum=2 %s -o %t2.o # RUN: llvm-readobj --sections --section-data %t2.o | \ # RUN: FileCheck -DINDEX=1 -DNAME=1 -DOFFSET=0x40 -DSIZE=3 -DADDRALIGN=0 %s --check-prefixes=SHDR,ARBITRARY-CONTENT # ARBITRARY-CONTENT-NEXT: SectionData ( # ARBITRARY-CONTENT-NEXT: 0000: 112233 # ARBITRARY-CONTENT-NEXT: ) --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC Sections: - Name: .debug_info Type: SHT_PROGBITS Content: "112233" ## c) Generate the .debug_info section when the "Size" is specified. # RUN: yaml2obj --docnum=3 %s -o %t3.o # RUN: llvm-readobj --sections --section-data %t3.o | \ # RUN: FileCheck -DINDEX=1 -DNAME=1 -DOFFSET=0x40 -DSIZE=16 -DADDRALIGN=0 %s --check-prefixes=SHDR,SIZE # SIZE-NEXT: SectionData ( # SIZE-NEXT: 0000: 00000000 00000000 00000000 00000000 # SIZE-NEXT: ) --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC Sections: - Name: .debug_info Type: SHT_PROGBITS Size: 0x10 ## d) Test that yaml2obj emits an error message when both the "Size" and the ## "debug_info" entry are specified at the same time. # RUN: not yaml2obj --docnum=4 %s 2>&1 | FileCheck %s --check-prefix=AMBIGUOUS-CONTENT # AMBIGUOUS-CONTENT: yaml2obj: error: cannot specify section '.debug_info' contents in the 'DWARF' entry and the 'Content' or 'Size' in the 'Sections' entry at the same time --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC Sections: - Name: .debug_info Type: SHT_PROGBITS Size: 0x10 DWARF: debug_abbrev: - Table: - Code: 1 Tag: DW_TAG_compile_unit Children: DW_CHILDREN_no debug_info: - Length: 0x1234 Version: 5 UnitType: DW_UT_type AbbrOffset: 0x1234 Entries: [] ## e) Test that yaml2obj emits an error message when both the "Content" and the ## "debug_info" entry are specified at the same time. # RUN: not yaml2obj --docnum=5 %s 2>&1 | FileCheck %s --check-prefix=AMBIGUOUS-CONTENT --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC Sections: - Name: .debug_info Type: SHT_PROGBITS Content: "00" DWARF: debug_abbrev: - Table: - Code: 1 Tag: DW_TAG_compile_unit Children: DW_CHILDREN_no debug_info: - Length: 0x1234 Version: 5 UnitType: DW_UT_type AbbrOffset: 0x1234 Entries: [] ## f) Test that all the properties can be overridden by the section header when ## the "debug_info" entry doesn't exist. # RUN: yaml2obj --docnum=6 %s -o %t6.o # RUN: llvm-readelf --sections %t6.o | FileCheck %s --check-prefix=OVERRIDDEN # OVERRIDDEN: [Nr] Name Type Address Off Size ES Flg Lk Inf Al # OVERRIDDEN: [ 1] .debug_info STRTAB 0000000000002020 000050 00000d 01 A 2 1 2 # OVERRIDDEN-NEXT: [ 2] .sec STRTAB 0000000000000000 00005d 000000 00 0 0 0 --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC Sections: - Name: .debug_info Type: SHT_STRTAB ## SHT_PROGBITS by default. Flags: [SHF_ALLOC] ## 0 by default. Link: .sec ## 0 by default. EntSize: 1 ## 0 by default. Info: 1 ## 0 by default. AddressAlign: 2 ## 0 by default. Address: 0x2020 ## 0x00 by default. Offset: 0x50 ## 0x40 for the first section. Size: 0x0d ## Set the "Size" so that we can reuse the check tag "OVERRIDDEN". - Name: .sec ## Linked by .debug_info. Type: SHT_STRTAB ## g) Test that all the properties can be overridden by the section header when ## the "debug_info" entry exists. # RUN: yaml2obj --docnum=7 %s -o %t7.o # RUN: llvm-readelf --sections %t7.o | FileCheck %s --check-prefix=OVERRIDDEN --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC Sections: - Name: .debug_info Type: SHT_STRTAB ## SHT_PROGBITS by default. Flags: [SHF_ALLOC] ## 0 by default. Link: .sec ## 0 by default. EntSize: 1 ## 0 by default. Info: 1 ## 0 by default. AddressAlign: 2 ## 0 by default. Address: 0x2020 ## 0x00 by default. Offset: 0x50 ## 0x40 for the first section. - Name: .sec ## Linked by .debug_info. Type: SHT_STRTAB DWARF: debug_abbrev: - Table: - Code: 1 Tag: DW_TAG_compile_unit Children: DW_CHILDREN_no debug_info: - Length: 0x1234 Version: 5 UnitType: DW_UT_type AbbrOffset: 0x1234 Entries: - AbbrCode: 0 Values: [] ## h) Test that yaml2obj doesn't crash when the 'Entries' of a compilation unit is empty. # RUN: yaml2obj --docnum=8 %s -o %t8.o # RUN: llvm-readelf --hex-dump=.debug_info %t8.o | \ # RUN: FileCheck %s --check-prefix=EMPTY-ENTRIES --match-full-lines # EMPTY-ENTRIES: Hex dump of section '.debug_info': # EMPTY-ENTRIES-NEXT: 0x00000000 34120000 05000204 34120000 4.......4... # EMPTY-ENTRIES-EMPTY: ## ^- 'Entries' is empty --- !ELF FileHeader: Class: ELFCLASS32 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_info: - Length: 0x1234 Version: 5 UnitType: DW_UT_type AbbrOffset: 0x1234 Entries: [] ## h) Test that yaml2obj emits values in the DIE according to the abbreviation whose ## index is equal to the value in 'AbbrevCode'. # RUN: yaml2obj --docnum=9 %s -o %t9.o # RUN: llvm-readelf --hex-dump=.debug_info %t9.o | \ # RUN: FileCheck %s --check-prefix=FORM --match-full-lines # FORM: Hex dump of section '.debug_info': # FORM-NEXT: 0x00000000 34120000 05000204 34120000 02341221 4.......4....4.! ## ^------- unit_length (4-byte) ## ^- abbreviation code (ULEB128) ## ^--- Form: DW_FORM_data2 (2-byte) ## ^- Form: DW_FORM_data4 (4-byte) # FORM-NEXT: 0x00000010 43658701 21436587 341200 Ce..!Ce.4.. ## ------ ## ^- abbreviation code (ULEB128) ## ^------- Form: DW_FORM_data4 (4-byte) ## ^--- Form: DW_FORM_data2 (2-byte) ## ^- abbreviation code (ULEB128) # FORM-EMPTY: --- !ELF FileHeader: Class: ELFCLASS32 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_abbrev: - Table: - Tag: DW_TAG_compile_unit Children: DW_CHILDREN_yes Attributes: - Attribute: DW_AT_low_pc Form: DW_FORM_data4 - Attribute: DW_AT_high_pc Form: DW_FORM_data2 - Tag: DW_TAG_subprogram Children: DW_CHILDREN_no Attributes: - Attribute: DW_AT_low_pc Form: DW_FORM_data2 - Attribute: DW_AT_high_pc Form: DW_FORM_data4 debug_info: - Length: 0x1234 Version: 5 UnitType: DW_UT_type AbbrOffset: 0x1234 Entries: ## Test that yaml2obj emits values when the abbrev code is specified. - AbbrCode: 2 Values: - Value: 0x1234 - Value: 0x87654321 ## Test that yaml2obj emits values when the abbrev code is specified to ## be lower than the first abbrev. - AbbrCode: 1 Values: - Value: 0x87654321 - Value: 0x1234 ## Test that yaml2obj ignores the contents of entries with abbrev code 0. - AbbrCode: 0 Values: - Value: 0x1234 ## i) Test that yaml2obj reports an error when 'debug_info' has values in its ## entries but 'debug_abbrev' doesn't have enough attributes for them. # RUN: not yaml2obj --docnum=10 %s -o %t10.o 2>&1 | \ # RUN: FileCheck %s --check-prefixes=ERROR # ERROR: yaml2obj: error: abbrev code must be less than or equal to the number of entries in abbreviation table --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_abbrev: - Table: [] debug_info: - Length: 0x1234 Version: 5 UnitType: DW_UT_type AbbrOffset: 0x1234 Entries: - AbbrCode: 1 Values: - Value: 0x1234 ## j) Test that yaml2obj emits the correct DWARF64 unit headers. ## DWARFv5 unit header. # RUN: yaml2obj --docnum=11 %s -o %t11.o # RUN: llvm-readelf --hex-dump=.debug_info %t11.o | \ # RUN: FileCheck %s --check-prefix=DWARFV5-HEADER # DWARFV5-HEADER: Hex dump of section '.debug_info': # DWARFV5-HEADER-NEXT: 0x00000000 ffffffff 0c000000 00000000 05000208 ................ ## ^------------------------- unit_length (12-byte) ## ^--- version (2-byte) ## ^- unit_type (1-byte) ## ^- address_size (1-byte) # DWARFV5-HEADER-NEXT: 0x00000010 34120000 00000000 4....... ## ^---------------- debug_abbrev_offset (8-byte) --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_info: - Format: DWARF64 Length: 0x0c Version: 5 UnitType: DW_UT_type AbbrOffset: 0x1234 Entries: [] ## DWARFv4 unit header. # RUN: yaml2obj --docnum=12 %s -o %t12.o # RUN: llvm-readelf --hex-dump=.debug_info %t12.o | \ # RUN: FileCheck %s --check-prefix=DWARFV4-HEADER # DWARFV4-HEADER: Hex dump of section '.debug_info': # DWARFV4-HEADER-NEXT: 0x00000000 ffffffff 0c000000 00000000 04003412 ..............4. ## ^------------------------- unit_length (12-byte) ## ^--- version (2-byte) ## ^--- debug_abbrev_offset (8-byte) # DWARFV4-HEADER-NEXT: 0x00000010 00000000 000008 ....... ## ------------- ## ^- address_size (1-byte) --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_info: - Format: DWARF64 Length: 0x0c Version: 4 AbbrOffset: 0x1234 Entries: [] ## k) Test that yaml2obj is able to emit a correct length for compilation units. # RUN: yaml2obj --docnum=13 %s -o %t13.o # RUN: llvm-readelf --hex-dump=.debug_info %t13.o | \ # RUN: FileCheck %s --check-prefix=INFER-LENGTH # INFER-LENGTH: Hex dump of section '.debug_info': # INFER-LENGTH-NEXT: 0x00000000 37000000 04000000 00000801 00000000 7............... ## ^------- unit_length (0x37) ## ^--- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) ## ^- abbrev code (ULEB128) 0x01 ## ^------- Form: DW_FORM_strp (4-byte) # INFER-LENGTH-NEXT: 0x00000010 0c001600 00000000 00001e00 00002011 .............. . ## ^--- Form: DW_FORM_data2 (2-byte) ## ^-------- Form: DW_FORM_strp (4-byte) ## ^-------- Form: DW_FORM_sec_offset (4-byte) ## ^-------- Form: DW_FORM_strp (4-byte) ## ^--- Form: DW_FORM_addr (8-byte) # INFER-LENGTH-NEXT: 0x00000020 00000000 00003300 00000220 11000000 ......3.... .... ## ------------- ## ^-------- Form: DW_FORM_data4 (4-byte) ## ^- abbrev code (ULEB128) 0x02 ## ^---------- Form: DW_FORM_addr (8-byte) # INFER-LENGTH-NEXT: 0x00000030 00000006 00000038 000000 .......8... ## ------ ## ^-------- Form: DW_FORM_data4 (4-byte) ## ^-------- Form: DW_FORM_strp (4-byte) ## The handwritten DIEs should look like: ## 0x0000000b: DW_TAG_compile_unit [1] * ## DW_AT_producer [DW_FORM_strp] ( .debug_str[0x00000000] = "clang version 10.0.0 ") ## DW_AT_language [DW_FORM_data2] (DW_LANG_C99) ## DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000016] = "hello.c") ## DW_AT_stmt_list [DW_FORM_sec_offset] (0x00000000) ## DW_AT_comp_dir [DW_FORM_strp] ( .debug_str[0x0000001e] = "/home/v/x/llvm/playground") ## DW_AT_low_pc [DW_FORM_addr] (0x0000000000001120) ## DW_AT_high_pc [DW_FORM_data4] (0x00000033) ## ## 0x0000002a: DW_TAG_subprogram [2] ## DW_AT_low_pc [DW_FORM_addr] (0x0000000000001120) ## DW_AT_high_pc [DW_FORM_data4] (0x00000006) ## DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000038] = "main") --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_str: - "clang version 10.0.0 " - "hello.c" - "/home/v/x/llvm/playground" - "main" debug_abbrev: - Table: - Code: 1 Tag: DW_TAG_compile_unit Children: DW_CHILDREN_yes Attributes: - Attribute: DW_AT_producer Form: DW_FORM_strp - Attribute: DW_AT_language Form: DW_FORM_data2 - Attribute: DW_AT_name Form: DW_FORM_strp - Attribute: DW_AT_stmt_list Form: DW_FORM_sec_offset - Attribute: DW_AT_comp_dir Form: DW_FORM_strp - Attribute: DW_AT_low_pc Form: DW_FORM_addr - Attribute: DW_AT_high_pc Form: DW_FORM_data4 - Code: 2 Tag: DW_TAG_subprogram Children: DW_CHILDREN_no Attributes: - Attribute: DW_AT_low_pc Form: DW_FORM_addr - Attribute: DW_AT_high_pc Form: DW_FORM_data4 - Attribute: DW_AT_name Form: DW_FORM_strp debug_info: - Version: 4 AbbrOffset: 0x00 Entries: - AbbrCode: 1 Values: - Value: 0x00 ## DW_AT_producer [DW_FORM_strp] - Value: 0x0c ## DW_LANG_C99, DW_AT_language [DW_FORM_data2] - Value: 0x16 ## DW_AT_name [DW_FORM_strp] - Value: 0x00 ## DW_AT_stmt_list [DW_FORM_sec_offset] - Value: 0x1e ## DW_AT_comp_dir [DW_FORM_strp] - Value: 0x1120 ## DW_AT_low_pc [DW_FORM_addr] - Value: 0x33 ## DW_AT_high_pc [DW_FORM_data4] - AbbrCode: 2 Values: - Value: 0x1120 ## DW_AT_low_pc [DW_FORM_addr] - Value: 0x06 ## DW_AT_high_pc [DW_FORM_data4] - Value: 0x38 ## DW_AT_name [DW_FORM_strp] ## l) Test that if we don't specify the 'Values' key for an entry, yaml2obj will only emit the abbrev_code. # RUN: yaml2obj --docnum=14 %s -o %t14.o # RUN: llvm-readelf --hex-dump=.debug_info %t14.o | \ # RUN: FileCheck %s --check-prefix=NO-VALUES # NO-VALUES: Hex dump of section '.debug_info': # NO-VALUES-NEXT: 0x00000000 0a000000 04000000 00000801 0002 .............. ## ^------- unit_length (4-byte) ## ^--- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) ## ^- abbrev_code (ULEB128) 0x01 ## ^- abbrev_code (ULEB128) 0x00 ## ^- abbrev_code (ULEB128) 0x02 --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_info: - Version: 4 AbbrOffset: 0x00 Entries: - AbbrCode: 1 - AbbrCode: 0 - AbbrCode: 2 ## m) Test that yaml2obj is able to infer the address size from the object file. # RUN: yaml2obj --docnum=15 -DBITS=64 %s -o %t15.64-bit.o # RUN: llvm-readelf --hex-dump=.debug_info %t15.64-bit.o | \ # RUN: FileCheck %s --check-prefix=ADDRSIZE -DADDRSIZE=08 # ADDRSIZE: Hex dump of section '.debug_info': # ADDRSIZE-NEXT: 0x00000000 07000000 04000000 0000[[ADDRSIZE]] ........... # RUN: yaml2obj --docnum=15 -DBITS=32 %s -o %t15.32-bit.o # RUN: llvm-readelf --hex-dump=.debug_info %t15.32-bit.o | \ # RUN: FileCheck %s --check-prefix=ADDRSIZE -DADDRSIZE=04 --- !ELF FileHeader: Class: ELFCLASS[[BITS]] Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_info: - Version: 4 AbbrOffset: 0x00 ## n) Test that yaml2obj emits an error message when a compilation unit has values but there is no associated abbrev table. ## RUN: not yaml2obj --docnum=16 %s 2>&1 | FileCheck %s --check-prefix=NO-ABBREV # NO-ABBREV: yaml2obj: error: cannot find abbrev table whose ID is 0 for compilation unit with index 0 --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC Machine: EM_X86_64 DWARF: debug_info: - Version: 4 AbbrOffset: 0x00 Entries: - AbbrCode: 1 Values: - Value: 0x1234 ## o) Test that yaml2obj is able to generate compilation units according to the ## associated abbrev table that is referenced by the 'AbbrevTableID' and infer ## the value of the debug_abbrev_offset field. # RUN: yaml2obj --docnum=17 %s -o %t17.o # RUN: llvm-readelf --hex-dump=.debug_info %t17.o | FileCheck %s --check-prefix=MULTI-TABLES # MULTI-TABLES: Hex dump of section '.debug_info': # MULTI-TABLES-NEXT: 0x00000000 0c000000 04000800 00000801 34120000 ............4... ## ^------- unit_length (4-byte) ## ^--- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) ## ^- abbrev_code (ULEB128) 0x01 ## ^------- Form: DW_FORM_data4 (4-byte) 0x1234 # MULTI-TABLES-NEXT: 0x00000010 0c000000 04000800 00000801 21430000 ............!C.. ## ^------- unit_length (4-byte) ## ^--- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) ## ^- abbrev_code (ULEB128) 0x01 ## ^------- Form: DW_FORM_data4 (4-byte) 0x4321 # MULTI-TABLES-NEXT: 0x00000020 10000000 04000000 00000801 78560000 ............xV.. ## ^------- unit_length (4-byte) ## ^--- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) ## ^- abbrev_code (ULEB128) 0x01 ## ^------- Form: DW_FORM_addr (8-byte) 0x5678 # MULTI-TABLES-NEXT: 0x00000030 00000000 0b000000 04001000 00000801 ................ ## -------- ## ^------- unit_length (4-byte) ## ^--- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) ## ^- abbrev_code (ULEB128) 0x01 # MULTI-TABLES-NEXT: 0x00000040 e58e02 ... ## ^----- Form: DW_FORM_udata (ULEB128) 0x8765 --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_abbrev: - Table: - Code: 1 Tag: DW_TAG_compile_unit Children: DW_CHILDREN_no Attributes: - Attribute: DW_AT_low_pc Form: DW_FORM_addr - ID: 2 Table: - Code: 1 Tag: DW_TAG_compile_unit Children: DW_CHILDREN_no Attributes: - Attribute: DW_AT_low_pc Form: DW_FORM_data4 - ID: 1 Table: - Code: 1 Tag: DW_TAG_compile_unit Children: DW_CHILDREN_no Attributes: - Attribute: DW_AT_low_pc Form: DW_FORM_udata debug_info: - Version: 4 AbbrevTableID: 2 Entries: - AbbrCode: 1 Values: - Value: 0x1234 - Version: 4 AbbrevTableID: 2 Entries: - AbbrCode: 1 Values: - Value: 0x4321 - Version: 4 AbbrevTableID: 0 Entries: - AbbrCode: 1 Values: - Value: 0x5678 - Version: 4 AbbrevTableID: 1 Entries: - AbbrCode: 1 Values: - Value: 0x8765 ## p) Test that when the debug_abbrev_offset field isn't specified and there is no associated ## abbrev table, yaml2obj will assign 0 to the debug_abbrev_offset field. # RUN: yaml2obj --docnum=18 %s -o %t18.o # RUN: llvm-readelf --hex-dump=.debug_info %t18.o | FileCheck %s --check-prefix=ZERO-OFFSET # ZERO-OFFSET: Hex dump of section '.debug_info': # ZERO-OFFSET-NEXT: 0x00000000 07000000 04000000 000008 ........... ## ^------- unit_length (4-byte) ## ^--- version (2-byte) ## ^-------- debug_abbrev_offset (4-byte) ## ^- address_size (1-byte) --- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC DWARF: debug_info: - Version: 4 AbbrevTableID: [[ABBREVID=<none>]] ## q) Test that when we assign an invalid 'AbbrevTableID' that doesn't point to an abbrev table, ## yaml2obj will assign 0 to the debug_abbrev_offset field. # RUN: yaml2obj --docnum=18 -DABBREVID=2 %s -o %t18.o # RUN: llvm-readelf --hex-dump=.debug_info %t18.o | FileCheck %s --check-prefix=ZERO-OFFSET

{ "language": "Assembly" }

.set LOCALID_STEVEN, 3 .set LOCALID_ARCHIE, 4 .set LOCALID_MAXIE, 5 Route128_MapScripts:: @ 81F6B38 map_script MAP_SCRIPT_ON_TRANSITION, Route128_OnTransition map_script MAP_SCRIPT_ON_FRAME_TABLE, Route128_OnFrame .byte 0 Route128_OnTransition: @ 81F6B43 call_if_set FLAG_SYS_WEATHER_CTRL, Common_EventScript_SetAbnormalWeather end Route128_OnFrame: @ 81F6B4D map_script_2 VAR_ROUTE128_STATE, 1, Route128_EventScript_KyogreAwakenedScene .2byte 0 Route128_EventScript_KyogreAwakenedScene:: @ 81F6B57 lockall delay 20 applymovement LOCALID_ARCHIE, Route128_Movement_ArchieLookAround waitmovement 0 msgbox Route128_Text_ArchieWhatHappened, MSGBOX_DEFAULT closemessage applymovement LOCALID_ARCHIE, Route128_Movement_ArchieBackUp waitmovement 0 msgbox Route128_Text_ArchieIOnlyWanted, MSGBOX_DEFAULT closemessage applymovement LOCALID_MAXIE, Route128_Movement_MaxieApproachArchie waitmovement 0 applymovement LOCALID_ARCHIE, Common_Movement_WalkInPlaceFastestUp waitmovement 0 msgbox Route128_Text_MaxieDoYouUnderstandNow, MSGBOX_DEFAULT closemessage applymovement LOCALID_MAXIE, Route128_Movement_MaxieApproachPlayer waitmovement 0 applymovement OBJ_EVENT_ID_PLAYER, Common_Movement_WalkInPlaceFastestUp waitmovement 0 msgbox Route128_Text_MaxieResposibilityFallsToArchieAndMe, MSGBOX_DEFAULT closemessage applymovement LOCALID_ARCHIE, Route128_Movement_ArchieRunLeft applymovement OBJ_EVENT_ID_PLAYER, Common_Movement_WalkInPlaceFastestLeft applymovement LOCALID_MAXIE, Route128_Movement_MaxieWalkLeft waitmovement 0 msgbox Route128_Text_MaxieThisDefiesBelief, MSGBOX_DEFAULT closemessage delay 40 applymovement LOCALID_MAXIE, Route128_Movement_MaxieExit applymovement LOCALID_ARCHIE, Route128_Movement_ArchieExit waitmovement 0 removeobject LOCALID_MAXIE removeobject LOCALID_ARCHIE delay 100 setfieldeffectargument 0, 1 dofieldeffect FLDEFF_NPCFLY_OUT waitfieldeffect FLDEFF_NPCFLY_OUT addobject LOCALID_STEVEN applymovement LOCALID_STEVEN, Route128_Movement_StevenApproachPlayer waitmovement 0 applymovement OBJ_EVENT_ID_PLAYER, Common_Movement_WalkInPlaceFastestRight waitmovement 0 msgbox Route128_Text_StevenWhatIsHappening, MSGBOX_DEFAULT closemessage applymovement LOCALID_STEVEN, Route128_Movement_StevenWalkUp applymovement OBJ_EVENT_ID_PLAYER, Common_Movement_WalkInPlaceFastestUp waitmovement 0 msgbox Route128_Text_StevenWholeWorldWillDrown, MSGBOX_DEFAULT applymovement LOCALID_STEVEN, Common_Movement_WalkInPlaceFastestDown waitmovement 0 msgbox Route128_Text_StevenImGoingToSootopolis, MSGBOX_DEFAULT closemessage applymovement LOCALID_STEVEN, Common_Movement_WalkInPlaceFastestDown waitmovement 0 delay 50 setfieldeffectargument 0, 1 dofieldeffect FLDEFF_NPCFLY_OUT delay 15 removeobject LOCALID_STEVEN waitfieldeffect FLDEFF_NPCFLY_OUT clearflag FLAG_HIDE_MAP_NAME_POPUP setvar VAR_ROUTE128_STATE, 2 releaseall end Route128_Movement_Unused1: @ 81F6C76 walk_fast_left step_end Route128_Movement_Unused2: @ 81F6C78 walk_left walk_left walk_left walk_left walk_left walk_left walk_up walk_up walk_up walk_up walk_up walk_up step_end Route128_Movement_StevenWalkUp: @ 81F6C85 walk_up step_end Route128_Movement_StevenApproachPlayer: @ 81F6C87 walk_fast_left step_end Route128_Movement_ArchieLookAround: @ 81F6C89 walk_fast_down walk_in_place_fastest_left delay_16 walk_in_place_fastest_right delay_16 delay_16 walk_in_place_fastest_down step_end Route128_Movement_ArchieBackUp: @ 81F6C91 lock_facing_direction walk_slow_up delay_16 unlock_facing_direction step_end Route128_Movement_ArchieRunLeft: @ 81F6C96 walk_fast_left walk_fast_left walk_fast_left walk_in_place_fastest_right step_end Route128_Movement_ArchieExit: @ 81F6C9B delay_16 delay_16 walk_fast_up walk_fast_left walk_fast_up walk_fast_up walk_fast_up walk_fast_up walk_fast_up walk_fast_up walk_fast_up walk_fast_up step_end Route128_Movement_MaxieWalkLeft: @ 81F6CA8 walk_left walk_left delay_8 delay_4 step_end Route128_Movement_MaxieApproachArchie: @ 81F6CAD walk_left walk_in_place_fastest_down step_end Route128_Movement_MaxieExit: @ 81F6CB0 walk_fast_left walk_fast_left walk_fast_left walk_fast_up walk_fast_up walk_fast_up walk_fast_up walk_fast_up walk_fast_up walk_fast_up step_end Route128_Movement_MaxieApproachPlayer: @ 81F6CBB walk_right walk_in_place_fastest_down step_end Route128_EventScript_Isaiah:: @ 81F6CBE trainerbattle_single TRAINER_ISAIAH_1, Route128_Text_IsaiahIntro, Route128_Text_IsaiahDefeat, Route128_EventScript_RegisterIsaiah specialvar VAR_RESULT, ShouldTryRematchBattle compare VAR_RESULT, TRUE goto_if_eq Route128_EventScript_RematchIsaiah msgbox Route128_Text_IsaiahPostBattle, MSGBOX_DEFAULT release end Route128_EventScript_RegisterIsaiah:: @ 81F6CEA special PlayerFaceTrainerAfterBattle waitmovement 0 msgbox Route128_Text_IsaiahRegister, MSGBOX_DEFAULT register_matchcall TRAINER_ISAIAH_1 release end Route128_EventScript_RematchIsaiah:: @ 81F6D09 trainerbattle_rematch TRAINER_ISAIAH_1, Route128_Text_IsaiahRematchIntro, Route128_Text_IsaiahRematchDefeat msgbox Route128_Text_IsaiahPostRematch, MSGBOX_AUTOCLOSE end Route128_EventScript_Katelyn:: @ 81F6D20 trainerbattle_single TRAINER_KATELYN_1, Route128_Text_KatelynIntro, Route128_Text_KatelynDefeat, Route128_EventScript_RegisterKatelyn specialvar VAR_RESULT, ShouldTryRematchBattle compare VAR_RESULT, TRUE goto_if_eq Route128_EventScript_RematchKatelyn msgbox Route128_Text_KatelynPostBattle, MSGBOX_DEFAULT release end Route128_EventScript_RegisterKatelyn:: @ 81F6D4C special PlayerFaceTrainerAfterBattle waitmovement 0 msgbox Route128_Text_KatelynRegister, MSGBOX_DEFAULT register_matchcall TRAINER_KATELYN_1 release end Route128_EventScript_RematchKatelyn:: @ 81F6D6B trainerbattle_rematch TRAINER_KATELYN_1, Route128_Text_KatelynRematchIntro, Route128_Text_KatelynRematchDefeat msgbox Route128_Text_KatelynPostRematch, MSGBOX_AUTOCLOSE end Route128_EventScript_Alexa:: @ 81F6D82 trainerbattle_single TRAINER_ALEXA, Route128_Text_AlexaIntro, Route128_Text_AlexaDefeat msgbox Route128_Text_AlexaPostBattle, MSGBOX_AUTOCLOSE end Route128_EventScript_Ruben:: @ 81F6D99 trainerbattle_single TRAINER_RUBEN, Route128_Text_RubenIntro, Route128_Text_RubenDefeat msgbox Route128_Text_RubenPostBattle, MSGBOX_AUTOCLOSE end Route128_EventScript_Wayne:: @ 81F6DB0 trainerbattle_single TRAINER_WAYNE, Route128_Text_WayneIntro, Route128_Text_WayneDefeat msgbox Route128_Text_WaynePostBattle, MSGBOX_AUTOCLOSE end Route128_EventScript_Harrison:: @ 81F6DC7 trainerbattle_single TRAINER_HARRISON, Route128_Text_HarrisonIntro, Route128_Text_HarrisonDefeat msgbox Route128_Text_HarrisonPostBattle, MSGBOX_AUTOCLOSE end Route128_EventScript_Carlee:: @ 81F6DDE trainerbattle_single TRAINER_CARLEE, Route128_Text_CarleeIntro, Route128_Text_CarleeDefeat msgbox Route128_Text_CarleePostBattle, MSGBOX_AUTOCLOSE end Route128_Text_ArchieWhatHappened: @ 81F6DF5 .string "ARCHIE: What happened…\n" .string "What is this wretched scene…\p" .string "Did I…make a horrible mistake?$" Route128_Text_ArchieIOnlyWanted: @ 81F6E48 .string "I…\n" .string "I only wanted…$" Route128_Text_MaxieDoYouUnderstandNow: @ 81F6E5A .string "MAXIE: Do you understand now,\n" .string "ARCHIE?\p" .string "Do you finally see how disastrous\n" .string "your dream turned out to be?\p" .string "We have to hurry! We have to do\n" .string "something before the situation goes\l" .string "completely out of control!$" Route128_Text_MaxieResposibilityFallsToArchieAndMe: @ 81F6F1E .string "MAXIE: {PLAYER}, don't say anything.\p" .string "I know that I have no right to be\n" .string "critical of ARCHIE…\p" .string "But the way things are now, I doubt\n" .string "that we humans will be capable of\l" .string "doing anything about it.\p" .string "But neither can we stand by and\n" .string "just watch helplessly.\p" .string "The responsibility for putting an end\n" .string "to this falls to ARCHIE and me…$" Route128_Text_MaxieThisDefiesBelief: @ 81F704F .string "MAXIE: This defies belief…\p" .string "Those super-ancient POKéMON…\p" .string "Their power is unbelievable.\n" .string "They've upset the balance of nature…$" Route128_Text_StevenWhatIsHappening: @ 81F70C9 .string "STEVEN: {PLAYER}{KUN}!\n" .string "What is happening?$" Route128_Text_StevenWholeWorldWillDrown: @ 81F70EA .string "This is terrible…\p" .string "After the scorching heat wave ended,\n" .string "this deluge began.\p" .string "If this doesn't stop, all of HOENN…\n" .string "No, the whole world will drown.\p" .string "This huge rain cloud is spreading\n" .string "from above SOOTOPOLIS…\p" .string "What in the world is taking place there?\p" .string "There's no point arguing here…\n" .string "SOOTOPOLIS might provide answers…$" Route128_Text_StevenImGoingToSootopolis: @ 81F721B .string "{PLAYER}{KUN}…\n" .string "I don't know what you intend to do,\l" .string "but don't do anything reckless.\p" .string "Okay.\n" .string "I'm going to SOOTOPOLIS.$"

{ "language": "Assembly" }

// RUN: echo "fun:*foo*" > %t.never-instrument // RUN: echo "src:*xray-never-instrument.cpp" >> %t.never-instrument // RUN: echo "[never]" > %t.xray-attrlist // RUN: echo "fun:*foo*" >> %t.xray-attrlist // RUN: echo "src:*xray-never-instrument.cpp" >> %t.xray-attrlist // RUN: %clang_cc1 -fxray-instrument -x c++ -std=c++11 \ // RUN: -fxray-never-instrument=%t.never-instrument -emit-llvm -o - %s \ // RUN: -triple x86_64-unknown-linux-gnu | FileCheck %s // RUN: %clang_cc1 -fxray-instrument -x c++ -std=c++11 \ // RUN: -fxray-attr-list=%t.xray-attrlist -emit-llvm -o - %s \ // RUN: -triple x86_64-unknown-linux-gnu | FileCheck %s void foo() {} [[clang::xray_always_instrument]] void bar() {} void baz() {} // CHECK: define void @_Z3foov() #[[NEVERATTR:[0-9]+]] { // CHECK: define void @_Z3barv() #[[ALWAYSATTR:[0-9]+]] { // CHECK: define void @_Z3bazv() #[[NEVERATTR:[0-9]+]] { // CHECK: attributes #[[NEVERATTR]] = {{.*}} "function-instrument"="xray-never" {{.*}} // CHECK: attributes #[[ALWAYSATTR]] = {{.*}} "function-instrument"="xray-always" {{.*}}

{ "language": "Assembly" }

# RUN: llvm-mc -triple=hexagon -disassemble < %s 2>&1 | FileCheck %s #CHECK: warning: invalid instruction encoding 0x00 0x80 0x00 0x7f 0x00 0x80 0x00 0x7f 0x00 0x80 0x00 0x7f 0x00 0xc0 0x00 0x7f

{ "language": "Assembly" }

# Automatically Generated: do not edit this file # autoscan's mapping to Autoconf macros -*- Makefile -*- # Copyright (C) 1992, 1993, 1994, 1996, 1999, 2000, 2001, 2002, 2009 # Free Software Foundation, Inc. # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation, either version 3 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program. If not, see <http://www.gnu.org/licenses/>. function: __argz_count AC_CHECK_FUNCS function: __argz_next AC_CHECK_FUNCS function: __argz_stringify AC_CHECK_FUNCS function: __fpending AC_CHECK_FUNCS function: acl AC_CHECK_FUNCS function: alarm AC_CHECK_FUNCS function: alloca AC_FUNC_ALLOCA function: atexit AC_CHECK_FUNCS function: btowc AC_CHECK_FUNCS function: bzero AC_CHECK_FUNCS function: chown AC_FUNC_CHOWN function: clock_gettime AC_CHECK_FUNCS function: dcgettext AM_GNU_GETTEXT function: doprnt AC_CHECK_FUNCS function: dup2 AC_CHECK_FUNCS function: endgrent AC_CHECK_FUNCS function: endpwent AC_CHECK_FUNCS function: error AC_FUNC_ERROR_AT_LINE function: error_at_line AC_FUNC_ERROR_AT_LINE function: euidaccess AC_CHECK_FUNCS function: fchdir AC_CHECK_FUNCS function: fdatasync AC_CHECK_FUNCS function: fesetround AC_CHECK_FUNCS function: floor AC_CHECK_FUNCS function: fork AC_FUNC_FORK function: fs_stat_dev AC_CHECK_FUNCS function: fseeko AC_FUNC_FSEEKO function: ftello AC_FUNC_FSEEKO function: ftime AC_CHECK_FUNCS function: ftruncate AC_CHECK_FUNCS function: getcwd AC_CHECK_FUNCS function: getdelim AC_CHECK_FUNCS function: getgroups AC_FUNC_GETGROUPS function: gethostbyaddr AC_CHECK_FUNCS function: gethostbyname AC_CHECK_FUNCS function: gethostname AC_CHECK_FUNCS function: gethrtime AC_CHECK_FUNCS function: getmntent AC_CHECK_FUNCS function: getmntent AC_FUNC_GETMNTENT function: getmntinfo AC_CHECK_FUNCS function: getpagesize AC_CHECK_FUNCS function: getpass AC_CHECK_FUNCS function: getspnam AC_CHECK_FUNCS function: gettimeofday AC_CHECK_FUNCS function: getusershell AC_CHECK_FUNCS function: getwd warn: getwd is deprecated, use getcwd instead function: hasmntopt AC_CHECK_FUNCS function: inet_ntoa AC_CHECK_FUNCS function: isascii AC_CHECK_FUNCS function: iswprint AC_CHECK_FUNCS function: lchown AC_CHECK_FUNCS function: listmntent AC_CHECK_FUNCS function: localeconv AC_CHECK_FUNCS function: localtime_r AC_CHECK_FUNCS function: lstat AC_FUNC_LSTAT_FOLLOWS_SLASHED_SYMLINK function: major AC_HEADER_MAJOR function: makedev AC_HEADER_MAJOR function: malloc AC_FUNC_MALLOC function: mblen AC_CHECK_FUNCS function: mbrlen AC_CHECK_FUNCS function: mbrtowc AC_FUNC_MBRTOWC function: memchr AC_CHECK_FUNCS function: memmove AC_CHECK_FUNCS function: mempcpy AC_CHECK_FUNCS function: memset AC_CHECK_FUNCS function: minor AC_HEADER_MAJOR function: mkdir AC_CHECK_FUNCS function: mkfifo AC_CHECK_FUNCS function: mktime AC_FUNC_MKTIME function: mmap AC_FUNC_MMAP function: modf AC_CHECK_FUNCS function: munmap AC_CHECK_FUNCS function: next_dev AC_CHECK_FUNCS function: nl_langinfo AC_CHECK_FUNCS function: obstack_init AC_FUNC_OBSTACK function: pathconf AC_CHECK_FUNCS function: pow AC_CHECK_FUNCS function: pstat_getdynamic AC_CHECK_FUNCS function: putenv AC_CHECK_FUNCS function: re_comp AC_CHECK_FUNCS function: realloc AC_FUNC_REALLOC function: realpath AC_CHECK_FUNCS function: regcmp AC_CHECK_FUNCS function: regcomp AC_CHECK_FUNCS function: resolvepath AC_CHECK_FUNCS function: rint AC_CHECK_FUNCS function: rmdir AC_CHECK_FUNCS function: rpmatch AC_CHECK_FUNCS function: select AC_CHECK_FUNCS function: setenv AC_CHECK_FUNCS function: sethostname AC_CHECK_FUNCS function: setlocale AC_CHECK_FUNCS function: socket AC_CHECK_FUNCS function: sqrt AC_CHECK_FUNCS function: stime AC_CHECK_FUNCS function: stpcpy AC_CHECK_FUNCS function: strcasecmp AC_CHECK_FUNCS function: strchr AC_CHECK_FUNCS function: strcoll AC_FUNC_STRCOLL function: strcspn AC_CHECK_FUNCS function: strdup AC_CHECK_FUNCS function: strerror AC_CHECK_FUNCS function: strerror_r AC_FUNC_STRERROR_R function: strncasecmp AC_CHECK_FUNCS function: strndup AC_CHECK_FUNCS function: strnlen AC_FUNC_STRNLEN function: strpbrk AC_CHECK_FUNCS function: strrchr AC_CHECK_FUNCS function: strspn AC_CHECK_FUNCS function: strstr AC_CHECK_FUNCS function: strtod AC_FUNC_STRTOD function: strtol AC_CHECK_FUNCS function: strtoul AC_CHECK_FUNCS function: strtoull AC_CHECK_FUNCS function: strtoumax AC_CHECK_FUNCS function: strverscmp AC_CHECK_FUNCS function: sysinfo AC_CHECK_FUNCS function: tzset AC_CHECK_FUNCS function: uname AC_CHECK_FUNCS function: utime AC_CHECK_FUNCS function: utmpname AC_CHECK_FUNCS function: utmpxname AC_CHECK_FUNCS function: vfork AC_FUNC_FORK function: wait3 AC_FUNC_WAIT3 function: wcwidth AC_CHECK_FUNCS header: OS.h AC_CHECK_HEADERS header: X11/Xlib.h AC_PATH_X header: alloca.h AC_FUNC_ALLOCA header: argz.h AC_CHECK_HEADERS header: arpa/inet.h AC_CHECK_HEADERS header: fcntl.h AC_CHECK_HEADERS header: fenv.h AC_CHECK_HEADERS header: float.h AC_CHECK_HEADERS header: fs_info.h AC_CHECK_HEADERS header: inttypes.h AC_CHECK_HEADERS header: langinfo.h AC_CHECK_HEADERS header: libintl.h AC_CHECK_HEADERS header: limits.h AC_CHECK_HEADERS header: locale.h AC_CHECK_HEADERS header: mach/mach.h AC_CHECK_HEADERS header: malloc.h AC_CHECK_HEADERS header: memory.h AC_CHECK_HEADERS header: mntent.h AC_CHECK_HEADERS header: mnttab.h AC_CHECK_HEADERS header: netdb.h AC_CHECK_HEADERS header: netinet/in.h AC_CHECK_HEADERS header: nl_types.h AC_CHECK_HEADERS header: nlist.h AC_CHECK_HEADERS header: paths.h AC_CHECK_HEADERS header: resolv.h AC_HEADER_RESOLV header: sgtty.h AC_CHECK_HEADERS header: shadow.h AC_CHECK_HEADERS header: stddef.h AC_CHECK_HEADERS header: stdint.h AC_CHECK_HEADERS header: stdio_ext.h AC_CHECK_HEADERS header: stdlib.h AC_CHECK_HEADERS header: string.h AC_CHECK_HEADERS header: strings.h AC_CHECK_HEADERS header: sys/acl.h AC_CHECK_HEADERS header: sys/file.h AC_CHECK_HEADERS header: sys/filsys.h AC_CHECK_HEADERS header: sys/fs/s5param.h AC_CHECK_HEADERS header: sys/fs_types.h AC_CHECK_HEADERS header: sys/fstyp.h AC_CHECK_HEADERS header: sys/ioctl.h AC_CHECK_HEADERS header: sys/mkdev.h AC_HEADER_MAJOR header: sys/mntent.h AC_CHECK_HEADERS header: sys/mount.h AC_CHECK_HEADERS header: sys/param.h AC_CHECK_HEADERS header: sys/socket.h AC_CHECK_HEADERS header: sys/statfs.h AC_CHECK_HEADERS header: sys/statvfs.h AC_CHECK_HEADERS header: sys/systeminfo.h AC_CHECK_HEADERS header: sys/time.h AC_CHECK_HEADERS header: sys/timeb.h AC_CHECK_HEADERS header: sys/vfs.h AC_CHECK_HEADERS header: sys/window.h AC_CHECK_HEADERS header: syslog.h AC_CHECK_HEADERS header: termio.h AC_CHECK_HEADERS header: termios.h AC_CHECK_HEADERS header: unistd.h AC_CHECK_HEADERS header: utime.h AC_CHECK_HEADERS header: utmp.h AC_CHECK_HEADERS header: utmpx.h AC_CHECK_HEADERS header: values.h AC_CHECK_HEADERS header: wchar.h AC_CHECK_HEADERS header: wctype.h AC_CHECK_HEADERS identifier: bool AC_HEADER_STDBOOL identifier: false AC_HEADER_STDBOOL identifier: gid_t AC_TYPE_UID_T identifier: inline AC_C_INLINE identifier: int16_t AC_TYPE_INT16_T identifier: int32_t AC_TYPE_INT32_T identifier: int64_t AC_TYPE_INT64_T identifier: int8_t AC_TYPE_INT8_T identifier: mode_t AC_TYPE_MODE_T identifier: obstack AC_FUNC_OBSTACK identifier: off_t AC_TYPE_OFF_T identifier: pid_t AC_TYPE_PID_T identifier: ptrdiff_t AC_CHECK_TYPES identifier: restrict AC_C_RESTRICT identifier: size_t AC_TYPE_SIZE_T identifier: ssize_t AC_TYPE_SSIZE_T identifier: st_blksize AC_CHECK_MEMBERS([struct stat.st_blksize]) identifier: st_blocks AC_STRUCT_ST_BLOCKS identifier: st_rdev AC_CHECK_MEMBERS([struct stat.st_rdev]) identifier: sys_siglist AC_CHECK_DECLS([sys_siglist]) identifier: tm_zone AC_STRUCT_TIMEZONE identifier: true AC_HEADER_STDBOOL identifier: uid_t AC_TYPE_UID_T identifier: uint16_t AC_TYPE_UINT16_T identifier: uint32_t AC_TYPE_UINT32_T identifier: uint64_t AC_TYPE_UINT64_T identifier: uint8_t AC_TYPE_UINT8_T makevar: AWK AC_PROG_AWK makevar: BISON AC_PROG_YACC makevar: CC AC_PROG_CC makevar: CPP AC_PROG_CPP makevar: CXX AC_PROG_CXX makevar: INSTALL AC_PROG_INSTALL makevar: LEX AC_PROG_LEX makevar: LN AC_PROG_LN_S makevar: MAKE AC_PROG_MAKE_SET makevar: MKDIR_P AC_PROG_MKDIR_P makevar: OBJC AC_PROG_OBJC makevar: OBJCXX AC_PROG_OBJCXX makevar: RANLIB AC_PROG_RANLIB makevar: YACC AC_PROG_YACC makevar: YFLAGS AC_PROG_YACC program: CC AC_PROG_CXX program: awk AC_PROG_AWK program: bison AC_PROG_YACC program: byacc AC_PROG_YACC program: c++ AC_PROG_CXX program: cc AC_PROG_CC program: cpp AC_PROG_CPP program: flex AC_PROG_LEX program: g++ AC_PROG_CXX program: gawk AC_PROG_AWK program: gcc AC_PROG_CC program: install AC_PROG_INSTALL program: lex AC_PROG_LEX program: ln AC_PROG_LN_S program: make AC_PROG_MAKE_SET program: mawk AC_PROG_AWK program: nawk AC_PROG_AWK program: objc AC_PROG_OBJC program: objcc AC_PROG_OBJC program: objcxx AC_PROG_OBJCXX program: ranlib AC_PROG_RANLIB program: yacc AC_PROG_YACC

{ "language": "Assembly" }

// Copyright 2016 Adrien Descamps // Distributed under BSD 3-Clause License /* You need to define the following macros before including this file: SSE_FUNCTION_NAME STD_FUNCTION_NAME YUV_FORMAT RGB_FORMAT */ /* You may define the following macro, which affects generated code: SSE_ALIGNED */ #ifdef SSE_ALIGNED /* Unaligned instructions seem faster, even on aligned data? */ /* #define LOAD_SI128 _mm_load_si128 #define SAVE_SI128 _mm_stream_si128 */ #define LOAD_SI128 _mm_loadu_si128 #define SAVE_SI128 _mm_storeu_si128 #else #define LOAD_SI128 _mm_loadu_si128 #define SAVE_SI128 _mm_storeu_si128 #endif #define UV2RGB_16(U,V,R1,G1,B1,R2,G2,B2) \ r_tmp = _mm_mullo_epi16(V, _mm_set1_epi16(param->v_r_factor)); \ g_tmp = _mm_add_epi16( \ _mm_mullo_epi16(U, _mm_set1_epi16(param->u_g_factor)), \ _mm_mullo_epi16(V, _mm_set1_epi16(param->v_g_factor))); \ b_tmp = _mm_mullo_epi16(U, _mm_set1_epi16(param->u_b_factor)); \ R1 = _mm_unpacklo_epi16(r_tmp, r_tmp); \ G1 = _mm_unpacklo_epi16(g_tmp, g_tmp); \ B1 = _mm_unpacklo_epi16(b_tmp, b_tmp); \ R2 = _mm_unpackhi_epi16(r_tmp, r_tmp); \ G2 = _mm_unpackhi_epi16(g_tmp, g_tmp); \ B2 = _mm_unpackhi_epi16(b_tmp, b_tmp); \ #define ADD_Y2RGB_16(Y1,Y2,R1,G1,B1,R2,G2,B2) \ Y1 = _mm_mullo_epi16(_mm_sub_epi16(Y1, _mm_set1_epi16(param->y_shift)), _mm_set1_epi16(param->y_factor)); \ Y2 = _mm_mullo_epi16(_mm_sub_epi16(Y2, _mm_set1_epi16(param->y_shift)), _mm_set1_epi16(param->y_factor)); \ \ R1 = _mm_srai_epi16(_mm_add_epi16(R1, Y1), PRECISION); \ G1 = _mm_srai_epi16(_mm_add_epi16(G1, Y1), PRECISION); \ B1 = _mm_srai_epi16(_mm_add_epi16(B1, Y1), PRECISION); \ R2 = _mm_srai_epi16(_mm_add_epi16(R2, Y2), PRECISION); \ G2 = _mm_srai_epi16(_mm_add_epi16(G2, Y2), PRECISION); \ B2 = _mm_srai_epi16(_mm_add_epi16(B2, Y2), PRECISION); \ #define PACK_RGB565_32(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4) \ { \ __m128i red_mask, tmp1, tmp2, tmp3, tmp4; \ \ red_mask = _mm_set1_epi16((short)0xF800); \ RGB1 = _mm_and_si128(_mm_unpacklo_epi8(_mm_setzero_si128(), R1), red_mask); \ RGB2 = _mm_and_si128(_mm_unpackhi_epi8(_mm_setzero_si128(), R1), red_mask); \ RGB3 = _mm_and_si128(_mm_unpacklo_epi8(_mm_setzero_si128(), R2), red_mask); \ RGB4 = _mm_and_si128(_mm_unpackhi_epi8(_mm_setzero_si128(), R2), red_mask); \ tmp1 = _mm_slli_epi16(_mm_srli_epi16(_mm_unpacklo_epi8(G1, _mm_setzero_si128()), 2), 5); \ tmp2 = _mm_slli_epi16(_mm_srli_epi16(_mm_unpackhi_epi8(G1, _mm_setzero_si128()), 2), 5); \ tmp3 = _mm_slli_epi16(_mm_srli_epi16(_mm_unpacklo_epi8(G2, _mm_setzero_si128()), 2), 5); \ tmp4 = _mm_slli_epi16(_mm_srli_epi16(_mm_unpackhi_epi8(G2, _mm_setzero_si128()), 2), 5); \ RGB1 = _mm_or_si128(RGB1, tmp1); \ RGB2 = _mm_or_si128(RGB2, tmp2); \ RGB3 = _mm_or_si128(RGB3, tmp3); \ RGB4 = _mm_or_si128(RGB4, tmp4); \ tmp1 = _mm_srli_epi16(_mm_unpacklo_epi8(B1, _mm_setzero_si128()), 3); \ tmp2 = _mm_srli_epi16(_mm_unpackhi_epi8(B1, _mm_setzero_si128()), 3); \ tmp3 = _mm_srli_epi16(_mm_unpacklo_epi8(B2, _mm_setzero_si128()), 3); \ tmp4 = _mm_srli_epi16(_mm_unpackhi_epi8(B2, _mm_setzero_si128()), 3); \ RGB1 = _mm_or_si128(RGB1, tmp1); \ RGB2 = _mm_or_si128(RGB2, tmp2); \ RGB3 = _mm_or_si128(RGB3, tmp3); \ RGB4 = _mm_or_si128(RGB4, tmp4); \ } #define PACK_RGB24_32_STEP1(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6) \ RGB1 = _mm_packus_epi16(_mm_and_si128(R1,_mm_set1_epi16(0xFF)), _mm_and_si128(R2,_mm_set1_epi16(0xFF))); \ RGB2 = _mm_packus_epi16(_mm_and_si128(G1,_mm_set1_epi16(0xFF)), _mm_and_si128(G2,_mm_set1_epi16(0xFF))); \ RGB3 = _mm_packus_epi16(_mm_and_si128(B1,_mm_set1_epi16(0xFF)), _mm_and_si128(B2,_mm_set1_epi16(0xFF))); \ RGB4 = _mm_packus_epi16(_mm_srli_epi16(R1,8), _mm_srli_epi16(R2,8)); \ RGB5 = _mm_packus_epi16(_mm_srli_epi16(G1,8), _mm_srli_epi16(G2,8)); \ RGB6 = _mm_packus_epi16(_mm_srli_epi16(B1,8), _mm_srli_epi16(B2,8)); \ #define PACK_RGB24_32_STEP2(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6) \ R1 = _mm_packus_epi16(_mm_and_si128(RGB1,_mm_set1_epi16(0xFF)), _mm_and_si128(RGB2,_mm_set1_epi16(0xFF))); \ R2 = _mm_packus_epi16(_mm_and_si128(RGB3,_mm_set1_epi16(0xFF)), _mm_and_si128(RGB4,_mm_set1_epi16(0xFF))); \ G1 = _mm_packus_epi16(_mm_and_si128(RGB5,_mm_set1_epi16(0xFF)), _mm_and_si128(RGB6,_mm_set1_epi16(0xFF))); \ G2 = _mm_packus_epi16(_mm_srli_epi16(RGB1,8), _mm_srli_epi16(RGB2,8)); \ B1 = _mm_packus_epi16(_mm_srli_epi16(RGB3,8), _mm_srli_epi16(RGB4,8)); \ B2 = _mm_packus_epi16(_mm_srli_epi16(RGB5,8), _mm_srli_epi16(RGB6,8)); \ #define PACK_RGB24_32(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6) \ PACK_RGB24_32_STEP1(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6) \ PACK_RGB24_32_STEP2(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6) \ PACK_RGB24_32_STEP1(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6) \ PACK_RGB24_32_STEP2(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6) \ PACK_RGB24_32_STEP1(R1, R2, G1, G2, B1, B2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6) \ #define PACK_RGBA_32(R1, R2, G1, G2, B1, B2, A1, A2, RGB1, RGB2, RGB3, RGB4, RGB5, RGB6, RGB7, RGB8) \ { \ __m128i lo_ab, hi_ab, lo_gr, hi_gr; \ \ lo_ab = _mm_unpacklo_epi8( A1, B1 ); \ hi_ab = _mm_unpackhi_epi8( A1, B1 ); \ lo_gr = _mm_unpacklo_epi8( G1, R1 ); \ hi_gr = _mm_unpackhi_epi8( G1, R1 ); \ RGB1 = _mm_unpacklo_epi16( lo_ab, lo_gr ); \ RGB2 = _mm_unpackhi_epi16( lo_ab, lo_gr ); \ RGB3 = _mm_unpacklo_epi16( hi_ab, hi_gr ); \ RGB4 = _mm_unpackhi_epi16( hi_ab, hi_gr ); \ \ lo_ab = _mm_unpacklo_epi8( A2, B2 ); \ hi_ab = _mm_unpackhi_epi8( A2, B2 ); \ lo_gr = _mm_unpacklo_epi8( G2, R2 ); \ hi_gr = _mm_unpackhi_epi8( G2, R2 ); \ RGB5 = _mm_unpacklo_epi16( lo_ab, lo_gr ); \ RGB6 = _mm_unpackhi_epi16( lo_ab, lo_gr ); \ RGB7 = _mm_unpacklo_epi16( hi_ab, hi_gr ); \ RGB8 = _mm_unpackhi_epi16( hi_ab, hi_gr ); \ } #if RGB_FORMAT == RGB_FORMAT_RGB565 #define PACK_PIXEL \ __m128i rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8; \ \ PACK_RGB565_32(r_8_11, r_8_12, g_8_11, g_8_12, b_8_11, b_8_12, rgb_1, rgb_2, rgb_3, rgb_4) \ \ PACK_RGB565_32(r_8_21, r_8_22, g_8_21, g_8_22, b_8_21, b_8_22, rgb_5, rgb_6, rgb_7, rgb_8) \ #elif RGB_FORMAT == RGB_FORMAT_RGB24 #define PACK_PIXEL \ __m128i rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6; \ __m128i rgb_7, rgb_8, rgb_9, rgb_10, rgb_11, rgb_12; \ \ PACK_RGB24_32(r_8_11, r_8_12, g_8_11, g_8_12, b_8_11, b_8_12, rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6) \ \ PACK_RGB24_32(r_8_21, r_8_22, g_8_21, g_8_22, b_8_21, b_8_22, rgb_7, rgb_8, rgb_9, rgb_10, rgb_11, rgb_12) \ #elif RGB_FORMAT == RGB_FORMAT_RGBA #define PACK_PIXEL \ __m128i rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8; \ __m128i rgb_9, rgb_10, rgb_11, rgb_12, rgb_13, rgb_14, rgb_15, rgb_16; \ __m128i a = _mm_set1_epi8((char)0xFF); \ \ PACK_RGBA_32(r_8_11, r_8_12, g_8_11, g_8_12, b_8_11, b_8_12, a, a, rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8) \ \ PACK_RGBA_32(r_8_21, r_8_22, g_8_21, g_8_22, b_8_21, b_8_22, a, a, rgb_9, rgb_10, rgb_11, rgb_12, rgb_13, rgb_14, rgb_15, rgb_16) \ #elif RGB_FORMAT == RGB_FORMAT_BGRA #define PACK_PIXEL \ __m128i rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8; \ __m128i rgb_9, rgb_10, rgb_11, rgb_12, rgb_13, rgb_14, rgb_15, rgb_16; \ __m128i a = _mm_set1_epi8((char)0xFF); \ \ PACK_RGBA_32(b_8_11, b_8_12, g_8_11, g_8_12, r_8_11, r_8_12, a, a, rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8) \ \ PACK_RGBA_32(b_8_21, b_8_22, g_8_21, g_8_22, r_8_21, r_8_22, a, a, rgb_9, rgb_10, rgb_11, rgb_12, rgb_13, rgb_14, rgb_15, rgb_16) \ #elif RGB_FORMAT == RGB_FORMAT_ARGB #define PACK_PIXEL \ __m128i rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8; \ __m128i rgb_9, rgb_10, rgb_11, rgb_12, rgb_13, rgb_14, rgb_15, rgb_16; \ __m128i a = _mm_set1_epi8((char)0xFF); \ \ PACK_RGBA_32(a, a, r_8_11, r_8_12, g_8_11, g_8_12, b_8_11, b_8_12, rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8) \ \ PACK_RGBA_32(a, a, r_8_21, r_8_22, g_8_21, g_8_22, b_8_21, b_8_22, rgb_9, rgb_10, rgb_11, rgb_12, rgb_13, rgb_14, rgb_15, rgb_16) \ #elif RGB_FORMAT == RGB_FORMAT_ABGR #define PACK_PIXEL \ __m128i rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8; \ __m128i rgb_9, rgb_10, rgb_11, rgb_12, rgb_13, rgb_14, rgb_15, rgb_16; \ __m128i a = _mm_set1_epi8((char)0xFF); \ \ PACK_RGBA_32(a, a, b_8_11, b_8_12, g_8_11, g_8_12, r_8_11, r_8_12, rgb_1, rgb_2, rgb_3, rgb_4, rgb_5, rgb_6, rgb_7, rgb_8) \ \ PACK_RGBA_32(a, a, b_8_21, b_8_22, g_8_21, g_8_22, r_8_21, r_8_22, rgb_9, rgb_10, rgb_11, rgb_12, rgb_13, rgb_14, rgb_15, rgb_16) \ #else #error PACK_PIXEL unimplemented #endif #if RGB_FORMAT == RGB_FORMAT_RGB565 #define SAVE_LINE1 \ SAVE_SI128((__m128i*)(rgb_ptr1), rgb_1); \ SAVE_SI128((__m128i*)(rgb_ptr1+16), rgb_2); \ SAVE_SI128((__m128i*)(rgb_ptr1+32), rgb_3); \ SAVE_SI128((__m128i*)(rgb_ptr1+48), rgb_4); \ #define SAVE_LINE2 \ SAVE_SI128((__m128i*)(rgb_ptr2), rgb_5); \ SAVE_SI128((__m128i*)(rgb_ptr2+16), rgb_6); \ SAVE_SI128((__m128i*)(rgb_ptr2+32), rgb_7); \ SAVE_SI128((__m128i*)(rgb_ptr2+48), rgb_8); \ #elif RGB_FORMAT == RGB_FORMAT_RGB24 #define SAVE_LINE1 \ SAVE_SI128((__m128i*)(rgb_ptr1), rgb_1); \ SAVE_SI128((__m128i*)(rgb_ptr1+16), rgb_2); \ SAVE_SI128((__m128i*)(rgb_ptr1+32), rgb_3); \ SAVE_SI128((__m128i*)(rgb_ptr1+48), rgb_4); \ SAVE_SI128((__m128i*)(rgb_ptr1+64), rgb_5); \ SAVE_SI128((__m128i*)(rgb_ptr1+80), rgb_6); \ #define SAVE_LINE2 \ SAVE_SI128((__m128i*)(rgb_ptr2), rgb_7); \ SAVE_SI128((__m128i*)(rgb_ptr2+16), rgb_8); \ SAVE_SI128((__m128i*)(rgb_ptr2+32), rgb_9); \ SAVE_SI128((__m128i*)(rgb_ptr2+48), rgb_10); \ SAVE_SI128((__m128i*)(rgb_ptr2+64), rgb_11); \ SAVE_SI128((__m128i*)(rgb_ptr2+80), rgb_12); \ #elif RGB_FORMAT == RGB_FORMAT_RGBA || RGB_FORMAT == RGB_FORMAT_BGRA || \ RGB_FORMAT == RGB_FORMAT_ARGB || RGB_FORMAT == RGB_FORMAT_ABGR #define SAVE_LINE1 \ SAVE_SI128((__m128i*)(rgb_ptr1), rgb_1); \ SAVE_SI128((__m128i*)(rgb_ptr1+16), rgb_2); \ SAVE_SI128((__m128i*)(rgb_ptr1+32), rgb_3); \ SAVE_SI128((__m128i*)(rgb_ptr1+48), rgb_4); \ SAVE_SI128((__m128i*)(rgb_ptr1+64), rgb_5); \ SAVE_SI128((__m128i*)(rgb_ptr1+80), rgb_6); \ SAVE_SI128((__m128i*)(rgb_ptr1+96), rgb_7); \ SAVE_SI128((__m128i*)(rgb_ptr1+112), rgb_8); \ #define SAVE_LINE2 \ SAVE_SI128((__m128i*)(rgb_ptr2), rgb_9); \ SAVE_SI128((__m128i*)(rgb_ptr2+16), rgb_10); \ SAVE_SI128((__m128i*)(rgb_ptr2+32), rgb_11); \ SAVE_SI128((__m128i*)(rgb_ptr2+48), rgb_12); \ SAVE_SI128((__m128i*)(rgb_ptr2+64), rgb_13); \ SAVE_SI128((__m128i*)(rgb_ptr2+80), rgb_14); \ SAVE_SI128((__m128i*)(rgb_ptr2+96), rgb_15); \ SAVE_SI128((__m128i*)(rgb_ptr2+112), rgb_16); \ #else #error SAVE_LINE unimplemented #endif #if YUV_FORMAT == YUV_FORMAT_420 #define READ_Y(y_ptr) \ y = LOAD_SI128((const __m128i*)(y_ptr)); \ #define READ_UV \ u = LOAD_SI128((const __m128i*)(u_ptr)); \ v = LOAD_SI128((const __m128i*)(v_ptr)); \ #elif YUV_FORMAT == YUV_FORMAT_422 #define READ_Y(y_ptr) \ { \ __m128i y1, y2; \ y1 = _mm_srli_epi16(_mm_slli_epi16(LOAD_SI128((const __m128i*)(y_ptr)), 8), 8); \ y2 = _mm_srli_epi16(_mm_slli_epi16(LOAD_SI128((const __m128i*)(y_ptr+16)), 8), 8); \ y = _mm_packus_epi16(y1, y2); \ } #define READ_UV \ { \ __m128i u1, u2, u3, u4, v1, v2, v3, v4; \ u1 = _mm_srli_epi32(_mm_slli_epi32(LOAD_SI128((const __m128i*)(u_ptr)), 24), 24); \ u2 = _mm_srli_epi32(_mm_slli_epi32(LOAD_SI128((const __m128i*)(u_ptr+16)), 24), 24); \ u3 = _mm_srli_epi32(_mm_slli_epi32(LOAD_SI128((const __m128i*)(u_ptr+32)), 24), 24); \ u4 = _mm_srli_epi32(_mm_slli_epi32(LOAD_SI128((const __m128i*)(u_ptr+48)), 24), 24); \ u = _mm_packus_epi16(_mm_packs_epi32(u1, u2), _mm_packs_epi32(u3, u4)); \ v1 = _mm_srli_epi32(_mm_slli_epi32(LOAD_SI128((const __m128i*)(v_ptr)), 24), 24); \ v2 = _mm_srli_epi32(_mm_slli_epi32(LOAD_SI128((const __m128i*)(v_ptr+16)), 24), 24); \ v3 = _mm_srli_epi32(_mm_slli_epi32(LOAD_SI128((const __m128i*)(v_ptr+32)), 24), 24); \ v4 = _mm_srli_epi32(_mm_slli_epi32(LOAD_SI128((const __m128i*)(v_ptr+48)), 24), 24); \ v = _mm_packus_epi16(_mm_packs_epi32(v1, v2), _mm_packs_epi32(v3, v4)); \ } #elif YUV_FORMAT == YUV_FORMAT_NV12 #define READ_Y(y_ptr) \ y = LOAD_SI128((const __m128i*)(y_ptr)); \ #define READ_UV \ { \ __m128i u1, u2, v1, v2; \ u1 = _mm_srli_epi16(_mm_slli_epi16(LOAD_SI128((const __m128i*)(u_ptr)), 8), 8); \ u2 = _mm_srli_epi16(_mm_slli_epi16(LOAD_SI128((const __m128i*)(u_ptr+16)), 8), 8); \ u = _mm_packus_epi16(u1, u2); \ v1 = _mm_srli_epi16(_mm_slli_epi16(LOAD_SI128((const __m128i*)(v_ptr)), 8), 8); \ v2 = _mm_srli_epi16(_mm_slli_epi16(LOAD_SI128((const __m128i*)(v_ptr+16)), 8), 8); \ v = _mm_packus_epi16(v1, v2); \ } #else #error READ_UV unimplemented #endif #define YUV2RGB_32 \ __m128i r_tmp, g_tmp, b_tmp; \ __m128i r_16_1, g_16_1, b_16_1, r_16_2, g_16_2, b_16_2; \ __m128i r_uv_16_1, g_uv_16_1, b_uv_16_1, r_uv_16_2, g_uv_16_2, b_uv_16_2; \ __m128i y_16_1, y_16_2; \ __m128i y, u, v, u_16, v_16; \ __m128i r_8_11, g_8_11, b_8_11, r_8_21, g_8_21, b_8_21; \ __m128i r_8_12, g_8_12, b_8_12, r_8_22, g_8_22, b_8_22; \ \ READ_UV \ \ /* process first 16 pixels of first line */\ u_16 = _mm_unpacklo_epi8(u, _mm_setzero_si128()); \ v_16 = _mm_unpacklo_epi8(v, _mm_setzero_si128()); \ u_16 = _mm_add_epi16(u_16, _mm_set1_epi16(-128)); \ v_16 = _mm_add_epi16(v_16, _mm_set1_epi16(-128)); \ \ UV2RGB_16(u_16, v_16, r_16_1, g_16_1, b_16_1, r_16_2, g_16_2, b_16_2) \ r_uv_16_1=r_16_1; g_uv_16_1=g_16_1; b_uv_16_1=b_16_1; \ r_uv_16_2=r_16_2; g_uv_16_2=g_16_2; b_uv_16_2=b_16_2; \ \ READ_Y(y_ptr1) \ y_16_1 = _mm_unpacklo_epi8(y, _mm_setzero_si128()); \ y_16_2 = _mm_unpackhi_epi8(y, _mm_setzero_si128()); \ \ ADD_Y2RGB_16(y_16_1, y_16_2, r_16_1, g_16_1, b_16_1, r_16_2, g_16_2, b_16_2) \ \ r_8_11 = _mm_packus_epi16(r_16_1, r_16_2); \ g_8_11 = _mm_packus_epi16(g_16_1, g_16_2); \ b_8_11 = _mm_packus_epi16(b_16_1, b_16_2); \ \ /* process first 16 pixels of second line */\ r_16_1=r_uv_16_1; g_16_1=g_uv_16_1; b_16_1=b_uv_16_1; \ r_16_2=r_uv_16_2; g_16_2=g_uv_16_2; b_16_2=b_uv_16_2; \ \ READ_Y(y_ptr2) \ y_16_1 = _mm_unpacklo_epi8(y, _mm_setzero_si128()); \ y_16_2 = _mm_unpackhi_epi8(y, _mm_setzero_si128()); \ \ ADD_Y2RGB_16(y_16_1, y_16_2, r_16_1, g_16_1, b_16_1, r_16_2, g_16_2, b_16_2) \ \ r_8_21 = _mm_packus_epi16(r_16_1, r_16_2); \ g_8_21 = _mm_packus_epi16(g_16_1, g_16_2); \ b_8_21 = _mm_packus_epi16(b_16_1, b_16_2); \ \ /* process last 16 pixels of first line */\ u_16 = _mm_unpackhi_epi8(u, _mm_setzero_si128()); \ v_16 = _mm_unpackhi_epi8(v, _mm_setzero_si128()); \ u_16 = _mm_add_epi16(u_16, _mm_set1_epi16(-128)); \ v_16 = _mm_add_epi16(v_16, _mm_set1_epi16(-128)); \ \ UV2RGB_16(u_16, v_16, r_16_1, g_16_1, b_16_1, r_16_2, g_16_2, b_16_2) \ r_uv_16_1=r_16_1; g_uv_16_1=g_16_1; b_uv_16_1=b_16_1; \ r_uv_16_2=r_16_2; g_uv_16_2=g_16_2; b_uv_16_2=b_16_2; \ \ READ_Y(y_ptr1+16*y_pixel_stride) \ y_16_1 = _mm_unpacklo_epi8(y, _mm_setzero_si128()); \ y_16_2 = _mm_unpackhi_epi8(y, _mm_setzero_si128()); \ \ ADD_Y2RGB_16(y_16_1, y_16_2, r_16_1, g_16_1, b_16_1, r_16_2, g_16_2, b_16_2) \ \ r_8_12 = _mm_packus_epi16(r_16_1, r_16_2); \ g_8_12 = _mm_packus_epi16(g_16_1, g_16_2); \ b_8_12 = _mm_packus_epi16(b_16_1, b_16_2); \ \ /* process last 16 pixels of second line */\ r_16_1=r_uv_16_1; g_16_1=g_uv_16_1; b_16_1=b_uv_16_1; \ r_16_2=r_uv_16_2; g_16_2=g_uv_16_2; b_16_2=b_uv_16_2; \ \ READ_Y(y_ptr2+16*y_pixel_stride) \ y_16_1 = _mm_unpacklo_epi8(y, _mm_setzero_si128()); \ y_16_2 = _mm_unpackhi_epi8(y, _mm_setzero_si128()); \ \ ADD_Y2RGB_16(y_16_1, y_16_2, r_16_1, g_16_1, b_16_1, r_16_2, g_16_2, b_16_2) \ \ r_8_22 = _mm_packus_epi16(r_16_1, r_16_2); \ g_8_22 = _mm_packus_epi16(g_16_1, g_16_2); \ b_8_22 = _mm_packus_epi16(b_16_1, b_16_2); \ \ void SSE_FUNCTION_NAME(uint32_t width, uint32_t height, const uint8_t *Y, const uint8_t *U, const uint8_t *V, uint32_t Y_stride, uint32_t UV_stride, uint8_t *RGB, uint32_t RGB_stride, YCbCrType yuv_type) { const YUV2RGBParam *const param = &(YUV2RGB[yuv_type]); #if YUV_FORMAT == YUV_FORMAT_420 const int y_pixel_stride = 1; const int uv_pixel_stride = 1; const int uv_x_sample_interval = 2; const int uv_y_sample_interval = 2; #elif YUV_FORMAT == YUV_FORMAT_422 const int y_pixel_stride = 2; const int uv_pixel_stride = 4; const int uv_x_sample_interval = 2; const int uv_y_sample_interval = 1; #elif YUV_FORMAT == YUV_FORMAT_NV12 const int y_pixel_stride = 1; const int uv_pixel_stride = 2; const int uv_x_sample_interval = 2; const int uv_y_sample_interval = 2; #endif #if RGB_FORMAT == RGB_FORMAT_RGB565 const int rgb_pixel_stride = 2; #elif RGB_FORMAT == RGB_FORMAT_RGB24 const int rgb_pixel_stride = 3; #elif RGB_FORMAT == RGB_FORMAT_RGBA || RGB_FORMAT == RGB_FORMAT_BGRA || \ RGB_FORMAT == RGB_FORMAT_ARGB || RGB_FORMAT == RGB_FORMAT_ABGR const int rgb_pixel_stride = 4; #else #error Unknown RGB pixel size #endif if (width >= 32) { uint32_t xpos, ypos; for(ypos=0; ypos<(height-(uv_y_sample_interval-1)); ypos+=uv_y_sample_interval) { const uint8_t *y_ptr1=Y+ypos*Y_stride, *y_ptr2=Y+(ypos+1)*Y_stride, *u_ptr=U+(ypos/uv_y_sample_interval)*UV_stride, *v_ptr=V+(ypos/uv_y_sample_interval)*UV_stride; uint8_t *rgb_ptr1=RGB+ypos*RGB_stride, *rgb_ptr2=RGB+(ypos+1)*RGB_stride; for(xpos=0; xpos<(width-31); xpos+=32) { YUV2RGB_32 { PACK_PIXEL SAVE_LINE1 if (uv_y_sample_interval > 1) { SAVE_LINE2 } } y_ptr1+=32*y_pixel_stride; y_ptr2+=32*y_pixel_stride; u_ptr+=32*uv_pixel_stride/uv_x_sample_interval; v_ptr+=32*uv_pixel_stride/uv_x_sample_interval; rgb_ptr1+=32*rgb_pixel_stride; rgb_ptr2+=32*rgb_pixel_stride; } } /* Catch the last line, if needed */ if (uv_y_sample_interval == 2 && ypos == (height-1)) { const uint8_t *y_ptr=Y+ypos*Y_stride, *u_ptr=U+(ypos/uv_y_sample_interval)*UV_stride, *v_ptr=V+(ypos/uv_y_sample_interval)*UV_stride; uint8_t *rgb_ptr=RGB+ypos*RGB_stride; STD_FUNCTION_NAME(width, 1, y_ptr, u_ptr, v_ptr, Y_stride, UV_stride, rgb_ptr, RGB_stride, yuv_type); } } /* Catch the right column, if needed */ { int converted = (width & ~31); if (converted != width) { const uint8_t *y_ptr=Y+converted*y_pixel_stride, *u_ptr=U+converted*uv_pixel_stride/uv_x_sample_interval, *v_ptr=V+converted*uv_pixel_stride/uv_x_sample_interval; uint8_t *rgb_ptr=RGB+converted*rgb_pixel_stride; STD_FUNCTION_NAME(width-converted, height, y_ptr, u_ptr, v_ptr, Y_stride, UV_stride, rgb_ptr, RGB_stride, yuv_type); } } } #undef SSE_FUNCTION_NAME #undef STD_FUNCTION_NAME #undef YUV_FORMAT #undef RGB_FORMAT #undef SSE_ALIGNED #undef LOAD_SI128 #undef SAVE_SI128 #undef UV2RGB_16 #undef ADD_Y2RGB_16 #undef PACK_RGB24_32_STEP1 #undef PACK_RGB24_32_STEP2 #undef PACK_RGB24_32 #undef PACK_RGBA_32 #undef PACK_PIXEL #undef SAVE_LINE1 #undef SAVE_LINE2 #undef READ_Y #undef READ_UV #undef YUV2RGB_32

{ "language": "Assembly" }

#include "z_boss_ganon2.h" #define FLAGS 0x00000035 #define THIS ((BossGanon2*)thisx) void BossGanon2_Init(Actor* thisx, GlobalContext* globalCtx); void BossGanon2_Destroy(Actor* thisx, GlobalContext* globalCtx); void BossGanon2_Update(Actor* thisx, GlobalContext* globalCtx); void BossGanon2_Draw(Actor* thisx, GlobalContext* globalCtx); /* const ActorInit Boss_Ganon2_InitVars = { ACTOR_BOSS_GANON2, ACTORTYPE_BOSS, FLAGS, OBJECT_GANON2, sizeof(BossGanon2), (ActorFunc)BossGanon2_Init, (ActorFunc)BossGanon2_Destroy, (ActorFunc)BossGanon2_Update, (ActorFunc)BossGanon2_Draw, }; */ #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FCF40.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FCF5C.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FD080.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FD108.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FD210.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FD27C.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/BossGanon2_Init.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/BossGanon2_Destroy.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FD4D4.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FD5C4.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FD5F4.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FF898.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFA24.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFAC8.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFBBC.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFC84.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFCFC.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFDB0.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFEBC.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFF90.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_808FFFE0.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_809000A0.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80900104.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80900210.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_8090026C.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_809002CC.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80900344.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80900580.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80900650.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80900818.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80900890.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80901020.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_8090109C.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_8090120C.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80902348.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80902524.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/BossGanon2_Update.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_809034E4.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80903F38.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80904108.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80904340.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_8090464C.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80904818.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_809049A0.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80904D88.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80904FC8.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_8090523C.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80905508.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80905674.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/BossGanon2_Draw.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80905DA8.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_809060E8.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80906538.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_809069F8.s") #pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_Boss_Ganon2/func_80906AB0.s")

{ "language": "Assembly" }

# Copyright 2013 the V8 project authors. All rights reserved. # Copyright (C) 2005, 2006, 2007, 2008, 2009 Apple Inc. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY APPLE INC. AND ITS CONTRIBUTORS ``AS IS'' AND ANY # EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE # DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR ITS CONTRIBUTORS BE LIABLE FOR ANY # DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON # ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. This test checks that the Function constructor places a newline after the opening brace, for compatibility reasons. It passes if there are no syntax error exceptions. On success, you will see a series of "PASS" messages, followed by "TEST COMPLETE". PASS successfullyParsed is true TEST COMPLETE

{ "language": "Assembly" }

; RUN: opt < %s -gvn | llvm-dis %struct.TypHeader = type { i32, %struct.TypHeader**, [3 x i8], i8 } define %struct.TypHeader* @LtRec(%struct.TypHeader* %hdL, %struct.TypHeader* %hdR) { entry: br i1 false, label %bb556.preheader, label %bb534.preheader bb534.preheader: ; preds = %entry ret %struct.TypHeader* null bb556.preheader: ; preds = %entry %tmp56119 = getelementptr %struct.TypHeader* %hdR, i32 0, i32 0 ; <i32*> [#uses=1] %tmp56220 = load i32* %tmp56119 ; <i32> [#uses=0] br i1 false, label %bb.nph23, label %bb675.preheader bb.nph23: ; preds = %bb556.preheader ret %struct.TypHeader* null bb656: ; preds = %bb675.outer, %bb656 %tmp678 = load i32* %tmp677 ; <i32> [#uses=0] br i1 false, label %bb684, label %bb656 bb684: ; preds = %bb675.outer, %bb656 br i1 false, label %bb924.preheader, label %bb675.outer bb675.outer: ; preds = %bb675.preheader, %bb684 %tmp67812 = load i32* %tmp67711 ; <i32> [#uses=0] br i1 false, label %bb684, label %bb656 bb675.preheader: ; preds = %bb556.preheader %tmp67711 = getelementptr %struct.TypHeader* %hdR, i32 0, i32 0 ; <i32*> [#uses=1] %tmp677 = getelementptr %struct.TypHeader* %hdR, i32 0, i32 0 ; <i32*> [#uses=1] br label %bb675.outer bb924.preheader: ; preds = %bb684 ret %struct.TypHeader* null }

{ "language": "Assembly" }

[GLOBAL asm_powoff] asm_powoff: mov ax, 5301h xor bx, bx int 15h mov ax, 530Fh mov bx, 1 mov cx, 1 int 15h mov ax, 5307h mov bx, 1 mov cx, 3 int 15h

{ "language": "Assembly" }

/***************************************************************************** * asm.S: arm utility macros ***************************************************************************** * Copyright (C) 2008-2016 x264 project * * Authors: Mans Rullgard <[email protected]> * David Conrad <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111, USA. * * This program is also available under a commercial proprietary license. * For more information, contact us at [email protected]. *****************************************************************************/ #include "config.h" .syntax unified #if HAVE_NEON .arch armv7-a #elif HAVE_ARMV6T2 .arch armv6t2 #elif HAVE_ARMV6 .arch armv6 #endif .fpu neon #ifdef PREFIX # define EXTERN_ASM _ #else # define EXTERN_ASM #endif #ifdef __ELF__ # define ELF #else # define ELF @ #endif #if HAVE_AS_FUNC # define FUNC #else # define FUNC @ #endif #if SYS_LINUX #define HAVE_SECTION_DATA_REL_RO 1 #else #define HAVE_SECTION_DATA_REL_RO 0 #endif .macro require8, val=1 ELF .eabi_attribute 24, \val .endm .macro preserve8, val=1 ELF .eabi_attribute 25, \val .endm .macro function name, export=1 .macro endfunc ELF .size \name, . - \name FUNC .endfunc .purgem endfunc .endm .align 2 .if \export == 1 .global EXTERN_ASM\name ELF .hidden EXTERN_ASM\name ELF .type EXTERN_ASM\name, %function FUNC .func EXTERN_ASM\name EXTERN_ASM\name: .else ELF .hidden \name ELF .type \name, %function FUNC .func \name \name: .endif .endm .macro const name, align=2, relocate=0 .macro endconst ELF .size \name, . - \name .purgem endconst .endm .if HAVE_SECTION_DATA_REL_RO && \relocate .section .data.rel.ro .else .section .rodata .endif .align \align \name: .endm .macro movrel rd, val #if defined(PIC) ldr \rd, 1f b 2f 1: @ FIXME: thumb .word \val - (2f + 8) 2: add \rd, \rd, pc #elif HAVE_ARMV6T2 movw \rd, #:lower16:\val movt \rd, #:upper16:\val #else ldr \rd, =\val #endif .endm .macro movrelx rd, val, got #if defined(PIC) && defined(__ELF__) ldr \got, 2f ldr \rd, 1f b 3f 1: @ FIXME: thumb .word \val(GOT) 2: .word _GLOBAL_OFFSET_TABLE_ - (3f + 8) 3: add \got, \got, pc ldr \rd, [\got, \rd] #elif defined(PIC) && defined(__APPLE__) ldr \rd, 1f b 2f 1: @ FIXME: thumb .word 3f - (2f + 8) 2: ldr \rd, [pc, \rd] .non_lazy_symbol_pointer 3: .indirect_symbol \val .word 0 .text #else movrel \rd, \val #endif .endm .macro movconst rd, val #if HAVE_ARMV6T2 movw \rd, #:lower16:\val .if \val >> 16 movt \rd, #:upper16:\val .endif #else ldr \rd, =\val #endif .endm #define GLUE(a, b) a ## b #define JOIN(a, b) GLUE(a, b) #define X(s) JOIN(EXTERN_ASM, s) #define FENC_STRIDE 16 #define FDEC_STRIDE 32 .macro HORIZ_ADD dest, a, b .ifnb \b vadd.u16 \a, \a, \b .endif vpaddl.u16 \a, \a vpaddl.u32 \dest, \a .endm .macro SUMSUB_AB sum, diff, a, b vadd.s16 \sum, \a, \b vsub.s16 \diff, \a, \b .endm .macro SUMSUB_ABCD s1, d1, s2, d2, a, b, c, d SUMSUB_AB \s1, \d1, \a, \b SUMSUB_AB \s2, \d2, \c, \d .endm .macro ABS2 a b vabs.s16 \a, \a vabs.s16 \b, \b .endm // dist = distance in elements (0 for vertical pass, 1/2 for horizontal passes) // op = sumsub/amax (sum and diff / maximum of absolutes) // d1/2 = destination registers // s1/2 = source registers .macro HADAMARD dist, op, d1, d2, s1, s2 .if \dist == 1 vtrn.16 \s1, \s2 .else vtrn.32 \s1, \s2 .endif .ifc \op, sumsub SUMSUB_AB \d1, \d2, \s1, \s2 .else vabs.s16 \s1, \s1 vabs.s16 \s2, \s2 vmax.s16 \d1, \s1, \s2 .endif .endm .macro TRANSPOSE8x8 r0 r1 r2 r3 r4 r5 r6 r7 vtrn.32 \r0, \r4 vtrn.32 \r1, \r5 vtrn.32 \r2, \r6 vtrn.32 \r3, \r7 vtrn.16 \r0, \r2 vtrn.16 \r1, \r3 vtrn.16 \r4, \r6 vtrn.16 \r5, \r7 vtrn.8 \r0, \r1 vtrn.8 \r2, \r3 vtrn.8 \r4, \r5 vtrn.8 \r6, \r7 .endm .macro TRANSPOSE4x4 r0 r1 r2 r3 vtrn.16 \r0, \r2 vtrn.16 \r1, \r3 vtrn.8 \r0, \r1 vtrn.8 \r2, \r3 .endm .macro TRANSPOSE4x4_16 d0 d1 d2 d3 vtrn.32 \d0, \d2 vtrn.32 \d1, \d3 vtrn.16 \d0, \d1 vtrn.16 \d2, \d3 .endm

{ "language": "Assembly" }

#ifndef CAPSTONE_X86_H #define CAPSTONE_X86_H /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh <[email protected]>, 2013-2015 */ #ifdef __cplusplus extern "C" { #endif #include "platform.h" // Calculate relative address for X86-64, given cs_insn structure #define X86_REL_ADDR(insn) (insn.address + insn.size + insn.detail->x86.disp) //> X86 registers typedef enum x86_reg { X86_REG_INVALID = 0, X86_REG_AH, X86_REG_AL, X86_REG_AX, X86_REG_BH, X86_REG_BL, X86_REG_BP, X86_REG_BPL, X86_REG_BX, X86_REG_CH, X86_REG_CL, X86_REG_CS, X86_REG_CX, X86_REG_DH, X86_REG_DI, X86_REG_DIL, X86_REG_DL, X86_REG_DS, X86_REG_DX, X86_REG_EAX, X86_REG_EBP, X86_REG_EBX, X86_REG_ECX, X86_REG_EDI, X86_REG_EDX, X86_REG_EFLAGS, X86_REG_EIP, X86_REG_EIZ, X86_REG_ES, X86_REG_ESI, X86_REG_ESP, X86_REG_FPSW, X86_REG_FS, X86_REG_GS, X86_REG_IP, X86_REG_RAX, X86_REG_RBP, X86_REG_RBX, X86_REG_RCX, X86_REG_RDI, X86_REG_RDX, X86_REG_RIP, X86_REG_RIZ, X86_REG_RSI, X86_REG_RSP, X86_REG_SI, X86_REG_SIL, X86_REG_SP, X86_REG_SPL, X86_REG_SS, X86_REG_CR0, X86_REG_CR1, X86_REG_CR2, X86_REG_CR3, X86_REG_CR4, X86_REG_CR5, X86_REG_CR6, X86_REG_CR7, X86_REG_CR8, X86_REG_CR9, X86_REG_CR10, X86_REG_CR11, X86_REG_CR12, X86_REG_CR13, X86_REG_CR14, X86_REG_CR15, X86_REG_DR0, X86_REG_DR1, X86_REG_DR2, X86_REG_DR3, X86_REG_DR4, X86_REG_DR5, X86_REG_DR6, X86_REG_DR7, X86_REG_DR8, X86_REG_DR9, X86_REG_DR10, X86_REG_DR11, X86_REG_DR12, X86_REG_DR13, X86_REG_DR14, X86_REG_DR15, X86_REG_FP0, X86_REG_FP1, X86_REG_FP2, X86_REG_FP3, X86_REG_FP4, X86_REG_FP5, X86_REG_FP6, X86_REG_FP7, X86_REG_K0, X86_REG_K1, X86_REG_K2, X86_REG_K3, X86_REG_K4, X86_REG_K5, X86_REG_K6, X86_REG_K7, X86_REG_MM0, X86_REG_MM1, X86_REG_MM2, X86_REG_MM3, X86_REG_MM4, X86_REG_MM5, X86_REG_MM6, X86_REG_MM7, X86_REG_R8, X86_REG_R9, X86_REG_R10, X86_REG_R11, X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15, X86_REG_ST0, X86_REG_ST1, X86_REG_ST2, X86_REG_ST3, X86_REG_ST4, X86_REG_ST5, X86_REG_ST6, X86_REG_ST7, X86_REG_XMM0, X86_REG_XMM1, X86_REG_XMM2, X86_REG_XMM3, X86_REG_XMM4, X86_REG_XMM5, X86_REG_XMM6, X86_REG_XMM7, X86_REG_XMM8, X86_REG_XMM9, X86_REG_XMM10, X86_REG_XMM11, X86_REG_XMM12, X86_REG_XMM13, X86_REG_XMM14, X86_REG_XMM15, X86_REG_XMM16, X86_REG_XMM17, X86_REG_XMM18, X86_REG_XMM19, X86_REG_XMM20, X86_REG_XMM21, X86_REG_XMM22, X86_REG_XMM23, X86_REG_XMM24, X86_REG_XMM25, X86_REG_XMM26, X86_REG_XMM27, X86_REG_XMM28, X86_REG_XMM29, X86_REG_XMM30, X86_REG_XMM31, X86_REG_YMM0, X86_REG_YMM1, X86_REG_YMM2, X86_REG_YMM3, X86_REG_YMM4, X86_REG_YMM5, X86_REG_YMM6, X86_REG_YMM7, X86_REG_YMM8, X86_REG_YMM9, X86_REG_YMM10, X86_REG_YMM11, X86_REG_YMM12, X86_REG_YMM13, X86_REG_YMM14, X86_REG_YMM15, X86_REG_YMM16, X86_REG_YMM17, X86_REG_YMM18, X86_REG_YMM19, X86_REG_YMM20, X86_REG_YMM21, X86_REG_YMM22, X86_REG_YMM23, X86_REG_YMM24, X86_REG_YMM25, X86_REG_YMM26, X86_REG_YMM27, X86_REG_YMM28, X86_REG_YMM29, X86_REG_YMM30, X86_REG_YMM31, X86_REG_ZMM0, X86_REG_ZMM1, X86_REG_ZMM2, X86_REG_ZMM3, X86_REG_ZMM4, X86_REG_ZMM5, X86_REG_ZMM6, X86_REG_ZMM7, X86_REG_ZMM8, X86_REG_ZMM9, X86_REG_ZMM10, X86_REG_ZMM11, X86_REG_ZMM12, X86_REG_ZMM13, X86_REG_ZMM14, X86_REG_ZMM15, X86_REG_ZMM16, X86_REG_ZMM17, X86_REG_ZMM18, X86_REG_ZMM19, X86_REG_ZMM20, X86_REG_ZMM21, X86_REG_ZMM22, X86_REG_ZMM23, X86_REG_ZMM24, X86_REG_ZMM25, X86_REG_ZMM26, X86_REG_ZMM27, X86_REG_ZMM28, X86_REG_ZMM29, X86_REG_ZMM30, X86_REG_ZMM31, X86_REG_R8B, X86_REG_R9B, X86_REG_R10B, X86_REG_R11B, X86_REG_R12B, X86_REG_R13B, X86_REG_R14B, X86_REG_R15B, X86_REG_R8D, X86_REG_R9D, X86_REG_R10D, X86_REG_R11D, X86_REG_R12D, X86_REG_R13D, X86_REG_R14D, X86_REG_R15D, X86_REG_R8W, X86_REG_R9W, X86_REG_R10W, X86_REG_R11W, X86_REG_R12W, X86_REG_R13W, X86_REG_R14W, X86_REG_R15W, X86_REG_ENDING // <-- mark the end of the list of registers } x86_reg; //> Sub-flags of EFLAGS #define X86_EFLAGS_MODIFY_AF (1ULL << 0) #define X86_EFLAGS_MODIFY_CF (1ULL << 1) #define X86_EFLAGS_MODIFY_SF (1ULL << 2) #define X86_EFLAGS_MODIFY_ZF (1ULL << 3) #define X86_EFLAGS_MODIFY_PF (1ULL << 4) #define X86_EFLAGS_MODIFY_OF (1ULL << 5) #define X86_EFLAGS_MODIFY_TF (1ULL << 6) #define X86_EFLAGS_MODIFY_IF (1ULL << 7) #define X86_EFLAGS_MODIFY_DF (1ULL << 8) #define X86_EFLAGS_MODIFY_NT (1ULL << 9) #define X86_EFLAGS_MODIFY_RF (1ULL << 10) #define X86_EFLAGS_PRIOR_OF (1ULL << 11) #define X86_EFLAGS_PRIOR_SF (1ULL << 12) #define X86_EFLAGS_PRIOR_ZF (1ULL << 13) #define X86_EFLAGS_PRIOR_AF (1ULL << 14) #define X86_EFLAGS_PRIOR_PF (1ULL << 15) #define X86_EFLAGS_PRIOR_CF (1ULL << 16) #define X86_EFLAGS_PRIOR_TF (1ULL << 17) #define X86_EFLAGS_PRIOR_IF (1ULL << 18) #define X86_EFLAGS_PRIOR_DF (1ULL << 19) #define X86_EFLAGS_PRIOR_NT (1ULL << 20) #define X86_EFLAGS_RESET_OF (1ULL << 21) #define X86_EFLAGS_RESET_CF (1ULL << 22) #define X86_EFLAGS_RESET_DF (1ULL << 23) #define X86_EFLAGS_RESET_IF (1ULL << 24) #define X86_EFLAGS_RESET_SF (1ULL << 25) #define X86_EFLAGS_RESET_AF (1ULL << 26) #define X86_EFLAGS_RESET_TF (1ULL << 27) #define X86_EFLAGS_RESET_NT (1ULL << 28) #define X86_EFLAGS_RESET_PF (1ULL << 29) #define X86_EFLAGS_SET_CF (1ULL << 30) #define X86_EFLAGS_SET_DF (1ULL << 31) #define X86_EFLAGS_SET_IF (1ULL << 32) #define X86_EFLAGS_TEST_OF (1ULL << 33) #define X86_EFLAGS_TEST_SF (1ULL << 34) #define X86_EFLAGS_TEST_ZF (1ULL << 35) #define X86_EFLAGS_TEST_PF (1ULL << 36) #define X86_EFLAGS_TEST_CF (1ULL << 37) #define X86_EFLAGS_TEST_NT (1ULL << 38) #define X86_EFLAGS_TEST_DF (1ULL << 39) #define X86_EFLAGS_UNDEFINED_OF (1ULL << 40) #define X86_EFLAGS_UNDEFINED_SF (1ULL << 41) #define X86_EFLAGS_UNDEFINED_ZF (1ULL << 42) #define X86_EFLAGS_UNDEFINED_PF (1ULL << 43) #define X86_EFLAGS_UNDEFINED_AF (1ULL << 44) #define X86_EFLAGS_UNDEFINED_CF (1ULL << 45) //> Operand type for instruction's operands typedef enum x86_op_type { X86_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). X86_OP_REG, // = CS_OP_REG (Register operand). X86_OP_IMM, // = CS_OP_IMM (Immediate operand). X86_OP_MEM, // = CS_OP_MEM (Memory operand). } x86_op_type; //> XOP Code Condition type typedef enum x86_xop_cc { X86_XOP_CC_INVALID = 0, // Uninitialized. X86_XOP_CC_LT, X86_XOP_CC_LE, X86_XOP_CC_GT, X86_XOP_CC_GE, X86_XOP_CC_EQ, X86_XOP_CC_NEQ, X86_XOP_CC_FALSE, X86_XOP_CC_TRUE, } x86_xop_cc; //> AVX broadcast type typedef enum x86_avx_bcast { X86_AVX_BCAST_INVALID = 0, // Uninitialized. X86_AVX_BCAST_2, // AVX512 broadcast type {1to2} X86_AVX_BCAST_4, // AVX512 broadcast type {1to4} X86_AVX_BCAST_8, // AVX512 broadcast type {1to8} X86_AVX_BCAST_16, // AVX512 broadcast type {1to16} } x86_avx_bcast; //> SSE Code Condition type typedef enum x86_sse_cc { X86_SSE_CC_INVALID = 0, // Uninitialized. X86_SSE_CC_EQ, X86_SSE_CC_LT, X86_SSE_CC_LE, X86_SSE_CC_UNORD, X86_SSE_CC_NEQ, X86_SSE_CC_NLT, X86_SSE_CC_NLE, X86_SSE_CC_ORD, } x86_sse_cc; //> AVX Code Condition type typedef enum x86_avx_cc { X86_AVX_CC_INVALID = 0, // Uninitialized. X86_AVX_CC_EQ, X86_AVX_CC_LT, X86_AVX_CC_LE, X86_AVX_CC_UNORD, X86_AVX_CC_NEQ, X86_AVX_CC_NLT, X86_AVX_CC_NLE, X86_AVX_CC_ORD, X86_AVX_CC_EQ_UQ, X86_AVX_CC_NGE, X86_AVX_CC_NGT, X86_AVX_CC_FALSE, X86_AVX_CC_NEQ_OQ, X86_AVX_CC_GE, X86_AVX_CC_GT, X86_AVX_CC_TRUE, X86_AVX_CC_EQ_OS, X86_AVX_CC_LT_OQ, X86_AVX_CC_LE_OQ, X86_AVX_CC_UNORD_S, X86_AVX_CC_NEQ_US, X86_AVX_CC_NLT_UQ, X86_AVX_CC_NLE_UQ, X86_AVX_CC_ORD_S, X86_AVX_CC_EQ_US, X86_AVX_CC_NGE_UQ, X86_AVX_CC_NGT_UQ, X86_AVX_CC_FALSE_OS, X86_AVX_CC_NEQ_OS, X86_AVX_CC_GE_OQ, X86_AVX_CC_GT_OQ, X86_AVX_CC_TRUE_US, } x86_avx_cc; //> AVX static rounding mode type typedef enum x86_avx_rm { X86_AVX_RM_INVALID = 0, // Uninitialized. X86_AVX_RM_RN, // Round to nearest X86_AVX_RM_RD, // Round down X86_AVX_RM_RU, // Round up X86_AVX_RM_RZ, // Round toward zero } x86_avx_rm; //> Instruction prefixes - to be used in cs_x86.prefix[] typedef enum x86_prefix { X86_PREFIX_LOCK = 0xf0, // lock (cs_x86.prefix[0] X86_PREFIX_REP = 0xf3, // rep (cs_x86.prefix[0] X86_PREFIX_REPE = 0xf3, // repe/repz (cs_x86.prefix[0] X86_PREFIX_REPNE = 0xf2, // repne/repnz (cs_x86.prefix[0] X86_PREFIX_CS = 0x2e, // segment override CS (cs_x86.prefix[1] X86_PREFIX_SS = 0x36, // segment override SS (cs_x86.prefix[1] X86_PREFIX_DS = 0x3e, // segment override DS (cs_x86.prefix[1] X86_PREFIX_ES = 0x26, // segment override ES (cs_x86.prefix[1] X86_PREFIX_FS = 0x64, // segment override FS (cs_x86.prefix[1] X86_PREFIX_GS = 0x65, // segment override GS (cs_x86.prefix[1] X86_PREFIX_OPSIZE = 0x66, // operand-size override (cs_x86.prefix[2] X86_PREFIX_ADDRSIZE = 0x67, // address-size override (cs_x86.prefix[3] } x86_prefix; // Instruction's operand referring to memory // This is associated with X86_OP_MEM operand type above typedef struct x86_op_mem { x86_reg segment; // segment register (or X86_REG_INVALID if irrelevant) x86_reg base; // base register (or X86_REG_INVALID if irrelevant) x86_reg index; // index register (or X86_REG_INVALID if irrelevant) int scale; // scale for index register int64_t disp; // displacement value } x86_op_mem; // Instruction operand typedef struct cs_x86_op { x86_op_type type; // operand type union { x86_reg reg; // register value for REG operand int64_t imm; // immediate value for IMM operand x86_op_mem mem; // base/index/scale/disp value for MEM operand }; // size of this operand (in bytes). uint8_t size; // How is this operand accessed? (READ, WRITE or READ|WRITE) // This field is combined of cs_ac_type. // NOTE: this field is irrelevant if engine is compiled in DIET mode. uint8_t access; // AVX broadcast type, or 0 if irrelevant x86_avx_bcast avx_bcast; // AVX zero opmask {z} bool avx_zero_opmask; } cs_x86_op; // Instruction structure typedef struct cs_x86 { // Instruction prefix, which can be up to 4 bytes. // A prefix byte gets value 0 when irrelevant. // prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above) // prefix[1] indicates segment override (irrelevant for x86_64): // See X86_PREFIX_CS/SS/DS/ES/FS/GS above. // prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE) // prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE) uint8_t prefix[4]; // Instruction opcode, wich can be from 1 to 4 bytes in size. // This contains VEX opcode as well. // An trailing opcode byte gets value 0 when irrelevant. uint8_t opcode[4]; // REX prefix: only a non-zero value is relavant for x86_64 uint8_t rex; // Address size, which can be overrided with above prefix[5]. uint8_t addr_size; // ModR/M byte uint8_t modrm; // SIB value, or 0 when irrelevant. uint8_t sib; // Displacement value, or 0 when irrelevant. int32_t disp; /* SIB state */ // SIB index register, or X86_REG_INVALID when irrelevant. x86_reg sib_index; // SIB scale. only applicable if sib_index is relavant. int8_t sib_scale; // SIB base register, or X86_REG_INVALID when irrelevant. x86_reg sib_base; // XOP Code Condition x86_xop_cc xop_cc; // SSE Code Condition x86_sse_cc sse_cc; // AVX Code Condition x86_avx_cc avx_cc; // AVX Suppress all Exception bool avx_sae; // AVX static rounding mode x86_avx_rm avx_rm; // EFLAGS updated by this instruction. // This can be formed from OR combination of X86_EFLAGS_* symbols in x86.h uint64_t eflags; // Number of operands of this instruction, // or 0 when instruction has no operand. uint8_t op_count; cs_x86_op operands[8]; // operands for this instruction. } cs_x86; //> X86 instructions typedef enum x86_insn { X86_INS_INVALID = 0, X86_INS_AAA, X86_INS_AAD, X86_INS_AAM, X86_INS_AAS, X86_INS_FABS, X86_INS_ADC, X86_INS_ADCX, X86_INS_ADD, X86_INS_ADDPD, X86_INS_ADDPS, X86_INS_ADDSD, X86_INS_ADDSS, X86_INS_ADDSUBPD, X86_INS_ADDSUBPS, X86_INS_FADD, X86_INS_FIADD, X86_INS_FADDP, X86_INS_ADOX, X86_INS_AESDECLAST, X86_INS_AESDEC, X86_INS_AESENCLAST, X86_INS_AESENC, X86_INS_AESIMC, X86_INS_AESKEYGENASSIST, X86_INS_AND, X86_INS_ANDN, X86_INS_ANDNPD, X86_INS_ANDNPS, X86_INS_ANDPD, X86_INS_ANDPS, X86_INS_ARPL, X86_INS_BEXTR, X86_INS_BLCFILL, X86_INS_BLCI, X86_INS_BLCIC, X86_INS_BLCMSK, X86_INS_BLCS, X86_INS_BLENDPD, X86_INS_BLENDPS, X86_INS_BLENDVPD, X86_INS_BLENDVPS, X86_INS_BLSFILL, X86_INS_BLSI, X86_INS_BLSIC, X86_INS_BLSMSK, X86_INS_BLSR, X86_INS_BOUND, X86_INS_BSF, X86_INS_BSR, X86_INS_BSWAP, X86_INS_BT, X86_INS_BTC, X86_INS_BTR, X86_INS_BTS, X86_INS_BZHI, X86_INS_CALL, X86_INS_CBW, X86_INS_CDQ, X86_INS_CDQE, X86_INS_FCHS, X86_INS_CLAC, X86_INS_CLC, X86_INS_CLD, X86_INS_CLFLUSH, X86_INS_CLFLUSHOPT, X86_INS_CLGI, X86_INS_CLI, X86_INS_CLTS, X86_INS_CLWB, X86_INS_CMC, X86_INS_CMOVA, X86_INS_CMOVAE, X86_INS_CMOVB, X86_INS_CMOVBE, X86_INS_FCMOVBE, X86_INS_FCMOVB, X86_INS_CMOVE, X86_INS_FCMOVE, X86_INS_CMOVG, X86_INS_CMOVGE, X86_INS_CMOVL, X86_INS_CMOVLE, X86_INS_FCMOVNBE, X86_INS_FCMOVNB, X86_INS_CMOVNE, X86_INS_FCMOVNE, X86_INS_CMOVNO, X86_INS_CMOVNP, X86_INS_FCMOVNU, X86_INS_CMOVNS, X86_INS_CMOVO, X86_INS_CMOVP, X86_INS_FCMOVU, X86_INS_CMOVS, X86_INS_CMP, X86_INS_CMPPD, X86_INS_CMPPS, X86_INS_CMPSB, X86_INS_CMPSD, X86_INS_CMPSQ, X86_INS_CMPSS, X86_INS_CMPSW, X86_INS_CMPXCHG16B, X86_INS_CMPXCHG, X86_INS_CMPXCHG8B, X86_INS_COMISD, X86_INS_COMISS, X86_INS_FCOMP, X86_INS_FCOMPI, X86_INS_FCOMI, X86_INS_FCOM, X86_INS_FCOS, X86_INS_CPUID, X86_INS_CQO, X86_INS_CRC32, X86_INS_CVTDQ2PD, X86_INS_CVTDQ2PS, X86_INS_CVTPD2DQ, X86_INS_CVTPD2PS, X86_INS_CVTPS2DQ, X86_INS_CVTPS2PD, X86_INS_CVTSD2SI, X86_INS_CVTSD2SS, X86_INS_CVTSI2SD, X86_INS_CVTSI2SS, X86_INS_CVTSS2SD, X86_INS_CVTSS2SI, X86_INS_CVTTPD2DQ, X86_INS_CVTTPS2DQ, X86_INS_CVTTSD2SI, X86_INS_CVTTSS2SI, X86_INS_CWD, X86_INS_CWDE, X86_INS_DAA, X86_INS_DAS, X86_INS_DATA16, X86_INS_DEC, X86_INS_DIV, X86_INS_DIVPD, X86_INS_DIVPS, X86_INS_FDIVR, X86_INS_FIDIVR, X86_INS_FDIVRP, X86_INS_DIVSD, X86_INS_DIVSS, X86_INS_FDIV, X86_INS_FIDIV, X86_INS_FDIVP, X86_INS_DPPD, X86_INS_DPPS, X86_INS_RET, X86_INS_ENCLS, X86_INS_ENCLU, X86_INS_ENTER, X86_INS_EXTRACTPS, X86_INS_EXTRQ, X86_INS_F2XM1, X86_INS_LCALL, X86_INS_LJMP, X86_INS_FBLD, X86_INS_FBSTP, X86_INS_FCOMPP, X86_INS_FDECSTP, X86_INS_FEMMS, X86_INS_FFREE, X86_INS_FICOM, X86_INS_FICOMP, X86_INS_FINCSTP, X86_INS_FLDCW, X86_INS_FLDENV, X86_INS_FLDL2E, X86_INS_FLDL2T, X86_INS_FLDLG2, X86_INS_FLDLN2, X86_INS_FLDPI, X86_INS_FNCLEX, X86_INS_FNINIT, X86_INS_FNOP, X86_INS_FNSTCW, X86_INS_FNSTSW, X86_INS_FPATAN, X86_INS_FPREM, X86_INS_FPREM1, X86_INS_FPTAN, X86_INS_FFREEP, X86_INS_FRNDINT, X86_INS_FRSTOR, X86_INS_FNSAVE, X86_INS_FSCALE, X86_INS_FSETPM, X86_INS_FSINCOS, X86_INS_FNSTENV, X86_INS_FXAM, X86_INS_FXRSTOR, X86_INS_FXRSTOR64, X86_INS_FXSAVE, X86_INS_FXSAVE64, X86_INS_FXTRACT, X86_INS_FYL2X, X86_INS_FYL2XP1, X86_INS_MOVAPD, X86_INS_MOVAPS, X86_INS_ORPD, X86_INS_ORPS, X86_INS_VMOVAPD, X86_INS_VMOVAPS, X86_INS_XORPD, X86_INS_XORPS, X86_INS_GETSEC, X86_INS_HADDPD, X86_INS_HADDPS, X86_INS_HLT, X86_INS_HSUBPD, X86_INS_HSUBPS, X86_INS_IDIV, X86_INS_FILD, X86_INS_IMUL, X86_INS_IN, X86_INS_INC, X86_INS_INSB, X86_INS_INSERTPS, X86_INS_INSERTQ, X86_INS_INSD, X86_INS_INSW, X86_INS_INT, X86_INS_INT1, X86_INS_INT3, X86_INS_INTO, X86_INS_INVD, X86_INS_INVEPT, X86_INS_INVLPG, X86_INS_INVLPGA, X86_INS_INVPCID, X86_INS_INVVPID, X86_INS_IRET, X86_INS_IRETD, X86_INS_IRETQ, X86_INS_FISTTP, X86_INS_FIST, X86_INS_FISTP, X86_INS_UCOMISD, X86_INS_UCOMISS, X86_INS_VCOMISD, X86_INS_VCOMISS, X86_INS_VCVTSD2SS, X86_INS_VCVTSI2SD, X86_INS_VCVTSI2SS, X86_INS_VCVTSS2SD, X86_INS_VCVTTSD2SI, X86_INS_VCVTTSD2USI, X86_INS_VCVTTSS2SI, X86_INS_VCVTTSS2USI, X86_INS_VCVTUSI2SD, X86_INS_VCVTUSI2SS, X86_INS_VUCOMISD, X86_INS_VUCOMISS, X86_INS_JAE, X86_INS_JA, X86_INS_JBE, X86_INS_JB, X86_INS_JCXZ, X86_INS_JECXZ, X86_INS_JE, X86_INS_JGE, X86_INS_JG, X86_INS_JLE, X86_INS_JL, X86_INS_JMP, X86_INS_JNE, X86_INS_JNO, X86_INS_JNP, X86_INS_JNS, X86_INS_JO, X86_INS_JP, X86_INS_JRCXZ, X86_INS_JS, X86_INS_KANDB, X86_INS_KANDD, X86_INS_KANDNB, X86_INS_KANDND, X86_INS_KANDNQ, X86_INS_KANDNW, X86_INS_KANDQ, X86_INS_KANDW, X86_INS_KMOVB, X86_INS_KMOVD, X86_INS_KMOVQ, X86_INS_KMOVW, X86_INS_KNOTB, X86_INS_KNOTD, X86_INS_KNOTQ, X86_INS_KNOTW, X86_INS_KORB, X86_INS_KORD, X86_INS_KORQ, X86_INS_KORTESTB, X86_INS_KORTESTD, X86_INS_KORTESTQ, X86_INS_KORTESTW, X86_INS_KORW, X86_INS_KSHIFTLB, X86_INS_KSHIFTLD, X86_INS_KSHIFTLQ, X86_INS_KSHIFTLW, X86_INS_KSHIFTRB, X86_INS_KSHIFTRD, X86_INS_KSHIFTRQ, X86_INS_KSHIFTRW, X86_INS_KUNPCKBW, X86_INS_KXNORB, X86_INS_KXNORD, X86_INS_KXNORQ, X86_INS_KXNORW, X86_INS_KXORB, X86_INS_KXORD, X86_INS_KXORQ, X86_INS_KXORW, X86_INS_LAHF, X86_INS_LAR, X86_INS_LDDQU, X86_INS_LDMXCSR, X86_INS_LDS, X86_INS_FLDZ, X86_INS_FLD1, X86_INS_FLD, X86_INS_LEA, X86_INS_LEAVE, X86_INS_LES, X86_INS_LFENCE, X86_INS_LFS, X86_INS_LGDT, X86_INS_LGS, X86_INS_LIDT, X86_INS_LLDT, X86_INS_LMSW, X86_INS_OR, X86_INS_SUB, X86_INS_XOR, X86_INS_LODSB, X86_INS_LODSD, X86_INS_LODSQ, X86_INS_LODSW, X86_INS_LOOP, X86_INS_LOOPE, X86_INS_LOOPNE, X86_INS_RETF, X86_INS_RETFQ, X86_INS_LSL, X86_INS_LSS, X86_INS_LTR, X86_INS_XADD, X86_INS_LZCNT, X86_INS_MASKMOVDQU, X86_INS_MAXPD, X86_INS_MAXPS, X86_INS_MAXSD, X86_INS_MAXSS, X86_INS_MFENCE, X86_INS_MINPD, X86_INS_MINPS, X86_INS_MINSD, X86_INS_MINSS, X86_INS_CVTPD2PI, X86_INS_CVTPI2PD, X86_INS_CVTPI2PS, X86_INS_CVTPS2PI, X86_INS_CVTTPD2PI, X86_INS_CVTTPS2PI, X86_INS_EMMS, X86_INS_MASKMOVQ, X86_INS_MOVD, X86_INS_MOVDQ2Q, X86_INS_MOVNTQ, X86_INS_MOVQ2DQ, X86_INS_MOVQ, X86_INS_PABSB, X86_INS_PABSD, X86_INS_PABSW, X86_INS_PACKSSDW, X86_INS_PACKSSWB, X86_INS_PACKUSWB, X86_INS_PADDB, X86_INS_PADDD, X86_INS_PADDQ, X86_INS_PADDSB, X86_INS_PADDSW, X86_INS_PADDUSB, X86_INS_PADDUSW, X86_INS_PADDW, X86_INS_PALIGNR, X86_INS_PANDN, X86_INS_PAND, X86_INS_PAVGB, X86_INS_PAVGW, X86_INS_PCMPEQB, X86_INS_PCMPEQD, X86_INS_PCMPEQW, X86_INS_PCMPGTB, X86_INS_PCMPGTD, X86_INS_PCMPGTW, X86_INS_PEXTRW, X86_INS_PHADDSW, X86_INS_PHADDW, X86_INS_PHADDD, X86_INS_PHSUBD, X86_INS_PHSUBSW, X86_INS_PHSUBW, X86_INS_PINSRW, X86_INS_PMADDUBSW, X86_INS_PMADDWD, X86_INS_PMAXSW, X86_INS_PMAXUB, X86_INS_PMINSW, X86_INS_PMINUB, X86_INS_PMOVMSKB, X86_INS_PMULHRSW, X86_INS_PMULHUW, X86_INS_PMULHW, X86_INS_PMULLW, X86_INS_PMULUDQ, X86_INS_POR, X86_INS_PSADBW, X86_INS_PSHUFB, X86_INS_PSHUFW, X86_INS_PSIGNB, X86_INS_PSIGND, X86_INS_PSIGNW, X86_INS_PSLLD, X86_INS_PSLLQ, X86_INS_PSLLW, X86_INS_PSRAD, X86_INS_PSRAW, X86_INS_PSRLD, X86_INS_PSRLQ, X86_INS_PSRLW, X86_INS_PSUBB, X86_INS_PSUBD, X86_INS_PSUBQ, X86_INS_PSUBSB, X86_INS_PSUBSW, X86_INS_PSUBUSB, X86_INS_PSUBUSW, X86_INS_PSUBW, X86_INS_PUNPCKHBW, X86_INS_PUNPCKHDQ, X86_INS_PUNPCKHWD, X86_INS_PUNPCKLBW, X86_INS_PUNPCKLDQ, X86_INS_PUNPCKLWD, X86_INS_PXOR, X86_INS_MONITOR, X86_INS_MONTMUL, X86_INS_MOV, X86_INS_MOVABS, X86_INS_MOVBE, X86_INS_MOVDDUP, X86_INS_MOVDQA, X86_INS_MOVDQU, X86_INS_MOVHLPS, X86_INS_MOVHPD, X86_INS_MOVHPS, X86_INS_MOVLHPS, X86_INS_MOVLPD, X86_INS_MOVLPS, X86_INS_MOVMSKPD, X86_INS_MOVMSKPS, X86_INS_MOVNTDQA, X86_INS_MOVNTDQ, X86_INS_MOVNTI, X86_INS_MOVNTPD, X86_INS_MOVNTPS, X86_INS_MOVNTSD, X86_INS_MOVNTSS, X86_INS_MOVSB, X86_INS_MOVSD, X86_INS_MOVSHDUP, X86_INS_MOVSLDUP, X86_INS_MOVSQ, X86_INS_MOVSS, X86_INS_MOVSW, X86_INS_MOVSX, X86_INS_MOVSXD, X86_INS_MOVUPD, X86_INS_MOVUPS, X86_INS_MOVZX, X86_INS_MPSADBW, X86_INS_MUL, X86_INS_MULPD, X86_INS_MULPS, X86_INS_MULSD, X86_INS_MULSS, X86_INS_MULX, X86_INS_FMUL, X86_INS_FIMUL, X86_INS_FMULP, X86_INS_MWAIT, X86_INS_NEG, X86_INS_NOP, X86_INS_NOT, X86_INS_OUT, X86_INS_OUTSB, X86_INS_OUTSD, X86_INS_OUTSW, X86_INS_PACKUSDW, X86_INS_PAUSE, X86_INS_PAVGUSB, X86_INS_PBLENDVB, X86_INS_PBLENDW, X86_INS_PCLMULQDQ, X86_INS_PCMPEQQ, X86_INS_PCMPESTRI, X86_INS_PCMPESTRM, X86_INS_PCMPGTQ, X86_INS_PCMPISTRI, X86_INS_PCMPISTRM, X86_INS_PCOMMIT, X86_INS_PDEP, X86_INS_PEXT, X86_INS_PEXTRB, X86_INS_PEXTRD, X86_INS_PEXTRQ, X86_INS_PF2ID, X86_INS_PF2IW, X86_INS_PFACC, X86_INS_PFADD, X86_INS_PFCMPEQ, X86_INS_PFCMPGE, X86_INS_PFCMPGT, X86_INS_PFMAX, X86_INS_PFMIN, X86_INS_PFMUL, X86_INS_PFNACC, X86_INS_PFPNACC, X86_INS_PFRCPIT1, X86_INS_PFRCPIT2, X86_INS_PFRCP, X86_INS_PFRSQIT1, X86_INS_PFRSQRT, X86_INS_PFSUBR, X86_INS_PFSUB, X86_INS_PHMINPOSUW, X86_INS_PI2FD, X86_INS_PI2FW, X86_INS_PINSRB, X86_INS_PINSRD, X86_INS_PINSRQ, X86_INS_PMAXSB, X86_INS_PMAXSD, X86_INS_PMAXUD, X86_INS_PMAXUW, X86_INS_PMINSB, X86_INS_PMINSD, X86_INS_PMINUD, X86_INS_PMINUW, X86_INS_PMOVSXBD, X86_INS_PMOVSXBQ, X86_INS_PMOVSXBW, X86_INS_PMOVSXDQ, X86_INS_PMOVSXWD, X86_INS_PMOVSXWQ, X86_INS_PMOVZXBD, X86_INS_PMOVZXBQ, X86_INS_PMOVZXBW, X86_INS_PMOVZXDQ, X86_INS_PMOVZXWD, X86_INS_PMOVZXWQ, X86_INS_PMULDQ, X86_INS_PMULHRW, X86_INS_PMULLD, X86_INS_POP, X86_INS_POPAW, X86_INS_POPAL, X86_INS_POPCNT, X86_INS_POPF, X86_INS_POPFD, X86_INS_POPFQ, X86_INS_PREFETCH, X86_INS_PREFETCHNTA, X86_INS_PREFETCHT0, X86_INS_PREFETCHT1, X86_INS_PREFETCHT2, X86_INS_PREFETCHW, X86_INS_PSHUFD, X86_INS_PSHUFHW, X86_INS_PSHUFLW, X86_INS_PSLLDQ, X86_INS_PSRLDQ, X86_INS_PSWAPD, X86_INS_PTEST, X86_INS_PUNPCKHQDQ, X86_INS_PUNPCKLQDQ, X86_INS_PUSH, X86_INS_PUSHAW, X86_INS_PUSHAL, X86_INS_PUSHF, X86_INS_PUSHFD, X86_INS_PUSHFQ, X86_INS_RCL, X86_INS_RCPPS, X86_INS_RCPSS, X86_INS_RCR, X86_INS_RDFSBASE, X86_INS_RDGSBASE, X86_INS_RDMSR, X86_INS_RDPMC, X86_INS_RDRAND, X86_INS_RDSEED, X86_INS_RDTSC, X86_INS_RDTSCP, X86_INS_ROL, X86_INS_ROR, X86_INS_RORX, X86_INS_ROUNDPD, X86_INS_ROUNDPS, X86_INS_ROUNDSD, X86_INS_ROUNDSS, X86_INS_RSM, X86_INS_RSQRTPS, X86_INS_RSQRTSS, X86_INS_SAHF, X86_INS_SAL, X86_INS_SALC, X86_INS_SAR, X86_INS_SARX, X86_INS_SBB, X86_INS_SCASB, X86_INS_SCASD, X86_INS_SCASQ, X86_INS_SCASW, X86_INS_SETAE, X86_INS_SETA, X86_INS_SETBE, X86_INS_SETB, X86_INS_SETE, X86_INS_SETGE, X86_INS_SETG, X86_INS_SETLE, X86_INS_SETL, X86_INS_SETNE, X86_INS_SETNO, X86_INS_SETNP, X86_INS_SETNS, X86_INS_SETO, X86_INS_SETP, X86_INS_SETS, X86_INS_SFENCE, X86_INS_SGDT, X86_INS_SHA1MSG1, X86_INS_SHA1MSG2, X86_INS_SHA1NEXTE, X86_INS_SHA1RNDS4, X86_INS_SHA256MSG1, X86_INS_SHA256MSG2, X86_INS_SHA256RNDS2, X86_INS_SHL, X86_INS_SHLD, X86_INS_SHLX, X86_INS_SHR, X86_INS_SHRD, X86_INS_SHRX, X86_INS_SHUFPD, X86_INS_SHUFPS, X86_INS_SIDT, X86_INS_FSIN, X86_INS_SKINIT, X86_INS_SLDT, X86_INS_SMSW, X86_INS_SQRTPD, X86_INS_SQRTPS, X86_INS_SQRTSD, X86_INS_SQRTSS, X86_INS_FSQRT, X86_INS_STAC, X86_INS_STC, X86_INS_STD, X86_INS_STGI, X86_INS_STI, X86_INS_STMXCSR, X86_INS_STOSB, X86_INS_STOSD, X86_INS_STOSQ, X86_INS_STOSW, X86_INS_STR, X86_INS_FST, X86_INS_FSTP, X86_INS_FSTPNCE, X86_INS_FXCH, X86_INS_SUBPD, X86_INS_SUBPS, X86_INS_FSUBR, X86_INS_FISUBR, X86_INS_FSUBRP, X86_INS_SUBSD, X86_INS_SUBSS, X86_INS_FSUB, X86_INS_FISUB, X86_INS_FSUBP, X86_INS_SWAPGS, X86_INS_SYSCALL, X86_INS_SYSENTER, X86_INS_SYSEXIT, X86_INS_SYSRET, X86_INS_T1MSKC, X86_INS_TEST, X86_INS_UD2, X86_INS_FTST, X86_INS_TZCNT, X86_INS_TZMSK, X86_INS_FUCOMPI, X86_INS_FUCOMI, X86_INS_FUCOMPP, X86_INS_FUCOMP, X86_INS_FUCOM, X86_INS_UD2B, X86_INS_UNPCKHPD, X86_INS_UNPCKHPS, X86_INS_UNPCKLPD, X86_INS_UNPCKLPS, X86_INS_VADDPD, X86_INS_VADDPS, X86_INS_VADDSD, X86_INS_VADDSS, X86_INS_VADDSUBPD, X86_INS_VADDSUBPS, X86_INS_VAESDECLAST, X86_INS_VAESDEC, X86_INS_VAESENCLAST, X86_INS_VAESENC, X86_INS_VAESIMC, X86_INS_VAESKEYGENASSIST, X86_INS_VALIGND, X86_INS_VALIGNQ, X86_INS_VANDNPD, X86_INS_VANDNPS, X86_INS_VANDPD, X86_INS_VANDPS, X86_INS_VBLENDMPD, X86_INS_VBLENDMPS, X86_INS_VBLENDPD, X86_INS_VBLENDPS, X86_INS_VBLENDVPD, X86_INS_VBLENDVPS, X86_INS_VBROADCASTF128, X86_INS_VBROADCASTI32X4, X86_INS_VBROADCASTI64X4, X86_INS_VBROADCASTSD, X86_INS_VBROADCASTSS, X86_INS_VCMPPD, X86_INS_VCMPPS, X86_INS_VCMPSD, X86_INS_VCMPSS, X86_INS_VCOMPRESSPD, X86_INS_VCOMPRESSPS, X86_INS_VCVTDQ2PD, X86_INS_VCVTDQ2PS, X86_INS_VCVTPD2DQX, X86_INS_VCVTPD2DQ, X86_INS_VCVTPD2PSX, X86_INS_VCVTPD2PS, X86_INS_VCVTPD2UDQ, X86_INS_VCVTPH2PS, X86_INS_VCVTPS2DQ, X86_INS_VCVTPS2PD, X86_INS_VCVTPS2PH, X86_INS_VCVTPS2UDQ, X86_INS_VCVTSD2SI, X86_INS_VCVTSD2USI, X86_INS_VCVTSS2SI, X86_INS_VCVTSS2USI, X86_INS_VCVTTPD2DQX, X86_INS_VCVTTPD2DQ, X86_INS_VCVTTPD2UDQ, X86_INS_VCVTTPS2DQ, X86_INS_VCVTTPS2UDQ, X86_INS_VCVTUDQ2PD, X86_INS_VCVTUDQ2PS, X86_INS_VDIVPD, X86_INS_VDIVPS, X86_INS_VDIVSD, X86_INS_VDIVSS, X86_INS_VDPPD, X86_INS_VDPPS, X86_INS_VERR, X86_INS_VERW, X86_INS_VEXP2PD, X86_INS_VEXP2PS, X86_INS_VEXPANDPD, X86_INS_VEXPANDPS, X86_INS_VEXTRACTF128, X86_INS_VEXTRACTF32X4, X86_INS_VEXTRACTF64X4, X86_INS_VEXTRACTI128, X86_INS_VEXTRACTI32X4, X86_INS_VEXTRACTI64X4, X86_INS_VEXTRACTPS, X86_INS_VFMADD132PD, X86_INS_VFMADD132PS, X86_INS_VFMADDPD, X86_INS_VFMADD213PD, X86_INS_VFMADD231PD, X86_INS_VFMADDPS, X86_INS_VFMADD213PS, X86_INS_VFMADD231PS, X86_INS_VFMADDSD, X86_INS_VFMADD213SD, X86_INS_VFMADD132SD, X86_INS_VFMADD231SD, X86_INS_VFMADDSS, X86_INS_VFMADD213SS, X86_INS_VFMADD132SS, X86_INS_VFMADD231SS, X86_INS_VFMADDSUB132PD, X86_INS_VFMADDSUB132PS, X86_INS_VFMADDSUBPD, X86_INS_VFMADDSUB213PD, X86_INS_VFMADDSUB231PD, X86_INS_VFMADDSUBPS, X86_INS_VFMADDSUB213PS, X86_INS_VFMADDSUB231PS, X86_INS_VFMSUB132PD, X86_INS_VFMSUB132PS, X86_INS_VFMSUBADD132PD, X86_INS_VFMSUBADD132PS, X86_INS_VFMSUBADDPD, X86_INS_VFMSUBADD213PD, X86_INS_VFMSUBADD231PD, X86_INS_VFMSUBADDPS, X86_INS_VFMSUBADD213PS, X86_INS_VFMSUBADD231PS, X86_INS_VFMSUBPD, X86_INS_VFMSUB213PD, X86_INS_VFMSUB231PD, X86_INS_VFMSUBPS, X86_INS_VFMSUB213PS, X86_INS_VFMSUB231PS, X86_INS_VFMSUBSD, X86_INS_VFMSUB213SD, X86_INS_VFMSUB132SD, X86_INS_VFMSUB231SD, X86_INS_VFMSUBSS, X86_INS_VFMSUB213SS, X86_INS_VFMSUB132SS, X86_INS_VFMSUB231SS, X86_INS_VFNMADD132PD, X86_INS_VFNMADD132PS, X86_INS_VFNMADDPD, X86_INS_VFNMADD213PD, X86_INS_VFNMADD231PD, X86_INS_VFNMADDPS, X86_INS_VFNMADD213PS, X86_INS_VFNMADD231PS, X86_INS_VFNMADDSD, X86_INS_VFNMADD213SD, X86_INS_VFNMADD132SD, X86_INS_VFNMADD231SD, X86_INS_VFNMADDSS, X86_INS_VFNMADD213SS, X86_INS_VFNMADD132SS, X86_INS_VFNMADD231SS, X86_INS_VFNMSUB132PD, X86_INS_VFNMSUB132PS, X86_INS_VFNMSUBPD, X86_INS_VFNMSUB213PD, X86_INS_VFNMSUB231PD, X86_INS_VFNMSUBPS, X86_INS_VFNMSUB213PS, X86_INS_VFNMSUB231PS, X86_INS_VFNMSUBSD, X86_INS_VFNMSUB213SD, X86_INS_VFNMSUB132SD, X86_INS_VFNMSUB231SD, X86_INS_VFNMSUBSS, X86_INS_VFNMSUB213SS, X86_INS_VFNMSUB132SS, X86_INS_VFNMSUB231SS, X86_INS_VFRCZPD, X86_INS_VFRCZPS, X86_INS_VFRCZSD, X86_INS_VFRCZSS, X86_INS_VORPD, X86_INS_VORPS, X86_INS_VXORPD, X86_INS_VXORPS, X86_INS_VGATHERDPD, X86_INS_VGATHERDPS, X86_INS_VGATHERPF0DPD, X86_INS_VGATHERPF0DPS, X86_INS_VGATHERPF0QPD, X86_INS_VGATHERPF0QPS, X86_INS_VGATHERPF1DPD, X86_INS_VGATHERPF1DPS, X86_INS_VGATHERPF1QPD, X86_INS_VGATHERPF1QPS, X86_INS_VGATHERQPD, X86_INS_VGATHERQPS, X86_INS_VHADDPD, X86_INS_VHADDPS, X86_INS_VHSUBPD, X86_INS_VHSUBPS, X86_INS_VINSERTF128, X86_INS_VINSERTF32X4, X86_INS_VINSERTF32X8, X86_INS_VINSERTF64X2, X86_INS_VINSERTF64X4, X86_INS_VINSERTI128, X86_INS_VINSERTI32X4, X86_INS_VINSERTI32X8, X86_INS_VINSERTI64X2, X86_INS_VINSERTI64X4, X86_INS_VINSERTPS, X86_INS_VLDDQU, X86_INS_VLDMXCSR, X86_INS_VMASKMOVDQU, X86_INS_VMASKMOVPD, X86_INS_VMASKMOVPS, X86_INS_VMAXPD, X86_INS_VMAXPS, X86_INS_VMAXSD, X86_INS_VMAXSS, X86_INS_VMCALL, X86_INS_VMCLEAR, X86_INS_VMFUNC, X86_INS_VMINPD, X86_INS_VMINPS, X86_INS_VMINSD, X86_INS_VMINSS, X86_INS_VMLAUNCH, X86_INS_VMLOAD, X86_INS_VMMCALL, X86_INS_VMOVQ, X86_INS_VMOVDDUP, X86_INS_VMOVD, X86_INS_VMOVDQA32, X86_INS_VMOVDQA64, X86_INS_VMOVDQA, X86_INS_VMOVDQU16, X86_INS_VMOVDQU32, X86_INS_VMOVDQU64, X86_INS_VMOVDQU8, X86_INS_VMOVDQU, X86_INS_VMOVHLPS, X86_INS_VMOVHPD, X86_INS_VMOVHPS, X86_INS_VMOVLHPS, X86_INS_VMOVLPD, X86_INS_VMOVLPS, X86_INS_VMOVMSKPD, X86_INS_VMOVMSKPS, X86_INS_VMOVNTDQA, X86_INS_VMOVNTDQ, X86_INS_VMOVNTPD, X86_INS_VMOVNTPS, X86_INS_VMOVSD, X86_INS_VMOVSHDUP, X86_INS_VMOVSLDUP, X86_INS_VMOVSS, X86_INS_VMOVUPD, X86_INS_VMOVUPS, X86_INS_VMPSADBW, X86_INS_VMPTRLD, X86_INS_VMPTRST, X86_INS_VMREAD, X86_INS_VMRESUME, X86_INS_VMRUN, X86_INS_VMSAVE, X86_INS_VMULPD, X86_INS_VMULPS, X86_INS_VMULSD, X86_INS_VMULSS, X86_INS_VMWRITE, X86_INS_VMXOFF, X86_INS_VMXON, X86_INS_VPABSB, X86_INS_VPABSD, X86_INS_VPABSQ, X86_INS_VPABSW, X86_INS_VPACKSSDW, X86_INS_VPACKSSWB, X86_INS_VPACKUSDW, X86_INS_VPACKUSWB, X86_INS_VPADDB, X86_INS_VPADDD, X86_INS_VPADDQ, X86_INS_VPADDSB, X86_INS_VPADDSW, X86_INS_VPADDUSB, X86_INS_VPADDUSW, X86_INS_VPADDW, X86_INS_VPALIGNR, X86_INS_VPANDD, X86_INS_VPANDND, X86_INS_VPANDNQ, X86_INS_VPANDN, X86_INS_VPANDQ, X86_INS_VPAND, X86_INS_VPAVGB, X86_INS_VPAVGW, X86_INS_VPBLENDD, X86_INS_VPBLENDMB, X86_INS_VPBLENDMD, X86_INS_VPBLENDMQ, X86_INS_VPBLENDMW, X86_INS_VPBLENDVB, X86_INS_VPBLENDW, X86_INS_VPBROADCASTB, X86_INS_VPBROADCASTD, X86_INS_VPBROADCASTMB2Q, X86_INS_VPBROADCASTMW2D, X86_INS_VPBROADCASTQ, X86_INS_VPBROADCASTW, X86_INS_VPCLMULQDQ, X86_INS_VPCMOV, X86_INS_VPCMPB, X86_INS_VPCMPD, X86_INS_VPCMPEQB, X86_INS_VPCMPEQD, X86_INS_VPCMPEQQ, X86_INS_VPCMPEQW, X86_INS_VPCMPESTRI, X86_INS_VPCMPESTRM, X86_INS_VPCMPGTB, X86_INS_VPCMPGTD, X86_INS_VPCMPGTQ, X86_INS_VPCMPGTW, X86_INS_VPCMPISTRI, X86_INS_VPCMPISTRM, X86_INS_VPCMPQ, X86_INS_VPCMPUB, X86_INS_VPCMPUD, X86_INS_VPCMPUQ, X86_INS_VPCMPUW, X86_INS_VPCMPW, X86_INS_VPCOMB, X86_INS_VPCOMD, X86_INS_VPCOMPRESSD, X86_INS_VPCOMPRESSQ, X86_INS_VPCOMQ, X86_INS_VPCOMUB, X86_INS_VPCOMUD, X86_INS_VPCOMUQ, X86_INS_VPCOMUW, X86_INS_VPCOMW, X86_INS_VPCONFLICTD, X86_INS_VPCONFLICTQ, X86_INS_VPERM2F128, X86_INS_VPERM2I128, X86_INS_VPERMD, X86_INS_VPERMI2D, X86_INS_VPERMI2PD, X86_INS_VPERMI2PS, X86_INS_VPERMI2Q, X86_INS_VPERMIL2PD, X86_INS_VPERMIL2PS, X86_INS_VPERMILPD, X86_INS_VPERMILPS, X86_INS_VPERMPD, X86_INS_VPERMPS, X86_INS_VPERMQ, X86_INS_VPERMT2D, X86_INS_VPERMT2PD, X86_INS_VPERMT2PS, X86_INS_VPERMT2Q, X86_INS_VPEXPANDD, X86_INS_VPEXPANDQ, X86_INS_VPEXTRB, X86_INS_VPEXTRD, X86_INS_VPEXTRQ, X86_INS_VPEXTRW, X86_INS_VPGATHERDD, X86_INS_VPGATHERDQ, X86_INS_VPGATHERQD, X86_INS_VPGATHERQQ, X86_INS_VPHADDBD, X86_INS_VPHADDBQ, X86_INS_VPHADDBW, X86_INS_VPHADDDQ, X86_INS_VPHADDD, X86_INS_VPHADDSW, X86_INS_VPHADDUBD, X86_INS_VPHADDUBQ, X86_INS_VPHADDUBW, X86_INS_VPHADDUDQ, X86_INS_VPHADDUWD, X86_INS_VPHADDUWQ, X86_INS_VPHADDWD, X86_INS_VPHADDWQ, X86_INS_VPHADDW, X86_INS_VPHMINPOSUW, X86_INS_VPHSUBBW, X86_INS_VPHSUBDQ, X86_INS_VPHSUBD, X86_INS_VPHSUBSW, X86_INS_VPHSUBWD, X86_INS_VPHSUBW, X86_INS_VPINSRB, X86_INS_VPINSRD, X86_INS_VPINSRQ, X86_INS_VPINSRW, X86_INS_VPLZCNTD, X86_INS_VPLZCNTQ, X86_INS_VPMACSDD, X86_INS_VPMACSDQH, X86_INS_VPMACSDQL, X86_INS_VPMACSSDD, X86_INS_VPMACSSDQH, X86_INS_VPMACSSDQL, X86_INS_VPMACSSWD, X86_INS_VPMACSSWW, X86_INS_VPMACSWD, X86_INS_VPMACSWW, X86_INS_VPMADCSSWD, X86_INS_VPMADCSWD, X86_INS_VPMADDUBSW, X86_INS_VPMADDWD, X86_INS_VPMASKMOVD, X86_INS_VPMASKMOVQ, X86_INS_VPMAXSB, X86_INS_VPMAXSD, X86_INS_VPMAXSQ, X86_INS_VPMAXSW, X86_INS_VPMAXUB, X86_INS_VPMAXUD, X86_INS_VPMAXUQ, X86_INS_VPMAXUW, X86_INS_VPMINSB, X86_INS_VPMINSD, X86_INS_VPMINSQ, X86_INS_VPMINSW, X86_INS_VPMINUB, X86_INS_VPMINUD, X86_INS_VPMINUQ, X86_INS_VPMINUW, X86_INS_VPMOVDB, X86_INS_VPMOVDW, X86_INS_VPMOVM2B, X86_INS_VPMOVM2D, X86_INS_VPMOVM2Q, X86_INS_VPMOVM2W, X86_INS_VPMOVMSKB, X86_INS_VPMOVQB, X86_INS_VPMOVQD, X86_INS_VPMOVQW, X86_INS_VPMOVSDB, X86_INS_VPMOVSDW, X86_INS_VPMOVSQB, X86_INS_VPMOVSQD, X86_INS_VPMOVSQW, X86_INS_VPMOVSXBD, X86_INS_VPMOVSXBQ, X86_INS_VPMOVSXBW, X86_INS_VPMOVSXDQ, X86_INS_VPMOVSXWD, X86_INS_VPMOVSXWQ, X86_INS_VPMOVUSDB, X86_INS_VPMOVUSDW, X86_INS_VPMOVUSQB, X86_INS_VPMOVUSQD, X86_INS_VPMOVUSQW, X86_INS_VPMOVZXBD, X86_INS_VPMOVZXBQ, X86_INS_VPMOVZXBW, X86_INS_VPMOVZXDQ, X86_INS_VPMOVZXWD, X86_INS_VPMOVZXWQ, X86_INS_VPMULDQ, X86_INS_VPMULHRSW, X86_INS_VPMULHUW, X86_INS_VPMULHW, X86_INS_VPMULLD, X86_INS_VPMULLQ, X86_INS_VPMULLW, X86_INS_VPMULUDQ, X86_INS_VPORD, X86_INS_VPORQ, X86_INS_VPOR, X86_INS_VPPERM, X86_INS_VPROTB, X86_INS_VPROTD, X86_INS_VPROTQ, X86_INS_VPROTW, X86_INS_VPSADBW, X86_INS_VPSCATTERDD, X86_INS_VPSCATTERDQ, X86_INS_VPSCATTERQD, X86_INS_VPSCATTERQQ, X86_INS_VPSHAB, X86_INS_VPSHAD, X86_INS_VPSHAQ, X86_INS_VPSHAW, X86_INS_VPSHLB, X86_INS_VPSHLD, X86_INS_VPSHLQ, X86_INS_VPSHLW, X86_INS_VPSHUFB, X86_INS_VPSHUFD, X86_INS_VPSHUFHW, X86_INS_VPSHUFLW, X86_INS_VPSIGNB, X86_INS_VPSIGND, X86_INS_VPSIGNW, X86_INS_VPSLLDQ, X86_INS_VPSLLD, X86_INS_VPSLLQ, X86_INS_VPSLLVD, X86_INS_VPSLLVQ, X86_INS_VPSLLW, X86_INS_VPSRAD, X86_INS_VPSRAQ, X86_INS_VPSRAVD, X86_INS_VPSRAVQ, X86_INS_VPSRAW, X86_INS_VPSRLDQ, X86_INS_VPSRLD, X86_INS_VPSRLQ, X86_INS_VPSRLVD, X86_INS_VPSRLVQ, X86_INS_VPSRLW, X86_INS_VPSUBB, X86_INS_VPSUBD, X86_INS_VPSUBQ, X86_INS_VPSUBSB, X86_INS_VPSUBSW, X86_INS_VPSUBUSB, X86_INS_VPSUBUSW, X86_INS_VPSUBW, X86_INS_VPTESTMD, X86_INS_VPTESTMQ, X86_INS_VPTESTNMD, X86_INS_VPTESTNMQ, X86_INS_VPTEST, X86_INS_VPUNPCKHBW, X86_INS_VPUNPCKHDQ, X86_INS_VPUNPCKHQDQ, X86_INS_VPUNPCKHWD, X86_INS_VPUNPCKLBW, X86_INS_VPUNPCKLDQ, X86_INS_VPUNPCKLQDQ, X86_INS_VPUNPCKLWD, X86_INS_VPXORD, X86_INS_VPXORQ, X86_INS_VPXOR, X86_INS_VRCP14PD, X86_INS_VRCP14PS, X86_INS_VRCP14SD, X86_INS_VRCP14SS, X86_INS_VRCP28PD, X86_INS_VRCP28PS, X86_INS_VRCP28SD, X86_INS_VRCP28SS, X86_INS_VRCPPS, X86_INS_VRCPSS, X86_INS_VRNDSCALEPD, X86_INS_VRNDSCALEPS, X86_INS_VRNDSCALESD, X86_INS_VRNDSCALESS, X86_INS_VROUNDPD, X86_INS_VROUNDPS, X86_INS_VROUNDSD, X86_INS_VROUNDSS, X86_INS_VRSQRT14PD, X86_INS_VRSQRT14PS, X86_INS_VRSQRT14SD, X86_INS_VRSQRT14SS, X86_INS_VRSQRT28PD, X86_INS_VRSQRT28PS, X86_INS_VRSQRT28SD, X86_INS_VRSQRT28SS, X86_INS_VRSQRTPS, X86_INS_VRSQRTSS, X86_INS_VSCATTERDPD, X86_INS_VSCATTERDPS, X86_INS_VSCATTERPF0DPD, X86_INS_VSCATTERPF0DPS, X86_INS_VSCATTERPF0QPD, X86_INS_VSCATTERPF0QPS, X86_INS_VSCATTERPF1DPD, X86_INS_VSCATTERPF1DPS, X86_INS_VSCATTERPF1QPD, X86_INS_VSCATTERPF1QPS, X86_INS_VSCATTERQPD, X86_INS_VSCATTERQPS, X86_INS_VSHUFPD, X86_INS_VSHUFPS, X86_INS_VSQRTPD, X86_INS_VSQRTPS, X86_INS_VSQRTSD, X86_INS_VSQRTSS, X86_INS_VSTMXCSR, X86_INS_VSUBPD, X86_INS_VSUBPS, X86_INS_VSUBSD, X86_INS_VSUBSS, X86_INS_VTESTPD, X86_INS_VTESTPS, X86_INS_VUNPCKHPD, X86_INS_VUNPCKHPS, X86_INS_VUNPCKLPD, X86_INS_VUNPCKLPS, X86_INS_VZEROALL, X86_INS_VZEROUPPER, X86_INS_WAIT, X86_INS_WBINVD, X86_INS_WRFSBASE, X86_INS_WRGSBASE, X86_INS_WRMSR, X86_INS_XABORT, X86_INS_XACQUIRE, X86_INS_XBEGIN, X86_INS_XCHG, X86_INS_XCRYPTCBC, X86_INS_XCRYPTCFB, X86_INS_XCRYPTCTR, X86_INS_XCRYPTECB, X86_INS_XCRYPTOFB, X86_INS_XEND, X86_INS_XGETBV, X86_INS_XLATB, X86_INS_XRELEASE, X86_INS_XRSTOR, X86_INS_XRSTOR64, X86_INS_XRSTORS, X86_INS_XRSTORS64, X86_INS_XSAVE, X86_INS_XSAVE64, X86_INS_XSAVEC, X86_INS_XSAVEC64, X86_INS_XSAVEOPT, X86_INS_XSAVEOPT64, X86_INS_XSAVES, X86_INS_XSAVES64, X86_INS_XSETBV, X86_INS_XSHA1, X86_INS_XSHA256, X86_INS_XSTORE, X86_INS_XTEST, X86_INS_FDISI8087_NOP, X86_INS_FENI8087_NOP, X86_INS_ENDING, // mark the end of the list of insn } x86_insn; //> Group of X86 instructions typedef enum x86_insn_group { X86_GRP_INVALID = 0, // = CS_GRP_INVALID //> Generic groups // all jump instructions (conditional+direct+indirect jumps) X86_GRP_JUMP, // = CS_GRP_JUMP // all call instructions X86_GRP_CALL, // = CS_GRP_CALL // all return instructions X86_GRP_RET, // = CS_GRP_RET // all interrupt instructions (int+syscall) X86_GRP_INT, // = CS_GRP_INT // all interrupt return instructions X86_GRP_IRET, // = CS_GRP_IRET // all privileged instructions X86_GRP_PRIVILEGE, // = CS_GRP_PRIVILEGE //> Architecture-specific groups X86_GRP_VM = 128, // all virtualization instructions (VT-x + AMD-V) X86_GRP_3DNOW, X86_GRP_AES, X86_GRP_ADX, X86_GRP_AVX, X86_GRP_AVX2, X86_GRP_AVX512, X86_GRP_BMI, X86_GRP_BMI2, X86_GRP_CMOV, X86_GRP_F16C, X86_GRP_FMA, X86_GRP_FMA4, X86_GRP_FSGSBASE, X86_GRP_HLE, X86_GRP_MMX, X86_GRP_MODE32, X86_GRP_MODE64, X86_GRP_RTM, X86_GRP_SHA, X86_GRP_SSE1, X86_GRP_SSE2, X86_GRP_SSE3, X86_GRP_SSE41, X86_GRP_SSE42, X86_GRP_SSE4A, X86_GRP_SSSE3, X86_GRP_PCLMUL, X86_GRP_XOP, X86_GRP_CDI, X86_GRP_ERI, X86_GRP_TBM, X86_GRP_16BITMODE, X86_GRP_NOT64BITMODE, X86_GRP_SGX, X86_GRP_DQI, X86_GRP_BWI, X86_GRP_PFI, X86_GRP_VLX, X86_GRP_SMAP, X86_GRP_NOVLX, X86_GRP_ENDING } x86_insn_group; #ifdef __cplusplus } #endif #endif

{ "language": "Assembly" }

/* SPDX-License-Identifier: BSD-2-Clause */ /* * Copyright (c) 2019, Linaro Limited */ #include <asm.S> /* * This function is the bottom of the user call stack. Mark it as such so that * the unwinding code won't try to go further down. * We need an assembly wrapper because Clang does not accept asm(".cantunwind") * in a C function: * * user_ta_header.c:44:6: error: .fnstart must precede .cantunwind directive * asm(".cantunwind"); * ^ */ FUNC __ta_entry, : UNWIND( .cantunwind) bl __ta_entry_c END_FUNC __ta_entry

{ "language": "Assembly" }

/* * Copyright 2015 The LibYuv Project Authors. All rights reserved. * * Use of this source code is governed by a BSD-style license * that can be found in the LICENSE file in the root of the source * tree. An additional intellectual property rights grant can be found * in the file PATENTS. All contributing project authors may * be found in the AUTHORS file in the root of the source tree. */ #include "libyuv/row.h" #include "libyuv/rotate_row.h" #ifdef __cplusplus namespace libyuv { extern "C" { #endif // This module is for GCC x86 and x64. #if !defined(LIBYUV_DISABLE_X86) && \ (defined(__x86_64__) || (defined(__i386__) && !defined(_MSC_VER))) // Transpose 8x8. 32 or 64 bit, but not NaCL for 64 bit. #if defined(HAS_TRANSPOSEWX8_SSSE3) void TransposeWx8_SSSE3(const uint8* src, int src_stride, uint8* dst, int dst_stride, int width) { asm volatile ( // Read in the data from the source pointer. // First round of bit swap. LABELALIGN "1: \n" "movq (%0),%%xmm0 \n" "movq (%0,%3),%%xmm1 \n" "lea (%0,%3,2),%0 \n" "punpcklbw %%xmm1,%%xmm0 \n" "movq (%0),%%xmm2 \n" "movdqa %%xmm0,%%xmm1 \n" "palignr $0x8,%%xmm1,%%xmm1 \n" "movq (%0,%3),%%xmm3 \n" "lea (%0,%3,2),%0 \n" "punpcklbw %%xmm3,%%xmm2 \n" "movdqa %%xmm2,%%xmm3 \n" "movq (%0),%%xmm4 \n" "palignr $0x8,%%xmm3,%%xmm3 \n" "movq (%0,%3),%%xmm5 \n" "lea (%0,%3,2),%0 \n" "punpcklbw %%xmm5,%%xmm4 \n" "movdqa %%xmm4,%%xmm5 \n" "movq (%0),%%xmm6 \n" "palignr $0x8,%%xmm5,%%xmm5 \n" "movq (%0,%3),%%xmm7 \n" "lea (%0,%3,2),%0 \n" "punpcklbw %%xmm7,%%xmm6 \n" "neg %3 \n" "movdqa %%xmm6,%%xmm7 \n" "lea 0x8(%0,%3,8),%0 \n" "palignr $0x8,%%xmm7,%%xmm7 \n" "neg %3 \n" // Second round of bit swap. "punpcklwd %%xmm2,%%xmm0 \n" "punpcklwd %%xmm3,%%xmm1 \n" "movdqa %%xmm0,%%xmm2 \n" "movdqa %%xmm1,%%xmm3 \n" "palignr $0x8,%%xmm2,%%xmm2 \n" "palignr $0x8,%%xmm3,%%xmm3 \n" "punpcklwd %%xmm6,%%xmm4 \n" "punpcklwd %%xmm7,%%xmm5 \n" "movdqa %%xmm4,%%xmm6 \n" "movdqa %%xmm5,%%xmm7 \n" "palignr $0x8,%%xmm6,%%xmm6 \n" "palignr $0x8,%%xmm7,%%xmm7 \n" // Third round of bit swap. // Write to the destination pointer. "punpckldq %%xmm4,%%xmm0 \n" "movq %%xmm0,(%1) \n" "movdqa %%xmm0,%%xmm4 \n" "palignr $0x8,%%xmm4,%%xmm4 \n" "movq %%xmm4,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "punpckldq %%xmm6,%%xmm2 \n" "movdqa %%xmm2,%%xmm6 \n" "movq %%xmm2,(%1) \n" "palignr $0x8,%%xmm6,%%xmm6 \n" "punpckldq %%xmm5,%%xmm1 \n" "movq %%xmm6,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "movdqa %%xmm1,%%xmm5 \n" "movq %%xmm1,(%1) \n" "palignr $0x8,%%xmm5,%%xmm5 \n" "movq %%xmm5,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "punpckldq %%xmm7,%%xmm3 \n" "movq %%xmm3,(%1) \n" "movdqa %%xmm3,%%xmm7 \n" "palignr $0x8,%%xmm7,%%xmm7 \n" "sub $0x8,%2 \n" "movq %%xmm7,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "jg 1b \n" : "+r"(src), // %0 "+r"(dst), // %1 "+r"(width) // %2 : "r"((intptr_t)(src_stride)), // %3 "r"((intptr_t)(dst_stride)) // %4 : "memory", "cc", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" ); } #endif // defined(HAS_TRANSPOSEWX8_SSSE3) // Transpose 16x8. 64 bit #if defined(HAS_TRANSPOSEWX8_FAST_SSSE3) void TransposeWx8_Fast_SSSE3(const uint8* src, int src_stride, uint8* dst, int dst_stride, int width) { asm volatile ( // Read in the data from the source pointer. // First round of bit swap. LABELALIGN "1: \n" "movdqu (%0),%%xmm0 \n" "movdqu (%0,%3),%%xmm1 \n" "lea (%0,%3,2),%0 \n" "movdqa %%xmm0,%%xmm8 \n" "punpcklbw %%xmm1,%%xmm0 \n" "punpckhbw %%xmm1,%%xmm8 \n" "movdqu (%0),%%xmm2 \n" "movdqa %%xmm0,%%xmm1 \n" "movdqa %%xmm8,%%xmm9 \n" "palignr $0x8,%%xmm1,%%xmm1 \n" "palignr $0x8,%%xmm9,%%xmm9 \n" "movdqu (%0,%3),%%xmm3 \n" "lea (%0,%3,2),%0 \n" "movdqa %%xmm2,%%xmm10 \n" "punpcklbw %%xmm3,%%xmm2 \n" "punpckhbw %%xmm3,%%xmm10 \n" "movdqa %%xmm2,%%xmm3 \n" "movdqa %%xmm10,%%xmm11 \n" "movdqu (%0),%%xmm4 \n" "palignr $0x8,%%xmm3,%%xmm3 \n" "palignr $0x8,%%xmm11,%%xmm11 \n" "movdqu (%0,%3),%%xmm5 \n" "lea (%0,%3,2),%0 \n" "movdqa %%xmm4,%%xmm12 \n" "punpcklbw %%xmm5,%%xmm4 \n" "punpckhbw %%xmm5,%%xmm12 \n" "movdqa %%xmm4,%%xmm5 \n" "movdqa %%xmm12,%%xmm13 \n" "movdqu (%0),%%xmm6 \n" "palignr $0x8,%%xmm5,%%xmm5 \n" "palignr $0x8,%%xmm13,%%xmm13 \n" "movdqu (%0,%3),%%xmm7 \n" "lea (%0,%3,2),%0 \n" "movdqa %%xmm6,%%xmm14 \n" "punpcklbw %%xmm7,%%xmm6 \n" "punpckhbw %%xmm7,%%xmm14 \n" "neg %3 \n" "movdqa %%xmm6,%%xmm7 \n" "movdqa %%xmm14,%%xmm15 \n" "lea 0x10(%0,%3,8),%0 \n" "palignr $0x8,%%xmm7,%%xmm7 \n" "palignr $0x8,%%xmm15,%%xmm15 \n" "neg %3 \n" // Second round of bit swap. "punpcklwd %%xmm2,%%xmm0 \n" "punpcklwd %%xmm3,%%xmm1 \n" "movdqa %%xmm0,%%xmm2 \n" "movdqa %%xmm1,%%xmm3 \n" "palignr $0x8,%%xmm2,%%xmm2 \n" "palignr $0x8,%%xmm3,%%xmm3 \n" "punpcklwd %%xmm6,%%xmm4 \n" "punpcklwd %%xmm7,%%xmm5 \n" "movdqa %%xmm4,%%xmm6 \n" "movdqa %%xmm5,%%xmm7 \n" "palignr $0x8,%%xmm6,%%xmm6 \n" "palignr $0x8,%%xmm7,%%xmm7 \n" "punpcklwd %%xmm10,%%xmm8 \n" "punpcklwd %%xmm11,%%xmm9 \n" "movdqa %%xmm8,%%xmm10 \n" "movdqa %%xmm9,%%xmm11 \n" "palignr $0x8,%%xmm10,%%xmm10 \n" "palignr $0x8,%%xmm11,%%xmm11 \n" "punpcklwd %%xmm14,%%xmm12 \n" "punpcklwd %%xmm15,%%xmm13 \n" "movdqa %%xmm12,%%xmm14 \n" "movdqa %%xmm13,%%xmm15 \n" "palignr $0x8,%%xmm14,%%xmm14 \n" "palignr $0x8,%%xmm15,%%xmm15 \n" // Third round of bit swap. // Write to the destination pointer. "punpckldq %%xmm4,%%xmm0 \n" "movq %%xmm0,(%1) \n" "movdqa %%xmm0,%%xmm4 \n" "palignr $0x8,%%xmm4,%%xmm4 \n" "movq %%xmm4,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "punpckldq %%xmm6,%%xmm2 \n" "movdqa %%xmm2,%%xmm6 \n" "movq %%xmm2,(%1) \n" "palignr $0x8,%%xmm6,%%xmm6 \n" "punpckldq %%xmm5,%%xmm1 \n" "movq %%xmm6,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "movdqa %%xmm1,%%xmm5 \n" "movq %%xmm1,(%1) \n" "palignr $0x8,%%xmm5,%%xmm5 \n" "movq %%xmm5,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "punpckldq %%xmm7,%%xmm3 \n" "movq %%xmm3,(%1) \n" "movdqa %%xmm3,%%xmm7 \n" "palignr $0x8,%%xmm7,%%xmm7 \n" "movq %%xmm7,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "punpckldq %%xmm12,%%xmm8 \n" "movq %%xmm8,(%1) \n" "movdqa %%xmm8,%%xmm12 \n" "palignr $0x8,%%xmm12,%%xmm12 \n" "movq %%xmm12,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "punpckldq %%xmm14,%%xmm10 \n" "movdqa %%xmm10,%%xmm14 \n" "movq %%xmm10,(%1) \n" "palignr $0x8,%%xmm14,%%xmm14 \n" "punpckldq %%xmm13,%%xmm9 \n" "movq %%xmm14,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "movdqa %%xmm9,%%xmm13 \n" "movq %%xmm9,(%1) \n" "palignr $0x8,%%xmm13,%%xmm13 \n" "movq %%xmm13,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "punpckldq %%xmm15,%%xmm11 \n" "movq %%xmm11,(%1) \n" "movdqa %%xmm11,%%xmm15 \n" "palignr $0x8,%%xmm15,%%xmm15 \n" "sub $0x10,%2 \n" "movq %%xmm15,(%1,%4) \n" "lea (%1,%4,2),%1 \n" "jg 1b \n" : "+r"(src), // %0 "+r"(dst), // %1 "+r"(width) // %2 : "r"((intptr_t)(src_stride)), // %3 "r"((intptr_t)(dst_stride)) // %4 : "memory", "cc", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15" ); } #endif // defined(HAS_TRANSPOSEWX8_FAST_SSSE3) // Transpose UV 8x8. 64 bit. #if defined(HAS_TRANSPOSEUVWX8_SSE2) void TransposeUVWx8_SSE2(const uint8* src, int src_stride, uint8* dst_a, int dst_stride_a, uint8* dst_b, int dst_stride_b, int width) { asm volatile ( // Read in the data from the source pointer. // First round of bit swap. LABELALIGN "1: \n" "movdqu (%0),%%xmm0 \n" "movdqu (%0,%4),%%xmm1 \n" "lea (%0,%4,2),%0 \n" "movdqa %%xmm0,%%xmm8 \n" "punpcklbw %%xmm1,%%xmm0 \n" "punpckhbw %%xmm1,%%xmm8 \n" "movdqa %%xmm8,%%xmm1 \n" "movdqu (%0),%%xmm2 \n" "movdqu (%0,%4),%%xmm3 \n" "lea (%0,%4,2),%0 \n" "movdqa %%xmm2,%%xmm8 \n" "punpcklbw %%xmm3,%%xmm2 \n" "punpckhbw %%xmm3,%%xmm8 \n" "movdqa %%xmm8,%%xmm3 \n" "movdqu (%0),%%xmm4 \n" "movdqu (%0,%4),%%xmm5 \n" "lea (%0,%4,2),%0 \n" "movdqa %%xmm4,%%xmm8 \n" "punpcklbw %%xmm5,%%xmm4 \n" "punpckhbw %%xmm5,%%xmm8 \n" "movdqa %%xmm8,%%xmm5 \n" "movdqu (%0),%%xmm6 \n" "movdqu (%0,%4),%%xmm7 \n" "lea (%0,%4,2),%0 \n" "movdqa %%xmm6,%%xmm8 \n" "punpcklbw %%xmm7,%%xmm6 \n" "neg %4 \n" "lea 0x10(%0,%4,8),%0 \n" "punpckhbw %%xmm7,%%xmm8 \n" "movdqa %%xmm8,%%xmm7 \n" "neg %4 \n" // Second round of bit swap. "movdqa %%xmm0,%%xmm8 \n" "movdqa %%xmm1,%%xmm9 \n" "punpckhwd %%xmm2,%%xmm8 \n" "punpckhwd %%xmm3,%%xmm9 \n" "punpcklwd %%xmm2,%%xmm0 \n" "punpcklwd %%xmm3,%%xmm1 \n" "movdqa %%xmm8,%%xmm2 \n" "movdqa %%xmm9,%%xmm3 \n" "movdqa %%xmm4,%%xmm8 \n" "movdqa %%xmm5,%%xmm9 \n" "punpckhwd %%xmm6,%%xmm8 \n" "punpckhwd %%xmm7,%%xmm9 \n" "punpcklwd %%xmm6,%%xmm4 \n" "punpcklwd %%xmm7,%%xmm5 \n" "movdqa %%xmm8,%%xmm6 \n" "movdqa %%xmm9,%%xmm7 \n" // Third round of bit swap. // Write to the destination pointer. "movdqa %%xmm0,%%xmm8 \n" "punpckldq %%xmm4,%%xmm0 \n" "movlpd %%xmm0,(%1) \n" // Write back U channel "movhpd %%xmm0,(%2) \n" // Write back V channel "punpckhdq %%xmm4,%%xmm8 \n" "movlpd %%xmm8,(%1,%5) \n" "lea (%1,%5,2),%1 \n" "movhpd %%xmm8,(%2,%6) \n" "lea (%2,%6,2),%2 \n" "movdqa %%xmm2,%%xmm8 \n" "punpckldq %%xmm6,%%xmm2 \n" "movlpd %%xmm2,(%1) \n" "movhpd %%xmm2,(%2) \n" "punpckhdq %%xmm6,%%xmm8 \n" "movlpd %%xmm8,(%1,%5) \n" "lea (%1,%5,2),%1 \n" "movhpd %%xmm8,(%2,%6) \n" "lea (%2,%6,2),%2 \n" "movdqa %%xmm1,%%xmm8 \n" "punpckldq %%xmm5,%%xmm1 \n" "movlpd %%xmm1,(%1) \n" "movhpd %%xmm1,(%2) \n" "punpckhdq %%xmm5,%%xmm8 \n" "movlpd %%xmm8,(%1,%5) \n" "lea (%1,%5,2),%1 \n" "movhpd %%xmm8,(%2,%6) \n" "lea (%2,%6,2),%2 \n" "movdqa %%xmm3,%%xmm8 \n" "punpckldq %%xmm7,%%xmm3 \n" "movlpd %%xmm3,(%1) \n" "movhpd %%xmm3,(%2) \n" "punpckhdq %%xmm7,%%xmm8 \n" "sub $0x8,%3 \n" "movlpd %%xmm8,(%1,%5) \n" "lea (%1,%5,2),%1 \n" "movhpd %%xmm8,(%2,%6) \n" "lea (%2,%6,2),%2 \n" "jg 1b \n" : "+r"(src), // %0 "+r"(dst_a), // %1 "+r"(dst_b), // %2 "+r"(width) // %3 : "r"((intptr_t)(src_stride)), // %4 "r"((intptr_t)(dst_stride_a)), // %5 "r"((intptr_t)(dst_stride_b)) // %6 : "memory", "cc", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8", "xmm9" ); } #endif // defined(HAS_TRANSPOSEUVWX8_SSE2) #endif // defined(__x86_64__) || defined(__i386__) #ifdef __cplusplus } // extern "C" } // namespace libyuv #endif

{ "language": "Assembly" }

.code16 .globl code16_start .globl code16_end CS_SEG = 0xf code16_start: .globl code16_func1 /* basic test */ code16_func1 = . - code16_start mov $1, %eax data32 lret /* test push/pop in 16 bit mode */ .globl code16_func2 code16_func2 = . - code16_start xor %eax, %eax mov $0x12345678, %ebx movl %esp, %ecx push %bx subl %esp, %ecx pop %ax data32 lret /* test various jmp opcodes */ .globl code16_func3 code16_func3 = . - code16_start jmp 1f nop 1: mov $4, %eax mov $0x12345678, %ebx xor %bx, %bx jz 2f add $2, %ax 2: call myfunc lcall $CS_SEG, $(myfunc2 - code16_start) ljmp $CS_SEG, $(myjmp1 - code16_start) myjmp1_next: cs lcall *myfunc2_addr - code16_start cs ljmp *myjmp2_addr - code16_start myjmp2_next: data32 lret myfunc2_addr: .short myfunc2 - code16_start .short CS_SEG myjmp2_addr: .short myjmp2 - code16_start .short CS_SEG myjmp1: add $8, %ax jmp myjmp1_next myjmp2: add $16, %ax jmp myjmp2_next myfunc: add $1, %ax ret myfunc2: add $4, %ax lret code16_end:

{ "language": "Assembly" }

### FILE="Main.annotation" ## Copyright: Public domain. ## Filename: LEM_GEOMETRY.agc ## Purpose: Part of the reconstructed source code for LMY99 Rev 0, ## otherwise known as Luminary Rev 99, the second release ## of the Apollo Guidance Computer (AGC) software for Apollo 11. ## It differs from LMY99 Rev 1 (the flown version) only in the ## placement of a single label. The corrections shown here have ## been verified to have the same bank checksums as AGC developer ## Allan Klumpp's copy of Luminary Rev 99, and so are believed ## to be accurate. This file is intended to be a faithful ## recreation, except that the code format has been changed to ## conform to the requirements of the yaYUL assembler rather than ## the original YUL assembler. ## ## Assembler: yaYUL ## Contact: Ron Burkey <[email protected]>. ## Website: www.ibiblio.org/apollo. ## Pages: 320-325 ## Mod history: 2009-05-16 RSB Adapted from the corresponding ## Luminary131 file, using page ## images from Luminary 1A. ## 2016-12-13 RSB Proofed text comments with octopus/ProoferComments ## and corrected the errors found. ## 2017-03-07 RSB Fixed comment-text error noticed while proofing ## Luminary 116. ## 2017-08-01 MAS Created from LMY99 Rev 1. ## This source code has been transcribed or otherwise adapted from ## digitized images of a hardcopy from the MIT Museum. The digitization ## was performed by Paul Fjeld, and arranged for by Deborah Douglas of ## the Museum. Many thanks to both. The images (with suitable reduction ## in storage size and consequent reduction in image quality as well) are ## available online at www.ibiblio.org/apollo. If for some reason you ## find that the images are illegible, contact me at [email protected] ## about getting access to the (much) higher-quality images which Paul ## actually created. ## ## The code has been modified to match LMY99 Revision 0, otherwise ## known as Luminary Revision 99, the Apollo 11 software release preceeding ## the listing from which it was transcribed. It has been verified to ## contain the same bank checksums as AGC developer Allan Klumpp's listing ## of Luminary Revision 99 (for which we do not have scans). ## ## Notations on Allan Klumpp's listing read, in part: ## ## ASSEMBLE REVISION 099 OF AGC PROGRAM LUMINARY BY NASA 2021112-51 ## Page 320 BANK 23 SETLOC LEMGEOM BANK SBANK= LOWSUPER EBANK= XSM # THESE TWO ROUTINES COMPUTE THE ACTUAL STATE VECTOR FOR LM,CSM BY ADDING # THE CONIC R,V AND THE DEVIATIONS R,V. THE STATE VECTORS ARE CONVERTED TO # METERS B-29 AND METERS/CSEC B-7 AND STORED APPROPRIATELY IN RN,VN OR # R-OTHER,V-OTHER FOR DOWNLINK. THE ROUTINES NAMES ARE SWITCHED IN THE # OTHER VEHICLES COMPUTER. # # INPUT # STATE VECTOR IN TEMPORARY STORAGE AREA # IF STATE VECTOR IS SCALED POS B27 AND VEL B5 # SET X2 TO +2 # IF STATE VECTOR IS SCALED POS B29 AND VEL B7 # SET X2 TO 0 # # OUTPUT # R(T) IN RN, V(T) IN VN, T IN PIPTIME # OR # R(T) IN R-OTHER, V(T) IN V-OTHER (T IS DEFINED BY T-OTHER) COUNT* $$/GEOM SVDWN2 BOF RVQ # SW=1=AVETOMID DOING W-MATRIX INTEG. AVEMIDSW +1 VLOAD VSL* TDELTAV 0 -7,2 VAD VSL* RCV 0,2 STOVL RN TNUV VSL* VAD 0 -4,2 VCV VSL* 0,2 STODL VN TET STORE PIPTIME RVQ ## Page 321 SVDWN1 VLOAD VSL* TDELTAV 0 -7,2 VAD VSL* RCV 0,2 STOVL R-OTHER TNUV VSL* VAD 0 -4,2 VCV VSL* 0,2 STORE V-OTHER RVQ ## Page 322 # THE FOLLOWING ROUTINE TAKES A HALF UNIT TARGET VECTOR REFERRED TO NAV BASE COORDINATES AND FINDS BOTH # GIMBAL ORIENTATIONS AT WHICH THE RR MIGHT SIGHT THE TARGET. THE GIMBAL ANGLES CORRESPONDING TO THE PRESENT MODE # ARE LEFT IN MODEA AND THOSE WHICH WOULD BE USED AFTER A REMODE IN MODEB. THIS ROUTINE ASSUMES MODE 1 IS TRUNNION # ANGLE LESS THAN 90 DEGS IN ABS VALUE WITH ARBITRARY SHAFT, WITH A CORRESPONDING DEFINITION FOR MODE 2. MODE # SELECTION AND LIMIT CHECKING ARE DONE ELSEWHERE. # # THE MODE 1 CONFIGURATION IS CALCULATED FROM THE VECTOR AND THEN MODE 2 IS FOUND USING THE RELATIONS # # S(2) = 180 + S(1) # T(2) = 180 - T(1) # # THE VECTOR ARRIVES IN MPAC WHERE TRG*SMNG OR *SMNB* WILL HAVE LEFT IT. RRANGLES STORE 32D DLOAD DCOMP # SINCE WE WILL FIND THE MODE 1 SHAFT 34D # ANGLE LATER, WE CAN FIND THE MODE 1 SETPD ASIN # TRUNNION BY SIMPLY TAKING THE ARCSIN OF 0 # THE Y COMPONENT, THE ASIN GIVING AN PUSH BDSU # ANSWER WHOSE ABS VAL IS LESS THAN 90 DEG LODPHALF STODL 4 # MODE 2 TRUNNION TO 4. LO6ZEROS STOVL 34D # UNIT THE PROJECTION OF THE VECTOR 32D # IN THE X-Z PLANE UNIT BOVB # IF OVERFLOW, TARGET VECTOR IS ALONG Y LUNDESCH # CALL FOR MANEUVER UNLESS ON LUNAR SURF STODL 32D # PROJECTION VECTOR. 32D SR1 STQ S2 STODL SINTH # USE ARCTRIG SINCE SHAFT COULD BE ARB. 36D SR1 STCALL COSTH ARCTRIG ## Page 323 PUSH DAD # MODE 1 SHAFT TO 2. LODPHALF STOVL 6 4 RTB # FIND MODE 2 CDU ANGLES. 2V1STO2S STOVL MODEB 0 RTB # MODE 1 ANGLES TO MODE A. 2V1STO2S STORE MODEA EXIT CS RADMODES # SWAP MODEA AND MODEB IF RR IN MODE 2. MASK ANTENBIT CCS A TCF +4 DXCH MODEA DXCH MODEB DXCH MODEA TC INTPRET GOTO S2 ## Page 324 # GIVEN RR TRUNNION AND SHAFT (T,S) IN TANGNB,+1, FIND THE ASSOCIATED # LINE OF SIGHT IN NAV BASE AXES. THE HALF UNIT VECTOR, .5(SIN(S)COS(T), # -SIN(T),COS(S)COS(T)) IS LEFT IN MPAC AND 32D. SETLOC INFLIGHT BANK COUNT* $$/GEOM RRNB SLOAD RTB TANGNB CDULOGIC SETPD PUSH # TRUNNION ANGLE TO 0 0 SIN DCOMP STODL 34D # Y COMPONENT COS PUSH # .5 COS(T) TO 0 SLOAD RTB TANGNB +1 CDULOGIC RRNB1 PUSH COS # SHAFT ANGLE TO 2 DMP SL1 0 STODL 36D # Z COMPONENT SIN DMP SL1 STOVL 32D 32D RVQ # THIS ENTRY TO RRNB REQUIRES THE TRUNNION AND SHAFT ANGLES IN MPAC AND MPAC +1 RESPECTIVELY RRNBMPAC STODL 20D # SAVE SHAFT CDU IN 21. MPAC # SET MODE TO DP. (THE PRECEEDING STORE # MAY BE DP, TP OR VECTOR.) RTB SETPD CDULOGIC 0 PUSH SIN # TRUNNION ANGLE TO 0 DCOMP STODL 34D # Y COMPONENT COS PUSH # .5COS(T) TO 0 SLOAD RTB # PICK UP CDU'S. 21D CDULOGIC GOTO RRNB1 ## Page 325 ## <br>This page has nothing on it.

{ "language": "Assembly" }

/* * Copyright (C) 2010 Google Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY APPLE AND ITS CONTRIBUTORS "AS IS" AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL APPLE OR ITS CONTRIBUTORS BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef OptionsObject_h #define OptionsObject_h // FIXME: Implement. #endif // OptionsObject_h

{ "language": "Assembly" }

.text .globl target .type target, @function #! file-offset 0 #! rip-offset 0 #! capacity 5 bytes # Text # Line RIP Bytes Opcode .target: # 0 0 OPC=<label> vmovsldup %xmm2, %xmm12 # 1 0 4 OPC=vmovsldup_xmm_xmm movdqa %xmm12, %xmm1 # 2 0x4 5 OPC=movdqa_xmm_xmm retq # 3 0x9 1 OPC=retq .size target, .-target

{ "language": "Assembly" }

#------------------------------------------------------------------------------ # $File: bsdi,v 1.7 2014/03/29 15:40:34 christos Exp $ # bsdi: file(1) magic for BSD/OS (from BSDI) objects # Some object/executable formats use the same magic numbers as are used # in other OSes; those are handled by entries in aout. # 0 lelong 0314 386 compact demand paged pure executable >16 lelong >0 not stripped >32 byte 0x6a (uses shared libs) # same as in SunOS 4.x, except for static shared libraries 0 belong&077777777 0600413 SPARC demand paged >0 byte &0x80 >>20 belong <4096 shared library >>20 belong =4096 dynamically linked executable >>20 belong >4096 dynamically linked executable >0 byte ^0x80 executable >16 belong >0 not stripped >36 belong 0xb4100001 (uses shared libs) 0 belong&077777777 0600410 SPARC pure >0 byte &0x80 dynamically linked executable >0 byte ^0x80 executable >16 belong >0 not stripped >36 belong 0xb4100001 (uses shared libs) 0 belong&077777777 0600407 SPARC >0 byte &0x80 dynamically linked executable >0 byte ^0x80 executable >16 belong >0 not stripped >36 belong 0xb4100001 (uses shared libs)

{ "language": "Assembly" }

// RUN: %clang -target x86_64-apple-darwin -fsyntax-only %s -no-integrated-as -### 2>&1 | FileCheck %s // Test that the autolinking feature is disabled with *not* using the // integrated assembler. // CHECK: -fno-autolink

{ "language": "Assembly" }

namespace N { struct A { }; namespace M { struct C { }; }; } namespace N { struct B { }; } N:: // RUN: %clang_cc1 -fsyntax-only -code-completion-at=%s:12:4 %s -o - | FileCheck -check-prefix=CHECK-CC1 %s // CHECK-CC1: A // CHECK-CC1: B // CHECK-CC1: M

{ "language": "Assembly" }

; RUN: llc %s -filetype=obj -o - | llvm-dwarfdump -v - | FileCheck %s ; Test that DW_OP_piece is emitted for constants. ; ; // Generated from: ; typedef struct { int a, b; } I; ; I i(int i) { ; I r = {i, 0}; ; return r; ; } ; ; typedef struct { float a, b; } F; ; F f(float f) { ; F r = {f, 0}; ; return r; ; } ; CHECK: .debug_info contents: ; CHECK: DW_TAG_subprogram ; CHECK: DW_AT_name {{.*}} "i" ; CHECK: DW_TAG_variable ; CHECK-NEXT: DW_AT_location {{.*}} ([[I:.*]] ; CHECK-NEXT: [{{.*}}, {{.*}}): DW_OP_reg5 RDI, DW_OP_piece 0x4, DW_OP_lit0, DW_OP_stack_value, DW_OP_piece 0x4) ; CHECK-NEXT: DW_AT_name {{.*}} "r" ; ; CHECK: DW_TAG_subprogram ; CHECK: DW_AT_name {{.*}} "f" ; CHECK: DW_TAG_variable ; CHECK-NEXT: DW_AT_location {{.*}} ([[F:.*]] ; CHECK-NEXT: [{{.*}}, {{.*}}): DW_OP_reg17 XMM0, DW_OP_piece 0x4, DW_OP_lit0, DW_OP_stack_value, DW_OP_piece 0x4 ; CHECK-NEXT: [{{.*}}, {{.*}}): DW_OP_piece 0x4, DW_OP_lit0, DW_OP_stack_value, DW_OP_piece 0x4) ; CHECK-NEXT: DW_AT_name {{.*}} "r" ; ; CHECK: .debug_loc contents: ; CHECK: [[I]]: ; CHECK-NEXT: [{{.*}}, {{.*}}): DW_OP_reg5 RDI, DW_OP_piece 0x4, DW_OP_lit0, DW_OP_stack_value, DW_OP_piece 0x4 ; CHECK: [[F]]: ; CHECK-NEXT: [{{.*}}, {{.*}}): DW_OP_reg17 XMM0, DW_OP_piece 0x4, DW_OP_lit0, DW_OP_stack_value, DW_OP_piece 0x4 source_filename = "stack-value-piece.c" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.12.0" %struct.I = type { i32, i32 } %struct.F = type { float, float } ; Function Attrs: nounwind readnone ssp uwtable define i64 @i(i32 %i) local_unnamed_addr #0 !dbg !7 { entry: tail call void @llvm.dbg.value(metadata i32 %i, metadata !18, metadata !22), !dbg !21 tail call void @llvm.dbg.value(metadata i32 0, metadata !18, metadata !23), !dbg !21 %retval.sroa.0.0.insert.ext = zext i32 %i to i64, !dbg !24 ret i64 %retval.sroa.0.0.insert.ext, !dbg !24 } ; Function Attrs: nounwind readnone declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 ; Function Attrs: nounwind readnone ssp uwtable define <2 x float> @f(float %f) local_unnamed_addr #0 !dbg !25 { entry: tail call void @llvm.dbg.value(metadata float %f, metadata !36, metadata !22), !dbg !38 tail call void @llvm.dbg.value(metadata float 0.000000e+00, metadata !36, metadata !23), !dbg !38 %retval.sroa.0.0.vec.insert = insertelement <2 x float> undef, float %f, i32 0, !dbg !39 %retval.sroa.0.4.vec.insert = insertelement <2 x float> %retval.sroa.0.0.vec.insert, float 0.000000e+00, i32 1, !dbg !39 ret <2 x float> %retval.sroa.0.4.vec.insert, !dbg !40 } ; Function Attrs: nounwind readnone declare void @llvm.dbg.value(metadata, metadata, metadata) #1 attributes #0 = { nounwind readnone ssp uwtable } attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3, !4, !5} !llvm.ident = !{!6} !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 4.0.0 (trunk 285655) (llvm/trunk 285654)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) !1 = !DIFile(filename: "stack-value-piece.c", directory: "/") !2 = !{} !3 = !{i32 2, !"Dwarf Version", i32 4} !4 = !{i32 2, !"Debug Info Version", i32 3} !5 = !{i32 1, !"PIC Level", i32 2} !6 = !{!"clang version 4.0.0 (trunk 285655) (llvm/trunk 285654)"} !7 = distinct !DISubprogram(name: "i", scope: !1, file: !1, line: 2, type: !8, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0) !8 = !DISubroutineType(types: !9) !9 = !{!10, !14} !10 = !DIDerivedType(tag: DW_TAG_typedef, name: "I", file: !1, line: 1, baseType: !11) !11 = distinct !DICompositeType(tag: DW_TAG_structure_type, file: !1, line: 1, size: 64, elements: !12) !12 = !{!13, !15} !13 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !11, file: !1, line: 1, baseType: !14, size: 32) !14 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) !15 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !11, file: !1, line: 1, baseType: !14, size: 32, offset: 32) !18 = !DILocalVariable(name: "r", scope: !7, file: !1, line: 3, type: !10) !19 = !DIExpression() !20 = !DILocation(line: 2, column: 9, scope: !7) !21 = !DILocation(line: 3, column: 5, scope: !7) !22 = !DIExpression(DW_OP_LLVM_fragment, 0, 32) !23 = !DIExpression(DW_OP_LLVM_fragment, 32, 32) !24 = !DILocation(line: 5, column: 1, scope: !7) !25 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 8, type: !26, isLocal: false, isDefinition: true, scopeLine: 8, flags: DIFlagPrototyped, isOptimized: true, unit: !0) !26 = !DISubroutineType(types: !27) !27 = !{!28, !32} !28 = !DIDerivedType(tag: DW_TAG_typedef, name: "F", file: !1, line: 7, baseType: !29) !29 = distinct !DICompositeType(tag: DW_TAG_structure_type, file: !1, line: 7, size: 64, elements: !30) !30 = !{!31, !33} !31 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !29, file: !1, line: 7, baseType: !32, size: 32) !32 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float) !33 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !29, file: !1, line: 7, baseType: !32, size: 32, offset: 32) !36 = !DILocalVariable(name: "r", scope: !25, file: !1, line: 9, type: !28) !37 = !DILocation(line: 8, column: 11, scope: !25) !38 = !DILocation(line: 9, column: 5, scope: !25) !39 = !DILocation(line: 10, column: 10, scope: !25) !40 = !DILocation(line: 11, column: 1, scope: !25)

{ "language": "Assembly" }

BEGIN:VEVENT DTSTART :20001104T150000 DTEND :20001104T160000 END:VEVENT BEGIN:VEVENT DTSTART :20001104T153000 DTEND :20001104T163000 END:VEVENT BEGIN:VEVENT DTSTART :20001104T160000 DTEND :20001104T170000 END:VEVENT BEGIN:VEVENT DTSTART :20001104T163000 DTEND :20001104T173000 END:VEVENT BEGIN:VEVENT DTSTART :20001104T170000 DTEND :20001104T180000 END:VEVENT

{ "language": "Assembly" }

/***************************************************************** | | Neptune - Trust Anchors | | This file is automatically generated by a script, do not edit! | | Copyright (c) 2002-2010, Axiomatic Systems, LLC. | All rights reserved. | | Redistribution and use in source and binary forms, with or without | modification, are permitted provided that the following conditions are met: | * Redistributions of source code must retain the above copyright | notice, this list of conditions and the following disclaimer. | * Redistributions in binary form must reproduce the above copyright | notice, this list of conditions and the following disclaimer in the | documentation and/or other materials provided with the distribution. | * Neither the name of Axiomatic Systems nor the | names of its contributors may be used to endorse or promote products | derived from this software without specific prior written permission. | | THIS SOFTWARE IS PROVIDED BY AXIOMATIC SYSTEMS ''AS IS'' AND ANY | EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | DISCLAIMED. IN NO EVENT SHALL AXIOMATIC SYSTEMS BE LIABLE FOR ANY | DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ****************************************************************/ /* ApplicationCA - Japanese Government */ const unsigned char NptTlsTrustAnchor_Base_0132_Data[932] = { 0x30,0x82,0x03,0xa0,0x30,0x82,0x02,0x88 ,0xa0,0x03,0x02,0x01,0x02,0x02,0x01,0x31 ,0x30,0x0d,0x06,0x09,0x2a,0x86,0x48,0x86 ,0xf7,0x0d,0x01,0x01,0x05,0x05,0x00,0x30 ,0x43,0x31,0x0b,0x30,0x09,0x06,0x03,0x55 ,0x04,0x06,0x13,0x02,0x4a,0x50,0x31,0x1c ,0x30,0x1a,0x06,0x03,0x55,0x04,0x0a,0x13 ,0x13,0x4a,0x61,0x70,0x61,0x6e,0x65,0x73 ,0x65,0x20,0x47,0x6f,0x76,0x65,0x72,0x6e ,0x6d,0x65,0x6e,0x74,0x31,0x16,0x30,0x14 ,0x06,0x03,0x55,0x04,0x0b,0x13,0x0d,0x41 ,0x70,0x70,0x6c,0x69,0x63,0x61,0x74,0x69 ,0x6f,0x6e,0x43,0x41,0x30,0x1e,0x17,0x0d ,0x30,0x37,0x31,0x32,0x31,0x32,0x31,0x35 ,0x30,0x30,0x30,0x30,0x5a,0x17,0x0d,0x31 ,0x37,0x31,0x32,0x31,0x32,0x31,0x35,0x30 ,0x30,0x30,0x30,0x5a,0x30,0x43,0x31,0x0b ,0x30,0x09,0x06,0x03,0x55,0x04,0x06,0x13 ,0x02,0x4a,0x50,0x31,0x1c,0x30,0x1a,0x06 ,0x03,0x55,0x04,0x0a,0x13,0x13,0x4a,0x61 ,0x70,0x61,0x6e,0x65,0x73,0x65,0x20,0x47 ,0x6f,0x76,0x65,0x72,0x6e,0x6d,0x65,0x6e ,0x74,0x31,0x16,0x30,0x14,0x06,0x03,0x55 ,0x04,0x0b,0x13,0x0d,0x41,0x70,0x70,0x6c ,0x69,0x63,0x61,0x74,0x69,0x6f,0x6e,0x43 ,0x41,0x30,0x82,0x01,0x22,0x30,0x0d,0x06 ,0x09,0x2a,0x86,0x48,0x86,0xf7,0x0d,0x01 ,0x01,0x01,0x05,0x00,0x03,0x82,0x01,0x0f ,0x00,0x30,0x82,0x01,0x0a,0x02,0x82,0x01 ,0x01,0x00,0xa7,0x6d,0xe0,0x74,0x4e,0x87 ,0x8f,0xa5,0x06,0xde,0x68,0xa2,0xdb,0x86 ,0x99,0x4b,0x64,0x0d,0x71,0xf0,0x0a,0x05 ,0x9b,0x8e,0xaa,0xe1,0xcc,0x2e,0xd2,0x6a ,0x3b,0xc1,0x7a,0xb4,0x97,0x61,0x8d,0x8a ,0xbe,0xc6,0x9a,0x9c,0x06,0xb4,0x86,0x51 ,0xe4,0x37,0x0e,0x74,0x78,0x7e,0x5f,0x8a ,0x7f,0x94,0xa4,0xd7,0x47,0x08,0xfd,0x50 ,0x5a,0x56,0xe4,0x68,0xac,0x28,0x73,0xa0 ,0x7b,0xe9,0x7f,0x18,0x92,0x40,0x4f,0x2d ,0x9d,0xf5,0xae,0x44,0x48,0x73,0x36,0x06 ,0x9e,0x64,0x2c,0x3b,0x34,0x23,0xdb,0x5c ,0x26,0xe4,0x71,0x79,0x8f,0xd4,0x6e,0x79 ,0x22,0xb9,0x93,0xc1,0xca,0xcd,0xc1,0x56 ,0xed,0x88,0x6a,0xd7,0xa0,0x39,0x21,0x04 ,0x57,0x2c,0xa2,0xf5,0xbc,0x47,0x41,0x4f ,0x5e,0x34,0x22,0x95,0xb5,0x1f,0x29,0x6d ,0x5e,0x4a,0xf3,0x4d,0x72,0xbe,0x41,0x56 ,0x20,0x87,0xfc,0xe9,0x50,0x47,0xd7,0x30 ,0x14,0xee,0x5c,0x8c,0x55,0xba,0x59,0x8d ,0x87,0xfc,0x23,0xde,0x93,0xd0,0x04,0x8c ,0xfd,0xef,0x6d,0xbd,0xd0,0x7a,0xc9,0xa5 ,0x3a,0x6a,0x72,0x33,0xc6,0x4a,0x0d,0x05 ,0x17,0x2a,0x2d,0x7b,0xb1,0xa7,0xd8,0xd6 ,0xf0,0xbe,0xf4,0x3f,0xea,0x0e,0x28,0x6d ,0x41,0x61,0x23,0x76,0x78,0xc3,0xb8,0x65 ,0xa4,0xf3,0x5a,0xae,0xcc,0xc2,0xaa,0xd9 ,0xe7,0x58,0xde,0xb6,0x7e,0x9d,0x85,0x6e ,0x9f,0x2a,0x0a,0x6f,0x9f,0x03,0x29,0x30 ,0x97,0x28,0x1d,0xbc,0xb7,0xcf,0x54,0x29 ,0x4e,0x51,0x31,0xf9,0x27,0xb6,0x28,0x26 ,0xfe,0xa2,0x63,0xe6,0x41,0x16,0xf0,0x33 ,0x98,0x47,0x02,0x03,0x01,0x00,0x01,0xa3 ,0x81,0x9e,0x30,0x81,0x9b,0x30,0x1d,0x06 ,0x03,0x55,0x1d,0x0e,0x04,0x16,0x04,0x14 ,0x54,0x5a,0xcb,0x26,0x3f,0x71,0xcc,0x94 ,0x46,0x0d,0x96,0x53,0xea,0x6b,0x48,0xd0 ,0x93,0xfe,0x42,0x75,0x30,0x0e,0x06,0x03 ,0x55,0x1d,0x0f,0x01,0x01,0xff,0x04,0x04 ,0x03,0x02,0x01,0x06,0x30,0x59,0x06,0x03 ,0x55,0x1d,0x11,0x04,0x52,0x30,0x50,0xa4 ,0x4e,0x30,0x4c,0x31,0x0b,0x30,0x09,0x06 ,0x03,0x55,0x04,0x06,0x13,0x02,0x4a,0x50 ,0x31,0x18,0x30,0x16,0x06,0x03,0x55,0x04 ,0x0a,0x0c,0x0f,0xe6,0x97,0xa5,0xe6,0x9c ,0xac,0xe5,0x9b,0xbd,0xe6,0x94,0xbf,0xe5 ,0xba,0x9c,0x31,0x23,0x30,0x21,0x06,0x03 ,0x55,0x04,0x0b,0x0c,0x1a,0xe3,0x82,0xa2 ,0xe3,0x83,0x97,0xe3,0x83,0xaa,0xe3,0x82 ,0xb1,0xe3,0x83,0xbc,0xe3,0x82,0xb7,0xe3 ,0x83,0xa7,0xe3,0x83,0xb3,0x43,0x41,0x30 ,0x0f,0x06,0x03,0x55,0x1d,0x13,0x01,0x01 ,0xff,0x04,0x05,0x30,0x03,0x01,0x01,0xff ,0x30,0x0d,0x06,0x09,0x2a,0x86,0x48,0x86 ,0xf7,0x0d,0x01,0x01,0x05,0x05,0x00,0x03 ,0x82,0x01,0x01,0x00,0x39,0x6a,0x44,0x76 ,0x77,0x38,0x3a,0xec,0xa3,0x67,0x46,0x0f ,0xf9,0x8b,0x06,0xa8,0xfb,0x6a,0x90,0x31 ,0xce,0x7e,0xec,0xda,0xd1,0x89,0x7c,0x7a ,0xeb,0x2e,0x0c,0xbd,0x99,0x32,0xe7,0xb0 ,0x24,0xd6,0xc3,0xff,0xf5,0xb2,0x88,0x09 ,0x87,0x2c,0xe3,0x54,0xe1,0xa3,0xa6,0xb2 ,0x08,0x0b,0xc0,0x85,0xa8,0xc8,0xd2,0x9c ,0x71,0xf6,0x1d,0x9f,0x60,0xfc,0x38,0x33 ,0x13,0xe1,0x9e,0xdc,0x0b,0x5f,0xda,0x16 ,0x50,0x29,0x7b,0x2f,0x70,0x91,0x0f,0x99 ,0xba,0x34,0x34,0x8d,0x95,0x74,0xc5,0x7e ,0x78,0xa9,0x66,0x5d,0xbd,0xca,0x21,0x77 ,0x42,0x10,0xac,0x66,0x26,0x3d,0xde,0x91 ,0xab,0xfd,0x15,0xf0,0x6f,0xed,0x6c,0x5f ,0x10,0xf8,0xf3,0x16,0xf6,0x03,0x8a,0x8f ,0xa7,0x12,0x11,0x0c,0xcb,0xfd,0x3f,0x79 ,0xc1,0x9c,0xfd,0x62,0xee,0xa3,0xcf,0x54 ,0x0c,0xd1,0x2b,0x5f,0x17,0x3e,0xe3,0x3e ,0xbf,0xc0,0x2b,0x3e,0x09,0x9b,0xfe,0x88 ,0xa6,0x7e,0xb4,0x92,0x17,0xfc,0x23,0x94 ,0x81,0xbd,0x6e,0xa7,0xc5,0x8c,0xc2,0xeb ,0x11,0x45,0xdb,0xf8,0x41,0xc9,0x96,0x76 ,0xea,0x70,0x5f,0x79,0x12,0x6b,0xe4,0xa3 ,0x07,0x5a,0x05,0xef,0x27,0x49,0xcf,0x21 ,0x9f,0x8a,0x4c,0x09,0x70,0x66,0xa9,0x26 ,0xc1,0x2b,0x11,0x4e,0x33,0xd2,0x0e,0xfc ,0xd6,0x6c,0xd2,0x0e,0x32,0x64,0x68,0xff ,0xad,0x05,0x78,0x5f,0x03,0x1d,0xa8,0xe3 ,0x90,0xac,0x24,0xe0,0x0f,0x40,0xa7,0x4b ,0xae,0x8b,0x28,0xb7,0x82,0xca,0x18,0x07 ,0xe6,0xb7,0x5b,0x74,0xe9,0x20,0x19,0x7f ,0xb2,0x1b,0x89,0x54}; const unsigned int NptTlsTrustAnchor_Base_0132_Size = 932;

{ "language": "Assembly" }

Qualcomm MSM8998 TLMM block This binding describes the Top Level Mode Multiplexer block found in the MSM8998 platform. - compatible: Usage: required Value type: <string> Definition: must be "qcom,msm8998-pinctrl" - reg: Usage: required Value type: <prop-encoded-array> Definition: the base address and size of the TLMM register space. - interrupts: Usage: required Value type: <prop-encoded-array> Definition: should specify the TLMM summary IRQ. - interrupt-controller: Usage: required Value type: <none> Definition: identifies this node as an interrupt controller - #interrupt-cells: Usage: required Value type: <u32> Definition: must be 2. Specifying the pin number and flags, as defined in <dt-bindings/interrupt-controller/irq.h> - gpio-controller: Usage: required Value type: <none> Definition: identifies this node as a gpio controller - #gpio-cells: Usage: required Value type: <u32> Definition: must be 2. Specifying the pin number and flags, as defined in <dt-bindings/gpio/gpio.h> - gpio-ranges: Usage: required Definition: see ../gpio/gpio.txt - gpio-reserved-ranges: Usage: optional Definition: see ../gpio/gpio.txt Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. Please refer to pinctrl-bindings.txt in this directory for details of the common pinctrl bindings used by client devices, including the meaning of the phrase "pin configuration node". The pin configuration nodes act as a container for an arbitrary number of subnodes. Each of these subnodes represents some desired configuration for a pin, a group, or a list of pins or groups. This configuration can include the mux function to select on those pin(s)/group(s), and various pin configuration parameters, such as pull-up, drive strength, etc. PIN CONFIGURATION NODES: The name of each subnode is not important; all subnodes should be enumerated and processed purely based on their content. Each subnode only affects those parameters that are explicitly listed. In other words, a subnode that lists a mux function but no pin configuration parameters implies no information about any pin configuration parameters. Similarly, a pin subnode that describes a pullup parameter implies no information about e.g. the mux function. The following generic properties as defined in pinctrl-bindings.txt are valid to specify in a pin configuration subnode: - pins: Usage: required Value type: <string-array> Definition: List of gpio pins affected by the properties specified in this subnode. Valid pins are: gpio0-gpio149 Supports mux, bias and drive-strength sdc2_clk, sdc2_cmd, sdc2_data Supports bias and drive-strength ufs_reset Supports bias and drive-strength - function: Usage: required Value type: <string> Definition: Specify the alternative function to be configured for the specified pins. Functions are only valid for gpio pins. Valid values are: gpio, adsp_ext, agera_pll, atest_char, atest_gpsadc0, atest_gpsadc1, atest_tsens, atest_tsens2, atest_usb1, atest_usb10, atest_usb11, atest_usb12, atest_usb13, audio_ref, bimc_dte0, bimc_dte1, blsp10_spi, blsp10_spi_a, blsp10_spi_b, blsp11_i2c, blsp1_spi, blsp1_spi_a, blsp1_spi_b, blsp2_spi, blsp9_spi, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10, blsp_spi11, blsp_spi12, blsp_uart1_a, blsp_uart1_b, blsp_uart2_a, blsp_uart2_b, blsp_uart3_a, blsp_uart3_b, blsp_uart7_a, blsp_uart7_b, blsp_uart8, blsp_uart8_a, blsp_uart8_b, blsp_uart9_a, blsp_uart9_b, blsp_uim1_a, blsp_uim1_b, blsp_uim2_a, blsp_uim2_b, blsp_uim3_a, blsp_uim3_b, blsp_uim7_a, blsp_uim7_b, blsp_uim8_a, blsp_uim8_b, blsp_uim9_a, blsp_uim9_b, bt_reset, btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, edp_hot, edp_lcd, gcc_gp1_a, gcc_gp1_b, gcc_gp2_a, gcc_gp2_b, gcc_gp3_a, gcc_gp3_b, hdmi_cec, hdmi_ddc, hdmi_hot, hdmi_rcv, isense_dbg, jitter_bist, ldo_en, ldo_update, lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync_a, mdp_vsync_b, modem_tsync, mss_lte, nav_dr, nav_pps, pa_indicator, pci_e0, phase_flag, pll_bypassnl, pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, pwr_crypto, pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b, qdss_cti1_a, qdss_cti1_b, qdss, qlink_enable, qlink_request, qua_mi2s, sd_card, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ssbi1, ssc_irq, ter_mi2s, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, tsif0, tsif1, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1, vsense_clkout, vsense_data0, vsense_data1, vsense_mode, wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, - bias-disable: Usage: optional Value type: <none> Definition: The specified pins should be configured as no pull. - bias-pull-down: Usage: optional Value type: <none> Definition: The specified pins should be configured as pull down. - bias-pull-up: Usage: optional Value type: <none> Definition: The specified pins should be configured as pull up. - output-high: Usage: optional Value type: <none> Definition: The specified pins are configured in output mode, driven high. Not valid for sdc pins. - output-low: Usage: optional Value type: <none> Definition: The specified pins are configured in output mode, driven low. Not valid for sdc pins. - drive-strength: Usage: optional Value type: <u32> Definition: Selects the drive strength for the specified pins, in mA. Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 Example: tlmm: pinctrl@03400000 { compatible = "qcom,msm8998-pinctrl"; reg = <0x03400000 0xc00000>; interrupts = <0 208 0>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&tlmm 0 0 175>; gpio-reserved-ranges = <0 4>, <81 4>; interrupt-controller; #interrupt-cells = <2>; uart_console_active: uart_console_active { mux { pins = "gpio4", "gpio5"; function = "blsp_uart8_a"; }; config { pins = "gpio4", "gpio5"; drive-strength = <2>; bias-disable; }; }; };

{ "language": "Assembly" }

/** ****************************************************************************** * @file startup_stm32f429xx.s * @author MCD Application Team * @brief STM32F429xx Devices vector table for GCC based toolchains. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ .syntax unified .cpu cortex-m4 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ bl main bx lr .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_IRQHandler /* PVD through EXTI Line detection */ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ .word FLASH_IRQHandler /* FLASH */ .word RCC_IRQHandler /* RCC */ .word EXTI0_IRQHandler /* EXTI Line0 */ .word EXTI1_IRQHandler /* EXTI Line1 */ .word EXTI2_IRQHandler /* EXTI Line2 */ .word EXTI3_IRQHandler /* EXTI Line3 */ .word EXTI4_IRQHandler /* EXTI Line4 */ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ .word CAN1_TX_IRQHandler /* CAN1 TX */ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ .word CAN1_SCE_IRQHandler /* CAN1 SCE */ .word EXTI9_5_IRQHandler /* External Line[9:5]s */ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ .word TIM2_IRQHandler /* TIM2 */ .word TIM3_IRQHandler /* TIM3 */ .word TIM4_IRQHandler /* TIM4 */ .word I2C1_EV_IRQHandler /* I2C1 Event */ .word I2C1_ER_IRQHandler /* I2C1 Error */ .word I2C2_EV_IRQHandler /* I2C2 Event */ .word I2C2_ER_IRQHandler /* I2C2 Error */ .word SPI1_IRQHandler /* SPI1 */ .word SPI2_IRQHandler /* SPI2 */ .word USART1_IRQHandler /* USART1 */ .word USART2_IRQHandler /* USART2 */ .word USART3_IRQHandler /* USART3 */ .word EXTI15_10_IRQHandler /* External Line[15:10]s */ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ .word FMC_IRQHandler /* FMC */ .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ .word UART4_IRQHandler /* UART4 */ .word UART5_IRQHandler /* UART5 */ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ .word TIM7_IRQHandler /* TIM7 */ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ .word ETH_IRQHandler /* Ethernet */ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ .word CAN2_TX_IRQHandler /* CAN2 TX */ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ .word CAN2_SCE_IRQHandler /* CAN2 SCE */ .word OTG_FS_IRQHandler /* USB OTG FS */ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ .word USART6_IRQHandler /* USART6 */ .word I2C3_EV_IRQHandler /* I2C3 event */ .word I2C3_ER_IRQHandler /* I2C3 error */ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ .word OTG_HS_IRQHandler /* USB OTG HS */ .word DCMI_IRQHandler /* DCMI */ .word 0 /* Reserved */ .word HASH_RNG_IRQHandler /* Hash and Rng */ .word FPU_IRQHandler /* FPU */ .word UART7_IRQHandler /* UART7 */ .word UART8_IRQHandler /* UART8 */ .word SPI4_IRQHandler /* SPI4 */ .word SPI5_IRQHandler /* SPI5 */ .word SPI6_IRQHandler /* SPI6 */ .word SAI1_IRQHandler /* SAI1 */ .word LTDC_IRQHandler /* LTDC_IRQHandler */ .word LTDC_ER_IRQHandler /* LTDC_ER_IRQHandler */ .word DMA2D_IRQHandler /* DMA2D */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak CAN1_TX_IRQHandler .thumb_set CAN1_TX_IRQHandler,Default_Handler .weak CAN1_RX0_IRQHandler .thumb_set CAN1_RX0_IRQHandler,Default_Handler .weak CAN1_RX1_IRQHandler .thumb_set CAN1_RX1_IRQHandler,Default_Handler .weak CAN1_SCE_IRQHandler .thumb_set CAN1_SCE_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM9_IRQHandler .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler .weak TIM1_UP_TIM10_IRQHandler .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM11_IRQHandler .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak TIM8_BRK_TIM12_IRQHandler .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler .weak TIM8_UP_TIM13_IRQHandler .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler .weak TIM8_TRG_COM_TIM14_IRQHandler .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak FMC_IRQHandler .thumb_set FMC_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak ETH_IRQHandler .thumb_set ETH_IRQHandler,Default_Handler .weak ETH_WKUP_IRQHandler .thumb_set ETH_WKUP_IRQHandler,Default_Handler .weak CAN2_TX_IRQHandler .thumb_set CAN2_TX_IRQHandler,Default_Handler .weak CAN2_RX0_IRQHandler .thumb_set CAN2_RX0_IRQHandler,Default_Handler .weak CAN2_RX1_IRQHandler .thumb_set CAN2_RX1_IRQHandler,Default_Handler .weak CAN2_SCE_IRQHandler .thumb_set CAN2_SCE_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak OTG_HS_EP1_OUT_IRQHandler .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_HS_EP1_IN_IRQHandler .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler .weak OTG_HS_WKUP_IRQHandler .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler .weak OTG_HS_IRQHandler .thumb_set OTG_HS_IRQHandler,Default_Handler .weak DCMI_IRQHandler .thumb_set DCMI_IRQHandler,Default_Handler .weak HASH_RNG_IRQHandler .thumb_set HASH_RNG_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler .weak UART7_IRQHandler .thumb_set UART7_IRQHandler,Default_Handler .weak UART8_IRQHandler .thumb_set UART8_IRQHandler,Default_Handler .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler .weak SPI5_IRQHandler .thumb_set SPI5_IRQHandler,Default_Handler .weak SPI6_IRQHandler .thumb_set SPI6_IRQHandler,Default_Handler .weak SAI1_IRQHandler .thumb_set SAI1_IRQHandler,Default_Handler .weak LTDC_IRQHandler .thumb_set LTDC_IRQHandler,Default_Handler .weak LTDC_ER_IRQHandler .thumb_set LTDC_ER_IRQHandler,Default_Handler .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

{ "language": "Assembly" }

; RUN: opt < %s -basicaa -globalsmodref-aa -gvn -instcombine -S | FileCheck %s @G = internal global i32* null ; <i32**> [#uses=3] declare i8* @malloc(i32) define void @test() { %a = call i8* @malloc(i32 4) %A = bitcast i8* %a to i32* store i32* %A, i32** @G ret void } define i32 @test1(i32* %P) { ; CHECK: ret i32 0 %g1 = load i32** @G ; <i32*> [#uses=2] %h1 = load i32* %g1 ; <i32> [#uses=1] store i32 123, i32* %P %g2 = load i32** @G ; <i32*> [#uses=0] %h2 = load i32* %g1 ; <i32> [#uses=1] %X = sub i32 %h1, %h2 ; <i32> [#uses=1] ret i32 %X }

{ "language": "Assembly" }

;****************************************************************************** ; ; grlib_driver_test.sct - Linker configuration file for grlib_driver_test. ; ; Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. ; Software License Agreement ; ; Texas Instruments (TI) is supplying this software for use solely and ; exclusively on TI's microcontroller products. The software is owned by ; TI and/or its suppliers, and is protected under applicable copyright ; laws. You may not combine this software with "viral" open-source ; software in order to form a larger program. ; ; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. ; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT ; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY ; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL ; DAMAGES, FOR ANY REASON WHATSOEVER. ; ; This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. ; ;****************************************************************************** LR_IROM 0x00000000 0x00100000 { ; ; Specify the Execution Address of the code and the size. ; ER_IROM 0x00000000 0x00100000 { *.o (RESET, +First) * (InRoot$$Sections, +RO) } ; ; Specify the Execution Address of the data area. ; RW_IRAM 0x20000000 0x00040000 { ; ; Uncomment the following line in order to use IntRegister(). ; ;* (vtable, +First) * (+RW, +ZI) } }

{ "language": "Assembly" }

/* Multiple versions of sincosf. Copyright (C) 2017 Free Software Foundation, Inc. This file is part of the GNU C Library. The GNU C Library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version. The GNU C Library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with the GNU C Library; if not, see <http://www.gnu.org/licenses/>. */ #include <libm-alias-float.h> extern void __redirect_sincosf (float, float *, float *); #define SYMBOL_NAME sincosf #include "ifunc-fma.h" libc_ifunc_redirected (__redirect_sincosf, __sincosf, IFUNC_SELECTOR ()); libm_alias_float (__sincos, sincos)

{ "language": "Assembly" }

// Copyright 2014 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build !gccgo #include "textflag.h" // // System calls for amd64, Solaris are implemented in runtime/syscall_solaris.go // TEXT ·sysvicall6(SB),NOSPLIT,$0-88 JMP syscall·sysvicall6(SB) TEXT ·rawSysvicall6(SB),NOSPLIT,$0-88 JMP syscall·rawSysvicall6(SB)

{ "language": "Assembly" }

; RUN: not llvm-as -disable-output <%s 2>&1 | FileCheck %s ; CHECK: invalid llvm.dbg.declare intrinsic variable ; CHECK-NEXT: call void @llvm.dbg.declare({{.*}}) ; CHECK-NEXT: !"" define void @foo(i32 %a) { entry: %s = alloca i32 call void @llvm.dbg.declare(metadata i32* %s, metadata !"", metadata !DIExpression()), !dbg !DILocation(scope: !1) ret void } declare void @llvm.dbg.declare(metadata, metadata, metadata) !llvm.module.flags = !{!0} !0 = !{i32 2, !"Debug Info Version", i32 3} !1 = distinct !DISubprogram()

{ "language": "Assembly" }

TEXT sin(SB), $0 FMOVD a+0(FP), F0 FSIN RET TEXT cos(SB), $0 FMOVD a+0(FP), F0 FCOS RET

{ "language": "Assembly" }

/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _SELFTESTS_POWERPC_BASIC_ASM_H #define _SELFTESTS_POWERPC_BASIC_ASM_H #include <ppc-asm.h> #include <asm/unistd.h> #define LOAD_REG_IMMEDIATE(reg, expr) \ lis reg, (expr)@highest; \ ori reg, reg, (expr)@higher; \ rldicr reg, reg, 32, 31; \ oris reg, reg, (expr)@high; \ ori reg, reg, (expr)@l; /* * Note: These macros assume that variables being stored on the stack are * doublewords, while this is usually the case it may not always be the * case for each use case. */ #if defined(_CALL_ELF) && _CALL_ELF == 2 #define STACK_FRAME_MIN_SIZE 32 #define STACK_FRAME_TOC_POS 24 #define __STACK_FRAME_PARAM(_param) (32 + ((_param)*8)) #define __STACK_FRAME_LOCAL(_num_params, _var_num) \ ((STACK_FRAME_PARAM(_num_params)) + ((_var_num)*8)) #else #define STACK_FRAME_MIN_SIZE 112 #define STACK_FRAME_TOC_POS 40 #define __STACK_FRAME_PARAM(i) (48 + ((i)*8)) /* * Caveat: if a function passed more than 8 doublewords, the caller will have * made more space... which would render the 112 incorrect. */ #define __STACK_FRAME_LOCAL(_num_params, _var_num) \ (112 + ((_var_num)*8)) #endif /* Parameter x saved to the stack */ #define STACK_FRAME_PARAM(var) __STACK_FRAME_PARAM(var) /* Local variable x saved to the stack after x parameters */ #define STACK_FRAME_LOCAL(num_params, var) \ __STACK_FRAME_LOCAL(num_params, var) #define STACK_FRAME_LR_POS 16 #define STACK_FRAME_CR_POS 8 /* * It is very important to note here that _extra is the extra amount of * stack space needed. This space can be accessed using STACK_FRAME_PARAM() * or STACK_FRAME_LOCAL() macros. * * r1 and r2 are not defined in ppc-asm.h (instead they are defined as sp * and toc). Kernel programmers tend to prefer rX even for r1 and r2, hence * %1 and %r2. r0 is defined in ppc-asm.h and therefore %r0 gets * preprocessed incorrectly, hence r0. */ #define PUSH_BASIC_STACK(_extra) \ mflr r0; \ std r0, STACK_FRAME_LR_POS(%r1); \ stdu %r1, -(_extra + STACK_FRAME_MIN_SIZE)(%r1); \ mfcr r0; \ stw r0, STACK_FRAME_CR_POS(%r1); \ std %r2, STACK_FRAME_TOC_POS(%r1); #define POP_BASIC_STACK(_extra) \ ld %r2, STACK_FRAME_TOC_POS(%r1); \ lwz r0, STACK_FRAME_CR_POS(%r1); \ mtcr r0; \ addi %r1, %r1, (_extra + STACK_FRAME_MIN_SIZE); \ ld r0, STACK_FRAME_LR_POS(%r1); \ mtlr r0; #endif /* _SELFTESTS_POWERPC_BASIC_ASM_H */

{ "language": "Assembly" }

; RUN: opt < %s -argpromotion -S | FileCheck %s ; RUN: opt < %s -passes=argpromotion -S | FileCheck %s %T = type { i32, i32, i32, i32 } @G = constant %T { i32 0, i32 0, i32 17, i32 25 } define internal i32 @test(%T* %p) { ; CHECK-LABEL: define internal i32 @test( ; CHECK: i32 %{{.*}}, i32 %{{.*}}) entry: %a.gep = getelementptr %T, %T* %p, i64 0, i32 3 %b.gep = getelementptr %T, %T* %p, i64 0, i32 2 %a = load i32, i32* %a.gep %b = load i32, i32* %b.gep ; CHECK-NOT: load %v = add i32 %a, %b ret i32 %v ; CHECK: ret i32 } define i32 @caller() { ; CHECK-LABEL: define i32 @caller( entry: %v = call i32 @test(%T* @G) ; CHECK: %[[B_GEP:.*]] = getelementptr %T, %T* @G, i64 0, i32 2 ; CHECK: %[[B:.*]] = load i32, i32* %[[B_GEP]] ; CHECK: %[[A_GEP:.*]] = getelementptr %T, %T* @G, i64 0, i32 3 ; CHECK: %[[A:.*]] = load i32, i32* %[[A_GEP]] ; CHECK: call i32 @test(i32 %[[B]], i32 %[[A]]) ret i32 %v }

{ "language": "Assembly" }

/* * Moniker generated from PCX/deskicon.pcx with pixel 13 masked out */ start AppIconAreaSCMonikerResource, data; visMoniker DisconnectButtonSCMoniker = { size = standard; style = icon; aspectRatio = normal; color = color4; cachedSize = 48, 30; gstring { GSBeginString GSDrawBitmapAtCP 906 Bitmap <48,30,0,BMF_4BIT or mask BMT_MASK> db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x80, 0x21, 0x08, 0x02, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0x0d, 0xdd, 0xdd, 0xdd, 0xdd, 0xed, 0xdd, 0xde, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xdd, 0xdd, 0x0d, 0xdd, 0xdd, 0xdd, 0xdd db 0x01, 0xc0, 0x11, 0x10, 0x03, 0x00 db 0xdd, 0xdd, 0xdd, 0xd0, 0x08, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x00, 0xdd, 0xdd, 0xdd, 0xdd db 0x03, 0xc0, 0x11, 0x10, 0x03, 0x80 db 0xdd, 0xdd, 0xdd, 0x0f, 0x08, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0x0d, 0xdd, 0xdd, 0xdd db 0x07, 0xc0, 0x08, 0x20, 0x03, 0xc0 db 0xdd, 0xdd, 0xd0, 0xff, 0x08, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0xf0, 0xdd, 0xdd, 0xdd db 0x0f, 0xc0, 0x08, 0x20, 0x03, 0xe0 db 0xdd, 0xdd, 0x0f, 0xff, 0x08, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0xff, 0x0d, 0xdd, 0xdd db 0x1f, 0xff, 0xc4, 0x4f, 0xff, 0xf0 db 0xdd, 0xd0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xf0, 0xdd, 0xdd db 0x3f, 0xff, 0xe0, 0x0f, 0xff, 0xf8 db 0xdd, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x8d, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0d, 0xdd db 0x7f, 0xff, 0xe0, 0x0f, 0xff, 0xfc db 0xd0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x8d, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xdd db 0xff, 0xff, 0xe0, 0x0f, 0xff, 0xfe db 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x8d, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0d db 0x7f, 0xff, 0xe0, 0x0f, 0xff, 0xff db 0xd0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x8d, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x88 db 0x3f, 0xff, 0xe0, 0x0f, 0xff, 0xfe db 0xdd, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x8d, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x08, 0x8d db 0x1f, 0xff, 0xe0, 0x0f, 0xff, 0xfc db 0xdd, 0xd0, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8d, 0xdd, 0xdd, 0xdd, 0xdd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xf0, 0x88, 0xdd db 0x0f, 0xff, 0xe4, 0x47, 0xff, 0xf8 db 0xdd, 0xdd, 0x0f, 0xff, 0x08, 0x88, 0x88, 0x88, 0x88, 0x8d, 0xde, 0xdd, 0xde, 0xdd, 0xd8, 0x88, 0x88, 0x88, 0x88, 0x0f, 0xff, 0x08, 0x8d, 0xdd db 0x07, 0xc0, 0x08, 0x20, 0x03, 0xf0 db 0xdd, 0xdd, 0xd0, 0xff, 0x08, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0xf0, 0x88, 0xdd, 0xdd db 0x03, 0xc0, 0x08, 0x20, 0x03, 0xe0 db 0xdd, 0xdd, 0xdd, 0x0f, 0x08, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x0f, 0x08, 0x8d, 0xdd, 0xdd db 0x01, 0xc0, 0x11, 0x10, 0x03, 0xc0 db 0xdd, 0xdd, 0xdd, 0xd0, 0x08, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x00, 0x88, 0xdd, 0xdd, 0xdd db 0x00, 0xc0, 0x11, 0x10, 0x03, 0x80 db 0xdd, 0xdd, 0xdd, 0xdd, 0x08, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0x08, 0x8d, 0xdd, 0xdd, 0xdd db 0x00, 0x40, 0x21, 0x08, 0x01, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xd8, 0xdd, 0xdd, 0xdd, 0xdd, 0xed, 0xdd, 0xde, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xdd, 0xdd, 0xd8, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd GSEndString } } end AppIconAreaSCMonikerResource; /* * Moniker generated from PCX/deskicon.pcx with pixel 13 masked out */ start AppIconAreaSMMonikerResource, data; visMoniker DisconnectButtonSMMoniker = { size = standard; style = icon; aspectRatio = normal; color = gray1; cachedSize = 48, 30; gstring { GSBeginString GSFillBitmapAtCP 186 Bitmap <48,30,0,BMF_MONO> db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 db 0x00, 0x80, 0x21, 0x08, 0x02, 0x00 db 0x01, 0xc0, 0x11, 0x10, 0x03, 0x00 db 0x02, 0xc0, 0x11, 0x10, 0x02, 0x80 db 0x04, 0xc0, 0x08, 0x20, 0x02, 0x40 db 0x08, 0xc0, 0x08, 0x20, 0x02, 0x20 db 0x10, 0xff, 0xc4, 0x4f, 0xfe, 0x10 db 0x20, 0x00, 0x60, 0x08, 0x00, 0x08 db 0x40, 0x00, 0x60, 0x08, 0x00, 0x04 db 0x80, 0x00, 0x60, 0x08, 0x00, 0x02 db 0x40, 0x00, 0x60, 0x08, 0x00, 0x07 db 0x20, 0x00, 0x60, 0x08, 0x00, 0x0e db 0x10, 0xff, 0xe0, 0x0f, 0xfe, 0x1c db 0x08, 0xff, 0xe4, 0x47, 0xfe, 0x38 db 0x04, 0xc0, 0x08, 0x20, 0x02, 0x70 db 0x02, 0xc0, 0x08, 0x20, 0x02, 0xe0 db 0x01, 0xc0, 0x11, 0x10, 0x03, 0xc0 db 0x00, 0xc0, 0x11, 0x10, 0x03, 0x80 db 0x00, 0x40, 0x21, 0x08, 0x01, 0x00 db 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 GSEndString } } end AppIconAreaSMMonikerResource; /* * Moniker generated from PCX/deskicon.pcx with pixel 13 masked out */ start AppIconAreaSCGAMonikerResource, data; visMoniker DisconnectButtonSCGAMoniker = { size = tiny; style = icon; aspectRatio = verySquished; color = gray1; cachedSize = 48, 14; gstring { GSBeginString GSFillBitmapAtCP 90 Bitmap <48,14,0,BMF_MONO> db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 db 0x00, 0x00, 0x81, 0x81, 0x00, 0x00 db 0x00, 0xc0, 0x61, 0x86, 0x06, 0x00 db 0x03, 0x70, 0x19, 0x98, 0x05, 0x80 db 0x0c, 0x7f, 0x84, 0x23, 0xfc, 0x60 db 0x30, 0x00, 0xe0, 0x02, 0x00, 0x18 db 0xc0, 0x00, 0xe0, 0x02, 0x00, 0x07 db 0x30, 0x00, 0xe0, 0x02, 0x00, 0x1f db 0x0c, 0x7f, 0xe0, 0x03, 0xfc, 0x7c db 0x03, 0x7f, 0xe4, 0x21, 0xfd, 0xf0 db 0x00, 0xf0, 0x19, 0x98, 0x07, 0xc0 db 0x00, 0x30, 0x61, 0x86, 0x01, 0x00 db 0x00, 0x00, 0x81, 0x81, 0x00, 0x00 db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 GSEndString } } end AppIconAreaSCGAMonikerResource;

{ "language": "Assembly" }

test compile target x86_64 function u0:51(i64, i64) system_v { ss0 = explicit_slot 0 ss1 = explicit_slot 1 ss2 = explicit_slot 1 ss3 = explicit_slot 1 block0(v0: i64, v1: i64): v2 = stack_addr.i64 ss1 v3 = load.i8 v1 store v3, v2 v4 = stack_addr.i64 ss2 v5 = stack_addr.i64 ss3 jump block1 block1: v6 = load.i8 v2 store v6, v5 v7 = load.i8 v5 v8 = bnot v7 store v8, v4 v9 = load.i8 v4 store v9, v0 return }

{ "language": "Assembly" }

/* -*- Mode: C; indent-tabs-mode: t; c-basic-offset: 8; tab-width: 8 -*- eel-lib-self-check-functions.h: Wrapper and prototypes for all self-check functions in libeel. Copyright (C) 2000 Eazel, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU Library General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Library General Public License for more details. You should have received a copy of the GNU Library General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Suite 500, Boston, MA 02110-1335, USA. Author: Darin Adler <[email protected]> */ #include "eel-self-checks.h" void eel_run_lib_self_checks (void); /* Putting the prototypes for these self-check functions in each header file for the files they are defined in would make compiling the self-check framework take way too long (since one file would have to include everything). So we put the list of functions here instead. Instead of just putting prototypes here, we put this macro that can be used to do operations on the whole list of functions. */ #define EEL_LIB_FOR_EACH_SELF_CHECK_FUNCTION(macro) \ macro (eel_self_check_glib_extensions) \ macro (eel_self_check_string) \ /* Add new self-check functions to the list above this line. */ /* Generate prototypes for all the functions. */ EEL_LIB_FOR_EACH_SELF_CHECK_FUNCTION (EEL_SELF_CHECK_FUNCTION_PROTOTYPE)

{ "language": "Assembly" }

/* This linker script generated from xt-genldscripts.tpp for LSP . */ /* Linker Script for ld -N */ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 iram1_0_seg : org = 0x40100000, len = 0x8000 irom0_0_seg : org = 0x40208000 + 0x1000, len = 0x33000 } PHDRS { dport0_0_phdr PT_LOAD; dram0_0_phdr PT_LOAD; dram0_0_bss_phdr PT_LOAD; iram1_0_phdr PT_LOAD; irom0_0_phdr PT_LOAD; } /* Default entry point: */ ENTRY(call_user_start) EXTERN(_DebugExceptionVector) EXTERN(_DoubleExceptionVector) EXTERN(_KernelExceptionVector) EXTERN(_NMIExceptionVector) EXTERN(_UserExceptionVector) PROVIDE(_memmap_vecbase_reset = 0x40000000); /* Various memory-map dependent cache attribute settings: */ _memmap_cacheattr_wb_base = 0x00000110; _memmap_cacheattr_wt_base = 0x00000110; _memmap_cacheattr_bp_base = 0x00000220; _memmap_cacheattr_unused_mask = 0xFFFFF00F; _memmap_cacheattr_wb_trapnull = 0x2222211F; _memmap_cacheattr_wba_trapnull = 0x2222211F; _memmap_cacheattr_wbna_trapnull = 0x2222211F; _memmap_cacheattr_wt_trapnull = 0x2222211F; _memmap_cacheattr_bp_trapnull = 0x2222222F; _memmap_cacheattr_wb_strict = 0xFFFFF11F; _memmap_cacheattr_wt_strict = 0xFFFFF11F; _memmap_cacheattr_bp_strict = 0xFFFFF22F; _memmap_cacheattr_wb_allvalid = 0x22222112; _memmap_cacheattr_wt_allvalid = 0x22222112; _memmap_cacheattr_bp_allvalid = 0x22222222; PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); SECTIONS { .dport0.rodata : ALIGN(4) { _dport0_rodata_start = ABSOLUTE(.); *(.dport0.rodata) *(.dport.rodata) _dport0_rodata_end = ABSOLUTE(.); } >dport0_0_seg :dport0_0_phdr .dport0.literal : ALIGN(4) { _dport0_literal_start = ABSOLUTE(.); *(.dport0.literal) *(.dport.literal) _dport0_literal_end = ABSOLUTE(.); } >dport0_0_seg :dport0_0_phdr .dport0.data : ALIGN(4) { _dport0_data_start = ABSOLUTE(.); *(.dport0.data) *(.dport.data) _dport0_data_end = ABSOLUTE(.); } >dport0_0_seg :dport0_0_phdr .data : ALIGN(4) { _data_start = ABSOLUTE(.); *(.data) *(.data.*) *(.gnu.linkonce.d.*) *(.data1) *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) *(.jcr) _data_end = ABSOLUTE(.); } >dram0_0_seg :dram0_0_phdr .rodata : ALIGN(4) { _rodata_start = ABSOLUTE(.); *(.sdk.version) *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) *(.rodata1) __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); *(.xt_except_table) *(.gcc_except_table) *(.gnu.linkonce.e.*) *(.gnu.version_r) *(.eh_frame) /* C++ constructor and destructor tables, properly ordered: */ KEEP (*crtbegin.o(.ctors)) KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) KEEP (*crtbegin.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) /* C++ exception handlers table: */ __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); *(.xt_except_desc) *(.gnu.linkonce.h.*) __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); *(.xt_except_desc_end) *(.dynamic) *(.gnu.version_d) . = ALIGN(4); /* this table MUST be 4-byte aligned */ _bss_table_start = ABSOLUTE(.); LONG(_bss_start) LONG(_bss_end) _bss_table_end = ABSOLUTE(.); _rodata_end = ABSOLUTE(.); } >dram0_0_seg :dram0_0_phdr .bss ALIGN(8) (NOLOAD) : ALIGN(4) { . = ALIGN (8); _bss_start = ABSOLUTE(.); *(.dynsbss) *(.sbss) *(.sbss.*) *(.gnu.linkonce.sb.*) *(.scommon) *(.sbss2) *(.sbss2.*) *(.gnu.linkonce.sb2.*) *(.dynbss) *(.bss) *(.bss.*) *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN (8); _bss_end = ABSOLUTE(.); _heap_start = ABSOLUTE(.); /* _stack_sentry = ALIGN(0x8); */ } >dram0_0_seg :dram0_0_bss_phdr /* __stack = 0x3ffc8000; */ .irom0.text : ALIGN(4) { _irom0_text_start = ABSOLUTE(.); *libmbedtls.a:(.literal .text .literal.* .text.*) */libaxtls.a:(.literal*, .text*) main.o(.literal*, .text*) /*ota.o(.literal*, .text*)*/ *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text) _irom0_text_end = ABSOLUTE(.); } >irom0_0_seg :irom0_0_phdr .text : ALIGN(4) { _stext = .; _text_start = ABSOLUTE(.); *(.UserEnter.text) . = ALIGN(16); *(.DebugExceptionVector.text) . = ALIGN(16); *(.NMIExceptionVector.text) . = ALIGN(16); *(.KernelExceptionVector.text) LONG(0) LONG(0) LONG(0) LONG(0) . = ALIGN(16); *(.UserExceptionVector.text) LONG(0) LONG(0) LONG(0) LONG(0) . = ALIGN(16); *(.DoubleExceptionVector.text) LONG(0) LONG(0) LONG(0) LONG(0) . = ALIGN (16); *(.entry.text) *(.init.literal) *(.init) *(.literal .text .literal.* .text.* .iram0.literal .iram0.text .iram0.text.*.literal .iram0.text.*) *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *(.fini.literal) *(.fini) *(.gnu.version) _text_end = ABSOLUTE(.); _etext = .; } >iram1_0_seg :iram1_0_phdr .lit4 : ALIGN(4) { _lit4_start = ABSOLUTE(.); *(*.lit4) *(.lit4.*) *(.gnu.linkonce.lit4.*) _lit4_end = ABSOLUTE(.); } >iram1_0_seg :iram1_0_phdr } /* get ROM code address */ INCLUDE "../boot8266/eagle.rom.addr.v6.ld"

{ "language": "Assembly" }

# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifc foo, foo .byte 1 .else .byte 0 .endif # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifc "foo space", "foo space" .byte 1 .else .byte 0 .endif # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifc foo space, foo space .byte 1 .else .byte 0 .endif # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifc unequal, unEqual .byte 0 .else .byte 1 .endif # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifnc foo, foo .byte 0 .else .byte 1 .endif # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifnc "foo space", "foo space" .byte 0 .else .byte 1 .endif # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifnc foo space, foo space .byte 0 .else .byte 1 .endif # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifnc unequal, unEqual .byte 1 .else .byte 0 .endif # CHECK-NOT: .byte 0 # CHECK: .byte 1 .ifnc equal, equal ; .byte 0 ; .else ; .byte 1 ; .endif

{ "language": "Assembly" }

// RUN: %clang_cc1 -O0 -triple spir -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -O0 -triple spir64 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -O0 -triple spir -fexperimental-new-pass-manager -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -O0 -triple spir64 -fexperimental-new-pass-manager -emit-llvm %s -o - | FileCheck %s // This file tests that using the _Float16 type with the spir target will not // use the llvm intrinsics but instead will use the half arithmetic // instructions directly. // Previously attempting to use a constant _Float16 with a comparison // instruction when the target is spir or spir64 lead to an assert being hit. bool fcmp_const() { _Float16 a = 0.0f16; const _Float16 b = 1.0f16; // CHECK-NOT: llvm.convert.to.fp16 // CHECK-NOT: llvm.convert.from.fp16 // CHECK: [[REG1:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: fcmp olt half [[REG1]], 0xH3C00 // CHECK: [[REG2:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: fcmp olt half [[REG2]], 0xH4000 // CHECK: [[REG3:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: fcmp ogt half [[REG3]], 0xH3C00 // CHECK: [[REG4:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: fcmp ogt half [[REG4]], 0xH4200 // CHECK: [[REG5:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: fcmp oeq half [[REG5]], 0xH3C00 // CHECK: [[REG7:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: fcmp oeq half [[REG7]], 0xH4400 // CHECK: [[REG8:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: fcmp une half [[REG8]], 0xH3C00 // CHECK: [[REG9:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: fcmp une half [[REG9]], 0xH4500 // CHECK: [[REG10:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: fcmp ole half [[REG10]], 0xH3C00 // CHECK: [[REG11:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: fcmp ole half [[REG11]], 0xH4600 // CHECK: [[REG12:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: fcmp oge half [[REG12]], 0xH3C00 // CHECK: [[REG13:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: fcmp oge half [[REG13]], 0xH4700 return a < b || a < 2.0f16 || a > b || a > 3.0f16 || a == b || a == 4.0f16 || a != b || a != 5.0f16 || a <= b || a <= 6.0f16 || a >= b || a >= 7.0f16; } bool fcmp() { _Float16 a = 0.0f16; _Float16 b = 1.0f16; // CHECK-NOT: llvm.convert.to.fp16 // CHECK-NOT: llvm.convert.from.fp16 // CHECK: [[REG1:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: [[REG2:%.*]] = load half, half* %b, align 2 // CHECK-NEXT: fcmp olt half [[REG1]], [[REG2]] // CHECK: [[REG3:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: [[REG4:%.*]] = load half, half* %b, align 2 // CHECK-NEXT: fcmp ogt half [[REG3]], [[REG4]] // CHECK: [[REG5:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: [[REG6:%.*]] = load half, half* %b, align 2 // CHECK-NEXT: fcmp oeq half [[REG5]], [[REG6]] // CHECK: [[REG7:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: [[REG8:%.*]] = load half, half* %b, align 2 // CHECK-NEXT: fcmp une half [[REG7]], [[REG8]] // CHECK: [[REG7:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: [[REG8:%.*]] = load half, half* %b, align 2 // CHECK-NEXT: fcmp ole half [[REG7]], [[REG8]] // CHECK: [[REG7:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: [[REG8:%.*]] = load half, half* %b, align 2 // CHECK-NEXT: fcmp oge half [[REG7]], [[REG8]] return a < b || a > b || a == b || a != b || a <= b || a >= b; } _Float16 fadd() { _Float16 a = 1.0f16; const _Float16 b = 2.0f16; // CHECK-NOT: llvm.convert.to.fp16 // CHECK-NOT: llvm.convert.from.fp16 // CHECK: [[REG1:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: [[REG2:%.*]] = fadd half [[REG1]], 0xH4000 // CHECK-NEXT: [[REG3:%.*]] = fadd half [[REG2]], 0xH4200 // CHECK-NEXT: ret half [[REG3]] return a + b + 3.0f16; } _Float16 fsub() { _Float16 a = 1.0f16; const _Float16 b = 2.0f16; // CHECK-NOT: llvm.convert.to.fp16 // CHECK-NOT: llvm.convert.from.fp16 // CHECK: [[REG1:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: [[REG2:%.*]] = fsub half [[REG1]], 0xH4000 // CHECK-NEXT: [[REG3:%.*]] = fsub half [[REG2]], 0xH4200 // CHECK-NEXT: ret half [[REG3]] return a - b - 3.0f16; } // CHECK: define spir_func half @_Z4fmulDF16_(half %arg) _Float16 fmul(_Float16 arg) { _Float16 a = 1.0f16; const _Float16 b = 2.0f16; // CHECK-NOT: llvm.convert.to.fp16 // CHECK-NOT: llvm.convert.from.fp16 // CHECK: [[REG1:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: [[REG2:%.*]] = load half, half* %arg.addr, align 2 // CHECK-NEXT: [[REG3:%.*]] = fmul half [[REG1]], [[REG2]] // CHECK-NEXT: [[REG4:%.*]] = fmul half [[REG3]], 0xH4000 // CHECK-NEXT: [[REG5:%.*]] = fmul half [[REG4]], 0xH4200 // CHECK-NEXT: ret half [[REG5]] return a * arg * b * 3.0f16; } _Float16 fdiv() { _Float16 a = 1.0f16; const _Float16 b = 2.0f16; // CHECK-NOT: llvm.convert.to.fp16 // CHECK-NOT: llvm.convert.from.fp16 // CHECK: [[REG1:%.*]] = load half, half* %a, align 2 // CHECK-NEXT: [[REG2:%.*]] = fdiv half [[REG1]], 0xH4000 // CHECK-NEXT: [[REG3:%.*]] = fdiv half [[REG2]], 0xH4200 // CHECK-NEXT: ret half [[REG3]] return a / b / 3.0f16; }

{ "language": "Assembly" }

@ RUN: llvm-mc -n -triple armv7-apple-darwin10 %s -filetype=obj -o %t.obj @ RUN: macho-dump --dump-section-data < %t.obj > %t.dump @ RUN: FileCheck < %t.dump %s .syntax unified .text _f0: bl _printf _f1: bl _f0 .data _d0: Ld0_0: .long Lsc0_0 - Ld0_0 .section __TEXT,__cstring,cstring_literals Lsc0_0: .long 0 .subsections_via_symbols @ CHECK: ('cputype', 12) @ CHECK: ('cpusubtype', 9) @ CHECK: ('filetype', 1) @ CHECK: ('num_load_commands', 3) @ CHECK: ('load_commands_size', 364) @ CHECK: ('flag', 8192) @ CHECK: ('load_commands', [ @ CHECK: # Load Command 0 @ CHECK: (('command', 1) @ CHECK: ('size', 260) @ CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @ CHECK: ('vm_addr', 0) @ CHECK: ('vm_size', 16) @ CHECK: ('file_offset', 392) @ CHECK: ('file_size', 16) @ CHECK: ('maxprot', 7) @ CHECK: ('initprot', 7) @ CHECK: ('num_sections', 3) @ CHECK: ('flags', 0) @ CHECK: ('sections', [ @ CHECK: # Section 0 @ CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @ CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @ CHECK: ('address', 0) @ CHECK: ('size', 8) @ CHECK: ('offset', 392) @ CHECK: ('alignment', 0) @ CHECK: ('reloc_offset', 408) @ CHECK: ('num_reloc', 2) @ CHECK: ('flags', 0x80000400) @ CHECK: ('reserved1', 0) @ CHECK: ('reserved2', 0) @ CHECK: ), @ CHECK: ('_relocations', [ @ CHECK: # Relocation 0 @ CHECK: (('word-0', 0x4), @ CHECK: ('word-1', 0x55000001)), @ CHECK: # Relocation 1 @ CHECK: (('word-0', 0x0), @ CHECK: ('word-1', 0x5d000003)), @ CHECK: ]) @ CHECK: ('_section_data', 'feffffeb fdffffeb') @ CHECK: # Section 1 @ CHECK: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @ CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @ CHECK: ('address', 8) @ CHECK: ('size', 4) @ CHECK: ('offset', 400) @ CHECK: ('alignment', 0) @ CHECK: ('reloc_offset', 424) @ CHECK: ('num_reloc', 2) @ CHECK: ('flags', 0x0) @ CHECK: ('reserved1', 0) @ CHECK: ('reserved2', 0) @ CHECK: ), @ CHECK: ('_relocations', [ @ CHECK: # Relocation 0 @ CHECK: (('word-0', 0xa2000000), @ CHECK: ('word-1', 0xc)), @ CHECK: # Relocation 1 @ CHECK: (('word-0', 0xa1000000), @ CHECK: ('word-1', 0x8)), @ CHECK: ]) @ CHECK: ('_section_data', '04000000') @ CHECK: # Section 2 @ CHECK: (('section_name', '__cstring\x00\x00\x00\x00\x00\x00\x00') @ CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @ CHECK: ('address', 12) @ CHECK: ('size', 4) @ CHECK: ('offset', 404) @ CHECK: ('alignment', 0) @ CHECK: ('reloc_offset', 0) @ CHECK: ('num_reloc', 0) @ CHECK: ('flags', 0x2) @ CHECK: ('reserved1', 0) @ CHECK: ('reserved2', 0) @ CHECK: ), @ CHECK: ('_relocations', [ @ CHECK: ]) @ CHECK: ('_section_data', '00000000') @ CHECK: ]) @ CHECK: ), @ CHECK: # Load Command 1 @ CHECK: (('command', 2) @ CHECK: ('size', 24) @ CHECK: ('symoff', 440) @ CHECK: ('nsyms', 4) @ CHECK: ('stroff', 488) @ CHECK: ('strsize', 24) @ CHECK: ('_string_data', '\x00_printf\x00_f1\x00_f0\x00_d0\x00\x00\x00\x00') @ CHECK: ('_symbols', [ @ CHECK: # Symbol 0 @ CHECK: (('n_strx', 13) @ CHECK: ('n_type', 0xe) @ CHECK: ('n_sect', 1) @ CHECK: ('n_desc', 0) @ CHECK: ('n_value', 0) @ CHECK: ('_string', '_f0') @ CHECK: ), @ CHECK: # Symbol 1 @ CHECK: (('n_strx', 9) @ CHECK: ('n_type', 0xe) @ CHECK: ('n_sect', 1) @ CHECK: ('n_desc', 0) @ CHECK: ('n_value', 4) @ CHECK: ('_string', '_f1') @ CHECK: ), @ CHECK: # Symbol 2 @ CHECK: (('n_strx', 17) @ CHECK: ('n_type', 0xe) @ CHECK: ('n_sect', 2) @ CHECK: ('n_desc', 0) @ CHECK: ('n_value', 8) @ CHECK: ('_string', '_d0') @ CHECK: ), @ CHECK: # Symbol 3 @ CHECK: (('n_strx', 1) @ CHECK: ('n_type', 0x1) @ CHECK: ('n_sect', 0) @ CHECK: ('n_desc', 0) @ CHECK: ('n_value', 0) @ CHECK: ('_string', '_printf') @ CHECK: ), @ CHECK: ]) @ CHECK: ), @ CHECK: # Load Command 2 @ CHECK: (('command', 11) @ CHECK: ('size', 80) @ CHECK: ('ilocalsym', 0) @ CHECK: ('nlocalsym', 3) @ CHECK: ('iextdefsym', 3) @ CHECK: ('nextdefsym', 0) @ CHECK: ('iundefsym', 3) @ CHECK: ('nundefsym', 1) @ CHECK: ('tocoff', 0) @ CHECK: ('ntoc', 0) @ CHECK: ('modtaboff', 0) @ CHECK: ('nmodtab', 0) @ CHECK: ('extrefsymoff', 0) @ CHECK: ('nextrefsyms', 0) @ CHECK: ('indirectsymoff', 0) @ CHECK: ('nindirectsyms', 0) @ CHECK: ('extreloff', 0) @ CHECK: ('nextrel', 0) @ CHECK: ('locreloff', 0) @ CHECK: ('nlocrel', 0) @ CHECK: ('_indirect_symbols', [ @ CHECK: ]) @ CHECK: ), @ CHECK: ])

{ "language": "Assembly" }

# xalloc.m4 serial 18 dnl Copyright (C) 2002-2006, 2009-2015 Free Software Foundation, Inc. dnl This file is free software; the Free Software Foundation dnl gives unlimited permission to copy and/or distribute it, dnl with or without modifications, as long as this notice is preserved. AC_DEFUN([gl_XALLOC], [:])

{ "language": "Assembly" }

#! /usr/bin/env perl # Copyright 2016-2020 The OpenSSL Project Authors. All Rights Reserved. # # Licensed under the OpenSSL license (the "License"). You may not use # this file except in compliance with the License. You can obtain a copy # in the file LICENSE in the source distribution or at # https://www.openssl.org/source/license.html # # ==================================================================== # Written by Andy Polyakov <[email protected]> for the OpenSSL # project. The module is, however, dual licensed under OpenSSL and # CRYPTOGAMS licenses depending on where you obtain it. For further # details see http://www.openssl.org/~appro/cryptogams/. # ==================================================================== # # ChaCha20 for C64x+. # # October 2015 # # Performance is 3.54 cycles per processed byte, which is ~4.3 times # faster than code generated by TI compiler. Compiler also disables # interrupts for some reason, thus making interrupt response time # dependent on input length. This module on the other hand is free # from such limitation. $output=pop; open STDOUT,">$output"; ($OUT,$INP,$LEN,$KEYB,$COUNTERA)=("A4","B4","A6","B6","A8"); ($KEYA,$COUNTERB,$STEP)=("A7","B7","A3"); @X= ("A16","B16","A17","B17","A18","B18","A19","B19", "A20","B20","A21","B21","A22","B22","A23","B23"); @Y= ("A24","B24","A25","B25","A26","B26","A27","B27", "A28","B28","A29","B29","A30","B30","A31","B31"); @DAT=("A6", "A7", "B6", "B7", "A8", "A9", "B8", "B9", "A10","A11","B10","B11","A12","A13","B12","B13"); # yes, overlaps with @DAT, used only in 2x interleave code path... @K2x=("A6", "B6", "A7", "B7", "A8", "B8", "A9", "B9", "A10","B10","A11","B11","A2", "B2", "A13","B13"); $code.=<<___; .text .if .ASSEMBLER_VERSION<7000000 .asg 0,__TI_EABI__ .endif .if __TI_EABI__ .asg ChaCha20_ctr32,_ChaCha20_ctr32 .endif .asg B3,RA .asg A15,FP .asg B15,SP .global _ChaCha20_ctr32 .align 32 _ChaCha20_ctr32: .asmfunc stack_usage(40+64) MV $LEN,A0 ; reassign [!A0] BNOP RA ; no data || [A0] STW FP,*SP--(40+64) ; save frame pointer and alloca(40+64) || [A0] MV SP,FP [A0] STDW B13:B12,*SP[4+8] ; ABI says so || [A0] MV $KEYB,$KEYA || [A0] MV $COUNTERA,$COUNTERB [A0] STDW B11:B10,*SP[3+8] || [A0] STDW A13:A12,*FP[-3] [A0] STDW A11:A10,*FP[-4] || [A0] MVK 128,$STEP ; 2 * input block size [A0] LDW *${KEYA}[0],@Y[4] ; load key || [A0] LDW *${KEYB}[1],@Y[5] || [A0] MVK 0x00007865,@Y[0] ; synthesize sigma || [A0] MVK 0x0000646e,@Y[1] [A0] LDW *${KEYA}[2],@Y[6] || [A0] LDW *${KEYB}[3],@Y[7] || [A0] MVKH 0x61700000,@Y[0] || [A0] MVKH 0x33200000,@Y[1] LDW *${KEYA}[4],@Y[8] || LDW *${KEYB}[5],@Y[9] || MVK 0x00002d32,@Y[2] || MVK 0x00006574,@Y[3] LDW *${KEYA}[6],@Y[10] || LDW *${KEYB}[7],@Y[11] || MVKH 0x79620000,@Y[2] || MVKH 0x6b200000,@Y[3] LDW *${COUNTERA}[0],@Y[12] ; load counter||nonce || LDW *${COUNTERB}[1],@Y[13] || CMPLTU A0,$STEP,A1 ; is length < 2*blocks? LDW *${COUNTERA}[2],@Y[14] || LDW *${COUNTERB}[3],@Y[15] || [A1] BNOP top1x? [A1] MVK 64,$STEP ; input block size || MVK 10,B0 ; inner loop counter DMV @Y[2],@Y[0],@X[2]:@X[0] ; copy block || DMV @Y[3],@Y[1],@X[3]:@X[1] ||[!A1] STDW @Y[2]:@Y[0],*FP[-12] ; offload key material to stack ||[!A1] STDW @Y[3]:@Y[1],*SP[2] DMV @Y[6],@Y[4],@X[6]:@X[4] || DMV @Y[7],@Y[5],@X[7]:@X[5] ||[!A1] STDW @Y[6]:@Y[4],*FP[-10] ||[!A1] STDW @Y[7]:@Y[5],*SP[4] DMV @Y[10],@Y[8],@X[10]:@X[8] || DMV @Y[11],@Y[9],@X[11]:@X[9] ||[!A1] STDW @Y[10]:@Y[8],*FP[-8] ||[!A1] STDW @Y[11]:@Y[9],*SP[6] DMV @Y[14],@Y[12],@X[14]:@X[12] || DMV @Y[15],@Y[13],@X[15]:@X[13] ||[!A1] MV @Y[12],@K2x[12] ; counter ||[!A1] MV @Y[13],@K2x[13] ||[!A1] STW @Y[14],*FP[-6*2] ||[!A1] STW @Y[15],*SP[8*2] ___ { ################################################################ # 2x interleave gives 50% performance improvement # my ($a0,$a1,$a2,$a3) = (0..3); my ($b0,$b1,$b2,$b3) = (4..7); my ($c0,$c1,$c2,$c3) = (8..11); my ($d0,$d1,$d2,$d3) = (12..15); $code.=<<___; outer2x?: ADD @X[$b1],@X[$a1],@X[$a1] || ADD @X[$b2],@X[$a2],@X[$a2] || ADD @X[$b0],@X[$a0],@X[$a0] || ADD @X[$b3],@X[$a3],@X[$a3] || DMV @Y[2],@Y[0],@K2x[2]:@K2x[0] || DMV @Y[3],@Y[1],@K2x[3]:@K2x[1] XOR @X[$a1],@X[$d1],@X[$d1] || XOR @X[$a2],@X[$d2],@X[$d2] || XOR @X[$a0],@X[$d0],@X[$d0] || XOR @X[$a3],@X[$d3],@X[$d3] || DMV @Y[6],@Y[4],@K2x[6]:@K2x[4] || DMV @Y[7],@Y[5],@K2x[7]:@K2x[5] SWAP2 @X[$d1],@X[$d1] ; rotate by 16 || SWAP2 @X[$d2],@X[$d2] || SWAP2 @X[$d0],@X[$d0] || SWAP2 @X[$d3],@X[$d3] ADD @X[$d1],@X[$c1],@X[$c1] || ADD @X[$d2],@X[$c2],@X[$c2] || ADD @X[$d0],@X[$c0],@X[$c0] || ADD @X[$d3],@X[$c3],@X[$c3] || DMV @Y[10],@Y[8],@K2x[10]:@K2x[8] || DMV @Y[11],@Y[9],@K2x[11]:@K2x[9] XOR @X[$c1],@X[$b1],@X[$b1] || XOR @X[$c2],@X[$b2],@X[$b2] || XOR @X[$c0],@X[$b0],@X[$b0] || XOR @X[$c3],@X[$b3],@X[$b3] || ADD 1,@Y[12],@Y[12] ; adjust counter for 2nd block ROTL @X[$b1],12,@X[$b1] || ROTL @X[$b2],12,@X[$b2] || MV @Y[14],@K2x[14] || MV @Y[15],@K2x[15] top2x?: ROTL @X[$b0],12,@X[$b0] || ROTL @X[$b3],12,@X[$b3] || ADD @Y[$b1],@Y[$a1],@Y[$a1] || ADD @Y[$b2],@Y[$a2],@Y[$a2] ADD @Y[$b0],@Y[$a0],@Y[$a0] || ADD @Y[$b3],@Y[$a3],@Y[$a3] || ADD @X[$b1],@X[$a1],@X[$a1] || ADD @X[$b2],@X[$a2],@X[$a2] || XOR @Y[$a1],@Y[$d1],@Y[$d1] || XOR @Y[$a2],@Y[$d2],@Y[$d2] XOR @Y[$a0],@Y[$d0],@Y[$d0] || XOR @Y[$a3],@Y[$d3],@Y[$d3] || ADD @X[$b0],@X[$a0],@X[$a0] || ADD @X[$b3],@X[$a3],@X[$a3] || XOR @X[$a1],@X[$d1],@X[$d1] || XOR @X[$a2],@X[$d2],@X[$d2] XOR @X[$a0],@X[$d0],@X[$d0] || XOR @X[$a3],@X[$d3],@X[$d3] || ROTL @X[$d1],8,@X[$d1] || ROTL @X[$d2],8,@X[$d2] || SWAP2 @Y[$d1],@Y[$d1] ; rotate by 16 || SWAP2 @Y[$d2],@Y[$d2] || SWAP2 @Y[$d0],@Y[$d0] || SWAP2 @Y[$d3],@Y[$d3] ROTL @X[$d0],8,@X[$d0] || ROTL @X[$d3],8,@X[$d3] || ADD @Y[$d1],@Y[$c1],@Y[$c1] || ADD @Y[$d2],@Y[$c2],@Y[$c2] || ADD @Y[$d0],@Y[$c0],@Y[$c0] || ADD @Y[$d3],@Y[$c3],@Y[$c3] || BNOP middle2x1? ; protect from interrupt ADD @X[$d1],@X[$c1],@X[$c1] || ADD @X[$d2],@X[$c2],@X[$c2] || XOR @Y[$c1],@Y[$b1],@Y[$b1] || XOR @Y[$c2],@Y[$b2],@Y[$b2] || XOR @Y[$c0],@Y[$b0],@Y[$b0] || XOR @Y[$c3],@Y[$b3],@Y[$b3] ADD @X[$d0],@X[$c0],@X[$c0] || ADD @X[$d3],@X[$c3],@X[$c3] || XOR @X[$c1],@X[$b1],@X[$b1] || XOR @X[$c2],@X[$b2],@X[$b2] || ROTL @X[$d1],0,@X[$d2] ; moved to avoid cross-path stall || ROTL @X[$d2],0,@X[$d3] XOR @X[$c0],@X[$b0],@X[$b0] || XOR @X[$c3],@X[$b3],@X[$b3] || MV @X[$d0],@X[$d1] || MV @X[$d3],@X[$d0] || ROTL @Y[$b1],12,@Y[$b1] || ROTL @Y[$b2],12,@Y[$b2] ROTL @X[$b1],7,@X[$b0] ; avoided cross-path stall || ROTL @X[$b2],7,@X[$b1] ROTL @X[$b0],7,@X[$b3] || ROTL @X[$b3],7,@X[$b2] middle2x1?: ROTL @Y[$b0],12,@Y[$b0] || ROTL @Y[$b3],12,@Y[$b3] || ADD @X[$b0],@X[$a0],@X[$a0] || ADD @X[$b1],@X[$a1],@X[$a1] ADD @X[$b2],@X[$a2],@X[$a2] || ADD @X[$b3],@X[$a3],@X[$a3] || ADD @Y[$b1],@Y[$a1],@Y[$a1] || ADD @Y[$b2],@Y[$a2],@Y[$a2] || XOR @X[$a0],@X[$d0],@X[$d0] || XOR @X[$a1],@X[$d1],@X[$d1] XOR @X[$a2],@X[$d2],@X[$d2] || XOR @X[$a3],@X[$d3],@X[$d3] || ADD @Y[$b0],@Y[$a0],@Y[$a0] || ADD @Y[$b3],@Y[$a3],@Y[$a3] || XOR @Y[$a1],@Y[$d1],@Y[$d1] || XOR @Y[$a2],@Y[$d2],@Y[$d2] XOR @Y[$a0],@Y[$d0],@Y[$d0] || XOR @Y[$a3],@Y[$d3],@Y[$d3] || ROTL @Y[$d1],8,@Y[$d1] || ROTL @Y[$d2],8,@Y[$d2] || SWAP2 @X[$d0],@X[$d0] ; rotate by 16 || SWAP2 @X[$d1],@X[$d1] || SWAP2 @X[$d2],@X[$d2] || SWAP2 @X[$d3],@X[$d3] ROTL @Y[$d0],8,@Y[$d0] || ROTL @Y[$d3],8,@Y[$d3] || ADD @X[$d0],@X[$c2],@X[$c2] || ADD @X[$d1],@X[$c3],@X[$c3] || ADD @X[$d2],@X[$c0],@X[$c0] || ADD @X[$d3],@X[$c1],@X[$c1] || BNOP middle2x2? ; protect from interrupt ADD @Y[$d1],@Y[$c1],@Y[$c1] || ADD @Y[$d2],@Y[$c2],@Y[$c2] || XOR @X[$c2],@X[$b0],@X[$b0] || XOR @X[$c3],@X[$b1],@X[$b1] || XOR @X[$c0],@X[$b2],@X[$b2] || XOR @X[$c1],@X[$b3],@X[$b3] ADD @Y[$d0],@Y[$c0],@Y[$c0] || ADD @Y[$d3],@Y[$c3],@Y[$c3] || XOR @Y[$c1],@Y[$b1],@Y[$b1] || XOR @Y[$c2],@Y[$b2],@Y[$b2] || ROTL @Y[$d1],0,@Y[$d2] ; moved to avoid cross-path stall || ROTL @Y[$d2],0,@Y[$d3] XOR @Y[$c0],@Y[$b0],@Y[$b0] || XOR @Y[$c3],@Y[$b3],@Y[$b3] || MV @Y[$d0],@Y[$d1] || MV @Y[$d3],@Y[$d0] || ROTL @X[$b0],12,@X[$b0] || ROTL @X[$b1],12,@X[$b1] ROTL @Y[$b1],7,@Y[$b0] ; avoided cross-path stall || ROTL @Y[$b2],7,@Y[$b1] ROTL @Y[$b0],7,@Y[$b3] || ROTL @Y[$b3],7,@Y[$b2] middle2x2?: ROTL @X[$b2],12,@X[$b2] || ROTL @X[$b3],12,@X[$b3] || ADD @Y[$b0],@Y[$a0],@Y[$a0] || ADD @Y[$b1],@Y[$a1],@Y[$a1] ADD @Y[$b2],@Y[$a2],@Y[$a2] || ADD @Y[$b3],@Y[$a3],@Y[$a3] || ADD @X[$b0],@X[$a0],@X[$a0] || ADD @X[$b1],@X[$a1],@X[$a1] || XOR @Y[$a0],@Y[$d0],@Y[$d0] || XOR @Y[$a1],@Y[$d1],@Y[$d1] XOR @Y[$a2],@Y[$d2],@Y[$d2] || XOR @Y[$a3],@Y[$d3],@Y[$d3] || ADD @X[$b2],@X[$a2],@X[$a2] || ADD @X[$b3],@X[$a3],@X[$a3] || XOR @X[$a0],@X[$d0],@X[$d0] || XOR @X[$a1],@X[$d1],@X[$d1] XOR @X[$a2],@X[$d2],@X[$d2] || XOR @X[$a3],@X[$d3],@X[$d3] || ROTL @X[$d0],8,@X[$d0] || ROTL @X[$d1],8,@X[$d1] || SWAP2 @Y[$d0],@Y[$d0] ; rotate by 16 || SWAP2 @Y[$d1],@Y[$d1] || SWAP2 @Y[$d2],@Y[$d2] || SWAP2 @Y[$d3],@Y[$d3] ROTL @X[$d2],8,@X[$d2] || ROTL @X[$d3],8,@X[$d3] || ADD @Y[$d0],@Y[$c2],@Y[$c2] || ADD @Y[$d1],@Y[$c3],@Y[$c3] || ADD @Y[$d2],@Y[$c0],@Y[$c0] || ADD @Y[$d3],@Y[$c1],@Y[$c1] || BNOP bottom2x1? ; protect from interrupt ADD @X[$d0],@X[$c2],@X[$c2] || ADD @X[$d1],@X[$c3],@X[$c3] || XOR @Y[$c2],@Y[$b0],@Y[$b0] || XOR @Y[$c3],@Y[$b1],@Y[$b1] || XOR @Y[$c0],@Y[$b2],@Y[$b2] || XOR @Y[$c1],@Y[$b3],@Y[$b3] ADD @X[$d2],@X[$c0],@X[$c0] || ADD @X[$d3],@X[$c1],@X[$c1] || XOR @X[$c2],@X[$b0],@X[$b0] || XOR @X[$c3],@X[$b1],@X[$b1] || ROTL @X[$d0],0,@X[$d3] ; moved to avoid cross-path stall || ROTL @X[$d1],0,@X[$d0] XOR @X[$c0],@X[$b2],@X[$b2] || XOR @X[$c1],@X[$b3],@X[$b3] || MV @X[$d2],@X[$d1] || MV @X[$d3],@X[$d2] || ROTL @Y[$b0],12,@Y[$b0] || ROTL @Y[$b1],12,@Y[$b1] ROTL @X[$b0],7,@X[$b1] ; avoided cross-path stall || ROTL @X[$b1],7,@X[$b2] ROTL @X[$b2],7,@X[$b3] || ROTL @X[$b3],7,@X[$b0] || [B0] SUB B0,1,B0 ; decrement inner loop counter bottom2x1?: ROTL @Y[$b2],12,@Y[$b2] || ROTL @Y[$b3],12,@Y[$b3] || [B0] ADD @X[$b1],@X[$a1],@X[$a1] ; modulo-scheduled || [B0] ADD @X[$b2],@X[$a2],@X[$a2] [B0] ADD @X[$b0],@X[$a0],@X[$a0] || [B0] ADD @X[$b3],@X[$a3],@X[$a3] || ADD @Y[$b0],@Y[$a0],@Y[$a0] || ADD @Y[$b1],@Y[$a1],@Y[$a1] || [B0] XOR @X[$a1],@X[$d1],@X[$d1] || [B0] XOR @X[$a2],@X[$d2],@X[$d2] [B0] XOR @X[$a0],@X[$d0],@X[$d0] || [B0] XOR @X[$a3],@X[$d3],@X[$d3] || ADD @Y[$b2],@Y[$a2],@Y[$a2] || ADD @Y[$b3],@Y[$a3],@Y[$a3] || XOR @Y[$a0],@Y[$d0],@Y[$d0] || XOR @Y[$a1],@Y[$d1],@Y[$d1] XOR @Y[$a2],@Y[$d2],@Y[$d2] || XOR @Y[$a3],@Y[$d3],@Y[$d3] || ROTL @Y[$d0],8,@Y[$d0] || ROTL @Y[$d1],8,@Y[$d1] || [B0] SWAP2 @X[$d1],@X[$d1] ; rotate by 16 || [B0] SWAP2 @X[$d2],@X[$d2] || [B0] SWAP2 @X[$d0],@X[$d0] || [B0] SWAP2 @X[$d3],@X[$d3] ROTL @Y[$d2],8,@Y[$d2] || ROTL @Y[$d3],8,@Y[$d3] || [B0] ADD @X[$d1],@X[$c1],@X[$c1] || [B0] ADD @X[$d2],@X[$c2],@X[$c2] || [B0] ADD @X[$d0],@X[$c0],@X[$c0] || [B0] ADD @X[$d3],@X[$c3],@X[$c3] || [B0] BNOP top2x? ; even protects from interrupt ADD @Y[$d0],@Y[$c2],@Y[$c2] || ADD @Y[$d1],@Y[$c3],@Y[$c3] || [B0] XOR @X[$c1],@X[$b1],@X[$b1] || [B0] XOR @X[$c2],@X[$b2],@X[$b2] || [B0] XOR @X[$c0],@X[$b0],@X[$b0] || [B0] XOR @X[$c3],@X[$b3],@X[$b3] ADD @Y[$d2],@Y[$c0],@Y[$c0] || ADD @Y[$d3],@Y[$c1],@Y[$c1] || XOR @Y[$c2],@Y[$b0],@Y[$b0] || XOR @Y[$c3],@Y[$b1],@Y[$b1] || ROTL @Y[$d0],0,@Y[$d3] ; moved to avoid cross-path stall || ROTL @Y[$d1],0,@Y[$d0] XOR @Y[$c0],@Y[$b2],@Y[$b2] || XOR @Y[$c1],@Y[$b3],@Y[$b3] || MV @Y[$d2],@Y[$d1] || MV @Y[$d3],@Y[$d2] || [B0] ROTL @X[$b1],12,@X[$b1] || [B0] ROTL @X[$b2],12,@X[$b2] ROTL @Y[$b0],7,@Y[$b1] ; avoided cross-path stall || ROTL @Y[$b1],7,@Y[$b2] ROTL @Y[$b2],7,@Y[$b3] || ROTL @Y[$b3],7,@Y[$b0] bottom2x2?: ___ } $code.=<<___; ADD @K2x[0],@X[0],@X[0] ; accumulate key material || ADD @K2x[1],@X[1],@X[1] || ADD @K2x[2],@X[2],@X[2] || ADD @K2x[3],@X[3],@X[3] ADD @K2x[0],@Y[0],@Y[0] || ADD @K2x[1],@Y[1],@Y[1] || ADD @K2x[2],@Y[2],@Y[2] || ADD @K2x[3],@Y[3],@Y[3] || LDNDW *${INP}++[8],@DAT[1]:@DAT[0] ADD @K2x[4],@X[4],@X[4] || ADD @K2x[5],@X[5],@X[5] || ADD @K2x[6],@X[6],@X[6] || ADD @K2x[7],@X[7],@X[7] || LDNDW *${INP}[-7],@DAT[3]:@DAT[2] ADD @K2x[4],@Y[4],@Y[4] || ADD @K2x[5],@Y[5],@Y[5] || ADD @K2x[6],@Y[6],@Y[6] || ADD @K2x[7],@Y[7],@Y[7] || LDNDW *${INP}[-6],@DAT[5]:@DAT[4] ADD @K2x[8],@X[8],@X[8] || ADD @K2x[9],@X[9],@X[9] || ADD @K2x[10],@X[10],@X[10] || ADD @K2x[11],@X[11],@X[11] || LDNDW *${INP}[-5],@DAT[7]:@DAT[6] ADD @K2x[8],@Y[8],@Y[8] || ADD @K2x[9],@Y[9],@Y[9] || ADD @K2x[10],@Y[10],@Y[10] || ADD @K2x[11],@Y[11],@Y[11] || LDNDW *${INP}[-4],@DAT[9]:@DAT[8] ADD @K2x[12],@X[12],@X[12] || ADD @K2x[13],@X[13],@X[13] || ADD @K2x[14],@X[14],@X[14] || ADD @K2x[15],@X[15],@X[15] || LDNDW *${INP}[-3],@DAT[11]:@DAT[10] ADD @K2x[12],@Y[12],@Y[12] || ADD @K2x[13],@Y[13],@Y[13] || ADD @K2x[14],@Y[14],@Y[14] || ADD @K2x[15],@Y[15],@Y[15] || LDNDW *${INP}[-2],@DAT[13]:@DAT[12] ADD 1,@Y[12],@Y[12] ; adjust counter for 2nd block || ADD 2,@K2x[12],@K2x[12] ; increment counter || LDNDW *${INP}[-1],@DAT[15]:@DAT[14] .if .BIG_ENDIAN SWAP2 @X[0],@X[0] || SWAP2 @X[1],@X[1] || SWAP2 @X[2],@X[2] || SWAP2 @X[3],@X[3] SWAP2 @X[4],@X[4] || SWAP2 @X[5],@X[5] || SWAP2 @X[6],@X[6] || SWAP2 @X[7],@X[7] SWAP2 @X[8],@X[8] || SWAP2 @X[9],@X[9] || SWAP4 @X[0],@X[1] || SWAP4 @X[1],@X[0] SWAP2 @X[10],@X[10] || SWAP2 @X[11],@X[11] || SWAP4 @X[2],@X[3] || SWAP4 @X[3],@X[2] SWAP2 @X[12],@X[12] || SWAP2 @X[13],@X[13] || SWAP4 @X[4],@X[5] || SWAP4 @X[5],@X[4] SWAP2 @X[14],@X[14] || SWAP2 @X[15],@X[15] || SWAP4 @X[6],@X[7] || SWAP4 @X[7],@X[6] SWAP4 @X[8],@X[9] || SWAP4 @X[9],@X[8] || SWAP2 @Y[0],@Y[0] || SWAP2 @Y[1],@Y[1] SWAP4 @X[10],@X[11] || SWAP4 @X[11],@X[10] || SWAP2 @Y[2],@Y[2] || SWAP2 @Y[3],@Y[3] SWAP4 @X[12],@X[13] || SWAP4 @X[13],@X[12] || SWAP2 @Y[4],@Y[4] || SWAP2 @Y[5],@Y[5] SWAP4 @X[14],@X[15] || SWAP4 @X[15],@X[14] || SWAP2 @Y[6],@Y[6] || SWAP2 @Y[7],@Y[7] SWAP2 @Y[8],@Y[8] || SWAP2 @Y[9],@Y[9] || SWAP4 @Y[0],@Y[1] || SWAP4 @Y[1],@Y[0] SWAP2 @Y[10],@Y[10] || SWAP2 @Y[11],@Y[11] || SWAP4 @Y[2],@Y[3] || SWAP4 @Y[3],@Y[2] SWAP2 @Y[12],@Y[12] || SWAP2 @Y[13],@Y[13] || SWAP4 @Y[4],@Y[5] || SWAP4 @Y[5],@Y[4] SWAP2 @Y[14],@Y[14] || SWAP2 @Y[15],@Y[15] || SWAP4 @Y[6],@Y[7] || SWAP4 @Y[7],@Y[6] SWAP4 @Y[8],@Y[9] || SWAP4 @Y[9],@Y[8] SWAP4 @Y[10],@Y[11] || SWAP4 @Y[11],@Y[10] SWAP4 @Y[12],@Y[13] || SWAP4 @Y[13],@Y[12] SWAP4 @Y[14],@Y[15] || SWAP4 @Y[15],@Y[14] .endif XOR @DAT[0],@X[0],@X[0] ; xor 1st block || XOR @DAT[3],@X[3],@X[3] || XOR @DAT[2],@X[2],@X[1] || XOR @DAT[1],@X[1],@X[2] || LDNDW *${INP}++[8],@DAT[1]:@DAT[0] XOR @DAT[4],@X[4],@X[4] || XOR @DAT[7],@X[7],@X[7] || LDNDW *${INP}[-7],@DAT[3]:@DAT[2] XOR @DAT[6],@X[6],@X[5] || XOR @DAT[5],@X[5],@X[6] || LDNDW *${INP}[-6],@DAT[5]:@DAT[4] XOR @DAT[8],@X[8],@X[8] || XOR @DAT[11],@X[11],@X[11] || LDNDW *${INP}[-5],@DAT[7]:@DAT[6] XOR @DAT[10],@X[10],@X[9] || XOR @DAT[9],@X[9],@X[10] || LDNDW *${INP}[-4],@DAT[9]:@DAT[8] XOR @DAT[12],@X[12],@X[12] || XOR @DAT[15],@X[15],@X[15] || LDNDW *${INP}[-3],@DAT[11]:@DAT[10] XOR @DAT[14],@X[14],@X[13] || XOR @DAT[13],@X[13],@X[14] || LDNDW *${INP}[-2],@DAT[13]:@DAT[12] [A0] SUB A0,$STEP,A0 ; SUB A0,128,A0 || LDNDW *${INP}[-1],@DAT[15]:@DAT[14] XOR @Y[0],@DAT[0],@DAT[0] ; xor 2nd block || XOR @Y[1],@DAT[1],@DAT[1] || STNDW @X[2]:@X[0],*${OUT}++[8] XOR @Y[2],@DAT[2],@DAT[2] || XOR @Y[3],@DAT[3],@DAT[3] || STNDW @X[3]:@X[1],*${OUT}[-7] XOR @Y[4],@DAT[4],@DAT[4] || [A0] LDDW *FP[-12],@X[2]:@X[0] ; re-load key material from stack || [A0] LDDW *SP[2], @X[3]:@X[1] XOR @Y[5],@DAT[5],@DAT[5] || STNDW @X[6]:@X[4],*${OUT}[-6] XOR @Y[6],@DAT[6],@DAT[6] || XOR @Y[7],@DAT[7],@DAT[7] || STNDW @X[7]:@X[5],*${OUT}[-5] XOR @Y[8],@DAT[8],@DAT[8] || [A0] LDDW *FP[-10],@X[6]:@X[4] || [A0] LDDW *SP[4], @X[7]:@X[5] XOR @Y[9],@DAT[9],@DAT[9] || STNDW @X[10]:@X[8],*${OUT}[-4] XOR @Y[10],@DAT[10],@DAT[10] || XOR @Y[11],@DAT[11],@DAT[11] || STNDW @X[11]:@X[9],*${OUT}[-3] XOR @Y[12],@DAT[12],@DAT[12] || [A0] LDDW *FP[-8], @X[10]:@X[8] || [A0] LDDW *SP[6], @X[11]:@X[9] XOR @Y[13],@DAT[13],@DAT[13] || STNDW @X[14]:@X[12],*${OUT}[-2] XOR @Y[14],@DAT[14],@DAT[14] || XOR @Y[15],@DAT[15],@DAT[15] || STNDW @X[15]:@X[13],*${OUT}[-1] [A0] MV @K2x[12],@X[12] || [A0] MV @K2x[13],@X[13] || [A0] LDW *FP[-6*2], @X[14] || [A0] LDW *SP[8*2], @X[15] [A0] DMV @X[2],@X[0],@Y[2]:@Y[0] ; duplicate key material || STNDW @DAT[1]:@DAT[0],*${OUT}++[8] [A0] DMV @X[3],@X[1],@Y[3]:@Y[1] || STNDW @DAT[3]:@DAT[2],*${OUT}[-7] [A0] DMV @X[6],@X[4],@Y[6]:@Y[4] || STNDW @DAT[5]:@DAT[4],*${OUT}[-6] || CMPLTU A0,$STEP,A1 ; is remaining length < 2*blocks? ||[!A0] BNOP epilogue? [A0] DMV @X[7],@X[5],@Y[7]:@Y[5] || STNDW @DAT[7]:@DAT[6],*${OUT}[-5] ||[!A1] BNOP outer2x? [A0] DMV @X[10],@X[8],@Y[10]:@Y[8] || STNDW @DAT[9]:@DAT[8],*${OUT}[-4] [A0] DMV @X[11],@X[9],@Y[11]:@Y[9] || STNDW @DAT[11]:@DAT[10],*${OUT}[-3] [A0] DMV @X[14],@X[12],@Y[14]:@Y[12] || STNDW @DAT[13]:@DAT[12],*${OUT}[-2] [A0] DMV @X[15],@X[13],@Y[15]:@Y[13] || STNDW @DAT[15]:@DAT[14],*${OUT}[-1] ;;===== branch to epilogue? is taken here [A1] MVK 64,$STEP || [A0] MVK 10,B0 ; inner loop counter ;;===== branch to outer2x? is taken here ___ { my ($a0,$a1,$a2,$a3) = (0..3); my ($b0,$b1,$b2,$b3) = (4..7); my ($c0,$c1,$c2,$c3) = (8..11); my ($d0,$d1,$d2,$d3) = (12..15); $code.=<<___; top1x?: ADD @X[$b1],@X[$a1],@X[$a1] || ADD @X[$b2],@X[$a2],@X[$a2] ADD @X[$b0],@X[$a0],@X[$a0] || ADD @X[$b3],@X[$a3],@X[$a3] || XOR @X[$a1],@X[$d1],@X[$d1] || XOR @X[$a2],@X[$d2],@X[$d2] XOR @X[$a0],@X[$d0],@X[$d0] || XOR @X[$a3],@X[$d3],@X[$d3] || SWAP2 @X[$d1],@X[$d1] ; rotate by 16 || SWAP2 @X[$d2],@X[$d2] SWAP2 @X[$d0],@X[$d0] || SWAP2 @X[$d3],@X[$d3] || ADD @X[$d1],@X[$c1],@X[$c1] || ADD @X[$d2],@X[$c2],@X[$c2] ADD @X[$d0],@X[$c0],@X[$c0] || ADD @X[$d3],@X[$c3],@X[$c3] || XOR @X[$c1],@X[$b1],@X[$b1] || XOR @X[$c2],@X[$b2],@X[$b2] XOR @X[$c0],@X[$b0],@X[$b0] || XOR @X[$c3],@X[$b3],@X[$b3] || ROTL @X[$b1],12,@X[$b1] || ROTL @X[$b2],12,@X[$b2] ROTL @X[$b0],12,@X[$b0] || ROTL @X[$b3],12,@X[$b3] ADD @X[$b1],@X[$a1],@X[$a1] || ADD @X[$b2],@X[$a2],@X[$a2] ADD @X[$b0],@X[$a0],@X[$a0] || ADD @X[$b3],@X[$a3],@X[$a3] || XOR @X[$a1],@X[$d1],@X[$d1] || XOR @X[$a2],@X[$d2],@X[$d2] XOR @X[$a0],@X[$d0],@X[$d0] || XOR @X[$a3],@X[$d3],@X[$d3] || ROTL @X[$d1],8,@X[$d1] || ROTL @X[$d2],8,@X[$d2] ROTL @X[$d0],8,@X[$d0] || ROTL @X[$d3],8,@X[$d3] || BNOP middle1x? ; protect from interrupt ADD @X[$d1],@X[$c1],@X[$c1] || ADD @X[$d2],@X[$c2],@X[$c2] ADD @X[$d0],@X[$c0],@X[$c0] || ADD @X[$d3],@X[$c3],@X[$c3] || XOR @X[$c1],@X[$b1],@X[$b1] || XOR @X[$c2],@X[$b2],@X[$b2] || ROTL @X[$d1],0,@X[$d2] ; moved to avoid cross-path stall || ROTL @X[$d2],0,@X[$d3] XOR @X[$c0],@X[$b0],@X[$b0] || XOR @X[$c3],@X[$b3],@X[$b3] || ROTL @X[$d0],0,@X[$d1] || ROTL @X[$d3],0,@X[$d0] ROTL @X[$b1],7,@X[$b0] ; avoided cross-path stall || ROTL @X[$b2],7,@X[$b1] ROTL @X[$b0],7,@X[$b3] || ROTL @X[$b3],7,@X[$b2] middle1x?: ADD @X[$b0],@X[$a0],@X[$a0] || ADD @X[$b1],@X[$a1],@X[$a1] ADD @X[$b2],@X[$a2],@X[$a2] || ADD @X[$b3],@X[$a3],@X[$a3] || XOR @X[$a0],@X[$d0],@X[$d0] || XOR @X[$a1],@X[$d1],@X[$d1] XOR @X[$a2],@X[$d2],@X[$d2] || XOR @X[$a3],@X[$d3],@X[$d3] || SWAP2 @X[$d0],@X[$d0] ; rotate by 16 || SWAP2 @X[$d1],@X[$d1] SWAP2 @X[$d2],@X[$d2] || SWAP2 @X[$d3],@X[$d3] || ADD @X[$d0],@X[$c2],@X[$c2] || ADD @X[$d1],@X[$c3],@X[$c3] ADD @X[$d2],@X[$c0],@X[$c0] || ADD @X[$d3],@X[$c1],@X[$c1] || XOR @X[$c2],@X[$b0],@X[$b0] || XOR @X[$c3],@X[$b1],@X[$b1] XOR @X[$c0],@X[$b2],@X[$b2] || XOR @X[$c1],@X[$b3],@X[$b3] || ROTL @X[$b0],12,@X[$b0] || ROTL @X[$b1],12,@X[$b1] ROTL @X[$b2],12,@X[$b2] || ROTL @X[$b3],12,@X[$b3] ADD @X[$b0],@X[$a0],@X[$a0] || ADD @X[$b1],@X[$a1],@X[$a1] || [B0] SUB B0,1,B0 ; decrement inner loop counter ADD @X[$b2],@X[$a2],@X[$a2] || ADD @X[$b3],@X[$a3],@X[$a3] || XOR @X[$a0],@X[$d0],@X[$d0] || XOR @X[$a1],@X[$d1],@X[$d1] XOR @X[$a2],@X[$d2],@X[$d2] || XOR @X[$a3],@X[$d3],@X[$d3] || ROTL @X[$d0],8,@X[$d0] || ROTL @X[$d1],8,@X[$d1] ROTL @X[$d2],8,@X[$d2] || ROTL @X[$d3],8,@X[$d3] || [B0] BNOP top1x? ; even protects from interrupt ADD @X[$d0],@X[$c2],@X[$c2] || ADD @X[$d1],@X[$c3],@X[$c3] ADD @X[$d2],@X[$c0],@X[$c0] || ADD @X[$d3],@X[$c1],@X[$c1] || XOR @X[$c2],@X[$b0],@X[$b0] || XOR @X[$c3],@X[$b1],@X[$b1] || ROTL @X[$d0],0,@X[$d3] ; moved to avoid cross-path stall || ROTL @X[$d1],0,@X[$d0] XOR @X[$c0],@X[$b2],@X[$b2] || XOR @X[$c1],@X[$b3],@X[$b3] || ROTL @X[$d2],0,@X[$d1] || ROTL @X[$d3],0,@X[$d2] ROTL @X[$b0],7,@X[$b1] ; avoided cross-path stall || ROTL @X[$b1],7,@X[$b2] ROTL @X[$b2],7,@X[$b3] || ROTL @X[$b3],7,@X[$b0] ||[!B0] CMPLTU A0,$STEP,A1 ; less than 64 bytes left? bottom1x?: ___ } $code.=<<___; ADD @Y[0],@X[0],@X[0] ; accumulate key material || ADD @Y[1],@X[1],@X[1] || ADD @Y[2],@X[2],@X[2] || ADD @Y[3],@X[3],@X[3] ||[!A1] LDNDW *${INP}++[8],@DAT[1]:@DAT[0] || [A1] BNOP tail? ADD @Y[4],@X[4],@X[4] || ADD @Y[5],@X[5],@X[5] || ADD @Y[6],@X[6],@X[6] || ADD @Y[7],@X[7],@X[7] ||[!A1] LDNDW *${INP}[-7],@DAT[3]:@DAT[2] ADD @Y[8],@X[8],@X[8] || ADD @Y[9],@X[9],@X[9] || ADD @Y[10],@X[10],@X[10] || ADD @Y[11],@X[11],@X[11] ||[!A1] LDNDW *${INP}[-6],@DAT[5]:@DAT[4] ADD @Y[12],@X[12],@X[12] || ADD @Y[13],@X[13],@X[13] || ADD @Y[14],@X[14],@X[14] || ADD @Y[15],@X[15],@X[15] ||[!A1] LDNDW *${INP}[-5],@DAT[7]:@DAT[6] [!A1] LDNDW *${INP}[-4],@DAT[9]:@DAT[8] [!A1] LDNDW *${INP}[-3],@DAT[11]:@DAT[10] LDNDW *${INP}[-2],@DAT[13]:@DAT[12] LDNDW *${INP}[-1],@DAT[15]:@DAT[14] .if .BIG_ENDIAN SWAP2 @X[0],@X[0] || SWAP2 @X[1],@X[1] || SWAP2 @X[2],@X[2] || SWAP2 @X[3],@X[3] SWAP2 @X[4],@X[4] || SWAP2 @X[5],@X[5] || SWAP2 @X[6],@X[6] || SWAP2 @X[7],@X[7] SWAP2 @X[8],@X[8] || SWAP2 @X[9],@X[9] || SWAP4 @X[0],@X[1] || SWAP4 @X[1],@X[0] SWAP2 @X[10],@X[10] || SWAP2 @X[11],@X[11] || SWAP4 @X[2],@X[3] || SWAP4 @X[3],@X[2] SWAP2 @X[12],@X[12] || SWAP2 @X[13],@X[13] || SWAP4 @X[4],@X[5] || SWAP4 @X[5],@X[4] SWAP2 @X[14],@X[14] || SWAP2 @X[15],@X[15] || SWAP4 @X[6],@X[7] || SWAP4 @X[7],@X[6] SWAP4 @X[8],@X[9] || SWAP4 @X[9],@X[8] SWAP4 @X[10],@X[11] || SWAP4 @X[11],@X[10] SWAP4 @X[12],@X[13] || SWAP4 @X[13],@X[12] SWAP4 @X[14],@X[15] || SWAP4 @X[15],@X[14] .else NOP 1 .endif XOR @X[0],@DAT[0],@DAT[0] ; xor with input || XOR @X[1],@DAT[1],@DAT[1] || XOR @X[2],@DAT[2],@DAT[2] || XOR @X[3],@DAT[3],@DAT[3] || [A0] SUB A0,$STEP,A0 ; SUB A0,64,A0 XOR @X[4],@DAT[4],@DAT[4] || XOR @X[5],@DAT[5],@DAT[5] || XOR @X[6],@DAT[6],@DAT[6] || XOR @X[7],@DAT[7],@DAT[7] || STNDW @DAT[1]:@DAT[0],*${OUT}++[8] XOR @X[8],@DAT[8],@DAT[8] || XOR @X[9],@DAT[9],@DAT[9] || XOR @X[10],@DAT[10],@DAT[10] || XOR @X[11],@DAT[11],@DAT[11] || STNDW @DAT[3]:@DAT[2],*${OUT}[-7] XOR @X[12],@DAT[12],@DAT[12] || XOR @X[13],@DAT[13],@DAT[13] || XOR @X[14],@DAT[14],@DAT[14] || XOR @X[15],@DAT[15],@DAT[15] || STNDW @DAT[5]:@DAT[4],*${OUT}[-6] || [A0] BNOP top1x? [A0] DMV @Y[2],@Y[0],@X[2]:@X[0] ; duplicate key material || [A0] DMV @Y[3],@Y[1],@X[3]:@X[1] || STNDW @DAT[7]:@DAT[6],*${OUT}[-5] [A0] DMV @Y[6],@Y[4],@X[6]:@X[4] || [A0] DMV @Y[7],@Y[5],@X[7]:@X[5] || STNDW @DAT[9]:@DAT[8],*${OUT}[-4] [A0] DMV @Y[10],@Y[8],@X[10]:@X[8] || [A0] DMV @Y[11],@Y[9],@X[11]:@X[9] || [A0] ADD 1,@Y[12],@Y[12] ; increment counter || STNDW @DAT[11]:@DAT[10],*${OUT}[-3] [A0] DMV @Y[14],@Y[12],@X[14]:@X[12] || [A0] DMV @Y[15],@Y[13],@X[15]:@X[13] || STNDW @DAT[13]:@DAT[12],*${OUT}[-2] [A0] MVK 10,B0 ; inner loop counter || STNDW @DAT[15]:@DAT[14],*${OUT}[-1] ;;===== branch to top1x? is taken here epilogue?: LDDW *FP[-4],A11:A10 ; ABI says so LDDW *FP[-3],A13:A12 || LDDW *SP[3+8],B11:B10 LDDW *SP[4+8],B13:B12 || BNOP RA LDW *++SP(40+64),FP ; restore frame pointer NOP 4 tail?: LDBU *${INP}++[1],B24 ; load byte by byte || SUB A0,1,A0 || SUB A0,1,B1 [!B1] BNOP epilogue? ; interrupts are disabled for whole time || [A0] LDBU *${INP}++[1],B24 || [A0] SUB A0,1,A0 || SUB B1,1,B1 [!B1] BNOP epilogue? || [A0] LDBU *${INP}++[1],B24 || [A0] SUB A0,1,A0 || SUB B1,1,B1 [!B1] BNOP epilogue? || ROTL @X[0],0,A24 || [A0] LDBU *${INP}++[1],B24 || [A0] SUB A0,1,A0 || SUB B1,1,B1 [!B1] BNOP epilogue? || ROTL @X[0],24,A24 || [A0] LDBU *${INP}++[1],A24 || [A0] SUB A0,1,A0 || SUB B1,1,B1 [!B1] BNOP epilogue? || ROTL @X[0],16,A24 || [A0] LDBU *${INP}++[1],A24 || [A0] SUB A0,1,A0 || SUB B1,1,B1 || XOR A24,B24,B25 STB B25,*${OUT}++[1] ; store byte by byte ||[!B1] BNOP epilogue? || ROTL @X[0],8,A24 || [A0] LDBU *${INP}++[1],A24 || [A0] SUB A0,1,A0 || SUB B1,1,B1 || XOR A24,B24,B25 STB B25,*${OUT}++[1] ___ sub TAIL_STEP { my $Xi= shift; my $T = ($Xi=~/^B/?"B24":"A24"); # match @X[i] to avoid cross path my $D = $T; $D=~tr/AB/BA/; my $O = $D; $O=~s/24/25/; $code.=<<___; ||[!B1] BNOP epilogue? || ROTL $Xi,0,$T || [A0] LDBU *${INP}++[1],$D || [A0] SUB A0,1,A0 || SUB B1,1,B1 || XOR A24,B24,$O STB $O,*${OUT}++[1] ||[!B1] BNOP epilogue? || ROTL $Xi,24,$T || [A0] LDBU *${INP}++[1],$T || [A0] SUB A0,1,A0 || SUB B1,1,B1 || XOR A24,B24,$O STB $O,*${OUT}++[1] ||[!B1] BNOP epilogue? || ROTL $Xi,16,$T || [A0] LDBU *${INP}++[1],$T || [A0] SUB A0,1,A0 || SUB B1,1,B1 || XOR A24,B24,$O STB $O,*${OUT}++[1] ||[!B1] BNOP epilogue? || ROTL $Xi,8,$T || [A0] LDBU *${INP}++[1],$T || [A0] SUB A0,1,A0 || SUB B1,1,B1 || XOR A24,B24,$O STB $O,*${OUT}++[1] ___ } foreach (1..14) { TAIL_STEP(@X[$_]); } $code.=<<___; ||[!B1] BNOP epilogue? || ROTL @X[15],0,B24 || XOR A24,B24,A25 STB A25,*${OUT}++[1] || ROTL @X[15],24,B24 || XOR A24,B24,A25 STB A25,*${OUT}++[1] || ROTL @X[15],16,B24 || XOR A24,B24,A25 STB A25,*${OUT}++[1] || XOR A24,B24,A25 STB A25,*${OUT}++[1] || XOR A24,B24,B25 STB B25,*${OUT}++[1] .endasmfunc .sect .const .cstring "ChaCha20 for C64x+, CRYPTOGAMS by <appro\@openssl.org>" .align 4 ___ print $code; close STDOUT or die "error closing STDOUT: $!";

{ "language": "Assembly" }

/*********************************************************************/ /* Copyright 2009, 2010 The University of Texas at Austin. */ /* All rights reserved. */ /* */ /* Redistribution and use in source and binary forms, with or */ /* without modification, are permitted provided that the following */ /* conditions are met: */ /* */ /* 1. Redistributions of source code must retain the above */ /* copyright notice, this list of conditions and the following */ /* disclaimer. */ /* */ /* 2. Redistributions in binary form must reproduce the above */ /* copyright notice, this list of conditions and the following */ /* disclaimer in the documentation and/or other materials */ /* provided with the distribution. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */ /* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */ /* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ /* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ /* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */ /* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */ /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */ /* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */ /* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */ /* POSSIBILITY OF SUCH DAMAGE. */ /* */ /* The views and conclusions contained in the software and */ /* documentation are those of the authors and should not be */ /* interpreted as representing official policies, either expressed */ /* or implied, of The University of Texas at Austin. */ /*********************************************************************/ #define ASSEMBLER #include "common.h" #include "version.h" #define PREFETCHSIZE 88 #define N $16 #define X $17 #define INCX $18 #define I $19 #define s0 $f0 #define s1 $f1 #define s2 $f10 #define s3 $f11 #define a0 $f12 #define a1 $f13 #define a2 $f14 #define a3 $f15 #define a4 $f16 #define a5 $f17 #define a6 $f18 #define a7 $f19 #define t0 $f20 #define t1 $f21 #define t2 $f22 #define t3 $f23 PROLOGUE PROFCODE fclr s0 unop fclr t0 addq INCX, INCX, INCX fclr s1 unop fclr t1 ble N, $L999 fclr s2 sra N, 2, I fclr s3 ble I, $L15 LD a0, 0 * SIZE(X) fclr t2 LD a1, 1 * SIZE(X) SXADDQ INCX, X, X LD a2, 0 * SIZE(X) fclr t3 LD a3, 1 * SIZE(X) SXADDQ INCX, X, X LD a4, 0 * SIZE(X) LD a5, 1 * SIZE(X) SXADDQ INCX, X, X lda I, -1(I) ble I, $L13 .align 4 $L12: ADD s0, t0, s0 ldl $31, PREFETCHSIZE * SIZE(X) fmov a0, t0 lda I, -1(I) ADD s1, t1, s1 LD a6, 0 * SIZE(X) fmov a1, t1 unop ADD s2, t2, s2 LD a7, 1 * SIZE(X) fmov a2, t2 SXADDQ INCX, X, X ADD s3, t3, s3 LD a0, 0 * SIZE(X) fmov a3, t3 unop ADD s0, t0, s0 LD a1, 1 * SIZE(X) fmov a4, t0 SXADDQ INCX, X, X ADD s1, t1, s1 LD a2, 0 * SIZE(X) fmov a5, t1 unop ADD s2, t2, s2 LD a3, 1 * SIZE(X) fmov a6, t2 SXADDQ INCX, X, X ADD s3, t3, s3 LD a4, 0 * SIZE(X) fmov a7, t3 unop LD a5, 1 * SIZE(X) unop SXADDQ INCX, X, X bne I, $L12 .align 4 $L13: ADD s0, t0, s0 LD a6, 0 * SIZE(X) fmov a0, t0 ADD s1, t1, s1 LD a7, 1 * SIZE(X) fmov a1, t1 SXADDQ INCX, X, X ADD s2, t2, s2 fmov a2, t2 ADD s3, t3, s3 fmov a3, t3 ADD s0, t0, s0 fmov a4, t0 ADD s1, t1, s1 fmov a5, t1 ADD s2, t2, s2 fmov a6, t2 ADD s3, t3, s3 fmov a7, t3 ADD s2, t2, s2 ADD s3, t3, s3 .align 4 $L15: ADD s0, s2, s0 and N, 3, I ADD s1, s3, s1 ble I, $L999 .align 4 $L17: ADD s0, t0, s0 LD a0, 0 * SIZE(X) fmov a0, t0 lda I, -1(I) ADD s1, t1, s1 LD a1, 1 * SIZE(X) fmov a1, t1 SXADDQ INCX, X, X bne I, $L17 .align 4 $L999: ADD s0, t0, s0 ADD s1, t1, s1 ADD s0, s1, s0 ret EPILOGUE

{ "language": "Assembly" }

; RUN: llc < %s -march=x86-64 | grep call ; PR4688 ; Return types can be empty structs, which can be awkward. target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-unknown-linux-gnu" define void @_ZN15QtSharedPointer22internalSafetyCheckAddEPVKv(i8* %ptr) { entry: %0 = call { } @_ZNK5QHashIPv15QHashDummyValueE5valueERKS0_(i8** undef) ; <{ }> [#uses=0] ret void } declare hidden { } @_ZNK5QHashIPv15QHashDummyValueE5valueERKS0_(i8** nocapture) nounwind

{ "language": "Assembly" }

// RUN: %clang_cc1 -E -frewrite-includes -I %S/Inputs %s | FileCheck %s --check-prefix=GNU // RUN: %clang_cc1 -E -frewrite-includes -fuse-line-directives -I %S/Inputs %s | FileCheck %s --check-prefix=LINE #include "test.h" int f() { return x; } #include "empty.h" // GNU: {{^}}# 1 "{{.*}}rewrite-includes-line-markers.c" // GNU: {{^}}#include "test.h" // GNU: {{^}}# 1 "{{.*}}test.h" // GNU: {{^}}#include "test2.h" // GNU: {{^}}# 1 "{{.*}}test2.h" // GNU: {{^}}int x; // GNU: {{^}}# 4 "{{.*}}rewrite-includes-line-markers.c" 2 // GNU: {{^}}int f() { return x; } // GNU: {{^}} // GNU: {{^}}# 1 "{{.*}}empty.h" 1 // GNU: {{^}}# 7 "{{.*}}rewrite-includes-line-markers.c" 2 // LINE: {{^}}#line 1 "{{.*}}rewrite-includes-line-markers.c" // LINE: {{^}}#include "test.h" // LINE: {{^}}#line 1 "{{.*}}test.h" // LINE: {{^}}#include "test2.h" // LINE: {{^}}#line 1 "{{.*}}test2.h" // LINE: {{^}}int x; // LINE: {{^}}#line 4 "{{.*}}rewrite-includes-line-markers.c" // LINE: {{^}}int f() { return x; } // LINE: {{^}} // LINE: {{^}}#line 1 "{{.*}}empty.h" // LINE: {{^}}#line 7 "{{.*}}rewrite-includes-line-markers.c"

{ "language": "Assembly" }

--- gcc/config/avr/avr.c.old 2008-11-04 14:14:27.405669400 -0700 +++ gcc/config/avr/avr.c 2008-11-04 14:14:55.772086800 -0700 @@ -283,6 +283,7 @@ static const struct mcu_type_s avr_mcu_t { "atmega32m1", ARCH_AVR5, "__AVR_ATmega32M1__" }, { "atmega32c1", ARCH_AVR5, "__AVR_ATmega32C1__" }, { "atmega32u4", ARCH_AVR5, "__AVR_ATmega32U4__" }, + { "atmega32u6", ARCH_AVR5, "__AVR_ATmega32U6__" }, { "at90usb646", ARCH_AVR5, "__AVR_AT90USB646__" }, { "at90usb647", ARCH_AVR5, "__AVR_AT90USB647__" }, { "at94k", ARCH_AVR5, "__AVR_AT94K__" }, --- gcc/config/avr/avr.h.old 2008-11-04 14:15:07.629280600 -0700 +++ gcc/config/avr/avr.h 2008-11-04 14:16:11.692586600 -0700 @@ -871,7 +871,7 @@ mmcu=*:-mmcu=%*}" mmcu=at90pwm316|\ mmcu=atmega32c1|\ mmcu=atmega32m1|\ - mmcu=atmega32u4|\ + mmcu=atmega32u*|\ mmcu=at90usb64*|\ mmcu=at90usb128*|\ mmcu=at94k: -m avr5}\ @@ -908,7 +908,7 @@ mmcu=*:-mmcu=%*}" mmcu=at90pwm*|\ mmcu=atmega32c1|\ mmcu=atmega32m1|\ - mmcu=atmega32u4|\ + mmcu=atmega32u*|\ mmcu=at90usb*: -Tdata 0x800100}\ %{mmcu=atmega640|\ mmcu=atmega1280|\ --- gcc/config/avr/t-avr.old 2008-11-04 14:17:13.610006800 -0700 +++ gcc/config/avr/t-avr 2008-11-04 14:17:24.793674400 -0700 @@ -118,6 +118,7 @@ MULTILIB_MATCHES = \ mmcu?avr5=mmcu?atmega32c1 \ mmcu?avr5=mmcu?atmega32m1 \ mmcu?avr5=mmcu?atmega32u4 \ + mmcu?avr5=mmcu?atmega32u6 \ mmcu?avr5=mmcu?at90usb646 \ mmcu?avr5=mmcu?at90usb647 \ mmcu?avr5=mmcu?at94k \

{ "language": "Assembly" }

// Copyright 2009 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build !gccgo #include "textflag.h" // // System calls for 386, Linux // // See ../runtime/sys_linux_386.s for the reason why we always use int 0x80 // instead of the glibc-specific "CALL 0x10(GS)". #define INVOKE_SYSCALL INT $0x80 // Just jump to package syscall's implementation for all these functions. // The runtime may know about them. TEXT ·Syscall(SB),NOSPLIT,$0-28 JMP syscall·Syscall(SB) TEXT ·Syscall6(SB),NOSPLIT,$0-40 JMP syscall·Syscall6(SB) TEXT ·SyscallNoError(SB),NOSPLIT,$0-24 CALL runtime·entersyscall(SB) MOVL trap+0(FP), AX // syscall entry MOVL a1+4(FP), BX MOVL a2+8(FP), CX MOVL a3+12(FP), DX MOVL $0, SI MOVL $0, DI INVOKE_SYSCALL MOVL AX, r1+16(FP) MOVL DX, r2+20(FP) CALL runtime·exitsyscall(SB) RET TEXT ·RawSyscall(SB),NOSPLIT,$0-28 JMP syscall·RawSyscall(SB) TEXT ·RawSyscall6(SB),NOSPLIT,$0-40 JMP syscall·RawSyscall6(SB) TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-24 MOVL trap+0(FP), AX // syscall entry MOVL a1+4(FP), BX MOVL a2+8(FP), CX MOVL a3+12(FP), DX MOVL $0, SI MOVL $0, DI INVOKE_SYSCALL MOVL AX, r1+16(FP) MOVL DX, r2+20(FP) RET TEXT ·socketcall(SB),NOSPLIT,$0-36 JMP syscall·socketcall(SB) TEXT ·rawsocketcall(SB),NOSPLIT,$0-36 JMP syscall·rawsocketcall(SB) TEXT ·seek(SB),NOSPLIT,$0-28 JMP syscall·seek(SB)

{ "language": "Assembly" }

1d0 < line 0 2a2 > line between 1 and 2 4,5c4,5 < line 3 < line 4 --- > adjusted line 3 > adjusted line 4 7,8d6 < line 6 < line 7

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0xbf8e2427 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.138767 0xbf91c321 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.167949 0xbf957f59 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.198075 0xbf995a85 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.229202 0xbf9d567b // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.261390 0xbfa17537 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.294704 0xbfa5b8df // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.329216 0xbfaa23c3 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.365003 0xbfaeb868 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.402146 0xbfb37988 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.440738 0xbfb86a1c // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.480877 0xbfbd8d5e // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.522670 0xbfc2e6d7 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.566235 0xbfc87a64 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.611702 0xbfce4c3f // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.659212 0xbfd4610f // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.708922 0xbfdabdf3 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.761004 0xbfe16891 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.815648 0xbfe8672a // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.873068 0xbfefc0ad // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.933497 0xbff77cd2 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -1.997199 0xbfffa435 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.064467 0xc004203c // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.135633 0xc008ae38 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.211069 0xc00d8226 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.291194 0xc012a2ec // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.376487 0xc018185f // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.467494 0xc01deb6c // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.564838 0xc024264f // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.669238 0xc02ad4cd // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.781525 0xc0320482 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -2.902666 0xc039c547 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -3.033791 0xc04229a3 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -3.176234 0xc04b476c // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -3.331574 0xc0553884 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -3.501700 0xc0601bdc // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -3.688888 0xc06c16bd // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -3.895905 0xc0795680 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -4.126151 0xc084096e // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -4.383851 0xc08c4882 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -4.674320 0xc0959408 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -5.004339 0xc0a0238b // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -5.382697 0xc0ac3f0d // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -5.820996 0xc0ba4599 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -6.334875 0xc0cab74c // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -6.945929 0xc0de450d // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -7.684846 0xc0f5ea42 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -8.596754 0xc1098c4e // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -9.750852 0xc11c037e // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -11.258921 0xc134248a // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -13.314036 0xc155064a // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -16.280896 0xc1823f46 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -20.940998 0xc1a7872a // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -29.326235 0xc1ea9c21 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -48.886876 0xc2438c29 // 0.000000 0x0 // 0.000000 0x0 // -0.900000 0xbf666666 // -146.675355 0xc312ace4

{ "language": "Assembly" }

/* Copyright (c) 2011 Red Hat Incorporated. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of Red Hat Incorporated may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "rl78-sys.h" .global _isatty .weak _isatty _isatty: RET(_isatty,1)

{ "language": "Assembly" }

%include print_eax.vm start: mov eax, 42 call print_eax mov eax, 23 call print_eax

{ "language": "Assembly" }

// Copyright 2009 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // +build !gccgo #include "textflag.h" // // System calls for AMD64, Linux // // Just jump to package syscall's implementation for all these functions. // The runtime may know about them. TEXT ·Syscall(SB),NOSPLIT,$0-56 JMP syscall·Syscall(SB) TEXT ·Syscall6(SB),NOSPLIT,$0-80 JMP syscall·Syscall6(SB) TEXT ·SyscallNoError(SB),NOSPLIT,$0-48 CALL runtime·entersyscall(SB) MOVQ a1+8(FP), DI MOVQ a2+16(FP), SI MOVQ a3+24(FP), DX MOVQ $0, R10 MOVQ $0, R8 MOVQ $0, R9 MOVQ trap+0(FP), AX // syscall entry SYSCALL MOVQ AX, r1+32(FP) MOVQ DX, r2+40(FP) CALL runtime·exitsyscall(SB) RET TEXT ·RawSyscall(SB),NOSPLIT,$0-56 JMP syscall·RawSyscall(SB) TEXT ·RawSyscall6(SB),NOSPLIT,$0-80 JMP syscall·RawSyscall6(SB) TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-48 MOVQ a1+8(FP), DI MOVQ a2+16(FP), SI MOVQ a3+24(FP), DX MOVQ $0, R10 MOVQ $0, R8 MOVQ $0, R9 MOVQ trap+0(FP), AX // syscall entry SYSCALL MOVQ AX, r1+32(FP) MOVQ DX, r2+40(FP) RET TEXT ·gettimeofday(SB),NOSPLIT,$0-16 JMP syscall·gettimeofday(SB)

{ "language": "Assembly" }

; RUN: opt < %s -argpromotion -S | FileCheck %s ; RUN: opt < %s -passes=argpromotion -S | FileCheck %s ; CHECK: load i32, i32* %A target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" define internal i32 @callee(i1 %C, i32* %P) { br i1 %C, label %T, label %F T: ; preds = %0 ret i32 17 F: ; preds = %0 %X = load i32, i32* %P ; <i32> [#uses=1] ret i32 %X } define i32 @foo() { %A = alloca i32 ; <i32*> [#uses=2] store i32 17, i32* %A %X = call i32 @callee( i1 false, i32* %A ) ; <i32> [#uses=1] ret i32 %X }

{ "language": "Assembly" }

# CS_ARCH_ARM, CS_MODE_ARM, None 0xd2,0x10,0xb0,0xe0 = ldrsbt r1, [r0], r2 0xd4,0x10,0xf0,0xe0 = ldrsbt r1, [r0], #4 0xf2,0x10,0xb0,0xe0 = ldrsht r1, [r0], r2 0xf4,0x10,0xf0,0xe0 = ldrsht r1, [r0], #4 0xb2,0x10,0xb0,0xe0 = ldrht r1, [r0], r2 0xb4,0x10,0xf0,0xe0 = ldrht r1, [r0], #4 0xb2,0x10,0xa0,0xe0 = strht r1, [r0], r2 0xb4,0x10,0xe0,0xe0 = strht r1, [r0], #4

{ "language": "Assembly" }

; RUN: %lli %s > /dev/null define i32 @main() { entry: br label %endif then: ; No predecessors! br label %endif endif: ; preds = %then, %entry %x = phi i32 [ 4, %entry ], [ 27, %then ] ; <i32> [#uses=0] %result = phi i32 [ 32, %then ], [ 0, %entry ] ; <i32> [#uses=0] ret i32 0 }

{ "language": "Assembly" }

// go run mkasm_darwin.go arm64 // Code generated by the command above; DO NOT EDIT. // +build go1.12 #include "textflag.h" TEXT ·libc_getgroups_trampoline(SB),NOSPLIT,$0-0 JMP libc_getgroups(SB) TEXT ·libc_setgroups_trampoline(SB),NOSPLIT,$0-0 JMP libc_setgroups(SB) TEXT ·libc_wait4_trampoline(SB),NOSPLIT,$0-0 JMP libc_wait4(SB) TEXT ·libc_accept_trampoline(SB),NOSPLIT,$0-0 JMP libc_accept(SB) TEXT ·libc_bind_trampoline(SB),NOSPLIT,$0-0 JMP libc_bind(SB) TEXT ·libc_connect_trampoline(SB),NOSPLIT,$0-0 JMP libc_connect(SB) TEXT ·libc_socket_trampoline(SB),NOSPLIT,$0-0 JMP libc_socket(SB) TEXT ·libc_getsockopt_trampoline(SB),NOSPLIT,$0-0 JMP libc_getsockopt(SB) TEXT ·libc_setsockopt_trampoline(SB),NOSPLIT,$0-0 JMP libc_setsockopt(SB) TEXT ·libc_getpeername_trampoline(SB),NOSPLIT,$0-0 JMP libc_getpeername(SB) TEXT ·libc_getsockname_trampoline(SB),NOSPLIT,$0-0 JMP libc_getsockname(SB) TEXT ·libc_shutdown_trampoline(SB),NOSPLIT,$0-0 JMP libc_shutdown(SB) TEXT ·libc_socketpair_trampoline(SB),NOSPLIT,$0-0 JMP libc_socketpair(SB) TEXT ·libc_recvfrom_trampoline(SB),NOSPLIT,$0-0 JMP libc_recvfrom(SB) TEXT ·libc_sendto_trampoline(SB),NOSPLIT,$0-0 JMP libc_sendto(SB) TEXT ·libc_recvmsg_trampoline(SB),NOSPLIT,$0-0 JMP libc_recvmsg(SB) TEXT ·libc_sendmsg_trampoline(SB),NOSPLIT,$0-0 JMP libc_sendmsg(SB) TEXT ·libc_kevent_trampoline(SB),NOSPLIT,$0-0 JMP libc_kevent(SB) TEXT ·libc_utimes_trampoline(SB),NOSPLIT,$0-0 JMP libc_utimes(SB) TEXT ·libc_futimes_trampoline(SB),NOSPLIT,$0-0 JMP libc_futimes(SB) TEXT ·libc_poll_trampoline(SB),NOSPLIT,$0-0 JMP libc_poll(SB) TEXT ·libc_madvise_trampoline(SB),NOSPLIT,$0-0 JMP libc_madvise(SB) TEXT ·libc_mlock_trampoline(SB),NOSPLIT,$0-0 JMP libc_mlock(SB) TEXT ·libc_mlockall_trampoline(SB),NOSPLIT,$0-0 JMP libc_mlockall(SB) TEXT ·libc_mprotect_trampoline(SB),NOSPLIT,$0-0 JMP libc_mprotect(SB) TEXT ·libc_msync_trampoline(SB),NOSPLIT,$0-0 JMP libc_msync(SB) TEXT ·libc_munlock_trampoline(SB),NOSPLIT,$0-0 JMP libc_munlock(SB) TEXT ·libc_munlockall_trampoline(SB),NOSPLIT,$0-0 JMP libc_munlockall(SB) TEXT ·libc_getattrlist_trampoline(SB),NOSPLIT,$0-0 JMP libc_getattrlist(SB) TEXT ·libc_pipe_trampoline(SB),NOSPLIT,$0-0 JMP libc_pipe(SB) TEXT ·libc_getxattr_trampoline(SB),NOSPLIT,$0-0 JMP libc_getxattr(SB) TEXT ·libc_fgetxattr_trampoline(SB),NOSPLIT,$0-0 JMP libc_fgetxattr(SB) TEXT ·libc_setxattr_trampoline(SB),NOSPLIT,$0-0 JMP libc_setxattr(SB) TEXT ·libc_fsetxattr_trampoline(SB),NOSPLIT,$0-0 JMP libc_fsetxattr(SB) TEXT ·libc_removexattr_trampoline(SB),NOSPLIT,$0-0 JMP libc_removexattr(SB) TEXT ·libc_fremovexattr_trampoline(SB),NOSPLIT,$0-0 JMP libc_fremovexattr(SB) TEXT ·libc_listxattr_trampoline(SB),NOSPLIT,$0-0 JMP libc_listxattr(SB) TEXT ·libc_flistxattr_trampoline(SB),NOSPLIT,$0-0 JMP libc_flistxattr(SB) TEXT ·libc_setattrlist_trampoline(SB),NOSPLIT,$0-0 JMP libc_setattrlist(SB) TEXT ·libc_fcntl_trampoline(SB),NOSPLIT,$0-0 JMP libc_fcntl(SB) TEXT ·libc_kill_trampoline(SB),NOSPLIT,$0-0 JMP libc_kill(SB) TEXT ·libc_ioctl_trampoline(SB),NOSPLIT,$0-0 JMP libc_ioctl(SB) TEXT ·libc_sysctl_trampoline(SB),NOSPLIT,$0-0 JMP libc_sysctl(SB) TEXT ·libc_sendfile_trampoline(SB),NOSPLIT,$0-0 JMP libc_sendfile(SB) TEXT ·libc_access_trampoline(SB),NOSPLIT,$0-0 JMP libc_access(SB) TEXT ·libc_adjtime_trampoline(SB),NOSPLIT,$0-0 JMP libc_adjtime(SB) TEXT ·libc_chdir_trampoline(SB),NOSPLIT,$0-0 JMP libc_chdir(SB) TEXT ·libc_chflags_trampoline(SB),NOSPLIT,$0-0 JMP libc_chflags(SB) TEXT ·libc_chmod_trampoline(SB),NOSPLIT,$0-0 JMP libc_chmod(SB) TEXT ·libc_chown_trampoline(SB),NOSPLIT,$0-0 JMP libc_chown(SB) TEXT ·libc_chroot_trampoline(SB),NOSPLIT,$0-0 JMP libc_chroot(SB) TEXT ·libc_clock_gettime_trampoline(SB),NOSPLIT,$0-0 JMP libc_clock_gettime(SB) TEXT ·libc_close_trampoline(SB),NOSPLIT,$0-0 JMP libc_close(SB) TEXT ·libc_dup_trampoline(SB),NOSPLIT,$0-0 JMP libc_dup(SB) TEXT ·libc_dup2_trampoline(SB),NOSPLIT,$0-0 JMP libc_dup2(SB) TEXT ·libc_exchangedata_trampoline(SB),NOSPLIT,$0-0 JMP libc_exchangedata(SB) TEXT ·libc_exit_trampoline(SB),NOSPLIT,$0-0 JMP libc_exit(SB) TEXT ·libc_faccessat_trampoline(SB),NOSPLIT,$0-0 JMP libc_faccessat(SB) TEXT ·libc_fchdir_trampoline(SB),NOSPLIT,$0-0 JMP libc_fchdir(SB) TEXT ·libc_fchflags_trampoline(SB),NOSPLIT,$0-0 JMP libc_fchflags(SB) TEXT ·libc_fchmod_trampoline(SB),NOSPLIT,$0-0 JMP libc_fchmod(SB) TEXT ·libc_fchmodat_trampoline(SB),NOSPLIT,$0-0 JMP libc_fchmodat(SB) TEXT ·libc_fchown_trampoline(SB),NOSPLIT,$0-0 JMP libc_fchown(SB) TEXT ·libc_fchownat_trampoline(SB),NOSPLIT,$0-0 JMP libc_fchownat(SB) TEXT ·libc_flock_trampoline(SB),NOSPLIT,$0-0 JMP libc_flock(SB) TEXT ·libc_fpathconf_trampoline(SB),NOSPLIT,$0-0 JMP libc_fpathconf(SB) TEXT ·libc_fsync_trampoline(SB),NOSPLIT,$0-0 JMP libc_fsync(SB) TEXT ·libc_ftruncate_trampoline(SB),NOSPLIT,$0-0 JMP libc_ftruncate(SB) TEXT ·libc_getdtablesize_trampoline(SB),NOSPLIT,$0-0 JMP libc_getdtablesize(SB) TEXT ·libc_getegid_trampoline(SB),NOSPLIT,$0-0 JMP libc_getegid(SB) TEXT ·libc_geteuid_trampoline(SB),NOSPLIT,$0-0 JMP libc_geteuid(SB) TEXT ·libc_getgid_trampoline(SB),NOSPLIT,$0-0 JMP libc_getgid(SB) TEXT ·libc_getpgid_trampoline(SB),NOSPLIT,$0-0 JMP libc_getpgid(SB) TEXT ·libc_getpgrp_trampoline(SB),NOSPLIT,$0-0 JMP libc_getpgrp(SB) TEXT ·libc_getpid_trampoline(SB),NOSPLIT,$0-0 JMP libc_getpid(SB) TEXT ·libc_getppid_trampoline(SB),NOSPLIT,$0-0 JMP libc_getppid(SB) TEXT ·libc_getpriority_trampoline(SB),NOSPLIT,$0-0 JMP libc_getpriority(SB) TEXT ·libc_getrlimit_trampoline(SB),NOSPLIT,$0-0 JMP libc_getrlimit(SB) TEXT ·libc_getrusage_trampoline(SB),NOSPLIT,$0-0 JMP libc_getrusage(SB) TEXT ·libc_getsid_trampoline(SB),NOSPLIT,$0-0 JMP libc_getsid(SB) TEXT ·libc_getuid_trampoline(SB),NOSPLIT,$0-0 JMP libc_getuid(SB) TEXT ·libc_issetugid_trampoline(SB),NOSPLIT,$0-0 JMP libc_issetugid(SB) TEXT ·libc_kqueue_trampoline(SB),NOSPLIT,$0-0 JMP libc_kqueue(SB) TEXT ·libc_lchown_trampoline(SB),NOSPLIT,$0-0 JMP libc_lchown(SB) TEXT ·libc_link_trampoline(SB),NOSPLIT,$0-0 JMP libc_link(SB) TEXT ·libc_linkat_trampoline(SB),NOSPLIT,$0-0 JMP libc_linkat(SB) TEXT ·libc_listen_trampoline(SB),NOSPLIT,$0-0 JMP libc_listen(SB) TEXT ·libc_mkdir_trampoline(SB),NOSPLIT,$0-0 JMP libc_mkdir(SB) TEXT ·libc_mkdirat_trampoline(SB),NOSPLIT,$0-0 JMP libc_mkdirat(SB) TEXT ·libc_mkfifo_trampoline(SB),NOSPLIT,$0-0 JMP libc_mkfifo(SB) TEXT ·libc_mknod_trampoline(SB),NOSPLIT,$0-0 JMP libc_mknod(SB) TEXT ·libc_open_trampoline(SB),NOSPLIT,$0-0 JMP libc_open(SB) TEXT ·libc_openat_trampoline(SB),NOSPLIT,$0-0 JMP libc_openat(SB) TEXT ·libc_pathconf_trampoline(SB),NOSPLIT,$0-0 JMP libc_pathconf(SB) TEXT ·libc_pread_trampoline(SB),NOSPLIT,$0-0 JMP libc_pread(SB) TEXT ·libc_pwrite_trampoline(SB),NOSPLIT,$0-0 JMP libc_pwrite(SB) TEXT ·libc_read_trampoline(SB),NOSPLIT,$0-0 JMP libc_read(SB) TEXT ·libc_readlink_trampoline(SB),NOSPLIT,$0-0 JMP libc_readlink(SB) TEXT ·libc_readlinkat_trampoline(SB),NOSPLIT,$0-0 JMP libc_readlinkat(SB) TEXT ·libc_rename_trampoline(SB),NOSPLIT,$0-0 JMP libc_rename(SB) TEXT ·libc_renameat_trampoline(SB),NOSPLIT,$0-0 JMP libc_renameat(SB) TEXT ·libc_revoke_trampoline(SB),NOSPLIT,$0-0 JMP libc_revoke(SB) TEXT ·libc_rmdir_trampoline(SB),NOSPLIT,$0-0 JMP libc_rmdir(SB) TEXT ·libc_lseek_trampoline(SB),NOSPLIT,$0-0 JMP libc_lseek(SB) TEXT ·libc_select_trampoline(SB),NOSPLIT,$0-0 JMP libc_select(SB) TEXT ·libc_setegid_trampoline(SB),NOSPLIT,$0-0 JMP libc_setegid(SB) TEXT ·libc_seteuid_trampoline(SB),NOSPLIT,$0-0 JMP libc_seteuid(SB) TEXT ·libc_setgid_trampoline(SB),NOSPLIT,$0-0 JMP libc_setgid(SB) TEXT ·libc_setlogin_trampoline(SB),NOSPLIT,$0-0 JMP libc_setlogin(SB) TEXT ·libc_setpgid_trampoline(SB),NOSPLIT,$0-0 JMP libc_setpgid(SB) TEXT ·libc_setpriority_trampoline(SB),NOSPLIT,$0-0 JMP libc_setpriority(SB) TEXT ·libc_setprivexec_trampoline(SB),NOSPLIT,$0-0 JMP libc_setprivexec(SB) TEXT ·libc_setregid_trampoline(SB),NOSPLIT,$0-0 JMP libc_setregid(SB) TEXT ·libc_setreuid_trampoline(SB),NOSPLIT,$0-0 JMP libc_setreuid(SB) TEXT ·libc_setrlimit_trampoline(SB),NOSPLIT,$0-0 JMP libc_setrlimit(SB) TEXT ·libc_setsid_trampoline(SB),NOSPLIT,$0-0 JMP libc_setsid(SB) TEXT ·libc_settimeofday_trampoline(SB),NOSPLIT,$0-0 JMP libc_settimeofday(SB) TEXT ·libc_setuid_trampoline(SB),NOSPLIT,$0-0 JMP libc_setuid(SB) TEXT ·libc_symlink_trampoline(SB),NOSPLIT,$0-0 JMP libc_symlink(SB) TEXT ·libc_symlinkat_trampoline(SB),NOSPLIT,$0-0 JMP libc_symlinkat(SB) TEXT ·libc_sync_trampoline(SB),NOSPLIT,$0-0 JMP libc_sync(SB) TEXT ·libc_truncate_trampoline(SB),NOSPLIT,$0-0 JMP libc_truncate(SB) TEXT ·libc_umask_trampoline(SB),NOSPLIT,$0-0 JMP libc_umask(SB) TEXT ·libc_undelete_trampoline(SB),NOSPLIT,$0-0 JMP libc_undelete(SB) TEXT ·libc_unlink_trampoline(SB),NOSPLIT,$0-0 JMP libc_unlink(SB) TEXT ·libc_unlinkat_trampoline(SB),NOSPLIT,$0-0 JMP libc_unlinkat(SB) TEXT ·libc_unmount_trampoline(SB),NOSPLIT,$0-0 JMP libc_unmount(SB) TEXT ·libc_write_trampoline(SB),NOSPLIT,$0-0 JMP libc_write(SB) TEXT ·libc_mmap_trampoline(SB),NOSPLIT,$0-0 JMP libc_mmap(SB) TEXT ·libc_munmap_trampoline(SB),NOSPLIT,$0-0 JMP libc_munmap(SB) TEXT ·libc_gettimeofday_trampoline(SB),NOSPLIT,$0-0 JMP libc_gettimeofday(SB) TEXT ·libc_fstat_trampoline(SB),NOSPLIT,$0-0 JMP libc_fstat(SB) TEXT ·libc_fstatat_trampoline(SB),NOSPLIT,$0-0 JMP libc_fstatat(SB) TEXT ·libc_fstatfs_trampoline(SB),NOSPLIT,$0-0 JMP libc_fstatfs(SB) TEXT ·libc_getfsstat_trampoline(SB),NOSPLIT,$0-0 JMP libc_getfsstat(SB) TEXT ·libc_lstat_trampoline(SB),NOSPLIT,$0-0 JMP libc_lstat(SB) TEXT ·libc_stat_trampoline(SB),NOSPLIT,$0-0 JMP libc_stat(SB) TEXT ·libc_statfs_trampoline(SB),NOSPLIT,$0-0 JMP libc_statfs(SB)

{ "language": "Assembly" }

COMMENT @----------------------------------------------------------------------- Copyright (c) Geoworks 1991 -- All Rights Reserved PROJECT: PC GEOS MODULE: FILE: uiChooseName.asm AUTHOR: Cheng, 7/92 ROUTINES: Name Description ---- ----------- REVISION HISTORY: Name Date Description ---- ---- ----------- Cheng 7/92 Initial revision DESCRIPTION: $Id: uiChooseName.asm,v 1.1 97/04/07 11:12:40 newdeal Exp $ -------------------------------------------------------------------------------@ ;--------------------------------------------------- SpreadsheetClassStructures segment resource SSChooseNameControlClass ;declare the class record SpreadsheetClassStructures ends ;--------------------------------------------------- ChooseNameControlCode segment resource COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% SSCNGetInfo %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% SYNOPSIS: Get GenControl info for the SSChooseNameControl CALLED BY: MSG_GEN_CONTROL_GET_INFO PASS: *ds:si - instance data ds:di - *ds:si es - seg addr of SSChooseNameControlClass ax - the message cx:dx - GenControlBuildInfo structure to fill in RETURN: cx:dx - filled in DESTROYED: bx, si, di, ds, es (method handler) PSEUDO CODE/STRATEGY: KNOWN BUGS/SIDE EFFECTS/IDEAS: REVISION HISTORY: Name Date Description ---- ---- ----------- cheng 7/92 Initial version %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@ SSCNGetInfo method dynamic SSChooseNameControlClass, \ MSG_GEN_CONTROL_GET_INFO mov si, offset SSCN_dupInfo mov es, cx mov di, dx ;es:di = dest segmov ds, cs mov cx, size GenControlBuildInfo rep movsb ret SSCNGetInfo endm SSCN_dupInfo GenControlBuildInfo < mask GCBF_SUSPEND_ON_APPLY, ; GCBI_flags SSCN_IniFileKey, ; GCBI_initFileKey SSCN_gcnList, ; GCBI_gcnList length SSCN_gcnList, ; GCBI_gcnCount SSCN_notifyTypeList, ; GCBI_notificationList length SSCN_notifyTypeList, ; GCBI_notificationCount SSCNName, ; GCBI_controllerName handle SSChooseNameControlUI, ; GCBI_dupBlock SSCN_childList, ; GCBI_childList length SSCN_childList, ; GCBI_childCount SSCN_featuresList, ; GCBI_featuresList length SSCN_featuresList, ; GCBI_featuresCount SSCN_DEFAULT_FEATURES, ; GCBI_features 0, ; GCBI_toolBlock 0, ; GCBI_toolList 0, ; GCBI_toolCount 0, ; GCBI_toolFeaturesList 0, ; GCBI_toolFeaturesCount 0, ; GCBI_toolFeatures SSCN_helpContext> ; GCBI_helpContext if FULL_EXECUTE_IN_PLACE SpreadsheetControlInfoXIP segment resource endif SSCN_helpContext char "dbInsName", 0 SSCN_IniFileKey char "ssChooseName", 0 SSCN_gcnList GCNListType \ <MANUFACTURER_ID_GEOWORKS, GAGCNLT_APP_TARGET_NOTIFY_SPREADSHEET_NAME_CHANGE> SSCN_notifyTypeList NotificationType \ <MANUFACTURER_ID_GEOWORKS, GWNT_SPREADSHEET_NAME_CHANGE> ;--- SSCN_childList GenControlChildInfo \ <offset ChooseNameDB, mask SSCNF_CHOOSE_NAME, mask GCCF_IS_DIRECTLY_A_FEATURE> ; Careful, this table is in the *opposite* order as the record which ; it corresponds to. SSCN_featuresList GenControlFeaturesInfo \ <offset ChooseNameList, ChooseNameName, 0> if FULL_EXECUTE_IN_PLACE SpreadsheetControlInfoXIP ends endif COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% SSCNUpdateUI %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% SYNOPSIS: Update UI for SSChooseNameControl CALLED BY: MSG_GEN_CONTROL_UPDATE_UI PASS: *ds:si - instance data ds:di - *ds:si es - seg addr of SSChooseNameControlClass ax - the message RETURN: none DESTROYED: ax, bx, cx, dx, bp, si (method handler) PSEUDO CODE/STRATEGY: KNOWN BUGS/SIDE EFFECTS/IDEAS: REVISION HISTORY: Name Date Description ---- ---- ----------- cheng 7/92 Initial version %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@ SSCNUpdateUI method dynamic SSChooseNameControlClass, \ MSG_GEN_CONTROL_UPDATE_UI call SSCGetChildBlockAndFeatures mov ax, MSG_SPREADSHEET_INIT_CHOOSE_NAME_LIST mov cx, ds:LMBH_handle mov dx, si call SSCSendToSpreadsheet ret SSCNUpdateUI endm COMMENT @----------------------------------------------------------------------- FUNCTION: SSCNUpdateUIWithNumNames DESCRIPTION: CALLED BY: INTERNAL (MSG_CNC_UPDATE_UI_WITH_NUM_NAMES) PASS: cx - number of names RETURN: DESTROYED: REGISTER/STACK USAGE: PSEUDO CODE/STRATEGY: KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS: REVISION HISTORY: Name Date Description ---- ---- ----------- Cheng 6/92 Initial version -------------------------------------------------------------------------------@ SSCNUpdateUIWithNumNames method dynamic SSChooseNameControlClass, \ MSG_CNC_UPDATE_UI_WITH_NUM_NAMES call SSCNEnableDisableUI call SSCGetChildBlockAndFeatures mov si, offset ChooseNameList mov ax, MSG_GEN_DYNAMIC_LIST_INITIALIZE clr di call ObjMessage ret SSCNUpdateUIWithNumNames endm COMMENT @----------------------------------------------------------------------- FUNCTION: SSCNEnableDisableUI DESCRIPTION: CALLED BY: INTERNAL () PASS: cx - number of names RETURN: DESTROYED: REGISTER/STACK USAGE: PSEUDO CODE/STRATEGY: KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS: REVISION HISTORY: Name Date Description ---- ---- ----------- Cheng 6/92 Initial version -------------------------------------------------------------------------------@ SSCNEnableDisableUI proc near uses ax,bx,cx,dx,di,si,bp .enter call SSCGetChildBlockAndFeatures ; bx <- child block ; ; We want to enable/disable the Paste trigger ; depending on whether or not there are any items ; mov ax, MSG_GEN_SET_ENABLED tst cx ; Check for items jnz enableDisable ; Branch if has items mov ax, MSG_GEN_SET_NOT_ENABLED enableDisable: ; ; If there are no entries in the list we disable the Paste triggers ; push bx mov si, offset ChooseNameTrigger mov di, mask MF_CALL mov dl, VUM_NOW call ObjMessage pop bx .leave ret SSCNEnableDisableUI endp COMMENT @----------------------------------------------------------------------- FUNCTION: SSCNRequestMoniker DESCRIPTION: CALLED BY: INTERNAL () PASS: cx:dx GenDynamicList OD bp - entry # RETURN: DESTROYED: REGISTER/STACK USAGE: PSEUDO CODE/STRATEGY: KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS: REVISION HISTORY: Name Date Description ---- ---- ----------- Cheng 6/92 Initial version -------------------------------------------------------------------------------@ SSCNRequestMoniker method dynamic SSChooseNameControlClass, MSG_CHOOSE_NAME_REQUEST_MONIKER .enter call SSCGetChildBlockAndFeatures mov ax, MSG_SPREADSHEET_NAME_REQUEST_ENTRY_MONIKER mov cx, bx mov dx, offset ChooseNameList ;^lcx:dx <- OD of list call SSCSendToSpreadsheet .leave ret SSCNRequestMoniker endm COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% SSCNChooseName %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% SYNOPSIS: Change the function that is selected CALLED BY: MSG_SS_CHOOSE_NAME PASS: *ds:si - instance data ds:di - *ds:si es - seg addr of SSChooseNameControlClass ax - the message cx - index of the function in the list RETURN: none DESTROYED: bx, si, di, ds, es (method handler) PSEUDO CODE/STRATEGY: KNOWN BUGS/SIDE EFFECTS/IDEAS: REVISION HISTORY: Name Date Description ---- ---- ----------- gene 9/27/92 Initial version %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@ SSCNChooseName method dynamic SSChooseNameControlClass, MSG_SS_CHOOSE_NAME if not KEYBOARD_ONLY_UI mov ax, MSG_META_RELEASE_FOCUS_EXCL call ObjCallInstanceNoLock mov ax, MSG_META_ENSURE_ACTIVE_FT call GenCallApplication endif push si call SSCGetChildBlockAndFeatures mov si, offset ChooseNameList ;^lbx:si <- OD of list mov ax, MSG_GEN_ITEM_GROUP_GET_SELECTION call SSCNObjMessageCall ; ax <- cur selection, carry if none jc donePop ;branch if none selected mov cx, ax ; cx <- item to get mov ax, MSG_GEN_ITEM_GROUP_GET_ITEM_OPTR call SSCNObjMessageCall ; ^lcx:dx <- selected item jnc donePop ;branch if none selected movdw bxsi, cxdx mov ax, MSG_GEN_GET_VIS_MONIKER call SSCNObjMessageCall ; ^lax <- VisMoniker chunk ; ; allocate a block of memory for the string and copy the string over ; push bx, ds mov si, ax call ObjLockObjBlock mov ds, ax mov si, ds:[si] ChunkSizePtr ds, si, cx add si, (offset VM_data + offset VMT_text) ; ds:si <- text string sub cx, (offset VM_data + offset VMT_text) ; cx <- text size push cx mov ax, cx ;ax <- # bytes to allocate mov cx, (mask HAF_LOCK shl 8) call MemAlloc ;ax <- seg; bx <- handle mov es, ax clr di ;es:di <- dest pop cx ;cx <- # of bytes to copy rep movsb call MemUnlock mov dx, bx ;dx <- handle of string pop bx, ds call MemUnlock pop si ;*ds:si <- controller ; ; dx = mem handle ; ; clr cx ; string is null-terminated clr bp ;bp.low <- offset; bp.high <- md mov ax, MSG_SPREADSHEET_REPLACE_TEXT_SELECTION clr bx, di call GenControlOutputActionRegs ret donePop: add sp, 2 ;clear si from stack ret SSCNChooseName endm SSCNObjMessageCall proc near uses di .enter mov di, mask MF_FIXUP_DS or mask MF_CALL call ObjMessage .leave ret SSCNObjMessageCall endp ChooseNameControlCode ends

{ "language": "Assembly" }

/*++ Copyright (c) 2013 Minoca Corp. This file is licensed under the terms of the GNU General Public License version 3. Alternative licensing terms are available. Contact [email protected] for details. See the LICENSE file at the root of this project for complete licensing information. Module Name: entry.S Abstract: This module implements the entry point for the loader. Author: Evan Green 18-Aug-2013 Environment: Kernel mode --*/ // // ------------------------------------------------------------------ Includes // #include <minoca/kernel/x86.inc> // // ---------------------------------------------------------------------- Code // // // .text specifies that this code belongs in the executable section. // // .code32 specifies that this is 32-bit protected mode code. // .text .code32 // // Stick this in the .init section so it ends up at the front of the binary. // .section .init // // .globl allows this label to be visible to the linker. // .globl _start // // void // start ( // ) // /*++ Routine Description: This routine implements the entry point for the firmware. It jumps to the main C routine. It is called by the file system specific boot code. Arguments: None. Return Value: TRUE if interrupts are enabled in the processor. FALSE if interrupts are globally disabled. --*/ _start: jmp EfiBiosMain # Just do it. // // --------------------------------------------------------- Internal Functions //

{ "language": "Assembly" }

#RUN: llvm-xray graph %s -o - -m %S/Inputs/simple-instrmap.yaml -d \ #RUN: | FileCheck %s -check-prefix=EMPTY #RUN: llvm-xray graph %s -o - -m %S/Inputs/simple-instrmap.yaml -d -e count \ #RUN: | FileCheck %s -check-prefix=COUNT # #RUN: llvm-xray graph %s -o - -m %S/Inputs/simple-instrmap.yaml -d -e min \ #RUN: | FileCheck %s -check-prefix=TIME #RUN: llvm-xray graph %s -o - -m %S/Inputs/simple-instrmap.yaml -d -e med \ #RUN: | FileCheck %s -check-prefix=TIME #RUN: llvm-xray graph %s -o - -m %S/Inputs/simple-instrmap.yaml -d -e 90p \ #RUN: | FileCheck %s -check-prefix=TIME #RUN: llvm-xray graph %s -o - -m %S/Inputs/simple-instrmap.yaml -d -e 99p \ #RUN: | FileCheck %s -check-prefix=TIME #RUN: llvm-xray graph %s -o - -m %S/Inputs/simple-instrmap.yaml -d -e max \ #RUN: | FileCheck %s -check-prefix=TIME #RUN: llvm-xray graph %s -o - -m %S/Inputs/simple-instrmap.yaml -d -e sum \ #RUN: | FileCheck %s -check-prefix=TIME # --- header: version: 1 type: 0 constant-tsc: true nonstop-tsc: true cycle-frequency: 0 records: # Here we reconstruct the following call trace: # # f1() # f2() # f3() # # But we find that we're missing an exit record for f2() because it's # tail-called f3(). We make sure that if we see a trace like this that we can # deduce tail calls, and account the time (potentially wrongly) to f2() when # f1() exits. That is because we don't go back to f3()'s entry record to # properly do the math on the timing of f2(). # # Note that by default, tail/sibling call deduction is disabled, and is enabled # with a flag "-d" or "-deduce-sibling-calls". # - { type: 0, func-id: 1, cpu: 1, thread: 111, kind: function-enter, tsc: 10000 } - { type: 0, func-id: 2, cpu: 1, thread: 111, kind: function-enter, tsc: 10001 } - { type: 0, func-id: 3, cpu: 1, thread: 111, kind: function-enter, tsc: 10002 } - { type: 0, func-id: 3, cpu: 1, thread: 111, kind: function-exit, tsc: 10003 } - { type: 0, func-id: 1, cpu: 1, thread: 111, kind: function-exit, tsc: 10004 } ... #EMPTY: digraph xray { #EMPTY-DAG: F0 -> F1 [label=""]; #EMPTY-DAG: F1 -> F2 [label=""]; #EMPTY-DAG: F2 -> F3 [label=""]; #EMPTY-DAG: F1 [label="@(1)"]; #EMPTY-DAG: F2 [label="@(2)"]; #EMPTY-DAG: F3 [label="@(3)"]; #EMPTY-NEXT: } #COUNT: digraph xray { #COUNT-DAG: F0 -> F1 [label="1"]; #COUNT-DAG: F1 -> F2 [label="1"]; #COUNT-DAG: F2 -> F3 [label="1"]; #COUNT-DAG: F1 [label="@(1)"]; #COUNT-DAG: F2 [label="@(2)"]; #COUNT-DAG: F3 [label="@(3)"]; #COUNT-NEXT: } #TIME: digraph xray { #TIME-DAG: F0 -> F1 [label="4.{{.*}}"]; #TIME-DAG: F1 -> F2 [label="3.{{.*}}"]; #TIME-DAG: F2 -> F3 [label="1.{{.*}}"]; #TIME-DAG: F1 [label="@(1)"]; #TIME-DAG: F2 [label="@(2)"]; #TIME-DAG: F3 [label="@(3)"]; #TIME-NEXT: }

{ "language": "Assembly" }

// REQUIRES: x86 // This is a test for R_X86_64_PC8 and R_X86_64_PC16. // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t1.o // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/x86-64-pcrel.s -o %t2.o // RUN: ld.lld -o %t.exe %t1.o %t2.o // RUN: llvm-objdump -s %t.exe | FileCheck %s // CHECK: Contents of section .text: // CHECK-NEXT: 2000cccc cccccccc cccccccc cccccccc // CHECK-NEXT: 20cccccc cccccccc cccccccc cccccccc // CHECK-NEXT: e0ffcccc cccccccc cccccccc cccccccc // CHECK-NEXT: e0cccccc cccccccc cccccccc cccccccc .globl _start _start: .word foo - _start .fill 14,1,0xcc .byte foo - _start .fill 15,1,0xcc

{ "language": "Assembly" }