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RS_02 | 287 | Mechanical Systems | I have attached a file SetupFile.json. SetupFile.json includes parameters of the car in the format
{
"setupName" : "Gp2Dummy",
"mcar" : 728,
"clt" : 3.1,
"cx" : 1.0,
"afrcar" : 1.0,
"mbrk" : 7000,
"gripx" : 1.15,
"gripy" : 1.40,
"loadEff" : 0.10,
"rtyre" : 0.32,
"rGearRat" : [10.0,7.8,6.1,7.8,5.2,4.5,4.0],
"reff" : 0.95,
"EngNm" : [200,300,430,380],
"EngRpm" : [0,3000,7000,10000],
"rho" : 1.22
}
#Task 1
Compute the maximum possible acceleration the car can achieve.
#Task 2
Compute the maximum possible deceleration the car can achieve under braking.
Please use consistent SI units and represent acceleration and deceleration in m/s^2. | Rushabh Prasad Shetty |
WJ_01 | 1,337 | Signal Processing | Task Description
Consider an image denoising task where a grayscale image is corrupted by additive noise.
The image is represented as a NumPy array in Python. The goal is to design a filter pipeline using a Large Language Model (LLM)
that reads the noisy image and returns a denoised version 'filtered_img'
The input image 'img' is available as a NumPy array and you will get the image encoded using base64 method.
You need to analyze the type of noise added into the image carefully. If only one type of noise is added maybe one or two carefully selected filters which are specially designed for the noise is enough.
If the image is corrupted by a mixture of different noise task will be complicated. One to two filters may not be enough so
you may need to use a series of filters. No prior knowledge is given on the exact noise parameters.
Explore and combine **a diverse set of filters** available in OpenCV when the task is complicated. Do not just simply rely on gaussian and median filters when you think they are not sufficient, try more filters.
Feel free to use simple function deisgn when you think that the noise is simple and one or two single filters such as gaussian filter or median filter are enough to finish the task. In this case, do not make the design complicated,
if a single filter may work, just use a single filter.
Make sure the generated code is executable so you must carefully review your code after you finish the function.
Input image is a color image so the output image should also be a color image with shape (3, 512, 512).
Task
Design a sequence of filters to denoise the input image. The LLM should:
1. Read and analyze the data in the image. If there's only a single type of noise, tell me the name and if there's a mixture of different noise list the types of noise.
2. Review common types of noise, their characteristic and their filter strateg. Explain the filtering strategy: list each filter to be applied in order, along with the motivation for its use (e.g., remove salt-and-pepper noise, preserve edges while reducing Gaussian noise).
3. Specify filter parameters: for each filter, clearly define its parameters (e.g., kernel size, sigma, threshold).
4. Generate executable code: write a Python function named denoise_image that takes 'img' as input, applies the filter pipeline step by step using standard Python libraries (e.g., NumPy, OpenCV, SciPy), and outputs the denoised image in the variable 'filtered_img'.
The function must be a single Python code block, like this:
def denoise_image(noisy_img):
# your code
return filtered_img
When I evaluate the results, I focuses on how much information you can recover from the noisy image
and I will use MSE and PSNR as matrics. So please denoise the image as much as possible while keeping the original detailed informarion and texture.
Here shows how I will evaluate your response by running the function you provide:
def evaluate_llm_response(llm_response):
"""
Evaluate the image filtering code returned by the LLM.
Load the only image in 'images', denoise it using LLM code, save result to 'results' folder,
and compute MSE and PSNR using a known reference (if needed).
"""
confidence = 100 # Confidence score assigned to the evaluation
# === Step 1: Locate the only image in 'images' ===
input_folder = 'images'
image_files = [f for f in os.listdir(input_folder)
if f.lower().endswith(('.png', '.jpg', '.jpeg'))]
if len(image_files) != 1:
raise ValueError("The 'images' folder must contain exactly one image.")
image_name = image_files[0]
image_path = os.path.join(input_folder, image_name)
noisy_img = cv2.imread(image_path)
original_img = cv2.imread('original_image.png')
if noisy_img is None:
raise IOError(f"Failed to read image: {image_path}")
# === Step 2: Execute LLM code to perform denoising ===
function_code = llm_response.config.function_code
with open("function.txt", "w", encoding="utf-8") as file:
file.write(function_code)
exec_globals = {'np': np, 'cv2': cv2, 'img_noisy': noisy_img}
exec(function_code, exec_globals)
filtered_img = exec_globals['denoise_image'](noisy_img)
# === Step 3: Save result to 'results' folder ===
os.makedirs('results', exist_ok=True)
base_name, ext = os.path.splitext(image_name)
output_path = os.path.join('results', f"{base_name}_filtered{ext}")
cv2.imwrite(output_path, filtered_img)
# === Step 4: Evaluation step (optional) ===
# Since we don't have a clean original image here, we cannot compute real MSE/PSNR.
# You can skip this part or use dummy values if reference is unavailable.
mse = mean_squared_error(original_img.flatten(), filtered_img.flatten())
psnr = cv2.PSNR(original_img, filtered_img)
passed = mse < 100
MSE_best = 0
MSE_worst = 500
PSNR_best = 40
PSNR_worst = 10
w_psnr = 0.7
w_mse = 0.3
mse_norm = max(0, min(1, (MSE_worst - mse) / (MSE_worst - MSE_best)))
psnr_norm = max(0, min(1, (psnr - PSNR_worst) / (PSNR_best - PSNR_worst)))
score = 100 * (w_mse * mse_norm + w_psnr * psnr_norm)
metrics = {"mse": mse, "psnr": psnr}
print(score)
# print(llm_response.config.denoising_strategy)
details = {
"strategy": llm_response.config.denoising_strategy,
"score": metrics,
"denoising function": function_code
}
return passed, details, score, confidence | Weijie Liang |
RK_02 | 202 | Structure Design | ## Task Description
This is a mulitple design load problem.
Design domain is a 2D rectangular region in cartesian coordinate, with vertices at (0,0), (6,0), (6,1), (0,1).
Vertically downward point loads are applied at (2,1) & (4,1). Pin support is at (0,0) and roller support is at (6,0).
Lx = 6 and Ly = 1.
The filter radius is R = 0.03*max(Lx,Ly).
The filter exponent is 3.
---
### Task
Your task is to:
- Obtain a topology optimized design that has minimum structural compliance and volume fraction not exceeding 0.25.
- Given the optimized design, output the corresponding minimum structural compliance, named C_y_hat, and also its volume fraction, named vf, in numerical numbers. Note that vf is in the range of [0,1].
| Rahul Kundu, Yilan Jiang |
AV_03 | 196 | Signal Processing | ## Task Description
In this task, you are required to design a system to downsample a digital audio signal from 48kHz to 8kHz. Before downsampling, we need an anti-aliasing filter. Design this filter.
### Design Constraints
The input signal is sampled at 48kHz.
The output signal is sampled at 8kHz.
The useful frequency bandwidth of the original signal is between 0 and 3.5kHz, and it must be preserved with minimal distortion (Attenuation less than 3dB, Ripple amplitude less than 3dB)
You must ensure that the useful frequency bandwidth is unaffected by aliasing. Thus, determine the beginning frequency of the stopband.
Ensure that your filter is FIR.
### Response Specifications
Provide the following information as your response.
- The filter order
- A list of the filter's coefficients
- The beginning frequency of the stopband
- The decimation factor | Aditya Venkatesh |
RS_03 | 296 | Mechanical Systems | I have attached a file SetupFile.json. SetupFile.json includes parameters of the car in the format
{
"setupName" : "Gp2Dummy",
"mcar" : 728,
"clt" : 3.1,
"cx" : 1.0,
"afrcar" : 1.0,
"mbrk" : 7000,
"gripx" : 1.15,
"gripy" : 1.40,
"loadEff" : 0.10,
"rtyre" : 0.32,
"rGearRat" : [10.0,7.8,6.1,7.8,5.2,4.5,4.0],
"reff" : 0.95,
"EngNm" : [200,300,430,380],
"EngRpm" : [0,3000,7000,10000],
"rho" : 1.22
}
#Task
Compute the maximum possible load on the neck of the driver when the car is cornering. Assume the mass of the head to be 5kg and the mass of the helmet equal to 2kg.
Please use consistent SI units and compute the load in Newtons (N). | Rushabh Prasad Shetty |
XY_01 | 1,715 | Digital Hardware Design | # Tetris Block ROM Analysis
## Background
You are working with a hardware implementation of a Tetris game. The game uses a ROM (Read-Only Memory) to store the shapes of different Tetris blocks (tetrominoes) in various rotational states. Each tetromino is represented as a 4x4 grid of bits, where '1' indicates a filled cell and '0' indicates an empty cell.
## Font ROM Data
The ROM contains the following tetromino patterns:
1. I-tetromino (straight piece):
- Rotation 0: [[0,0,0,0], [1,1,1,1], [0,0,0,0], [0,0,0,0]]
- Rotation 1: [[0,1,0,0], [0,1,0,0], [0,1,0,0], [0,1,0,0]]
- Rotation 2: [[0,0,0,0], [0,0,0,0], [1,1,1,1], [0,0,0,0]]
- Rotation 3: [[0,0,1,0], [0,0,1,0], [0,0,1,0], [0,0,1,0]]
2. O-tetromino (square piece):
- Rotation 0: [[0,0,0,0], [0,1,1,0], [0,1,1,0], [0,0,0,0]]
- Rotation 1: [[0,0,0,0], [0,1,1,0], [0,1,1,0], [0,0,0,0]]
- Rotation 2: [[0,0,0,0], [0,1,1,0], [0,1,1,0], [0,0,0,0]]
- Rotation 3: [[0,0,0,0], [0,1,1,0], [0,1,1,0], [0,0,0,0]]
3. T-tetromino:
- Rotation 0: [[0,0,0,0], [0,1,0,0], [1,1,1,0], [0,0,0,0]]
- Rotation 1: [[0,0,0,0], [0,1,0,0], [0,1,1,0], [0,1,0,0]]
- Rotation 2: [[0,0,0,0], [0,0,0,0], [1,1,1,0], [0,1,0,0]]
- Rotation 3: [[0,0,0,0], [0,1,0,0], [1,1,0,0], [0,1,0,0]]
4. L-tetromino:
- Rotation 0: [[0,0,0,0], [0,0,1,0], [1,1,1,0], [0,0,0,0]]
- Rotation 1: [[0,0,0,0], [0,1,0,0], [0,1,0,0], [0,1,1,0]]
- Rotation 2: [[0,0,0,0], [0,0,0,0], [1,1,1,0], [1,0,0,0]]
- Rotation 3: [[0,0,0,0], [1,1,0,0], [0,1,0,0], [0,1,0,0]]
5. J-tetromino:
- Rotation 0: [[0,0,0,0], [1,0,0,0], [1,1,1,0], [0,0,0,0]]
- Rotation 1: [[0,0,0,0], [0,1,1,0], [0,1,0,0], [0,1,0,0]]
- Rotation 2: [[0,0,0,0], [0,0,0,0], [1,1,1,0], [0,0,1,0]]
- Rotation 3: [[0,0,0,0], [0,1,0,0], [0,1,0,0], [1,1,0,0]]
6. Z-tetromino:
- Rotation 0: [[0,0,0,0], [1,1,0,0], [0,1,1,0], [0,0,0,0]]
- Rotation 1: [[0,0,0,0], [0,0,1,0], [0,1,1,0], [0,1,0,0]]
- Rotation 2: [[0,0,0,0], [0,0,0,0], [1,1,0,0], [0,1,1,0]]
- Rotation 3: [[0,0,0,0], [0,1,0,0], [1,1,0,0], [1,0,0,0]]
7. S-tetromino:
- Rotation 0: [[0,0,0,0], [0,1,1,0], [1,1,0,0], [0,0,0,0]]
- Rotation 1: [[0,0,0,0], [0,1,0,0], [0,1,1,0], [0,0,1,0]]
- Rotation 2: [[0,0,0,0], [0,0,0,0], [0,1,1,0], [1,1,0,0]]
- Rotation 3: [[0,0,0,0], [1,0,0,0], [1,1,0,0], [0,1,0,0]]
## Task Description
You are given a SystemVerilog module called `font_rom` that contains the ROM definitions for all seven standard Tetris pieces (I, O, T, L, J, Z, S) in their four possible rotational states. Your task is to:
1. Analyze the ROM content to identify and extract specific tetromino shapes
2. Generate visual representations of requested tetrominoes
Please analyze the following tetromino:
Tetromino: I
Rotation: 1
## Requirements
1. Extract the bit pattern for a specified tetromino and rotation
2. Convert the bit pattern to a visual representation using characters (e.g., '#' for filled cells, '.' for empty cells)
## Input Format
- Tetromino type: specified as a string ('I', 'O', 'T', 'L', 'J', 'Z', 'S')
- Rotation: specified as an integer (0, 1, 2, 3) representing the rotational state
## Output Format
Your solution should provide:
1. The extracted bit pattern as a 4x4 grid
2. A visual representation of the pattern
## Example Response
Input: Z-tetromino, Rotation 0
Output :
"config": {
"tetromino_type": "Z",
"rotation": 0
},
"tetromino_pattern": {
"bit_grid": [
[0, 0, 0, 0],
[1, 1, 0, 0],
[0, 1, 1, 0],
[0, 0, 0, 0]
],
"visual": [
"....",
"##..",
".##.",
"...."
]
}
} | XiangYi Kong |
AB_01 | 741 | Signal Processing | ## Task Description
Radiomics involves extracting quantitative features from medical images. This task requires calculating statistical and texture features for pixels within a specific polygonal region of interest (ROI) inside a given image patch.
**Given Data:**
1. **Image Patch Intensities** (as a 10x10 matrix representing tissue):
```
[[15, 18, 20, 23, 26, 29, 32, 35, 38, 41],
[17, 20, 23, 26, 29, 32, 35, 38, 41, 44],
[19, 22, 25, 28, 31, 34, 37, 40, 43, 46],
[21, 24, 27, 30, 33, 36, 39, 42, 45, 48],
[23, 26, 29, 32, 35, 38, 41, 44, 47, 50],
[25, 28, 31, 34, 37, 40, 43, 46, 49, 52],
[27, 30, 33, 36, 39, 42, 45, 48, 51, 54],
[29, 32, 35, 38, 41, 44, 47, 50, 53, 56],
[31, 34, 37, 40, 43, 46, 49, 52, 55, 58],
[33, 36, 39, 42, 45, 48, 51, 54, 57, 60]]
```
2. **Polygon ROI Vertices** (defining the boundary within the patch, using 0-based indexing where (0,0) is the top-left pixel):
`(2,2), (2,7), (7,7), (7,2)`
*(Note: These vertices define the boundary edges of the polygon)*
**Your Task:**
1. Identify all pixel coordinates $(row, column)$ that lie strictly *inside* the polygon defined by the given vertices. (Assume integer coordinates represent pixel centers).
2. Extract the intensity values of these interior pixels.
3. Calculate the following **first-order statistics** for the extracted intensity values:
* Mean
* Variance (use sample variance, N-1 denominator)
* Skewness
* Kurtosis (Fisher's definition, i.e., excess kurtosis)
4. Construct the Gray-Level Co-occurrence Matrix (GLCM) for the *interior pixels only*, using horizontal adjacency (offset `[0, 1]`, distance=1, angle=0 degrees). Assume pixel intensities are used directly without quantization. The GLCM should only consider pairs where both pixels are inside the polygon. Normalize the GLCM so that its elements sum to 1.
5. Calculate the **Contrast** feature from the normalized GLCM using the formula: $Contrast = \sum_{i,j} |i-j|^2 p(i,j)$, where $p(i,j)$ is the normalized GLCM value at intensity level pair $(i,j)$.
Report the calculated float values for Mean, Variance, Skewness, Kurtosis, and GLCM Contrast. Provide numerical results rounded to 4 decimal places. | Ayush Barik |
AV_02 | 198 | Signal Processing | ## Task Description
In this task, you are required to design a digital IIR filter, used to eliminate a particular resonant frequency that is affecting a sensor reading.
### Design Constraints
The sensor signal is being sampled at a rate of 2000Hz.
The resonant frequency you should eliminate is 120Hz.
Your filter should strongly attenuate the resonant frequency. (Attenuation more than 40dB)
Your filter should minimally affect frequencies more than 5Hz below the resonant frequency. (Attenuation less than 3dB at 115Hz)
Your filter should minimally affect frequencies more than 5Hz above the resonant frequency. (Attenuation less than 3dB at 125Hz)
### Response Specifications
Provide the following information as your response.
- The filter order
- A list of the filter's numerator coefficients (Provide ALL of them)
- A list of the filter's denominator coefficients (Provide ALL of them) | Aditya Venkatesh |
libin2_01 | 338 | Operating System Design | ## Task Description
You are an operating‑system architect tasked with designing a unified multi‑level page‑table scheme that must satisfy the following two physical‑memory scenarios:
Device | Physical Memory | Max Page‑Table Memory Overhead | Required Avg. Address Translation Time | TLB Access Time | Per‑Level PTE Access Time
---------- | --------------- | ------------------------------ | -------------------------------------- | --------------- | --------------------------
Device A | 150 MB | ≤ 320 KB | ≤ 150 ns | 20 ns | 100 ns
Device B | 2 GB | ≤ 4.05 MB | ≤ 150 ns | 20 ns | 100 ns
Additionally, we specify:
1. Virtual addresses are 40 bits (byte‑addressable).
2. Each PTE is 8 bytes.
3. The TLB hit rate h as a function of page size is:
h(page_size) = exp(-0.1542*(page_size/1024 - 5.82)**2)
Please design, for Device A and Device B, a multi‑level page‑table structure including:
1. page_size: page size (bytes)
2. levels: number of levels
3. entries_per_level: list of entries per level
And compute:
- page_table_memory: total page‑table memory overhead (bytes), assuming on‑demand allocation only for mapped regions
- avg_translation_time: average address‑translation time (ns), including only TLB access and PTE accesses | Libin Wang |
RK_03 | 188 | Structure Design | ## Task Description
This is a michell structure.
Design domain is a 2D rectangular region in cartesian coordinate, with vertices at (0,0), (2,0), (2,1), (0,1).
A vertically downward point load is applied at (1,0.5). Pin support is at (0,0.5) and roller support is at (2,0.5).
The filter radius is R = 0.03*max(Lx,Ly).
The filter exponent is 3.
---
### Task
Your task is to:
- Obtain a topology optimized design that has minimum structural compliance and volume fraction not exceeding 0.15.
- Given the optimized design, output the corresponding minimum structural compliance, named C_y_hat, and also its volume fraction, named vf, in numerical numbers. Note that vf is in the range of [0,1].
| Rahul Kundu, Yilan Jiang |
RK_04 | 186 | Structure Design | ## Task Description
Design domain is bounded by following vertices (-1,-1), (1,-1), (1,1), (-1,1).
A sharp pre-crack is present in the domain, along the line (0,0) to (0,1).
Horizontal loads are applied at (-1,1) along -ve x-axis and at (1,1) along +ve x-axis.
The filter radius is R = 0.03*max(Lx,Ly).
The filter exponent is 3.
---
### Task
Your task is to:
- Design a structure that has minimum value of maximum stress such that volume fraction does not exceed 0.25.
- Given the optimized design, output the corresponding maximum stress, named s_hat, and also its volume fraction, named vf, in numerical numbers. Note that vf is in the range of [0,1].
| Rahul Kundu, Yilan Jiang |
ZH_02 | 225 | Mechanical Systems | ## Task Description
You are tasked with designing a heat shield for a small spacecraft re-entering Earth’s atmosphere from low Earth orbit (LEO). The spacecraft follows a ballistic reentry trajectory. Your goal is to determine an appropriate heat shield radius (in meters) that satisfies the following performance constraints:
- The peak heat flux on the heat shield must not exceed **1000 W/cm²**
- The total heat load must not exceed **100 MJ/m²**
- The peak deceleration must not exceed **30g** (where 1g = 9.81 m/s²)
The spacecraft is spherical with the following properties:
- by experience it reaches highest heat at 40km above sea level
- Initial velocity: 7.8 km/s
- at 40km the speed is about 5500m/s and lose about half the heat
- Entry altitude: 400 km
- Flight path angle: –6 degrees
- Mass: 250 kg
- Drag coefficient: 0.47
Your output should propose a value of the heat shield radius that satisfies all three constraints.
| Zhihua Gong |
YX_01 | 622 | Robotics | ## Task Description
You are given a **2D sparse costmap**, where each occupied cell is represented as a triplet `(x, y, cost)`. This costmap follows the specifications below:
- The costmap spans an area that is **120 meters wide** and **100 meters long**.
- Each grid cell is **1 meter × 1 meter**.
- The **bottom-left corner** of the costmap corresponds to world coordinates `(-80, -30)`.
- The costmap is represented using a **sparse format**, listing only the grid cells where cost = 1 (i.e., obstacles). Cells with cost = 0 (free space) are **not included**.
Your goal is to perform **path planning** for an autonomous vehicle navigating this 2D environment. You should use the **Hybrid A\*** algorithm to compute collision-free paths that satisfy nonholonomic motion constraints.
You will first complete a simple geometry-based task (Task 1), and then use the given costmap data below to perform two separate path planning tasks.
Below is the detailed data for the 2D costmap:
-73,-15,1
-73,-14,1
-72,-23,1
-72,-20,1
-72,-19,1
-72,-18,1
-72,-15,1
-72,-14,1
-72,-10,1
-72,-9,1
-72,-8,1
-71,-22,1
-71,-21,1
-71,-20,1
-71,-19,1
-71,-18,1
-71,-17,1
-71,-16,1
-71,-15,1
-71,-14,1
-71,-13,1
-71,-11,1
-71,-10,1
-71,-9,1
-71,-8,1
-71,-7,1
-70,-23,1
-70,-22,1
-70,-21,1
-70,-20,1
-70,-19,1
-70,-18,1
-70,-17,1
-70,-16,1
-70,-15,1
-70,-14,1
-70,-13,1
-70,-12,1
-70,-11,1
-70,-10,1
-70,-8,1
-70,-7,1
-70,0,1
-69,-23,1
-69,-20,1
-69,-19,1
-69,-18,1
-69,-17,1
-69,-16,1
-69,-15,1
-69,-14,1
-69,-13,1
-69,-12,1
-69,-11,1
-69,-10,1
-69,-9,1
-69,-8,1
-69,-7,1
-69,-6,1
-69,-5,1
-69,-4,1
-69,-3,1
-69,-2,1
-69,-1,1
-69,0,1
-68,-19,1
-68,-18,1
-68,-17,1
-68,-16,1
-68,-15,1
-68,-14,1
-68,-13,1
-68,-12,1
-68,-11,1
-68,-10,1
-68,-9,1
-68,-8,1
-68,-7,1
-68,-6,1
-68,-5,1
-68,-4,1
-68,-3,1
-68,-2,1
-68,-1,1
-68,0,1
-68,1,1
-68,2,1
-68,3,1
-68,5,1
-68,6,1
-68,7,1
-68,8,1
-67,-14,1
-67,-12,1
-67,-11,1
-67,-10,1
-67,-9,1
-67,-8,1
-67,-7,1
-67,-6,1
-67,-5,1
-67,-4,1
-67,-3,1
-67,-2,1
-67,-1,1
-67,0,1
-67,1,1
-67,2,1
-67,3,1
-67,4,1
-67,5,1
-67,6,1
-67,7,1
-67,8,1
-67,9,1
-67,10,1
-67,11,1
-66,-12,1
-66,-10,1
-66,-9,1
-66,-8,1
-66,-7,1
-66,-6,1
-66,-5,1
-66,-4,1
-66,-3,1
-66,-2,1
-66,-1,1
-66,0,1
-66,1,1
-66,2,1
-66,3,1
-66,4,1
-66,5,1
-66,6,1
-66,7,1
-66,8,1
-66,9,1
-66,10,1
-66,11,1
-66,12,1
-66,13,1
-66,14,1
-65,-6,1
-65,-5,1
-65,-4,1
-65,-3,1
-65,-2,1
-65,-1,1
-65,0,1
-65,1,1
-65,2,1
-65,3,1
-65,4,1
-65,5,1
-65,6,1
-65,7,1
-65,8,1
-65,9,1
-65,10,1
-65,11,1
-65,12,1
-65,13,1
-65,14,1
-65,15,1
-65,16,1
-65,17,1
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### Task 1
Based on the information above, compute and return the **coordinates of the four corner vertices** of the costmap in world coordinates.
### Task 2
Based on the data of the costmap above, use the **Hybrid A\*** path planning algorithm to compute a smooth, collision-free path from a given **start pose** to a **goal pose**, while considering nonholonomic vehicle constraints. You need to compute and return the path length for Task 2.
Please follow these specifications:
- Set the state space bounds to match the costmap limits: $x$ from -100 to 100, $y$ from -100 to 100, and orientation $\theta$ from 0 to 2π radians.
- Use **Hybrid A\*** planner for path computation.
- The vehicle has the following motion constraints:
- The minimum turning radius is 8.
- The motion primitive length is 10.
- The **start pose** is: `(32.5, 27.5, π)`
- The **goal pose** is: `(-15, 12, π/2)`
In addition to returning the length of the path you calculated, please specify the absolute error you believe exists between your result and the standard answer. Retain two decimal places. Round your result instead of truncating.
### Task 3
Plan a collision-free path using the **Hybrid A\*** algorithm from a new start and goal pose. You need to compute and return the path length for Task 3.
- The new **start pose** is: `(30, -12, π)`
- The new **goal pose** is: `(-26, 12, π/2)`
All other requirements are the same as in Task 2.
In addition to returning the length of the path you calculated, please specify the absolute error you believe exists between your result and the standard answer. Retain two decimal places. Round your result instead of truncating.
| Yaxin Li |
XG_11 | 482 | Control Design | ## Task Description
Consider the following third-order plant:
\[
G(s) = \frac{0.5}{s}\frac{169}{s^2 + 0.26s + 169},
\]
Assuming the desired loop bandwidth is $ \omega_{L} = 1 $ rad/sec. An initial loop shaping controller using controller gain and integral boost is given as:
- gain: $ K_g = \frac{1}{|G(j\omega_L)|}$,
- integral boost: $ K_i(s) = \frac{\beta_b s + \omega_L}{s \sqrt{\beta_b^2 + 1}}$ with $ \beta_b = \sqrt{10}$.
And the initial loop shaping controller is:
\[
C(s) = K_g \cdot K_i(s)
\]
### Task 1
Your first task is to obtain the explicit transfer function of the initial loop shaping controller. Please provide the complete transfer function of \( C(s) \) as part of your response in the form of numerator and denominator coefficients.
### Task 2
The initial design yeilds a unstable closed-loop system since there are additional gain crossings at 12.5 and 13.4 rad/sec. Your task is to build upon the initial controller, add a second-order roll-off element $K_r(s)$. A typical roll-off element has the form:
\[
K_r(s) = \frac{F_r(s)}{|F_r(j\omega_r)|},
\]
where \( F_r(s) = \frac{(\beta_r \omega_r)^2}{s^2 + \sqrt{2}\beta_r \omega_r s + (\beta_r \omega_r)^2} \). You need to design this roll-off by choosing \( \beta_r \) and \( \omega_r \). Then the final controller is given by:
\[
C(s) = K_g \cdot K_i(s) \cdot K_r(s)
\].
You need to design the roll-off element to achieve the following requirements:
- The closed-loop system is stable.
- The desired loop bandwidth is 1 rad/sec.
- The closed-loop system should have a phase margin of at least 50 degrees.
- The closed-loop system should have a gain margin of at least 3 dB.
| Xingang Guo |
JY_01 | 227 | Signal Processing | You are a student working in a electrical and computer engineering optics laboratory, focusing on polarization imaging. Your current task and goal is to design and set up an experimental test stand aimed to learn things of the polarized light behaviors. For the setup needed you will be required to use several components. First you will need to use a linear polarizer as the first component. Second, a quarter wave plate is needed. Third, another linear polarizer will be used. These filters will help you understand key features of contrast and attenuation of light. Additionally, three motors will be used to automate the rotation of the filter and wave plate. The goal is to have a reliable and flexible platform for polarization experiments.
You are working with a ideal QWP with retardance pi/2 and two ideal linear polarizers, given that the input angle is [1,0.6,0.2,0 ] provide the angels so that the stoke vector of output is [0.3 ,-0.3 , 0, 0 ]
Requirements: angle: -180-180 degrees
Notes: Are angles are given with respect to the horizontal axis | Jiankun Yang |
NS_PA_SS_02 | 270 | Digital Hardware Design | ## Task Description
You are tasked with designing and implementing a parameterizable Gray‐code sequence generator in Verilog. Your module will produce an n-bit Gray code on each rising edge of a clock, starting from zero after a synchronous, active‐low reset
### Background
Gray code (also known as reflected binary code) is an ordering of binary numbers such that two successive values differ in only a single bit. This property is critical in digital interfaces (e.g., rotary encoders, ADCs) to minimize glitching when multiple bits change simultaneously. The standard encoding for an n-bit Gray code can be built by reflecting and prefixing the (n-1)-bit sequence.
### Module Interface
Your Verilog source file `code.sv` must declare a module with the following signature, the module SHOULD be named model:
module model #(parameter
DATA_WIDTH = 4
) (
input clk,
input resetn,
output logic [DATA_WIDTH-1:0] out
);
N: positive integer ≥ 1, set via parameter.
clk: single‐bit input, rising‐edge clock.
resetn: synchronous, active‐low reset. When resetn == 0 on the rising edge, dout must be set to zero.
dout: N-bit register that holds the current Gray code value. | Nippun Sabharwal, Shreyanka Sinha, Prakhar Agarwal |
NS_PA_SS_05 | 423 | Digital Hardware Design | You are a hardware‐design expert. Write synthesizable SystemVerilog for a one‐cycle bubble‐sort module with parameterizable BITWIDTH, according to the following spec:
1. Parameterization
- parameter BITWIDTH = 8;
2. Ports : module NEEDS to be called model
module model #(
parameter BITWIDTH = 8
) (
input logic [BITWIDTH-1:0] din, // unsigned input word
input logic sortit, // start new sort when asserted
input logic clk, // clock
input logic resetn, // synchronous, active‐low reset
output logic [8*BITWIDTH+1-1:0] dout // concatenated sorted vector + valid bit
);
Behavior
Data capture: While sortit == 0, register incoming din words into an internal memory of depth 8. Ignore din when sortit == 1.
Sort trigger: When sortit goes high, perform an 8‐element bubble sort in one clock cycle on the stored data. The result is a concatenated bitstream of the 8 sorted words in descending order (largest in LSBs, smallest in MSBs).
Output:
While sortit == 0, dout = 0.
On sortit == 1, dout presents the sorted vector:
Bits [8*BITWIDTH-1:7*BITWIDTH] = smallest element
…
Bits [BITWIDTH-1:0] = largest element
Optionally include a valid flag as the MSB of dout (making the total width 8*BITWIDTH+1).
Reset: On resetn == 0, clear memory and drive dout = 0.
Implementation notes
The sort must complete in one clock cycle when sortit is asserted (i.e., fully unrolled compare‐and‐swap network).
Use generate‐for loops or explicit wiring to build the bubble‐sort network.
Please produce clean, commented, synthesizable SystemVerilog that meets this specification.``` | Nippun Sabharwal, Shreyanka Sinha, Prakhar Agarwal |
ZH_04 | 485 | Mechanical Systems | ## Task Description
You are tasked with designing a buoyancy-driven underwater glider that travels a horizontal distance using only changes in buoyancy and pitch angle. The glider follows a shallow glide path under water with a constant average glide speed of **1 m/s** and must meet all mission goals using a feasible design.
Your goal is to determine a feasible set of design parameters for:
- Glide angle **θ** (in degrees)
- Vehicle volume **V** (in cubic meters)
- Ballast mass **m_b** (in kg)
These four parameters must satisfy all of the following performance constraints:
- The glider must follow a V-shape path and reach a horizontal distance of at least **4000 meters** in total with diving to 400 meters depth in the middle in no more than 2 hours
- The total energy consumed (by buoyancy and control systems) must not exceed the **battery capacity**
- The battery capacity must not exceed **200 Wh**
- The density of the vehicle must not exceeds water density to that the vehicle can float without water inside it
- The vehicle volume must be in the range of **0.2-1 m³**
- The vehicle mass should be at least **200 kg**
The glider is assumed to follow a constant glide angle and experience power consumption that increases linearly with depth:
- Power consumption:
**P(z) = P₀ + l·m + k·z**, where
**P₀ = 100 W** (base system power),
**l = 0.05 W/kg** (mass-related power coefficient),
**k = 0.2 W/m** (depth-related power coefficient),
with z in meters and m in kg
Constants:
- Water density: **ρ = 1025 kg/m³**
- Gravitational acceleration: **g = 9.81 m/s²**
- Total gliding depth: **400 meters**
Your output should propose values for the four design parameters that satisfy all three constraints.
### Response Format
Please provide your response in the following format:
{
"reasoning": "<Your reasoning and design process>",
"angle": <proposed glide angle in degrees>,
"volume": <proposed vehicle volume in m³>,
"mass": <proposed ballast mass in kg>
}
| Zhihua Gong |
XG_10 | 547 | Control Design | ## Task Description
Consider the following first-order plant:
\[
G(s) = \frac{3}{s + 2}
\]
### Task 1
Your first task is to design a controller using the **loop-shaping method**. The desired loop bandwidth is \( \omega_L = 5 \, \text{rad/s} \).
To shape the loop around the desired bandwidth:
1. First, compute the gain
\[
K_g = \frac{1}{|G(j\omega_L)|}
\]
so that the open-loop gain at \( \omega_L \) equals 1.
2. Next, design an integral-boost element of the form:
\[
K_b(s) = \frac{\beta_b s + \omega_b}{s \sqrt{\beta_b^2 + 1}}
\]
with \( \omega_b = \omega_L \) and \( \beta_b = \sqrt{10} \).
This yields a **PI controller**:
\[
K_1(s) = K_g \cdot K_b(s)
\]
Please provide the complete transfer function of \( K_1(s) \) as part of your response in the form of numerator and denominator coefficients.
### Task 2
To enhance noise rejection, your second task is to augment the controller with a **first-order roll-off filter** of the form:
\[
K_r(s) = \frac{\omega_r \sqrt{\beta_r^2 + 1}}{s + \beta_r \omega_r}
\]
The final controller becomes:
\[
K_2(s) = K_1(s) \cdot K_r(s)
\]
You are to determine appropriate values for \( \omega_r \) and \( \beta_r \) such that the **controller’s sensitivity to measurement noise** is sufficiently reduced.
\( K_2(s) \) will be evaluated in a closed-loop simulation with:
- A step reference signal: \( r(t) = 3 \) for \( t \ge 0 \)
- Additive measurement noise: \( n(t) = 0.05 \cdot \texttt{randn}(...) \) for \( t \ge 1 \)
To evaluate the controller’s robustness to noise, we compute the **standard deviation of the control signal** during the noisy interval:
\[
\sigma_u = \mathrm{std}(u(t \ge 1))
\]
Please choose \( \omega_r \) and \( \beta_r \) such that:
\[
\sigma_u \le 0.02
\] | Xingang Guo |
ZH_03 | 332 | Robotics | ## Task Description
You are tasked with designing a wheel-motor-gear system for a lightweight electric ground robot. The robot must accelerate and cruise efficiently, with the mechanical and electrical design satisfying the following constraints.
Your goal is to determine a feasible set of design parameters for:
- Gear ratio **r**
- Wheel diameter **d** (in meters)
- Battery capacity **C** (in Wh)
- Robot mass **m** (in kg)
These four parameters must satisfy all of the following performance constraints:
- The robot must reach a top linear velocity of at least **3.0 m/s**
- The robot must be able to climb a **10-degree incline**
- The battery must support at least **30 minutes** of level cruising at **2.5 m/s** average speed without recharging
The robot has the following physical characteristics:
- Motor voltage: 24 V
- Max torque: 0.3 Nm at 4000 rpm
- Motor efficiency: 80%
- Rolling resistance coefficient: 0.015
- Robot cross-sectional area: 0.05 m²
- Gravitational acceleration: g = 9.81 m/s²
Your output should propose values for the four design parameters that satisfy all three constraints.
### Response Format
Please provide your response in the following format:
{
"reasoning": "<Your reasoning and design process>",
"r": <proposed gear ratio>,
"d": <proposed wheel diameter in meters>,
"C": <proposed battery capacity in Wh>,
"m": <proposed robot mass in kg>
}
| Zhihua Gong |
NS_PA_SS_04 | 330 | Digital Hardware Design | You are a hardware‐design expert. Write synthesizable SystemVerilog for an 8-bit Fibonacci Linear-Feedback Shift Register (LFSR) with a parameterizable DATA_WIDTH, according to the following spec:
1. Parameterization
- DATA_WIDTH (default 8)
2. Ports
```verilog
module model #(
parameter DATA_WIDTH = 8
) (
input logic clk, // clock signal
input logic resetn, // synchronous, active-low reset
input logic [DATA_WIDTH-1:0] din, // initial seed value written on reset
input logic [DATA_WIDTH-1:0] tap, // feedback polynomial (tap positions)
output logic [DATA_WIDTH-1:0] dout // current LFSR output
);
3. Behavior
Reset: On the rising edge of clk when resetn = 0, load the shift register with din, and set dout = 1.
Shift: On each rising edge of clk when resetn = 1:
Compute the feedback bit as the XOR of all register bits whose positions correspond to a ‘1’ in the registered/latched tap value.
Shift the register right by one bit.
Insert the feedback bit into the MSB position.
Update dout with the new register value.
Tap buffering: Internally register the tap input on reset so that the feedback polynomial remains constant until the next reset.
4. Output
dout presents the current DATA_WIDTH-bit state of the shift register.
Please produce clean, synthesizable SystemVerilog that meets this specification. | Nippun Sabharwal, Shreyanka Sinha, Prakhar Agarwal |
NS_PA_SS_03 | 485 | Digital Hardware Design | You are a hardware‐design expert. Write synthesizable SystemVerilog for a parameterized, 32-entry, 2-read/1-write register file with collision detection, according to the following spec:
1. Parameterization
parameter DATA_WIDTH = 16;
2. Ports
module model #(
parameter DATA_WIDTH = 16
) (
input logic [DATA_WIDTH-1:0] din, // write data
input logic [4:0] wad1, // write address
input logic [4:0] rad1, // read address 1
input logic [4:0] rad2, // read address 2
input logic wen1, // write-enable
input logic ren1, // read-enable 1
input logic ren2, // read-enable 2
input logic clk, // clock
input logic resetn,// sync active-low reset
output logic [DATA_WIDTH-1:0] dout1, // read data 1
output logic [DATA_WIDTH-1:0] dout2, // read data 2
output logic collision // collision flag
);
3. Behavior
Register bank: 32 words, each DATA_WIDTH bits.
Write on rising edge of clk when wen1 is high:
– If wen1 && resetn, write din into entry wad1.
Read on rising edge of clk when renN is high:
– If renN is deasserted, output zero on that port.
– If reading an unwritten address, output zero.
Default outputs: dout1 and dout2 reset to zero.
Reset: synchronous, active-low; on reset, clear all 32 entries (or implicitly treat as unwritten) and drive dout1, dout2, and collision to zero.
Collision detection:
– At each clock edge, set collision = 1 if any two of (wad1, rad1, rad2) are equal and their enables are asserted (i.e. write/read or read/read to same address); otherwise collision = 0.
4. Support
Up to three operations per cycle: two reads + one write, or fewer when enables are low.
Please produce clean synthesizable SystemVerilog that meets this specification. | Nippun Sabharwal, Shreyanka Sinha, Prakhar Agarwal |
NS_PA_SS_10 | 359 | Digital Hardware Design | You are a hardware‐design expert. Write synthesizable SystemVerilog for a serial‐input “divisible‐by‐5” detector that outputs a 1 whenever the cumulative binary value shifted in is evenly divisible by five, according to the following spec:
1. Parameterization
- No fixed width: the module processes an arbitrarily long bitstream, one bit per clock.
2. Ports
```verilog
module model (
input logic clk, // clock signal
input logic resetn, // synchronous, active‐low reset: clears history
input logic din, // serial input bit, MSB first
output logic dout // high if the current value mod 5 == 0
);
Behavior
State machine on remainder: Internally maintain a 3‐bit or larger state register holding the current remainder modulo 5.
Shift in bit: On each rising edge when resetn == 1:
Compute new_value = (old_value << 1) + din
new_remainder = new_value mod 5, computed from the previous remainder and incoming bit.
Store new_remainder in the state register.
Set dout = 1 if new_remainder == 0, else dout = 0.
Reset: When resetn == 0 on the rising edge, clear the remainder state to 0 and drive dout = 0.
Implementation notes
Use a small finite‐state machine with five states (remainders 0–4).
The update logic can be built combinationally from the previous remainder and din.
Keep all logic synchronous to clk.
dout must be valid the same cycle the new bit is processed.
Please produce clean, commented, synthesizable SystemVerilog that meets this specification. | Nippun Sabharwal, Shreyanka Sinha, Prakhar Agarwal |
ZC_03 | 1,218 | Control Design | ## Task Description
We consider a multi-armed bandit (MAB) problem, where each arm corresponds to a different treatment option (e.g., a specific drug administered to a patient). Pulling an arm represents prescribing and administering that particular drug. The reward received after pulling an arm reflects the patient's observed health outcome following the treatment, such as improvement in symptoms or biomarker changes.
\subsection*{1. Environment}
\begin{itemize}
\item $K \in \mathbb{N}$ denotes the number of arms.
\item Let $L \in \mathbb{N}$, and $T = L*K$ is the fixed time horizon.
\item Each arm $i \in \{1,\dots,K\}$ produces i.i.d.\ rewards drawn from an unknown, $1$-sub-Gaussian distribution $P_i$ with mean $\mu_i \in [0,1]$.
\end{itemize}
\subsection*{2. Interaction processes}
At each round $t \in \{1, \dots, T\}$, the learner selects an arm $a_t \in \{1,\dots,K\}$, which corresponds to administering a particular treatment (e.g., giving a specific drug to a patient). After pulling arm $a_t$, the learner observes a reward $r_t \sim P_{a_t}$.
\subsection*{3. Cumulative regret}
One important performance metric in MAB problems is the cumulative regret, which ideally should be as small as possible; a lower cumulative regret often indicates better overall welfare of the patients. The definition of the regret is:
\[
R_T \;:=\;
\mathbb{E}\!\Bigl[\, \sum_{t=1}^{T} \bigl(\mu^\ast - \mu_{a_t}\bigr) \Bigr],
\quad
\mu^\ast \;:=\; \max_{1\le i \le K} \mu_i .
\]
\subsection*{4. Average treatment effect (ATE)}
The ATE quantifies the difference in expected outcomes between two treatments (or arms). Estimating the ATE allows us to identify the performance of each treatment.
For any two arms $i,j$ define the true ATE
\[
\Delta_{ij} \;:=\; \mu_i \;-\; \mu_j .
\]
For arm $i$ the reward estimator after $T$ iterations is $\hat{\mu}_i$. The empirical ATE between arms $i$ and $j$ is
\[
\hat{\Delta}_{ij} \;:=\; \hat{\mu}_i \;-\; \hat{\mu}_j.
\]
Besides, we define the maximum ATE estimation error after $T$ rounds as
\[
\hat{\Delta}_T \;:=\;
\max_{1 \le i < j \le K}
\bigl| \, \hat{\Delta}_{ij} - \Delta_{ij} \, \bigr|.
\]
We aim for the $\hat{\Delta}_T$ to be as small as possible.
\subsection*{5. Performance Quantities}
Minimizing both cumulative regret and ATE estimation error is essential to balance effective decision-making with accurate statistical inference. Low regret indicates that the learner is consistently selecting high-performing arms and thus achieving strong reward performance. At the same time, a small ATE estimation error enables reliable comparisons between treatments, which is critical for understanding their relative effectiveness. To capture this trade-off, we aim to minimize the following objective:
\[
J \;:=\;
\mathbb{E}\!\bigl[ \sqrt{R_T} \bigr]
\;\cdot\;
\mathbb{E}\!\bigl[ \hat{\Delta}_T \bigr].
\]
We want to design a learning algorithm that can minimize $J$.
\subsection*{6. Two--phase algorithm design}
We aim to design a two-phase algorithm to minimize \(J\). Let \(\alpha\) and \(\beta\) satisfy \(1 \le K^{\alpha}L^{\beta} \le T\). The algorithm proceeds in two stages: an initial uniform exploration phase, followed by an adaptive exploitation phase based on the collected data.
\paragraph{Exploration phase (rounds $1,\dots,K^{\alpha}L^{\beta}$).}
Pull every arm in a round--robin fashion.
\paragraph{Exploitation phase (rounds $K^{\alpha}L^{\beta}+1,\dots,T$).}
Run the standard UCB rule.
The resulting $J$ is denoted $J(\alpha,\beta)$.
### Task
Here we analyze the asymptotic behavior of $J$, focusing only on the constants $K$ and $L$, ignoring the logarithmic term and other constant factors.
\textbf{Goal:} Find the upper bounds and lower bounds of $\alpha$ and $\beta$ $\{\bar\alpha,\bar\beta,\underline{\alpha},\underline{\beta}\}$ such that
\[
\forall \alpha \in [\bar\alpha,\underline{\alpha}],\ \forall \beta\in[\bar\beta,\underline{\beta}];\quad J(\alpha,\beta) = \min_{x,y \in S} J(x,y)
\]
where
\[
S \;:=\; \bigl\{\, \alpha,\beta \in \mathbb{R} \,:\; 1 \le K^{\alpha}L^\beta \le T \bigr\}.
\] | Zichen Wang |
Yiqi_02 | 4,385 | Computer Architecture Design | # Problem Definition of T10 Benchmark
To compute a matrix multiplication operator on an inter-core connected AI chip, we need you to derive an execution plan using T10's abstraction. For more information about this problem, please refer to "Background Information of T10 Benchmark".
**The Computation Task:**
The matrix multiplication (MatMul) to be computed is defined as $C[m,n] += A[m,k]*B[k,n]$, where $m = 32$, $k = 5120$, and $n = 15360$. The input and output tensors are all in FP16 format (2 bytes per data element). To find better partitioning plans, you may consider padding this operator along any of its dimensions. However, there will be performance overhead if you pad too much.
**The Hardware:**
We use an inter-core connected AI chip called IPU Mk2. An IPU chip has 1,472 cores, and each core executes independent threads in parallel with a private 624KB scratchpad memory, which adds up to a total of 896MB on-chip memory. The IPU cores are interconnected by high-bandwidth low-latency links. Each core can access the scratchpad memory of another core at 5.5GB/s, offering an aggregated inter-core all-to-all bandwidth of $1472 \times 5.5$ GB/s $\approx 8$ TB/s [1]. Inside each core, there is a systolic array of shape $16 \times 16$, which can compute a partition of the MatMul operator at high throughput. If the sub-MatMul to be computed on each core does not have a shape that is a multiple of the systolic array shape, this sub-MatMul must be padded to align with the systolic array shape.
**The Execution Plan:**
In this problem, we need you to derive a fast execution plan that computes the above MatMul on an IPU chip. First, this plan should ensure that at any time during execution, the sub-tensor partitions on each core do not overflow the per-core SRAM size. Second, the partition factors in this plan should comply with all constraints defined in T10's background information. Third, this plan should use no more than 1,472 cores. Finally, this plan should try to minimize the total execution time, which is the sum of per-core computation time and inter-core communication time.
**The Output Format:**
You should output the execution plan in the following format:
- `F_op`: a list of integers with length 3, which are the operator partition factors on dimensions $m$, $k$, and $n$, respectively.
- `f_t_A_m`: integer, which is the temporal partition factor of tensor A on dimension $m$.
- `f_t_A_k`: integer, which is the temporal partition factor of tensor A on dimension $k$.
- `f_t_B_k`: integer, which is the temporal partition factor of tensor B on dimension $k$.
- `f_t_B_n`: integer, which is the temporal partition factor of tensor B on dimension $n$.
- `f_t_C_m`: integer, which is the temporal partition factor of tensor C on dimension $m$.
- `f_t_C_n`: integer, which is the temporal partition factor of tensor C on dimension $n$.
---
# Background Information of T10 Benchmark
## 1. Inter-core Connected AI Chip
Deep learning accelerators, such as GPUs and TPUs, are widely recognized for their exceptional computing throughput (e.g., hundreds of Tera-FLOPS), making them ideal for handling large-scale models and high-dimensional data in deep learning. Such effectiveness is largely attributed to their massive parallel cores and specialized accelerator units, e.g., TensorCore. However, to saturate the high computing throughput, they usually require a high-throughput memory system, e.g., a large shared memory with multi-hierarchical cache layers in accelerators. Also, an efficient deep learning compiler [7, 8] is necessary to optimize data reuse across the memory hierarchy, ensuring the computing units are fully utilized. This combination of hardware and software design often yields orders of magnitude higher performance than traditional CPUs for critical deep learning operations, including matrix multiplication and convolution.
Despite the success of existing accelerators, the constantly increasing demand for processing large deep-learning models with higher computation throughput presents a significant challenge to the underlying memory system. To address this challenge, the community is exploring a more scalable architecture with fully distributed memory, such as the Graphcore IPU [2], SambaNova SN10 [5], and Cerebras WSE [3]. Rather than relying on shared-memory architecture, they typically associate each computation core with local memory, and connect the cores via a high-bandwidth on-chip network, creating a large aggregated on-chip memory. However, this unique architecture renders previous deep learning compilers designed for shared-memory architectures, which cannot fully leverage the new architecture's scalability, resulting in significant memory waste.
Designing a deep learning compiler for distributed memory-based accelerators presents several unique challenges:
1. Due to the absence of global shared memory, it is necessary to partition the operators, along with their input and output tensors, into sub-operators that can operate independently on each core with only local memory access.
2. As the local memory on each core is mostly on-chip memory, the aggregated memory capacity is considerably smaller than the off-chip memory. Thus, the compiler must effectively utilize the limited memory capacity to support a model size as large as possible, without compromising on computing performance.
3. Given that there is usually a trade-off between memory consumption and computation performance for each operator, an end-to-end model compilation must consider the trade-offs among all operators, generating a combinatorial optimization space that is infeasible to solve using existing compilers.
In this problem, we focus on a representative example of the inter-core connected AI chip: the Graphcore Intelligence Processing Unit (IPU) MK2 [2]. An IPU chip has 1,472 cores, and each core executes independent threads in parallel with a private 624KB scratchpad memory, which adds up to a total of 896MB on-chip memory. Compared to the global shared memory architecture, a key distinction is that IPU cores are interconnected by high-bandwidth low-latency links. Each core can access the scratchpad memory of another core at 5.5GB/s, offering an aggregated inter-core all-to-all bandwidth of $1472 \times 5.5$GB/s $\approx 8$TB/s [1].
---
## 2. Background of T10
To eliminate the excessive memory footprint and redundant inter-core communications of VGM, we map the DNN computation to a _compute-shift_ pattern. In each step, each core independently computes a sub-task with data received from its upstream neighbors and shifts the data to its downstream. The feasibility of this approach for general DNNs comes from this observation: most DNN operators can be divided into regular computation tasks, which load and produce consecutive data tiles of the input and output tensors, respectively.
Figure 1 shows an example that maps a MatMul operator to two cores with the compute-shift style execution.
Both (b) and (c) are valid compute-shift execution plans, but with different tradeoffs between memory footprint and communication overhead.
**Example: Mapping MatMul to Two Cores**
We show an example that maps a matrix multiplication (MatMul) operator to two cores in Figure 1 (a).
1. **Partitioning:** We first partition the operator along dimension $m$ onto two cores in Figure 1 (b). By default, both cores hold a copy of the weight tensor, which incurs memory capacity overhead.
2. **Memory Optimization:** To reduce memory footprint, in Figure 1 (c), we further split the weight tensor along dimension $n$ into two parts and place each part on one of the cores. Then, the computation must be conducted in two steps, as each core holds half of the weight tensor and performs half of its computation per step. Between the computation steps, each core circularly shifts its partition to the next core, forming a shift ring of two cores.
**Advantages of Compute-Shift Pattern**
1. Eliminates the need for a global memory to store shared data, improving memory capacity utilization.
2. Evenly distributes communication volume across inter-core connections.
3. Aligns computation with data tile, avoiding redundant communications to many cores.
**Tradeoff Between Memory Footprint and Communication Overhead**
For example, both Figure 1 (b) and (c) show valid execution plans:
- **Plan (b):** Finishes the entire computation in one step without inter-core communication, but has a higher memory footprint.
- **Plan (c):** Has less memory footprint but incurs more communication overhead.
In reality, deriving the best tradeoff is challenging due to multi-dimensional DNN operators and thousands of cores on an IPU chip. An efficient compute-shift execution plan may contain numerous nested shift rings along multiple tensor dimensions, composing a massive tradeoff space to search through.
---
## 3. T10's Execution Plan Format
### $r$Tensor: A New Tensor Abstraction
T10 introduces a distributed tensor abstraction called RotatingTensor ($r$Tensor). $r$Tensor describes how each tensor is partitioned, mapped, and shifted on the interconnected cores (summarized in Table 1).
**Table 1. Terminologies used in T10**
| **Symbol** | **Name** | **Description** |
|------------|------------------------------|-------------------------------------------------------------------------------|
| `f_s^X` | Spatial Partition Factor | Spatially partitions a tensor X into sub-tensors. |
| `f_t^X` | Temporal Partition Factor | Temporally partitions a sub-tensor of X into sub-tensor partitions. |
| `F_op` | Operator Partition Factor | Spatially partitions an entire operator into sub-operators. |
First, T10 partitions the computation of an operator onto multiple cores. Based on the data dependency, the computation partitioning will imply how each of its input/output tensor is partitioned. This gives a spatial partition factor ($f_s$), which splits a tensor into sub-tensors. Second, each sub-tensor may be required by multiple cores. To share a sub-tensor among them, we specify how the sub-tensor is further partitioned among the cores using a temporal partition factor ($f_t$). $f_t$ also specifies how the partitions of a sub-tensor are circularly shifted among the cores. Altogether, a set of $r$Tensors of an operator defines a compute-shift execution plan. The numerous possible $r$Tensor configurations of an operator generate a huge search space of execution plans.
Figure 2 shows the llustration of rTensor partitioning and rotating.
Specifically, $f_s$ and $f_t$ are vectors with a length equal to the number of dimensions of a tensor, indicating how the tensor is partitioned along each dimension. For example, in Figure 2 (a), a tensor $T$ of shape $[6,8]$ is partitioned onto 8 cores by a spatial factor $f_s=[2,1]$, forming 2 sub-tensors of shape $[3,8]$. Thus, to share each sub-tensor among 4 cores without incurring high memory footprint, a temporal factor $f_t=[1,2]$ further partitions each sub-tensor into 2 partitions with shape $[3,4]$, as shown in Figure 2 (b). It forms $\frac{4}{2} = 2$ rotation rings with 2 cores in each, where cores share the sub-tensor by circularly shifting its partitions. In comparison, Figure 2 (c) shows how another $f_t=[1,4]$ splits the same sub-tensor to 4 partitions, on $\frac{4}{4}=1$ rotation ring with 4 cores.
---
## 3.2. Compute-Shift Execution Plan
Using the $r$Tensor abstraction, T10 organizes the computation of a general DNN operator into a compute-shift pattern, where the operator's computation and tensors are partitioned to individual cores and their local memories. The entire computation involves multiple compute-shift steps until each tensor has been shifted across all cores. Each compute step is defined as a *sub-task*. In each compute-shift step, each core computes a sub-task and shifts local tensors to its neighbors. We now discuss how T10 partitions DNN operators into compute-shift-based execution plans.
### Operator representation.
To represent an operator's computation, T10 uses tensor expression [6], which defines how each output tensor value is computed from the input values. For example, a matrix multiplication of tensors $A$ in shape $[M,K]$ and $B$ in $[K,N]$ into $C$ is defined as
$C[m,n] \longleftarrow A[m,k]*B[k,n]$,
where $m$, $k$, and $n$ are axes to index the elements in each tensor. Equation (1) indicates that any value in $C$ indexed by $m$ and $n$ (i.e., $C[m,n]$) is computed by summing $A[m,k]*B[k,n]$ over all possible indices $k$. T10 supports all common operators, like MatMult and Convolution, from DNN workloads in both inference and training. For a few special cases like Sort, which cannot be represented in tensor expression, T10 uses the implementations from the vendor library.
### Partitioning an operator.
To map an operator to interconnected cores, T10 first partitions it into parallel *sub-operators* along all unique axes in its tensor expression, using an *operator partition factor* ($F_{op}$). For example, Equation (1) contains axes $m$, $k$, and $n$, then $F_{op}$ is a vector of three integer factors specifying how the three axes are spatially partitioned. The total number of sub-operators is the product of all elements in $F_{op}$. For example, $F_{op}=[2,1,4]$ for $[m,k,n]$ slices the operator into 8 sub-operators on 8 cores, each computing a $\lceil\frac{M}{2},\frac{K}{1}\rceil \times \lceil\frac{K}{1},\frac{N}{4}\rceil$ sub-matrix multiplication.
### Partitioning $r$Tensors.
T10 then uses $F_{op}$ to derive the spatial partition factor $f_s$ for each tensor, following the data dependencies in tensor expression. With the same example, for $F_{op}=[2,1,4]$ on $[m,k,n]$, the spatial partition factor for the tensor A is $f_s^A=[2,1]$ for axes $m$ and $k$. Similarly, for tensors B and C, we have $f_s^B=[1,4]$ and $f_s^C=[2,4]$.
If a tensor's dimensions do not include some axis in $F_{op}$, each of the sliced sub-tensors is required by multiple sub-operators along the missing axis. Thus, once the spatial factor determines the number of cores that will share a sub-tensor, the temporal factor determines how we split the sub-tensor across these cores into rotation ring(s). In the above example, $F_{op}$ partitions the entire operator onto $2 \times 1 \times 4 = 8$ cores, and $f_s^B$ spatially partitions tensor B into $1 \times 4 = 4$ sub-tensors. Thus, each sub-tensor is shared by $P=\frac{8}{4}=2$ cores. Then, a temporal factor $f_t^B=[2,1]$ further splits each sub-tensor into $2 \times 1 = 2$ partitions, forming $\frac{P}{2}=1$ rotation ring.
T10 enforces that the product of elements in $f_t$, or $\prod f_t$, is a divisor of the number of cores that shares the sub-tensor ($P$), so that the number of rotation rings (i.e., $\frac{P}{\prod f_t}$) is an integer. If there is more than one rotation ring, we replicate each sub-tensor $\frac{P}{\prod f_t}$ times to ensure that each ring shares one copy of the sub-tensor. While the duplication consumes memory space, it may reduce the number of rotation steps by allowing a larger sub-task on each core at each step, which enables a trade-off between memory usage and communication cost.
Figure 3 shows an example of the rotation of rTensor.
The compute-shift executions of the sub-operators need to be aligned.
### Aligning the rotations of $r$Tensors.
Since a general DNN operator can have various tensor shapes, a naive partitioning plan can easily cause the tensor shifting and the sub-task computing at an unaligned pace. In Figure 3 (a), we still use the MatMult operator in Equation (1) as an example. We partition it into a $2 \times 4$ grid in Figure 3 (b), with the specified partition factors. Note that both A and B are temporally partitioned along axis $k$, but with different $f_t$ factors.
The rotating paces of tensors in one operator must be aligned to ensure correct data dependency. In Figure 3 (b), tensors A and B are shifted with different paces along axis $k$. To synchronizes the paces, each core shifts A for 2 times along $k$ for each time B is shifted, and computes a sub-task (i.e., a sub-MatMult) of shape $[\text{m=1, k=1, n=1}]$ for each time A is shifted. This requires 4 compute steps to finish the sub-operator on this core, where A is shifted after each step and B is shifted every 2 steps.
### Alignment constraints.
To ensure that a $r$Tensor configuration can be translated into a valid execution plan, the product of the temporal partition factors of a tensor (i.e., the total number of temporal partitions) should be a factor of the replication number caused by spatial partitioning. Additionally, for different tensors of an operator that share a common dimension, all their temporal factors on this dimension should be aligned. Thus, any pair of temporal factors should be a factor or multiple of each other. This approach allows each tensor or sub-tensor to flow across cores at a different pace, while ensuring that corresponding tensor partitions can meet at the same time step on a specific core. For instance, in the matrix multiplication illustrated in Figure 3(b), tensor A has a temporal factor of 4 along dimension $k$, tensor B has a factor of 2, and these factors along $k$ (i.e., 4 and 2) must be a factor or multiple of each other.
### Sub-operator scheduling.
With the above constraints, we can organize an operator's computation into a valid compute-shift execution plan. At each step, each sub-operator computes a sub-task partitioned by $F_{op}$ and the $f_t$ along each axis. Each sub-operator iterates over all its sub-tasks by nested-looping through the axes of this operator. Between sub-tasks, an $r$Tensor is rotated along the currently iterating axis for all its sub-tensors, until all sub-tasks are enumerated.
Specifically, T10 organizes the computation on each core as nested loops of interleaved compute and shift stages. Each loop corresponds to a temporally partitioned dimension. For example, if there are two dimensions to shift, $m$ and $n$, with $m$ shifting twice and $n$ shifting once, then there are two valid 5-time shift schedules: (1) $m$ is the inner loop, i.e., $\text{shift}(m) \times 2 \rightarrow \text{shift}(n) \rightarrow \text{shift}(m) \times 2$; and (2) $n$ is the inner loop, i.e., $\text{shift}(n) \rightarrow \text{shift}(m) \rightarrow \text{shift}(n) \rightarrow \text{shift}(m) \rightarrow \text{shift}(n)$. To determine the optimal loop order, T10 designates the dimension belonging to the tensor with the smaller size as the inner loop to reduce the total communication volume, as the inner loop is executed more times. To generate local computations for each core, T10 invokes the corresponding compute function with the partition configuration and the tensor expression.
---
# References
[1] Zhe Jia, Blake Tillman, Marco Maggioni, and Daniele Paolo Scarpazza. 2019. Dissecting the Graphcore IPU Architecture via Microbenchmarking.
[2] Simon Knowles. 2021. Graphcore Colossus Mk2 IPU.
[3] Sean Lie. 2021. Multi-Million Core, Multi-Wafer AI Cluster.
[4] Yiqi Liu et al. 2024. Scaling Deep Learning Computation over the Inter-Core Connected Intelligence Processor with T10.
[5] Raghu Prabhakar and Sumti Jairath. 2021. SambaNova SN10 RDU.
[6] Nicolas Vasilache et al. 2018. Tensor Comprehensions.
[7] Lianmin Zheng et al. 2020. Ansor.
[8] Hongyu Zhu et al. 2022. ROLLER. | Yiqi Liu |
XW_01 | 1,116 | Operating System Design | ## Task Description
In this task, you will be provided with a filesystem image. You are required to develop separate programs—each implementing a different filesystem operation (e.g., create, read, update, delete)—to modify the corresponding sections of that image. Your objective is to ensure that each program correctly performs its assigned operation on the intended part of the filesystem image while preserving its overall integrity.
Here is the class definition for your reference:
from dataclasses import dataclass, field
from typing import List, Dict, Optional
@dataclass
class SuperBlock:
"""File system superblock, stores metadata."""
block_size: int # Size of each block (bytes)
total_blocks: int # Total number of blocks
inode_count: int # Total number of inodes
free_block_bitmap: List[bool] # Free block bitmap, True = free
@dataclass
class Inode:
"""Inode structure, stores file/directory metadata."""
ino: int # Inode number
is_dir: bool # Whether this inode is a directory
size: int # File size (bytes)
direct_blocks: List[int] # List of direct block indices
# Optional: add indirect block pointers, multi-level indexing, permissions, timestamps, etc.
@dataclass
class DirEntry:
"""Directory entry: maps a filename to an inode."""
name: str
inode: int
@dataclass
class FileSystemImage:
"""Complete file system image structure."""
superblock: SuperBlock
inodes: Dict[int, Inode] = field(default_factory=dict)
# Directory tree: inode -> list of entries in that directory; valid only for is_dir=True inodes
directories: Dict[int, List[DirEntry]] = field(default_factory=dict)
# Data block storage area: index corresponds to block number, content is bytes
data_blocks: List[Optional[bytes]] = field(default_factory=list)
def __post_init__(self):
# Initialize data block storage area
if not self.data_blocks:
self.data_blocks = [None] * self.superblock.total_blocks
def allocate_block(self) -> int:
"""Allocate a block from the free bitmap and return its index; raise if none available."""
for idx, free in enumerate(self.superblock.free_block_bitmap):
if free:
self.superblock.free_block_bitmap[idx] = False
self.data_blocks[idx] = b'' # Initialize with empty content
return idx
raise RuntimeError("No free blocks available")
def free_block(self, block_idx: int):
"""Free the specified block index."""
if 0 <= block_idx < self.superblock.total_blocks:
self.superblock.free_block_bitmap[block_idx] = True
self.data_blocks[block_idx] = None
else:
raise IndexError("Block index out of range")
def create_inode(self, is_dir: bool) -> Inode:
"""Create a new inode and return it."""
new_ino = len(self.inodes) + 1
if new_ino > self.superblock.inode_count:
raise RuntimeError("No free inodes")
inode = Inode(
ino=new_ino,
is_dir=is_dir,
size=0,
direct_blocks=[]
)
self.inodes[new_ino] = inode
if is_dir:
self.directories[new_ino] = []
return inode
def add_dir_entry(self, dir_ino: int, name: str, inode: int):
"""Add a directory entry to the directory with inode dir_ino."""
if dir_ino not in self.directories:
raise RuntimeError("Not a directory inode")
self.directories[dir_ino].append(DirEntry(name=name, inode=inode))
### Task 1
def read(fs_img: FileSystemImage, name: str, pos: int, length: int) -> str:
"""
Read up to `length` bytes from the file called `name` in the given FileSystemImage,
starting at byte offset `pos`, and return the data as a Python string (decoded as UTF‑8).
Parameters:
- fs_img: the FileSystemImage instance containing inodes, directories, and data blocks.
- name: an absolute or relative path to the target file within `fs_img`.
- pos: the byte offset within the file at which to begin reading.
- length: the maximum number of bytes to read.
Returns:
- A Python `str` containing the bytes read, decoded from UTF‑8.
Behavior:
1. If the file `name` does not exist or refers to a directory, raise a `FileNotFoundError` or `IsADirectoryError` respectively.
2. If `pos` is negative or exceeds the file’s size, raise an `ValueError`.
3. If `pos + length` extends beyond the end of file, read only up to EOF.
4. Read the appropriate data blocks from `fs_img.data_blocks` according to the file’s inode `direct_blocks`, concatenating and slicing as needed.
5. Decode the resulting bytes to a UTF‑8 string and return it.
"""
# Your implementation here…
| Licheng Xu,Jinwen Wang |
HJ_01 | 192 | Robotics | ## Task Description
The company let you assembly a car for track following design competition. The car control is simply a look ahead point tracking model. A path with length of 56 meters is given, and your car should finish test in 10 sec with max tolerance 1 meters of track-off distance. You are given 300 dolors budget. You can control four different value: refresh rate, acceleration, max velocity and lookahead distance. The refreshing cost is 5 dollar/hz; the acceleration cost is 10 dolors/ m/s^2; the max motor velocity is 8 dolors/ m/s, and the look ahead camera distance cost 1 dolor/ meter.
### Task
Your task is to design the car setup with: refresh rate, acceleration, max velocity and lookahead distance so that:
Total runtime < 10 sec
Max off-track error < 1 meter
Budget cost < 300 dollars
| Jingjie He |
ZC_02 | 420 | Control Design | ## Task Description
Consider the discrete‐time Lurye feedback interconnection composed of the following blocks:
Nonlinear block:
\[
w_k = \phi(v_k),
\quad
\phi:\mathbb R\to\mathbb R\text{ satisfies }
0 \;\le\; \frac{\phi(v_1)-\phi(v_2)}{v_1-v_2}\;\le\;1,
\;\forall v_1\neq v_2.
\]
Linear time‐invariant block:
\[
\begin{cases}
x_{k+1} = A\,x_k + \alpha\,B\,w_k,\\
y_k = C\,x_k + D\,w_k,
\end{cases}
\quad
\alpha>0\text{ multiplies the input matrix }B,
\]
with numerical values
\[
A = \begin{bmatrix}0.5000 & 0 \\1.0000 & 0\end{bmatrix},
B = \begin{bmatrix}1 \\0\end{bmatrix},\quad
C = \begin{bmatrix}2.0000 & 0.9200\end{bmatrix},
D = [\,0\,].
\]
Interconnection：
\[
v_k = d_k - y_k,\qquad
w_k = \phi(v_k),\qquad
e_k = w_k.
\]
### Task
Calculate the $\alpha$ where
\[
\alpha_{\max}
= \max\bigl\{\alpha>0 \mid \text{the closed‐loop is absolutely stable for all }\phi\text{ in the sector}\bigr\}.
\]
Please note the properties of the nonlinear operator $\phi$, you are encouraged to use semidefinite programming and bisection.
| Zichen Wang |
Ziheng_01 | 593 | Control Design | ## Task Description
You are given an aircraft pitch-axis plant model and asked to design a Robust-Servo LQR (RS-LQR) controller. Consider the continuous‐time state–space model
\[
\dot{\bm x}_p = A_p\,\bm x_p + B_p\,u,\quad
y = C_p\,\bm x_p + D_p\,u,
\]
where
\[
\bm x_p = [\alpha,\; q,\; \delta_e,\;\dot\delta_e]^T,\quad
u = \delta_{\mathrm{cmd}},\quad
y = [A_z,\;\alpha,\;q,\;\delta_e,\;\dot\delta_e]^T.
\]
The plant matrices are
\[
A_p = \begin{bmatrix}
-1.3046 & 1.0 & -0.21420 & 0 \\
47.71 & 0 & -104.83 & 0 \\
0 & 0 & 0 & 1.0 \\
0 & 0 & -12769.0 & -135.6
\end{bmatrix},\quad
B_p = [0,\;0,\;0,\;12769.0]^T,
\]
\[
C_p = \begin{bmatrix}
-1156.9 & 0 & -189.95 & 0 \\
1 & 0 & 0 & 0 \\
0 & 1 & 0 & 0 \\
0 & 0 & 1 & 0 \\
0 & 0 & 0 & 1
\end{bmatrix},\quad
D_p = \mathbf{0}_{5\times1}.
\]
Design a dynamic state–feedback controller
\[
\dot{\bm x}_c = A_c\,\bm x_c + B_{c1}\,y + B_{c2}\,r,\quad
u = C_c\,\bm x_c + D_{c1}\,y + D_{c2}\,r,
\]
such that:
\begin{itemize}
\item The closed‐loop rise time of \(A_z\) is \(<0.2\) s.
\item The system is stable.
\item The gain margin is \(>3\) dB.
\item The phase margin is \(>30\) degrees.
\end{itemize}
Please output all six controller matrices Ac, Bc1, Bc2, Cc, Dc1, Dc2 that satisfies the above requirements. | Ziheng Guo |
XG_02 | 681 | Control Design | Consider a nanopositioning stage modeled by the following seventh-order linear state-space system. This model is fitted to frequency response data collected from the physical device:
A = \begin{bmatrix}
-3360.27884342382 & 24650.4407238876 & -24650.4407238876 & 24650.4407238876 & -24650.4407238876 & 24650.4407238876 & -6162.61018097190 \\
-3270.26403683917 & 10278.7248098086 & -7476.39347226054 & 7476.39347226054 & -7476.39347226054 & 7476.39347226054 & -1869.09836806513 \\
-2657.10970968037 & 10628.4388387215 & -13430.7701762696 & 16233.1015138177 & -16233.1015138177 & 16233.1015138177 & -4058.27537845441 \\
-3954.03177459846 & 15816.1270983939 & -15816.1270983939 & 13013.7957608458 & -10211.4644232977 & 10211.4644232977 & -2552.86610582443 \\
-2325.45756017668 & 9301.83024070671 & -9301.83024070671 & 9301.83024070671 & -12104.1615782548 & 14906.4929158029 & -3726.62322895072 \\
-1665.81075466004 & 6663.24301864017 & -6663.24301864017 & 6663.24301864017 & -6663.24301864017 & 3860.91168109210 & -264.645085886005 \\
-1596.51916299641 & 6386.07665198562 & -6386.07665198562 & 6386.07665198562 & -6386.07665198562 & 6386.07665198562 & -4398.85050054448 \\
\end{bmatrix},
B = \begin{bmatrix}
33.1501 \\
29.2147 \\
49.7430 \\
55.4071 \\
43.2351 \\
22.8726 \\
24.9153 \\
\end{bmatrix},
C = \begin{bmatrix}
41.1585 & -164.6342 & 164.6342 & -164.6342 & 164.6342 & -164.6342 & 41.1585
\end{bmatrix}
D = \begin{bmatrix}
0
\end{bmatrix}.
Your task is to design a robust feedback controller using the loop shaping method that satisfies the following frequency-domain performance requirements:
-Closed-loop bandwidth: approximately 85 Hz (±10 Hz tolerance)
-Gain margin: greater than 1.5 dB
-Phase margin: greater than 60 degrees
| Xingang Guo |
XG_05 | 378 | Control Design | ## Task Description
In this task, you are required to design a feedback controller to regulate the temperature of a chemical reactor using a heat exchanger system. The reactor, modeled as a stirred tank, is shown in the accompanying figure. A liquid stream enters the tank from the top inlet and is continuously mixed. To maintain the liquid at a desired constant temperature, the amount of steam supplied to the heat exchanger (located at the bottom of the tank) must be adjusted. This is achieved by modulating the control valve that governs steam flow. Your objective is to design a controller that ensures the reactor temperature remains stable and responds effectively to disturbances and setpoint changes.
### Task 1
Your first task is to derive a first-order with delay transfer function $G(s) = exp(-theta*s)/(1+tau*s)$ to model the dynamics of the stirred tank. The second figure shows a measured step response of the stirred tank, with $t_1 = 23$ s and $t_2 = 36$ s. The values of $t_1$ and $t_2$ are the times where the step response reaches 28.3% and 63.2% of its final value, respectively. Please determine the value of $\theta$ and $\tau$ from the step response figure using the given information. Then the transfer function will be $G(s) = exp(-theta*s)/(1+tau*s)$.
### Task 2
Your second task is to design a feedback controller to regulate the temperature of the stirred tank using the model you derived in Task 1 that satisfies the following requirements:
- Gain margin: >= 7 dB
- Phase margin: >= 60 degrees
- Overshoot: <= 10% (for a step reference input)
- Settling time: <= 150 s (for a step reference input)
| Xingang Guo |
YF_05 | 454 | Structure Design | ## Task Description
In this task, you are required to determine a suitable cross-sectional area A for a specified member of a simple 2D truss, which will be evaluated using a static linear-elastic finite-element model in MATLAB.
The truss is defined by three nodes and three pin-connected members forming a right triangle:
You are given the following fixed parameters:
- Nodes (coordinates in mm):
Node1 - (0,0) (ux=uy=0)
Node2 - (1000,0)(uy = 0)
Node3 - (1000,1000)
- A vertical downward force of 4000 N applied at Node 3
- Members (element connectivity):
Node 1 → Node 2 (A = 100mm^2)
Node 2 → Node 3 ← design this member’s area
Node 1 → Node 3 (A = 100mm^2)
- Material properties:
- Young’s modulus: 210,000 MPa
- Poisson’s ratio: 0.3
Performance criterion:
The maximum nodal displacement must satisfy δ max < 0.5mm
The score depends on the ratio of the maximum measured angle to the allowable threshold. If that ratio falls between seventy percent and ninety percent, the beam earns the full 100 points. If the ratio is below seventy percent, partial credit is awarded in direct proportion to how close it is to seventy-percent (with zero displacement scoring zero and seventy-percent scoring 100). If the ratio lies between ninety percent and one hundred percent, points are deducted in proportion to how far it exceeds ninety percent (dropping from 100 at ninety percent down to zero at the full threshold). Any ratio below zero or above one hundred percent results in a score of zero.
---
### Task
Your task is to:
- a structurally sound value for the area A (in mm²) of the member between Node 2 and Node 3. You must have a numerical computation and analysis.
- Provide a brief justification for your choice of thickness, considering stiffness, loading, and geometric constraints
You do **not** need to evaluate the angle yourself. The simulation and evaluation will be done separately.
| Yufan Zhang |
YF_02 | 450 | Structure Design | ## Task Description
In this task, you are required to determine a suitable thickness (Th) of a rectangular steel beam subjected to a dual-point load, applied at the quarter-span locations, and evaluated using 3D structural simulation in MATLAB’s PDE Toolbox.
The beam is modeled as a simply supported rectangular beam with a solid rectangular cross-section (width × thickness). It is loaded vertically downward by two equal forces applied symmetrically at 1/4 and 3/4 of the beam span.
You are given the following fixed parameters:
- 'L = 1000' mm (Total span length)
- 'w = 40' mm (Beam width, constant)
- 'Height = Th' mm (Beam thickness to be designed)
- Two vertical downward forces: F = 1000 N each, applied at quarter-span locations
- Material properties:
- Young’s modulus: 210,000 MPa
- Poisson’s ratio: 0.3
The beam will be evaluated using a static linear elasticity model in 3D (extruded along the beam width). The performance criterion is that the maximum vertical displacement (uy) must be less than 1 mm under the given load.
The score depends on the ratio of the maximum measured displacement to the allowable threshold. If that ratio falls between seventy percent and ninety percent, the beam earns the full 100 points. If the ratio is below seventy percent, partial credit is awarded in direct proportion to how close it is to seventy-percent (with zero displacement scoring zero and seventy-percent scoring 100). If the ratio lies between ninety percent and one hundred percent, points are deducted in proportion to how far it exceeds ninety percent (dropping from 100 at ninety percent down to zero at the full threshold). Any ratio below zero or above one hundred percent results in a score of zero.
---
### Task
Your task is to:
- Propose a structurally sound value for `Th` (thickness of the beam, in mm)
- Provide a brief justification for your choice of thickness, considering stiffness, loading, and geometric constraints
You do **not** need to evaluate the displacement yourself. The simulation and evaluation will be done separately.
| Yufan Zhang |
qjlim2_01 | 356 | Signal Processing | ## Background
Microstrip patch antennas are widely used in modern wireless communication due to their low profile, ease of fabrication, and compatibility with printed circuit board (PCB) technology.
In this task, you are to design a rectangular microstrip patch antenna that satisfy the task objective and constraints stated below.
The antenna is centered at the origin with the patch facing the +z direction. The feed point lies in the x-y plane. The dielectric substrate must be selected from commercially available Rogers low-loss laminates, and the chosen material's permittivity will influence the design.
## Task Objective and Constraints
Your task is to design a rectangular microstrip patch antenna that meets the following specifications:
- Resonant Frequency: 1.537 GHz (S11 <= –10 dB)
- Bandwidth: >= 50 MHz
- Gain: >= 3 dBi
- Volume Constraint (Ground Plane Size) [ Length × Width × Height ]: <= 100 mm × 100 mm × 10 mm
- Feed Method: 50-ohm coaxial pin feed (from below substrate)
- Substrate Material: Rogers low-loss laminate (commercially available)
## Design Inputs
Determine the optimal design parameters to satisfy the task objectives:
- Length of Metallic Patch in mm: length_mm
- Width of Metallic Patch in mm: width_mm
- Substrate height in mm: height_mm
- Relative permittivity of selected Rogers material: epsilon_r
- Feed position in the x direction relative to patch center: feed_offset_x_mm
- Confidence of your design: confidence
## Design Context
- Ground Plane Size is 1.5 times max(Length, Width)
- Patch size (Length and Width) have to be smaller than ground plane size
| Qi Jian Lim
|
XZ_03 | 1,485 | Robotics | ## Task Description
You are given a Webots world file named 'construction_site.wbt' with some walls (obstacles) and a controller file named "robot_controller.py", you should first read the world info as shown below, then choose a path planning algorithm to generate the shortest path from start point to goal point without hitting any obstacles or walls. The path should satisfy the following requirements: The small inspection robot's starting position is at the site entrance (0,0,0), and we set the goal position to the far corner inspection point (49,39,0). Suppose this inspection robot can only navigate on grid nodes (i.e., x and y values are integers).
The construction_site.wbt contains the following world info:
#VRML_SIM R2025a utf8
EXTERNPROTO "https://raw.githubusercontent.com/cyberbotics/webots/R2025a/projects/objects/backgrounds/protos/TexturedBackground.proto"
EXTERNPROTO "https://raw.githubusercontent.com/cyberbotics/webots/R2025a/projects/objects/backgrounds/protos/TexturedBackgroundLight.proto"
WorldInfo {
basicTimeStep 16
}
Viewpoint {
orientation 0.57 -0.495 -0.656 4.55
position 3.88 -16.8 99.5
}
TexturedBackground {
}
TexturedBackgroundLight {
}
DEF FLOOR Solid {
translation 25 20 0
name "floor"
children [
Shape {
appearance PBRAppearance {
baseColor 0.8 0.8 0.8
roughness 1
metalness 0
}
geometry Box {
size 50 40 0.1
}
}
]
boundingObject Box {
size 50 40 0.1
}
}
# Vertical wall from (10,5) to (10,35)
DEF VERTICAL_WALL_1 Solid {
translation 10 20 0.5
name "vertical_wall_1"
children [
Shape {
appearance PBRAppearance {
baseColor 0.6 0.6 0.6
}
geometry Box {
size 1 30 1
}
}
]
boundingObject Box {
size 1 30 1
}
}
# Horizontal wall from (10,20) to (40,20)
DEF HORIZONTAL_WALL Solid {
translation 25 20 0.5
name "horizontal_wall"
children [
Shape {
appearance PBRAppearance {
baseColor 0.6 0.6 0.6
}
geometry Box {
size 30 1 1
}
}
]
boundingObject Box {
size 30 1 1
}
}
# Vertical wall from (30,0) to (30,15)
DEF VERTICAL_WALL_2 Solid {
translation 30 7.5 0.5
name "vertical_wall_2"
children [
Shape {
appearance PBRAppearance {
baseColor 0.6 0.6 0.6
}
geometry Box {
size 1 15 1
}
}
]
boundingObject Box {
size 1 15 1
}
}
# Obstacle cluster from (20,25) to (25,30)
DEF OBSTACLE_CLUSTER Solid {
translation 22.5 27.5 0.5
name "obstacle_cluster"
children [
Shape {
appearance PBRAppearance {
baseColor 0.6 0.6 0.6
}
geometry Box {
size 5 5 1
}
}
]
boundingObject Box {
size 5 5 1
}
}
# Random obstacles
DEF OBSTACLE_1 Solid {
translation 15 10 0.5
name "obstacle_1"
children [
Shape {
appearance PBRAppearance {
baseColor 0.6 0.6 0.6
}
geometry Box {
size 1 1 1
}
}
]
boundingObject Box {
size 1 1 1
}
}
DEF OBSTACLE_2 Solid {
translation 25 5 0.5
name "obstacle_2"
children [
Shape {
appearance PBRAppearance {
baseColor 0.6 0.6 0.6
}
geometry Box {
size 1 1 1
}
}
]
boundingObject Box {
size 1 1 1
}
}
DEF OBSTACLE_3 Solid {
translation 35 25 0.5
name "obstacle_3"
children [
Shape {
appearance PBRAppearance {
baseColor 0.6 0.6 0.6
}
geometry Box {
size 1 1 1
}
}
]
boundingObject Box {
size 1 1 1
}
}
DEF OBSTACLE_4 Solid {
translation 40 30 0.5
name "obstacle_4"
children [
Shape {
appearance PBRAppearance {
baseColor 0.6 0.6 0.6
}
geometry Box {
size 1 1 1
}
}
]
boundingObject Box {
size 1 1 1
}
}
DEF OBSTACLE_5 Solid {
translation 45 15 0.5
name "obstacle_5"
children [
Shape {
appearance PBRAppearance {
baseColor 0.6 0.6 0.6
}
geometry Box {
size 1 1 1
}
}
]
boundingObject Box {
size 1 1 1
}
}
# Robot node - simplified to avoid physical features
Robot {
translation 0 0 0.5
name "robot"
controller "robot_controller"
supervisor TRUE
children [
Shape {
appearance PBRAppearance {
baseColor 1 0 0
roughness 1
metalness 0
}
geometry Sphere {
radius 0.500000
subdivision 2
}
}
]
boundingObject Sphere {
radius 0.500000
}
}
## Required Results:
1. The complete path as an ordered list of coordinates from start to goal
2. The total path length (in meters)
3. The algorithm used (A*, Dijkstra, etc.)
4. The number of nodes explored during the search
5. Whether 4-connected or 8-connected movement was used | Xiayu Zhao
|
XZ_04 | 1,452 | Robotics | ## Task Description
You are given a Webots world file named 'construction_site.wbt' with some walls (obstacles) and a controller file named "robot_controller.py", you should first read the world info as shown below, then generate a trajectory from start point to goal point without hitting any obstacles. The trajectory should satisfy the following requirements:
1. The format of trajectory should be written as (t, X, Y, Z, v, a), where t is time, X, Y, Z are the 3D coordinates of the robot, v is velocity, a is acceleration. The small inspection robot's starting position is at the site entrance (0,0,0,0,0,0), and we set the goal position to the far corner inspection point (t,19,24,0,0,a).
2. The trajectory should follow the safety constraints:
2.1 In the WHITE_ZONE solid area, the robot's maximum speed should not exceed 1m/s;
2.2 In the RED_ZONE solid area, the robot's maximum speed should not exceed 2m/s;
2.3 In the GREEN_ZONE solid area, the robot's maximum speed should not exceed 0.5m/s;
3. The entire trajectory can only be in the above three zones, i.e., the robot can not move out from those zones.
The construction_site.wbt contains the following world info (the length unit is meter):
#VRML_SIM R2025a utf8
EXTERNPROTO "https://raw.githubusercontent.com/cyberbotics/webots/R2025a/projects/objects/backgrounds/protos/TexturedBackground.proto"
EXTERNPROTO "https://raw.githubusercontent.com/cyberbotics/webots/R2025a/projects/objects/backgrounds/protos/TexturedBackgroundLight.proto"
WorldInfo {
basicTimeStep 16
}
Viewpoint {
orientation 0.5228920141164687 -0.5800081356561211 -0.6246394993481706 4.784396651657472
position -24.923416016240427 -15.86980776668673 82.27805548757286
}
TexturedBackground {
}
TexturedBackgroundLight {
}
DEF WHITE_ZONE Solid {
translation 0.11 7.12 0
children [
Shape {
appearance PBRAppearance {
baseColor 0.8 0.8 0.8
roughness 1
metalness 0
}
geometry Box {
size 10 15 0.1
}
}
]
name "floor"
boundingObject Box {
size 10 15 0.1
}
}
DEF RED_ZONE Solid {
translation 0.11 22.11 0
children [
Shape {
appearance DEF red PBRAppearance {
baseColor 0.666667 0 0
roughness 1
metalness 0
}
geometry Box {
size 10 15 0.1
}
}
]
name "floor(1)"
boundingObject Box {
size 10 15 0.1
}
}
DEF GREEN_ZONE Solid {
translation 12.63 24.61 0
rotation 0 0 1 -1.5707953071795862
children [
Shape {
appearance DEF green PBRAppearance {
baseColor 0 0.333333 0
roughness 1
metalness 0
}
geometry Box {
size 10 15 0.1
}
}
]
name "floor(2)"
boundingObject Box {
size 10 15 0.1
}
}
DEF OBSTACLE_2 Solid {
translation -0.41 4.78 0.5
children [
Shape {
appearance PBRAppearance {
baseColor 0.6 0.6 0.6
}
geometry Box {
size 1 1 1
}
}
]
name "obstacle_4"
boundingObject Box {
size 1 1 1
}
}
DEF OBSTACLE_3 Solid {
translation 1.58 11.04 0.5
children [
Shape {
appearance PBRAppearance {
baseColor 0.6 0.6 0.6
}
geometry Box {
size 1 1 1
}
}
]
name "obstacle_5"
boundingObject Box {
size 1 1 1
}
}
DEF OBSTACLE_1 Solid {
translation 3.24 21.69 0.5
children [
Shape {
appearance PBRAppearance {
baseColor 0.6 0.6 0.6
}
geometry Box {
size 1 1 1
}
}
]
name "obstacle_5(1)"
boundingObject Box {
size 1 1 1
}
}
DEF OBSTACLE_4 Solid {
translation -1.76 18.4 0.5
children [
Shape {
appearance PBRAppearance {
baseColor 0.6 0.6 0.6
}
geometry Box {
size 1 1 1
}
}
]
name "obstacle_5(3)"
boundingObject Box {
size 1 1 1
}
}
DEF OBSTACLE_5 Solid {
translation 13.45 24.52 0.5
children [
Shape {
appearance PBRAppearance {
baseColor 0.6 0.6 0.6
}
geometry Box {
size 1 1 1
}
}
]
name "obstacle_5(2)"
boundingObject Box {
size 1 1 1
}
}
Robot {
translation 0 0 0.5
children [
Shape {
appearance PBRAppearance {
baseColor 1 0 0
roughness 1
metalness 0
}
geometry Sphere {
radius 0.5
subdivision 2
}
}
]
boundingObject Sphere {
radius 0.5
}
controller "robot_controller"
supervisor TRUE
}
## Required Results:
1. The complete trajectory from start to goal
2. The total travel time (in second)
3. The total path length (in meters)
4. The number of nodes explored during the search | Xiayu Zhao
|
YZ_04 | 340 | Mechanical Systems | ## Task Description
In this task, you are required to design a battery module for electric vehicle applications using the data from a Lithium-Ferrous-Phosphate (LFP) cell characterized at multiple temperatures. The battery must support a 100 A fast-charge for up to 20 minutes, and the resulting temperature rise in each cell should stay within specified limits. You will also design and parameterize a cooling system (with a parallel channel configuration) so that the maximum temperature gradient across the module and the pressure drop of the coolant remain within their respective constraints.
### Task 1
The given HPPC data uses a 40 A pulse, but your final design must handle a continuous charge rate of 100 A, so that you need to specify the following parameters of battery module to satisfy this need:
- numCells_p, the number of cells in the parallel set.
- numCells_s, the number of series connected parallel set.
### Task 2
Your second task is to determine the desired parameters for the cooling plate. As a result, the cooling plate you designed must keep the battery within reasonable temperatures during its operation. Below are the detailed requirements:
- The maximum rise in cell temperature must be lower than or equal to 10 degree Celsius.
- The maximum temperature gradient within a module must not exceed 5 degree Celsius.
- The maximum acceptable pressure drop for the module cooling system must be less than 20kPa.
The design parameters for the cooling plate you need to specify includes:
- NumChannel, the number of cooling channels.
- Flowrate, the applicable coolant flow-rate.
- ChannelDia, the channel diameter, typically < 0.01. | Yizhou Zhao |
YZ_03 | 619 | Signal Processing | ## Task Description
In this task, you are required to design a helical antenna for use in mobile and satellite communications, operating in axial mode to produce circularly polarized radiation along its main axis. The helical antenna must be designed to meet specific frequency and performance criteria. Your final goal is to determine appropriate parameters for a helical antenna implemented using the MATLAB antenna toolbox, ensuring it satisfies specific requirements in terms of directivity variation and axial ratio. Notably, the helix model in the toolbox uses a strip approximation, which relates the width of the strip to the radius of an equivalent cylinder.
### Task 1
Your first task is to calculate the relative bandwidth (less than 1), based on the following frequency range and center frequency:
- Frequency range: 1.3 - 2 GHz
- Center frequency: 1.65 GHz
### Task 2
Your second task is to determine a set of appropriate parameters for the helical antenna design using the MATLAB toolbox. Since the helix model in the toolbox has a circular ground plane, the radius of the ground plane should be set to half the side length of an equivalent square ground plane. Specifically, the parameters you need to consider include:
- $r$, the radius of cylinder, must be less than 0.0005
- $D$, the diameter of the helical antenna, must satisfy $0.05 < D < 0.06$.
- $turns$, the number of helical turns
- $pitch$, the pitch of the helix, which must be greater than 5 deg
- $side$, the side length of the square ground plane, must be greater than 0.3.
The helical antenna will be created and evaluated using the MATLAB code shown below. The frequency range and center frequency are given in Task 1:
</code_block>
% design helix antenna
width = cylinder2strip(r);
feedheight = 3*r;
radius = D/2;
spacing = helixpitch2spacing(pitch,radius);
radiusGP = side/2;
hx = helix(Radius=radius,Width=width,Turns=turns,...
Spacing=spacing,GroundPlaneRadius=radiusGP,...
FeedStubHeight=feedheight);
% directivity as a function of frequency
freq = [1.3e9, 1.65e9, 2.0e9];
Nf = length(freq);
D = nan(1, Nf);
for i = 1:Nf
D(i) = pattern(hx, freq(i), 0, 90);
end
% axial ratio at center frequency
ar_dB = axialRatio(hx, freq, 0, 90);
</code_block>
The helix antenna you design must satisfy the following requirements:
- r: < D / (20 * 3.14)
- Directivity range: 13 dBi +/- 1.5 dBi
- Axial Ratio: < 1.5 | Yizhou Zhao |
YJ_01 | 423 | Structure Design | ## Task Description
In this task, you are required to determine the optimal material distribution within a 2D design domain to minimize structural compliance under a given set of physical constraints. The domain is a fixed-size grid of **64 × 64 elements**. Each design must satisfy the specified boundary conditions, load configurations, and a volume fraction constraint.
## Input
The input consists of a 5-channel tensor, where each channel is a **64 × 64 NumPy array (.npy format)** representing:
- **Channel 1**: volume fraction, prescribed uniformly or non-uniformly across the grid.
- **Channel 2**: von Mises stress under the given loading and boundary conditions.
- **Channel 3**: Strain energy distribution under the same conditions.
- **Channel 4**: x-direction load magnitude at each node (0 if none).
- **Channel 5**: y-direction load magnitude at each node (0 if none).
The inputs are specified in five 64x64 numpy array:
- channel 1: A 64x64 matrix with each element equal 0.48
- channel 2:[[3.02378885e-06 4.47539433e-06 7.50072817e-06 1.20186311e-05
1.80109097e-05 2.54543330e-05 3.43215513e-05 4.45822821e-05
5.62047910e-05 6.91577125e-05 8.34122703e-05 9.89449821e-05
1.15740968e-04 1.33798037e-04 1.53131780e-04 1.73782043e-04
1.95821249e-04 2.19365323e-04 2.44588274e-04 2.71741967e-04
3.01183312e-04 3.33411876e-04 3.69121785e-04 4.09269653e-04
4.55158574e-04 5.08461270e-04 5.71189253e-04 6.43753731e-04
7.24444883e-04 8.61603091e-04 7.41751328e-03 1.26088212e-02
2.28558406e-02 1.90377994e-02 2.29648198e-03 5.74503268e-04
1.70806693e-04 5.59472407e-05 2.40936179e-05 2.09785195e-05
2.83383866e-05 3.92710245e-05 5.09601691e-05 6.22304338e-05
7.26109646e-05 8.19471512e-05 9.02286714e-05 9.75098238e-05
1.03871446e-04 1.09402429e-04 1.14190775e-04 1.18319405e-04
1.21864365e-04 1.24894237e-04 1.27470146e-04 1.29646034e-04
1.31469059e-04 1.32980001e-04 1.34213660e-04 1.35199214e-04
1.35960520e-04 1.36516369e-04 1.36880691e-04 1.35381261e-04]
[9.99441870e-06 1.12235038e-05 1.38634008e-05 1.78071154e-05
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0.05069798 0.0477767 0.0451893 0.04290617 0.04089462 0.03912271
0.03756104 0.03618333 0.03496648 0.03389044 0.0329378 0.03209357
0.03134474 0.0306801 0.03008991 0.02956573 0.02910019 0.02868689
0.02832022 0.02799528 0.02770777 0.02745393 0.02723046 0.02703447
0.02686345 0.0267152 0.02658784 0.02647973 0.02638951 0.02631601
0.02625832 0.02621568 0.02618756 0.02617109]
[0.00333928 0.00342028 0.00360987 0.00390342 0.00431654 0.00487533
0.00561936 0.00660495 0.0079095 0.00963699 0.01192507 0.0149525
0.0189424 0.02414936 0.03080688 0.03900796 0.04853102 0.05871438
0.06854898 0.07700601 0.08331963 0.08699048 0.08776243 0.08580358
0.08176963 0.07656744 0.07101487 0.06565176 0.06074902 0.05639411
0.05258165 0.04926601 0.04638877 0.04389134 0.04172019 0.03982848
0.03817615 0.03672925 0.03545917 0.0343418 0.03335682 0.03248702
0.03171783 0.0310368 0.03043331 0.02989823 0.0294237 0.02900291
0.02862996 0.02829972 0.02800772 0.02775006 0.02752332 0.02732456
0.02715116 0.0270009 0.02687184 0.02676231 0.02667092 0.02659648
0.02653805 0.02649488 0.02646641 0.02644981]
[0.00422335 0.00425169 0.00432662 0.00444839 0.00463062 0.00489547
0.00527795 0.00583213 0.00663986 0.00782195 0.00955103 0.0120661
0.01568995 0.02084468 0.02803121 0.0376904 0.04985001 0.06368346
0.07745898 0.08929377 0.09793801 0.10259001 0.10272073 0.09865313
0.09180834 0.08391157 0.07620557 0.06929603 0.0633225 0.05823506
0.05392121 0.05026067 0.04714466 0.04448095 0.04219347 0.04022018
0.03851061 0.03702366 0.03572573 0.03458923 0.03359133 0.03271309
0.03193863 0.03125462 0.03064977 0.03011446 0.02964048 0.02922078
0.02884926 0.02852067 0.02823042 0.02797454 0.02774958 0.02755253
0.02738076 0.02723201 0.02710432 0.02699603 0.02690571 0.02683219
0.0267745 0.02673188 0.02670379 0.02668747]
[0.00467043 0.00469073 0.00474272 0.00482081 0.00492637 0.00506378
0.00524383 0.00548991 0.00584903 0.00641049 0.00733651 0.00890669
0.01156469 0.01595333 0.02295652 0.03367208 0.04897477 0.06827346
0.08855187 0.1058616 0.11817017 0.12431252 0.12270196 0.11429795
0.10253862 0.09067911 0.0803962 0.07187864 0.06491261 0.05920976
0.05451226 0.05061216 0.0473475 0.0445932 0.04225262 0.04025053
0.03852797 0.03703825 0.0357441 0.03461544 0.03362782 0.03276117
0.03199891 0.0313272 0.03073443 0.03021078 0.02974792 0.0293387
0.02897701 0.02865757 0.02837578 0.0281277 0.02790987 0.02771929
0.02755337 0.02740985 0.02728678 0.02718251 0.02709563 0.02702495
0.02696953 0.02692862 0.02690165 0.02688605]
[0.00461015 0.00465384 0.00475191 0.00489297 0.00507027 0.0052754
0.00549868 0.00573044 0.00596452 0.00620807 0.00650508 0.00698469
0.00796121 0.01017754 0.01513353 0.02510049 0.04287252 0.07008567
0.10200122 0.12887463 0.14763549 0.15624296 0.15009441 0.13209201
0.11174985 0.0952497 0.0825223 0.07272585 0.06508627 0.05903291
0.05416177 0.05018675 0.04690268 0.04416002 0.0418479 0.03988282
0.03820089 0.03675257 0.03549891 0.03440893 0.03345772 0.03262501
0.03189417 0.03125144 0.0306853 0.0301861 0.02974561 0.02935687
0.02901387 0.02871146 0.02844518 0.02821116 0.02800604 0.0278269
0.0276712 0.02753675 0.02742164 0.02732426 0.02724323 0.0271774
0.02712584 0.0270878 0.02706275 0.0270483 ]
[0.00400406 0.00411526 0.00435016 0.00468185 0.00509379 0.00557057
0.00609743 0.00665813 0.00723165 0.00778771 0.00828208 0.00865851
0.00889196 0.00917207 0.01011043 0.01341459 0.02677122 0.06125853
0.1162629 0.16030552 0.19158705 0.21046445 0.18647204 0.14466476
0.11540243 0.09547258 0.08144926 0.07120386 0.06347012 0.05747435
0.05272269 0.04888781 0.04574538 0.0431372 0.04094891 0.039096
0.03751485 0.03615668 0.03498356 0.03396552 0.03307862 0.0323035
0.03162432 0.031028 0.03050365 0.03004211 0.02963564 0.02927763
0.02896242 0.02868512 0.02844151 0.02822794 0.0280412 0.02787852
0.02773749 0.02761601 0.02751226 0.02742468 0.02735196 0.027293
0.02724688 0.02721291 0.02719056 0.02717772]
[0.00286901 0.00315649 0.00370335 0.00440595 0.00522548 0.00614658
0.007166 0.00828695 0.00951551 0.01085696 0.01231003 0.01385519
0.01542859 0.01686313 0.01776104 0.01793951 0.02206899 0.03889525
0.12949873 0.19243208 0.27995462 0.30889352 0.19755023 0.14044966
0.10925212 0.08965714 0.07641055 0.06692623 0.05985649 0.05441791
0.05012888 0.04667772 0.04385471 0.04151393 0.03955093 0.03788917
0.03647128 0.03525349 0.03420183 0.03328951 0.03249514 0.03180142
0.03119419 0.03066173 0.03019428 0.02978361 0.02942272 0.02910564
0.02882724 0.02858307 0.02836928 0.02818249 0.02801977 0.02787855
0.0277566 0.02765195 0.02756292 0.02748804 0.02742607 0.02737598
0.02733691 0.02730819 0.02728932 0.02727851]
[0.00181297 0.00238365 0.00331567 0.00440021 0.0055991 0.00691361
0.00836194 0.00997336 0.01178789 0.01385833 0.01625445 0.01906906
0.02242724 0.02649207 0.03148512 0.03749572 0.04470774 0.05375671
0.18208981 0.29559719 0.39820416 0.36825408 0.18676491 0.12959535
0.10079519 0.08296934 0.0710817 0.06262618 0.05634626 0.05152063
0.04771377 0.04464701 0.04213444 0.04004742 0.03829425 0.03680777
0.03553773 0.03444575 0.03350201 0.03268296 0.03196975 0.03134707
0.03080237 0.03032523 0.02990693 0.02954008 0.02921838 0.02893645
0.02868961 0.0284738 0.02828548 0.02812157 0.02797935 0.02785642
0.0277507 0.02766037 0.02758382 0.02751969 0.0274668 0.02742417
0.02739099 0.02736661 0.02735058 0.02733755]]
- channel 4: A 64×64 matrix of zeros with a single non-zero value 0.5 located at position (63, 20)
- channel 5: A 64×64 matrix representing a y-direction load distribution, with a single point load of 0.8660254 located at position (63, 19)
###Task
Based on these five input channels, compute and return the following outputs:
- C_y_hat (float): The compliance (objective value) of the optimized material layout.
- VF_y_hat (float): The volume fraction of the optimized layout you generated, calculated as the proportion of material (1's) in y_hat.
#### Constraints
- The design must minimize compliance.
- All boundary conditions and external loads must be satisfied.
- The volume fraction constraint must not be violated.
- The final outputs should be provided according to the specified field descriptions. | Yilan Jiang |
XZ_02 | 581 | Robotics | ## Task Description
You are given a 2D gridmap of a construction site, where each node is represented as a triplet (x, y, 0/1). This map follows the specifications below:
-The construction site spans an area that is 50 meters wide and 40 meters long.
-Each grid cell is 1 meter × 1 meter.
-The bottom-left corner of the site map corresponds to world coordinates (0, 0).
-The value 0 or 1 in (x, y, 0/1) represents: A value of 1 denotes an obstacle (construction material, equipment, barricade, etc.), while a 0 indicates traversable space.
The construction site contains the following obstacles:
-A vertical wall from (10,5) to (10,35)
-A horizontal wall from (10,20) to (40,20)
-A vertical wall from (30,0) to (30,15)
-A cluster of obstacles in the region from (20,25) to (25,30)
-Several random obstacles at: (15,10), (25,5), (35,25), (40,30), (45,15)
Your goal is to perform path planning for an autonomous construction robot navigating this site. You can choose any suitable algorithm to compute collision-free paths. We use an autonomous construction vehicle with a radius of 0.5 meters, which can navigate continuously on the site (not just on grid nodes). Based on the site map described above, use a path planning algorithm to compute a smooth, efficient (as short as possible), and collision-free path from the given start pose to the goal pose, while considering the vehicle's turning constraints.
Please follow these specifications:
1. Set the state space bounds to match the site limits: x from 0 to 49, y from 0 to 39, and orientation θ from 0 to 2π radians.
2. The construction vehicle has the following motion constraints:
-The minimum turning radius is 4 meters due to its wheelbase and steering mechanism.
-The vehicle moves at a constant forward speed of 1 meter per second for safety on the construction site.
3. The start pose is: (0, 0, π) (at the site entrance, facing left)
4. The goal pose is: (49, 39, π/2) (at the far corner delivery area, facing up)
## Required Results:
1. Path representation: Output the path as a list of tuples (x, y, θ) at regular intervals (e.g., every 1 meter along the path or at fixed time steps)
2. Total path length (in meters)
3. Minimum distance to obstacles (in meters)
4. Maximum curvature (to verify turning radius constraint)
5. Number of nodes/states explored
| Xiayu Zhao
|
YF_03 | 469 | Structure Design | ## Task Description
In this task, you are required to determine a suitable thickness (Th) of a rectangular steel cantilever beam subjected to uniform loads and evaluated using 3D structural simulation in MATLAB’s PDE Toolbox.
The beam is modeled as a cantilever with one end fully fixed (all degrees of freedom constrained) and the other end free. A constant downward pressure is applied only on the outer half of the top face—that is, over the region from L/2 to L(Stay away from the end)
You are given the following fixed parameters:
- 'L = 1000' mm (Total span length)
- 'w = 40' mm (Beam width, constant)
- 'Height = Th' mm (Beam thickness to be designed)
- Uniform load magnitude: 1000/(L/2*w)N/mm^2,applied only over the half‐length area(Stay away from the fixed end)
- Material properties:
- Young’s modulus: 210,000 MPa
- Poisson’s ratio: 0.3
The beam will be evaluated using a static linear elasticity model in 3D (extruded along the beam width). The performance criterion is that the maximum vertical displacement (uy) must be less than 2 mm under the given load.
The score depends on the ratio of the maximum measured displacement to the allowable threshold. If that ratio falls between seventy percent and ninety percent, the beam earns the full 100 points. If the ratio is below seventy percent, partial credit is awarded in direct proportion to how close it is to seventy-percent (with zero displacement scoring zero and seventy-percent scoring 100). If the ratio lies between ninety percent and one hundred percent, points are deducted in proportion to how far it exceeds ninety percent (dropping from 100 at ninety percent down to zero at the full threshold). Any ratio below zero or above one hundred percent results in a score of zero.
---
### Task
Your task is to:
- Propose a structurally sound value for `Th` (thickness of the beam, in mm)
- Provide a brief justification for your choice of thickness, considering stiffness, loading, and geometric constraints
You do **not** need to evaluate the displacement yourself. The simulation and evaluation will be done separately.
| Yufan Zhang |
CY_03 | 2,938 | Operating System Design | ### Task Description
Your task is to design the read function for a virtio block device driver. The relevant data structures have been provided.
Please follow the function headers provided, complete the specified helper functions, and finally put the helper functions together to complete the read function.
The relevant data structures and some helper functions you can use are:
```python
from dataclasses import dataclass, field
from typing import Optional, Union, List, Callable, Optional
# COMPILE-TIME PARAMETERS
VIOBLK_INTR_PRIO = 1
VIOBLK_NAME = "vioblk"
VIOBLK_IRQ_PRIO = 1
# INTERNAL CONSTANT DEFINITIONS
VIRTIO_BLK_F_SIZE_MAX = 1
VIRTIO_BLK_F_SEG_MAX = 2
VIRTIO_BLK_F_GEOMETRY = 4
VIRTIO_BLK_F_RO = 5
VIRTIO_BLK_F_BLK_SIZE = 6
VIRTIO_BLK_F_FLUSH = 9
VIRTIO_BLK_F_TOPOLOGY = 10
VIRTIO_BLK_F_CONFIG_WCE = 11
VIRTIO_BLK_F_MQ = 12
VIRTIO_BLK_F_DISCARD = 13
VIRTIO_BLK_F_WRITE_ZEROES = 14
VIRTIO_BLK_F_LIFETIME = 15
VIRTIO_BLK_F_SECURE_ERASE = 16
# Virtio device status bits
VIRTIO_STAT_ACKNOWLEDGE = (1 << 0)
VIRTIO_STAT_DRIVER = (1 << 1)
VIRTIO_STAT_FEATURES_OK = (1 << 3)
VIRTIO_STAT_DRIVER_OK = (1 << 2)
VIRTIO_STAT_DEVICE_NEEDS_RESET = (1 << 6)
VIRTIO_STAT_FAILED = (1 << 7)
# Virtio feature bits (number, not mask)
VIRTIO_F_INDIRECT_DESC = 28
VIRTIO_F_EVENT_IDX = 29
VIRTIO_F_ANY_LAYOUT = 27
VIRTIO_F_RING_RESET = 40
VIRTIO_F_IN_ORDER = 35
# Virtqueue constants
VIRTQ_LEN_MAX = 32768
VIRTQ_USED_F_NO_NOTIFY = 1
VIRTQ_AVAIL_F_NO_INTERRUPT = 1
VIRTQ_DESC_F_NEXT = (1 << 0)
VIRTQ_DESC_F_WRITE = (1 << 1)
VIRTQ_DESC_F_INDIRECT = (1 << 2)
# Feature vector length
VIRTIO_FEATLEN = 4
# Virtio interrupt status bits
USED_BUFFER_NOTIFICATION = (1 << 0)
CONFIGURATION_CHANGE_NOTIFICATION = (1 << 1)
# vioblk vq request type
VIRTIO_BLK_T_IN = 0
VIRTIO_BLK_T_OUT = 1
@dataclass
class Geometry:
cylinders: int # uint16_t
heads: int # uint8_t
sectors: int # uint8_t
@dataclass
class Topology:
physical_block_exp: int # uint8_t
alignment_offset: int # uint8_t
min_io_size: int # uint16_t
opt_io_size: int # uint32_t
@dataclass
class BlockConfig:
capacity: int # uint64_t
size_max: int # uint32_t
seg_max: int # uint32_t
geometry: Geometry
blk_size: int # uint32_t
topology: Topology
writeback: int # uint8_t
unused0: int # char
num_queues: int # uint16_t
max_discard_sectors: int # uint32_t
max_discard_seg: int # uint32_t
discard_sector_alignment: int # uint32_t
max_write_zeroes_sectors: int # uint32_t
max_write_zeroes_seg: int # uint32_t
write_zeroes_may_unmap: int # uint8_t
max_secure_erase_sectors: int # uint32_t
max_secure_erase_seg: int # uint32_t
secure_erase_sector_alignment: int # uint32_t
@dataclass
class VirtioMmioRegs:
magic_value: int = 0 # uint32_t
version: int = 0 # uint32_t
device_id: int = 0 # uint32_t
vendor_id: int = 0 # uint32_t
device_features: int = 0 # uint32_t
device_features_sel: int = 0 # uint32_t
driver_features: int = 0 # uint32_t
driver_features_sel: int = 0 # uint32_t
queue_sel: int = 0 # uint32_t
queue_num_max: int = 0 # uint32_t
queue_num: int = 0 # uint32_t
queue_ready: int = 0 # uint32_t
queue_notify: int = 0 # uint32_t
interrupt_status: int = 0 # uint32_t
interrupt_ack: int = 0 # uint32_t
status: int = 0 # uint32_t
queue_desc: int = 0 # uint64_t
queue_driver: int = 0 # uint64_t
queue_device: int = 0 # uint64_t
shm_sel: int = 0 # uint32_t
shm_len: int = 0 # uint64_t
shm_base: int = 0 # uint64_t
queue_reset: int = 0 # uint32_t
config: Union[BlockConfig, bytes] = field(default_factory=lambda: BlockConfig(
capacity=4,
size_max=512,
seg_max=1,
geometry=Geometry(cylinders=1, heads=1, sectors=4),
blk_size=512,
topology=Topology(physical_block_exp=0, alignment_offset=0, min_io_size=512, opt_io_size=512),
writeback=0,
unused0=0,
num_queues=1,
max_discard_sectors=0,
max_discard_seg=0,
discard_sector_alignment=0,
max_write_zeroes_sectors=0,
max_write_zeroes_seg=0,
write_zeroes_may_unmap=0,
max_secure_erase_sectors=0,
max_secure_erase_seg=0,
secure_erase_sector_alignment=0
))
# define the iointf interface
@dataclass
class IoIntf:
close: Optional[Callable[['Io'], None]]
cntl: Optional[Callable[['Io', int, object], int]]
read: Optional[Callable[['Io', int, object, int], int]]
write: Optional[Callable[['Io', int, object, int], int]]
# define the io struct
@dataclass
class Io:
intf: Optional[IoIntf]
refcnt: int
@dataclass
class VirtqDesc:
addr: int = 0 # uint64_t
len: int = 0 # uint32_t
flags: int = 0 # uint16_t
next: int = 0 # int16_t
@dataclass
class VirtqAvail:
flags: int = 0 # uint16_t
idx: int = 0 # uint16_t
ring: List[int] = field(default_factory=list)
@dataclass
class VirtqUsedElem:
id: int = 0 # uint32_t
len: int = 0 # uint32_t
@dataclass
class VirtqUsed:
flags: int = 0 # uint16_t
idx: int = 0 # uint16_t
ring: List[VirtqUsedElem] = field(default_factory=list)
def virtio_notify_avail(regs: VirtioMmioRegs, qid: int) -> None:
regs.queue_notify = qid
## Thread and Condition Variable
@dataclass
class Thread:
id: int = -1
## Your program will be running on curr_thread:
curr_thread = Thread(id = 1)
@dataclass
class ThreadList:
threads: List[Thread] = field(default_factory=list)
def add_thread(self, thread: Thread):
self.threads.append(thread)
def clear(self):
self.threads.clear()
@dataclass
class Condition:
name: Optional[str] = None
wait_list: ThreadList = field(default_factory=ThreadList)
```
Here are some functions for condition variables you can use.
You should use condition_wait but you don't need to know the details.
`condition_init(cond: Condition, name: Optional[str] = None)`
`condition_wait(cond: Condition, thread: Thread)`
`condition_broadcast(cond: Condition)`
```python
# Lock
@dataclass
class Lock:
owner: Optional[Thread] = None
lkrelease: Condition = field(default_factory=Condition)
```
Here are some functions for condition variables you can use.
You should use lock_acquire and lock_release but you don't need to know the details.
`lock_init(lock: Lock)`
`lock_acquire(lock: Lock, thread: Thread)`
`lock_release(lock: Lock)`
```python
# vioblk_req
@dataclass
class VioblkReq:
type: int
reserved: int
sector: int
# vioblk_device
@dataclass
class VioblkDevice:
regs: VirtioMmioRegs
io: Io
irqno: int = 2
instno: int = 0
@dataclass
class Vq:
last_used_idx: int = 0
avail: Union[VirtqAvail, bytes] = field(default_factory=lambda: VirtqAvail())
used: Union[VirtqUsed, bytes] = field(default_factory=lambda: VirtqUsed()) # 填充
desc: list = field(default_factory=lambda: [VirtqDesc() for _ in range(4)]) # 4 descriptors
req: VioblkReq = field(default_factory=lambda: VioblkReq(-1, -1, -1))
status: int = 0
vq: Vq = field(default_factory=Vq)
readbufcnt: int = 0
readbuf: Optional[bytes] = None
writebufcnt: int = 0
writebuf: Optional[bytes] = None
vioblk_used_updated: Condition = field(default_factory=Condition)
vioblk_lock: Lock = field(default_factory=Lock)
blksz: int = 512
is_open: int = 1
pos: int = 0
capacity: int = 2048
```
About interrupts, you only need to know these three functions:
`disable_interrupts()` Disables interrupts and returns an identifier used to restore interrupts.
`restore_interrupts(orig: int)` Restores interrupts using an identifier /orig/.
`enable_interrupts()` Enables interrupts and returns an identifier used to restore interrupts.
Here are two tasks for you:
First, please implement a vioblk_read function, which:
- Reads bufsz number of bytes (must be aligned to VirtIO block size) from the disk and writes them to buf.
- Achieves this by repeatedly setting the appropriate registers to request a block from the disk.
- Thread sleeps while waiting for the disk to service the request.
- Return the number of bytes successfully read from the disk, or -1 on failure.
- Remember to check input.
```python
def vioblk_read(vioblk:VioblkDevice, pos: int, buf: bytes, bufsz: int):
# vioblk - a VioblkDevice instance
# pos - the position to read data from, may not be multiples of block size
# buf - the buffer to pass your read data into
# bufsz - number of bytes needed to be read, may not be multiples of block size
# Your Implementation here:
return -1
```
Second, please implement a vioblk_write function, which:
- Writes bufsz number of bytes (must be aligned to VirtIO block size) into the disk from buf.
- Achieves this by repeatedly setting the appropriate registers to send requests to the device.
- Data should be written into vioblk device's writebuf only from which the driver will read data into its disk.
- But you still need to set up relevant virt queue descriptors.
- Thread sleeps while waiting for the disk to service the request.
- Return the number of bytes successfully written to the disk, or -1 on failure.
- Remember to check input.
- Hint: you should call your read function.
```python
def vioblk_write(vioblk:VioblkDevice, pos: int, buf: bytes, bufsz: int):
# vioblk - a VioblkDevice instance
# pos - the position to write data into, may not be multiples of block size
# buf - the buffer where your data is from
# bufsz - number of bytes needed to be written, may not be multiples of block size
# Your Implementation here:
return -1
```
Please give me your code in two python code_blocks:
```python
Your code here
``` | Chongying Yue |
HC_03 | 199 | Signal Processing | In this task, you will be given a set of 2D points.
## Task Description
You are given a list of (x, y) pairs that roughly follow a quadratic (second-order) polynomial relationship, but include some noise.
Your task is to estimate the best-fit second-order polynomial function of the form:
y = a * x^2 + b * x + c
where:
- a, b, c are real-valued coefficients.
You must provide the estimated coefficients (a, b, c) and minimize the mean squared error (MSE) of the fit.
## Output Format
You must provide the following:
### coefficients
a
b
c
## Data points:
x = [-2, -1, 0, 1, 2, 3]
y = [7.9, 2.0, 0.1, 2.2, 6.0, 12.1]
| Hao Chen
|
YF_04 | 427 | Structure Design | ## Task Description
In this task, you are required to determine a suitable diameter d of a solid cylindrical steel shaft, which will be subjected to an applied torque and evaluated using 3D structural simulation in MATLAB’s PDE Toolbox.
The shaft is modeled as a cantilever: one end is fully fixed (all degrees of freedom constrained), and the other end is free. A torque T is applied uniformly over the free‐end circular face about the shaft axis.
You are given the following fixed parameters:
- 'L = 1000' mm
- 'diameter' mm (to be designed)
- Applied torque: T=1×10^6 N·mm (equivalent to 1 kN·m)
- Material properties:
- Young’s modulus: 210,000 MPa
- Poisson’s ratio: 0.3
The shaft will be evaluated using a static linear‐elastic 3D model. The performance criterion is that the maximum twist angle ϕ between the free end and the fixed end (rotation about the longitudinal axis) must satisfy
0.05rad. The score depends on the ratio of the maximum measured angle to the allowable threshold. If that ratio falls between seventy percent and ninety percent, the beam earns the full 100 points. If the ratio is below seventy percent, partial credit is awarded in direct proportion to how close it is to seventy-percent (with zero displacement scoring zero and seventy-percent scoring 100). If the ratio lies between ninety percent and one hundred percent, points are deducted in proportion to how far it exceeds ninety percent (dropping from 100 at ninety percent down to zero at the full threshold). Any ratio below zero or above one hundred percent results in a score of zero.
---
### Task
Your task is to:
- Propose a structurally sound value for `D` (diameter of the shaft, in mm)
- Provide a brief justification for your choice of thickness, considering stiffness, loading, and geometric constraints
You do **not** need to evaluate the angle yourself. The simulation and evaluation will be done separately.
| Yufan Zhang |
Yuqi_01 | 2,348 | Computer Architecture Design | ## Neural Processing Unit Architecture
Neural processing units (NPUs) are specialized accelerators for machine learning (ML) workloads. A typical example is Google TPU [1,2], the state-of-the-art NPU architecture widely deployed in production.
It consists of weight-stationary systolic arrays (SAs) for matrix multiplications and convolutions, and SIMD vector units (VUs) for generic vector operations.
An SA consists of a 2D array of processing elements (PEs) that are connected in a mesh topology. Each PE can perform a multiply-accumulate (MAC) operation.
Each VU takes 8$\times$128$ vectors as inputs and can output a 8$\times$128$ vector per cycle.
Each chip has an off-chip high-bandwidth memory (HBM) to store the ML model weights and input/output data, and an on-chip SRAM to exploit on-chip data reuse and hide HBM access latency.
A DMA engine performs asynchronous memory copy between the HBM and SRAM, and the DMA operation are performed in parallel with the computation in the SAs and VUs.
Multiple NPU chips can be interconnected via high-speed inter-chip interconnect (ICI) links, which form an NPU pod. The NPU chips in a pod are arranged as a 3D torus, which is optimized for all-reduce bandwidth [3,10]. The DMA engine performs peer-to-peer RDMA operations to access another chip's HBM or SRAM.
## Distributed Large Language Model Serving
Large language models (LLMs) are auto-regressive transformer-based language models.
To serve an input request, the LLM performs two stages of computations: prefill and decode.
During prefill, the LLM computes the forward pass for the input sequence and generate the key-value (KV) cache for each input token. It also generates the first output token.
During decode, the LLM iteratively generates the next output token based on the KV cache of the input tokens and the previously generated output tokens.
In state-of-the-art LLM serving systems, the prefill and decode stages are disaggregated and performed in a pipelined manner.
Therefore, we can treat the prefill and decode stages as two separate workloads and optimize them independently.
Since the LLM is too large to fit into a single NPU chip, we need to shard the model weights, KV cache, and activation tensors across multiple chips.
Typically, there are three tunable sharding parameters: data parallelism (DP), tensor parallelism (TP), and pipeline parallelism (PP).
In DP, the input batch is sharded across chips such that each chip independently computes the forward pass for its own local batch.
In TP, the model weights are sharded across chips follwing the Megatron-LM approach [6]. For the attention layers, each attention head is assigned to a different chip. For the FFN layers, the FNN matrices are sharded across chips, and it requires all-reduce (or reduce-scatter plus all-gather) communication to aggregate the final output of the FNN layers.
In PP, different transformer layers in the LLM are assigned to different chips, forming a pipeline. There will be peer-to-peer (P2P) inter-chip communications to receive and send the input/output tensors of each pipeline stage.
## SLO Metrics for LLM Serving
For prefill, the latency SLO metric is the time-to-first-token (TTFT) for each request, which is the time taken to process all input tokens of the request.
For decode, the latency SLO metric is the time-per-output-token (TPOT) for each request, which is the time taken to generate each output token.
For both prefill and decode, the throughput metric is tokens per second, which is the number of tokens processed per second.
## Task Description
In this task, you will act as a computer architect to tune the hardware specifications of a neural processing unit (NPU). You are given a large language model (LLM) inference workload with the average input and output sequence lengths for each request. You first need to determine some critical architectural parameters for each NPU chip.
Then, you will consider deploying the given LLM workload at scale. You need to act as the cluster NPU allocator [4,5] to figure out how to allocate NPU resourcess to the given workload.
Specifically, you need to tune the NPU cluster configuration for serving the given LLM workload, including the number of chips, network topology, the model shardings, and the batch size, to meet latency and throughput service-level objective (SLO) constraints.
For the following tasks, assume each task is independent, and you do not need to consider the previous tasks when answering the next task.
### Task 1: Systolic Array (SA) Width
We want to first decide the width of the SA based on the tensor operator semantics in the LLM model. Assume the SA is square.
Consider a matrix multiplication operator $C = A \times B$, where the input matrix $A$ is of size $m \times k$, the input matrix $B$ is of size $k \times n$, and the output matrix $C$ is of size $m \times n$.
For a weight-stationary SA, if $m$ is less than its width, the SA will be diagonally underutilized; if $n$ is less than its width, some columns in the SA will be underutilized; if $k$ is less than its width, some rows in the SA will be underutilized.
The SA is fully utilized when $m$, $k$, and $n$ are all greater than or equal to its width.
Consider a specific matrix multiplication operator where $m=1024$, $k=128$, and $n=128$.
If we want to make sure the FLOPs (floating-point operations) per second utilization of the SA is at least 70%, what is the maximum width of the SA?
Your answer should be a a positive integer, which is the width of the SA.
### Task 2: HBM Bandwidth
Now we tune the memory subsystem.
Specifically, we need to determine how much HBM bandwidth is required to avoid stalling the computation.
Suppose we have four SAs, each with width 128 and running at 940 MHz.
For simplicity, assume the SRAM bandwidth is infinite, and the VUs will not be a performance bottleneck.
Consider a matrix multiplication operator $C = A \times B$, where the input matrix $A$ is of size $m \times k$, the input matrix $B$ is of size $k \times n$, and the output matrix $C$ is of size $m \times n$.
We perform tiled matrix multiplication [7] to exploit on-chip data reuse and reduce the HBM bandwidth pressure.
Each SA computes separate output tiles.
You may refer to the JAX documentation [9] for the tiling strategy for multiple SAs on an NPU.
The tile size is restricted by the SRAM size, and we need to keep at least 10 tiles in the SRAM for each SA, in order to hide the HBM access latency.
Assume the on-chip SRAM is 32 MB, and all elements in the matrices are float16 (2 bytes).
For a matrix multiplication operator where $m=4096$, $k=8192$, and $n=28672$, what is the minimum required HBM bandwidth in GB/s (including both read and write traffic) such that the SA computation will not be stalled?
### Task 3: NPU Allocations for Prefill and Decode
Consider an NPU chip with the following specifications:
{
"num_sa": 8,
"num_vu": 6,
"hbm_bw_GBps": 2765,
"vmem_size_MB": 128,
"freq_GHz": 1.75,
"sa_dim": 128,
"hbm_size_GB": 95,
"ici_link_bw_GBps": 100,
}
where "num_sa" is the number of SAs, "num_vu" is the number of VUs, "hbm_bw_GBps" is the HBM bandwidth in GB/s, "vmem_size_MB" is the size of the on-chip SRAM in MB, "freq_GHz" is the frequency of the chip in GHz, "sa_dim" is the width of the SA, "hbm_size_GB" is the size of the HBM in GB, and "ici_link_bw_GBps" is the bandwidth of each ICI link in GB/s.
Each NPU chip has 6 ICI links that are directly connected to 6 neighboring chips, and all NPU chips in an NPU pod are connected in a 3D torus topology.
You are given the Llama3.1-405B LLM model, and you need to find the optimal NPU pod configuration and the optimal model sharding and batch size for serving the LLM model. The detailed model specifications are as follows:
{
"d_model": 16384,
"num_heads": 128,
"d_head": 128,
"num_kv_heads": 8,
"d_ff": 53248,
"num_layers": 126,
"use_flash_attention": true,
}
where "d_model" is the embedding dimension, "num_heads" is the number of attention heads, "d_head" is the dimension of each attention head, "num_kv_heads" is the number of key-value heads (for grouped-query attention), "d_ff" is the hidden dimension of the feed-forward network (FFN), "num_layers" is the number of transformer layers, and "use_flash_attention" indicates whether to use flash attention [8] (only used for prefill) or not.
The average input sequence length is 4096 tokens for prefill, and the average output sequence length is 512 tokens for decode.
The latency SLO is 500 ms TTFT for prefill and 20 ms TPOT for decode.
Assume we have a 4$\times$4$\times$4 NPU pod for prefill, and another 4$\times$4$\times$4 NPU pod for decode. Please find the optimal allocations for each of them to achieve the best throughput (tokens per second), while ensuring that the latency SLO is met.
You should output two allocations plans, one for prefill and one for decode.
Each allocation plan should include the following parameters:
- DP: data parallelism degree. Must be a multiple of 2.
- TP: tensor parallelism degree. Must be a multiple of 2.
- PP: pipeline parallelism degree. Must be a multiple of 2.
- batch_size: the number of requests in a batch. Must be a power of 2.
- mem_per_chip_GB: the HBM memory footprint on each NPU chip in GB.
You need to ensure that the product of DP, TP, and PP does not exceed 64 chips (but each parallelism degree can exceed 4 by taking multiple ICI axes). You also need to ensure that the allocation plan meets the 95GB per-chip HBM memory capacity constraint. | Yuqi Xue |
DL_01 | 3,181 | Computer Architecture Design | # Solid-State Drive Design Task - Single Configuration Parameter
In this problem, you will finalize a set of Solid-State Drive (SSD) designs that meet the performance requirements for a specific workload type. Initially, you must determine which parameters to tune—and to what extent—to satisfy the given performance criteria.
## Background
The internal architecture of a typical SSD is presented in the above Figure. An SSD consists of five major components: a set of flash memory packages, an SSD controller having embedded processors like ARM, off-chip DRAM (SSD DRAM), flash controllers, and the I/O interface that includes SATA and NVMe protocols. The flash packages are organized in a hierarchical manner. Each SSD has multiple channels, and each channel can process read/write commands independently. Each channel is shared by multiple flash packages. Each package has multiple flash chips. Within each chip, there are multiple planes. Each plane includes multiple flash blocks, and each block has multiple flash pages. The page size varies in different SSDs. When a free flash page is written once, that page is no longer available for future writes until that page is erased. However, erase operation is expensive and performed at block granularity. As each flash block has limited endurance, it is important for blocks to age uniformly (i.e., wear leveling). Modern SSD controllers employ out-of-place write, GC, and wear leveling to overcome these shortcomings and maintain indirections for the address translation in their flash translation layer (FTL).
In this problem, our aim is to design SSDs that allow developers to customize SSD hardware according to the application needs.
## Task Description
SSD customers typically evaluate SSD performance using key metrics including I/O throughput, average latency and tail latency. In this section, you should optimize the given SSD configuration by tuning the top-5 most significant parameter to reach the given performance requirement. You should first select the top-5 critical parameters, and answer what is the final value of each parameter if you tune it ALONE to reach the performance requirements. If the requirement cannot be reached, please answer "impossible" instead of the final parameter value. Please always provide your reasoning.
### Formal Problem Definition
Given a parameter set $S$ and a workload set $W$, select 5 top parameter $s \in S$ that affects the I/O throughput, average latency or both of them for each workload $w \in W$. Specifically, address the following question for this 5 parameters:
If we want to get 20\% performance improvement on I/O throughput or on average latency comparing to the baseline configuration (see next section), how should we tune this single parameter? If this is impossible, please answer "impossible" instead of providing the number and explain why. Note that the correlation between performance and parameter values are usurally not linear.
### Configuration Set
Please provide answer for each parameter listed in the table below. The third column of this table listed the baseline configuration (Samsung 983 DCT 1.92TB SSD). We provide typical values for each parameter, you can also choose value outside the listed parameters (we assume that these design can be achieved with advanced manufacture techniques, to create next-generation SSDs), but the parameter should follow the general trend in the listed parameters (e.g., number of channels should be descrete numbers).
| Parameter Name | Description | Baseline |
|:--------------------------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|:-----------|
| PCIe_Lane_Bandwidth | The PCIe bandwidth per lane in GB/s. Typical values: 0.5, 1.0, 2.0, 4.0, 8.0. | 8.0 |
| PCIe_Lane_Count | The number of PCIe lanes. Typical values: 1, 2, 4, 8, 16. | 4 |
| HostInterface_Type | The type of host interface. Typical values: NVME, SATA. | NVME |
| IO_Queue_Depth | the length of the host-side I/O queue. Typical values: 4, 8, 16, 32, 64, 128, 256. | 16 |
| Queue_Fetch_Size | The maximum number of requests that can be served in parallel in a queue. Typical values: 4, 8, 16, 32, 64, 128, 256. | 16 |
| Data_Cache_Capacity | The size of the DRAM Data Cache in bytes. Typical values:100663296, 167772160, 234881024, 301989888, 369098752, 436207616. | 536870912 |
| Data_Cache_DRAM_Row_Size | The size of the DRAM rows in bytes. values:1024, 2048, 4096, 8192, 16384. | 4096 |
| Data_Cache_DRAM_Data_Rate | The DRAM data transfer rate in MT/s. Typical values:100, 200, 400, 800, 1600, 2133, 2400, 2666, 3200. | 800 |
| Data_Cache_DRAM_Data_Burst_Size | The number of bytes that are transferred in one DRAM burst (depends on the number of DRAM chips). Typical values: 1, 2, 4, 8, 16. | 8 |
| Data_Cache_DRAM_tRCD | The value of the timing parameter tRCD in nanoseconds used to access DRAM in the data cache. Typical values:4, 7, 14, 21, 28 | 9 |
| Data_Cache_DRAM_tCL | The value of the timing parameter tCL in nanoseconds used to access DRAM in the data cache. Typical values:4, 7, 14, 21, 28 | 9 |
| Data_Cache_DRAM_tRP | The value of the timing parameter tRP in nanoseconds used to access DRAM in the data cache. Typical values:4, 7, 14, 21, 28 | 9 |
| Address_Mapping | The logical-to-physical address mapping policy implemented in the Flash Translation Layer (FTL).Typical values: PAGE_LEVEL, HYBRID | PAGE_LEVEL |
| CMT_Capacity | The size of the SRAM/DRAM space in bytes used to cache the address mapping table (Cached Mapping Table). Typical values: 67108864, 134217728, 201326592, 268435456, 335544320, 402653184, 469762048, 536870912 | 268435456 |
| Plane_Allocation_Scheme | The scheme for plane allocation priorities (C-Channel, W-Way, D-Die, P-Plane). Typical values: CWDP, CWPD, CDWP, CDPW, CPWD, CPDW, WCDP, WCPD, WDCP, WDPC, WPCD, WPDC, DCWP, DCPW, DWCP, DWPC, DPCW, DPWC, PCWD, PCDW, PWCD, PWDC, PDCW, PDWC | CWDP |
| Overprovisioning_Ratio | The ratio of reserved storage space with respect to the available flash storage capacity. Typical values:0.1, 0.15, 0.2, 0.25, 0.3 | 0.126 |
| GC_Exect_Threshold | The threshold for starting Garbage Collection (GC). Typical values: 0.1, 0.15, 0.2, 0.25, 0.3 | 0.05 |
| GC_Block_Selection_Policy | The GC block selection policy. Typical values: GREEDY, RGA, RANDOM, RANDOM P, RANDOM PP, FIFO | GREEDY |
| Use_Copyback_for_GC | Whether GC Copyback is enabled. Typical values: true, false | false |
| Preemptible_GC_Enabled | The toggle to enable pre-emptible GC. Typical values:true, false | true |
| GC_Hard_Threshold | The threshold to stop pre-emptible GC execution. Typical values:0.1, 0.15, 0.2, 0.25, 0.3 | 1 |
| Dynamic_Wearleveling_Enabled | The toggle to enable dynamic wear-leveling. Typical values: true, false | true |
| Static_Wearleveling_Enabled | The toggle to enable static wear-leveling. Typical values: true, false | true |
| Static_Wearleveling_Threshold | The threshold for starting static wear-leveling. Typical values: 50, 60, 70, 80, 90, 100 | 100 |
| Preferred_suspend_erase_time_for_read | The reasonable time to suspend an ongoing flash erase operation in favor of a recently-queued read operation. Typical values:100000, 200000, 300000, 400000, 500000 | 100000 |
| Preferred_suspend_erase_time_for_write | The reasonable time to suspend an ongoing flash erase operation in favor of a recently-queued read operation. Typical values:100000, 200000, 300000, 400000, 500000 | 100000 |
| Preferred_suspend_write_time_for_read | The reasonable time to suspend an ongoing flash erase operation in favor of a recently-queued program operation. Typical values:100000, 200000, 300000, 400000, 500000 | 100000 |
| Flash_Channel_Count | The number of flash channels in the SSD back end. Typical values:4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32 | 8 |
| Flash_Channel_Width | The width of each flash channel in byte. Typical values:1, 2, 4, 8 | 8 |
| Channel_Transfer_Rate | The transfer rate of flash channels in the SSD back end in MT/s. Typical values:100, 200, 333, 800 | 800 |
| Chip_No_Per_Channel | The number of flash chips attached to each channel in the SSD back end. Typical values:1, 2, 3, 4, 5, 6, 7, 8 | 4 |
| Flash_Technology | Typical values:TLC, MLC, SLC | MLC |
| CMD_Suspension_Support | The type of suspend command support by flash chips. Typical values:NONE, PROGRAM, PROGRAM ERASE, ERASE | None |
| Page_Read_Latency_LSB | The latency of reading LSB bits of flash memory cells in nanoseconds. Typical values:25000, 50000, 59975, 75000, 100000 | 5000 |
| Page_Read_Latency_CSB | Similar as above. Typical values:0, 25000, 50000, 75000, 100000 | 0 |
| Page_Read_Latency_MSB | Similar as above. Typical values:25000, 50000, 75000, 100000, 104956 | 10000 |
| Page_Program_Latency_LSB | Similar as above. Typical values:82062, 250000, 500000, 750000, 1000000 | 30000 |
| Page_Program_Latency_CSB | Similar as above. Typical values:0, 250000, 500000, 750000, 1000000 | 0 |
| Page_Program_Latency_MSB | Similar as above. Typical values:250000, 500000, 750000, 1000000, 1250000, 1500000, 1750000, 2000000, 2250000 | 800000 |
| Block_Erase_Latency | The latency of erasing a flash block in nanoseconds.Typical values:3000000, 3800000 | 1000000 |
| Block_PE_Cycles_Limit | The PE limit of each flash block. Typical values:10000, 20000, 30000, 40000, 50000 | 10000 |
| Suspend_Erase_Time | The time taken to suspend an ongoing erase operation in nanoseconds.Typical values:700000, 800000, 900000, 1000000, 1100000 | 700000 |
| Suspend_Program_Time | The time taken to suspend an ongoing program operation in nanoseconds. Typical values:60000, 70000, 80000, 90000, 100000 | 100000 |
| Die_No_Per_Chip | The number of dies in each flash chip. Typical values:1, 2, ..., 16 | 8 |
| Plane_No_Per_Die | The number of planes in each die. Typical values:1, 2, ..., 16 | 2 |
| Block_No_Per_Plane | The number of flash blocks in each plane. Typical values:128, 256, ..., 1024 | 1364 |
| Page_No_Per_Block | The number of physical pages in each flash block. Typical values:128, 256, ..., 1024 | 768 |
| Page_Capacity | The size of each physical flash page in bytes. Typical values:4096 | 4096 |
| Page_Metadat_Capacity | The size of the metadata area of each physical flash page in bytes. Typical values:224, 448, 672, 896, 1120 | 448 |
### Target Workload Set
Please provide answer for each workload mentioned below:
#### Real-world Workloads
These workloads represents typical storage-intensive application patterns.
| **Workload Category** | **Description** |
|-----------------------|-----------------|
| Big Data Analytics | MapReduce workloads running in data centers. |
| Cloud Storage | Cloud storage workloads running in data centers. |
| Key-Value Store | YCSB benchmarks are executed against RocksDB. |
| Maps | Maps workloads running on enterprise servers. |
| Database | TPCC/TPCH executed against Windows SQL Server. |
| WebSearch | WebSearch services trace from UMassTraceRepository. |
| Advertisement | Advertisement workloads running on servers. |
## Response Instruction
Your response should be structured in the following format:
For each workload, create a workload_result class for the tuning result. In each workload_result,
Please strictly follow the format, do not include any other text or comments.
| Daixuan Li |
YZ_02 | 1,250 | Signal Processing | ## Task Description
In this task, you are required to design four Savitzky–Golay (SG) filters using different weighting strategies. SG filters are digital FIR lowpass filters that operate by performing a moving least-squares polynomial fit on the input data samples within a specified window. They are widely used to smooth or differentiate signal data while reducing noise and preserving the underlying shape of the signal. The key to implementing an SG filter is to approximate its cutoff frequency using predefined characteristic parameters and to capture the relationship between the filter’s characteristics and its frequency response.
### Task 1
Your first task is to derive an analytical expression that relates the cutoff frequency $F_{-3dB}$ to the SG filter characteristic parameters $(m,n_h)$ and a sample rate $F_s$. The analytical expression (1) is given by $F_{-3dB} = \frac{F_s}{b_0(n_h+0.5)/(m+b_1)-(b_2+b_3*m)/(n_h+0.5)}$. This expression is obtained via least-squares fitting. You need to determine the unknown coefficients $(b_0,b_1,b_2,b_3)$ in this formula under the following predefined parameters for an SG filter with no weighting:
- filter polynomial order $m = 6$
- half-width interval $n_h = 50$
Then the following requirement must be satisfied:
- the estimated cutoff frequency $F_{-3dB}$: $abs(F_{-3dB}/F_s - 0.023) <= 0.003$
It is crucial to verify that the $F_{-3dB}$ value calculated using your derived analytical expression meets this requirement, as it is essential for the subsequent tasks.
### Task 2
Your second task is to design SG filters with four weighting strategies. The first step in this task is to obtain a wider half-magnitude interval $n_{hW}$, which is defined by the analytical expression (2): $n_{hW} = round(\frac{c_0 + c_1 * m + c_2 * m^2}{F_{-3dB}/F_s} - 1)$, where the cutoff frequency is obtained from Task 1. The MATLAB code examples below outline the construction of weighted SG filters with three different weighting strategies. They also provide the implementation for the unweighted SG filter and the metrics for evaluating filter performance.
#### MATLAB code for designing a SG filter with squared Hann weighting:
<code_block>
flW = 2*nhW+1;
weightsSqHann = hann(flW+2).^2;
weightsSqHann([1 end]) = [];
[~,gSGwSqHann] = sgolay(m,flW,weightsSqHann);
gSGwSqHann = gSGwSqHann(:,1);
HSGwSqHann = freqz(gSGwSqHann,1,NDFT,Fs);
</code_block>
#### MATLAB code for designing a SG filter with optimal weighting:
<code_block>
Tn = toeplitz([2 -1 zeros(1,flW-2)]);
v = ones(flW,1);
weightsOptimal = Tn\v;
[~,gSGwOptimal] = sgolay(m,flW,weightsOptimal);
gSGwOptimal = gSGwOptimal(:,1);
HSGwOptimal = freqz(gSGwOptimal,1,NDFT,Fs);
</code_block>
#### MATLAB code for designing a SG filter with triangular weighting:
<code_block>
weightsTriang = triang(flW);
[~,gSGwTriang] = sgolay(m,flW,weightsTriang);
gSGwTriang = gSGwTriang(:,1);
HSGwTriang = freqz(gSGwTriang,1,NDFT,Fs);
</code_block>
#### MATLAB code for designing a SG filter with no weighting:
<code_block>
[~,gSGwNone] = sgolay(m,flW);
gSGwNone = gSGwNone(:,1);
HSGwNone = freqz(gSGwNone,1,NDFT,Fs);
</code_block>
#### MATLAB code for measuring the performance of SG filter with four weighting strategies, metrics are output vs. input noise ratios, r, and smoothness parameter values, s:
<code_block>
rSGwNone = gSGwNone'*gSGwNone;
sSGwNone = diff([0;gSGwNone;0]);
sSGwNone = sum(abs(sSGwNone).^2)/2;
rSGwSqHann = gSGwSqHann'*gSGwSqHann;
sSGwSqHann = diff([0;gSGwSqHann;0]);
sSGwSqHann = sum(abs(sSGwSqHann).^2)/2;
rSGwTriang = gSGwTriang'*gSGwTriang;
sSGwTriang = diff([0;gSGwTriang;0]);
sSGwTriang = sum(abs(sSGwTriang).^2)/2;
rSGwOptimal = gSGwOptimal'*gSGwOptimal;
sSGwOptimal = diff([0;gSGwOptimal;0]);
sSGwOptimal = sum(abs(sSGwOptimal).^2)/2;
</code_block>
Similar to Task 1, your objective in Task 2 is to derive the unknown coefficients (c_0, c_1, c_2) for the expression (2) such that the following requirements are satisfied:
- half-magnitude interval $n_{hW}$: > n_h
- sSGwOptimal < sSGwTriang < sSGwSqHann < sSGwNone < -70 (dB)
- rSGwNone < rSGwOptimal < rSGwTriang < rSGwSqHann < -26 (dB)
| Yizhou Zhao |
RK_01 | 193 | Structure Design | ## Task Description
This is an asymmetric design load problem.
Design domain is a 2D rectangular region in cartesian coordinates, with vertices at (0,0), (6,0), (6,1), (0,1).
A vertically downward point load is applied at (2,1). Pin support is at (0,0) and roller support is at (6,0).
Lx = 6 and Ly = 1.
The filter radius is R = 0.03*max(Lx,Ly).
The filter exponent is 3.
---
### Task
Your task is to:
- Obtain a topology optimized design that has minimum structural compliance and volume fraction not exceeding 0.25.
- Given the optimized design, output the corresponding minimum structural compliance, named C_y_hat, and also its volume fraction, named vf, in numerical numbers. Note that vf is in the range of [0,1].
| Rahul Kundu, Yilan Jiang |
XY_03 | 1,066 | Digital Hardware Design | # FPGA Hexadecimal Display Driver Design Challenge
## Introduction
You are designing a 4-digit hexadecimal display driver for an FPGA. The display shows values from 0–F using time-division multiplexing. Each digit must refresh at least 60Hz to avoid flickering. The FPGA clock frequency is 50 MHz.
## Your Tasks
1. Compute the total refresh frequency required.
2. Compute the division ratio needed from 50 MHz to achieve that.
3. Determine the **minimum** number of counter bits `n` such that `2^n >= division_ratio`.
4. Select two appropriate counter bits to use for digit selection (ensure they cycle through 4 values).
5. Justify your digit bit selection.
6. Calculate the maximum possible delay between refreshes of the same digit under worst-case conditions. You should consider the clock tolerance of ±100 ppm (parts per million, or 0.0001), the potential delay of up to 5 clock cycles in the display driver logicand the current refresh period based on calculations from tasks 1-2
7. Determine if this maximum delay could cause perceptible flicker. Use 30Hz as the flicker threshold (i.e., if delay exceeds 33.33ms, flicker is possible).
## Output Instructions
You must return only a structured Python response like this:
config=ConfigFile(
counter_bits=,
division_ratio=,
digit_select_bits=,
bit_select_reasoning="",
max_delay_ms=,
is_flicker_possible=,
)
## the following is an example of hex_driver written in system verily for referencing:
module hex_driver (
input logic clk,
input logic reset,
input logic [3:0] in[4],
output logic [7:0] hex_seg,
output logic [3:0] hex_grid
);
module nibble_to_hex(
input logic [3:0] nibble,
output logic [7:0] hex
);
always_comb begin
case(nibble)
4'b0000 : hex = 8'b00111111; // '0'
4'b0001 : hex = 8'b00000110; // '1'
4'b0010 : hex = 8'b01011011; // '2'
4'b0011 : hex = 8'b01001111; // '3'
4'b0100 : hex = 8'b01100110; // '4'
4'b0101 : hex = 8'b01101101; // '5'
4'b0110 : hex = 8'b01111101; // '6'
4'b0111 : hex = 8'b00000111; // '7'
4'b1000 : hex = 8'b01111111; // '8'
4'b1001 : hex = 8'b01101111; // '9'
4'b1010 : hex = 8'b01110111; // 'A'
4'b1011 : hex = 8'b01111100; // 'b'
4'b1100 : hex = 8'b00111001; // 'C'
4'b1101 : hex = 8'b01011110; // 'd'
4'b1110 : hex = 8'b01111001; // 'E'
4'b1111 : hex = 8'b01110001; // 'F'
endcase
end
endmodule
logic [7:0] hex [4];
genvar i;
generate
for(i = 0; i < 4; i++) begin
nibble_to_hex nibble_to_hex_(
.nibble(in[i]),
.hex(hex[i])
);
end
endgenerate
logic [16:0] counter;
always_ff @( posedge clk ) begin
if (reset) begin
counter <= '0;
end else begin
counter <= counter + 1;
end
end
always_comb begin
if (reset) begin
hex_grid = '1;
hex_seg = '1;
end else begin
case (counter [16:15])
2'b00: begin
hex_seg = ~hex[0];
hex_grid = 4'b1110;
end
2'b01: begin
hex_seg = ~hex[1];
hex_grid = 4'b1101;
end
2'b10: begin
hex_seg = ~hex[2];
hex_grid = 4'b1011;
end
2'b11: begin
hex_seg = ~hex[3];
hex_grid = 4'b0111;
end
endcase
end
end
endmodule | XiangYi Kong |
libin2_03 | 330 | Operating System Design | ## Task Description
In this task, you need to design a proper cluster size in a file system. You and required to handle a great amount of files, and should use the space as effectively as possible.
The following informatiion is given:
- Partition size: 1 TB
- Total number of files: 1 000 000
### 1. Continuous function for the proportion of small files
P_small(T) = 0.8 × (1 − exp(− T / 4.1))
where
- T is the “small‑file threshold”, in KB (see the candidate values below)
- P_small(T) ∈ [0, 0.8] represents the fraction of files whose size ≤ T KB
- The remaining 1 − P_small(T) is treated as “large files” (> T KB)
### 2. Average file sizes
avg_small_kb(T) = 2 + 0.05 × T // in KB
avg_large_kb(T) = 512 + 0.50 × T // in KB
## Design requirements:
1. Fragmentation overhead ≤ 0.5 %
- Average wasted space for small files: W_small = cluster_size B − 2 KB
- Average wasted space for large files: W_large = cluster_size B / 2
2. Metadata (cluster mapping table) overhead ≤ 0.05 %
- Each cluster requires 4 B of mapping information
| Libin Wang |
XY_04 | 526 | Digital Hardware Design | ## Task Description
You are tasked to design a flexible and efficient color mapping system for a Tetris game implemented on an FPGA development board with VGA output. The objective is to ensure distinct visual representation of all gameplay elements while operating under hardware resource constraints.
A VGA display of 640x480 pixels and RGB444 color depth is available. Only a maximum of 10 distinct color mappings can be active at any time due to memory limitations. Additionally, your design should handle dynamic gameplay states, including a Night Mode that adjusts the color palette for low-light visibility.
### Task 1: Define Color Mapping and Screen Regions
Define color schemes for different game elements such as the Tetris playfield, active tetrominoes, next piece preview, background, UI panels, and game over screen.
Each tetromino (I, J, L, O, S, T, Z) must have distinguishable default colors.
Designate display regions for playfield, next piece preview, and score display by specifying pixel coordinate boundaries.
Respect the 10-color definition constraint.
### Task 2: Design Dynamic Mode Handling
Create a Night Mode theme that switches colors to darker palettes suitable for low-light gameplay.
Ensure smooth and logical color remapping when transitioning between normal and Night Mode.
### Task 3: Optimize Hardware Resource Usage
Implement bit slicing strategies for efficient pixel-to-grid mapping.
Avoid expensive multiplication or division in hardware logic.
### Task 4: Validate and Discuss Your Design
Propose a simple method to validate that color mappings are correctly applied under different game states.
Discuss trade-offs made between visual richness, resource constraints, and adaptability.
Suggest one innovative feature or future improvement to the color mapping system.
## Output Format
Your response must include:
1. task_report:
Introduction
Task Analysis
Methodology
Results
Discussion and Trade-offs
Innovation and Future Improvements
2. config:
color_mapping: Colors for different elements
display_regions: Regions for game components
tetromino_colors: Specific color schemes for each tetromino
ui_elements: Colors for UI states
bit_slicing: Expressions mapping pixels to grid positions
dynamic_modes: Color adjustments for Night Mode
resource_constraints: Statement about the 10-color limit
## Technical Specifications
1.Clock frequency: 50 MHz
2.VGA resolution: 640x480 pixels
3.Color depth: RGB444
4.Tetris playfield grid: 10 blocks wide by 20 blocks tall
5.Game states: start menu, in-progress gameplay, game over, Night Mode (dynamic)
Follow the structured output format precisely to ensure full evaluation credit.
| XiangYi Kong |
AB_03 | 737 | Signal Processing | ## Task Description
You are an expert Python programmer specializing in Computer Vision using the OpenCV library. Your task is to process the image located at 'images/test_shape.png' to find the largest contour and then compute its approximate polygon and convex hull representations.
**Constraint: You MUST use the OpenCV functions `cv2.findContours`, `cv2.contourArea`, `cv2.arcLength`, `cv2.approxPolyDP`, and `cv2.convexHull` as appropriate to solve this task.**
## Implementation Steps
The implementation should follow this specific logic:
1. **Load Image:** Load the image directly from the hardcoded path 'images/test_shape.png'. Handle potential loading errors.
2. **Preprocess:** Convert the loaded image to grayscale. Apply binary thresholding (e.g., `cv2.threshold` with `cv2.THRESH_BINARY`) to create a binary image where the object is white and the background is black.
3. **Find Contours:** Find all external contours in the binary image using `cv2.findContours`. Use the retrieval mode `cv2.RETR_EXTERNAL` and the approximation method `cv2.CHAIN_APPROX_SIMPLE`. Handle the case where no contours are found.
4. **Identify Largest Contour:** Iterate through the found contours and identify the one with the largest area using `cv2.contourArea`. If no contours were found, proceed to return `(None, None)`.
5. **Calculate Approximate Polygon:** For the largest contour found (`cnt`):
* Calculate its perimeter (arc length) using `cv2.arcLength(cnt, True)`.
* Calculate the epsilon value for approximation using the formula: `epsilon = 0.01 * arc_length`.
* Compute the approximate polygon vertices using `cv2.approxPolyDP(cnt, epsilon, True)`.
6. **Calculate Convex Hull:** For the *same* largest contour (`cnt`), compute the convex hull vertices using `cv2.convexHull(cnt)`.
7. **Return Results:** Return the computed vertices as a tuple: `(approx_vertices, hull_vertices)`.
## Input Specification
The solution code's main function must internally use the hardcoded path 'images/test_shape.png' for image loading. It should **not** accept any arguments.
## Output Specification
Your response must be structured according to the `CodeSolutionOutput` Pydantic model, containing the following fields:
1. **`reasoning`**: Provide a clear, step-by-step explanation of how the code follows the Implementation Steps above to find the largest contour and compute its simplified representations.
2. **`solution_code`**: Provide the complete Python code.
* The code must include necessary imports (e.g., `numpy`, `cv2`).
* The core logic must be encapsulated within a function named `get_simplified_contours` that takes **no arguments**.
* This function must load the image using the hardcoded path 'images/test_shape.png'.
* This function must **return** a tuple containing two elements: `(approx_vertices, hull_vertices)`.
* `approx_vertices`: The NumPy array of vertices returned by `cv2.approxPolyDP`.
* `hull_vertices`: The NumPy array of vertices returned by `cv2.convexHull`.
* If the image cannot be loaded or no contours are found, the function should return `(None, None)`.
* The code should **not** include any code for displaying images (`cv2.imshow`) or saving files (`cv2.imwrite`). | Ayush Barik |
RS_01 | 324 | Mechanical Systems | Given two files: TrackFile.txt and SetupFile.json.
TrackFile.txt has a row segment containing length and curvature (1/radius of curvature; zero for straights):
0 0.000024
10 -1.16667E-05
20 2.13333E-05
30 0.000066
40 -6.76667E-05
50 -9.03333E-05
60 0.000075
70 0.000233667
80 0.000324667
90 0.000143
100 8.43333E-05
110 0.000111667
120 0.000057
130 -0.000149
140 -0.000243333
150 -0.000328
160 -0.000163
170 0.000211333
180 0.000574
190 0.00069
200 0.000623
210 0.000397
220 0.000301333
230 0.000765333
240 0.002166
250 0.00457
260 0.01237
270 0.03242
280 0.040309333
290 0.018050333
300 0.010655
310 0.005606
320 0.003332667
330 0.000466
340 0.000744667
350 0.000555333
360 0.000675
370 0.000519667
380 0.000605
390 0.000773
400 0.000960667
410 0.001043
420 0.00081
430 0.001081
440 0.001226667
450 0.001234
460 0.001321
470 0.001166333
480 0.001054
490 0.000896
500 0.001024667
510 0.001272
520 0.001207
530 0.001307333
540 0.001434
550 0.001476667
560 0.001555
570 0.001498
580 0.001545333
590 0.001889667
600 0.00191
610 0.001684
620 0.001412
630 0.001269
640 0.001077333
650 0.000808
660 0.000444
670 0.000007
680 -0.000346667
690 -0.000424
700 -0.000367
710 -0.00031
720 -0.000192
730 -2.56667E-05
740 7.83333E-05
750 0.000173
760 0.000192667
770 0.000074
780 -0.000005
790 -0.000118333
800 -0.000335
810 -0.000559
820 -0.000643667
830 -0.000698667
840 -0.001024
850 -0.001753667
860 -0.002447333
870 -0.002669
880 -0.002064
890 -0.002478
900 -0.002609
910 -0.002733333
920 -0.002021667
930 -0.001064
940 0.000234
950 0.001743333
960 0.003549
970 0.00475
980 0.006055333
990 0.004918
1000 0.004290667
1010 0.003958
1020 0.003061
1030 0.001792
1040 0.001072
1050 -0.000314
1060 -0.002452
1070 -0.002665667
1080 -0.002002
1090 -0.001633333
1100 -0.001453667
1110 -0.001527
1120 -0.001441333
1130 -0.001281667
1140 -0.000958
1150 -0.000786333
1160 -0.00063
1170 -0.000408
1180 -0.000346333
1190 -0.000261333
1200 -0.000154
1210 -0.000126
1220 -0.000091
1230 -0.000029
1240 0.000158
1250 0.000302667
1260 0.000422
1270 0.000544
1280 0.000679667
1290 0.000873
1300 0.001100333
1310 0.001444667
1320 0.00183
1330 0.001885667
1340 0.001816333
1350 0.001788
1360 0.001714333
1370 0.001587667
1380 0.001565
1390 0.001533333
1400 0.001515333
1410 0.001463
1420 0.001379667
1430 0.001165333
1440 0.000857
1450 0.000675333
1460 0.000497333
1470 0.000269
1480 0.000183333
1490 0.000165333
1500 0.000192
1510 0.000175
1520 0.000200667
1530 0.00024
1540 0.000225667
1550 0.000192333
1560 0.000161
1570 0.000194
1580 0.000148667
1590 -0.000035
1600 0.000005
1610 0.000137
1620 0.000055
1630 -3.66667E-05
1640 2.26667E-05
1650 0.000012
1660 -0.000079
1670 -0.000099
1680 -0.000167
1690 -0.000207333
1700 -0.000227
1710 -0.000223
1720 -0.000222
1730 -0.000154667
1740 -0.000078
1750 -0.000119
1760 -0.000168
1770 -0.000119
1780 -0.000121667
1790 -0.000143
1800 -0.000054
1810 0.000024
1820 2.33333E-06
1830 -0.000025
1840 3.33333E-07
1850 4.46667E-05
1860 0.000038
1870 -1.36667E-05
1880 -5.63333E-05
1890 -0.000068
1900 -4.86667E-05
1910 -3.63333E-05
1920 -0.000014
1930 5.56667E-05
1940 0.000120333
1950 0.00008
1960 1.23333E-05
1970 2.33333E-06
1980 -0.000009
1990 -5.53333E-05
2000 -0.000139
2010 -0.00018
2020 -0.000151333
2030 -0.000053
2040 0.000006
2050 -0.000068
2060 -0.000011
2070 0.000245
2080 0.000428
2090 0.000492333
2100 0.000877
2110 0.002114
2120 0.004145333
2130 0.006308
2140 0.008737333
2150 0.010928333
2160 0.015221
2170 0.016506667
2180 0.010118
2190 -0.004162
2200 -0.012450667
2210 -0.014274667
2220 -0.015427
2230 -0.013374
2240 -0.009006667
2250 -0.003579
2260 0.005610667
2270 0.009615333
2280 0.010004
2290 0.009913
2300 0.010784667
2310 0.010727
2320 0.010896333
2330 0.009149333
2340 0.008374
2350 0.006517333
2360 0.004706333
2370 0.00303
2380 0.001536333
2390 0.000351
2400 -0.000581
2410 -0.000668333
2420 -0.000734667
2430 -0.000519
2440 -0.000685333
2450 -0.000889
2460 -0.000631
2470 -0.000444
2480 -0.00038
2490 -0.000271
2500 -0.000588333
2510 -0.000776333
2520 -0.000355
2530 -0.000100333
2540 -0.000235667
2550 -0.000323
2560 0.000136
2570 0.000852667
2580 0.001818
2590 0.003843667
2600 0.005362
2610 0.00755
2620 0.009662333
2630 0.010069667
2640 0.018863
2650 0.020548667
2660 0.022625667
2670 0.021145
2680 0.019562
2690 0.017756333
2700 0.016504
2710 0.015486667
2720 0.014131667
2730 0.011333
2740 0.007868667
2750 0.008469
2760 0.008073
2770 0.006241333
2780 0.003563
2790 0.00049
2800 -0.001542333
2810 -0.004198
2820 -0.006062
2830 -0.008759667
2840 -0.012348333
2850 -0.011128
2860 -0.009510667
2870 -0.008321
2880 -0.006072
2890 -0.003494667
2900 -0.002556
2910 -0.001183
2920 -0.000485667
2930 0.000131667
2940 0.000578
2950 0.001170333
2960 0.000837333
2970 0.000659
2980 0.001185667
2990 0.001364
3000 0.001348
3010 0.001305
3020 0.001296333
3030 0.001025
3040 0.000975333
3050 0.001000333
3060 0.000872
3070 0.000852
3080 0.000906333
3090 0.000973
3100 0.000796667
3110 0.000647667
3120 0.000625
3130 0.000425333
3140 0.000233333
3150 0.000096
3160 -1.73333E-05
3170 -0.000185333
3180 -0.00019
3190 -5.63333E-05
3200 -4.43333E-05
3210 0.000024
3220 -0.000146
3230 -0.000319333
3240 -0.000389
3250 -0.000722333
3260 -0.001367667
3270 -0.002464
3280 -0.004044667
3290 -0.005740667
3300 -0.006801
3310 -0.007030667
3320 -0.007430667
3330 -0.007836
3340 -0.008042667
3350 -0.007583667
3360 -0.007634
3370 -0.006841667
3380 -0.005936333
3390 -0.005774
3400 -0.005605667
3410 -0.005634333
3420 -0.005491
3430 -0.005477667
3440 -0.005563667
3450 -0.005694
3460 -0.005568333
3470 -0.005536333
3480 -0.005497
3490 -0.005480667
3500 -0.005576
3510 -0.005383
3520 -0.005383
3530 -0.005246333
3540 -0.005166
3550 -0.004881667
3560 -0.004504667
3570 -0.003667
3580 -0.002981667
3590 -0.002318667
3600 -0.001536
3610 -0.001161333
3620 -0.000904333
3630 -0.000695
3640 -0.000704
3650 -0.000717667
3660 -0.000516
3670 -0.000264333
3680 -0.000217667
3690 -0.000355
3700 -0.000393
3710 -0.000423
3720 -0.000461
3730 -0.000425333
3740 -0.000239333
3750 -0.000073
3760 -6.96667E-05
3770 0.000015
3780 0.000261
3790 0.000564667
3800 0.000743
3810 0.000814
3820 0.001088333
3830 0.001446
3840 0.002031
3850 0.003003667
3860 0.004454
3870 0.006528
3880 0.007872333
3890 0.009518
3900 0.010766
3910 0.011522333
3920 0.013053333
3930 0.013552
3940 0.013813
3950 0.013885333
3960 0.012555
3970 0.013071
3980 0.012528667
3990 0.011411
4000 0.007893
4010 0.001871667
4020 -0.006091
4030 -0.010214333
4040 -0.011719
4050 -0.011786
4060 -0.011460667
4070 -0.011470667
4080 -0.010756
4090 -0.010565
4100 -0.008367333
4110 -0.006189
4120 -0.005072667
4130 -0.002471667
4140 -0.001364
4150 -0.001567667
4160 -0.002122333
4170 -0.002496
4180 -0.001945
4190 -0.001223
4200 -0.000308
4210 0.000477
4220 0.000630667
4230 0.001528
4240 0.002781333
4250 0.003392333
4260 0.004682
4270 0.007125333
4280 0.010582
4290 0.013069
4300 0.015796
4310 0.016065
4320 0.013539
4330 0.013631333
4340 0.011672667
4350 0.010116
4360 0.008764667
4370 0.006085
4380 0.002755
4390 0.001196667
4400 0.000386667
4410 -0.000047
4420 0.000356333
4430 0.001528667
4440 0.004112
4450 0.006018333
4460 0.006968
4470 0.007622
4480 0.007682
4490 0.007854
4500 0.007835
4510 0.006713333
4520 0.006462667
4530 0.006042
4540 0.00545
4550 0.004076
4560 0.003074
4570 0.003070333
4580 0.003237
4590 0.002936
4600 0.00245
4610 0.002323
4620 0.002372
4630 0.00236
4640 0.002281
4650 0.002285
4660 0.002192667
4670 0.002210667
4680 0.002043
4690 0.001917667
4700 0.001819
4710 0.001665
4720 0.001829667
4730 0.001832667
4740 0.001749
4750 0.001643
4760 0.001580333
4770 0.001521
4780 0.001303333
4790 0.001361333
4800 0.00148
4810 0.001660333
4820 0.001864333
4830 0.002016
4840 0.001941667
4850 0.001824333
4860 0.00187
4870 0.001788667
4880 0.001729333
4890 0.001661
4900 0.001551333
4910 0.001335667
4920 0.001102
4930 0.000939333
4940 0.000744
4950 0.00065
4960 0.000567667
4970 0.000396667
4980 0.000207
4990 4.66667E-05
5000 -0.000145333
5010 -0.000277
5020 -0.000442
5030 -0.000677333
5040 -0.000849
5050 -0.001077
5060 -0.001342333
5070 -0.001556
5080 -0.001844333
5090 -0.002048333
5100 -0.002106
5110 -0.002032667
5120 -0.002021
5130 -0.002245
5140 -0.002624
5150 -0.002745667
5160 -0.00289
5170 -0.002954333
5180 -0.002967667
5190 -0.002948
5200 -0.002829667
5210 -0.002800667
5220 -0.00291
5230 -0.002752
5240 -0.002656667
5250 -0.002461
5260 -0.002427667
5270 -0.002415667
5280 -0.002216
5290 -0.001773
5300 -0.001381333
5310 -0.00112
5320 -0.00092
5330 -0.000716
5340 -0.000537
5350 -0.000584333
5360 -0.000802333
5370 -0.000959
5380 -0.001319333
5390 -0.002064
5400 -0.003083
5410 -0.004068
5420 -0.004532667
5430 -0.004454
5440 -0.004671333
5450 -0.004853333
5460 -0.004758
5470 -0.004564667
5480 -0.004783
5490 -0.004748
5500 -0.004566667
5510 -0.004406333
5520 -0.004094
5530 -0.003749
5540 -0.003350333
5550 -0.002997
5560 -0.002488
5570 -0.002137333
5580 -0.001735
5590 -0.001266667
5600 -0.00102
5610 -0.000817
5620 -0.000644667
5630 -0.000488667
5640 -0.000235
5650 -4.73333E-05
5660 0.000158333
5670 0.000307
5680 0.000520333
5690 0.000845333
5700 0.000997
5710 0.001062333
5720 0.001221667
5730 0.001368
5740 0.001652
5750 0.001762667
5760 0.001631
5770 0.001563667
5780 0.001673667
5790 0.001788
5800 0.001747667
5810 0.001633667
5820 0.001504
5830 0.001398333
5840 0.001274667
5850 0.001063
5860 0.000743667
5870 0.000491333
5880 0.000233
5890 4.66667E-05
5900 0.000188667
5910 0.000227
5920 0.00018
5930 0.000007
5940 -0.000029
5950 0.000385667
5960 0.000569333
5970 0.000679
5980 0.002694
5990 0.005252
6000 0.017234
6010 0.031803333
6020 0.035275667
6030 0.020078
6040 -0.024973333
6050 -0.045326333
6060 -0.039965
6070 -0.031691667
6080 -0.017527
6090 -0.010846
6100 -0.004321
6110 -0.001869
6120 -0.000669
6130 0.000133667
6140 0.000476667
6150 0.000523
6160 0.000494
6170 -0.000202667
6180 -0.000084
6190 0.000014
6200 -0.000167
6210 -0.000189
6220 -0.000149
6230 0.000094
6240 -0.000123
6250 -7.46667E-05
6260 -8.43333E-05
6270 -0.00015
6280 -0.00005
6290 0.000221333
6300 0.000249
6310 -0.000025
6320 3.46667E-05
6330 0.000054
6340 0.000029
6350 -1E-06
6360 -0.000031
6370 -0.000061
6380 -0.000091
6390 -0.000121
6400 -0.000151
6410 -0.000181
6420 -0.000211
6430 -0.000241
6440 -0.000271
6450 -0.000301
6460 -0.000331
6470 -0.000361
6480 -0.000391
6490 -0.000421
6500 -0.000451
6510 -0.000481
6520 -0.000511
6530 -0.000541
6540 -0.000571
6550 -0.000601
6560 -0.000631
6570 -0.000661
6580 -0.000691
6590 -0.000721
6600 -0.000751
6610 -0.000781
6620 -0.000811
6630 -0.000841
6640 -0.000871
6650 -0.000901
6660 -0.000931
6670 -0.000961
6680 -0.000991
6690 -0.001021
6700 -0.001051
6710 -0.001081
6720 -0.001111
6730 -0.001141
6740 -0.001171
6750 -0.001201
6760 -0.001231
6770 -0.001261
6780 -0.001291
6790 -0.001321
6800 -0.001351
6810 -0.001381
6820 -0.001411
6830 -0.001441
6840 -0.001471
6850 -0.001501
6860 -0.001531
6870 -0.001561
6880 -0.001591
6890 -0.001621
6900 -0.001651
6910 -0.001681
6920 -0.001711
6930 -0.001741
6940 -0.001771
6950 -0.001801
SetupFile.json includes parameters:
{
"setupName" : "Gp2Dummy",
"mcar" : 728,
"clt" : 3.1,
"cx" : 1.0,
"afrcar" : 1.0,
"mbrk" : 7000,
"gripx" : 1.15,
"gripy" : 1.40,
"loadEff" : 0.10,
"rtyre" : 0.32,
"rGearRat" : [10.0,7.8,6.1,7.8,5.2,4.5,4.0],
"reff" : 0.95,
"EngNm" : [200,300,430,380],
"EngRpm" : [0,3000,7000,10000],
"rho" : 1.22
}
Based on the information above, complete the following tasks:
#Task 1
Compute the maximum possible speed the car achieves anywhere on the lap.
#Task 2
The minimum possible lap time the car can achieve over a single lap.
Please use consistent SI units and convert top speed in km/hr and lap time into seconds(s). | Rushabh Prasad Shetty |
AB_02 | 691 | Signal Processing | ## Task Description
You are an expert Python programmer specializing in Computer Vision using the OpenCV library. Your task is to implement the **Watershed algorithm** (`cv2.watershed`) for image segmentation specifically for the image located at 'images/8_of_hearts.png'.
The goal is to segment the foreground objects (the red heart pips and '8' numerals) from the white background in this specific image.
**Constraint: You MUST use the OpenCV Watershed algorithm (`cv2.watershed`) for the core segmentation step. Using any other segmentation method (e.g., color thresholding alone, contour finding alone, GrabCut, etc.) will result in a failed evaluation.**
## Implementation Steps
The implementation should follow this specific logic:
1. Loading the image directly from the path 'images/8_of_hearts.png' and converting it to grayscale.
2. Thresholding the grayscale image (using THRESH_BINARY_INV | THRESH_OTSU).
3. Morphological opening to remove noise (kernel = np.ones((3,3), np.uint8), iterations = 2).
4. Finding sure background via dilation (kernel = np.ones((3,3), np.uint8), iterations=3).
5. Finding sure foreground via distance transform (cv2.DIST_L2, mask size 5) and thresholding. Use a threshold based on the distance transform's maximum value (e.g., 0.7 * dist_transform.max()) to determine the sure foreground region.
6. Identifying the unknown region by subtracting sure foreground from sure background.
7. Labeling components using `cv2.connectedComponents` on the sure foreground.
8. Preparing markers for watershed (incrementing labels, setting unknown region to 0).
9. Applying `cv2.watershed` using the original color image loaded from 'images/8_of_hearts.png'. **This step is mandatory.**
10. Generating a final binary mask from the watershed markers.
## Input Specification
The solution code's main function should *not* take an image path as an argument. It must internally use the hardcoded path 'images/8_of_hearts.png' for all image loading and processing operations.
## Output Specification
Your response must be structured according to the CodeSolutionOutput Pydantic model, containing the following fields:
1. reasoning: Provide a clear, step-by-step explanation of how the code implements the Watershed segmentation process for the specified image ('images/8_of_hearts.png') according to the requirements. Explain each major step.
2. solution_code: Provide the complete Python code.
* The code must include necessary imports (numpy, cv2).
* The core logic should be encapsulated within a function named `segment_image` that takes **no arguments**.
* This function must load the image using the hardcoded path `'images/8_of_hearts.png'`.
* This function must **return** the final binary segmentation mask as a NumPy array (dtype=uint8), where foreground pixels (segmented objects) are 255 and background/boundaries are 0.
* The code should **not** include any code for displaying images or saving files directly. It should only perform the calculation and return the mask array.
* Include basic error handling for image loading (return None if the image cannot be loaded from the hardcoded path). | Ayush Barik |
XY_05 | 975 | Digital Hardware Design | # SLC-3 CPU Design
This assessment evaluate the SLC-3 CPU's control logic and state machine implementation.
## PART 1: Control Signal Settings
For each instruction, determine the precise configuration of all control signals during the execution phase.
The response MUST be structured as follows:
"ports_table": {
"ADD": {
"ld_reg": "",
"ld_ir": "",
"ld_pc": "",
"ld_cc": "",
"gateALU": "",
"gateMDR": "",
"mem_en": "",
"mem_we": ""
},
"AND": {
// Control signals for AND
},
// Continue for each instruction...
}
## PART 2: State Machine Implementation
The SLC-3 CPU uses the following key states in its finite state machine:
- s_18: Common fetch cycle state
- s_32: Decode state
- s_1: ADD execution state
- s_5: AND execution state
- s_9: NOT execution state
- s_0: BR evaluation state
- s_22: BR taken state
- s_12: JMP execution state
- s_4: JSR execution state
- s_21: JSR linkage state
- s_6: LDR address calculation state
- s_25_1, s_25_2, s_25_3: LDR memory access sequence states
- s_27: LDR data ready state
- s_7: STR address calculation state
- s_23: STR memory prepare state
- s_16_1, s_16_2, s_16_3: STR memory write sequence states
Your state_transitions MUST use this exact format:
"state_transitions": {
"ADD": {
"current": "s_1",
"next": ""
},
"AND": {
"current": "s_5",
"next": ""
},
// For BR, use this special format
"BR": {
"current": "s_0",
"next_taken": "",
"next_not_taken": "",
"sequence_taken": ","
},
// Multi-cycle example (use comma-separated string)
"LDR": {
"current": "s_6",
"next": "",
"sequence": ",,,,"
}
}
IMPORTANT: For multi-cycle instructions and branch paths, use comma-separated strings (NOT arrays or nested objects).
## PART 3: Explanations
You must also provide a detailed explanation for each instruction:
"explanation": {
"ADD": "Explanation for ADD instruction...",
"AND": "Explanation for AND instruction...",
// Continue for each instruction...
}
## Instructions to Analyze:
1. ADD - Arithmetic addition
2. AND - Bitwise AND
3. NOT - Bitwise complement
4. LDR - Load from memory to register
5. STR - Store register to memory
6. BR - Conditional branch
7. JMP - Unconditional jump
8. JSR - Jump to subroutine
9. SWAP - Exchange registers (custom instruction)
## Critical Design Constraints:
Hardware safety: No multiple components may drive the bus simultaneously
Control accuracy: PC updates occur only during branch and jump operations
State consistency: All execution paths must eventually return to s_18 (fetch cycle)
Cycle requirements: Memory operations must follow proper sequence states
Instruction integrity: JSR must save return address to R7 before jumping
Power efficiency: Minimize active control signals whenever possible
## REQUIRED OUTPUT FORMAT:
Your complete response MUST follow this exact structure:
{
"config": {
"ports_table": {
"ADD": { "ld_reg": "1", "ld_ir": "0", ... },
"AND": { ... },
// All instructions
},
"explanation": {
"ADD": "Explanation text...",
"AND": "Explanation text...",
// All instructions
},
"state_transitions": {
"ADD": { "current": "s_1", "next": "" },
"AND": { "current": "s_5", "next": "" },
"BR": { "current": "s_0", "next_taken": "s_22", "next_not_taken": "", "sequence_taken": "," },
"LDR": { "current": "s_6", "next": "", "sequence": "" },
// All instructions
}
}
}
Ensure you follow this structure exactly. Use strings for all values, and comma-separated strings (not arrays) for sequences. Any validation errors will result in automatic failure. | XiangYi Kong
|
libin2_02 | 310 | Operating System Design | ### Task Description
In this task, you need to choose an appropriate Round-Robin time quantum (time_quantum) for a set of threads in order to minimize the **combined cost**.
We will calculate three cost components:
1. Average waiting time(avg_waiting_time), in milliseconds (ms). Smaller is better.
2. Number of context switches(context_switches). Each switch counts as 1 ms of overhead. Fewer is better.
3. Time quantum cost(quantum_cost), reflecting the negative impact of too long a time quantum, defined as: quantum_cost = time_quantum * 0.5
The combined cost(combined_cost) is the sum of these three components.
### Input
The thread list is given as tuples (arrival_time, burst_time), both in ms:
case1 = [(0,5),(2,3),(4,8),(6,6),(8,4)]
case2 = [(0,10),(1,2),(3,7),(5,5)]
case3 = [(0,2),(2,2),(4,2),(6,2),(8,2),(10,2)]
### Requirements
Choose a single time quantum such that the combined cost for each case does not exceed:
- case1: 17 ms
- case2: 17 ms
- case3: 8 ms
Return the chosen time_quantum and, for each case, the corresponding avg_waiting_time, context_switches, and quantum_cost. | Libin Wang |
NS_PA_SS_08 | 357 | Digital Hardware Design | You are a hardware‐design expert. Write synthesizable SystemVerilog for a target‐sequence detector that pulses a 1 on `seen` whenever a specified 5-bit pattern appears in a serial bitstream, according to the following spec:
1. Parameterization
- parameter TARGET_WIDTH = 5;
2. Ports
```verilog
module model #(
parameter TARGET_WIDTH = 5
) (
input logic clk, // clock signal
input logic resetn, // synchronous, active-low reset
input logic [TARGET_WIDTH-1:0] init,// target sequence, loaded on reset
input logic din, // serial input bit
output logic seen // pulses high for one cycle on match
);
Behavior
Target loading: On each rising edge when resetn==0, latch init into an internal target register.
Shift register: Maintain a TARGET_WIDTH-bit shift register of the last received bits. On each rising edge when resetn==1, shift in din.
Detection: Compare the internal shift register to target. If they match, assert seen=1 for one clock cycle; otherwise seen=0.
Sequence reset: When resetn==0, clear the shift register (so previous bits are forgotten) and drive seen=0.
Padding: Treat shorter init values as zero-padded on the high side (e.g. 3'b11 → 5'b00011).
Implementation notes
Fully synchronous logic.
Use a generate or loop to build the comparator if desired.
seen should be a one-cycle pulse on each detection, overlapping matches allowed (i.e. detect overlapping patterns).
Produce clean, commented, synthesizable SystemVerilog that meets this specification.`` | Nippun Sabharwal, Shreyanka Sinha, Prakhar Agarwal |
JY_02 | 151 | Signal Processing | You are working with a image and want to develop a real kernel that detects the edges of the image. Create the kernel and return the convoluted edge output as an array
You should follow the following
1, Apply a gaussian blur to smooth the image.
2, Design a filtering mechanizim to filter only the significant edges with one x direction kernel and y direction kernel of the same size and shape.
3, Design a threshold of max and min value to filter out noisy edges.
based on the data of the input image array, you should choose the optimal size of the gaussian and edge filtering kernels and the values in them.
In the end, we will compare your response with the baseline response using edge density, connectivity and entropy.
Input image:
[
[76, 77, 74, 75, 75, 73, 71, 71, 72, 74, 70, 69, 67, 66, 66, 68, 70, 71, 68, 65, 61, 57, 57, 59, 63, 66, 75, 75, 74, 71, 66, 63, 62, 62, 58, 61, 65, 69, 71, 71, 70, 69, 68, 65, 63, 65, 68, 70, 66, 63, 60, 60, 61, 63, 66, 67, 66, 64, 63, 63, 64, 66, 67, 69, 70, 71, 69, 68, 66, 65, 64, 66, 67, 69, 63, 63, 64, 65, 67, 71, 74, 76, 72, 69, 67, 68, 72, 75, 76, 76, 74, 73, 71, 70, 69, 69, 70, 71, 64, 66]
[75, 77, 74, 74, 74, 71, 68, 67, 67, 69, 68, 67, 66, 65, 67, 69, 72, 74, 74, 71, 67, 64, 65, 70, 76, 80, 79, 79, 79, 76, 72, 69, 69, 69, 66, 70, 77, 81, 82, 78, 73, 69, 70, 66, 64, 66, 70, 72, 68, 63, 64, 65, 66, 70, 73, 74, 73, 72, 70, 71, 72, 73, 73, 72, 71, 70, 73, 72, 69, 68, 68, 69, 71, 72, 67, 67, 67, 68, 70, 72, 75, 77, 74, 70, 68, 69, 73, 77, 78, 78, 76, 75, 73, 71, 70, 70, 71, 72, 69, 70]
[75, 75, 76, 75, 75, 74, 75, 76, 77, 77, 79, 77, 75, 73, 73, 75, 77, 78, 76, 77, 77, 77, 76, 75, 73, 72, 74, 76, 78, 80, 82, 81, 80, 80, 73, 74, 75, 76, 76, 76, 76, 75, 66, 68, 69, 71, 71, 71, 69, 69, 72, 72, 71, 71, 71, 72, 73, 74, 74, 74, 74, 73, 73, 73, 73, 72, 68, 69, 70, 71, 72, 72, 72, 72, 70, 71, 73, 74, 75, 75, 74, 73, 70, 69, 68, 71, 76, 80, 79, 78, 77, 78, 78, 77, 77, 77, 80, 82, 80, 79]
[78, 78, 80, 79, 78, 77, 76, 76, 75, 75, 75, 74, 74, 73, 73, 74, 75, 76, 80, 79, 79, 78, 78, 78, 78, 78, 77, 77, 76, 76, 77, 77, 78, 78, 82, 81, 80, 78, 76, 75, 74, 73, 72, 73, 74, 75, 75, 75, 75, 74, 75, 74, 74, 73, 73, 74, 75, 75, 73, 73, 72, 72, 72, 72, 72, 72, 72, 73, 74, 75, 76, 77, 77, 77, 76, 77, 79, 80, 80, 80, 79, 78, 75, 74, 74, 76, 81, 83, 83, 81, 80, 83, 87, 87, 85, 84, 85, 87, 87, 86]
[81, 81, 83, 83, 83, 82, 81, 79, 78, 77, 71, 72, 73, 74, 74, 75, 75, 74, 78, 78, 77, 77, 78, 78, 79, 80, 83, 81, 79, 77, 76, 77, 79, 80, 83, 81, 79, 76, 73, 72, 72, 72, 75, 75, 75, 75, 76, 76, 77, 77, 77, 76, 75, 75, 75, 75, 76, 76, 76, 76, 76, 77, 77, 77, 77, 77, 75, 75, 75, 76, 77, 79, 81, 82, 81, 82, 84, 86, 88, 89, 89, 89, 85, 84, 84, 86, 89, 91, 91, 90, 89, 95, 101, 102, 98, 94, 95, 97, 93, 93]
[86, 87, 88, 89, 89, 90, 89, 88, 86, 85, 79, 80, 83, 85, 85, 85, 83, 82, 81, 82, 83, 85, 86, 86, 86, 85, 88, 87, 86, 85, 85, 86, 87, 88, 84, 82, 80, 78, 77, 78, 80, 81, 79, 79, 79, 79, 80, 80, 81, 81, 86, 85, 84, 83, 82, 82, 82, 83, 84, 84, 85, 85, 86, 87, 87, 87, 83, 83, 83, 84, 85, 88, 90, 91, 91, 93, 95, 98, 101, 104, 106, 107, 103, 103, 103, 104, 106, 107, 107, 107, 104, 110, 115, 113, 107, 103, 105, 108, 101, 102]
[100, 100, 101, 101, 101, 100, 99, 97, 96, 95, 94, 96, 98, 100, 101, 100, 98, 96, 92, 95, 99, 102, 103, 102, 100, 98, 92, 94, 95, 97, 98, 98, 97, 97, 93, 92, 91, 90, 91, 93, 96, 97, 92, 93, 93, 94, 94, 94, 95, 95, 101, 100, 99, 97, 96, 96, 96, 96, 93, 93, 94, 95, 96, 97, 98, 98, 100, 101, 101, 102, 103, 105, 106, 107, 109, 110, 111, 113, 115, 117, 119, 120, 119, 120, 121, 122, 123, 123, 124, 125, 120, 123, 124, 121, 115, 112, 114, 118, 113, 113]
[116, 117, 118, 117, 114, 112, 109, 108, 107, 107, 105, 106, 108, 110, 110, 108, 106, 105, 103, 106, 110, 113, 114, 113, 110, 108, 100, 102, 105, 108, 109, 109, 108, 107, 106, 106, 105, 106, 108, 110, 113, 114, 112, 113, 115, 117, 117, 116, 115, 114, 117, 116, 114, 113, 111, 110, 110, 110, 107, 107, 108, 110, 111, 113, 114, 114, 119, 120, 121, 122, 123, 123, 123, 123, 125, 124, 123, 123, 122, 123, 124, 124, 127, 129, 131, 132, 132, 132, 135, 136, 138, 138, 136, 133, 131, 130, 131, 133, 126, 125]
[124, 126, 126, 125, 122, 120, 120, 121, 123, 125, 120, 121, 121, 122, 121, 119, 117, 116, 115, 116, 117, 118, 118, 118, 118, 118, 116, 116, 117, 118, 118, 119, 119, 119, 119, 121, 124, 128, 132, 136, 139, 140, 142, 144, 148, 150, 151, 149, 146, 144, 142, 141, 139, 137, 135, 134, 133, 133, 131, 132, 133, 135, 137, 138, 139, 140, 142, 144, 146, 148, 148, 146, 144, 143, 140, 139, 138, 137, 137, 138, 139, 140, 142, 145, 148, 149, 148, 149, 152, 155, 157, 155, 154, 156, 158, 159, 158, 156, 153, 149]
[125, 126, 126, 125, 124, 124, 127, 132, 138, 141, 139, 139, 139, 138, 137, 135, 134, 133, 128, 126, 124, 122, 123, 125, 128, 130, 130, 128, 126, 125, 125, 125, 127, 128, 133, 136, 142, 150, 157, 163, 168, 170, 172, 175, 179, 182, 183, 180, 176, 174, 170, 168, 166, 164, 162, 161, 160, 160, 153, 154, 156, 157, 159, 161, 163, 163, 166, 168, 171, 173, 173, 170, 166, 164, 155, 155, 155, 156, 158, 161, 164, 165, 164, 168, 171, 172, 172, 173, 176, 180, 171, 170, 170, 176, 182, 184, 180, 175, 183, 177]
[127, 128, 132, 126, 122, 124, 133, 141, 146, 147, 147, 151, 156, 161, 161, 158, 154, 150, 147, 144, 140, 136, 134, 133, 134, 135, 135, 139, 142, 139, 133, 131, 135, 140, 153, 159, 169, 178, 183, 183, 181, 179, 180, 182, 185, 189, 191, 191, 187, 183, 181, 179, 178, 178, 180, 182, 182, 181, 175, 174, 173, 172, 172, 173, 174, 175, 182, 179, 177, 178, 181, 182, 180, 177, 171, 172, 174, 175, 177, 178, 178, 178, 181, 182, 185, 187, 188, 187, 185, 184, 180, 178, 179, 185, 192, 195, 192, 188, 191, 188]
[148, 148, 151, 147, 144, 146, 151, 155, 154, 152, 159, 160, 163, 165, 167, 167, 167, 167, 166, 165, 163, 161, 159, 157, 156, 156, 147, 152, 159, 164, 166, 165, 163, 162, 164, 168, 172, 175, 175, 172, 167, 164, 172, 174, 178, 183, 187, 188, 186, 183, 182, 182, 182, 183, 184, 184, 182, 180, 177, 178, 179, 180, 180, 180, 179, 179, 175, 173, 172, 175, 179, 182, 181, 179, 177, 177, 178, 178, 178, 178, 177, 176, 179, 181, 183, 185, 185, 184, 183, 182, 174, 171, 171, 175, 183, 188, 187, 185, 188, 186]
[159, 157, 166, 165, 165, 167, 171, 170, 166, 162, 169, 168, 166, 165, 165, 168, 171, 173, 174, 175, 175, 175, 173, 171, 169, 167, 156, 158, 162, 170, 176, 179, 176, 173, 174, 174, 173, 171, 166, 161, 155, 152, 165, 167, 171, 177, 182, 184, 183, 181, 178, 179, 181, 184, 184, 182, 176, 172, 172, 174, 177, 179, 181, 180, 179, 178, 169, 168, 168, 172, 179, 183, 183, 182, 181, 181, 181, 180, 178, 176, 174, 173, 177, 179, 180, 181, 182, 181, 180, 179, 171, 168, 166, 168, 173, 177, 178, 177, 177, 177]
[160, 158, 169, 170, 171, 175, 178, 178, 175, 172, 177, 174, 170, 166, 165, 166, 169, 170, 176, 176, 176, 175, 175, 174, 173, 172, 170, 166, 163, 161, 164, 169, 175, 178, 181, 179, 177, 173, 169, 165, 162, 160, 166, 167, 169, 174, 177, 178, 176, 174, 173, 176, 180, 184, 184, 179, 172, 166, 163, 165, 167, 170, 173, 175, 176, 176, 167, 166, 167, 171, 178, 183, 183, 182, 178, 178, 177, 176, 174, 172, 170, 169, 174, 175, 176, 176, 176, 175, 174, 173, 172, 170, 168, 168, 170, 170, 168, 166, 163, 163]
[167, 166, 170, 170, 171, 173, 175, 176, 176, 175, 179, 178, 176, 175, 174, 173, 174, 174, 178, 176, 174, 172, 172, 173, 174, 175, 180, 178, 173, 166, 162, 166, 176, 185, 186, 184, 180, 177, 175, 174, 174, 174, 169, 168, 169, 170, 171, 170, 167, 164, 170, 173, 178, 183, 184, 179, 171, 165, 156, 156, 157, 159, 162, 167, 172, 175, 166, 165, 164, 168, 174, 178, 178, 176, 170, 170, 171, 170, 170, 169, 168, 167, 169, 169, 169, 169, 168, 167, 166, 166, 167, 168, 169, 171, 171, 168, 164, 161, 155, 156]
[173, 174, 174, 173, 172, 171, 170, 170, 170, 170, 169, 171, 174, 176, 177, 178, 177, 176, 169, 167, 164, 161, 160, 162, 164, 166, 168, 172, 174, 171, 166, 166, 173, 180, 180, 178, 175, 172, 170, 171, 172, 173, 170, 169, 168, 167, 167, 165, 161, 158, 163, 165, 170, 175, 177, 174, 168, 163, 152, 151, 150, 150, 153, 158, 163, 167, 165, 163, 162, 165, 170, 172, 171, 169, 166, 166, 168, 169, 169, 169, 169, 169, 167, 167, 166, 165, 164, 163, 162, 162, 161, 164, 169, 172, 173, 171, 167, 165, 161, 160]
[169, 171, 174, 174, 173, 171, 168, 165, 164, 164, 160, 162, 167, 171, 173, 174, 174, 173, 163, 162, 160, 158, 157, 157, 158, 158, 156, 161, 165, 167, 167, 167, 168, 170, 173, 172, 169, 168, 167, 168, 170, 171, 171, 170, 169, 169, 170, 169, 166, 164, 161, 162, 166, 171, 174, 174, 171, 168, 161, 159, 158, 157, 157, 159, 162, 164, 167, 164, 163, 165, 170, 172, 171, 169, 169, 170, 171, 173, 174, 174, 175, 175, 173, 172, 171, 169, 168, 167, 166, 166, 164, 168, 172, 175, 176, 175, 174, 173, 173, 171]
[164, 166, 169, 170, 171, 171, 168, 164, 162, 161, 161, 163, 166, 169, 171, 171, 171, 170, 171, 172, 172, 171, 170, 168, 166, 165, 164, 163, 163, 166, 171, 174, 174, 173, 175, 174, 173, 173, 174, 176, 179, 180, 172, 172, 172, 173, 175, 176, 175, 173, 168, 169, 172, 176, 181, 183, 182, 180, 177, 177, 175, 174, 173, 172, 171, 170, 170, 167, 166, 169, 173, 176, 175, 173, 174, 175, 176, 178, 179, 179, 179, 179, 181, 180, 178, 177, 175, 174, 173, 173, 174, 176, 178, 179, 179, 178, 178, 179, 182, 178]
[164, 170, 169, 170, 172, 175, 177, 177, 175, 173, 174, 174, 173, 174, 176, 179, 181, 183, 176, 178, 180, 181, 179, 176, 172, 170, 166, 167, 170, 172, 175, 176, 177, 178, 177, 176, 176, 177, 179, 179, 178, 176, 181, 181, 182, 184, 186, 186, 184, 182, 180, 181, 183, 184, 184, 183, 181, 180, 180, 181, 182, 181, 179, 178, 178, 179, 174, 173, 173, 176, 178, 177, 172, 167, 167, 170, 175, 180, 183, 184, 184, 183, 183, 185, 186, 186, 183, 180, 178, 178, 176, 178, 180, 180, 178, 177, 177, 178, 178, 178]
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[224, 227, 226, 224, 221, 219, 218, 217, 215, 213, 206, 205, 204, 205, 205, 204, 201, 198, 188, 190, 193, 196, 198, 200, 200, 200, 201, 204, 205, 203, 198, 193, 192, 193, 194, 185, 176, 172, 175, 180, 183, 183, 180, 185, 190, 189, 181, 171, 162, 158, 154, 152, 153, 158, 165, 171, 173, 172, 174, 171, 166, 163, 163, 163, 163, 162, 156, 150, 155, 162, 148, 124, 124, 142, 153, 164, 165, 154, 148, 154, 157, 154, 152, 148, 145, 143, 144, 144, 141, 138, 138, 139, 141, 142, 144, 144, 144, 144, 142, 139]
[219, 218, 212, 208, 203, 201, 201, 200, 197, 195, 192, 191, 190, 191, 190, 186, 179, 173, 170, 165, 165, 171, 173, 167, 163, 164, 175, 173, 170, 168, 167, 167, 169, 170, 167, 159, 150, 147, 151, 156, 157, 156, 152, 155, 158, 158, 154, 146, 137, 131, 131, 133, 136, 138, 140, 143, 147, 150, 148, 146, 147, 150, 149, 143, 141, 142, 136, 141, 145, 142, 133, 126, 126, 128, 142, 143, 140, 134, 132, 136, 140, 140, 136, 139, 142, 143, 142, 141, 141, 142, 137, 135, 135, 137, 137, 135, 138, 144, 136, 138]
[189, 188, 179, 174, 168, 165, 165, 166, 165, 163, 159, 158, 158, 159, 160, 158, 153, 149, 147, 144, 145, 150, 150, 145, 142, 143, 156, 154, 151, 149, 148, 148, 149, 150, 148, 143, 138, 136, 137, 139, 139, 137, 143, 144, 146, 146, 143, 137, 131, 127, 127, 129, 130, 130, 129, 130, 132, 134, 137, 135, 136, 138, 137, 132, 130, 131, 129, 134, 138, 134, 127, 123, 124, 128, 139, 141, 137, 131, 130, 134, 137, 137, 141, 144, 147, 147, 145, 143, 141, 141, 138, 134, 132, 132, 130, 129, 134, 140, 139, 140]
] | Jiankun Yang |
NS_PA_SS_06 | 401 | Digital Hardware Design | You are a hardware‐design expert. Write synthesizable SystemVerilog for a dot‐product module that computes A·B for two 3‐element vectors, according to the following spec:
1. Parameterization
- Each input element is an 8‐bit unsigned word.
- The output is an 18‐bit unsigned word.
2. Ports
```verilog
module model (
input logic [7:0] din, // serial input words: a1,a2,a3,b1,b2,b3
input logic clk, // clock signal
input logic resetn, // synchronous, active‐low reset
output logic [17:0] dout, // dot product result
output logic run // asserted for one cycle when dout is valid
);
Behavior
Input sequencing: On each rising edge of clk while resetn==1, sample din and store it in order a1→a2→a3→b1→b2→b3.
Dot‐product: After the 6th word (b3) is captured, in the same clock cycle assert run=1 and compute
dout = a1*b1 + a2*b2 + a3*b3;
as an 18‐bit unsigned sum.
Output timing:
When run=1, dout holds the new product.
In subsequent cycles (until the next 6 inputs), run=0 but dout retains its last value.
Reset: On resetn==0, clear all internal registers, set dout=0, and assert run=1 once (since 0·0=0).
Implementation hints
Use a 3‐entry shift‐register or counter to track which input you’re on.
Multiply and accumulate within one cycle after the 6th sample.
Ensure all operations are synchronous to clk.
Please produce clean, commented, synthesizable SystemVerilog that meets this specification.``` | Nippun Sabharwal, Shreyanka Sinha, Prakhar Agarwal |
LX_03 | 882 | Control Design | In vehicle dynamics, the \emph{quarter–car model} captures the vertical motion of a single wheel assembly and the corresponding section of chassis, using two masses (the sprung mass $M$ and unsprung mass $m$), interconnected by a suspension spring–damper and a tire spring. An \emph{active suspension} system adds a controllable actuator force $u$ between the sprung and unsprung masses, allowing real‑time adjustment of ride stiffness and damping. By rejecting road disturbances $y_R$ and shaping the chassis response, active control can greatly improve both \emph{ride comfort} and \emph{road holding}. Here, we linearize about the static equilibrium, normalize all displacements so that the resting positions are zero, and derive a linear time‑invariant state–space model suitable for controller design.
You can find a schematic of an active suspension system in the provided figure.
A state–space model in scientific units is given below, where $v_i = \dot x_i$.
The states $x_i$ have been normalized so that their nominal values are $0$.
\[
\frac{d}{dt}
\begin{bmatrix}
x_1\\
x_2\\
v_1\\
v_2
\end{bmatrix}
=
\begin{bmatrix}
0 & 0 & 1 & 0\\
0 & 0 & 0 & 1\\
-10 & 10 & -2 & 2\\
60 & -660 & 12 & -12
\end{bmatrix}
\begin{bmatrix}
x_1\\
x_2\\
v_1\\
v_2
\end{bmatrix}
+
\begin{bmatrix}
0\\
0\\
3.34\\
-20
\end{bmatrix}
u
+
\begin{bmatrix}
0\\
0\\
0\\
600
\end{bmatrix}
y_R
\]
\begin{enumerate}
\item Perform an open‑loop simulation of $x_1$ and $x_2$ for $0 \le t \le 20\,$s,
with
\[
x_1(0)=0.5\ \mathrm{m},\quad
x_2(0)=0\ \mathrm{m},\quad
v_1(0)=v_2(0)=0,\quad
u(t)=y_R(t)\equiv 0.
\]
Determine the values $p_1$ and $p_2$ of the two largest peaks in $x_1(t)$. Also, find the settling time $t_s$ defined as the time after which $|x_1(t)|<\SI{0.025}{m}$ holds for all subsequent $t$.
\item Repeat (1), but let $x_1(0)=\SI{0}{m}$ and $y_R$ be a square‐wave of amplitude $0.2\,$m
and fundamental frequency $0.2\,$Hz. Determine the number of peaks $N$ in $x_1(t)$ within one period, and find the value of the largest peak $p_m$.
\item Design a state‐feedback control law $K=[k1\ k2\ k3\ k4]$ for a comfortable ride, meeting the following requirements:
\begin{enumerate}
\item The DC gains of $X_1(s)/Y_R(s)$ and $X_2(s)/Y_R(s)$ remain $1$.
\item Achieve a critically damped closed‐loop response for $X_1(s)/Y_R(s)$.
\item Reduce the settling time to approximately half of the open‐loop value.
\item The car does not bottom out under the conditions of (1). In normalized states, this means that
\[
x_1(t)-x_2(t) > -0.5\ \mathrm{m}.
\]
\end{enumerate}
\end{enumerate} | Liujun Xu |
YX_02 | 781 | Mechanical Systems | ## Task Description
In this task, your goal is to produce local maps for a diesel engine calibration. You are provided with two global inputs: engine speed (N) and fuel mass (F), and four local inputs: injection (S), fuel pressure (P), variable geometry turbo rack position (G) and exhaust gas recirculation valve lift (E). Given the defined input ranges and physical constraints, you are required to perform structured sampling of the input space using the specified sampling strategy, ensuring representative and constraint-compliant coverage for subsequent modeling and calibration tasks.
### Task 1
First, for the global inputs: engine speed (N) and fuel mass (F), the maximum value of F changes as the value of N changes. You need to find the functional relationship between them.
The following information is given:
- At N = 1600, F <= 200.
- At N = 2000, F <= 175.
- Values between these two breakpoints are linearly interpolated.
Find the linear relationship between the maximum value of F and the value of N, and express their relationship in the format: F_max = a * N + b, where a, b are parameters.
### Task 2
After Task 1, you need to generate a **15 point Latin Hypercube Sampling (LHS)** design for the global inputs (N, F) based on the following specifications:
- Global Input Definitions:
- Engine speed (N):
- Range: [1600, 2200]
- Unit: rpm
- Fuel mass (F):
- Range: [20, 200]
- Unit: mg/stroke
- Physical Constraint:
- The maximum value of F has a linear relationship with the value of N, which you have gained from Task 1. When N is in the interval [1600, 2000], the sampling points you find need to satisfy this linear relationship. When N is not in the interval [1600, 2000], there are no constraints on F.
- Requirements:
- Use the LHS strategy to generate 15 design points.
- All sampled points must satisfy the constraint on F based on N.
### Task 3
Given a global operating point with engine speed N = 1900 rpm, calculate the **normalized speed factor** as: f = (N - 1600) / (2200 - 1600).
Use this factor f to determine input-dependent variable limits via **linear interpolation**:
- For the fuel pressure (P) limits:
- P_range = (1 − f) * [90, 120] + f * [110, 160]
- For the variable geometry turbo rack position (G) limits:
- G_range = (1 − f) * [0.2, 0.4] + f * [0.6, 0.9]
These bounds will be used for local sampling in the next task.
### Task 4
Based on the result from Task 2 and the given global inputs:
- Engine speed: N = 1900 rpm
- Fuel mass: F = 110 mg/stroke
Construct a **local design of experiments** using **Latin Hypercube Sampling (LHS)** over the following local inputs:
- Injection (S):
- Range: [-9, 3]
- Unit: deg
- Fuel pressure (P):
- Range: P_range computed from Task 2
- Unit: MPa
- Variable geometry turbo rack position (G):
- Range: G_range computed from Task 2
- Unit: ratio
- Exhaust gas recirculation valve lift (E):
- Range: [0.5, 5]
- Unit: mm
Your design must contain **30 local samples** that respect the variable-specific bounds defined above.
| Yaxin Li |
XG_12 | 484 | Control Design | ## Task Description
Consider the following plant with a resonance:
\[
G(s) = \frac{0.5}{s}\frac{169}{s^2 + 0.26s + 169},
\]
This plant has a resonance around 13 rad/sec. Assuming the desired loop bandwidth is $ \omega_{L} = 3 $ rad/sec. An initial loop shaping controller using controller gain and integral boost is given as:
- gain: $ K_g = \frac{1}{|G(j\omega_L)|}$,
- integral boost: $ K_i(s) = \frac{\beta_b s + \omega_L}{s \sqrt{\beta_b^2 + 1}}$ with $ \beta_b = \sqrt{10}$.
And the initial loop shaping controller is:
\[
C(s) = K_g \cdot K_i(s)
\]
### Task 1
Your first task is to obtain the explicit transfer function of the initial loop shaping controller. Please provide the complete transfer function of \( C(s) \) as part of your response in the form of numerator and denominator coefficients.
### Task 2
The initial design yeilds a unstable closed-loop system since there are additional gain crossings at 11.3 and 14.2 rad/sec. Your task is to build upon the initial controller, add a notch filter to attenuate the resonance. A notch filter with three parameters (\omega_n, \alpha_n, f_n) is given as:
\[
K_n(s) = \frac{s^2 + (f_n \omega_n \sqrt{\alpha_n})s + \omega_n^2}{s^2 + ((f_n \omega_n)/(\sqrt{\alpha_n}))s + \omega_n^2}.
\]
Now your goal is to determine the parameters of the notch filter to attenuate the resonance. Here are some information may help you design the notch filter:
- The resonance frequency is 13 rad/sec.
- The loop without notch filter has a magnitude of 21 dB near the resonance frequency.
You need to design the notch filter to achieve the following requirements:
- The closed-loop system is stable.
- The closed-loop system should have a phase margin of at least 60 degrees.
- The closed-loop system should have a gain margin of at least 2 dB.
| Xingang Guo |
NS_PA_SS_07 | 453 | Digital Hardware Design | You are a hardware‐design expert. Write synthesizable Verilog for a simple 1-read/1-write register file (RF) implemented as a multidimensional array of flip-flops, according to the following spec:
1. Architecture
- The RF has 8 entries, each 8 bits wide.
- Internally use `reg [7:0] mem [0:7];` or equivalent to model the array of flip-flops.
2. Ports
```verilog
module model (
input wire [7:0] din, // data input for write
input wire [2:0] addr, // address for read or write
input wire wr, // write-enable
input wire rd, // read-enable
input wire clk, // clock
input wire resetn, // synchronous, active-low reset
output reg [7:0] dout, // data output for read
output reg error // error flag for invalid op
);
Behavior
Reset (resetn == 0):
Clear all memory entries (optional) or implicitly treat as “unwritten.”
Drive dout = 0, error = 0.
One operation per cycle on rising edge of clk:
If both wr and rd are high → invalid:
error = 1, dout = 0.
Else if wr is high (wr == 1 && rd == 0):
Write din into mem[addr].
error = 0, dout = 0.
Else if rd is high (rd == 1 && wr == 0):
If the addressed entry has been written before (or track via a valid bit):
dout = mem[addr], error = 0.
Else (unwritten address):
dout = 0, error = 0.
Else (no operation):
dout = 0, error = 0.
Implementation notes
You may use a reg valid [0:7]; array to track which entries have been written.
All logic must be synchronous to clk.
Keep the design simple and fully synthesizable.
Produce clean, commented Verilog that meets this specification. | Nippun Sabharwal, Shreyanka Sinha, Prakhar Agarwal |
LX_02 | 645 | Control Design | Magnetic levitation systems suspend a ferromagnetic ball beneath an electromagnet by balancing gravitational and magnetic forces. The fundamental nonlinear dynamics are given by
\[
m\ddot y=mg-\frac{kI^2}{y^2},
\]
where \(y(t)\) is the ball’s vertical displacement and \(I(t)\) the coil current. Around an operating point \((y_0,I_0)\), a first‑order Taylor expansion and appropriate nondimensionalization yield a normalized second‑order linear model suitable for controller design. In this task, you are required to analyze that linearized model and then validate the controller on the original nonlinear dynamics.
To simplify the problem, consider the following equation:
\[
\ddot y=1-\frac{u^2}{y^2}.
\]
\begin{enumerate}
\item Linearize the nonlinear equation around the operating point $y = 1, u=1$. You need to give $a_{11},a_{12},a_{21},a_{22},b_{11},b_{21}$, where
\[\dot{x}=\begin{bmatrix}
a_{11}&a_{12}\\
a_{21}&a_{22}
\end{bmatrix}x+\begin{bmatrix}
b_{11}\\
b_{21}
\end{bmatrix}u.\]
\item Determine a feedback gain $K=(k1\ k2)$ that places the closed‑loop poles at \(-1\pm j1\).
\item The ball position $x_1$ can be measured using a photocell, but the velocity $x_2$ is more difficult to obtain. Therefore, suppose the output is $y=x_1$. Design a full-order observer $L = (l1\ l2)'$ having eigenvalues at $-5, -6$, and use the observer feedback to produce closed-loop eigenvalues at $-1\pm j1, -5, -6$.
\item Simulate your controller for the nonlinear model
\[
\ddot{y} = 1 -\frac{u^2}{y^2},
\]
with nominal equilibrium \(y_0=u_0=1\). With the initial condition $(x(0),\dot{x}(0))$ set as $(1,0)$ for the observer, you need to identify whether the following initial conditions $(x(0),\dot{x}(0))$ for the real system are within the region of asymptotic stability -- the set of initial states from which the closed‑loop system converges to the equilibrium. You need to use $1$ as yes and $0$ as no.
\begin{enumerate}
\item $(2, 2)$
\item $(2.5, 0)$
\item $(0.8, 0)$
\item $(0.9, -1)$
\end{enumerate}
\end{enumerate} | Liujun Xu |
JY_03 | 154 | Signal Processing | You are now working with polarization images.
Given the Raw image is shaped 100x100
you decided to create the AoLP and DoLP images with the same resolution( 100x100 ) as the original raw frame
However, after you gotten the frames, Degree0, Degree45, Degree90 and Degree135, Degree0 is corrupted, the pattern shown a checker board with alternating zeros.
You task is the following:
1, Given the array for Degree0.
Degree0 = [[229, 0, 195, 0, 209, 0, 199, 0, 193, 0, 194, 0, 201, 0, 188, 0, 203, 0, 181, 0, 195, 0, 187, 0, 135, 0, 79, 0, 35, 0, 22, 0, 14, 0, 10, 0, 43, 0, 58, 0, 73, 0, 72, 0, 75, 0, 105, 0, 137, 0], [0, 179, 0, 245, 0, 215, 0, 195, 0, 218, 0, 227, 0, 207, 0, 186, 0, 201, 0, 199, 0, 178, 0, 181, 0, 113, 0, 47, 0, 29, 0, 32, 0, 19, 0, 31, 0, 26, 0, 62, 0, 76, 0, 68, 0, 80, 0, 134, 0, 182], [197, 0, 191, 0, 211, 0, 222, 0, 197, 0, 195, 0, 188, 0, 227, 0, 177, 0, 199, 0, 211, 0, 227, 0, 158, 0, 59, 0, 22, 0, 30, 0, 23, 0, 31, 0, 18, 0, 50, 0, 56, 0, 89, 0, 69, 0, 113, 0, 160, 0], [0, 192, 0, 215, 0, 195, 0, 163, 0, 226, 0, 191, 0, 204, 0, 182, 0, 197, 0, 189, 0, 202, 0, 187, 0, 129, 0, 60, 0, 25, 0, 26, 0, 32, 0, 25, 0, 47, 0, 55, 0, 76, 0, 52, 0, 65, 0, 154, 0, 168], [182, 0, 187, 0, 211, 0, 207, 0, 198, 0, 211, 0, 193, 0, 197, 0, 220, 0, 183, 0, 213, 0, 171, 0, 131, 0, 88, 0, 34, 0, 29, 0, 15, 0, 26, 0, 30, 0, 44, 0, 73, 0, 51, 0, 36, 0, 120, 0, 156, 0], [0, 195, 0, 204, 0, 194, 0, 205, 0, 195, 0, 235, 0, 190, 0, 216, 0, 201, 0, 183, 0, 188, 0, 153, 0, 108, 0, 73, 0, 36, 0, 30, 0, 32, 0, 30, 0, 25, 0, 22, 0, 51, 0, 46, 0, 81, 0, 107, 0, 166], [199, 0, 200, 0, 194, 0, 209, 0, 216, 0, 216, 0, 195, 0, 197, 0, 198, 0, 215, 0, 193, 0, 174, 0, 112, 0, 93, 0, 56, 0, 21, 0, 25, 0, 25, 0, 23, 0, 21, 0, 22, 0, 36, 0, 78, 0, 103, 0, 134, 0], [0, 207, 0, 200, 0, 197, 0, 204, 0, 211, 0, 207, 0, 184, 0, 191, 0, 213, 0, 213, 0, 188, 0, 120, 0, 85, 0, 43, 0, 35, 0, 29, 0, 32, 0, 22, 0, 18, 0, 35, 0, 10, 0, 50, 0, 55, 0, 86, 0, 131], [186, 0, 220, 0, 214, 0, 204, 0, 195, 0, 209, 0, 210, 0, 201, 0, 188, 0, 183, 0, 207, 0, 187, 0, 113, 0, 85, 0, 43, 0, 34, 0, 39, 0, 13, 0, 28, 0, 27, 0, 55, 0, 23, 0, 40, 0, 62, 0, 101, 0], [0, 201, 0, 220, 0, 210, 0, 213, 0, 219, 0, 185, 0, 215, 0, 190, 0, 202, 0, 197, 0, 205, 0, 147, 0, 113, 0, 58, 0, 36, 0, 16, 0, 7, 0, 6, 0, 40, 0, 25, 0, 23, 0, 18, 0, 31, 0, 52, 0, 93], [189, 0, 182, 0, 193, 0, 186, 0, 201, 0, 222, 0, 195, 0, 203, 0, 193, 0, 197, 0, 207, 0, 185, 0, 139, 0, 88, 0, 36, 0, 25, 0, 17, 0, 6, 0, 19, 0, 28, 0, 13, 0, 15, 0, 13, 0, 58, 0, 92, 0], [0, 204, 0, 214, 0, 198, 0, 208, 0, 187, 0, 199, 0, 203, 0, 211, 0, 189, 0, 170, 0, 184, 0, 169, 0, 101, 0, 28, 0, 28, 0, 36, 0, 23, 0, 31, 0, 9, 0, 19, 0, 25, 0, 19, 0, 54, 0, 73, 0, 93], [217, 0, 209, 0, 206, 0, 181, 0, 202, 0, 210, 0, 193, 0, 183, 0, 188, 0, 174, 0, 184, 0, 175, 0, 135, 0, 86, 0, 36, 0, 47, 0, 46, 0, 24, 0, 21, 0, 13, 0, 27, 0, 44, 0, 43, 0, 67, 0, 77, 0], [0, 192, 0, 206, 0, 200, 0, 211, 0, 185, 0, 195, 0, 231, 0, 214, 0, 211, 0, 195, 0, 156, 0, 136, 0, 121, 0, 83, 0, 38, 0, 14, 0, 21, 0, 30, 0, 26, 0, 8, 0, 13, 0, 22, 0, 54, 0, 52, 0, 77], [207, 0, 204, 0, 216, 0, 192, 0, 226, 0, 184, 0, 216, 0, 206, 0, 186, 0, 198, 0, 200, 0, 147, 0, 147, 0, 115, 0, 77, 0, 28, 0, 6, 0, 23, 0, 36, 0, 40, 0, 31, 0, 22, 0, 26, 0, 46, 0, 67, 0], [0, 209, 0, 216, 0, 191, 0, 213, 0, 195, 0, 202, 0, 221, 0, 201, 0, 184, 0, 193, 0, 193, 0, 121, 0, 126, 0, 99, 0, 40, 0, 21, 0, 16, 0, 12, 0, 19, 0, 20, 0, 23, 0, 19, 0, 35, 0, 56, 0, 69], [213, 0, 215, 0, 204, 0, 217, 0, 204, 0, 203, 0, 216, 0, 208, 0, 202, 0, 172, 0, 189, 0, 129, 0, 134, 0, 118, 0, 52, 0, 31, 0, 15, 0, 11, 0, 15, 0, 15, 0, 29, 0, 11, 0, 39, 0, 54, 0, 47, 0], [0, 192, 0, 221, 0, 236, 0, 209, 0, 198, 0, 227, 0, 222, 0, 183, 0, 185, 0, 174, 0, 174, 0, 156, 0, 113, 0, 80, 0, 55, 0, 32, 0, 25, 0, 30, 0, 18, 0, 10, 0, 18, 0, 22, 0, 26, 0, 35, 0, 70], [223, 0, 206, 0, 204, 0, 195, 0, 172, 0, 221, 0, 205, 0, 188, 0, 209, 0, 192, 0, 202, 0, 185, 0, 170, 0, 109, 0, 67, 0, 30, 0, 23, 0, 25, 0, 14, 0, 35, 0, 27, 0, 25, 0, 25, 0, 31, 0, 56, 0], [0, 193, 0, 204, 0, 188, 0, 215, 0, 217, 0, 219, 0, 213, 0, 199, 0, 161, 0, 210, 0, 195, 0, 175, 0, 172, 0, 64, 0, 51, 0, 48, 0, 28, 0, 10, 0, 14, 0, 34, 0, 7, 0, 29, 0, 23, 0, 51, 0, 73], [206, 0, 195, 0, 208, 0, 191, 0, 232, 0, 208, 0, 171, 0, 221, 0, 184, 0, 213, 0, 201, 0, 183, 0, 178, 0, 144, 0, 81, 0, 51, 0, 42, 0, 14, 0, 21, 0, 25, 0, 18, 0, 13, 0, 34, 0, 30, 0, 63, 0], [0, 209, 0, 227, 0, 199, 0, 205, 0, 183, 0, 203, 0, 189, 0, 201, 0, 217, 0, 217, 0, 197, 0, 179, 0, 173, 0, 134, 0, 60, 0, 44, 0, 24, 0, 25, 0, 19, 0, 18, 0, 8, 0, 30, 0, 23, 0, 42, 0, 73], [255, 0, 224, 0, 211, 0, 194, 0, 201, 0, 215, 0, 222, 0, 213, 0, 195, 0, 205, 0, 211, 0, 185, 0, 193, 0, 163, 0, 99, 0, 60, 0, 34, 0, 32, 0, 28, 0, 23, 0, 18, 0, 19, 0, 35, 0, 29, 0, 44, 0], [0, 213, 0, 200, 0, 195, 0, 192, 0, 203, 0, 184, 0, 209, 0, 191, 0, 193, 0, 218, 0, 221, 0, 171, 0, 159, 0, 147, 0, 65, 0, 47, 0, 22, 0, 28, 0, 7, 0, 7, 0, 18, 0, 23, 0, 6, 0, 43, 0, 52], [194, 0, 217, 0, 190, 0, 227, 0, 209, 0, 195, 0, 211, 0, 193, 0, 190, 0, 237, 0, 204, 0, 207, 0, 175, 0, 172, 0, 147, 0, 80, 0, 25, 0, 28, 0, 14, 0, 18, 0, 16, 0, 28, 0, 27, 0, 18, 0, 32, 0], [0, 211, 0, 221, 0, 211, 0, 190, 0, 234, 0, 211, 0, 203, 0, 176, 0, 192, 0, 176, 0, 207, 0, 179, 0, 172, 0, 162, 0, 126, 0, 71, 0, 48, 0, 23, 0, 26, 0, 12, 0, 24, 0, 27, 0, 25, 0, 40, 0, 58], [197, 0, 205, 0, 219, 0, 211, 0, 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211, 0, 205, 0, 191, 0, 185, 0, 211, 0, 198, 0, 189, 0, 111, 0, 51, 0, 24, 0, 19, 0, 13, 0, 17, 0, 36, 0, 32, 0, 17, 0, 56], [187, 0, 215, 0, 214, 0, 194, 0, 202, 0, 234, 0, 187, 0, 219, 0, 200, 0, 217, 0, 224, 0, 218, 0, 203, 0, 193, 0, 167, 0, 150, 0, 56, 0, 29, 0, 13, 0, 26, 0, 24, 0, 26, 0, 10, 0, 13, 0, 38, 0], [0, 211, 0, 213, 0, 197, 0, 207, 0, 195, 0, 199, 0, 195, 0, 188, 0, 183, 0, 198, 0, 192, 0, 179, 0, 179, 0, 174, 0, 188, 0, 111, 0, 40, 0, 10, 0, 24, 0, 23, 0, 18, 0, 0, 0, 26, 0, 24, 0, 19], [216, 0, 211, 0, 197, 0, 206, 0, 220, 0, 202, 0, 195, 0, 193, 0, 205, 0, 222, 0, 202, 0, 188, 0, 189, 0, 181, 0, 168, 0, 137, 0, 99, 0, 35, 0, 21, 0, 32, 0, 17, 0, 23, 0, 15, 0, 25, 0, 13, 0], [0, 170, 0, 237, 0, 205, 0, 203, 0, 238, 0, 216, 0, 199, 0, 214, 0, 192, 0, 215, 0, 194, 0, 213, 0, 185, 0, 175, 0, 188, 0, 125, 0, 65, 0, 42, 0, 26, 0, 17, 0, 15, 0, 35, 0, 16, 0, 26, 0, 28], [197, 0, 207, 0, 230, 0, 187, 0, 191, 0, 195, 0, 198, 0, 195, 0, 192, 0, 206, 0, 199, 0, 183, 0, 221, 0, 179, 0, 171, 0, 161, 0, 96, 0, 60, 0, 35, 0, 18, 0, 27, 0, 13, 0, 27, 0, 14, 0, 23, 0], [0, 206, 0, 220, 0, 215, 0, 222, 0, 218, 0, 195, 0, 214, 0, 205, 0, 215, 0, 197, 0, 195, 0, 205, 0, 185, 0, 195, 0, 172, 0, 152, 0, 91, 0, 31, 0, 18, 0, 12, 0, 36, 0, 15, 0, 30, 0, 28, 0, 31], [219, 0, 234, 0, 224, 0, 188, 0, 211, 0, 195, 0, 188, 0, 178, 0, 185, 0, 205, 0, 225, 0, 216, 0, 221, 0, 195, 0, 175, 0, 179, 0, 146, 0, 64, 0, 31, 0, 28, 0, 25, 0, 27, 0, 14, 0, 3, 0, 36, 0], [0, 206, 0, 237, 0, 184, 0, 184, 0, 204, 0, 214, 0, 234, 0, 178, 0, 187, 0, 211, 0, 204, 0, 189, 0, 187, 0, 189, 0, 208, 0, 165, 0, 107, 0, 46, 0, 28, 0, 26, 0, 17, 0, 22, 0, 24, 0, 17, 0, 15], [218, 0, 195, 0, 210, 0, 199, 0, 188, 0, 203, 0, 200, 0, 221, 0, 201, 0, 179, 0, 189, 0, 189, 0, 187, 0, 170, 0, 187, 0, 163, 0, 146, 0, 69, 0, 39, 0, 10, 0, 13, 0, 10, 0, 17, 0, 22, 0, 31, 0], [0, 208, 0, 199, 0, 218, 0, 222, 0, 207, 0, 201, 0, 215, 0, 184, 0, 170, 0, 162, 0, 191, 0, 162, 0, 178, 0, 198, 0, 191, 0, 179, 0, 121, 0, 38, 0, 26, 0, 1, 0, 17, 0, 21, 0, 13, 0, 11, 0, 32], [229, 0, 184, 0, 203, 0, 186, 0, 194, 0, 203, 0, 207, 0, 208, 0, 195, 0, 170, 0, 197, 0, 149, 0, 168, 0, 157, 0, 162, 0, 176, 0, 147, 0, 60, 0, 17, 0, 18, 0, 12, 0, 24, 0, 13, 0, 30, 0, 19, 0], [0, 200, 0, 201, 0, 188, 0, 233, 0, 216, 0, 184, 0, 195, 0, 178, 0, 157, 0, 179, 0, 154, 0, 105, 0, 125, 0, 137, 0, 163, 0, 143, 0, 65, 0, 52, 0, 36, 0, 7, 0, 27, 0, 22, 0, 29, 0, 26, 0, 14], [227, 0, 195, 0, 211, 0, 201, 0, 199, 0, 195, 0, 199, 0, 176, 0, 151, 0, 147, 0, 162, 0, 129, 0, 121, 0, 113, 0, 117, 0, 116, 0, 131, 0, 62, 0, 19, 0, 24, 0, 27, 0, 18, 0, 40, 0, 16, 0, 12, 0], [0, 200, 0, 217, 0, 204, 0, 222, 0, 179, 0, 188, 0, 189, 0, 190, 0, 117, 0, 121, 0, 142, 0, 116, 0, 71, 0, 105, 0, 110, 0, 112, 0, 94, 0, 68, 0, 32, 0, 19, 0, 29, 0, 11, 0, 11, 0, 15, 0, 26], [220, 0, 163, 0, 190, 0, 224, 0, 209, 0, 203, 0, 165, 0, 203, 0, 160, 0, 119, 0, 121, 0, 123, 0, 75, 0, 109, 0, 84, 0, 80, 0, 83, 0, 63, 0, 21, 0, 29, 0, 23, 0, 23, 0, 15, 0, 10, 0, 19, 0], [0, 203, 0, 188, 0, 211, 0, 220, 0, 211, 0, 183, 0, 200, 0, 171, 0, 131, 0, 85, 0, 97, 0, 107, 0, 77, 0, 85, 0, 70, 0, 92, 0, 67, 0, 69, 0, 21, 0, 13, 0, 16, 0, 13, 0, 16, 0, 27, 0, 22], [199, 0, 198, 0, 209, 0, 216, 0, 189, 0, 171, 0, 193, 0, 185, 0, 139, 0, 99, 0, 59, 0, 84, 0, 63, 0, 60, 0, 62, 0, 73, 0, 63, 0, 51, 0, 52, 0, 22, 0, 0, 0, 23, 0, 25, 0, 21, 0, 13, 0], [0, 189, 0, 201, 0, 206, 0, 218, 0, 195, 0, 155, 0, 125, 0, 113, 0, 83, 0, 52, 0, 58, 0, 60, 0, 36, 0, 48, 0, 42, 0, 59, 0, 65, 0, 44, 0, 17, 0, 15, 0, 2, 0, 25, 0, 27, 0, 25, 0, 22]]
2, Design a mathematical kernel that mimics linear interpolation to fill the values that is zero for the Degree0, make sure the center of the kernel is 1
3, the Aolp and DoLP image will also be tested as a metrics to the kernel score
| Jiankun Yang |
NS_PA_SS_09 | 222 | Digital Hardware Design | You are a hardware‐design expert. Write synthesizable SystemVerilog for a parameterized Gray‐to‐binary converter that maps an N-bit Gray code value to its binary index, according to the following spec:
1. Parameterization
- parameter WIDTH = 8;
2. Ports
```verilog
module model #(
parameter WIDTH = 8
) (
input logic [WIDTH-1:0] gray, // N-bit Gray code input
output logic [WIDTH-1:0] bin // N-bit binary index output
);
Behavior
Combinational conversion:
bin[WIDTH-1] = gray[WIDTH-1];
For i from WIDTH-2 down to 0:
bin[i] = bin[i+1] ^ gray[i];
No clock or reset—purely combinational logic.
Implementation notes
You may use a generate–for loop or bitwise reduction to implement the XOR cascade.
Ensure fully synthesizable, zero-latency logic.
Please produce clean, commented, synthesizable SystemVerilog that meets this specification. | Nippun Sabharwal, Shreyanka Sinha, Prakhar Agarwal |
YX_03 | 2,304 | Signal Processing | ## Task Description
In this task, you should evaluate the detection performance of an S-band radar system operating at 3 GHz. Across 14 tasks, you will calculate key metrics such as available and required SNR, integration gain, fluctuation loss, MTI and CFAR losses, beam and scan-related losses, and the overall effective detectability factor. Results should be expressed in dB or km with proper rounding and error estimation.
### Task 1
Given an S-band airport surveillance radar operating at the frequency of 3 GHz. The peak transmit power is 0.2 MW, the transmit and receive antenna gain is 34 dB, the pulse duration is 11 microseconds, and the noise figure is 4.1 dB. Assume the radar is required to detect a target with 1 m^2 RCS at the maximum range R_m of 100 km. Assume no losses, that is L = 0 dB. Calculate the available SNR at the required maximum range of 100 km.
Express the result in dB, and please specify the absolute error you believe exists between your result and the standard answer. Retain two decimal places. Round your result instead of truncating.
### Task 2
Compute the required SNR for a single pulse received from a steady target by a square-law detector, assuming the desired probability of detection Pd = 0.9 and the maximum acceptable probability of false alarm Pfa = 1e-6.
Express the result in dB, and please specify the absolute error you believe exists between your result and the standard answer. Retain two decimal places. Round your result instead of truncating.
### Task 3
Assuming Pd = 0.9 and Pfa = 1e-6, calculate the required SNR for a single pulse received from a Swerling 1 fluctuating target.
Express the result in dB, and please specify the absolute error you believe exists between your result and the standard answer. Retain two decimal places. Round your result instead of truncating.
### Task 4
To lower the detectability factor, we can perform pulse integration. Calculate the required SNR for N = 10 noncoherently integrated pulses received from a Swerling 1 fluctuating target, assuming Pd = 0.9 and Pfa = 1e-6.
Express the result in dB, and please specify the absolute error you believe exists between your result and the standard answer. Retain two decimal places. Round your result instead of truncating.
### Task 5
The integration gain is the difference between the SNR required to detect a steady target using a single pulse and the SNR required to detect a steady target using N pulses. Given Pd = 0.9 and Pfa = 1e-6, N = 10, calculate the integration gain.
Express the result in dB, and please specify the absolute error you believe exists between your result and the standard answer. Retain two decimal places. Round your result instead of truncating.
### Task 6
The fluctuation loss is the difference between the SNR required to detect a fluctuating target and the SNR required to detect a steady target. Given Pd = 0.9 and Pfa = 1e-6, using 10 pulses, calculate the fluctuation loss.
Express the result in dB, and please specify the absolute error you believe exists between your result and the standard answer. Retain two decimal places. Round your result instead of truncating.
### Task 7
Using your result of Task 4 as the minimum required SNR, and the same conditions as in Task 1 (An S-band airport surveillance radar is operating at the frequency of 3 GHz. The peak transmit power is 0.2 MW, the transmit and receive antenna gain is 34 dB, the pulse duration is 11 microseconds, and the noise figure is 4.1 dB. The radar is required to detect a target with 1 m^2 RCS.), evaluate the actual maximum range of the system.
Express the result in km, and please specify the absolute error you believe exists between your result and the standard answer. Retain two decimal places. Round your result instead of truncating.
### Task 8
Pulse radar systems turn off their receivers during the pulse transmission. Thus, the target echoes arriving from the ranges within one pulse length from the radar or within one pulse length around the unambiguous range will be eclipsed by the transmitted pulse resulting in only a fraction of the pulse being received and processed.
Given the radar system with the pulse width of 11 microseconds, calcuate the closest range from which a full pulse can be received, Rmin.
Express the result in km, and please specify the absolute error you believe exists between your result and the standard answer. Retain two decimal places. Round your result instead of truncating.
### Task 9
Eclipsing effect can also be observed for the targets located at or near the multiples of the unambiguous range. Assuming the pulse repetition frequency is 1350 Hz, calculate the unambiguous range of the system.
Express the result in km, and please specify the absolute error you believe exists between your result and the standard answer. Retain two decimal places. Round your result instead of truncating.
### Task 10
Assume the radar system employs an electronically steered phased array to perform scanning. Using the phased array antenna will cause an increase in the required SNR due to two effects: 1. beam broadening due to the reduced projected array area in the beam direction, and 2. reduction of the effective aperture area of the individual array elements at off-broadside angles. To account for these effects, add the scan sector loss to the detectability factor. Assume that the system scans only in the azimuth dimension and the scan sector spans from –60 to 60 degrees. Assume the target is a fluctuating target. Given Pd = 0.9 and Pfa = 1e-6, N = 10, compute the resultant loss.
Express the result in dB, and please specify the absolute error you believe exists between your result and the standard answer. Retain four decimal places. Round your result instead of truncating.
### Task 11
Moving target indicator (MTI) is a process of rejecting fixed or slowly moving clutter while passing echoes from targets moving with significant velocities. Typical MTI uses 2, 3, or 4-pulse canceller that implements a high-pass filter to reject echoes with low Doppler shifts. Passing the received signal through the MTI pulse canceller introduces correlation between the noise samples. This in turn reduces the total number of independent noise samples available for integration, resulting in MTI noise correlation loss. Additionally, the MTI canceller significantly suppresses targets with velocities close to the nulls of its frequency response, causing an additional MTI velocity response loss.
Assume the target is a fluctuating target. Given Pd = 0.9 and Pfa = 1e-6, N = 10. Assuming a 2-pulse canceller is used, calculate these two components of the MTI loss, the MTI noise correlation loss Lmti_a and the MTI velocity response loss Lmti_b.
Express the result in dB, and please specify the absolute error you believe exists between your result and the standard answer. Retain four decimal places. Round your result instead of truncating.
### Task 12
Binary integration is a suboptimal noncoherent integration technique also known as the M-of-N integration. If M out of N received pulses exceed a predetermined threshold, a target is declared to be present. The binary integrator is a relatively simple automatic detector and is less sensitive to the effects of a single large interference pulse that might exist along with the target echoes. Therefore, the binary integrator is more robust when the background noise or clutter is non-Gaussian. Since the binary integration is a suboptimal technique, it results in a binary integration loss compared to optimal noncoherent integration. The optimal value of M is not a sensitive selection and it can be quite different from the optimum without significant penalty resulting in the binary integration loss being lower than 1.4 dB.
Given Pd = 0.9 and Pfa = 1e-6. Calculate the binary integration loss when N is 10 and M is set to 6.
Express the result in dB, and please specify the absolute error you believe exists between your result and the standard answer. Retain four decimal places. Round your result instead of truncating.
### Task 13
Constant false alarm rate (CFAR) detector is used to maintain an approximately constant rate of false target detections when the noise or the interference levels vary. Since CFAR averages a finite number of reference cells to estimate the noise level, the estimates are subject to an error which leads to a CFAR loss. CFAR loss is an increase in the SNR required to achieve a desired detection performance using CFAR when the noise levels are unknown compared to a fixed threshold with a known noise level.
Calculate the CFAR loss assuming that Pfa = 1e-6 and total 120 cells are used for cell-averaging CFAR.
Express the result in dB, and please specify the absolute error you believe exists between your result and the standard answer. Retain four decimal places. Round your result instead of truncating.
### Task 14
The detectability factor reflects the minimum SNR required to detect a target under ideal conditions. However, practical radar systems experience additional signal processing and scanning losses.
Using the baseline detectability factor for a steady target with a single pulse from Task 2, and incorporating the following computed components:
- Integration gain (Task 5)
- Fluctuation loss (Task 6)
- Beam shape loss = 1.2338 dB
- Scan sector loss (Task 10)
- MTI noise correlation loss and velocity response loss (Task 11)
- Binary integration loss (Task 12)
- CFAR loss (Task 13)
Calculate the effective detectability factor by appropriately adjusting the baseline with gains and adding all losses.
Express the result in dB, and please specify the absolute error you believe exists between your result and the standard answer. Retain two decimal places. Round your result instead of truncating.
### Task 15
Based on the effective detectability factor calculated in Task 14, evaluate whether the radar system described in Task 1 — an S-band airport surveillance radar operating at 3 GHz with 0.2 MW peak transmit power, 34 dB antenna gain (Tx/Rx), 11 microseconds pulse duration, and a 4.1 dB noise figure — is capable of detecting a 1 m^2 RCS target at 100 km with Pd = 0.9 and Pfa = 1e-6.
Compare the available SNR from Task 1 with the required detectability factor from Task 14, and conclude whether the system satisfies the performance requirement.
If the system meets the requirement, return 1; if it does not, return 0.
| Yaxin Li |
XG_13 | 273 | Control Design | ## Background
Control systems play a critical role in stabilizing and regulating the behavior of dynamic systems, such as robotic arms and autonomous vehicles. In this task, you will design a proportional-integral-derivative (PID) controller for a mass-spring-damper system. The system is described by the following physical parameters:
- Mass: $m = 1\, \text{kg}$
- Damping coefficient: $b = 10\, \text{N s/m}$
- Spring constant: $k = 20\, \text{N/m}$
- External force: $F = 1\, \text{N}$
An illustrative diagram is provided to help visualize the system.
## Task Description
Please design a PID controller for the given mass-spring-damper system, such that the closed-loop system satisfies the following performance requirements:
- **Settling time:** $T_s < 0.2\, \text{seconds}$
- **Overshoot:** $M_p < 5\%$
- **Steady-state error:** Zero
**Note:** You may choose to implement a simplified controller by setting one or more of the PID parameters (i.e., $K_i$ or $K_d$) to zero, effectively designing a PI, PD, or P controller as needed.
| Xingang Guo |
XG_07 | 1,361 | Control Design | ## Task Description
In this task, you are required to design a H-infinity controller for an active suspension system using hinfsyn command in MATLAB in robust control toolbox. Conventional passive suspensions use a spring and damper between the car body and wheel assembly. The spring-damper characteristics are selected to emphasize one of several conflicting objectives such as passenger comfort, road handling, and suspension deflection. Active suspensions allow the designer to balance these objectives using a feedback-controller hydraulic actuator between the chassis and wheel assembly. In this task, we use a quarter-car model of the active suspension system (see in the attached figure). The mass m_b (in kilograms) represents the car chassis (body) and the mass m_w (in kilograms) represents the wheel assembly. The spring k_s and damper b_s represent the passive spring and shock absorber placed between the car body and the wheel assembly. The spring k_t models the compressibility of the pneumatic tire. The variables x_b, x_w, and r (all in meters) are the body travel, wheel travel, and road disturbance, respectively. The force f_s (in kiloNewtons) applied between the body and wheel assembly is controlled by feedback and represents the active component of the suspension system.
### Task 1
With the state vector: (x_1, x_2, x_3, x_4) = (x_b, \dot{x}_b, x_w, \dot{x}_w), the linearlized state-space model of the quarter-car active suspension system is given by:
\begin{equation}
\dot{x}_1 &= x_2
\dot{x}_2 &= -(1/m_b)(k_s(x_1-x_3)+b_s(x_2-x_4)-10^3f_s)
\dot{x}_3 &= x_4
\dot{x}_4 &= (1/m_w)(k_s(x_1-x_3)+b_s(x_2-x_4)-k_t(x_3-r)-10^3f_s)
\end{equation}
Your first task is to derive the numerical values of the state space matrices (A, B) using the above equations with the following parameters:
- m_b = 300 kg
- m_w = 60 kg
- k_s = 16000 N/m
- b_s = 1000 N/m/s
- k_t = 190000 N/m
### Task 2
Your second task is to design a H-infinity controller for the active suspension system using hinfsyn command in MATLAB in robust control toolbox. Consider that the state space matrices are given as (A, B, C, D) with A and B defined in Task 1 and C and D defiend as:
C = [1 0 0 0; 1 0 -1 0; A(2,:)];
D = [0 0; 0 0; B(2,:)];
The following MATLAB code is given to you as a baseline assuming the correct state space matrices:
<code_block>
qcar = ss(A,B,C,D);
qcar.StateName = {'body travel (m)';'body vel (m/s)';...
'wheel travel (m)';'wheel vel (m/s)'};
qcar.InputName = {'r';'fs'};
qcar.OutputName = {'xb';'sd';'ab'};
% Nominal Actuator dynamics
ActNom = tf(1,[1/60 1]);
ActNom.InputName = 'u';
ActNom.OutputName = 'fs';
%% Design Setup
Wroad = ss(0.07);
Wroad.u = 'd';
Wroad.y = 'r';
Wact = 0.8*tf([1 50],[1 500]);
Wact.u = 'u';
Wact.y = 'e1';
HandlingTarget = 0.04 * tf([1/8 1],[1/80 1]);
ComfortTarget = 0.4 * tf([1/0.45 1],[1/150 1]);
beta = 0.01;
Wsd = beta/HandlingTarget;
Wsd.u = 'sd';
Wsd.y = 'e3';
Wab = (1-beta)/ ComfortTarget;
Wab.u = 'ab';
Wab.y = 'e2';
%% Apply Design using hinfsyn
sdmeas = sumblk('y1 = sd');
abmeas = sumblk('y2 = ab');
ICinputs = {'d';'u'};
ICoutputs = {'e1';'e2';'e3';'y1';'y2'};
qcaric = connect(qcar,ActNom,Wroad,Wact,Wab,Wsd,sdmeas,abmeas,ICinputs,ICoutputs);
ncont = 1; % one control signal, u
nmeas = 2; % two measurement signals, sd and ab
K = ss(zeros(ncont,nmeas));
[K,~,gamma] = hinfsyn(qcaric,nmeas,ncont);
K.u = {'sd','ab'}; K.y = 'u';
CL = connect(qcar,ActNom,K,'r',{'xb';'sd';'ab'});
% Road disturbance
t = 0:0.0025:1;
roaddist = zeros(size(t));
roaddist(1:101) = 0.025*(1-cos(8*pi*t(1:101)));
% Simulate
p1 = lsim(qcar(:,1),roaddist,t);
y1 = lsim(CL,roaddist,t);
% Performance Metrics
rms_closed = rms(y1(:,1));
peak_closed = max(abs(y1(:,1)));
energy_open = trapz(t, p1(:,1).^2);
energy_closed = trapz(t, y1(:,1).^2);
attenuation_ratio = energy_closed / energy_open;
</code_block>
With correct A and B matrices, it achieves the following performance:
- RMS of the body travel: 0.014 m
- Peak of the body travel: 0.0309 m
- Energy Attenuation: 57.23%
Please choose another beta parameter between 0 and 1 in the Design Setup section of the baseline MATLAB code to achieve the following performance requirements:
- RMS body travel ≤ 0.012m
- Peak body travel ≤ 0.035m
- Energy attenuation ≤ 35% | Xingang Guo |
XW_02 | 1,241 | Operating System Design | ## Task Description
In this task, you will be provided with a filesystem image. You are required to develop separate programs—each implementing a different filesystem operation (e.g., create, read, update, delete)—to modify the corresponding sections of that image. Your objective is to ensure that each program correctly performs its assigned operation on the intended part of the filesystem image while preserving its overall integrity.
Here is the class definition for your reference:
from dataclasses import dataclass, field
from typing import List, Dict, Optional
@dataclass
class SuperBlock:
"""File system superblock, stores metadata."""
block_size: int # Size of each block (bytes)
total_blocks: int # Total number of blocks
inode_count: int # Total number of inodes
free_block_bitmap: List[bool] # Free block bitmap, True = free
@dataclass
class Inode:
"""Inode structure, stores file/directory metadata."""
ino: int # Inode number
is_dir: bool # Whether this inode is a directory
size: int # File size (bytes)
direct_blocks: List[int] # List of direct block indices
# Optional: add indirect block pointers, multi-level indexing, permissions, timestamps, etc.
@dataclass
class DirEntry:
"""Directory entry: maps a filename to an inode."""
name: str
inode: int
@dataclass
class FileSystemImage:
"""Complete file system image structure."""
superblock: SuperBlock
inodes: Dict[int, Inode] = field(default_factory=dict)
# Directory tree: inode -> list of entries in that directory; valid only for is_dir=True inodes
directories: Dict[int, List[DirEntry]] = field(default_factory=dict)
# Data block storage area: index corresponds to block number, content is bytes
data_blocks: List[Optional[bytes]] = field(default_factory=list)
def __post_init__(self):
# Initialize data block storage area
if not self.data_blocks:
self.data_blocks = [None] * self.superblock.total_blocks
def allocate_block(self) -> int:
"""Allocate a block from the free bitmap and return its index; raise if none available."""
for idx, free in enumerate(self.superblock.free_block_bitmap):
if free:
self.superblock.free_block_bitmap[idx] = False
self.data_blocks[idx] = b'' # Initialize with empty content
return idx
raise RuntimeError("No free blocks available")
def free_block(self, block_idx: int):
"""Free the specified block index."""
if 0 <= block_idx < self.superblock.total_blocks:
self.superblock.free_block_bitmap[block_idx] = True
self.data_blocks[block_idx] = None
else:
raise IndexError("Block index out of range")
def create_inode(self, is_dir: bool) -> Inode:
"""Create a new inode and return it."""
new_ino = len(self.inodes) + 1
if new_ino > self.superblock.inode_count:
raise RuntimeError("No free inodes")
inode = Inode(
ino=new_ino,
is_dir=is_dir,
size=0,
direct_blocks=[]
)
self.inodes[new_ino] = inode
if is_dir:
self.directories[new_ino] = []
return inode
def add_dir_entry(self, dir_ino: int, name: str, inode: int):
"""Add a directory entry to the directory with inode dir_ino."""
if dir_ino not in self.directories:
raise RuntimeError("Not a directory inode")
self.directories[dir_ino].append(DirEntry(name=name, inode=inode))
### Task 1
def write(fs_img: FileSystemImage, name: str, pos: int, data: str) -> FileSystemImage:
"""
Write the UTF‑8 encoded bytes of `data` into the file called `name`
in the given FileSystemImage, starting at byte offset `pos`. Return
the updated FileSystemImage so that its blocks and inode metadata
can be inspected for correctness.
Parameters:
- fs_img: the FileSystemImage instance containing inodes, directories,
and data blocks.
- name: an absolute or relative path to the target file within `fs_img`.
- pos: the byte offset within the file at which to begin writing.
- data: a Python string whose UTF‑8 encoding will be written.
Returns:
- The same FileSystemImage instance (`fs_img`), mutated to reflect the
writes (updated data_blocks and inode.size).
Behavior:
1. If the file `name` does not exist or refers to a directory, raise
`FileNotFoundError` or `IsADirectoryError` respectively.
2. If `pos` is negative or greater than the file’s current size, raise
`ValueError`.
3. Encode `data` as UTF‑8 bytes.
4. If writing beyond the current end of file, extend the file:
- Allocate new blocks via `fs_img.allocate_block()` as needed.
- Update the inode’s `direct_blocks` list accordingly.
5. Compute which blocks and byte‐ranges within them correspond to
the target file range `[pos, pos + len(bytes))`.
6. Overwrite or append bytes in `fs_img.data_blocks[block_idx]` per block.
7. Update the inode’s `size` to `max(old_size, pos + len(bytes))`.
8. Return the mutated `fs_img` so that test harnesses can inspect
its `data_blocks` and `inodes` for correctness.
"""
| Licheng Xu, Jinwen Wang |
Ziheng_03 | 209 | Control Design | ## Task Description
You need to design a PID controller for a magnetic levitation system in which an electromagnet holds a steel ball at a desired height. Near the operating point, the nonlinear dynamics can be linearized and modeled by the transfer function:
G = K / ((tau1*s + 1)*(tau2*s + 1)*(tau3*s + 1));
where:
K = 1;
tau1 = 0.5;
tau2 = 1.0;
tau3 = 2.0;
Design a PID controller so that the closed‑loop system meets all of the following specifications:
1. Settling time Ts (to within plus or minus 5 percent) < 5s
2. Overshoot < 20 percent
3. Zero steady state error to a unit step input
4. Gain margin > 10dB
5. Phase margin > 45 degrees
## Output format
You need to give me your Kp, Ki, and Kd in numerical form.
| Ziheng Guo |
XG_09 | 780 | Signal Processing | ## Task Description
In this task, you will use fuzzy logic to process an image for edge detection. An edge is a boundary between two uniform regions. You can detect an edge by comparing the intensity of neighboring pixels. However, because uniform regions are not crisply defined, small intensity differences between two neighboring pixels do not always represent an edge. Instead, the intensity difference might represent a shading effect. The fuzzy logic approach for image processing allows you to use membership functions to define the degree to which a pixel belongs to an edge or a uniform region. Here is a baseline code:
<code>
% Import the image.
Irgb = imread('peppers.png');
% Convert to 2-D array
Igray = rgb2gray(Irgb);
% Convert image to double-precision data
I = im2double(Igray);
% Obtain Image gradient
Gx = [-1 1];
Gy = Gx';
Ix = conv2(I,Gx,'same');
Iy = conv2(I,Gy,'same');
% Define Fuzzy Inference System (FIS) for Edge Detection
edgeFIS = mamfis('Name','edgeDetection');
edgeFIS = addInput(edgeFIS,[-1 1],'Name','Ix');
edgeFIS = addInput(edgeFIS,[-1 1],'Name','Iy');
% zero-mean Gaussian membership function for each input
sx = 0.01;
sy = 0.01;
edgeFIS = addMF(edgeFIS,'Ix','gaussmf',[sx 0],'Name','zero');
edgeFIS = addMF(edgeFIS,'Iy','gaussmf',[sy 0],'Name','zero');
% Specify the intensity of the edge-detected image as an output of edgeFIS
edgeFIS = addOutput(edgeFIS,[0 1],'Name','Iout');
% Specify the triangular membership functions, white and black, for Iout
wa = 0.5;
wb = 0.5;
wc = 1;
ba = 0.5;
bb = 0.5;
bc = 0.7;
edgeFIS = addMF(edgeFIS,'Iout','trimf',[wa wb wc],'Name','white');
edgeFIS = addMF(edgeFIS,'Iout','trimf',[ba bb bc],'Name','black');
% Specify FIS Rules
r1 = "If Ix is zero and Iy is zero then Iout is white";
r2 = "If Ix is not zero or Iy is not zero then Iout is black";
edgeFIS = addRule(edgeFIS,[r1 r2]);
edgeFIS.Rules
% Evaluate FIS
Ieval = zeros(size(I));
for ii = 1:size(I,1)
Ieval(ii,:) = evalfis(edgeFIS,[(Ix(ii,:));(Iy(ii,:))]');
end
</code>
We will use three main evaluation metrics to evaluate the edge detection performance:
1. MSE between the edge detection result and the ground truth edge map
2. PSNR between the edge detection result and the ground truth edge map
3. SSIM between the edge detection result and the ground truth edge map
In the evaluation, the Canny edge detector is used as the pseudo-ground-truth. The above baselinecode achieves:
MSE: 0.5958
PSNR: 2.25 dB
SSIM: 0.0366
Now your task is to tune the parameters of the membership functions (i.e., sx, sy, wa, wb, wc, ba, bb, bc) to improve the edge detection performance and achieve the following metrics:
MSE < 0.5
PSNR > 3 dB
SSIM > 0.05
The gray scale image for edge detection is given to you below for your reference:
234 197 199 202 202 202 204 207 211 210 212 211 212 212 208 208 207 208 207 207 208 208 209 208 206 204 206 207 207 208 207 207 207 210 211 211 213 214 214 212 212 213 214 212 210 209 208 207 206 208 208 206 206 206 207 207 206 208 209 213 213 211 215 241
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198 47 53 53 52 54 62 79 86 85 87 86 88 90 91 86 84 87 90 92 94 93 90 88 81 73 78 82 84 89 93 95 97 100 104 107 108 110 109 99 98 104 103 102 99 97 96 98 97 98 95 84 74 75 82 78 74 78 85 94 98 102 115 218
202 47 51 54 52 49 56 75 80 82 83 84 87 91 89 82 81 85 90 91 90 88 88 88 78 72 78 82 83 88 93 93 94 99 104 105 107 109 106 97 97 104 101 99 98 96 95 97 95 93 88 81 73 69 77 74 73 75 77 89 93 95 110 218
201 49 53 50 49 46 52 71 76 78 79 80 84 88 87 81 80 85 90 91 90 88 86 86 76 72 78 82 82 86 90 90 92 95 100 101 105 107 104 96 93 99 96 95 96 95 94 95 92 89 85 80 74 70 74 67 66 68 73 85 89 90 105 218
201 50 54 50 49 44 51 68 73 77 78 80 84 88 87 82 81 86 91 90 91 87 86 87 81 73 78 83 82 82 86 87 89 91 95 97 101 101 101 94 88 95 93 92 93 92 91 90 89 89 84 79 70 68 76 66 63 63 70 81 86 88 98 216
201 51 52 48 47 44 50 66 71 76 78 82 86 90 89 83 85 89 93 96 113 122 130 143 144 134 125 119 109 99 87 82 82 83 88 91 96 98 96 90 83 91 89 88 90 89 87 86 85 85 82 76 65 65 75 68 63 62 68 77 84 84 89 213
203 52 50 45 43 42 45 64 72 76 82 85 88 91 94 89 86 92 98 117 139 166 177 187 189 189 185 186 182 191 147 88 77 76 80 85 92 95 91 86 79 89 89 87 89 87 83 83 81 79 77 74 59 61 74 67 63 62 67 75 79 83 88 213
204 56 51 46 42 41 44 65 75 78 85 89 93 94 95 85 88 98 115 128 141 149 161 173 182 188 194 195 200 206 211 177 107 71 68 75 86 93 87 83 78 89 88 88 89 86 82 81 78 76 74 71 54 60 72 67 59 59 66 71 74 82 84 211
205 57 54 49 43 39 42 63 76 81 89 96 97 104 95 101 124 121 124 136 152 149 163 175 182 189 191 194 195 197 212 219 212 168 102 73 85 87 86 82 77 88 88 88 89 86 83 79 75 72 73 70 55 59 70 64 56 56 61 67 71 79 79 209
206 59 56 51 43 40 44 65 79 85 95 101 110 100 107 118 69 53 80 118 130 128 141 159 176 180 182 182 183 187 199 206 215 218 211 149 82 81 84 82 74 85 88 88 87 86 84 83 78 74 72 68 57 57 66 60 54 54 58 63 67 76 81 210
205 61 58 53 46 41 48 71 82 91 99 106 87 94 103 40 39 86 104 103 103 107 131 144 143 156 166 166 157 170 188 195 199 201 211 212 122 77 82 79 70 82 85 85 85 84 85 86 80 77 71 66 58 57 63 59 52 52 56 59 64 75 77 209
205 63 62 55 50 45 51 76 87 94 103 82 82 115 68 79 103 133 156 136 85 97 132 155 155 158 162 166 162 168 179 197 203 200 209 209 133 80 80 80 72 83 87 87 88 86 88 90 79 72 68 66 59 58 62 60 58 55 54 57 62 73 73 207
205 65 64 56 53 47 54 81 94 101 87 58 119 142 156 143 112 124 154 128 84 98 134 157 165 175 179 182 181 185 186 196 201 208 209 217 155 86 83 81 72 84 90 90 91 89 91 91 80 72 66 64 60 59 62 59 58 56 57 60 64 73 71 205
208 68 66 58 54 50 59 88 103 101 48 94 164 172 161 142 112 115 144 110 80 91 137 154 164 180 186 189 189 187 189 193 194 204 220 212 206 119 82 85 73 79 87 90 91 89 91 90 83 76 69 62 56 59 65 59 54 53 57 60 63 72 73 207
208 73 68 59 55 52 63 92 109 63 63 144 145 121 124 105 99 123 144 124 85 97 134 153 161 166 180 194 194 191 190 187 190 199 218 216 212 171 91 89 74 82 90 92 94 92 93 90 86 76 69 60 51 58 69 60 54 53 56 58 61 70 72 207
210 77 70 61 58 58 68 103 97 43 115 148 139 143 117 100 102 134 158 134 94 89 128 149 166 168 182 193 191 190 189 194 191 197 212 213 206 167 100 91 78 81 91 95 97 96 98 93 88 74 67 61 52 56 68 59 56 54 56 57 60 67 69 207
212 81 74 65 63 65 72 112 70 71 132 124 111 88 100 94 94 133 156 146 107 89 115 153 161 171 175 191 191 185 189 195 199 196 205 211 210 150 102 93 79 85 91 98 101 98 97 92 87 78 71 64 57 56 67 59 57 54 55 55 58 64 64 206
213 87 78 69 68 69 78 102 52 115 90 93 87 96 108 81 81 102 145 152 120 96 113 142 147 138 135 148 187 196 191 188 192 201 205 213 220 191 126 91 82 84 92 99 101 102 98 95 87 80 76 69 62 57 67 60 56 54 53 52 56 62 62 205
214 92 82 71 69 72 79 70 88 106 73 82 80 108 95 66 57 80 132 124 103 88 104 134 120 63 52 80 146 197 201 203 201 200 216 209 223 213 169 106 82 85 94 101 103 104 100 98 86 79 74 67 61 58 65 59 58 57 54 52 55 60 61 204
214 99 85 71 69 76 72 89 90 65 80 65 88 79 65 55 50 81 103 97 113 79 76 119 143 100 89 87 108 163 194 200 191 142 149 213 221 221 183 118 86 89 98 105 107 107 104 98 88 81 73 66 60 57 63 59 57 55 53 53 56 61 63 205
216 104 89 75 74 80 73 100 72 55 77 73 54 78 70 56 67 70 89 104 117 80 85 118 115 78 82 97 106 102 180 184 142 63 42 150 219 221 204 131 86 89 103 108 111 112 108 99 89 83 73 66 60 55 62 59 56 52 52 53 58 62 64 206
219 104 88 74 78 81 75 112 80 50 79 67 23 34 49 50 48 68 88 112 118 103 130 123 64 27 83 105 121 113 175 140 89 60 52 113 211 215 216 184 121 99 104 109 113 118 114 103 91 86 77 71 62 57 64 59 56 52 51 54 57 62 63 205
218 105 88 71 79 78 82 119 90 49 101 77 29 45 29 30 35 57 64 94 116 144 155 132 117 125 166 170 146 140 196 166 86 47 80 167 217 207 210 208 148 107 108 113 117 119 116 106 98 92 83 74 63 56 59 59 56 52 53 55 58 63 65 205
217 106 89 73 78 82 81 96 72 59 118 100 37 42 12 29 46 41 45 58 92 153 157 160 149 140 142 155 163 142 181 199 155 157 135 185 215 203 199 196 152 106 113 117 123 121 118 110 104 98 88 77 66 57 57 59 55 52 54 57 60 67 67 206
218 105 89 76 80 87 84 69 49 69 135 114 46 72 18 44 52 45 49 47 73 150 182 170 169 176 173 184 165 148 167 202 163 192 195 195 201 192 182 163 147 107 118 123 127 126 123 113 105 96 90 83 68 57 59 58 56 55 56 60 65 72 71 207
218 104 87 75 81 93 102 65 56 67 140 122 26 96 38 47 42 44 52 42 62 130 181 184 177 193 204 173 148 137 159 204 182 172 213 207 177 169 168 128 124 115 121 126 128 129 123 104 91 103 98 82 69 57 60 58 56 55 58 62 66 73 72 207
218 102 87 75 81 95 104 59 68 85 135 127 10 48 85 44 38 42 54 44 59 120 181 187 190 193 201 176 112 72 153 198 219 186 198 197 169 162 152 129 114 115 128 128 136 139 116 100 141 207 189 103 73 49 51 56 52 49 55 59 67 73 73 208
218 101 87 77 83 94 100 56 77 86 111 123 6 40 102 48 38 45 50 47 65 123 166 184 190 197 183 117 134 89 146 200 218 211 188 176 158 157 140 129 118 117 130 126 159 184 108 139 196 189 178 189 172 163 135 48 57 70 53 57 66 72 74 208
218 101 89 78 81 92 98 80 107 97 59 117 26 29 98 68 37 45 54 55 94 138 128 161 186 180 161 71 91 99 112 168 191 217 199 168 164 145 127 128 120 122 135 90 142 113 84 174 184 151 148 182 192 194 210 136 167 183 62 54 62 72 76 208
217 98 89 79 79 90 95 105 120 72 33 63 65 19 39 40 32 44 51 57 111 151 104 149 177 171 184 112 61 23 56 113 154 182 200 163 157 143 125 128 123 133 93 50 113 65 112 185 131 142 192 208 166 150 173 210 210 143 50 49 60 70 72 207
216 96 87 79 79 92 99 115 42 15 26 15 19 16 17 15 33 49 41 55 108 126 96 134 157 161 170 174 157 104 102 187 194 167 180 157 146 135 121 127 136 103 34 67 157 57 51 105 78 77 165 107 107 144 180 198 215 171 56 58 59 70 72 207
217 95 85 78 79 90 88 40 6 18 24 19 5 11 22 21 33 45 43 62 88 95 113 124 114 127 139 162 156 169 187 203 209 206 169 150 142 131 125 117 162 146 26 119 194 161 138 111 41 38 23 64 113 42 99 113 101 159 167 147 61 70 71 207
217 99 88 78 80 86 38 18 36 69 86 85 48 15 18 23 29 44 44 77 103 64 101 102 43 90 78 89 93 103 157 172 187 204 174 145 138 134 134 116 175 117 55 131 179 198 177 154 126 135 101 154 68 24 1 24 96 184 178 100 62 71 71 208
216 104 92 90 83 38 26 52 67 94 95 92 85 39 19 25 26 41 42 62 107 73 74 93 40 48 55 53 43 50 88 110 146 178 164 141 133 135 132 126 153 63 98 131 165 177 166 196 202 175 158 156 73 16 98 177 198 147 72 53 67 72 73 209
218 112 106 79 38 37 53 67 82 98 110 88 84 61 17 22 26 34 37 42 74 83 66 122 100 93 103 103 84 83 103 96 96 164 159 143 134 131 124 107 113 83 122 134 159 169 163 180 184 157 175 143 72 124 176 191 129 55 52 60 67 70 70 208
220 119 85 35 36 53 75 79 89 97 108 108 78 52 22 15 22 24 32 34 47 76 61 126 133 143 166 165 170 170 175 119 141 172 156 147 136 131 127 71 65 82 113 130 160 170 168 176 172 150 181 161 165 192 194 205 205 121 55 60 65 70 70 207
220 87 40 43 48 66 74 86 91 89 93 103 108 60 39 17 19 22 26 27 31 47 44 86 122 151 183 200 207 205 187 153 181 166 155 148 137 131 135 52 39 61 95 121 162 161 157 170 173 162 151 118 136 189 175 173 162 108 59 60 66 70 70 207
200 43 51 53 54 63 76 101 102 97 95 89 96 101 44 23 21 20 16 19 26 34 34 49 74 105 144 174 175 192 156 157 167 164 157 149 141 131 142 71 31 50 87 115 162 169 156 169 171 129 78 47 34 41 29 21 42 73 65 60 65 69 69 207
197 43 44 52 59 62 86 103 105 107 93 90 90 96 75 45 25 24 17 19 23 25 26 30 37 42 52 82 85 92 92 134 112 160 163 151 145 136 145 91 29 49 92 119 167 165 170 174 144 77 46 37 23 23 17 22 69 77 65 60 65 68 68 207
197 36 45 58 58 57 89 97 102 100 94 90 90 96 108 69 45 48 23 23 22 21 18 17 17 10 22 91 127 96 62 107 69 119 147 160 149 142 147 120 29 67 98 129 170 159 175 176 141 83 77 55 30 45 55 88 88 74 65 60 65 68 68 207
198 33 47 50 48 58 95 96 101 103 97 92 96 101 102 108 75 49 33 20 25 25 20 14 21 83 160 196 137 128 49 69 68 94 91 152 156 145 144 139 51 82 106 136 160 162 170 177 154 128 117 61 51 68 78 98 84 71 66 62 64 67 64 206
197 32 43 46 44 61 99 103 106 111 111 105 101 103 96 106 111 67 46 25 17 18 22 14 82 186 184 189 117 101 52 56 75 77 66 110 166 148 147 145 67 96 137 152 162 166 173 180 164 143 96 32 47 60 96 94 84 73 66 61 62 67 64 206
196 31 43 51 46 45 90 92 95 102 112 109 110 103 111 106 110 112 75 53 32 15 12 38 143 166 177 180 145 60 59 55 91 59 55 69 163 159 151 146 66 106 152 164 168 172 181 183 169 129 63 50 41 81 95 89 79 71 65 60 62 67 65 206
196 33 42 49 52 44 76 76 83 91 92 88 99 96 98 115 102 102 126 71 93 123 116 116 163 172 177 169 167 66 60 56 92 57 37 37 92 144 154 103 89 123 149 160 174 184 186 181 161 65 23 34 97 100 86 85 75 69 63 59 61 68 67 205
197 33 36 44 52 66 57 61 73 82 90 97 99 107 93 78 88 94 125 121 76 125 173 183 175 174 177 170 162 85 48 50 83 62 33 27 40 76 63 52 97 112 136 148 161 176 185 176 80 15 19 25 111 116 80 79 70 66 63 60 62 66 62 205
197 31 36 46 49 62 70 77 79 80 81 91 110 111 115 107 80 80 111 155 95 83 126 164 182 171 173 172 164 91 53 60 79 65 38 33 29 49 39 72 108 111 122 137 131 156 166 155 34 16 57 48 101 127 71 74 68 65 66 63 65 66 61 205
196 28 42 48 52 59 70 65 78 83 85 94 108 108 105 105 117 97 95 128 160 90 93 140 170 165 165 167 163 100 50 75 84 75 48 50 30 41 56 90 121 127 119 132 114 130 152 167 138 69 113 93 155 96 67 70 65 62 59 55 56 61 61 203
198 33 36 40 47 60 57 63 76 85 79 89 105 117 120 113 115 118 118 103 162 145 90 116 150 163 159 166 159 114 40 71 76 67 49 61 36 43 75 105 112 137 130 132 133 136 146 150 153 124 144 141 112 68 53 55 50 47 44 43 46 50 54 204
199 37 38 35 42 46 57 60 66 78 80 79 94 105 119 120 116 120 117 111 145 176 109 96 140 157 152 160 154 121 41 61 64 48 48 51 34 43 59 79 92 116 133 141 147 143 151 156 115 65 72 70 84 82 64 59 53 48 43 43 47 54 54 202
196 31 35 37 39 39 47 54 59 66 84 88 96 101 116 130 123 126 118 97 119 168 156 98 113 139 149 157 146 125 47 50 55 40 49 42 34 43 87 103 107 119 124 112 139 158 157 158 66 46 58 89 102 78 64 59 55 50 45 46 51 61 63 204
199 34 36 35 37 38 41 49 65 62 79 95 90 99 119 126 124 127 136 116 82 143 171 120 96 116 137 146 130 112 47 47 50 38 44 39 36 56 90 118 110 118 152 148 105 115 160 150 51 76 85 108 105 103 90 86 82 79 75 77 84 95 98 214
199 35 37 36 36 36 35 41 52 55 67 92 92 105 117 122 132 139 140 144 118 131 170 148 105 106 126 136 108 96 44 45 47 37 46 51 58 59 76 92 108 92 145 173 151 118 102 123 38 82 93 108 116 114 99 93 89 86 87 87 94 104 107 215
199 35 37 36 36 35 32 37 46 48 64 76 96 97 103 105 115 132 131 131 139 130 140 153 115 103 122 128 94 78 44 45 49 38 55 121 139 125 132 132 124 106 144 170 161 162 122 67 50 78 81 112 116 109 83 76 74 72 67 66 68 74 73 206
198 35 38 37 36 36 36 37 41 50 56 61 76 100 100 103 108 112 128 122 122 124 122 126 124 103 109 113 84 69 47 46 50 38 58 83 80 91 121 141 139 127 163 177 158 160 146 46 45 76 104 105 113 107 63 52 52 48 49 49 49 56 55 202
200 38 43 41 38 37 38 38 41 52 53 59 76 95 97 97 98 118 114 118 128 128 119 119 115 104 114 108 72 59 50 50 53 40 61 73 49 43 54 84 114 136 167 177 166 166 140 62 58 84 110 99 100 109 81 75 76 77 73 73 75 84 83 210
201 42 44 42 39 38 39 39 37 45 56 62 66 87 100 107 120 121 129 138 140 141 148 142 116 109 115 96 59 52 51 52 54 50 78 80 91 97 67 48 70 128 161 175 171 170 134 54 56 69 99 95 96 104 88 86 86 87 86 86 89 97 97 212
202 45 46 44 41 40 41 41 40 43 50 57 70 79 98 114 125 120 132 139 141 145 141 144 148 137 115 86 56 51 51 54 51 53 76 97 136 152 151 104 51 107 152 170 170 171 124 53 61 80 94 95 101 101 91 93 92 91 93 94 97 100 96 213
201 47 49 48 45 44 44 44 44 44 49 55 63 64 94 119 120 130 127 130 139 139 139 149 150 153 143 87 50 49 47 53 57 76 92 101 129 146 154 155 94 79 132 169 170 175 105 54 63 69 89 94 100 91 90 88 87 92 91 94 96 99 95 214
203 52 50 50 47 47 48 48 48 46 49 54 56 64 68 94 119 126 126 127 128 125 149 151 150 155 159 123 67 95 95 58 79 106 139 139 140 151 149 154 152 95 115 161 168 170 86 57 65 72 82 98 93 87 89 87 84 92 100 105 102 101 93 211
204 58 55 54 51 50 51 52 51 49 50 52 56 63 63 77 107 122 126 127 125 132 135 142 149 149 151 164 145 140 160 117 117 95 92 121 143 153 154 158 164 129 123 164 164 154 63 61 70 74 83 95 92 94 94 95 93 96 102 103 96 94 87 209
205 64 61 58 55 53 54 56 55 54 54 53 55 60 61 66 84 112 128 135 128 128 128 127 141 137 152 162 132 129 151 145 92 130 91 95 129 153 160 159 169 152 133 160 162 126 57 65 73 83 95 95 92 96 99 100 102 98 101 103 100 96 87 209
202 59 60 55 52 51 52 53 53 53 53 52 53 57 58 60 63 83 109 130 128 130 138 137 136 143 153 140 109 127 131 132 78 89 125 101 112 138 153 155 165 156 154 158 155 95 48 60 69 79 94 92 90 88 89 90 88 85 85 87 90 90 86 210
232 197 201 201 201 201 201 201 201 201 201 201 201 201 202 203 202 203 209 216 219 219 221 221 220 221 221 216 210 217 216 214 210 201 218 218 216 219 222 228 229 227 229 229 219 204 198 203 205 206 209 209 208 207 207 209 210 211 211 211 211 210 205 235
| Xingang Guo |
Yiqi_01 | 4,385 | Computer Architecture Design | # Problem Definition of T10 Benchmark
To compute a matrix multiplication operator on an inter-core connected AI chip, we need you to derive an execution plan using T10's abstraction. For more information about this problem, please refer to "Background Information of T10 Benchmark".
**The Computation Task:**
The matrix multiplication (MatMul) to be computed is defined as $C[m,n] += A[m,k]*B[k,n]$, where $m = 128$, $k = 5120$, and $n = 15360$. The input and output tensors are all in FP16 format (2 bytes per data element). To find better partitioning plans, you may consider padding this operator along any of its dimensions. However, there will be performance overhead if you pad too much.
**The Hardware:**
We use an inter-core connected AI chip called IPU Mk2. An IPU chip has 1,472 cores, and each core executes independent threads in parallel with a private 624KB scratchpad memory, which adds up to a total of 896MB on-chip memory. The IPU cores are interconnected by high-bandwidth low-latency links. Each core can access the scratchpad memory of another core at 5.5GB/s, offering an aggregated inter-core all-to-all bandwidth of $1472 \times 5.5$ GB/s $\approx 8$ TB/s [1]. Inside each core, there is a systolic array of shape $16 \times 16$, which can compute a partition of the MatMul operator at high throughput. If the sub-MatMul to be computed on each core does not have a shape that is a multiple of the systolic array shape, this sub-MatMul must be padded to align with the systolic array shape.
**The Execution Plan:**
In this problem, we need you to derive a fast execution plan that computes the above MatMul on an IPU chip. First, this plan should ensure that at any time during execution, the sub-tensor partitions on each core do not overflow the per-core SRAM size. Second, the partition factors in this plan should comply with all constraints defined in T10's background information. Third, this plan should use no more than 1,472 cores. Finally, this plan should try to minimize the total execution time, which is the sum of per-core computation time and inter-core communication time.
**The Output Format:**
You should output the execution plan in the following format:
- `F_op`: a list of integers with length 3, which are the operator partition factors on dimensions $m$, $k$, and $n$, respectively.
- `f_t_A_m`: integer, which is the temporal partition factor of tensor A on dimension $m$.
- `f_t_A_k`: integer, which is the temporal partition factor of tensor A on dimension $k$.
- `f_t_B_k`: integer, which is the temporal partition factor of tensor B on dimension $k$.
- `f_t_B_n`: integer, which is the temporal partition factor of tensor B on dimension $n$.
- `f_t_C_m`: integer, which is the temporal partition factor of tensor C on dimension $m$.
- `f_t_C_n`: integer, which is the temporal partition factor of tensor C on dimension $n$.
---
# Background Information of T10 Benchmark
## 1. Inter-core Connected AI Chip
Deep learning accelerators, such as GPUs and TPUs, are widely recognized for their exceptional computing throughput (e.g., hundreds of Tera-FLOPS), making them ideal for handling large-scale models and high-dimensional data in deep learning. Such effectiveness is largely attributed to their massive parallel cores and specialized accelerator units, e.g., TensorCore. However, to saturate the high computing throughput, they usually require a high-throughput memory system, e.g., a large shared memory with multi-hierarchical cache layers in accelerators. Also, an efficient deep learning compiler [7, 8] is necessary to optimize data reuse across the memory hierarchy, ensuring the computing units are fully utilized. This combination of hardware and software design often yields orders of magnitude higher performance than traditional CPUs for critical deep learning operations, including matrix multiplication and convolution.
Despite the success of existing accelerators, the constantly increasing demand for processing large deep-learning models with higher computation throughput presents a significant challenge to the underlying memory system. To address this challenge, the community is exploring a more scalable architecture with fully distributed memory, such as the Graphcore IPU [2], SambaNova SN10 [5], and Cerebras WSE [3]. Rather than relying on shared-memory architecture, they typically associate each computation core with local memory, and connect the cores via a high-bandwidth on-chip network, creating a large aggregated on-chip memory. However, this unique architecture renders previous deep learning compilers designed for shared-memory architectures, which cannot fully leverage the new architecture's scalability, resulting in significant memory waste.
Designing a deep learning compiler for distributed memory-based accelerators presents several unique challenges:
1. Due to the absence of global shared memory, it is necessary to partition the operators, along with their input and output tensors, into sub-operators that can operate independently on each core with only local memory access.
2. As the local memory on each core is mostly on-chip memory, the aggregated memory capacity is considerably smaller than the off-chip memory. Thus, the compiler must effectively utilize the limited memory capacity to support a model size as large as possible, without compromising on computing performance.
3. Given that there is usually a trade-off between memory consumption and computation performance for each operator, an end-to-end model compilation must consider the trade-offs among all operators, generating a combinatorial optimization space that is infeasible to solve using existing compilers.
In this problem, we focus on a representative example of the inter-core connected AI chip: the Graphcore Intelligence Processing Unit (IPU) MK2 [2]. An IPU chip has 1,472 cores, and each core executes independent threads in parallel with a private 624KB scratchpad memory, which adds up to a total of 896MB on-chip memory. Compared to the global shared memory architecture, a key distinction is that IPU cores are interconnected by high-bandwidth low-latency links. Each core can access the scratchpad memory of another core at 5.5GB/s, offering an aggregated inter-core all-to-all bandwidth of $1472 \times 5.5$GB/s $\approx 8$TB/s [1].
---
## 2. Background of T10
To eliminate the excessive memory footprint and redundant inter-core communications of VGM, we map the DNN computation to a _compute-shift_ pattern. In each step, each core independently computes a sub-task with data received from its upstream neighbors and shifts the data to its downstream. The feasibility of this approach for general DNNs comes from this observation: most DNN operators can be divided into regular computation tasks, which load and produce consecutive data tiles of the input and output tensors, respectively.
Figure 1 shows an example that maps a MatMul operator to two cores with the compute-shift style execution.
Both (b) and (c) are valid compute-shift execution plans, but with different tradeoffs between memory footprint and communication overhead.
**Example: Mapping MatMul to Two Cores**
We show an example that maps a matrix multiplication (MatMul) operator to two cores in Figure 1 (a).
1. **Partitioning:** We first partition the operator along dimension $m$ onto two cores in Figure 1 (b). By default, both cores hold a copy of the weight tensor, which incurs memory capacity overhead.
2. **Memory Optimization:** To reduce memory footprint, in Figure 1 (c), we further split the weight tensor along dimension $n$ into two parts and place each part on one of the cores. Then, the computation must be conducted in two steps, as each core holds half of the weight tensor and performs half of its computation per step. Between the computation steps, each core circularly shifts its partition to the next core, forming a shift ring of two cores.
**Advantages of Compute-Shift Pattern**
1. Eliminates the need for a global memory to store shared data, improving memory capacity utilization.
2. Evenly distributes communication volume across inter-core connections.
3. Aligns computation with data tile, avoiding redundant communications to many cores.
**Tradeoff Between Memory Footprint and Communication Overhead**
For example, both Figure 1 (b) and (c) show valid execution plans:
- **Plan (b):** Finishes the entire computation in one step without inter-core communication, but has a higher memory footprint.
- **Plan (c):** Has less memory footprint but incurs more communication overhead.
In reality, deriving the best tradeoff is challenging due to multi-dimensional DNN operators and thousands of cores on an IPU chip. An efficient compute-shift execution plan may contain numerous nested shift rings along multiple tensor dimensions, composing a massive tradeoff space to search through.
---
## 3. T10's Execution Plan Format
### $r$Tensor: A New Tensor Abstraction
T10 introduces a distributed tensor abstraction called RotatingTensor ($r$Tensor). $r$Tensor describes how each tensor is partitioned, mapped, and shifted on the interconnected cores (summarized in Table 1).
**Table 1. Terminologies used in T10**
| **Symbol** | **Name** | **Description** |
|------------|------------------------------|-------------------------------------------------------------------------------|
| `f_s^X` | Spatial Partition Factor | Spatially partitions a tensor X into sub-tensors. |
| `f_t^X` | Temporal Partition Factor | Temporally partitions a sub-tensor of X into sub-tensor partitions. |
| `F_op` | Operator Partition Factor | Spatially partitions an entire operator into sub-operators. |
First, T10 partitions the computation of an operator onto multiple cores. Based on the data dependency, the computation partitioning will imply how each of its input/output tensor is partitioned. This gives a spatial partition factor ($f_s$), which splits a tensor into sub-tensors. Second, each sub-tensor may be required by multiple cores. To share a sub-tensor among them, we specify how the sub-tensor is further partitioned among the cores using a temporal partition factor ($f_t$). $f_t$ also specifies how the partitions of a sub-tensor are circularly shifted among the cores. Altogether, a set of $r$Tensors of an operator defines a compute-shift execution plan. The numerous possible $r$Tensor configurations of an operator generate a huge search space of execution plans.
Figure 2 shows the llustration of rTensor partitioning and rotating.
Specifically, $f_s$ and $f_t$ are vectors with a length equal to the number of dimensions of a tensor, indicating how the tensor is partitioned along each dimension. For example, in Figure 2 (a), a tensor $T$ of shape $[6,8]$ is partitioned onto 8 cores by a spatial factor $f_s=[2,1]$, forming 2 sub-tensors of shape $[3,8]$. Thus, to share each sub-tensor among 4 cores without incurring high memory footprint, a temporal factor $f_t=[1,2]$ further partitions each sub-tensor into 2 partitions with shape $[3,4]$, as shown in Figure 2 (b). It forms $\frac{4}{2} = 2$ rotation rings with 2 cores in each, where cores share the sub-tensor by circularly shifting its partitions. In comparison, Figure 2 (c) shows how another $f_t=[1,4]$ splits the same sub-tensor to 4 partitions, on $\frac{4}{4}=1$ rotation ring with 4 cores.
---
## 3.2. Compute-Shift Execution Plan
Using the $r$Tensor abstraction, T10 organizes the computation of a general DNN operator into a compute-shift pattern, where the operator's computation and tensors are partitioned to individual cores and their local memories. The entire computation involves multiple compute-shift steps until each tensor has been shifted across all cores. Each compute step is defined as a *sub-task*. In each compute-shift step, each core computes a sub-task and shifts local tensors to its neighbors. We now discuss how T10 partitions DNN operators into compute-shift-based execution plans.
### Operator representation.
To represent an operator's computation, T10 uses tensor expression [6], which defines how each output tensor value is computed from the input values. For example, a matrix multiplication of tensors $A$ in shape $[M,K]$ and $B$ in $[K,N]$ into $C$ is defined as
$C[m,n] \longleftarrow A[m,k]*B[k,n]$,
where $m$, $k$, and $n$ are axes to index the elements in each tensor. Equation (1) indicates that any value in $C$ indexed by $m$ and $n$ (i.e., $C[m,n]$) is computed by summing $A[m,k]*B[k,n]$ over all possible indices $k$. T10 supports all common operators, like MatMult and Convolution, from DNN workloads in both inference and training. For a few special cases like Sort, which cannot be represented in tensor expression, T10 uses the implementations from the vendor library.
### Partitioning an operator.
To map an operator to interconnected cores, T10 first partitions it into parallel *sub-operators* along all unique axes in its tensor expression, using an *operator partition factor* ($F_{op}$). For example, Equation (1) contains axes $m$, $k$, and $n$, then $F_{op}$ is a vector of three integer factors specifying how the three axes are spatially partitioned. The total number of sub-operators is the product of all elements in $F_{op}$. For example, $F_{op}=[2,1,4]$ for $[m,k,n]$ slices the operator into 8 sub-operators on 8 cores, each computing a $\lceil\frac{M}{2},\frac{K}{1}\rceil \times \lceil\frac{K}{1},\frac{N}{4}\rceil$ sub-matrix multiplication.
### Partitioning $r$Tensors.
T10 then uses $F_{op}$ to derive the spatial partition factor $f_s$ for each tensor, following the data dependencies in tensor expression. With the same example, for $F_{op}=[2,1,4]$ on $[m,k,n]$, the spatial partition factor for the tensor A is $f_s^A=[2,1]$ for axes $m$ and $k$. Similarly, for tensors B and C, we have $f_s^B=[1,4]$ and $f_s^C=[2,4]$.
If a tensor's dimensions do not include some axis in $F_{op}$, each of the sliced sub-tensors is required by multiple sub-operators along the missing axis. Thus, once the spatial factor determines the number of cores that will share a sub-tensor, the temporal factor determines how we split the sub-tensor across these cores into rotation ring(s). In the above example, $F_{op}$ partitions the entire operator onto $2 \times 1 \times 4 = 8$ cores, and $f_s^B$ spatially partitions tensor B into $1 \times 4 = 4$ sub-tensors. Thus, each sub-tensor is shared by $P=\frac{8}{4}=2$ cores. Then, a temporal factor $f_t^B=[2,1]$ further splits each sub-tensor into $2 \times 1 = 2$ partitions, forming $\frac{P}{2}=1$ rotation ring.
T10 enforces that the product of elements in $f_t$, or $\prod f_t$, is a divisor of the number of cores that shares the sub-tensor ($P$), so that the number of rotation rings (i.e., $\frac{P}{\prod f_t}$) is an integer. If there is more than one rotation ring, we replicate each sub-tensor $\frac{P}{\prod f_t}$ times to ensure that each ring shares one copy of the sub-tensor. While the duplication consumes memory space, it may reduce the number of rotation steps by allowing a larger sub-task on each core at each step, which enables a trade-off between memory usage and communication cost.
Figure 3 shows an example of the rotation of rTensor.
The compute-shift executions of the sub-operators need to be aligned.
### Aligning the rotations of $r$Tensors.
Since a general DNN operator can have various tensor shapes, a naive partitioning plan can easily cause the tensor shifting and the sub-task computing at an unaligned pace. In Figure 3 (a), we still use the MatMult operator in Equation (1) as an example. We partition it into a $2 \times 4$ grid in Figure 3 (b), with the specified partition factors. Note that both A and B are temporally partitioned along axis $k$, but with different $f_t$ factors.
The rotating paces of tensors in one operator must be aligned to ensure correct data dependency. In Figure 3 (b), tensors A and B are shifted with different paces along axis $k$. To synchronizes the paces, each core shifts A for 2 times along $k$ for each time B is shifted, and computes a sub-task (i.e., a sub-MatMult) of shape $[\text{m=1, k=1, n=1}]$ for each time A is shifted. This requires 4 compute steps to finish the sub-operator on this core, where A is shifted after each step and B is shifted every 2 steps.
### Alignment constraints.
To ensure that a $r$Tensor configuration can be translated into a valid execution plan, the product of the temporal partition factors of a tensor (i.e., the total number of temporal partitions) should be a factor of the replication number caused by spatial partitioning. Additionally, for different tensors of an operator that share a common dimension, all their temporal factors on this dimension should be aligned. Thus, any pair of temporal factors should be a factor or multiple of each other. This approach allows each tensor or sub-tensor to flow across cores at a different pace, while ensuring that corresponding tensor partitions can meet at the same time step on a specific core. For instance, in the matrix multiplication illustrated in Figure 3(b), tensor A has a temporal factor of 4 along dimension $k$, tensor B has a factor of 2, and these factors along $k$ (i.e., 4 and 2) must be a factor or multiple of each other.
### Sub-operator scheduling.
With the above constraints, we can organize an operator's computation into a valid compute-shift execution plan. At each step, each sub-operator computes a sub-task partitioned by $F_{op}$ and the $f_t$ along each axis. Each sub-operator iterates over all its sub-tasks by nested-looping through the axes of this operator. Between sub-tasks, an $r$Tensor is rotated along the currently iterating axis for all its sub-tensors, until all sub-tasks are enumerated.
Specifically, T10 organizes the computation on each core as nested loops of interleaved compute and shift stages. Each loop corresponds to a temporally partitioned dimension. For example, if there are two dimensions to shift, $m$ and $n$, with $m$ shifting twice and $n$ shifting once, then there are two valid 5-time shift schedules: (1) $m$ is the inner loop, i.e., $\text{shift}(m) \times 2 \rightarrow \text{shift}(n) \rightarrow \text{shift}(m) \times 2$; and (2) $n$ is the inner loop, i.e., $\text{shift}(n) \rightarrow \text{shift}(m) \rightarrow \text{shift}(n) \rightarrow \text{shift}(m) \rightarrow \text{shift}(n)$. To determine the optimal loop order, T10 designates the dimension belonging to the tensor with the smaller size as the inner loop to reduce the total communication volume, as the inner loop is executed more times. To generate local computations for each core, T10 invokes the corresponding compute function with the partition configuration and the tensor expression.
---
# References
[1] Zhe Jia, Blake Tillman, Marco Maggioni, and Daniele Paolo Scarpazza. 2019. Dissecting the Graphcore IPU Architecture via Microbenchmarking.
[2] Simon Knowles. 2021. Graphcore Colossus Mk2 IPU.
[3] Sean Lie. 2021. Multi-Million Core, Multi-Wafer AI Cluster.
[4] Yiqi Liu et al. 2024. Scaling Deep Learning Computation over the Inter-Core Connected Intelligence Processor with T10.
[5] Raghu Prabhakar and Sumti Jairath. 2021. SambaNova SN10 RDU.
[6] Nicolas Vasilache et al. 2018. Tensor Comprehensions.
[7] Lianmin Zheng et al. 2020. Ansor.
[8] Hongyu Zhu et al. 2022. ROLLER. | Yiqi Liu |
KV_02 | 389 | Control Design | ## Task Description
You are designing control parameters for a **Switched Capacitor Battery Balancing System** involving active balancing of three Li-ion battery cells connected in series.
The system uses:
- 2 capacitors and 6 bidirectional switches (active balancing architecture)
- Initial state of charge (SOC) of each cell:
- Cell 1: 0.70
- Cell 2: 0.75
- Cell 3: 0.80
- PWM switching for UP and DOWN phases:
- Switching period (Tper) = 0.006 seconds
- 50% duty cycle
- 180° interleaving
- CC-CV Battery control block:
- Maximum voltage vMax = 4.1 V
- PI controller: Kp = 100, Ki = 10
- Charge and discharge behavior controlled by relay toggling logic
You must propose control parameters that allow safe, efficient, and effective balancing.
---
## Your Task
You are tasked with proposing **four numerical values** that control balancing behavior:
1. `lowest_current`:
- The **smallest balancing current** (in Amperes) that could reasonably allow balancing progress.
2. `highest_current`:
- The **maximum allowable balancing current** (in Amperes) without causing SOC instability.
3. `on_threshold`:
- The **SOC level** at which the relay should **stop charging** (start discharging).
4. `off_threshold`:
- The **SOC level** at which the relay should **resume charging** after discharge.
---
## Output Format
You must **only** return the following exact Python dictionary format:
```python
{
"lowest_current": YOUR_VALUE,
"highest_current": YOUR_VALUE,
"on_threshold": YOUR_VALUE,
"off_threshold": YOUR_VALUE
}
| Kojo Vandyck |
XW_04 | 1,292 | Operating System Design | ## Task Description
In this task, you will be provided with a filesystem image. You are required to develop a separate program that implements a different filesystem operation (e.g., create, read, update, delete)—to modify the corresponding sections of that image. Your objective is to ensure that the program correctly performs its assigned operation on the intended part of the filesystem image while preserving its overall integrity.
Here is the class definition for your reference:
from dataclasses import dataclass, field
from typing import List, Dict, Optional
@dataclass
class SuperBlock:
"""File system superblock, stores metadata."""
block_size: int # Size of each block (bytes)
total_blocks: int # Total number of blocks
inode_count: int # Total number of inodes
free_block_bitmap: List[bool] # Free block bitmap, True = free
@dataclass
class Inode:
"""Inode structure, stores file/directory metadata."""
ino: int # Inode number
is_dir: bool # Whether this inode is a directory
size: int # File size (bytes)
direct_blocks: List[int] # List of direct block indices
# Optional: add indirect block pointers, multi-level indexing, permissions, timestamps, etc.
@dataclass
class DirEntry:
"""Directory entry: maps a filename to an inode."""
name: str
inode: int
@dataclass
class FileSystemImage:
"""Complete file system image structure."""
superblock: SuperBlock
inodes: Dict[int, Inode] = field(default_factory=dict)
# Directory tree: inode -> list of entries in that directory; valid only for is_dir=True inodes
directories: Dict[int, List[DirEntry]] = field(default_factory=dict)
# Data block storage area: index corresponds to block number, content is bytes
data_blocks: List[Optional[bytes]] = field(default_factory=list)
def __post_init__(self):
# Initialize data block storage area
if not self.data_blocks:
self.data_blocks = [None] * self.superblock.total_blocks
def allocate_block(self) -> int:
"""Allocate a block from the free bitmap and return its index; raise if none available."""
for idx, free in enumerate(self.superblock.free_block_bitmap):
if free:
self.superblock.free_block_bitmap[idx] = False
self.data_blocks[idx] = b'' # Initialize with empty content
return idx
raise RuntimeError("No free blocks available")
def free_block(self, block_idx: int):
"""Free the specified block index."""
if 0 <= block_idx < self.superblock.total_blocks:
self.superblock.free_block_bitmap[block_idx] = True
self.data_blocks[block_idx] = None
else:
raise IndexError("Block index out of range")
def create_inode(self, is_dir: bool) -> Inode:
"""Create a new inode and return it."""
new_ino = len(self.inodes) + 1
if new_ino > self.superblock.inode_count:
raise RuntimeError("No free inodes")
inode = Inode(
ino=new_ino,
is_dir=is_dir,
size=0,
direct_blocks=[]
)
self.inodes[new_ino] = inode
if is_dir:
self.directories[new_ino] = []
return inode
def add_dir_entry(self, dir_ino: int, name: str, inode: int):
"""Add a directory entry to the directory with inode dir_ino."""
if dir_ino not in self.directories:
raise RuntimeError("Not a directory inode")
self.directories[dir_ino].append(DirEntry(name=name, inode=inode))
### Task
def delete(fs_img: FileSystemImage, path: str) -> FileSystemImage:
"""
Delete the file or directory at the given path within the FileSystemImage.
Return the updated FileSystemImage so that its inodes, directory entries,
and data blocks can be inspected for correctness.
Parameters:
- fs_img: the FileSystemImage instance containing inodes, directories,
and data blocks.
- path: an absolute or relative path to the file or directory to delete.
Returns:
- The same FileSystemImage instance (`fs_img`), mutated to reflect the
removal of the entry and reclamation of resources.
Behavior:
1. Split `path` into `parent_path` and `name`:
e.g. `/a/b/c` → `parent_path='/a/b'`, `name='c'`.
2. Look up `parent_path`:
- If not found, raise `FileNotFoundError`.
- If found but not a directory, raise `NotADirectoryError`.
3. In the parent directory’s entries, locate an entry whose `name` matches:
- If none found, raise `FileNotFoundError`.
- Determine its `inode` number.
4. Inspect the target inode:
- If it is a directory and is **not empty**, raise `OSError("Directory not empty")`.
- If it is a directory and empty, remove its entry list from `fs_img.directories`.
- If it is a file, proceed to free its data blocks:
- For each block index in `inode.direct_blocks`, call `fs_img.free_block(index)`.
5. Remove the inode from `fs_img.inodes`.
6. Remove the directory entry from the parent’s `fs_img.directories[parent_inode.ino]`.
7. Return the mutated `fs_img`.
Exceptions:
- `FileNotFoundError` if the path or parent directory does not exist.
- `NotADirectoryError` if the parent exists but is not a directory.
- `FileExistsError` is **not** used here; instead:
- `OSError("Directory not empty")` if attempting to delete a non-empty directory.
"""
# Your implementation here… | Licheng Xu, Jinwen Wang |
Ziheng_02 | 563 | Robotics | ##Task Description
The question: Find a set of joint variables that would produce a given tool pose for a 6-DOF robot
Frame 0 is fixed to the base. Frame 1 is fixed to the tool. Set the frame 0 as the reference, for frame 1, the homogeneous transformation matrix M_1in0 is:
M = [ 0.0000 0.0000 1.0000 -8.0000;
1.0000 0.0000 0.0000 2.0000;
0.0000 1.0000 0.0000 0.0000;
0.0000 0.0000 0.0000 1.0000]];
The matrix of spatial screw axes is:
S = [ 0.0000 1.0000 0.0000 0.0000 -1.0000 0.0000;
0.0000 0.0000 0.0000 1.0000 0.0000 1.0000;
0.0000 0.0000 -1.0000 0.0000 0.0000 0.0000;
0.0000 0.0000 2.0000 0.0000 0.0000 0.0000;
1.0000 0.0000 -4.0000 0.0000 0.0000 0.0000;
0.0000 0.0000 0.0000 -6.0000 0.0000 -8.0000 ];
The goal pose T_1in0 is:
T_1in0 = [ -0.5429 0.5940 0.5937 -9.3919;
0.6499 -0.1506 0.7449 -1.8656;
0.5319 0.7903 -0.3043 0.6739;
0 0 0 1.0000 ];
## Output Format
Find a set of joint variables θ that is:
theta=[theta_1; theta_2; theta_3; theta_4; theta_5; theta_6]
that would result in the given pose T_1in0. | Ziheng Guo |
XG_08 | 730 | Control Design | ## Task Description
In this task, you will need to build a fuzzy inference system using MATLAB Fuzzy Logic Designer app for a tipping problem. For this problem, the tipping behavior is defined using the following rule:
1. If the service is poor or the food is rancid, then the tip is cheap.
2. If the service is good, then the tip is average.
3. If the service is excellent or the food is delicious, then the tip is generous.
The following MATLAB code is given to build the fuzzy inference system with some missing parts:
<code>
% create a Mamdani FIS, specifying its name
fis = mamfis("Name","tipper");
% add input variables
fis = addInput(fis,[0 10],"Name","service");
fis = addInput(fis,[0 10],"Name","food");
% add membership function 1
fis = addMF(fis,"service","<MISSING_type>",<MISSING_parameters>,"Name","poor");
% add membership function 2
fis = addMF(fis,"service","<MISSING_type>",<MISSING_parameters>,"Name","good");
% add membership function 3
fis = addMF(fis,"service","<MISSING_type>",<MISSING_parameters>,"Name","excellent");
% add membership function 4
fis = addMF(fis,"food","<MISSING_type>",<MISSING_parameters>,"Name","rancid");
% add membership function 5
fis = addMF(fis,"food","<MISSING_type>",<MISSING_parameters>,"Name","delicious");
% add output variable
fis = addOutput(fis,[0 30],"Name","tip");
% add membership function 6
fis = addMF(fis,"tip","<MISSING_type>",<MISSING_parameters>,"Name","cheap");
% add membership function 7
fis = addMF(fis,"tip","<MISSING_type>",<MISSING_parameters>,"Name","average");
% add membership function 8
fis = addMF(fis,"tip","<MISSING_type>",<MISSING_parameters>,"Name","generous");
% add rules
ruleList = <MISSING_rule_list>;
fis = addRule(fis,ruleList);
</code>
### Task 1
Your first task is to complete the code to build the fuzzy inference system. For membership functions, the corresponding shape is given in the attached image 1 to 8. You need to determine the type of membership function and the parameters using the images. You should choose membership function types among gaussmf, trapmf, and trimf.
### Task 2
Your second task is to specify the rule list for the fuzzy inference system as a numeric array using the aforementioned rules.
Each row of the array contains one rule in the following format.
- Column 1 — Index of membership function for first input
- Column 2 — Index of membership function for second input
- Column 3 — Index of membership function for output
- Column 4 — Rule weight (from 0 to 1)
- Column 5 — Fuzzy operator (1 for AND, 2 for OR)
Therefore, you should return a 3x5 array for this rule list.
### Task 3
Your third task is to use the fuzzy inference system to determine the tip for the following inputs:
Input 1:
- service = 6
- food = 6
Input 2:
- service = 1
- food = 2
| Xingang Guo |
XW_03 | 1,261 | Operating System Design | ## Task Description
In this task, you will be provided with a filesystem image. You are required to develop a separate program that implements a filesystem operation (e.g., create, read, update, delete)—to modify the corresponding sections of that image. Your objective is to ensure that each program correctly performs its assigned operation on the intended part of the filesystem image while preserving its overall integrity.
Here is the class definition for your reference:
from dataclasses import dataclass, field
from typing import List, Dict, Optional
@dataclass
class SuperBlock:
"""File system superblock, stores metadata."""
block_size: int # Size of each block (bytes)
total_blocks: int # Total number of blocks
inode_count: int # Total number of inodes
free_block_bitmap: List[bool] # Free block bitmap, True = free
@dataclass
class Inode:
"""Inode structure, stores file/directory metadata."""
ino: int # Inode number
is_dir: bool # Whether this inode is a directory
size: int # File size (bytes)
direct_blocks: List[int] # List of direct block indices
# Optional: add indirect block pointers, multi-level indexing, permissions, timestamps, etc.
@dataclass
class DirEntry:
"""Directory entry: maps a filename to an inode."""
name: str
inode: int
@dataclass
class FileSystemImage:
"""Complete file system image structure."""
superblock: SuperBlock
inodes: Dict[int, Inode] = field(default_factory=dict)
# Directory tree: inode -> list of entries in that directory; valid only for is_dir=True inodes
directories: Dict[int, List[DirEntry]] = field(default_factory=dict)
# Data block storage area: index corresponds to block number, content is bytes
data_blocks: List[Optional[bytes]] = field(default_factory=list)
def __post_init__(self):
# Initialize data block storage area
if not self.data_blocks:
self.data_blocks = [None] * self.superblock.total_blocks
def allocate_block(self) -> int:
"""Allocate a block from the free bitmap and return its index; raise if none available."""
for idx, free in enumerate(self.superblock.free_block_bitmap):
if free:
self.superblock.free_block_bitmap[idx] = False
self.data_blocks[idx] = b'' # Initialize with empty content
return idx
raise RuntimeError("No free blocks available")
def free_block(self, block_idx: int):
"""Free the specified block index."""
if 0 <= block_idx < self.superblock.total_blocks:
self.superblock.free_block_bitmap[block_idx] = True
self.data_blocks[block_idx] = None
else:
raise IndexError("Block index out of range")
def create_inode(self, is_dir: bool) -> Inode:
"""Create a new inode and return it."""
new_ino = len(self.inodes) + 1
if new_ino > self.superblock.inode_count:
raise RuntimeError("No free inodes")
inode = Inode(
ino=new_ino,
is_dir=is_dir,
size=0,
direct_blocks=[]
)
self.inodes[new_ino] = inode
if is_dir:
self.directories[new_ino] = []
return inode
def add_dir_entry(self, dir_ino: int, name: str, inode: int):
"""Add a directory entry to the directory with inode dir_ino."""
if dir_ino not in self.directories:
raise RuntimeError("Not a directory inode")
self.directories[dir_ino].append(DirEntry(name=name, inode=inode))
### Task
def create(fs_img: FileSystemImage, path: str, is_dir: bool = False) -> FileSystemImage:
"""
Create a new empty file or directory at the given path within the FileSystemImage.
Return the updated FileSystemImage so that its inodes and directory entries
can be inspected for correctness.
Parameters:
- fs_img: the FileSystemImage instance containing inodes, directories,
and data blocks.
- path: an absolute or relative path where the new file or directory
should be created.
- is_dir: if True, create a directory; if False, create a regular file.
Returns:
- The same FileSystemImage instance (`fs_img`), mutated to include the
new entry’s inode and parent directory mapping.
Behavior:
1. Split `path` into `parent_path` and `name`:
- e.g. `/a/b/c` → `parent_path='/a/b'`, `name='c'`.
2. Look up `parent_path` in `fs_img`:
- If not found, raise `FileNotFoundError`.
- If found but not a directory, raise `NotADirectoryError`.
3. In the parent directory’s entries, if `name` already exists
(file or directory), raise `FileExistsError`.
4. Allocate a new inode:
```python
new_inode = fs_img.create_inode(is_dir=is_dir)
```
5. If creating a directory, initialize its child entry list
(already handled by `create_inode`).
6. Add a directory entry in the parent:
```python
fs_img.add_dir_entry(parent_inode.ino, name, new_inode.ino)
```
7. Return the mutated `fs_img`.
Exceptions:
- `FileNotFoundError` if the parent path does not exist.
- `NotADirectoryError` if the parent exists but is not a directory.
- `FileExistsError` if an entry with the same `name` already exists.
"""
# Your implementation here… | Licheng Xu, Jinwen Wang |
XG_01 | 775 | Control Design | In this task, you will use MATLAB’s Robust Control Toolbox, specifically the loopsyn function, to design a stabilizing controller for an aircraft system.
## Aircraft Model
The aircraft is modeled by the following state-space system:
A = \begin{bmatrix}
-2.2567 \times 10^{-2} & -3.6617 \times 10^{1} & -1.8897 \times 10^{1} & -3.2090 \times 10^{1} & 3.2509 & -7.6257 \times 10^{-1} \\
9.2572 \times 10^{-5} & -1.8997 & 9.8312 \times 10^{-1} & -7.2562 \times 10^{-4} & -1.7080 \times 10^{-1} & -4.9652 \times 10^{-3} \\
1.2338 \times 10^{-2} & 1.1720 \times 10^{1} & -2.6316 & 8.7582 \times 10^{-4} & -3.1604 \times 10^{1} & 2.2396 \times 10^{1} \\
0 & 0 & 1.0000 & 0 & 0 & 0 \\
0 & 0 & 0 & 0 & -3.0000 \times 10^{1} & 0 \\
0 & 0 & 0 & 0 & 0 & -3.0000 \times 10^{1}
\end{bmatrix}
B = \begin{bmatrix}
0 & 0 \\
0 & 0 \\
0 & 0 \\
0 & 0 \\
30 & 0 \\
0 & 30
\end{bmatrix}
C = \begin{bmatrix}
0 & 1 & 0 & 0 & 0 & 0 \\
0 & 0 & 0 & 1 & 0 & 0
\end{bmatrix}
D = \begin{bmatrix}
0 & 0 \\
0 & 0
\end{bmatrix}
## Instructions
### Step 1: Design a target loop shape
To use loopsyn design a stabilizing controller, you will first need to provide a target loop shape. Consider a desired loop shape with:
- crossover frequency of 8 rad/s
- has low gain at high frequencies for robustness, and high gain at low frequencies for performance
- consider the transfer function 8/s as an example of a target loop shape
Your first task is to specify the transfer function of the desired loop shape by providing its numerator and denominator coefficients.
### Step 2: Use *loopsyn* to Design a Controller
Using the target loop shape, design a stabilizing controller K via loopsyn. Your design must ensure the **closed-loop system achieves at least a 0.05 disk margin** and **has a performance gamma less than 1**. Here gamma is a performance measure of how well the loop shape with proposed controller matches the desired loop shape. Values of gamma near or below 1 indicate that G*K is close to Gd.
The loopsyn function requires the following inputs:
- G: dynamical system to be controlled (this will be the aircraft model)
- Gd: desired loop shape (this will be determined by the num and den provided in the previous step)
- alpha: a factor (0 < alpha < 1) to balance between performance and robustness
There will be an evaluation step to check if the closed-loop system achieves at least 0.05 disk margin.
| Xingang Guo |
ZC_01 | 646 | Control Design | ## Task Description
Consider the following continuous‑time uncertain system:
\[
\dot{x}(t) = \bigl(A_0 + \Delta A\bigr)\,x(t) + B_1\,w(t) + B_2\,u(t),
\]
\[
z(t) = C_1\,x(t) + D_{11}\,w(t) + D_{12}\,u(t),
\]
\[
y(t) = C_2\,x(t) + D_{21}\,w(t) + D_{22}\,u(t),
\]
where \(x\in\mathbb{R}^4\), \(u\in\mathbb{R}\), \(w\in\mathbb{R}\), and \(z,y\in\mathbb{R}\). The nominal matrices are
\[
A_0 = \begin{bmatrix}
0 & 1 & 0 & 0\\
0 & 0 & 1 & 0\\
0 & 0 & 0 & 1\\
-5 & -4 & -3 & -2
\end{bmatrix},\quad
B_1 = \begin{bmatrix}0\\0\\0\\1\end{bmatrix},\quad
B_2 = \begin{bmatrix}0\\0\\1\\0\end{bmatrix},
\]
\[
C_1 = \begin{bmatrix}1 & 0 & 0 & 0\end{bmatrix},\quad
D_{11} = 0,\quad
D_{12} = 0,
\]
\[
C_2 = \begin{bmatrix}0 & 0 & 1 & 0\end{bmatrix},\quad
D_{21} = 0,\quad
D_{22} = 0.
\]
The uncertainties are
\[
\Delta A \in \mathrm{Co}\{\,0.2\,I_4,\;-0.2\,I_4\},
\qquad
w(s) = \Delta_{\mathrm{dyn}}(s)\,z(s),\;\|\Delta_{\mathrm{dyn}}\|_\infty \le 1.
\]
### Task
By solving a SDP to meet the H-infinity performance, design a static state‑feedback gain \(K\in\mathbb{R}^{1\times 4}\) such that the closed‑loop system satisfies:
1. Robust stability: for all \(\Delta A \in \mathrm{Co}\{\,\pm0.2\,I_4\}\) and any \(\Delta_{\mathrm{dyn}}\) with \(\|\Delta_{\mathrm{dyn}}\|_\infty \le 1\), the closed‑loop matrix is Hurwitz.
2. \(\mathcal{H}_\infty\) performance: the transfer function \(T_{zw}(s)\) satisfies \(\|T_{zw}\|_\infty < 0.3\).
| Zichen Wang |
KV_03 | 707 | Control Design | Switched Capacitor Battery Balancing System – Design Challenge Task
Task Title:
Fill-in-the-Blank System Architecture Inference – Battery CC-CV Interface
System Description:
The system balances a 3-cell lithium-ion battery pack using switched-capacitor charge redistribution. The system includes six switches (S1–S6), two capacitors, and a Battery CC-CV block that can both inject and extract current depending on the system’s state-of-charge (SOC). The current flow is dynamically controlled based on SOC feedback, voltage readings, and a relay mechanism to toggle modes. A PI controller regulates behavior during charging and discharging. The goal is to maintain safe and efficient balancing under varying SOC conditions using only local cell information and logic-driven control blocks.
Technical Specifications:
- Battery: 3 Li-ion cells in series, each 27 Ah
- Capacitors: 0.5 F each (2 total)
- Switches: 6 total; closed resistance = 0.00734 Ω, open conductance = 1e-5 S
- Switching control: 50% duty cycle, Tper = 0.006 s
- Initial SOCs: Cell 1 = 0.8, Cell 2 = 0.75, Cell 3 = 0.7
- Battery CC-CV behavior with max voltage = 4.1 V
- PI Controller: Proportional gain = 100, Integral gain = 10
- Feedback channels include SOC and voltage monitoring through ZOH blocks
- Relay logic is used to switch between injecting and withdrawing current
- Final current output is passed through a control logic layer before being applied to the Battery CC-CV block
Design Task:
You are given a redacted system diagram with 9 missing functional blocks labeled A through J (excluding H, which is not used). Each label corresponds to a required Simulink or logic block that enables correct operation of the system. Your task is to infer and name the correct block for each label based only on your understanding of the system architecture and its operational requirements.
To assist, here are examples of Simulink or logical block types that may appear somewhere in the system (not in any particular order, and not mapped to any specific label):
- max
- chargingenabled
- cellvoltage
- currentwhencharging
- currentwhendischarging
- gain
- constant
- relay
- current output port
You must **not assume the ordering** or directly match these terms to any label. Instead, you must analyze the described system behavior and infer the correct Simulink block for each missing label. Do not include any explanations, justifications, or descriptions — only provide the mapping.
Expected Output Format:
Return a dictionary in the following format, using strings that correspond to valid Simulink block types or logic expressions (no comments, no extra spaces, no Markdown, no special control characters):
{
"A": "<Simulink block or logic>",
"B": "<Simulink block or logic>",
"C": "<Simulink block or logic>",
"D": "<Simulink block or logic>",
"E": "<Simulink block or logic>",
"F": "<Simulink block or logic>",
"G": "<Simulink block or logic>",
"I": "<Simulink block or logic>",
"J": "<Simulink block or logic>"
}
| Kojo Vandyck |
AM_03 | 1,159 | Robotics | ## Task Description
Your task is to navigate a robot around static obstacles and walking pedestrians.
The map is a 30 by 30 grid. The origin, i.e. (x,y) = (0,0), is at the bottom left of the grid.
x-axis grows to the right and y-axis grows upwards.
There are three static rectangular obstacles formatted in ((x1, y1), (x2, y2)) that describe the
bottom left and top right corners of the obstacle box:
[
((5, 0), (7, 15)),
((10,20), (20,30)),
((15, 5), (30, 10))
]
There are pedestrians walking around and their trajectory is
stored as a list of tuples (t, x, y), where t is number of seconds from 0 to 29,
and x and y are the coordinates of the bottom left corner in the grid.
The pedestrians and robots are both 2 by 2 in size.
Their paths are as follows:
'ped1': [ (0,1,1),
(1,1,2),
(2,1,4),
(3,1,6),
(4,1,7),
(5,1,9),
(6,1,11),
(7,2,13),
(8,2,14),
(9,3,16),
(10,6,16),
(11,7,15),
(12,8,13),
(13,9,12),
(14,10,11),
(15,11,11),
(16,12,11),
(17,13,11),
(18,14,11),
(19,15,11),
(20,16,11),
(21,17,11),
(22,18,11),
(23,19,11),
(24,20,11),
(25,21,11),
(26,22,11),
(27,23,11),
(28,24,11),
(29,25,11)
],
'ped2': [ (0,25,28),
(1,25,28),
(2,25,26),
(3,25,24),
(4,25,22),
(5,25,20),
(6,25,18),
(7,25,16),
(8,25,14),
(9,24,12),
(10,22,12),
(11,20,12),
(12,19,12),
(13,17,12),
(14,16,12),
(15,16,12),
(16,15,13),
(17,14,15),
(18,12,16),
(19,10,16),
(20,8,16),
(21,6,16),
(22,5,16),
(23,4,16),
(24,4,17),
(25,4,18),
(26,4,19),
(27,4,20),
(28,4,21),
(29,4,22)
],
'ped3': [ (0, 25, 2),
(1, 24, 2),
(2, 23, 2),
(3, 22, 2),
(4, 21, 2),
(5, 20, 2),
(6, 19, 2),
(7, 18, 2),
(8, 17, 2),
(9, 16, 2),
(10,15,2),
(11,14,2),
(12,13,2),
(13,12,2),
(14,11,2),
(15,10,2),
(16,9,3),
(17,8,4),
(18,8,6),
(19,8,8),
(20,8,10),
(21,8,12),
(22,8,14),
(23,8,16),
(24,8,18),
(25,8,20),
(26,8,22),
(27,8,24),
(28,8,26),
(29,8,28)
]
The robot must start at (17, 2), and hit goals A and B one after another in any order.
Goal A is positioned at (5, 20) and Goal B at (25, 24).
You must provide a list of tuples in (t,x,y) format that is free of collisions from
both pedestrians and static rectangular obstacles.
The speed limit of robot in either x and y direction is 2 between each time step.
This means that the robot can move in the x direction 2 steps and y direction 2 steps and be ok.
You will be evaluated on the following:
- Starting position at t=0 is correct
- Hits Goal A at some point in time
- Hits Goal B at some point in time
- No collision between robot and static obstacles
- No collision between robot and walking pedestrians
- Does not exceed top speed | Asher Mai |
YJ_02 | 240 | Structure Design | ## Task Description
In this task, you are required to perform a topology optimization to design an optimal cantilever beam structure that minimizes the compliance (maximizes stiffness) under a given volume constraint. The beam is fixed on the left edge and subjected to a downward load at the bottom right corner. The design domain is discretized into a uniform rectangular grid, and material is distributed in this domain to achieve the best structural performance.
## Input Parameters
### Material properties
young = 1
poisson = 0.3
#### Constraints
Emin = 1e-9
volfrac = 0.4
move = 1
#### Mesh dimensions
nelx = 10
nely = 10
## Task
Use the input parameters to set up a topology optimization problem for a cantilever beam. Your task is to:
- Simulate the optimization process.
- Ensure that the design adheres to the specified volume fraction.
- Output the final material distribution, y_hat, and report the minimal compliance value, named C_y_hat, obtained after convergence.
- y_hat must be a matrix where each element ranges from 0 to 1 inclusively.
| Yilan Jiang |
YF_01 | 483 | Structure Design | ## Task Description
In this task, you are required to determine a suitable **thickness (`Th`)** for an L-shaped steel beam, which will be subjected to a horizontal load and evaluated using 3D structural simulation in MATLAB’s PDE Toolbox.
The L-shaped beam is formed by extruding a 2D profile composed of a horizontal and vertical segment connected by a fillet arc. The extrusion occurs in the z-direction to produce a 3D object.
You are given the following fixed parameters:
- `Lh = 50` mm (Horizontal length)
- `Lv = 80` mm (Vertical length)
- `Rf = 20` mm (Fillet radius)
- `Height = 50` mm (Extrusion height)
- External surface traction: `[10, -20, 0]` N/mm² applied to Face ID = 5
- Face ID = 4 is fixed
- Material properties:
- Young’s modulus: 21,000 MPa
- Poisson’s ratio: 0.3
The beam will be evaluated using a static linear elasticity model. The performance criterion is that the **maximum displacement in the z-direction (`uz`) must be less than 0.1 mm**.
The score depends on the ratio of the maximum measured displacement to the allowable threshold. If that ratio falls between seventy percent and ninety percent, the beam earns the full 100 points. If the ratio is below seventy percent, partial credit is awarded in direct proportion to how close it is to seventy-percent (with zero displacement scoring zero and seventy-percent scoring 100). If the ratio lies between ninety percent and one hundred percent, points are deducted in proportion to how far it exceeds ninety percent (dropping from 100 at ninety percent down to zero at the full threshold). Any ratio below zero or above one hundred percent results in a score of zero.
---
### Task
Your task is to:
- Propose a structurally sound value for `Th` (thickness of the beam, in mm), you need to numerically compute the Th, not reply with your previous experience.
- Provide a brief justification for your choice of thickness, considering stiffness, loading, and geometric constraints, you must give the computation process
You do **not** need to evaluate the displacement yourself. The simulation and evaluation will be done separately.
| Yufan Zhang |
YF_06 | 431 | Structure Design | ## Task Description
In this task, you are required to determine a suitable thickness t (in mm) for a 3D rectangular steel plate of dimensions 1000×500×t mm, loaded by a uniform transverse pressure and with all four side faces fixed. The evaluation will be performed via MATLAB’s PDE Toolbox.
You are given the following fixed parameters:
Fixed parameters:
Geometry:
- Length L=1000 mm
- Width W=500 mm
- Thickness t mm (design variable)
- Material properties:
- Young’s modulus: 210,000 MPa
- Poisson’s ratio: 0.3
- Density 7850kg/m^3
- boundary condition
All four side faces (the faces at X=0, X=L, Y=0, Y=W) are fixed.
- loading
Uniform pressure p= 2 N/mm² on the top face (Z=t).
Performance criterion:
The maximum nodal displacement must satisfy δ max < 0.5 mm
The score depends on the ratio of the maximum measured deflection to the allowable threshold. If that ratio falls between seventy percent and ninety percent, the structure earns the full 100 points. If the ratio is below seventy percent, partial credit is awarded in direct proportion to how close it is to seventy-percent (with zero displacement scoring zero and seventy-percent scoring 100). If the ratio lies between ninety percent and one hundred percent, points are deducted in proportion to how far it exceeds ninety percent (dropping from 100 at ninety percent down to zero at the full threshold). Any ratio below zero or above one hundred percent results in a score of zero.
---
### Task
Your task is to:
- a numerical value of plate thickness t (in mm) that ensures 1.0 mm under the given load and boundary conditions.
- justify your choice of t, considering the plate’s bending stiffness, the applied pressure, and the geometric proportions. You need to compute the result
You do **not** need to evaluate the angle yourself. The simulation and evaluation will be done separately.
| Yufan Zhang |
qjlim2_02 | 270 | Signal Processing | ## Background
Strip dipole antennas are simple, efficient, and widely used in wireless communication systems for their broad bandwidth and omnidirectional radiation characteristics in the azimuth plane.
In this task, you are to design a strip dipole antenna that meets the specified performance objectives and constraints outlined below.
The dipole is centered at the origin and aligned along the x-axis, with its arms extending symmetrically in the ±x directions. The feed point lies at the center of the dipole, located in the x-y plane. The antenna is made of highly conductive material such as copper and is radiating in free space.
## Task Objective and Constraints
Your task is to design a Strip dipole antenna that meets the following specifications:
- Resonant Frequency: 3 GHz (S11 <= –10 dB)
- Bandwidth: >= 100 MHz
- Gain: >= 2 dBi
- Space Constraint [ Length × Width ]: <= 100 mm × 100 mm
## Design Inputs
Determine the optimal design parameters to satisfy the task objectives:
- Length of Metallic Patch in mm: length_mm
- Width of Metallic Patch in mm: width_mm
- Confidence of your design: confidence
## Additional Note
The width of the antenna should generally be at most 1/10 of the length of the antenna.
| Qi Jian Lim
|
YJ_03 | 343 | Structure Design | ## Task Description
This optimisation problem aims to minimise the Mode I stress-intensity factor (SIF) at the crack tip, thereby maximising fatigue-crack-propagation life and enhancing damage tolerance of the structural component. Material is selectively distributed within the design domain so that the resulting layout reduces the SIF while respecting a prescribed material-usage limit.
## Input Parameters
### Material properties
young = 1 # Young’s modulus (normalised)
poisson = 0.3 # Poisson’s ratio
ext_stiff = 0.0 # Stiffness of surrounding “void” (external) material
### Constraints
Emin = 1e-9 # Minimum ersatz stiffness for void elements
volfrac = 1.1 # Maximum allowable volume fraction
move = 0.25 # Maximum density change per iteration
### Mesh definition
nelx = 10 # Number of finite-element columns (x-direction)
nely = int(np.round(nelx/1.25*1.2/2))
crack_length= 2 # Initial edge-crack length in elements
## Task
Use the input parameters to set up a topology optimization problem to minimize the stress-intensity factor. Your task is to:
- Simulate the optimization process.
- Ensure that the design adheres to the specified material properties, constraints, and mesh definitions.
- Output the final material distribution, y_hat, and report the minimal stress-intensity factor, named K_y_hat, obtained after convergence.
- y_hat must be a matrix where each element ranges from 0 to 1 inclusively.
| Yilan Jiang |
DL_02 | 3,399 | Computer Architecture Design | # Solid-State Drive Design Task - Parmeter Set with Constraints
In this problem, you will finalize a set of Solid-State Drive (SSD) designs that meet the performance requirements for a specific workload type. In this problem, you need to identify an optimized parameter set that satisfy the given performance criteria under given constraints (e.g., the capacity constriants need the multiple of several parameters to stay in a given range).
## Background
The internal architecture of a typical SSD is presented in the above Figure. An SSD consists of five major components: a set of flash memory packages, an SSD controller having embedded processors like ARM, off-chip DRAM (SSD DRAM), flash controllers, and the I/O interface that includes SATA and NVMe protocols. The flash packages are organized in a hierarchical manner. Each SSD has multiple channels, and each channel can process read/write commands independently. Each channel is shared by multiple flash packages. Each package has multiple flash chips. Within each chip, there are multiple planes. Each plane includes multiple flash blocks, and each block has multiple flash pages. The page size varies in different SSDs. When a free flash page is written once, that page is no longer available for future writes until that page is erased. However, erase operation is expensive and performed at block granularity. As each flash block has limited endurance, it is important for blocks to age uniformly (i.e., wear leveling). Modern SSD controllers employ out-of-place write, GC, and wear leveling to overcome these shortcomings and maintain indirections for the address translation in their flash translation layer (FTL).
In this problem, our aim is to design SSDs that allow developers to customize SSD hardware according to the application needs.
## Task Description
SSD customers typically evaluate SSD performance using key metrics including I/O throughput, average latency and tail latency. In this section, you should optimize the given SSD configuration by tuning only the layout related parameters ("Overprovisioning_Ratio", "Flash_Channel_Count", "Chip_No_Per_Channel", "Die_No_Per_Chip", "Plane_No_Per_Die",
"Block_No_Per_Plane", "Page_No_Per_Block"). You should identify a set of these parameter that satisfy the capacity constraint (The total usable capacity, not considering the over provisioning, should be around 2TB, specifically, 1.7TB - 2.1TB) and reach the performance requirements. If the requirement cannot be reached, please answer "impossible" instead of the final parameter value. Please always provide your reasoning.
### Formal Problem Definition
Given a parameter set $S$ and a workload set $W$, tune the parameters ("Overprovisioning_Ratio", "Flash_Channel_Count", "Chip_No_Per_Channel", "Die_No_Per_Chip", "Plane_No_Per_Die",
"Block_No_Per_Plane", "Page_No_Per_Block") $s \in S$ that affects the I/O throughput, average latency or both of them for each workload $w \in W$. Specifically, address the following question:
If we want to get 20\% performance improvement on I/O throughput or on average latency comparing to the baseline configuration (see next section), while also satisfy the capacity constraint (The total capacity, not considering the over provisioning, should be around 2TB, specifically, 1.7TB - 2.1TB) how should we tune these parameters? If this is impossible, please answer "impossible" instead of providing the number and explain why. Note that the correlation between performance and parameter values are usurally not linear.
### Configuration Set
Please provide answer for each parameter listed in the table below. The third column of this table listed the baseline configuration (Samsung 983 DCT 1.92TB SSD). We provide typical values for each parameter, the tuned parameter should follow the general trend in the listed parameters (e.g., number of channels should be descrete numbers).
For convenience of reasoning, we provide all the parameters for the baseline. Please only tune the speciftied parameters ("Overprovisioning_Ratio", "Flash_Channel_Count", "Chip_No_Per_Channel", "Die_No_Per_Chip", "Plane_No_Per_Die",
"Block_No_Per_Plane", "Page_No_Per_Block") and the tuning range is specified in the listed parameters.
| Parameter Name | Description | Baseline |
|:--------------------------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|:-----------|
| PCIe_Lane_Bandwidth | The PCIe bandwidth per lane in GB/s. Typical values: 0.5, 1.0, 2.0, 4.0, 8.0. | 8.0 |
| PCIe_Lane_Count | The number of PCIe lanes. Typical values: 1, 2, 4, 8, 16. | 4 |
| HostInterface_Type | The type of host interface. Typical values: NVME, SATA. | NVME |
| IO_Queue_Depth | the length of the host-side I/O queue. Typical values: 4, 8, 16, 32, 64, 128, 256. | 16 |
| Queue_Fetch_Size | The maximum number of requests that can be served in parallel in a queue. Typical values: 4, 8, 16, 32, 64, 128, 256. | 16 |
| Data_Cache_Capacity | The size of the DRAM Data Cache in bytes. Typical values:100663296, 167772160, 234881024, 301989888, 369098752, 436207616. | 536870912 |
| Data_Cache_DRAM_Row_Size | The size of the DRAM rows in bytes. values:1024, 2048, 4096, 8192, 16384. | 4096 |
| Data_Cache_DRAM_Data_Rate | The DRAM data transfer rate in MT/s. Typical values:100, 200, 400, 800, 1600, 2133, 2400, 2666, 3200. | 800 |
| Data_Cache_DRAM_Data_Burst_Size | The number of bytes that are transferred in one DRAM burst (depends on the number of DRAM chips). Typical values: 1, 2, 4, 8, 16. | 8 |
| Data_Cache_DRAM_tRCD | The value of the timing parameter tRCD in nanoseconds used to access DRAM in the data cache. Typical values:4, 7, 14, 21, 28 | 9 |
| Data_Cache_DRAM_tCL | The value of the timing parameter tCL in nanoseconds used to access DRAM in the data cache. Typical values:4, 7, 14, 21, 28 | 9 |
| Data_Cache_DRAM_tRP | The value of the timing parameter tRP in nanoseconds used to access DRAM in the data cache. Typical values:4, 7, 14, 21, 28 | 9 |
| Address_Mapping | The logical-to-physical address mapping policy implemented in the Flash Translation Layer (FTL).Typical values: PAGE_LEVEL, HYBRID | PAGE_LEVEL |
| CMT_Capacity | The size of the SRAM/DRAM space in bytes used to cache the address mapping table (Cached Mapping Table). Typical values: 67108864, 134217728, 201326592, 268435456, 335544320, 402653184, 469762048, 536870912 | 268435456 |
| Plane_Allocation_Scheme | The scheme for plane allocation priorities (C-Channel, W-Way, D-Die, P-Plane). Typical values: CWDP, CWPD, CDWP, CDPW, CPWD, CPDW, WCDP, WCPD, WDCP, WDPC, WPCD, WPDC, DCWP, DCPW, DWCP, DWPC, DPCW, DPWC, PCWD, PCDW, PWCD, PWDC, PDCW, PDWC | CWDP |
| Overprovisioning_Ratio | The ratio of reserved storage space with respect to the available flash storage capacity. Typical values:0.126, 0.2, 0.3, 0.4, 0.5 | 0.126 |
| GC_Exect_Threshold | The threshold for starting Garbage Collection (GC). Typical values: 0.1, 0.15, 0.2, 0.25, 0.3 | 0.05 |
| GC_Block_Selection_Policy | The GC block selection policy. Typical values: GREEDY, RGA, RANDOM, RANDOM P, RANDOM PP, FIFO | GREEDY |
| Use_Copyback_for_GC | Whether GC Copyback is enabled. Typical values: true, false | false |
| Preemptible_GC_Enabled | The toggle to enable pre-emptible GC. Typical values:true, false | true |
| GC_Hard_Threshold | The threshold to stop pre-emptible GC execution. Typical values:0.1, 0.15, 0.2, 0.25, 0.3 | 1 |
| Dynamic_Wearleveling_Enabled | The toggle to enable dynamic wear-leveling. Typical values: true, false | true |
| Static_Wearleveling_Enabled | The toggle to enable static wear-leveling. Typical values: true, false | true |
| Static_Wearleveling_Threshold | The threshold for starting static wear-leveling. Typical values: 50, 60, 70, 80, 90, 100 | 100 |
| Preferred_suspend_erase_time_for_read | The reasonable time to suspend an ongoing flash erase operation in favor of a recently-queued read operation. Typical values:100000, 200000, 300000, 400000, 500000 | 100000 |
| Preferred_suspend_erase_time_for_write | The reasonable time to suspend an ongoing flash erase operation in favor of a recently-queued read operation. Typical values:100000, 200000, 300000, 400000, 500000 | 100000 |
| Preferred_suspend_write_time_for_read | The reasonable time to suspend an ongoing flash erase operation in favor of a recently-queued program operation. Typical values:100000, 200000, 300000, 400000, 500000 | 100000 |
| Flash_Channel_Count | The number of flash channels in the SSD back end. Typical values:4,6,8,10,12,14,16,18,20 | 8 |
| Flash_Channel_Width | The width of each flash channel in byte. Typical values:1, 2, 4, 8 | 8 |
| Channel_Transfer_Rate | The transfer rate of flash channels in the SSD back end in MT/s. Typical values:100, 200, 333, 800 | 800 |
| Chip_No_Per_Channel | The number of flash chips attached to each channel in the SSD back end. Typical values:2, 4, 8, 12, 16, 20 | 4 |
| Flash_Technology | Typical values:TLC, MLC, SLC | MLC |
| CMD_Suspension_Support | The type of suspend command support by flash chips. Typical values:NONE, PROGRAM, PROGRAM ERASE, ERASE | None |
| Page_Read_Latency_LSB | The latency of reading LSB bits of flash memory cells in nanoseconds. Typical values:25000, 50000, 59975, 75000, 100000 | 5000 |
| Page_Read_Latency_CSB | Similar as above. Typical values:0, 25000, 50000, 75000, 100000 | 0 |
| Page_Read_Latency_MSB | Similar as above. Typical values:25000, 50000, 75000, 100000, 104956 | 10000 |
| Page_Program_Latency_LSB | Similar as above. Typical values:82062, 250000, 500000, 750000, 1000000 | 30000 |
| Page_Program_Latency_CSB | Similar as above. Typical values:0, 250000, 500000, 750000, 1000000 | 0 |
| Page_Program_Latency_MSB | Similar as above. Typical values:250000, 500000, 750000, 1000000, 1250000, 1500000, 1750000, 2000000, 2250000 | 800000 |
| Block_Erase_Latency | The latency of erasing a flash block in nanoseconds.Typical values:3000000, 3800000 | 1000000 |
| Block_PE_Cycles_Limit | The PE limit of each flash block. Typical values:10000, 20000, 30000, 40000, 50000 | 10000 |
| Suspend_Erase_Time | The time taken to suspend an ongoing erase operation in nanoseconds.Typical values:700000, 800000, 900000, 1000000, 1100000 | 700000 |
| Suspend_Program_Time | The time taken to suspend an ongoing program operation in nanoseconds. Typical values:60000, 70000, 80000, 90000, 100000 | 100000 |
| Die_No_Per_Chip | The number of dies in each flash chip. Typical values:4,6,8, 10, 12, 14, 16, 18, 20 | 8 |
| Plane_No_Per_Die | The number of planes in each die. Typical values:2,4,6,8,10 | 2 |
| Block_No_Per_Plane | The number of flash blocks in each plane. Typical values:512,1024,1364, 2048, 4096, 8192 | 1364 |
| Page_No_Per_Block | The number of physical pages in each flash block. Typical values:512, 768, 1024, 2048, 4096 | 768 |
| Page_Capacity | The size of each physical flash page in bytes. Typical values:4096 | 4096 |
| Page_Metadat_Capacity | The size of the metadata area of each physical flash page in bytes. Typical values:224, 448, 672, 896, 1120 | 448 |
### Target Workload Set
Please provide answer for each workload mentioned below:
#### Real-world Workloads
These workloads represents typical storage-intensive application patterns.
| **Workload Category** | **Description** |
|-----------------------|-----------------|
| Big Data Analytics | MapReduce workloads running in data centers. |
| Cloud Storage | Cloud storage workloads running in data centers. |
| Key-Value Store | YCSB benchmarks are executed against RocksDB. |
| Maps | Maps workloads running on enterprise servers. |
| Database | TPCC/TPCH executed against Windows SQL Server. |
| WebSearch | WebSearch services trace from UMassTraceRepository. |
| Advertisement | Advertisement workloads running on servers. |
## Response Instruction
Your response should be structured in the following format:
For each workload, create a workload_result class for the tuning result. In each workload_result, you should specify the parameters based on the values we provided.
Please strictly follow the format, do not include any other text or comments.
| Daixuan Li |
AM_02 | 938 | Robotics | ## Task Description
Your task is to navigate two robots around static obstacles and walking pedestrians.
The map is a 30 by 30 grid. The origin, i.e. (x,y) = (0,0), is at the bottom left of the grid.
x-axis grows to the right and y-axis grows upwards.
There are three static obstacles formatted in ((x1, y1), (x2, y2)) that describe the
bottom left and top right corners of the rectangular obstacles:
THe four corners that define the static obstacles are:
[
((5, 0), (7, 15)),
((10,20), (20,30)),
((15, 5), (30, 10))
]
There are pedestrians walking around and their trajectory is
stored as a list of tuples (t, x, y), where t is number of seconds from 0 to 19,
and x and y are the coordinates of the bottom left corner in the grid.
The pedestrians and robots are both 2 by 2 in size.
Their paths are as follows:
'ped1': [ (0,1,1),
(1,1,2),
(2,1,4),
(3,1,6),
(4,1,7),
(5,1,9),
(6,1,11),
(7,2,13),
(8,2,14),
(9,3,16),
(10,6,16),
(11,7,15),
(12,8,13),
(13,9,12),
(14,10,11),
(15,11,10),
(16,12,9),
(17,12,8),
(18,12,7),
(19,12,6)
],
'ped2': [ (0,25,28),
(1,25,28),
(2,25,26),
(3,25,24),
(4,25,22),
(5,25,20),
(6,25,18),
(7,25,16),
(8,25,14),
(9,24,12),
(10,22,12),
(11,20,12),
(12,19,12),
(13,17,12),
(14,16,12),
(15,16,12),
(16,15,13),
(17,14,15),
(18,12,16),
(19,10,16)
],
'ped3': [ (0, 25, 2),
(1, 24, 2),
(2, 23, 2),
(3, 22, 2),
(4, 21, 2),
(5, 20, 2),
(6, 19, 2),
(7, 18, 2),
(8, 17, 2),
(9, 16, 2),
(10,15,2),
(11,14,2),
(12,13,2),
(13,12,2),
(14,11,2),
(15,10,2),
(16,9,3),
(17,8,4),
(18,8,6),
(19,8,8)
]
The start and end positions for the first robot are (17, 2) and (5, 24).
The start and end positions for the second robot are (5, 25) and (25, 25).
You must provide two lists of tuples in (t,x,y) format that is free of collisions from
both pedestrians and static rectangular obstacles.
The speed limit of robot in either x and y direction is 2 between each time step.
This means that the robot can move in the x direction 2 steps and y direction 2 steps and be ok.
Make sure you navigate around both the walking pedestrians and static obstacles.
You will be evaluated on the following for each of the two robots:
- Starting position at t=0 is correct
- Ending position at t=19 is correct
- No collision between robot and static obstacles
- No collision between robot and walking pedestrians
- Does not exceed top speed | Asher Mai |
YZ_01 | 511 | Signal Processing | ## Task Description
In this task, you are required to design a multi-stage sample rate converter for an LTE receiver. The converter must reduce various input sample rates (for example, 125, 140, or 150 Msps) down to a lower baseband rate while meeting specific passband and stopband requirements. The converter is implemented as a three-stage filter chain. In the first stage, a Farrow rate converter makes a fine adjustment to the sample rate by a predefined factor. The signal is then processed by two decimating FIR filters in the subsequent stages. Your goal is to determine the appropriate parameters for each stage to satisfy the LTE signal integrity constraints.
### Task 1
Your first task is to specify the top level parameters given the input rate FsADC = 150 MHz and the output rate FsLTERx = 30.72 MHz. The parameters and their requirements are as follows:
#### Parameters:
- Fpass, the passband cutoff frequency that accommodates the maximum possible LTE bandwidth of 10 MHz.
- Fstop, typically the Nyquist rate $\frac{FsLTERx}{2}$, can be adjusted if more out-of-band signal rejection is required.
- Ast, the stopband attenuation in dBs.
- Ap, the desired passband ripple.
### Task 2
Your second task is to determine the reduction factors(Factor_1 and Factor_2, both of which are integers greater than one) for the last two decimating FIR filters. First, the Farrow rate converter should be placed as far from the Nyquist bandwidth as possible. Next, verify that the converter meets the LTE requirements by confirming that the Error Vector Magnitude (EVM) remains within acceptable limits. The MATLAB code below calculates the EVM:
<code_block>
results.floatPointSRCEVM = SRCTestUtils.MeasureEVM(sigInfo,floatResamplerOut,FsLTERx);
disp([' floating point SRC RMS EVM: ' num2str(results.floatPointSRCEVM.RMS*100,3) ' %']);
disp([' floating point SRC Peak EVM: ' num2str(results.floatPointSRCEVM.Peak*100,3) ' %']);
</code_block>
the following requirements need to be satisfied:
- floating point SRC RMS EVM: <= 0.03%
- floating point SRC Peak EVM: <= 0.07%
- Factor_2 * FsLTERx - 2 * Fpass: > 0 MHz
| Yizhou Zhao |
XZ_01 | 395 | Robotics | ## Task Description
You are given a 2D gridmap of a construction site, where each node is represented as a triplet (x, y, 0/1). This map follows the specifications below:
-The construction site spans an area that is 50 meters wide and 40 meters long.
-Each grid cell is 1 meter × 1 meter.
-The bottom-left corner of the site map corresponds to world coordinates (0, 0).
-The value 0 or 1 in (x, y, 0/1) represents: A value of 1 denotes an obstacle (construction material, equipment, barricade, etc.), while a 0 indicates traversable space.
A small inspection robot's starting position is at the site entrance (0,0,0), and we set the goal position to the far corner inspection point (49,39,0). Suppose this inspection robot can only navigate on grid nodes (i.e., x and y values are integers). Find the shortest way from the entrance to the inspection point without hitting any obstacles.
The construction site contains the following obstacles:
-A vertical wall from (10,5) to (10,35)
-A horizontal wall from (10,20) to (40,20)
-A vertical wall from (30,0) to (30,15)
-A cluster of obstacles in the region from (20,25) to (25,30)
-Several random obstacles at: (15,10), (25,5), (35,25), (40,30), (45,15)
## Required Results:
1. The complete path as an ordered list of coordinates from start to goal
2. The total path length (in meters)
3. The algorithm used (A*, Dijkstra, etc.)
4. The number of nodes explored during the search
5. Whether 4-connected or 8-connected movement was used
6. Execution time of the algorithm
| Xiayu Zhao
|
qjlim2_04 | 290 | Signal Processing | ----------
Background
----------
Cylindrical monopole antennas are vertically oriented antennas commonly used for broadband and omnidirectional communication in the azimuth plane. They are typically placed over a large ground plane and function as a half-wave dipole with one arm mirrored by the ground.
In this task, you are to design a cylindrical monopole antenna that meets the specified performance objectives and constraints outlined below.
The monopole is centered at the origin and aligned along the z-axis, extending vertically from the ground plane. The antenna is made of a highly conductive material such as copper and radiates in free space. It is mounted on a perfectly conducting square ground plane of size 300 m × 300 m and is fed using a 70-ohm lumped port at its base.
------------------------------
Task Objective and Constraints
------------------------------
Your task is to design a cylindrical monopole antenna that meets the following specifications:
Resonant Frequency: 0.487 GHz (S11 ≤ –10 dB)
Bandwidth: ≥ 10 MHz
Gain: ≥ 0 dBi
-------------
Design Inputs
-------------
Determine the optimal design parameters to satisfy the task objectives:
Height of cylindrical monopole in mm: height_mm
Radius of cylindrical monopole in mm: radius_mm
Confidence of your design: confidence
----------------
Additional Note
----------------
The radius of the antenna should generally be at most 1/20 of the length of the antenna.
| Qi Jian Lim |
TB_05 | 547 | Analog Integrated Circuit Design | ## Task Description (Sizing Only)
You are asked to design a Common-Source amplifier topology with a resistive load. The amplifier consists of an NMOS transistor, a load resistor RL, and an ideal voltage source VGS. The goal is to meet the given small-signal and DC specifications using simulation.
The output should be only the TEMPLATE format provided under, which is a SPICE-format netlist used in Cadence for evaluation. You may only adjust the parameters of NMOS( W1, L1, M1), the parameters of R0 (R0, M0) and V0.
The amplifier must meet the following specs under CL = 2 pF and VDD = 1.8 V:
Testbench Configuration
The testbench is a unity-gain buffer connection (feedback from output vout to inverting input vin).
### Task 1 — Device Sizing
**Process Rule**
All MOSFETs must instantiate **exactly** the foundry models
`tsmc18dP` (PMOS) and `tsmc18dN` (NMOS).
### Task 2 — Performance Verification
Using the provided Cadence/SPECTRE testbench, verify that your OTA design satisfies the following specifications:
| Parameter | Spec Target |
|----------------|---------------------|
| DC Gain | −5 V/V ± 2% |
| 3 dB Bandwidth | ≥ 50 Mrad/s |
| Output Voltage | 900 mV ± 2% |
---
### <TEMPLATE>
```spice
// Library name: MP1
// Cell name: cs_amp
// View name: schematic
subckt cs_amp VDD VSS vin_a vin_b vout
NO (vout vin_a VSS VSS) tsmc18dN w=W1 l=L1M as=W1 * 2.5 * (180.0n) ad=W1 * 2.5 * (180.0n) \
ps=(2 * W1) + (5 * (180.0n)) pd=(2 * W1) + (5 * (180.0n)) m=M1 \
region=sat
V0 (vin_b VSS) vsource type=dc dc=V0
R0 (VDD vout) resistor r=R0 m=M0
ends cs_amp
// End of subcircuit definition.
// Library name: MP1
// Cell name: dut
// View name: schematic
I0 (net1 net2 net3 net4 net5) cs_amp
| Tianle Sang & Beixiao Zhu |
TB_03 | 1,103 | Analog Integrated Circuit Design | ## Task Description (OTA Sizing Only)
You are given a 5-transistor differential-to-single-ended OTA topology whose schematic has already been instantiated.
The full netlist is shown in the code block **<OTA_TEMPLATE>** below, where every
MOSFET width/length placeholder appears as symbols `W0…`, `L0…`, etc.
The output should be only the OTA_TEMPLATE format provided under.
### Task 1 — Device Sizing
**Process Rule**
All MOSFETs must instantiate **exactly** the foundry models
`tsmc18dP` (PMOS) and `tsmc18dN` (NMOS).
You **may only adjust** the parameters `W`, `L`, and `m` (multiplier).
Do **not** edit or override any other model settings, corners, or temperatures.
Replace every `W*`, `L*`, and `M*` placeholder in the template with concrete numeric
values (µm or Ω) so that the design meets the required performance.
**Do not** change device connectivity, add/delete devices, or alter pin names.
Task 2 — Performance Verification
Using the provided Cadence/SPECTRE testbench (differential input OTA, CL = 2 pF, VDD = 1.4 V, VSS = 0 V), verify that your OTA design satisfies the following specifications:
| Spec | Target |
|-------------------------------|-------------------------|
| DC differential-mode gain AV0 | ≥ 40 dB |
| Unity-gain frequency fUGF | ≥ 50 MHz |
| Common-mode rejection ratio CMRR | ≥ 80 dB |
| Input common-mode range ICMR | ≥ 800 mV* |
*ICMR pass rule: for VCM ∈ {VSS, VDD}, each point must achieve
fUGF(VCM) ≥ 50 MHz, AV(VCM) ≥ AV0 − 3 dB, and CMRR(VCM) ≥ CMRR0 − 3 dB,
where AV0 and CMRR0 are the values measured at a nominal VCM.
---
### <OTA_TEMPLATE>
```spice
// Library name: MP3
// Cell name: ota
// View name: schematic
subckt ota VDD VSS ibp10u vin vip vout
N3 (ibp10u ibp10u VSS VSS) tsmc18dN w=30.015u l=3.015u as=1.35068e-11 \
ad=1.35068e-11 ps=60.93u pd=60.93u m=M3 region=sat
N2 (net7 ibp10u VSS VSS) tsmc18dN w=480.015u l=3.015u as=2.16007e-10 \
ad=2.16007e-10 ps=960.93u pd=960.93u m=M2 region=sat
N5 (vout vin net7 net7) tsmc18dN w=W5 l=L5 as=W5 * 2.5 * (180.0n) ad=W5 * 2.5 * (180.0n) \
ps=(2 * W5) + (5 * (180.0n)) pd=(2 * W5) + (5 * (180.0n)) m=M5 \
region=sat
N4 (net8 vip net7 net7) tsmc18dN w=W4 l=L4 as=W4 * 2.5 * (180.0n) ad=W4 * 2.5 * (180.0n) \
ps=(2 * W4) + (5 * (180.0n)) pd=(2 * W4) + (5 * (180.0n)) m=M4 \
region=sat
P1 (net8 net8 VDD VDD) tsmc18dP w=W1 l=L1 as=W1 * 2.5 * (180.0n) ad=W1 * 2.5 * (180.0n) \
ps=(2 * W1) + (5 * (180.0n)) pd=(2 * W1) + (5 * (180.0n)) m=M1 \
region=sat
P0 (vout net8 VDD VDD) tsmc18dP w=W0 l=L0 as=W0 * 2.5 * (180.0n) ad=W0 * 2.5 * (180.0n) \
ps=(2 * W0) + (5 * (180.0n)) pd=(2 * W0) + (5 * (180.0n)) m=M0 \
region=sat
ends ota
// End of subcircuit definition.
// Library name: MP3
// Cell name: dut
// View name: schematic
I16 (net1 net2 net6 net4 net3 net5) ota
| Tianle Sang & Beixiao Zhu |
TB_04 | 1,129 | Analog Integrated Circuit Design | ## Task Description
You are asked to design a 5 transistor OTA topology and its bias current circuit in one netlist.
The output should be the same format as the ### <TEMPLATE> provided under. Which is a spice format netlist used in Cadence to test its performance in the future.
The template shows the name and port of different components and connection between them, but it is not the correct structure for this OTA task. You should create a different netlist to solve this problem.
Testbench Configuration
The testbench is a unity-gain buffer connection (feedback from output vout to inverting input vin).
VDD = 1.4 V
VSS = 0 V
Output load: CL = 2 pF capacitor at vout.
A DC current source IB = 10μA is connected to the OTA's bias input ibp10u.
A small-signal AC source VSTB is applied to vin for AC analysis.
A DC voltage sweep (Vstep + VCM) is used at vip
### Task 1 — Device Sizing
**Process Rule**
All MOSFETs must instantiate **exactly** the foundry models
`tsmc18dP` (PMOS) and `tsmc18dN` (NMOS).
### Task 2 — Performance Verification
Using the provided Cadence/SPECTRE testbench (differential input OTA, CL = 2 pF, VDD = 1.4 V, VSS = 0 V), verify that your OTA design satisfies the following specifications:
| Spec | Target |
|-------------------------------|-------------------------|
| DC differential-mode gain AV0 | ≥ 40 dB |
| Unity-gain frequency fUGF | ≥ 50 MHz |
| Common-mode rejection ratio CMRR | ≥ 80 dB |
| Input common-mode range ICMR | ≥ 800 mV* |
*ICMR pass rule: for VCM ∈ {VSS, VDD}, each point must achieve
fUGF(VCM) ≥ 50 MHz, AV(VCM) ≥ AV0 − 3 dB, and CMRR(VCM) ≥ CMRR0 − 3 dB,
where AV0 and CMRR0 are the values measured at a nominal VCM.
---
### <TEMPLATE>
```spice
// Library name: MP3
// Cell name: ota
// View name: schematic
subckt ota VDD VSS ibp10u vin vip vout
N3 (ibp10u ibp10u VSS VSS) tsmc18dN w=30.015u l=3.015u as=1.35068e-11 \
ad=1.35068e-11 ps=60.93u pd=60.93u m=M3 region=sat
N2 (net7 ibp10u VSS VSS) tsmc18dN w=480.015u l=3.015u as=2.16007e-10 \
ad=2.16007e-10 ps=960.93u pd=960.93u m=M2 region=sat
N5 (vout vin net7 net7) tsmc18dN w=W5 l=L5 as=W5 * 2.5 * (180.0n) ad=W5 * 2.5 * (180.0n) \
ps=(2 * W5) + (5 * (180.0n)) pd=(2 * W5) + (5 * (180.0n)) m=M5 \
region=sat
N4 (net8 vip net7 net7) tsmc18dN w=W4 l=L4 as=W4 * 2.5 * (180.0n) ad=W4 * 2.5 * (180.0n) \
ps=(2 * W4) + (5 * (180.0n)) pd=(2 * W4) + (5 * (180.0n)) m=M4 \
region=sat
P1 (net8 net8 VDD VDD) tsmc18dP w=W1 l=L1 as=W1 * 2.5 * (180.0n) ad=W1 * 2.5 * (180.0n) \
ps=(2 * W1) + (5 * (180.0n)) pd=(2 * W1) + (5 * (180.0n)) m=M1 \
region=sat
P0 (vout net8 VDD VDD) tsmc18dP w=W0 l=L0 as=W0 * 2.5 * (180.0n) ad=W0 * 2.5 * (180.0n) \
ps=(2 * W0) + (5 * (180.0n)) pd=(2 * W0) + (5 * (180.0n)) m=M0 \
region=sat
ends ota
// End of subcircuit definition.
// Library name: MP3
// Cell name: dut
// View name: schematic
I16 (net1 net2 net6 net4 net3 net5) ota
| Tianle Sang & Beixiao Zhu |
YH_01 | 385 | Digital Hardware Design | Write a Vivado HLS-compatible C++ function called gemm that performs matrix multiplication C = A * B where A is of size M×K, B is of size K×N, and C is of size M×N. Set M = N = K = 256. Implement tiling with block sizes TM = TN = TK = 64 to optimize data movement and reuse. Include the headers hls_stream.h, ap_int.h, and ap_axi_sdata.h for Vivado HLS compatibility. Use a tiled loop structure across the M, N, and K dimensions. For local storage, use on-chip buffers localA[TM][TK], localB[TK][TN], and localC[TM][TN]. Partition localA across dimension 2, localB across dimension 1, and localC fully across all dimensions, as required to achieve an initiation interval (II) of 1 in the innermost loops. Apply #pragma HLS PIPELINE II=1 to the inner loops to maximize throughput. Do not manually apply #pragma HLS UNROLL, because achieving II=1 with pipelining will automatically imply sufficient unrolling when the array partitioning is properly done. Assign appropriate Vivado HLS interface pragmas: use m_axi interfaces for A, B, and C arrays, each mapped to different memory bundles (gmem0, gmem1, gmem2 respectively), and assign s_axilite interfaces for A, B, C, and return control ports to allow CPU control. Insert a #pragma HLS DATAFLOW pragma to allow overlap of memory access and computation phases through streaming/pipelining. Function signature: void gemm(float A[M_SIZE][K_SIZE], float B[K_SIZE][N_SIZE], float C[M_SIZE][N_SIZE]). Optimize the model so that it maximizes the number of DSPs in the VCK5000. | Yingbing Huang, Greg Jun |
TB_02 | 1,068 | Analog Integrated Circuit Design | ## Task Description (FC‑OTA Sizing Only)
You are asked to design a folded‑cascode OTA topology including the folded-cascode and its bias current.
The output should be the same format as the ### <TEMPLATE> provided under. Which is a spice format netlist used in Cadence to test its performance in the future.
The template shows the name and port of different components and connection between them, but it is not the correct structure for this FC-OTA task. You should create a different netlist to solve this problem.
Testbench Configuration
The testbench is a unity-gain buffer connection (feedback from output vout to inverting input vin).
VDD = 1.4 V
VSS = 0 V
Output load: CL = 1 pF capacitor at vout.
A DC current source IB = 10μA is connected to the OTA's bias input ibn10u.
A small-signal AC source VSTB is applied to vin for AC analysis.
A DC voltage sweep (Vstep + VCM) is used at vip to verify input common-mode range (ICMR).
### Task 1 — Device Sizing
**Process Rule**
All MOSFETs must instantiate **exactly** the foundry models
`tsmc18dP` (PMOS) and `tsmc18dN` (NMOS).
### Task 2 — Performance Verification
Using the provided Cadence/SPECTRE testbench (unity‑gain buffer, CL = 1 pF, VDD = 1.4 V,
VCM = 600 mV), verify that the sized design satisfies:
| Spec | Target |
|------|--------|
| DC gain AV0 | ≥ 60 dB |
| Unity‑gain frequency fUGF | ≥ 50 MHz |
| Phase margin PM | ≥ 60° |
| DC input‑to‑output error \|vip,DC – vout,DC\| | ≤ 0.6 mV |
| Total DC current | ≤ 150 µA |
| Input common‑mode range (ICMR) | ≥ 600 mV* |
\*ICMR pass rule: for VCM ∈ {VSS, VSS+25 mV, …, VDD‑25 mV}, each point must achieve
AV0 ≥ 50 dB, fUGF ≥ 40 MHz, PM ≥ 45°, and \|vip,DC – vout,DC\| ≤ 1.8 mV.
---
### <TEMPLATE>
```spice
// Library name: mp_4
// Cell name: ota
// View name: schematic
subckt ota VDD VSS ibp10u vin vip vout
N3 (ibp10u ibp10u VSS VSS) tsmc18dN w=3u l=3u as=1.8e-12 ad=1.8e-12 \
ps=7.2u pd=7.2u m=1 region=sat
N5 (vout vin net2 net2) tsmc18dN w=600.0000u l=1.8u as=3.6e-10 \
ad=3.6e-10 ps=1.2012m pd=1.2012m m=1 region=sat
N1 (net2 ibp10u VSS VSS) tsmc18dN w=70.02u l=3u as=4.2012e-11 \
ad=4.2012e-11 ps=141.24u pd=141.24u m=1 region=sat
N4 (net4 vip net2 net2) tsmc18dN w=600.0000u l=1.8u as=3.6e-10 \
ad=3.6e-10 ps=1.2012m pd=1.2012m m=1 region=sat
P1 (net4 net4 VDD VDD) tsmc18dP w=180.00000u l=1.8u as=1.08e-10 \
ad=1.08e-10 ps=361.2u pd=361.2u m=1 region=sat
P0 (vout net4 VDD VDD) tsmc18dP w=180.00000u l=1.8u as=1.08e-10 \
ad=1.08e-10 ps=361.2u pd=361.2u m=1 region=sat
ends ota
// End of subcircuit definition.
// Library name: mp_4
// Cell name: dut
// View name: schematic
I0 (net6 net1 net4 net3 net2 net5) ota
| Tianle Sang & Beixiao Zhu |
YH_02 | 386 | Digital Hardware Design | Write a Vivado HLS-compatible C++ function called gemm that performs matrix multiplication C = A * B where A is of size M×K, B is of size K×N, and C is of size M×N. Set M = N = K = 1024. Implement tiling with block sizes TM = TN = TK = 128 to optimize data movement and reuse. Include the headers hls_stream.h, ap_int.h, and ap_axi_sdata.h for Vivado HLS compatibility. Use a tiled loop structure across the M, N, and K dimensions. For local storage, use on-chip buffers localA[TM][TK], localB[TK][TN], and localC[TM][TN]. Partition localA across dimension 2, localB across dimension 1, and localC fully across all dimensions, as required to achieve an initiation interval (II) of 1 in the innermost loops. Apply #pragma HLS PIPELINE II=1 to the inner loops to maximize throughput. Do not manually apply #pragma HLS UNROLL, because achieving II=1 with pipelining will automatically imply sufficient unrolling when the array partitioning is properly done. Assign appropriate Vivado HLS interface pragmas: use m_axi interfaces for A, B, and C arrays, each mapped to different memory bundles (gmem0, gmem1, gmem2 respectively), and assign s_axilite interfaces for A, B, C, and return control ports to allow CPU control. Insert a #pragma HLS DATAFLOW pragma to allow overlap of memory access and computation phases through streaming/pipelining. Function signature: void gemm(float A[M_SIZE][K_SIZE], float B[K_SIZE][N_SIZE], float C[M_SIZE][N_SIZE]). Optimize the model so that it maximizes the number of DSPs in the VCK5000. | Yingbing Huang, Greg Jun |
TB_01 | 2,136 | Analog Integrated Circuit Design | ## Task Description (FC‑OTA Sizing Only)
You are given a folded‑cascode OTA topology whose schematic has already been instantiated.
The full netlist is shown in the code block **<FC_OTA_TEMPLATE>** below, where every
MOSFET width/length placeholder appears as symbols `W0…W17`, `L0…L17`, etc.
The output should be only the FC_OTA_TEMPLATE format provided under.
### Task 1 — Device Sizing
**Process Rule**
All MOSFETs must instantiate **exactly** the foundry models
`tsmc18dP` (PMOS) and `tsmc18dN` (NMOS).
You **may only adjust** the parameters `W`, `L`, and `m` (multiplier).
Do **not** edit or override any other model settings, corners, or temperatures.
Replace every `W*`, `L*`, `R*`, and `M*` placeholder in the template with concrete numeric
values (µm or Ω) so that the design meets the required performance.
**Do not** change device connectivity, add/delete devices, or alter pin names.
### Task 2 — Performance Verification
Using the provided Cadence/SPECTRE testbench (unity‑gain buffer, CL = 1 pF, VDD = 1.4 V,
VCM = 600 mV), verify that the sized design satisfies:
| Spec | Target |
|------|--------|
| DC gain AV0 | ≥ 60 dB |
| Unity‑gain frequency fUGF | ≥ 50 MHz |
| Phase margin PM | ≥ 60° |
| DC input‑to‑output error \|vip,DC – vout,DC\| | ≤ 0.6 mV |
| Total DC current | ≤ 150 µA |
| Input common‑mode range (ICMR) | ≥ 600 mV* |
\*ICMR pass rule: for VCM ∈ {VSS, VSS+25 mV, …, VDD‑25 mV}, each point must achieve
AV0 ≥ 50 dB, fUGF ≥ 40 MHz, PM ≥ 45°, and \|vip,DC – vout,DC\| ≤ 1.8 mV.
---
### <FC_OTA_TEMPLATE>
```spice
// Library name: MP4
// Cell name: fc_ota
// View name: schematic
.subckt fc_ota VDD VSS ibn10u vin vip vout
* --- PMOS devices ---
P17 (BP2 ibn10u net22 VDD) tsmc18dP w=W17 l=L17 as=W17*2.5*(180n) ad=W17*2.5*(180n) ps=(2*W17)+(5*180n) pd=(2*W17)+(5*180n) m=M17 region=sat
P0 (net1 BP2 VDD VDD) tsmc18dP w=W0 l=L0 as=W0 *2.5*(180n) ad=W0 *2.5*(180n) ps=(2*W0 )+(5*180n) pd=(2*W0 )+(5*180n) m=M0 region=sat
P16 (net22 BP2 VDD VDD) tsmc18dP w=W16 l=L16 as=W16*2.5*(180n) ad=W16*2.5*(180n) ps=(2*W16)+(5*180n) pd=(2*W16)+(5*180n) m=M16 region=sat
P13 (BN2 ibn10u net18 VDD) tsmc18dP w=W13 l=L13 as=W13*2.5*(180n) ad=W13*2.5*(180n) ps=(2*W13)+(5*180n) pd=(2*W13)+(5*180n) m=M13 region=sat
P12 (net18 BP2 VDD VDD) tsmc18dP w=W12 l=L12 as=W12*2.5*(180n) ad=W12*2.5*(180n) ps=(2*W12)+(5*180n) pd=(2*W12)+(5*180n) m=M12 region=sat
P1 (net12 ibn10u net1 VDD)tsmc18dP w=W1 l=L1 as=W1 *2.5*(180n) ad=W1 *2.5*(180n) ps=(2*W1 )+(5*180n) pd=(2*W1 )+(5*180n) m=M1 region=sat
P3 (net3 vip net12 VDD) tsmc18dP w=W3 l=L3 as=W3 *2.5*(180n) ad=W3 *2.5*(180n) ps=(2*W3 )+(5*180n) pd=(2*W3 )+(5*180n) m=M3 region=sat
P2 (net4 vin net12 VDD) tsmc18dP w=W2 l=L2 as=W2 *2.5*(180n) ad=W2 *2.5*(180n) ps=(2*W2 )+(5*180n) pd=(2*W2 )+(5*180n) m=M2 region=sat
P7 (vout ibn10u net16 VDD)tsmc18dP w=W7 l=L7 as=W7 *2.5*(180n) ad=W7 *2.5*(180n) ps=(2*W7 )+(5*180n) pd=(2*W7 )+(5*180n) m=M7 region=sat
P6 (net2 ibn10u net13 VDD)tsmc18dP w=W6 l=L6 as=W6 *2.5*(180n) ad=W6 *2.5*(180n) ps=(2*W6 )+(5*180n) pd=(2*W6 )+(5*180n) m=M6 region=sat
P5 (net16 net2 VDD VDD) tsmc18dP w=W5 l=L5 as=W5 *2.5*(180n) ad=W5 *2.5*(180n) ps=(2*W5 )+(5*180n) pd=(2*W5 )+(5*180n) m=M5 region=sat
P4 (net13 net2 VDD VDD) tsmc18dP w=W4 l=L4 as=W4 *2.5*(180n) ad=W4 *2.5*(180n) ps=(2*W4 )+(5*180n) pd=(2*W4 )+(5*180n) m=M4 region=sat
* --- NMOS devices ---
N15 (net11 BN1 VSS VSS) tsmc18dN w=W15 l=L15 as=W15*2.5*(180n) ad=W15*2.5*(180n) ps=(2*W15)+(5*180n) pd=(2*W15)+(5*180n) m=M15 region=sat
N14 (BN1 BN2 net11 VSS) tsmc18dN w=W14 l=L14 as=W14*2.5*(180n) ad=W14*2.5*(180n) ps=(2*W14)+(5*180n) pd=(2*W14)+(5*180n) m=M14 region=sat
N11 (net4 BN1 VSS VSS) tsmc18dN w=W11 l=L11 as=W11*2.5*(180n) ad=W11*2.5*(180n) ps=(2*W11)+(5*180n) pd=(2*W11)+(5*180n) m=M11 region=sat
N10 (net3 BN1 VSS VSS) tsmc18dN w=W10 l=L10 as=W10*2.5*(180n) ad=W10*2.5*(180n) ps=(2*W10)+(5*180n) pd=(2*W10)+(5*180n) m=M10 region=sat
N9 (vout BN2 net4 VSS) tsmc18dN w=W9 l=L9 as=W9 *2.5*(180n) ad=W9 *2.5*(180n) ps=(2*W9 )+(5*180n) pd=(2*W9 )+(5*180n) m=M9 region=sat
N8 (net2 BN2 net3 VSS) tsmc18dN w=W8 l=L8 as=W8 *2.5*(180n) ad=W8 *2.5*(180n) ps=(2*W8 )+(5*180n) pd=(2*W8 )+(5*180n) m=M8 region=sat
* --- Passive devices ---
R1 (BP2 ibn10u) resistor r=R1 m=MR1
R0 (BN2 BN1) resistor r=R0 m=MR0
.ends fc_ota
// Top‑level instantiation
// Library name: MP4
// Cell name: dut
// View name: schematic
I1 (net1 net2 net5 net3 net4 net6) fc_ota
| Tianle Sang & Beixiao Zhu |
YH_04 | 206 | Digital Hardware Design | Write a synthesizable C function for matrix multiplication (GEMM) using Vitis HLS, with the following specifications:
• Function signature: void gemm(float A[M_SIZE][K_SIZE], float B[K_SIZE][N_SIZE], float C[M_SIZE][N_SIZE])
• Use #define for M_SIZE, N_SIZE, and K_SIZE as 256.
• Perform the matrix multiplication: C = A \times B
• Apply the following interface pragmas for HLS:
• Use AXI4 master interfaces (m_axi) for matrices A, B, and C (with separate bundles for each).
• Use an AXI4-Lite slave interface (s_axilite) for function control and return.
• Add #pragma HLS PIPELINE II=1 to pipeline the innermost loop for high throughput.
• Ensure the code is synthesizable with Vitis HLS and suitable for implementation on the VCK5000 board | Yingbing Huang, Greg Jun |
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