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/********************\r
* Filename: parameters.v\r
* Description: Parameters for Packet FLITS\r
* $Revision: 21 $\r
* $Id: parameters.v 21 2015-11-21 10:54:06Z ranga $\r
* $Date: 2015-11-21 12:54:06 +0200 (Sat, 21 Nov 2015) $\r
* $Author: ranga $\r
*********************/\r
\r
// defining the flit ID -- One hot encoding\r
`define HEADER 3'b001\r
`define PAYLOAD 3'b010\r
`define TAIL 3'b100\r
\r
// Specifying the FIFO parameters\r
`define FIFO_DEPTH 'd4 // 4 flits capacity\r
`define PTR_SIZE `FIFO_DEPTH // Controls reading and writing (for full and empty) >> Depends on the FIFO_DEPTH\r
`define DATA_WIDTH 'd32 // # of data bits with parity |
/********************
* Filename: state_defines.v
* Description: definitions of the possibile values for the arbiter state variable
one-hot encoding considered
* $Revision: 21 $
* $Id: state_defines.v 21 2015-11-21 10:54:06Z ranga $
* $Date: 2015-11-21 12:54:06 +0200 (Sat, 21 Nov 2015) $
* $Author: ranga $
*********************/
`define IDLE 6'b000001
`define GRANT_L 6'b000010
`define GRANT_N 6'b000100
`define GRANT_E 6'b001000
`define GRANT_W 6'b010000
`define GRANT_S 6'b100000
`define L_PORT 5'b00001
`define N_PORT 5'b00010
`define E_PORT 5'b00100
`define W_PORT 5'b01000
`define S_PORT 5'b10000 |
/********************
* Filename: arbiter.v
* Description: Packets with the same priority and destined for the same output port are scheduled with a round-robin arbiter with the last served as least priority.
Priority direction Local, North, East, South, West
Maintains the priority till it reads the TAIL flit
One-hot encoding for state variable
Output values [5:0]: Output[5:1] -> selection, Output[0] -> idle
*
* $Revision: 26 $
* $Id: arbiter.v 26 2015-11-22 19:24:28Z ranga $
* $Date: 2015-11-22 21:24:28 +0200 (Sun, 22 Nov 2015) $
* $Author: ranga $
*********************/
`include "parameters.v"
`include "state_defines.v"
module arbiter(clk, rst,
Lflit_id, Nflit_id, Eflit_id, Wflit_id, Sflit_id,
Llength, Nlength, Elength, Wlength, Slength,
Lreq, Nreq, Ereq, Wreq, Sreq,
nextstate
);
input clk, rst;
input [2:0] Lflit_id, Nflit_id, Eflit_id, Wflit_id, Sflit_id;
input [11:0] Llength, Nlength, Elength, Wlength, Slength;
input Lreq, Nreq, Ereq, Wreq, Sreq;
output reg [5:0] nextstate;
// Declaring the local variables
reg [5:0] currentstate;
reg Lruntimer, Nruntimer, Eruntimer, Wruntimer, Sruntimer;
wire Ltimesup, Ntimesup, Etimesup, Wtimesup, Stimesup;
// Timer module that runs for the entire packet length
timer Ltimer (clk, rst, Lflit_id, Llength, Lruntimer, Ltimesup);
timer Ntimer (clk, rst, Nflit_id, Nlength, Nruntimer, Ntimesup);
timer Etimer (clk, rst, Eflit_id, Elength, Eruntimer, Etimesup);
timer Wtimer (clk, rst, Wflit_id, Wlength, Wruntimer, Wtimesup);
timer Stimer (clk, rst, Sflit_id, Slength, Sruntimer, Stimesup);
// Arbiter - State Machine
// Current state sequential Logic
always @ (posedge clk) begin
if(rst)
currentstate <= `IDLE;
else
currentstate <= nextstate;
end
// Next state decoder Logic
always @ (Lreq, Nreq, Ereq, Wreq, Sreq, Ltimesup, Ntimesup, Etimesup, Wtimesup, Stimesup, currentstate) begin
{Lruntimer, Nruntimer, Eruntimer, Wruntimer, Sruntimer} = 0;
case(currentstate)
`IDLE:
begin
if(Lreq == 1) begin
nextstate = `GRANT_L;
end
else if(Nreq == 1) begin
nextstate = `GRANT_N;
end
else if(Ereq == 1) begin
nextstate = `GRANT_E;
end
else if(Wreq == 1) begin
nextstate = `GRANT_W;
end
else if (Sreq == 1) begin
nextstate = `GRANT_S;
end
else begin
nextstate = `IDLE;
end
end
`GRANT_L:
begin
if(Lreq == 1 && Ltimesup == 0) begin
Lruntimer = 1;
nextstate = `GRANT_L;
end
else if(Nreq == 1) begin
nextstate = `GRANT_N;
end
else if(Ereq == 1) begin
nextstate = `GRANT_E;
end
else if(Wreq == 1) begin
nextstate = `GRANT_W;
end
else if(Sreq == 1) begin
nextstate = `GRANT_S;
end
else begin
nextstate = `IDLE;
end
end
`GRANT_N:
begin
if(Nreq == 1 && Ntimesup == 0) begin
Nruntimer = 1;
nextstate = `GRANT_N;
end
else if(Ereq == 1) begin
nextstate = `GRANT_E;
end
else if(Wreq == 1) begin
nextstate = `GRANT_W;
end
else if(Sreq == 1) begin
nextstate = `GRANT_S;
end
else if(Lreq == 1) begin
nextstate = `GRANT_L;
end
else begin
nextstate = `IDLE;
end
end
`GRANT_E:
begin
if(Ereq == 1 && Etimesup == 0) begin
Eruntimer = 1;
nextstate = `GRANT_E;
end
else if(Wreq == 1) begin
nextstate = `GRANT_W;
end
else if(Sreq == 1) begin
nextstate = `GRANT_S;
end
else if(Lreq == 1) begin
nextstate = `GRANT_L;
end
else if(Nreq == 1) begin
nextstate = `GRANT_N;
end
else begin
nextstate = `IDLE;
end
end
`GRANT_W:
begin
if(Wreq == 1 && Wtimesup == 0) begin
Wruntimer = 1;
nextstate = `GRANT_W;
end
else if(Sreq == 1) begin
nextstate = `GRANT_S;
end
else if(Lreq == 1) begin
nextstate = `GRANT_L;
end
else if(Nreq == 1) begin
nextstate = `GRANT_N;
end
else if(Ereq == 1) begin
nextstate = `GRANT_E;
end
else begin
nextstate = `IDLE;
end
end
`GRANT_S:
begin
if(Sreq == 1 && Stimesup == 0) begin
Sruntimer = 1;
nextstate = `GRANT_S;
end
else if(Lreq == 1) begin
nextstate = `GRANT_L;
end
else if(Nreq == 1) begin
nextstate = `GRANT_N;
end
else if(Ereq == 1) begin
nextstate = `GRANT_E;
end
else if(Wreq == 1) begin
nextstate = `GRANT_W;
end
else begin
nextstate = `IDLE;
end
end
default:
begin
nextstate = `IDLE;
end
endcase
end
endmodule
module timer (clk, rst, flit_id, length, runtimer, timesup);
input clk, rst;
input [2 : 0] flit_id;
input [11 : 0] length;
input runtimer;
output reg timesup;
//Declaring the local variables
reg [11 : 0] timeoutclockperiods; // stores packet length
reg [11 : 0] count;
// Setting Access time for each request
always @ (posedge clk) begin: timeout
if(rst) begin
count <= 0;
timeoutclockperiods <= 0;
end
else begin
if (flit_id == `HEADER) begin
timeoutclockperiods <= length;
end
if (runtimer == 0) begin
count <= 0;
end
else begin
count <= count + 1;
end
end
end
// Asserting the timesup signal when the access time exceeds timeoutclockperiod
always @ (count, timeoutclockperiods) begin : timeup
if (count == timeoutclockperiods)
timesup = 1;
else
timesup = 0;
end
endmodule
|
`timescale 1ns/1ps
//changed to synchrounous reset
module y86_seq(
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE, bus_RE,
output [7:0] current_opcode);
// global control
reg [5:1] full;
wire [4:0] ue={ full[4:1], full[5] };
always @(posedge clk) begin
if(rst)
\t full<='b10000;
\t else
full<={ ue[4], ue[3], ue[2], ue[1], ue[0] };
end
// stage 1 IF
reg [31:0] IR;
always @(posedge clk)
if(ue[0]) IR<=bus_in;
// stage 2 ID
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode=IR[7:0];
wire [1:0] mod=IR[15:14];
reg ZF;
wire load=opcode=='h8b && mod==1;
wire move=opcode=='h89 && mod==3;
wire store=opcode=='h89 && mod==1;
wire memory=load || store;
wire add=opcode=='h01;
wire sub=opcode=='h29;
wire halt=opcode=='hf4;
wire aluop=add || sub;
wire jnez=opcode=='h75;
wire [4:0] RD=IR[10:8];
wire [4:0] RS=IR[13:11];
wire [4:0] Aad=memory?6:RD,
Bad=RS;
wire [31:0] distance={ { 24 { IR[15] } }, IR[15:8] };
wire [31:0] displacement={ { 24 { IR[23] } }, IR[23:16] };
wire btaken=jnez && !ZF;
wire [1:0] length=memory ?3:
(aluop || move || jnez)?2:
1;
always @(posedge clk)
if(rst)
\t IP<=0;
else if(ue[1]) begin
A<=Aop;
B<=Bop;
if(!halt)
\tbegin
\t IP<=IP+length+(btaken?distance:0);
\tend
else
\tbegin
$finish;
\tend
end
// stage 3 EX
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2=memory?displacement:sub?~B:B;
wire [31:0] ALUout=A+ALU_op2+sub;
always @(posedge clk)
if(rst)
\t ZF=0;
else if(ue[2]) begin
MAR<=ALUout;
C<=move?B:ALUout;
MDRw<=B;
if(aluop) ZF<=(ALUout==0);
end
// stage 4 MEM
reg [31:0] MDRr;
always @(posedge clk)
if(ue[3] && load) MDRr<=bus_in;
assign bus_A=ue[3]?MAR:ue[0]?IP:0;
assign bus_RE=ue[0] || (ue[3] && load);
// stage 5 WB
reg [31:0] R[7:0];
assign Aop=R[Aad];
assign Bop=R[Bad];
assign bus_WE=ue[3] && store;
assign bus_out=MDRw;
always @(posedge clk)
if(rst) begin
\t R[00]<=0; R[01]<=0; R[02]<=0; R[03]<=0; R[04]<=0; R[05]<=0; R[06]<=0; R[07]<=0;
\t end
\t else if(ue[4])
if(aluop || move || load)
\t\tif(load)//rausgezogen
\t\t\tR[RS]<=MDRr;
\t\telse
\t\tR[RD]<=C;
\t\t\t\t
assign current_opcode = opcode;
// ... and now for something completely different.
// synthesis translate_off
wire [31:0] eax = R[0];
wire [31:0] ecx = R[1];
wire [31:0] edx = R[2];
wire [31:0] ebx = R[3];
wire [31:0] esp = R[4];
wire [31:0] ebp = R[5];
wire [31:0] esi = R[6];
wire [31:0] edi = R[7];
wire [7:0] regs = IR[15:8];
// synthesis translate_on
endmodule
|
/********************
* Filename: state_defines.v
* Description: definitions of the possibile values for the arbiter state variable
one-hot encoding considered
* $Revision: 21 $
* $Id: state_defines.v 21 2015-11-21 10:54:06Z ranga $
* $Date: 2015-11-21 12:54:06 +0200 (Sat, 21 Nov 2015) $
* $Author: ranga $
*********************/
`define IDLE 6'b000001
`define GRANT_L 6'b000010
`define GRANT_N 6'b000100
`define GRANT_E 6'b001000
`define GRANT_W 6'b010000
`define GRANT_S 6'b100000
`define L_PORT 5'b00001
`define N_PORT 5'b00010
`define E_PORT 5'b00100
`define W_PORT 5'b01000
`define S_PORT 5'b10000 |
/********************
* Filename: arbiter.v
* Description: Packets with the same priority and destined for the same output port are scheduled with a round-robin arbiter with the last served as least priority.
Priority direction Local, North, East, South, West
Maintains the priority till it reads the TAIL flit
One-hot encoding for state variable
Output values [5:0]: Output[5:1] -> selection, Output[0] -> idle
*
* $Revision: 26 $
* $Id: arbiter.v 26 2015-11-22 19:24:28Z ranga $
* $Date: 2015-11-22 21:24:28 +0200 (Sun, 22 Nov 2015) $
* $Author: ranga $
*********************/
`timescale 1ns/1ps
`include "parameters.v"
`include "state_defines.v"
module arbiter(clk, rst,
Lflit_id, Nflit_id, Eflit_id, Wflit_id, Sflit_id,
Llength, Nlength, Elength, Wlength, Slength,
Lreq, Nreq, Ereq, Wreq, Sreq,
nextstate
);
input clk, rst;
input [2:0] Lflit_id, Nflit_id, Eflit_id, Wflit_id, Sflit_id;
input [11:0] Llength, Nlength, Elength, Wlength, Slength;
input Lreq, Nreq, Ereq, Wreq, Sreq;
output reg [5:0] nextstate;
// Declaring the local variables
reg [5:0] currentstate;
reg Lruntimer, Nruntimer, Eruntimer, Wruntimer, Sruntimer;
wire Ltimesup, Ntimesup, Etimesup, Wtimesup, Stimesup;
// Timer module that runs for the entire packet length
timer Ltimer (clk, rst, Lflit_id, Llength, Lruntimer, Ltimesup);
timer Ntimer (clk, rst, Nflit_id, Nlength, Nruntimer, Ntimesup);
timer Etimer (clk, rst, Eflit_id, Elength, Eruntimer, Etimesup);
timer Wtimer (clk, rst, Wflit_id, Wlength, Wruntimer, Wtimesup);
timer Stimer (clk, rst, Sflit_id, Slength, Sruntimer, Stimesup);
// Arbiter - State Machine
// Current state sequential Logic
always @ (posedge clk) begin
if(rst)
currentstate <= `IDLE;
else
currentstate <= nextstate;
end
// Next state decoder Logic
always @ (Lreq, Nreq, Ereq, Wreq, Sreq, Ltimesup, Ntimesup, Etimesup, Wtimesup, Stimesup, currentstate) begin
{Lruntimer, Nruntimer, Eruntimer, Wruntimer, Sruntimer} = 0;
case(currentstate)
`IDLE:
begin
if(Lreq == 1) begin
nextstate = `GRANT_L;
end
else if(Nreq == 1) begin
nextstate = `GRANT_N;
end
else if(Ereq == 1) begin
nextstate = `GRANT_E;
end
else if(Wreq == 1) begin
nextstate = `GRANT_W;
end
else if (Sreq == 1) begin
nextstate = `GRANT_S;
end
else begin
nextstate = `IDLE;
end
end
`GRANT_L:
begin
if(Lreq == 1 && Ltimesup == 0) begin
Lruntimer = 1;
nextstate = `GRANT_L;
end
else if(Nreq == 1) begin
nextstate = `GRANT_N;
end
else if(Ereq == 1) begin
nextstate = `GRANT_E;
end
else if(Wreq == 1) begin
nextstate = `GRANT_W;
end
else if(Sreq == 1) begin
nextstate = `GRANT_S;
end
else begin
nextstate = `IDLE;
end
end
`GRANT_N:
begin
if(Nreq == 1 && Ntimesup == 0) begin
Nruntimer = 1;
nextstate = `GRANT_N;
end
else if(Ereq == 1) begin
nextstate = `GRANT_E;
end
else if(Wreq == 1) begin
nextstate = `GRANT_W;
end
else if(Sreq == 1) begin
nextstate = `GRANT_S;
end
else if(Lreq == 1) begin
nextstate = `GRANT_L;
end
else begin
nextstate = `IDLE;
end
end
`GRANT_E:
begin
if(Ereq == 1 && Etimesup == 0) begin
Eruntimer = 1;
nextstate = `GRANT_E;
end
else if(Wreq == 1) begin
nextstate = `GRANT_W;
end
else if(Sreq == 1) begin
nextstate = `GRANT_S;
end
else if(Lreq == 1) begin
nextstate = `GRANT_L;
end
else if(Nreq == 1) begin
nextstate = `GRANT_N;
end
else begin
nextstate = `IDLE;
end
end
`GRANT_W:
begin
if(Wreq == 1 && Wtimesup == 0) begin
Wruntimer = 1;
nextstate = `GRANT_W;
end
else if(Sreq == 1) begin
nextstate = `GRANT_S;
end
else if(Lreq == 1) begin
nextstate = `GRANT_L;
end
else if(Nreq == 1) begin
nextstate = `GRANT_N;
end
else if(Ereq == 1) begin
nextstate = `GRANT_E;
end
else begin
nextstate = `IDLE;
end
end
`GRANT_S:
begin
if(Sreq == 1 && Stimesup == 0) begin
Sruntimer = 1;
nextstate = `GRANT_S;
end
else if(Lreq == 1) begin
nextstate = `GRANT_L;
end
else if(Nreq == 1) begin
nextstate = `GRANT_N;
end
else if(Ereq == 1) begin
nextstate = `GRANT_E;
end
else if(Wreq == 1) begin
nextstate = `GRANT_W;
end
else begin
nextstate = `IDLE;
end
end
default:
begin
nextstate = `IDLE;
end
endcase
end
endmodule
module timer (clk, rst, flit_id, length, runtimer, timesup);
input clk, rst;
input [2 : 0] flit_id;
input [11 : 0] length;
input runtimer;
output reg timesup;
//Declaring the local variables
reg [11 : 0] timeoutclockperiods; // stores packet length
reg [11 : 0] count;
// Setting Access time for each request
always @ (posedge clk) begin: timeout
if(rst) begin
count <= 0;
timeoutclockperiods <= 0;
end
else begin
if (flit_id == `HEADER) begin
timeoutclockperiods <= length;
end
if (runtimer == 0) begin
count <= 0;
end
else begin
count <= count + 1;
end
end
end
// Asserting the timesup signal when the access time exceeds timeoutclockperiod
always @ (count, timeoutclockperiods) begin : timeup
if (count == timeoutclockperiods)
timesup = 1;
else
timesup = 0;
end
endmodule
|
/********************\r
* Filename: parameters.v\r
* Description: Parameters for Packet FLITS\r
* $Revision: 21 $\r
* $Id: parameters.v 21 2015-11-21 10:54:06Z ranga $\r
* $Date: 2015-11-21 12:54:06 +0200 (Sat, 21 Nov 2015) $\r
* $Author: ranga $\r
*********************/\r
\r
// defining the flit ID -- One hot encoding\r
`define HEADER 3'b001\r
`define PAYLOAD 3'b010\r
`define TAIL 3'b100\r
\r
// Specifying the FIFO parameters\r
`define FIFO_DEPTH 'd4 // 4 flits capacity\r
`define PTR_SIZE `FIFO_DEPTH // Controls reading and writing (for full and empty) >> Depends on the FIFO_DEPTH\r
`define DATA_WIDTH 'd32 // # of data bits with parity |
`timescale 1ns / 1ps
// NES Controller SIPO //
// Developed by Michael Swan //
module nes_controller(
\t\tinput master_clock,
\t\t// Device connections
\t\toutput data_clock,
\t\toutput data_latch,
\t\tinput serial_data,
\t\t// Data output
\t\toutput reg [7:0] button_state,
\t\toutput update_clock
);
\t// Unit Parameters //
\tparameter Hz = 1;
\tparameter KHz = 1000*Hz;
\tparameter MHz = 1000*KHz;
\t
\t// Context-sensitive Parameters //
\tparameter MASTER_CLOCK_FREQUENCY = 100*MHz; // USER VARIABLE
\tparameter OUTPUT_UPDATE_FREQUENCY = 120*Hz; // USER VARIABLE
\t
\t// Clock divider register size
\tparameter DIVIDER_EXPONENT = log2( (MASTER_CLOCK_FREQUENCY / OUTPUT_UPDATE_FREQUENCY) / 10 ) - 2;
\t
\t// Generate a clock for generating the data clock and sampling the controller's output
\treg [DIVIDER_EXPONENT:0] sample_count;
\twire sample_clock = sample_count[DIVIDER_EXPONENT];
\talways @(posedge master_clock) sample_count <= sample_count + 1;
\t
\t// Keep track of the stage of the cycle
\treg [3:0] cycle_stage;
\treg [7:0] data;
\t// Generate control signals for the three phases
\twire latch_phase = cycle_stage == 0;
\twire data_phase = cycle_stage >= 1 & cycle_stage <= 8;
\twire end_phase = cycle_stage == 9;
\t
\t// Handle inputs from the controller
\talways @(posedge sample_clock) begin
\t\t if(latch_phase) data <= 4'h0;
\t\telse if(data_phase) data <= {data[6:0], serial_data};
\t\telse if(end_phase) begin
\t\t\tcycle_stage <= 4'h0;
\t\t\tbutton_state[7:0] <= data;
\t\tend
\t\tcycle_stage <= cycle_stage + 1;
\tend
\t// Generate output signals
\tassign data_latch = latch_phase;
\tassign data_clock = data_phase & sample_clock;
\tassign update_clock = sample_clock;
\t
\t// Helper functions
\tfunction integer log2;
\t\t input [31:0] value;
\t\t begin
\t\t\t value = value - 1;
\t\t\t for (log2 = 0; value > 0; log2 = log2 + 1) begin
\t\t\t\t\tvalue = value >> 1;
\t\t\t end
\t\t end
\tendfunction
endmodule
|
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