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(* Test visibility of coercions *)
Require Import make_local.
(* Local coercion must not be used *)
Check (0 = true).
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Require Import EquivDec List.
Generalizable All Variables.
Program Definition list_eqdec `(eqa : EqDec A eq) : EqDec (list A) eq :=
(fun (x y : list A) => _).
Admit Obligations of list_eqdec.
Program Definition list_eqdec' `(eqa : EqDec A eq) : EqDec (list A) eq :=
(fun _ : nat => (fun (x y : list A) => _)) 0.
Admit Obligations of list_eqdec'.
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Class C.
Parameter P: C -> Prop.
Fail Record R: Type := { _: C; u: P _ }.
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(* Test bug 2168: ending section of some name was removing objects of the
same name *)
Require Import make_notation.
Check add2 3.
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(* Check that constraints on locals are preserved by discharging *)
Definition Type2 := Type.
Section A.
Let Type1 : Type2 := Type.
Definition Type1' := Type1.
End A.
Definition Inconsistency : Type1' := Type2.
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:42:57 03/03/2016
// Design Name:
// Module Name: Modificacion_Ciclo_Trabajo
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Modificacion_Ciclo_Trabajo(
\tinput wire clk_100MHz,
\tinput wire clk_de_trabajo,
\tinput wire rst,
\tinput wire up,
\tinput wire down,
\tinput wire chip_select, //Tanto para seleccionar el registro como para habilitar el contador universal
\toutput wire signal_out,
\toutput wire [3:0]ciclo_actual\t
\t
);
\t
wire [3:0] ref; //Referencia que entra al comparador a partir del contador A/D
wire out_aumentar,out_disminuir;
wire [3:0]out_contador_AD;
\t
Comp_16bits Instancia_Comparador (
.in(out_contador_AD),
.out(signal_out),
.rst(rst),
.ref(ref),
.clk(clk_de_trabajo)
);
Registro_Universal Instancia_Reg_universal
(
.aumentar(up),
.disminuir(down),
.clk(clk_100MHz),
.reset(rst),
.chip_select(chip_select),
.out_aumentar(out_aumentar),
.out_disminuir(out_disminuir)
);
Contador_Ascendente_Descendente Instancia_Contador_AD (
.clk(clk_100MHz),
.reset(rst),
.enUP(out_aumentar),
.enDOWN(out_disminuir),
.q(out_contador_AD)
);
\t
Contador_conReset Instancia_Contador_conReset
(
.clk(clk_de_trabajo),
.reset(rst),
.q(ref)
);
assign ciclo_actual = out_contador_AD;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:59:28 03/01/2016
// Design Name: Synchro
// Module Name: D:/ISE/Proyecto1/TB_synchro.v
// Project Name: Proyecto1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Synchro
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_synchro;
\t// Inputs
\treg dato;
\treg clk;
\t// Outputs
\twire ds;
\t// Instantiate the Unit Under Test (UUT)
\tSynchro uut (
\t\t.dato(dato),
\t\t.clk(clk),
\t\t.ds(ds)
\t);
\tinitial begin
\t\t// Initialize Inputs
\t\tdato = 0;
\t\tclk = 0;
\t\t// Wait 100 ns for global reset to finish
\t\t#30;
dato = 1;
\t\t#50;
dato = 0;
\t\t// Add stimulus here
\tend
always #10 clk = ~clk;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: ITCR\t
// Engineer: Yermy Benavides
//
// Create Date: 18:24:48 02/29/2016
// Design Name: DivFrec
// Module Name: D:/ISE/Proyecto1/DivFrec_tb.v
// Project Name: Proyecto1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: DivFrec
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module DivFrec_tb;
\t// Inputs
\treg clk;
\treg rst;
\treg [15:0] div;
\t// Outputs
\twire clkd;
\t// Instantiate the Unit Under Test (UUT)
\tDivFrec uut (
\t\t.clk(clk),
\t\t.rst(rst),
\t\t.div(div),
\t\t.clkd(clkd)
\t);
\tinitial begin
\t\t// Initialize Inputs
\t\tclk = 0;
\t\trst = 0;
\t\tdiv = 0;
\t\t// Wait 10 ns for global reset to finish
\t\t#10 div = 16'b111110011;
\t
\tend
\t
\talways #10 clk = ~clk;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:47:41 03/01/2016
// Design Name:
// Module Name: Synchro
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Synchro(dato,clk,ds);
input wire dato,clk;
output wire ds;
wire c1,c2,c3;
FFD FF1(
.dato(dato),
.clk(clk),
.q(c1)
);
FFD FF2(
.dato(c1),
.clk(clk),
.q(c2)
);
FFD FF3(
.dato(c2),
.clk(clk),
.q(c3)
);
\t
assign ds = c1 && c2 && c3;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: ITCR
// Engineer: Yermy Benavides
//
// Create Date: 21:08:09 02/29/2016
// Design Name:
// Module Name: MDF
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MDF(clk,rst,entrada,salida,salida_1kHz,q);
input wire clk,rst;
input wire [3:0]entrada;
output wire salida;
output wire salida_1kHz;
output wire [10:0]q;
\t
Traductor Conv(
.in(entrada),
.out(q),
.clk(clk),
.rst(rst)
);
\t
DivFrec DF(
.clk(clk),
.rst(rst),
.div(q),
.clkd(salida),
\t .clk_1kHz(salida_1kHz)
);\t
\t
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:49:15 03/01/2016
// Design Name:
// Module Name: FF-D
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FFD(dato,clk,q);
input dato, clk;
output reg q;
always @ ( posedge clk)
begin
q <= dato;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:50:03 03/02/2016
// Design Name:
// Module Name: Control_visualizador_numerico
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Control_visualizador_numerico
(
input wire [3:0] cuenta_frec,
input wire [3:0] cuenta_CT,
input wire clock,
input wire reset,
input wire funct_select,
output wire [7:0] code_digitos_decimal, //secuencia para mostrar el digito correcto
output wire [3:0] code_7seg //secuencia para encender el 7 segmentos correcto
);
wire [3:0] OutFSM_InConversorBCD; //Conexion entre la maquina de estados y el conversor BCD a 7 segmentos
FSM Instancia_FSM
(
.clk(clock),
.rst(reset),
.Funct_Select(funct_select),
.Count_CT(cuenta_CT),
.Count_F(cuenta_frec),
.C_Digit(OutFSM_InConversorBCD),
.C_7Seg(code_7seg)
);
Conversor_BCD_7seg Instancia_Conversor_BCD_7seg
(
.Valor_Decimal(OutFSM_InConversorBCD),
.Code_7seg(code_digitos_decimal)
);
endmodule
|
`timescale 10ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:31:50 03/07/2016
// Design Name: DPWM
// Module Name: D:/TEC/I 2016/Lab Digitales/Proyecto I/I-Proyecto-Laboratorio-de-Dise-o-Sistemas-Digitales/TB_PDWM.v
// Project Name: PRIMER_PROYECTO
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: DPWM
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_PDWM;
\t// Inputs
\treg CLK_FPGA_BOARD;
\treg boton_aumentar;
\treg boton_disminuir;
\treg seleccion_funcion;
\treg seleccion_salida;
\treg reinicio;
\t// Outputs
\twire BUCK_Gate;
\twire Full_Bridge;
\twire [3:0] anodos_7seg;
\twire [7:0] catodos_7seg;
\t// Instantiate the Unit Under Test (UUT)
\tDPWM uut (
\t\t.CLK_FPGA_BOARD(CLK_FPGA_BOARD),
\t\t.boton_aumentar(boton_aumentar),
\t\t.boton_disminuir(boton_disminuir),
\t\t.seleccion_funcion(seleccion_funcion),
\t\t.seleccion_salida(seleccion_salida),
\t\t.reinicio(reinicio),
\t\t.BUCK_Gate(BUCK_Gate),
\t\t.Full_Bridge(Full_Bridge),
\t\t.anodos_7seg(anodos_7seg),
\t\t.catodos_7seg(catodos_7seg)
\t);
initial begin
forever #0.5 CLK_FPGA_BOARD = ~CLK_FPGA_BOARD;
end
\tinitial begin
\t\t// Initialize Inputs
\t\tCLK_FPGA_BOARD = 0;
\t\tboton_aumentar = 0;
\t\tboton_disminuir = 0;
\t\tseleccion_funcion = 0;
\t\tseleccion_salida = 0;
\t\treinicio = 0;
\t\t// Wait 100 ns for global reset to finish
\t\t#10;
\t\t
\t\tboton_aumentar = 0;
\t\tboton_disminuir = 0;
\t\tseleccion_funcion = 0;
\t\tseleccion_salida = 0;
\t\treinicio = 1;
\t\t#10
\t\t
\t\tboton_aumentar = 0;
\t\tboton_disminuir = 0;
\t\tseleccion_funcion = 0;
\t\tseleccion_salida = 0;
\t\treinicio = 0;
\t\t#10
\t\t
\t\tboton_aumentar = 1;
\t\tboton_disminuir = 0;
\t\tseleccion_funcion = 0;
\t\tseleccion_salida = 0;
\t\treinicio = 0;
\t\t#100
\t\tboton_aumentar = 0;
\t\tboton_disminuir = 0;
\t\tseleccion_funcion = 0;
\t\tseleccion_salida = 0;
\t\treinicio = 0;
\t\t#10
\t\tboton_aumentar = 1;
\t\tboton_disminuir = 0;
\t\tseleccion_funcion = 0;
\t\tseleccion_salida = 0;
\t\treinicio = 0;
\t\t#100
\t\tboton_aumentar = 0;
\t\tboton_disminuir = 0;
\t\tseleccion_funcion = 0;
\t\tseleccion_salida = 0;
\t\treinicio = 0;
\t\t
\t\t\t\t#10
\t\t
\t\tboton_aumentar = 1;
\t\tboton_disminuir = 0;
\t\tseleccion_funcion = 0;
\t\tseleccion_salida = 0;
\t\treinicio = 0;
\t\t#100
\t\tboton_aumentar = 0;
\t\tboton_disminuir = 0;
\t\tseleccion_funcion = 0;
\t\tseleccion_salida = 0;
\t\treinicio = 0;
\t\t// Add stimulus here
\t\t#10000000$stop;
\tend
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:52:27 02/29/2016
// Design Name: FSM
// Module Name: C:/Users/Jafet/Documents/Proyectos Dis.Sist.Digitales/I_Proyecto_Laboratorio_Sistemas_Digitales/FSM_Testbench.v
// Project Name: I_Proyecto_Laboratorio_Sistemas_Digitales
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: FSM
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module FSM_Testbench;
\t// Inputs
\treg clk;
\treg rst;
\treg Funct_Select;
\treg [3:0] Count_CT;
\treg [3:0] Count_F;
\t// Outputs
\twire [3:0] C_Digit;
\twire [3:0] C_7Seg;
\t// Instantiate the Unit Under Test (UUT)
\tFSM uut (
\t\t.clk(clk),
\t\t.rst(rst),
\t\t.Funct_Select(Funct_Select),
\t\t.Count_CT(Count_CT),
\t\t.Count_F(Count_F),
\t\t.C_Digit(C_Digit),
\t\t.C_7Seg(C_7Seg)
\t);
\t
\t//this process block sets up the free running clock
\tinitial begin
\tclk = 0;
\tforever #5 clk = ~clk;
\tend
\tinitial begin
\t\t// Initialize Inputs
\t\tclk = 0;
\t\trst = 0;
\t\tFunct_Select = 0;
\t\tCount_CT = 0;
\t\tCount_F = 0;
\t
\t\tend
\t\t// Wait 100 ns for global reset to finish
\t\t//#100;
\t\t// Add stimulus here
\t\t
\tinitial begin
\t
\t\trst = 1;
\t\tFunct_Select = 1'b0;
\t\tCount_CT = 4'b0000;
\t\tCount_F = 4'b0000;
\t\t#200
\t\trst = 0;
\t\tFunct_Select = 1'b0;
\t\tCount_CT = 4'b0000;
\t\tCount_F = 4'b0000;
\t\t#800
\t\trst = 0;
\t\tFunct_Select = 1'b1;
\t\tCount_CT = 4'b0000;
\t\tCount_F = 4'b0000;
\t\t#800
\t\trst = 0;
\t\tFunct_Select = 1'b0;
\t\tCount_CT = 4'b0001;
\t\tCount_F = 4'b0001;
\t\t#800
\t\trst = 0;
\t\tFunct_Select = 1'b1;
\t\tCount_CT = 4'b0001;
\t\tCount_F = 4'b0001;
\t\t#1000 $stop;
\t\t
\tend
\t
\t/*reg [3:0] i;
\t
\tinitial begin
\t
\trst = 1;
\tFunct_Select = 1'b0;
\tCount_CT = 4'b0000;
\tCount_F = 4'b0000;
\t#200
\trst = 0;
\tFunct_Select = 1'b0;
\tfor(i=4'b0;i<16;i=i+1)
\talways@ posedge clck
\tbegin
\tCount_CT <= i;
\tCount_F <= i;
\tend
\t#1000 $stop;
\tend*/
\t
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:18:58 02/21/2016
// Design Name:
// Module Name: Demux
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Demux (out,in,sel);
parameter nO = 2;
parameter nS = 1;
output[nO-1:0] out; //demux out
input in; //demux input
input[nS-1:0] sel; //demux select signal
assign out = in << sel; //shift left in tantas sel veces
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:03:15 02/21/2016
// Design Name:
// Module Name: Contador_Ascendente_Descendente
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Contador_Ascendente_Descendente
\t# (parameter N = 4) // Para definir el n\xfamero de bits del contador
\t(
\t\tinput wire clk,
\t\tinput wire reset,
\t\tinput wire enUP,
\t\tinput wire enDOWN,
\t\toutput wire [N-1:0] q
);
//Signal Declarations
reg [N-1:0] q_act, q_next;
//Body of "state" registers
always@(posedge clk,posedge reset)
\tif(reset)
\t\tq_act <= 0;
\telse
\t\tq_act <= q_next;
//Specified functions of the counter \t\t
always@*
\tif(enUP)
\t\tq_next = q_act + 1\'b1;
\t
\telse if (enDOWN)
\t\tq_next = q_act - 1\'b1;
\t\t
\telse
\t\tq_next = q_act;
//Output Logic
assign q = q_act;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:09:32 02/29/2016
// Design Name: Comp_16bits
// Module Name: D:/ISE/Proyecto1/Comp_16bits_tb.v
// Project Name: Proyecto1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Comp_16bits
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Comp_16bits_tb;
\t// Inputs
\treg [15:0] in;
\treg rst;
\treg [15:0] ref;
\t// Outputs
\twire out;
\t// Instantiate the Unit Under Test (UUT)
\tComp_16bits uut (
\t\t.in(in),
\t\t.out(out),
\t\t.rst(rst),
\t\t.ref(ref)
\t);
\tinitial begin
\t\t// Initialize Inputs
\t\tin = 0;
\t\trst = 0;
\t\tref = 0;
\t\t// Wait 100 ns for global reset to finish
\t\t#100;
\t\t// Add stimulus here
\t\t
\t\t
\tend
endmodule
|
`timescale 10ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:38:47 03/06/2016
// Design Name: DPWM
// Module Name: C:/Users/Jafet/Documents/Proyectos Dis.Sist.Digitales/I_Proyecto_Laboratorio_Sistemas_Digitales/DPWM_TestBench.v
// Project Name: I_Proyecto_Laboratorio_Sistemas_Digitales
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: DPWM
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module DPWM_TestBench;
\t// Inputs
\treg CLK_FPGA_BOARD;
\treg boton_aumentar;
\treg boton_disminuir;
\treg seleccion_funcion;
\treg seleccion_salida;
\treg reinicio;
\t// Outputs
\twire BUCK_Gate;
\twire Full_Bridge;
\twire [3:0] anodos_7seg;
\twire [7:0] catodos_7seg;
\t// Instantiate the Unit Under Test (UUT)
\tDPWM uut (
\t\t.CLK_FPGA_BOARD(CLK_FPGA_BOARD),
\t\t.boton_aumentar(boton_aumentar),
\t\t.boton_disminuir(boton_disminuir),
\t\t.seleccion_funcion(seleccion_funcion),
\t\t.seleccion_salida(seleccion_salida),
\t\t.reinicio(reinicio),
\t\t.BUCK_Gate(BUCK_Gate),
\t\t.Full_Bridge(Full_Bridge),
\t\t.anodos_7seg(anodos_7seg),
\t\t.catodos_7seg(catodos_7seg)
\t);
\tinitial
\tbegin
\t\t// Initialize Inputs
\t\tCLK_FPGA_BOARD = 0;
\t\tboton_aumentar = 0;
\t\tboton_disminuir = 0;
\t\tseleccion_funcion = 0;
\t\tseleccion_salida = 0;
\t\treinicio = 0;
\tend
\t\t// Wait 100 ns for global reset to finish
\t\t//#100;
\t\t
\t\t\t
\t\t\t
\t//this process block sets up the free running clock
\t\tinitial
\t\tbegin
\t\tCLK_FPGA_BOARD = 0;
\t\tforever #5 CLK_FPGA_BOARD = ~CLK_FPGA_BOARD;
\t\tend
\t\t// Add stimulus here
\t\t
\t\tinitial
\t\tbegin
\t\t
\t\treinicio = 1;
\t\tboton_aumentar = 0;
\t\tboton_disminuir = 0;
\t\tseleccion_funcion = 0;
\t\tseleccion_salida = 0;
\t\t#10
\t\t
\t\treinicio = 0;
\t\t#10
\t\t
\t\treinicio = 0;
\t\tboton_aumentar = 1;
\t\t#50
\t\tboton_aumentar = 0;
\t\t#20
\t\tboton_aumentar = 1;
\t\t#20
\t\tboton_aumentar = 0;
\t\tboton_disminuir = 0;
\t\t/*
\t\tseleccion_funcion = 0;
\t\tseleccion_salida = 0;
\t\t#200
\t\t*/
\t\t//#1000000$stop;
\t\t
\t\tend
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:54:48 02/29/2016
// Design Name:
// Module Name: DivFrec
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DivFrec(clk,rst,div,clkd,clk_1kHz);
input wire clk,rst;
input wire [10:0]div;
output wire clkd;
output wire clk_1kHz;
reg [10:0]q = 0;
reg cd = 0;
reg [15:0]q_1kHz = 0;
reg cd_1kHz = 0;
// Para generar el clock dividido variable a partir de la cuenta
always@(posedge clk, posedge rst)
\tif (rst)
\t\tbegin
\t\tq <= 0;
\t\tcd <=0;
\t\tend
\telse
\t\tif (q==div)
\t\t\tbegin
\t\t\tq <= 0;
\t\t\tcd <= ~cd;
\t\t\tend
\t\telse
\t\t\tq <= q + 11'b1;
\t\t
assign clkd = cd;
// Para generar el clock dividido fijo de 1 kHz
always@(posedge clk, posedge rst)
\tif (rst)
\t\tbegin
\t\tq_1kHz <= 0;
\t\tcd_1kHz <=0;
\t\tend
\telse
\t\tif (q_1kHz==16'd49999)
\t\t\tbegin
\t\t\tq_1kHz <= 0;
\t\t\tcd_1kHz <= ~cd_1kHz;
\t\t\tend
\t\telse
\t\t\tq_1kHz <= q_1kHz + 16'b1;
\t\t
assign clk_1kHz = cd_1kHz;
endmodule |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:15:09 03/03/2016
// Design Name: Universal_Binary_Counter
// Module Name: D:/ISE/PRIMER_PROYECTO/TB_Contador_16bits.v
// Project Name: PRIMER_PROYECTO
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Universal_Binary_Counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_Contador_16bits;
\t// Inputs
\treg clk;
\treg rst;
\t// Outputs
\twire [15:0] out;
\t// Instantiate the Unit Under Test (UUT)
\tUniversal_Binary_Counter uut (
\t\t.clk(clk),
\t\t.rst(rst),
\t\t.out(out)
\t);
\tinitial
\tbegin
\t\t// Initialize Inputs
\t\tclk = 0;
\t\trst = 0;
\t\t// Wait 100 ns for global reset to finish
\t\t#100;
\t\trst = 1;
\t\t#10;
\t\trst = 0;
\t\t// Add stimulus here
\tend
\t
always #10 clk = ~clk;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:38:41 03/01/2016
// Design Name:
// Module Name: Registro_universal
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Registro_Universal
\t(
\t\tinput wire aumentar, //boton aumentar
\t\tinput wire disminuir, //boton disminuir
\t\tinput wire clk, //system clock
\t\tinput wire reset, //system reset
\t\tinput wire chip_select, //Control data
\t\toutput wire out_aumentar, //boton aumentar
\t\toutput wire out_disminuir //boton disminuir
);
//body
reg aumentar_actual,disminuir_actual,aumentar_next,disminuir_next;
//Combinacional
always@(posedge clk, posedge reset)
begin
\tif(reset)
\t\tbegin
\t\taumentar_actual <= 0;
\t\tdisminuir_actual <= 0;
\t\tend
\telse
\tbegin
\t\taumentar_actual <= aumentar_next;
\t\tdisminuir_actual <= disminuir_next;
\tend
end
//Secuencial
always@*
\tbegin
\t
\tcase(chip_select)
\t
\t1'b0: //Hold
\tbegin
\taumentar_next = aumentar_actual;
\tdisminuir_next = disminuir_actual;
\tend
\t1'b1: //Load
\tbegin
\taumentar_next = aumentar;
\tdisminuir_next = disminuir;
\tend
\tendcase
\t
\tend
assign out_aumentar = aumentar_actual;
assign out_disminuir = disminuir_actual;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:05:17 02/29/2016
// Design Name: Traductor
// Module Name: D:/ISE/Proyecto1/TB_traductr.v
// Project Name: Proyecto1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Traductor
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_traductr;
\t// Inputs
\treg [3:0] in;
\treg clk;
\treg rst;
\t// Outputs
\twire [15:0] out;
\t// Instantiate the Unit Under Test (UUT)
\tTraductor uut (
\t\t.in(in),
\t\t.out(out),
\t\t.clk(clk),
\t\t.rst(rst)
\t);
\tinitial begin
\t\t// Initialize Inputs
\t\tin = 4'b0010;
\t\tclk = 0;
\t\trst = 0;
\t\t// Wait 100 ns for global reset to finish
\t\t#100;
\t\t// Add stimulus here
\tend
\talways #10 clk=~clk;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:22:18 02/21/2016
// Design Name:
// Module Name: Frecuency_Selector
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Frecuency_Selector(
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: ITCR
// Engineer: Yermy Benavides
//
// Create Date: 21:40:24 02/29/2016
// Design Name: MDF
// Module Name: D:/ISE/Proyecto1/TB_MDF.v
// Project Name: Proyecto1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: MDF
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_MDF;
\t// Inputs
\treg clk;
\treg rst;
\treg [3:0] entrada;
\t// Outputs
\twire salida;
\twire [15:0]q;
\t// Instantiate the Unit Under Test (UUT)
\tMDF uut (
\t\t.clk(clk),
\t\t.rst(rst),
\t\t.entrada(entrada),
\t\t.salida(salida),
\t\t.q(q)
\t);
\tinitial begin
\t\t// Initialize Inputs
\t\tclk = 0;
\t\trst = 0;
\t\tentrada = 0;
\t\t
\t\t// Wait 100 ns for global reset to finish
\t\t#10;
\t\tentrada = 4\'b1111;
\t\t#10000;
\t\tentrada = 4\'b1010;
\tend
\talways #1000 clk = ~clk;
\t
/*\tinitial
\t\tbegin
\t\t$monitor("%d,\\t%b,\\t%b,\\t%b,\\t%d",$time, clk,rst,div,clkd);
\t\tend
initial
#500 $finish;\t
\t\t
*/\t\t
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: I.T.C.R
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 17:02:57 02/28/2016
// Design Name:
// Module Name: Conversor_BCD_7seg
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Conversor_BCD_7seg
(
input wire [3:0] Valor_Decimal,
output reg [7:0] Code_7seg
);
//Descripci\xf3n combinacional del valor decimal a c\xf3digo para el 7 segmentos
always @*
begin
case(Valor_Decimal)
4'h0: Code_7seg = 8'b00000011; //0
4'h1: Code_7seg = 8'b10011111; //1
4'h2: Code_7seg = 8'b00100101; //2
4'h3: Code_7seg = 8'b00001101; //3
4'h4: Code_7seg = 8'b10011001; //4
4'h5: Code_7seg = 8'b01001001; //5
4'h6: Code_7seg = 8'b01000001; //6
4'h7: Code_7seg = 8'b00011111; //8
4'h8: Code_7seg = 8'b00000001; //9
4'h9: Code_7seg = 8'b00001001; //Caso default no enciende el 7 seg
default: Code_7seg = 8'b11111111;
endcase
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:40:50 03/07/2016
// Design Name: Modificacion_Ciclo_Trabajo
// Module Name: D:/TEC/I 2016/Lab Digitales/Proyecto I/I-Proyecto-Laboratorio-de-Dise-o-Sistemas-Digitales/TB_CT.v
// Project Name: PRIMER_PROYECTO
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Modificacion_Ciclo_Trabajo
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_CT;
\t// Inputs
\treg clk_100MHz;
\treg clk_de_trabajo;
\treg rst;
\treg up;
\treg down;
\treg chip_select;
\t// Outputs
\twire signal_out;
\twire [3:0] ciclo_actual;
\t// Instantiate the Unit Under Test (UUT)
\tModificacion_Ciclo_Trabajo uut (
\t\t.clk_100MHz(clk_100MHz),
\t\t.clk_de_trabajo(clk_de_trabajo),
\t\t.rst(rst),
\t\t.up(up),
\t\t.down(down),
\t\t.chip_select(chip_select),
\t\t.signal_out(signal_out),
\t\t.ciclo_actual(ciclo_actual)
\t);
initial begin
forever #5 clk_100MHz = ~clk_100MHz;
end
initial begin
forever #10 clk_de_trabajo = ~clk_de_trabajo;
end
\tinitial begin
\t\t// Initialize Inputs
\t\tclk_100MHz = 0;
\t\tclk_de_trabajo = 0;
\t\trst = 1;
\t\tup = 0;
\t\tdown = 0;
\t\tchip_select = 1;
\t\t// Wait 100 ns for global reset to finish
\t\t#10;
\t\trst = 0;
\t\t/*
\t\t#10
\t\tup = 1;
\t\t#50
\t\tup = 0;
*/
\t\t// Add stimulus here
\tend
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: I.T.C.R
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 17:20:57 02/28/2016
// Design Name:
// Module Name: Mux_2x1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mux_2x1(Seleccion,D1,D0,Y);
input wire Seleccion;
input wire [3:0] D1,D0;
output reg [3:0] Y;
always @*
begin
case(Seleccion)
1'b0: Y <= D0;
1'b1: Y <= D1;
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:34:46 03/03/2016
// Design Name:
// Module Name: DPWM
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DPWM
(
input wire CLK_FPGA_BOARD,
input wire boton_aumentar,
input wire boton_disminuir,
input wire seleccion_funcion,
input wire seleccion_salida,
input wire reinicio,
output reg BUCK_Gate,
output reg Full_Bridge,
output wire [3:0] anodos_7seg,
output wire [7:0] catodos_7seg
);
wire boton_aumentar_sincronizado;
wire boton_disminuir_sincronizado;
wire seleccion_funcion_sincronizado;
wire seleccion_salida_sincronizado;
wire reinicio_sincronizado;
wire [3:0] OutCuenta_Modificacion_Frec_Conmu_In_Control_visualizador_numerico;//Cuenta del modulo de modificacion de la frecuencia
wire [3:0] OutCuenta_Modificacion_CT_In_Control_visualizador_numerico;//Cuenta del modulo de modificacion del ciclo de trabajo
wire OutCLK1kHz_Modificacion_Frec_Conmu_In_Control_visualizador_numerico; //clock de 1 kHz fijo para la FSM
wire OutCLKVar_Modificacion_Frec_Conmu_In_Modificacion_CT;//Clock variable que entra al m\xf3dulo de modificacion del ciclo de trabajo
wire OutSignal_Modificacion_Ciclo_Trabajo_In_Distribucion_Salida; //Se\xf1al de conmutaci\xf3n hacia el bloque de distribuci\xf3n de salid
Sincronizador Instancia_Sincronizador(
.incambiarfuncion(seleccion_funcion),
.incambiarsalida(seleccion_salida),
.inrst(reinicio),
.inbtup(boton_aumentar),
.inbtdown(boton_disminuir),
.clk(CLK_FPGA_BOARD),
.outcambiarfuncion(seleccion_funcion_sincronizado),
.outcambiarsalida(seleccion_salida_sincronizado),
.outbtup(boton_aumentar_sincronizado),
.outbtdown(boton_disminuir_sincronizado),
.outrst(reinicio_sincronizado)
);
Modificacion_Frec_Conmu Instancia_Modificacion_Frec_Conmu
(
.CLK_100MHz(CLK_FPGA_BOARD),
.aumentar_Frec(boton_aumentar_sincronizado),
.disminuir_Frec(boton_disminuir_sincronizado),
.funct_select(~seleccion_funcion_sincronizado),
.reset(reinicio_sincronizado),
.CLK_dividido(OutCLKVar_Modificacion_Frec_Conmu_In_Modificacion_CT),
.CLK_1kHz(OutCLK1kHz_Modificacion_Frec_Conmu_In_Control_visualizador_numerico),
.OutContadorAD_InMDF(OutCuenta_Modificacion_Frec_Conmu_In_Control_visualizador_numerico) //Conexiones entre contador y bloque MDF (traductor y divisor de clock), tambi\xe9n para la FSM
);
Modificacion_Ciclo_Trabajo Instancia_Modificacion_Ciclo_Trabajo (
.clk_100MHz(CLK_FPGA_BOARD),
.clk_de_trabajo(OutCLKVar_Modificacion_Frec_Conmu_In_Modificacion_CT),
.rst(reinicio_sincronizado),
.up(boton_aumentar_sincronizado),
.down(boton_disminuir_sincronizado),
.chip_select(seleccion_funcion_sincronizado),
.signal_out(OutSignal_Modificacion_Ciclo_Trabajo_In_Distribucion_Salida),
.ciclo_actual(OutCuenta_Modificacion_CT_In_Control_visualizador_numerico)
);
Control_visualizador_numerico Instancia_Control_visualizador_numerico
(
.cuenta_frec(OutCuenta_Modificacion_Frec_Conmu_In_Control_visualizador_numerico),
.cuenta_CT(OutCuenta_Modificacion_CT_In_Control_visualizador_numerico),
.clock(OutCLK1kHz_Modificacion_Frec_Conmu_In_Control_visualizador_numerico),
.reset(reinicio_sincronizado),
.funct_select(seleccion_funcion_sincronizado),
.code_digitos_decimal(catodos_7seg), //secuencia para mostrar el digito correcto
.code_7seg(anodos_7seg) //secuencia para encender el 7 segmentos correcto
);
////////////////////////////////////
always @(posedge CLK_FPGA_BOARD)
begin
\tif (seleccion_salida_sincronizado) begin
\t\tFull_Bridge <= OutSignal_Modificacion_Ciclo_Trabajo_In_Distribucion_Salida;
\t\tBUCK_Gate <= 0;
\t\tend
\telse begin
\t\tFull_Bridge <= 0;
\t\tBUCK_Gate <= OutSignal_Modificacion_Ciclo_Trabajo_In_Distribucion_Salida;
\t\tend
end
/*
Distribucion_Salida Instancia_Distribucion_Salida
(\t
.In_signal_conmutacion(OutSignal_Modificacion_Ciclo_Trabajo_In_Distribucion_Salida),
.select_salida(seleccion_salida_sincronizado),
.Out_signal_conmutacion({Full_Bridge,BUCK_Gate})//1 para full bridge y 0 para BUCK gate
);
*/
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:21:20 02/21/2016
// Design Name:
// Module Name: Contador_conResetEnable
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Contador_conReset
\t# (parameter N = 4) // Para definir el n\xfamero de bits del contador
\t(
\t\tinput wire clk,
\t\tinput wire reset,
\t\toutput wire [N-1:0] q
);
//Signal Declarations
reg [N-1:0] q_act, q_next;
//Body of "state" registers
always@(posedge clk,posedge reset)
\tif(reset)
\t\tq_act <= 0;
\telse
\t\tq_act <= q_next;
//Specified functions of the counter \t\t
always@*
q_next = q_act + 1\'b1;
\t\t
//Output Logic
assign q = q_act;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:11:32 11/03/2015
// Design Name:
// Module Name: MUX16
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MUX16(Seleccion,Dn,Y);
input [3:0] Seleccion;
input [15:0] Dn;
output Y;
wire [3:0] Seleccion;
wire [15:0] Dn;
wire Y;
assign Y = Dn[Seleccion];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Andr\xe9s Chaves Barrantes
//
// Create Date: 15:16:17 02/21/2016
// Design Name:
// Module Name: Frecuency_Divider
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Frecuency_Divider(
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: ITCR
// Engineer: Yermy Benvaides
//
// Create Date: 20:33:46 02/29/2016
// Design Name:
// Module Name: Traductor
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Traductor(in,out,clk,rst);
input wire clk,rst;
input wire [3:0]in;
output reg [10:0]out;
always@(posedge clk, posedge rst)
\tif (rst)
\t\tbegin
\t\tout <= 11'd0;
\t\tend
\telse
\t\tcase(in)
\t\t\t4'b0000: out <= 11'd1666;
\t\t\t4'b0001: out <= 11'd999;
\t\t\t4'b0010: out <= 11'd666;
\t\t\t4'b0011: out <= 11'd499;
\t\t\t4'b0100: out <= 11'd399;
\t\t\t4'b0101: out <= 11'd332;
\t\t\t4'b0110: out <= 116'd285;
\t\t\t4'b0111: out <= 11'd249;
\t\t\t4'b1000: out <= 11'd221;
\t\t\t4'b1001: out <= 11'd199;
\t\t\t4'b1010: out <= 11'd181;
\t\t\t4'b1011: out <= 11'd165;
\t\t\t4'b1100: out <= 11'd152;
\t\t\t4'b1101: out <= 11'd141;
\t\t\t4'b1110: out <= 11'd132;
\t\t\t4'b1111: out <= 11'd124;
\t\t\tdefault out <= 11'd0;
\t\tendcase
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: I.T.C.R
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 11:47:39 02/28/2016
// Design Name:
// Module Name: FSM
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM
(
\tinput wire clk,rst, //\tClock y reset
\tinput wire Funct_Select,// Entradas
\tinput wire [3:0] Count_CT,
\tinput wire [3:0] Count_F,
\toutput reg [3:0]C_Digit, //Current digit y current 7 segmentos
\toutput reg [3:0]C_7Seg // Salidas, definidas como reg
);
wire [3:0] Multiplexed_Count;
//Mux_2x1 instancia_Mux_2x1 (.Seleccion(Funct_Select),.D1(Count_CT),.D0(Count_F),.Y(Multiplexed_Count));
Mux_2x1 instancia_MUX_2x1 (
.Seleccion(Funct_Select),
.D1(Count_CT),
.D0(Count_F),
.Y(Multiplexed_Count)
);
//*********************************************************
localparam [3:0]
// Codificaci\xf3n de los estados o etiquetas
Eval_Funct_Select = 4'b0000,
Send_PNumb_CT = 4'b0001, //Mandar primer d\xedgito ciclo de trabajo
Send_SNumb_CT = 4'b0010, //Mandar segundo d\xedgito ciclo de trabajo
Send_TNumb_CT = 4'b0011, //Mandar tercer d\xedgito ciclo de trabajo
Send_CNumb_CT = 4'b0100, //Mandar cuarto d\xedgito ciclo de trabajo
Send_PNumb_F = 4'b0101, //Mandar primer d\xedgito frecuencia
Send_SNumb_F = 4'b0110, //Mandar segundo d\xedgito frecuencia
Send_TNumb_F = 4'b0111, //Mandar tercer d\xedgito frecuencia
Send_CNumb_F = 4'b1000; //Mandar cuarto d\xedgito frecuencia
reg [3:0] state, state_next;
// Reg, estado actual y siguiente
//*********************************************************
//Parte Secuencial
always@(posedge clk, posedge rst)
begin
\tif(rst)
\t\tstate <= Eval_Funct_Select;
\telse
\t\tstate <= state_next;
end
//*********************************************************
//Parte Combinacional
always@*
begin
\tstate_next = state;
\tC_Digit = 0;
\tC_7Seg = 0;
\t
case(state)
//-------------------------------------------\t\t
\t\tEval_Funct_Select:
\t\t
\t\tif(Funct_Select)
\t\tbegin
\t\tstate_next = Send_PNumb_CT;
\t\tend
\t\telse
\t\tbegin
\t\tstate_next = Send_PNumb_F;
\t\tend
//-------------------------------------------\t\t\t
Send_PNumb_CT:
\t\t
\t\tbegin
\t\tstate_next = Send_SNumb_CT;
\t\tC_7Seg = 4'h8;\t\t
\t\t
\t\tcase(Multiplexed_Count)
\t\t
\t\t4'h0: C_Digit = 4'h0;
\t\t4'h1: C_Digit = 4'h0;
\t\t4'h2: C_Digit = 4'h0;
\t\t4'h3: C_Digit = 4'h0;
\t\t4'h4: C_Digit = 4'h0;
\t\t4'h5: C_Digit = 4'h0;
\t\t4'h6: C_Digit = 4'h0;
\t\t4'h7: C_Digit = 4'h0;
\t\t4'h8: C_Digit = 4'h0;
\t\t4'h9: C_Digit = 4'h0;
\t\t4'hA: C_Digit = 4'h0;
\t\t4'hB: C_Digit = 4'h0;
\t\t4'hC: C_Digit = 4'h0;
\t\t4'hD: C_Digit = 4'h0;
\t\t4'hE: C_Digit = 4'h0;
\t\t4'hF: C_Digit = 4'h1;
\t\tendcase
\t\t
\t\tend
//-------------------------------------------\t\t
Send_SNumb_CT:
\t\t
\t\tbegin
\t\tstate_next = Send_TNumb_CT;
\t\tC_7Seg = 4'h4;
\t\t
\t\tcase(Multiplexed_Count)
\t\t
\t\t4'h0: C_Digit = 4'h0;
\t\t4'h1: C_Digit = 4'h0;
\t\t4'h2: C_Digit = 4'h1;
\t\t4'h3: C_Digit = 4'h2;
\t\t4'h4: C_Digit = 4'h2;
\t\t4'h5: C_Digit = 4'h3;
\t\t4'h6: C_Digit = 4'h4;
\t\t4'h7: C_Digit = 4'h4;
\t\t4'h8: C_Digit = 4'h5;
\t\t4'h9: C_Digit = 4'h6;
\t\t4'hA: C_Digit = 4'h6;
\t\t4'hB: C_Digit = 4'h7;
\t\t4'hC: C_Digit = 4'h8;
\t\t4'hD: C_Digit = 4'h8;
\t\t4'hE: C_Digit = 4'h9;
\t\t4'hF: C_Digit = 4'h0;
\t\tendcase
\t\t
\t\tend
//-------------------------------------------
Send_TNumb_CT:
\t\t
\t\tbegin
\t\tstate_next = Send_CNumb_CT;
\t\tC_7Seg = 4'h2;\t\t\t
\t\t
\t\tcase(Multiplexed_Count)
\t\t
\t\t4'h0: C_Digit = 4'h0;
\t\t4'h1: C_Digit = 4'h6;
\t\t4'h2: C_Digit = 4'h3;
\t\t4'h3: C_Digit = 4'h0;
\t\t4'h4: C_Digit = 4'h6;
\t\t4'h5: C_Digit = 4'h3;
\t\t4'h6: C_Digit = 4'h0;
\t\t4'h7: C_Digit = 4'h6;
\t\t4'h8: C_Digit = 4'h3;
\t\t4'h9: C_Digit = 4'h0;
\t\t4'hA: C_Digit = 4'h6;
\t\t4'hB: C_Digit = 4'h3;
\t\t4'hC: C_Digit = 4'h0;
\t\t4'hD: C_Digit = 4'h6;
\t\t4'hE: C_Digit = 4'h3;
\t\t4'hF: C_Digit = 4'h0;
\t\tendcase
\t\t
\t\tend
//-------------------------------------------\t\t
Send_CNumb_CT:
\t\t
\t\tbegin
\t\tstate_next = Eval_Funct_Select;
\t\tC_7Seg = 4'h1;\t
\t\t
\t\tcase(Multiplexed_Count)
\t\t
\t\t4'h0: C_Digit = 4'h0;
\t\t4'h1: C_Digit = 4'h7;
\t\t4'h2: C_Digit = 4'h3;
\t\t4'h3: C_Digit = 4'h0;
\t\t4'h4: C_Digit = 4'h7;
\t\t4'h5: C_Digit = 4'h3;
\t\t4'h6: C_Digit = 4'h0;
\t\t4'h7: C_Digit = 4'h7;
\t\t4'h8: C_Digit = 4'h3;
\t\t4'h9: C_Digit = 4'h0;
\t\t4'hA: C_Digit = 4'h7;
\t\t4'hB: C_Digit = 4'h3;
\t\t4'hC: C_Digit = 4'h0;
\t\t4'hD: C_Digit = 4'h7;
\t\t4'hE: C_Digit = 4'h3;
\t\t4'hF: C_Digit = 4'h0;
\t\tendcase
\t\t
\t\tend
//-------------------------------------------
Send_PNumb_F:
\t\t
\t\tbegin
\t\tstate_next = Send_SNumb_F;
\t\tC_7Seg = 4'h8;\t
\t\t
\t\tcase(Multiplexed_Count)
\t\t
\t\t4'h0: C_Digit = 4'h0;
\t\t4'h1: C_Digit = 4'h0;
\t\t4'h2: C_Digit = 4'h0;
\t\t4'h3: C_Digit = 4'h0;
\t\t4'h4: C_Digit = 4'h0;
\t\t4'h5: C_Digit = 4'h0;
\t\t4'h6: C_Digit = 4'h0;
\t\t4'h7: C_Digit = 4'h0;
\t\t4'h8: C_Digit = 4'h0;
\t\t4'h9: C_Digit = 4'h0;
\t\t4'hA: C_Digit = 4'h0;
\t\t4'hB: C_Digit = 4'h0;
\t\t4'hC: C_Digit = 4'h0;
\t\t4'hD: C_Digit = 4'h0;
\t\t4'hE: C_Digit = 4'h0;
\t\t4'hF: C_Digit = 4'h0;
\t\tendcase
\t\t
\t\tend
//-------------------------------------------
Send_SNumb_F:
\t\t
\t\tbegin
\t\tstate_next = Send_TNumb_F;
\t\tC_7Seg = 4'h4;\t
\t\t
\t\tcase(Multiplexed_Count)
\t\t
\t\t4'h0: C_Digit = 4'h0;
\t\t4'h1: C_Digit = 4'h0;
\t\t4'h2: C_Digit = 4'h0;
\t\t4'h3: C_Digit = 4'h1;
\t\t4'h4: C_Digit = 4'h1;
\t\t4'h5: C_Digit = 4'h1;
\t\t4'h6: C_Digit = 4'h1;
\t\t4'h7: C_Digit = 4'h2;
\t\t4'h8: C_Digit = 4'h2;
\t\t4'h9: C_Digit = 4'h2;
\t\t4'hA: C_Digit = 4'h2;
\t\t4'hB: C_Digit = 4'h3;
\t\t4'hC: C_Digit = 4'h3;
\t\t4'hD: C_Digit = 4'h3;
\t\t4'hE: C_Digit = 4'h3;
\t\t4'hF: C_Digit = 4'h4;
\t\tendcase
\t\t
\t\tend
//-------------------------------------------
Send_TNumb_F:
\t\t
\t\tbegin
\t\tstate_next = Send_CNumb_F;
\t\tC_7Seg = 4'h2;\t
\t\t
\t\tcase(Multiplexed_Count)
\t\t
\t\t4'h0: C_Digit = 4'h3;
\t\t4'h1: C_Digit = 4'h5;
\t\t4'h2: C_Digit = 4'h7;
\t\t4'h3: C_Digit = 4'h0;
\t\t4'h4: C_Digit = 4'h2;
\t\t4'h5: C_Digit = 4'h5;
\t\t4'h6: C_Digit = 4'h7;
\t\t4'h7: C_Digit = 4'h0;
\t\t4'h8: C_Digit = 4'h2;
\t\t4'h9: C_Digit = 4'h5;
\t\t4'hA: C_Digit = 4'h7;
\t\t4'hB: C_Digit = 4'h0;
\t\t4'hC: C_Digit = 4'h2;
\t\t4'hD: C_Digit = 4'h5;
\t\t4'hE: C_Digit = 4'h7;
\t\t4'hF: C_Digit = 4'h0;
\t\tendcase
\t\t
\t\tend
//-------------------------------------------
Send_CNumb_F:
\t\t
\t\tbegin
\t\tstate_next = Eval_Funct_Select;
\t\tC_7Seg = 4'h1;\t
\t\t
\t\tcase(Multiplexed_Count)
\t\t
\t\t4'h0: C_Digit = 4'h0;
\t\t4'h1: C_Digit = 4'h0;
\t\t4'h2: C_Digit = 4'h5;
\t\t4'h3: C_Digit = 4'h0;
\t\t4'h4: C_Digit = 4'h5;
\t\t4'h5: C_Digit = 4'h0;
\t\t4'h6: C_Digit = 4'h5;
\t\t4'h7: C_Digit = 4'h0;
\t\t4'h8: C_Digit = 4'h5;
\t\t4'h9: C_Digit = 4'h0;
\t\t4'hA: C_Digit = 4'h5;
\t\t4'hB: C_Digit = 4'h0;
\t\t4'hC: C_Digit = 4'h5;
\t\t4'hD: C_Digit = 4'h0;
\t\t4'hE: C_Digit = 4'h5;
\t\t4'hF: C_Digit = 4'h0;
\t\tendcase
\t\t
\t\tend
//-------------------------------------------
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:52:22 02/15/2015
// Design Name:
// Module Name: Universal_Binary_Counter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Universal_Binary_Counter(\t
out , // Output of the counter
clk , // clock Input
rst // reset Input
);
output reg [3:0] out;
input clk, rst;
reg bandera;
\t
always @(posedge clk, posedge rst)
if (rst) begin
out <= 8'b0;
bandera = 0;
end
else if (bandera == 0)
\tbegin
\tout <= out + 4'b1;
\tif (out==16) out <=4 'b0;
\tend
else if (bandera==1)
\tbegin
\tout <= out - 4'b1;
\tif(out==0) bandera =1;
\tend
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: ITCR
// Engineer: Yermy Benavides
//
// Create Date: 11:46:16 02/23/2016
// Design Name:
// Module Name: Comp_16bits
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Comp_16bits(in,out,rst,ref,clk);
input wire [3:0] in, ref;
input wire rst,clk;
output reg out;
always@(posedge clk,posedge rst)
if (rst) out = 1'b0;
else if (in >= ref) out = 1'b1;
else out = 1'b0;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 17:39:32 03/02/2016
// Design Name:
// Module Name: Modificacion_Frec_Conmu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Modificacion_Frec_Conmu
\t(
\tinput wire CLK_100MHz,
\tinput wire aumentar_Frec,
\tinput wire disminuir_Frec,
\tinput wire funct_select,
\tinput wire reset,
\toutput wire CLK_dividido,
\toutput wire CLK_1kHz,
\toutput wire [3:0] OutContadorAD_InMDF //Conexiones entre contador y bloque MDF (traductor y divisor de clock), tambi\xe9n para la FSM
);
wire OutRegistroAumentar_InContadorADAumentar; //Conexiones entre registro y contador A/D
wire OutRegistroDisminuir_InContadorADDisminuir;
Registro_Universal Instancia_Registro_Universal(
.aumentar(aumentar_Frec), //boton aumentar
.disminuir(disminuir_Frec), //boton disminuir
.clk(CLK_100MHz), //system clock
.reset(reset), //system reset
.chip_select(~funct_select), //Control data (funct_select)
.out_aumentar(OutRegistroAumentar_InContadorADAumentar), //boton aumentar
.out_disminuir(OutRegistroDisminuir_InContadorADDisminuir) //boton disminuir
);
Contador_Ascendente_Descendente Instancia_Contador_Ascendente_Descendente(
.clk(CLK_100MHz),
.reset(reset),
.enUP(OutRegistroAumentar_InContadorADAumentar),
.enDOWN(OutRegistroDisminuir_InContadorADDisminuir),
.q(OutContadorAD_InMDF)
);
MDF Instancia_MDF(
.clk(CLK_100MHz),
.rst(reset),
.entrada(OutContadorAD_InMDF),
.salida(CLK_dividido),
.salida_1kHz(CLK_1kHz),
.q()
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:33:10 03/01/2016
// Design Name:
// Module Name: Sincronizador
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Sincronizador(incambiarfuncion,incambiarsalida,inrst,inbtup,inbtdown,outcambiarfuncion,outcambiarsalida,outrst,outbtup,outbtdown,clk);
input wire incambiarfuncion,incambiarsalida,inrst,inbtup,inbtdown,clk;
output wire outcambiarfuncion,outcambiarsalida,outbtup,outbtdown,outrst;
Synchro S1 (
.dato(incambiarfuncion),
.clk(clk),
.ds(outcambiarfuncion)
);
\t
Synchro S2 (
.dato(incambiarsalida),
.clk(clk),
.ds(outcambiarsalida)
);
Synchro S3 (
.dato(inrst),
.clk(clk),
.ds(outrst)
);
Synchro S4 (
.dato(inbtup),
.clk(clk),
.ds(outbtup)
);
Synchro S5 (
.dato(inbtdown),
.clk(clk),
.ds(outbtdown)
);
endmodule
|
`timescale 10ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:02:39 03/03/2016
// Design Name: Modificacion_Ciclo_Trabajo
// Module Name: D:/ISE/PRIMER_PROYECTO/TB_Modificador_ciclo_trabajo.v
// Project Name: PRIMER_PROYECTO
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Modificacion_Ciclo_Trabajo
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_Modificador_ciclo_trabajo;
\t// Inputs
\treg clk_100MHz;
\treg clk_de_trabajo;
\treg rst;
\treg up;
\treg down;
\treg func_select;
\treg chip_select;
\t// Outputs
\twire signal_out;
\twire [3:0] ciclo_actual;
\t
\t// Instantiate the Unit Under Test (UUT)
\tModificacion_Ciclo_Trabajo uut (
\t\t.clk_100MHz(clk_100MHz),
\t\t.clk_de_trabajo(clk_de_trabajo),
\t\t.rst(rst),
\t\t.up(up),
\t\t.down(down),
\t\t.func_select(func_select),
\t\t.chip_select(chip_select),
\t\t.signal_out(signal_out),
\t\t.ciclo_actual(ciclo_actual)
\t\t
\t);
\tinitial begin
\t\t// Initialize Inputs
\t\tclk_100MHz = 0;
\t\tclk_de_trabajo = 0;
\t\trst = 0;
\t\tup = 0;
\t\tdown = 0;
\t\tfunc_select = 0;
\t\tchip_select = 0;
\t\t// Wait 100 ns for global reset to finish
\t\t#10;
\t\trst=1;
\t\t#10
\t\trst=0;
\t\t
\t\t#10
\t\tup=1;
\t\t//#2
\t\t/*
\t\tup=0;
\t\t#70
\t\tdown=1;
\t\t
\t\t*/
\t\t
\t\t// Add stimulus here
\tend
always #10 clk_100MHz = ~clk_100MHz;
always #60 clk_de_trabajo = ~clk_de_trabajo;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 18:53:02 03/02/2016
// Design Name:
// Module Name: Distribucion_Salida
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Distribucion_Salida
(\t
\t input wire In_signal_conmutacion,
\t input wire select_salida,
\t output wire [1:0] Out_signal_conmutacion
);
Demux Instancia_Demux(
.out(Out_signal_conmutacion),
.in(In_signal_conmutacion),
.sel(select_salida));
endmodule |
LIBAVFILTER_$MAJOR {
global: avfilter_*; av_*;
local: *;
};
|
LIBAVUTIL_$MAJOR {
global: av*;
local: *;
};
|
LIBSWSCALE_$MAJOR {
global: swscale_*; sws_*;
local: *;
};
|
LIBSWRESAMPLE_$MAJOR {
global: swr_*; swresample_*;
local: *;
};
|
LIBAVFORMAT_$MAJOR {
global: av*;
#FIXME those are for ffserver
ff_inet_aton;
ff_socket_nonblock;
ff_rtsp_parse_line;
ff_rtp_get_local_rtp_port;
ff_rtp_get_local_rtcp_port;
ffio_open_dyn_packet_buf;
ffio_set_buf_size;
ffurl_close;
ffurl_open;
ffurl_read_complete;
ffurl_seek;
ffurl_size;
ffurl_write;
#those are deprecated, remove on next bump
url_feof;
local: *;
};
|
LIBAVDEVICE_$MAJOR {
global: avdevice_*; av_*;
local: *;
};
|
LIBPOSTPROC_$MAJOR {
global: postproc_*; pp_*;
local: *;
};
|
LIBAVCODEC_$MAJOR {
global: av*;
#deprecated, remove after next bump
audio_resample;
audio_resample_close;
local: *;
};
|
LIBAVRESAMPLE_$MAJOR {
global: av*;
local: *;
};
|
always @(negedge reset or posedge clk) begin
if (reset == 0) begin
d_out <= 16'h0000;
d_out_mem[resetcount] <= d_out;
laststoredvalue <= d_out;
end else begin
d_out <= d_out + 1'b1;
end
end
always @(bufreadaddr)
bufreadval = d_out_mem[bufreadaddr]; |
/**************************************************************************
****
* test task one
* the line below has 53 asteriks
*****************************************************/
task pass_task_1;
begin
end
endtask
/**************************************************************************
****
* test task one
* the line below has 54 asteriks
******************************************************/
task fail_task_2;
begin
end
endtask
/**************************************************************************
****
* test function one
* the line below has 53 asteriks
*****************************************************/
function pass_func_1;
begin
end
endfunction
/**************************************************************************
****
* test function two
* the line below has 54 asteriks
******************************************************/
function fail_func_2;
begin
end
endfunction
/**************************************************************************
****
* test function one
* the line below has 53 asteriks
*****************************************************/
`define pass_define_1 1'b1;
/**************************************************************************
****
* test function two
* the line below has 54 asteriks
******************************************************/
`define fail_define_2 1'b1;
|
/*
Bugs item #762027, was opened at 2003-06-27 18:32
Message generated for change (Tracker Item Submitted) made by Item Submitter
You can respond by visiting:
https://sourceforge.net/tracker/?func=detail&atid=106556&aid=762027&group_id=6556
Category: None
Group: None
Status: Open
Resolution: None
Priority: 5
Submitted By: cdic (cdic)
Assigned to: Nobody/Anonymous (nobody)
Summary: multi-line definition w/o back-slash will be missing
Initial Comment:
There is a small bug (language verilog):
*/
wire N_84, N_83; // is ok.
wire N_84,
N_83; // then N_83 will be missing in tags.
/*
Thanks for fixing it.
cdic
*/
|
parameter ramaddr_0 = {1'b1,9'd0};
|
// somewhat contrived, but i came across a real-life file that caused this
// crash.
value=
hello/
world;
|
// File example.v
//
// Below is an example of a comment that is mis-parsed by exuberant ctags.
// It uses the multi-line comment format, i.e. /* ... */ except that in
// this case, the character sequence immediately preceeding the closing
// delimiter is an asterisk. (Any even number of asterisks would have the
// same problem.
// The line immediately afterwards is used to demonstrate the problem.
// the module name 'wahoo' isn't recognised, because the parser mistakenly
// thinks we are still in a multi-line comment.
/*
* I am a multi-line comment
* I happen to end in a strange
* (but legal) way: **/
module wahoo ()
begin
end
|
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33
// Digital model of a traffic light
// By Dan Hyde August 10, 1995
module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red = off; amber = off; green = off;
$display(" Time green amber red");
$monitor("%3d %b %b %b", $time, green, amber, red);
end
// task to wait for \'tics\' positive edge clocks
// before turning light off
task light;
output color;
input [31:0] tics;
begin
repeat(tics) // wait to detect tics positive edges on clock
@(posedge clock);
color = off;
end
endtask
// waveform for clock period of 2 time units
always begin: clock_wave
#1 clock = 0;
#1 clock = 1;
end
always begin: main_process
red = on;
light(red, red_tics); // call task to wait
green = on;
light(green, green_tics);
amber = on;
light(amber, amber_tics);
end
endmodule
|
/*
*
**/
module top(outsig, insig);
output outsig;
input insig;
assign outsig = insig;
endmodule
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
/*
* In Verilog, the following two lines are both valid syntax:
*
* `define GUEST
* `define GUEST <value>
*
* The first defines "GUEST" as existing, but with no assigned
* value. The second defines "GUEST" as existing with an
* assigned value. Ctags55 correctly handles both cases, but
* Ctags551 - Ctags554 only handles the `define with value
* correctly. Here is some test code to demonstrate this:
*/
`define HOSTA
`define HOSTB
`define HOSTC
`define HOSTD
`define GUESTA 1
`define GUESTB 2
`define GUESTC 3
`define GUESTD 4
/*
* Ctags55 correctly generates a tag for all `defines in the
* code, but Ctags554 does not generate tags for "HOSTB"
* or "HOSTD".
*/
|
//phase 2: testing basic op codes with the n,z,c flags, 64bit
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:23];
wire [63:0] iaddrbus;
reg [63:0] iaddrbusout[0:23];
wire [31:0] dselect;
reg [31:0] dselectout[0:23];
wire [63:0] dbus;
reg [63:0] dbusout[0:23];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [31:0] dontcare_addr;
reg [24*8:1] iname[0:23];
integer error, k, ntests;
//all opcode parameters to be used
parameter ADD = 11\'b10001011000;
parameter ADDI = 10\'b1001000100;
parameter ADDIS = 10\'b1011000100;
parameter ADDS = 11\'b10101011000;
parameter AND = 11\'b10001010000;
parameter ANDI = 10\'b1001001000;
parameter ANDIS = 10\'b1111001000;
parameter ANDS = 11\'b11101010000;
//CBNZ
//CBZ
parameter EOR = 11\'b11001010000;
parameter EORI = 10\'b1101001000;
//LDUR
//parameter LW = \'b;
//LSL
//LSR
//MOVZ
parameter ORR = 11\'b10101010000;
parameter ORRI = 10\'b1011001000;
//STUR
//parameter SW = \'b;
parameter SUB = 11\'b11001011000;
parameter SUBI = 10\'b1101000100;
parameter SUBIS = 10\'b1111000100;
parameter SUBS = 11\'b11101011000;
//B
//parameter B.EQ = \'b;
//parameter B.NE = \'b;
//parameter SLT = \'b;
//parameter SLE = \'b
//register parameters
parameter R0 = 5\'b00000;
parameter R0_dselect = 32\'b00000000000000000000000000000001;
parameter R20 = 5\'b10100;
parameter R20_dselect = 32\'b00000000000100000000000000000000;
parameter R21 = 5\'b10101;
parameter R21_dselect = 32\'b00000000001000000000000000000000;
parameter R22 = 5\'b10110;
parameter R22_dselect = 32\'b00000000010000000000000000000000;
parameter R23 = 5\'b10111;
parameter R23_dselect = 32\'b00000000100000000000000000000000;
parameter R24 = 5\'b11000;
parameter R24_dselect = 32\'b00000001000000000000000000000000;
parameter R25 = 5\'b11001;
parameter R25_dselect = 32\'b00000010000000000000000000000000;
parameter R26 = 5\'b11010;
parameter R26_dselect = 32\'b00000100000000000000000000000000;
parameter R27 = 5\'b11011;
parameter R27_dselect = 32\'b00001000000000000000000000000000;
parameter R28 = 5\'b11100;
parameter R28_dselect = 32\'b00010000000000000000000000000000;
parameter R29 = 5\'b11101;
parameter R29_dselect = 32\'b00100000000000000000000000000000;
parameter R30 = 5\'b11110;
parameter R30_dselect = 32\'b01000000000000000000000000000000;
parameter R31 = 5\'b11111;
parameter R31_dselect = 32\'b10000000000000000000000000000000;
//other parameterz to be used
parameter zeroSham = 6\'b000000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.dbus(dbus),.dselect(dselect));
initial begin
dontcare = 64\'hx;
dontcare_addr = 32\'hx;
//phase 1: testing basic op commands and instruction bus
//* ADDI, R20, R31, #AAA
iname[0] = "ADDI, R20, R31, #AAA";//testing addi, result in R20 = 00000AAA
iaddrbusout[0] = 64\'h00000000;
// opcode rm/ALUImm rn rd...
instrbusin[0]={ADDI, 12\'hAAA, R31, R20};
dselectout[0] = R20_dselect;
dbusout[0] = 64\'h00000AAA;
//* ADDI, R31, R23, #002
iname[1] = "ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 00000000
iaddrbusout[1] = 64\'h00000004;
// opcode rm/ALUImm rn rd...
instrbusin[1]={ADDI, 12\'h002, R23, R31};
dselectout[1] = R31_dselect;
dbusout[1] = dontcare;
//* ADDI, R0, R23, #002
iname[2] = "ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 00000002
iaddrbusout[2] = 64\'h00000008;
// opcode rm/ALUImm rn rd...
instrbusin[2]={ADDI, 12\'h002, R23, R0};
dselectout[2] = R0_dselect;
dbusout[2] = 64\'h00000002;
//* ORRI, R21, R24, #001
iname[3] = "ORRI, R21, R24, #001";//testing ori, result in R21 = 00000001
iaddrbusout[3] = 64\'h0000000C;
// opcode rm/ALUImm rn rd...
instrbusin[3]={ORRI, 12\'h001, R24, R21};
dselectout[3] = R21_dselect;
dbusout[3] = 64\'h00000001;
//* EORI, R22, R20, #000
iname[4] = "EORI, R22, R20, #000";//testing xori, result in R22 = 00000AAA
iaddrbusout[4] = 64\'h00000010;
// opcode rm/ALUImm rn rd...
instrbusin[4]={EORI, 12\'h000, R20, R22};
dselectout[4] = R22_dselect;
dbusout[4] = 64\'h00000AAA;
//* ANDI, R23, R0, #003
iname[5] = "ANDI, R23, R0, #003";//testing andi, result in R23 = 00000002
iaddrbusout[5] = 64\'h00000014;
// opcode rm/ALUImm rn rd...
instrbusin[5]={ANDI, 12\'h003, R0, R23};
dselectout[5] = R23_dselect;
dbusout[5] = 64\'h00000002;
//* SUBI, R24, R20, #00A
iname[6] = "SUBI, R24, R20, #00A";//testing subi, result in R24 = 00000AA0
iaddrbusout[6] = 64\'h00000018;
// opcode rm/ALUImm rn rd...
instrbusin[6]={SUBI, 12\'h00A, R20, R24};
dselectout[6] = R24_dselect;
dbusout[6] = 64\'h00000AA0;
// op, rd, rn, rm
//* ADD, R25, R20, R0
iname[7] = "ADD, R25, R20, R0";//testing add, result in R25 = 00000AAC
iaddrbusout[7] = 64\'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7]={ADD, R0, zeroSham, R20, R25};
dselectout[7] = R25_dselect;
dbusout[7] = 64\'h00000AAC;
// op, rd, rn, rm
//* AND, R26, R20, R22
iname[8] = "AND, R26, R20, R22";//testing and, result in R26 = 00000AAA
iaddrbusout[8] = 64\'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8]={AND, R22, zeroSham, R20, R26};
dselectout[8] = R26_dselect;
dbusout[8] = 64\'h00000AAA;
// op, rd, rn, rm
//* XOR, R27, R23, R21
iname[9] = "EOR, R27, R23, R21";//testing xor, result in R27 = 00000003
iaddrbusout[9] = 64\'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9]={EOR, R21, zeroSham, R23, R27};
dselectout[9] = R27_dselect;
dbusout[9] = 64\'h00000003;
// op, rd, rn, rm
//* OR, R28, R25, R23
iname[10] = "ORR, R28, R25, R23";//testing or, result in R28 = 00000AAE
iaddrbusout[10] = 64\'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10]={ORR, R23, zeroSham, R25, R28};
dselectout[10] = R28_dselect;
dbusout[10] = 64\'h00000AAE;
// op, rd, rn, rm
//* SUB, R29, R20, R22
iname[11] = "SUB, R29, R20, R22";//testing sub, result in R29 = 00000000
iaddrbusout[11] = 64\'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11]={SUB, R22, zeroSham, R20, R29};
dselectout[11] = R29_dselect;
dbusout[11] = 64\'h00000000;
// op, rd, rn, aluImm
//* ADDI, R30, R31, #000
iname[12] = "ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 00000000
iaddrbusout[12] = 64\'h00000030;
// opcode rm/ALUImm rn rd...
instrbusin[12]={ADDI, 12\'h000, R31, R30};
dselectout[12] = R30_dselect;
dbusout[12] = 64\'h00000000;
//phase 2: testing basic op codes with the n,z,c flags
// op, rd, rn, aluImm
//* SUBIS,R20, R0, #003
iname[13] = "SUBIS,R20, R0, #003";//testing subis, n flag, result in R20 = FFFFFFFF
iaddrbusout[13] = 64\'h00000034;
// opcode rm/ALUImm rn rd...
instrbusin[13] = {SUBIS, 12\'h003, R0, R20};
dselectout[13] = dontcare;
dbusout[13] = dontcare;
// op, rd, rn, rm
//* SUBS, R21, R25, R28
iname[14] = "SUBS, R21, R25, R28";//testing subs, n flag, result in R21 = FFFFFFFE
iaddrbusout[14] = 64\'h00000038;
// op, rm, shamt, rn, rd
instrbusin[14] = {SUBS, R28, zeroSham, R25, R21};
dselectout[14] = dontcare;
dbusout[14] = dontcare;
// op, rd, rn, aluImm
//* ADDIS,R22, R31, #000
iname[15] = "ADDIS,R22, R31, #000";//testing addis, z flag, result in R22 = 00000000
iaddrbusout[15] = 64\'h0000003C;
// opcode rm/ALUImm rn rd...
instrbusin[15] = {ADDIS, 12\'h000, R31, R22};
dselectout[15] = dontcare;
dbusout[15] = dontcare;
// op, rd, rn, rm
//* ADDS R23, R20, R23
iname[16] = "ADDS R23, R20, R23";//testing adds, c flag, result in R23 = 00000001
iaddrbusout[16] = 64\'h00000040;
// op, rm, shamt, rn, rd
instrbusin[16] = {ADDS, R23, zeroSham, R20, R23};
dselectout[16] = dontcare;
dbusout[16] = dontcare;
// op, rd, rn, aluImm
//* ANDIS,R24, R20, #002
iname[17] = "ANDIS,R24, R20, #002";//testing andis, reseting n,z flags to low, result in R24 = 00000002
iaddrbusout[17] = 64\'h00000044;
// opcode rm/ALUImm rn rd...
instrbusin[17] = {ANDIS, 12\'h002, R20, R24};
dselectout[17] = dontcare;
dbusout[17] = dontcare;
// op, rd, rn, rm
//* ANDS, R25, R21, R20
iname[18] = "ANDS, R25, R21, R20";//testing ands, n flag, result in R25 = FFFFFFFE
iaddrbusout[18] = 64\'h00000048;
// op, rm, shamt, rn, rd
instrbusin[18] = {ANDS, R20, zeroSham, R21, R25};
dselectout[18] = dontcare;
dbusout[18] = dontcare;
//* NOP
iaddrbusout[19] = 64\'h0000004C;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[19] = 32\'b00000000000000000000000000000000;
dselectout[19] = dontcare_addr;
dbusout[19] = dontcare;
//* NOP
iaddrbusout[20] = 64\'h00000050;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[20] = 32\'b00000000000000000000000000000000;
dselectout[20] = dontcare_addr;
dbusout[20] = dontcare;
//* NOP
iaddrbusout[21] = 64\'h00000054;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[21] = 32\'b00000000000000000000000000000000;
dselectout[21] = dontcare_addr;
dbusout[21] = dontcare;
//* NOP
iaddrbusout[22] = 64\'h00000058;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[22] = 32\'b00000000000000000000000000000000;
dselectout[22] = dontcare_addr;
dbusout[22] = dontcare;
//* NOP
iaddrbusout[23] = 64\'h0000005C;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[23] = 32\'b00000000000000000000000000000000;
dselectout[23] = dontcare_addr;
dbusout[23] = dontcare;
ntests = 24;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
//assign databus = clkd ? 32\'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
//databusk = 32\'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
$display ("Time=%t\
clk=%b", $realtime, clk);
for (k=0; k<= 23; k=k+1) begin
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set dbus and dselect data data for 4th previous instruction
if (k >=4)
//databusk = databusin[k-4];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b%b%b%b%b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check writeback data address from 4th previous instruction
if ( (k >= 4) && (dselectout[k-4] !== dontcare_addr) ) begin
$display (" Testing writeback data address for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dselect = %b", dselect);
$display (" Correct dselect = %b", dselectout[k-4]);
if (dselectout[k-4] !== dselect) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check writeback data from 4th previous instruction
if ( (k >= 4) && (dbusout[k-4] !== dontcare) ) begin
$display (" Testing writeback data for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dbus = %b", dbus);
$display (" Correct dbus = %b", dbusout[k-4]);
if (dbusout[k-4] !== dbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("-----SIMULATION INCONCLUSIVE - CHECK YOUR NZVC BIT(S) IN THE SCOPE------");
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
//phase 2: testing basic op codes with the n,z,c flags, 32bit
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:23];
wire [31:0] iaddrbus, dselect;
reg [31:0] iaddrbusout[0:23], dselectout[0:23];
wire [31:0] dbus;
reg [31:0] databusk, dbusout[0:23];
reg clk, reset;
reg clkd;
reg [31:0] dontcare;
reg [24*8:1] iname[0:23];
integer error, k, ntests;
//all opcode parameters to be used
parameter ADD = 11\'b10001011000;
parameter ADDI = 10\'b1001000100;
parameter ADDIS = 10\'b1011000100;
parameter ADDS = 11\'b10101011000;
parameter AND = 11\'b10001010000;
parameter ANDI = 10\'b1001001000;
parameter ANDIS = 10\'b1111001000;
parameter ANDS = 11\'b11101010000;
//CBNZ
//CBZ
parameter EOR = 11\'b11001010000;
parameter EORI = 10\'b1101001000;
//LDUR
//parameter LW = \'b;
//LSL
//LSR
//MOVZ
parameter ORR = 11\'b10101010000;
parameter ORRI = 10\'b1011001000;
//STUR
//parameter SW = \'b;
parameter SUB = 11\'b11001011000;
parameter SUBI = 10\'b1101000100;
parameter SUBIS = 10\'b1111000100;
parameter SUBS = 11\'b11101011000;
//B
//parameter B.EQ = \'b;
//parameter B.NE = \'b;
//parameter SLT = \'b;
//parameter SLE = \'b
//register parameters
parameter R0 = 5\'b00000;
parameter R0_dselect = 32\'b00000000000000000000000000000001;
parameter R20 = 5\'b10100;
parameter R20_dselect = 32\'b00000000000100000000000000000000;
parameter R21 = 5\'b10101;
parameter R21_dselect = 32\'b00000000001000000000000000000000;
parameter R22 = 5\'b10110;
parameter R22_dselect = 32\'b00000000010000000000000000000000;
parameter R23 = 5\'b10111;
parameter R23_dselect = 32\'b00000000100000000000000000000000;
parameter R24 = 5\'b11000;
parameter R24_dselect = 32\'b00000001000000000000000000000000;
parameter R25 = 5\'b11001;
parameter R25_dselect = 32\'b00000010000000000000000000000000;
parameter R26 = 5\'b11010;
parameter R26_dselect = 32\'b00000100000000000000000000000000;
parameter R27 = 5\'b11011;
parameter R27_dselect = 32\'b00001000000000000000000000000000;
parameter R28 = 5\'b11100;
parameter R28_dselect = 32\'b00010000000000000000000000000000;
parameter R29 = 5\'b11101;
parameter R29_dselect = 32\'b00100000000000000000000000000000;
parameter R30 = 5\'b11110;
parameter R30_dselect = 32\'b01000000000000000000000000000000;
parameter R31 = 5\'b11111;
parameter R31_dselect = 32\'b10000000000000000000000000000000;
//other parameterz to be used
parameter zeroSham = 6\'b000000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.dbus(dbus),.dselect(dselect));
initial begin
dontcare = 32\'hx;
//phase 1: testing basic op commands and instruction bus
//* ADDI, R20, R31, #AAA
iname[0] = "ADDI, R20, R31, #AAA";//testing addi, result in R20 = 00000AAA
iaddrbusout[0] = 32\'h00000000;
// opcode rm/ALUImm rn rd...
instrbusin[0]={ADDI, 12\'hAAA, R31, R20};
dselectout[0] = R20_dselect;
dbusout[0] = 32\'h00000AAA;
//* ADDI, R31, R23, #002
iname[1] = "ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 00000000
iaddrbusout[1] = 32\'h00000004;
// opcode rm/ALUImm rn rd...
instrbusin[1]={ADDI, 12\'h002, R23, R31};
dselectout[1] = R31_dselect;
dbusout[1] = dontcare;
//* ADDI, R0, R23, #002
iname[2] = "ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 00000002
iaddrbusout[2] = 32\'h00000008;
// opcode rm/ALUImm rn rd...
instrbusin[2]={ADDI, 12\'h002, R23, R0};
dselectout[2] = R0_dselect;
dbusout[2] = 32\'h00000002;
//* ORRI, R21, R24, #001
iname[3] = "ORRI, R21, R24, #001";//testing ori, result in R21 = 00000001
iaddrbusout[3] = 32\'h0000000C;
// opcode rm/ALUImm rn rd...
instrbusin[3]={ORRI, 12\'h001, R24, R21};
dselectout[3] = R21_dselect;
dbusout[3] = 32\'h00000001;
//* EORI, R22, R20, #000
iname[4] = "EORI, R22, R20, #000";//testing xori, result in R22 = 00000AAA
iaddrbusout[4] = 32\'h00000010;
// opcode rm/ALUImm rn rd...
instrbusin[4]={EORI, 12\'h000, R20, R22};
dselectout[4] = R22_dselect;
dbusout[4] = 32\'h00000AAA;
//* ANDI, R23, R0, #003
iname[5] = "ANDI, R23, R0, #003";//testing andi, result in R23 = 00000002
iaddrbusout[5] = 32\'h00000014;
// opcode rm/ALUImm rn rd...
instrbusin[5]={ANDI, 12\'h003, R0, R23};
dselectout[5] = R23_dselect;
dbusout[5] = 32\'h00000002;
//* SUBI, R24, R20, #00A
iname[6] = "SUBI, R24, R20, #00A";//testing subi, result in R24 = 00000AA0
iaddrbusout[6] = 32\'h00000018;
// opcode rm/ALUImm rn rd...
instrbusin[6]={SUBI, 12\'h00A, R20, R24};
dselectout[6] = R24_dselect;
dbusout[6] = 32\'h00000AA0;
// op, rd, rn, rm
//* ADD, R25, R20, R0
iname[7] = "ADD, R25, R20, R0";//testing add, result in R25 = 00000AAC
iaddrbusout[7] = 32\'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7]={ADD, R0, zeroSham, R20, R25};
dselectout[7] = R25_dselect;
dbusout[7] = 32\'h00000AAC;
// op, rd, rn, rm
//* AND, R26, R20, R22
iname[8] = "AND, R26, R20, R22";//testing and, result in R26 = 00000AAA
iaddrbusout[8] = 32\'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8]={AND, R22, zeroSham, R20, R26};
dselectout[8] = R26_dselect;
dbusout[8] = 32\'h00000AAA;
// op, rd, rn, rm
//* XOR, R27, R23, R21
iname[9] = "EOR, R27, R23, R21";//testing xor, result in R27 = 00000003
iaddrbusout[9] = 32\'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9]={EOR, R21, zeroSham, R23, R27};
dselectout[9] = R27_dselect;
dbusout[9] = 32\'h00000003;
// op, rd, rn, rm
//* OR, R28, R25, R23
iname[10] = "ORR, R28, R25, R23";//testing or, result in R28 = 00000AAE
iaddrbusout[10] = 32\'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10]={ORR, R23, zeroSham, R25, R28};
dselectout[10] = R28_dselect;
dbusout[10] = 32\'h00000AAE;
// op, rd, rn, rm
//* SUB, R29, R20, R22
iname[11] = "SUB, R29, R20, R22";//testing sub, result in R29 = 00000000
iaddrbusout[11] = 32\'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11]={SUB, R22, zeroSham, R20, R29};
dselectout[11] = R29_dselect;
dbusout[11] = 32\'h00000000;
// op, rd, rn, aluImm
//* ADDI, R30, R31, #000
iname[12] = "ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 00000000
iaddrbusout[12] = 32\'h00000030;
// opcode rm/ALUImm rn rd...
instrbusin[12]={ADDI, 12\'h000, R31, R30};
dselectout[12] = R30_dselect;
dbusout[12] = 32\'h00000000;
//phase 2: testing basic op codes with the n,z,c flags
// op, rd, rn, aluImm
//* SUBIS,R20, R0, #003
iname[13] = "SUBIS,R20, R0, #003";//testing subis, n flag, result in R20 = FFFFFFFF
iaddrbusout[13] = 32\'h00000034;
// opcode rm/ALUImm rn rd...
instrbusin[13] = {SUBIS, 12\'h003, R0, R20};
dselectout[13] = dontcare;
dbusout[13] = dontcare;
// op, rd, rn, rm
//* SUBS, R21, R25, R28
iname[14] = "SUBS, R21, R25, R28";//testing subs, n flag, result in R21 = FFFFFFFE
iaddrbusout[14] = 32\'h00000038;
// op, rm, shamt, rn, rd
instrbusin[14] = {SUBS, R28, zeroSham, R25, R21};
dselectout[14] = dontcare;
dbusout[14] = dontcare;
// op, rd, rn, aluImm
//* ADDIS,R22, R31, #000
iname[15] = "ADDIS,R22, R31, #000";//testing addis, z flag, result in R22 = 00000000
iaddrbusout[15] = 32\'h0000003C;
// opcode rm/ALUImm rn rd...
instrbusin[15] = {ADDIS, 12\'h000, R31, R22};
dselectout[15] = dontcare;
dbusout[15] = dontcare;
// op, rd, rn, rm
//* ADDS R23, R20, R23
iname[16] = "ADDS R23, R20, R23";//testing adds, c flag, result in R23 = 00000001
iaddrbusout[16] = 32\'h00000040;
// op, rm, shamt, rn, rd
instrbusin[16] = {ADDS, R23, zeroSham, R20, R23};
dselectout[16] = dontcare;
dbusout[16] = dontcare;
// op, rd, rn, aluImm
//* ANDIS,R24, R20, #002
iname[17] = "ANDIS,R24, R20, #002";//testing andis, reseting n,z flags to low, result in R24 = 00000002
iaddrbusout[17] = 32\'h00000044;
// opcode rm/ALUImm rn rd...
instrbusin[17] = {ANDIS, 12\'h002, R20, R24};
dselectout[17] = dontcare;
dbusout[17] = dontcare;
// op, rd, rn, rm
//* ANDS, R25, R21, R20
iname[18] = "ANDS, R25, R21, R20";//testing ands, n flag, result in R25 = FFFFFFFE
iaddrbusout[18] = 32\'h00000048;
// op, rm, shamt, rn, rd
instrbusin[18] = {ANDS, R20, zeroSham, R21, R25};
dselectout[18] = dontcare;
dbusout[18] = dontcare;
//* NOP
iaddrbusout[19] = 32\'h0000004C;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[19] = 32\'b00000000000000000000000000000000;
dselectout[19] = dontcare;
dbusout[19] = dontcare;
//* NOP
iaddrbusout[20] = 32\'h00000050;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[20] = 32\'b00000000000000000000000000000000;
dselectout[20] = dontcare;
dbusout[20] = dontcare;
//* NOP
iaddrbusout[21] = 32\'h00000054;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[21] = 32\'b00000000000000000000000000000000;
dselectout[21] = dontcare;
dbusout[21] = dontcare;
//* NOP
iaddrbusout[22] = 32\'h00000058;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[22] = 32\'b00000000000000000000000000000000;
dselectout[22] = dontcare;
dbusout[22] = dontcare;
//* NOP
iaddrbusout[23] = 32\'h0000005C;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[23] = 32\'b00000000000000000000000000000000;
dselectout[23] = dontcare;
dbusout[23] = dontcare;
//this number will be inacurate for a while(the number below)
// (no. instructions) + (no. loads) + 2*(no. stores) = 35 + 2 + 2*7 = 51
ntests = 24;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
//assign databus = clkd ? 32\'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
//databusk = 32\'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
$display ("Time=%t\
clk=%b", $realtime, clk);
for (k=0; k<= 26; k=k+1) begin
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set dbus and dselect data data for 4th previous instruction
if (k >=4)
//databusk = databusin[k-4];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b%b%b%b%b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check writeback data address from 4th previous instruction
if ( (k >= 4) && (dselectout[k-4] !== dontcare) ) begin
$display (" Testing writeback data address for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dselect = %b", dselect);
$display (" Correct dselect = %b", dselectout[k-4]);
if (dselectout[k-4] !== dselect) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check writeback data from 4th previous instruction
if ( (k >= 4) && (dbusout[k-4] !== dontcare) ) begin
$display (" Testing writeback data for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dbus = %b", dbus);
$display (" Correct dbus = %b", dbusout[k-4]);
if (dbusout[k-4] !== dbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("-----SIMULATION INCONCLUSIVE - CHECK YOUR NZVC BIT(S) IN THE SCOPE------");
end
endmodule
|
//phase 9: testing B.LT and B.GE branch
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:87];
wire [63:0] iaddrbus, daddrbus;
reg [63:0] iaddrbusout[0:87], daddrbusout[0:87];
wire [63:0] databus;
reg [63:0] databusk, databusin[0:87], databusout[0:87];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [24*8:1] iname[0:87];
integer error, k, ntests;
//all opcode parameters to be used
parameter ADD = 11\'b10001011000;
parameter ADDI = 10\'b1001000100;
parameter ADDIS = 10\'b1011000100;
parameter ADDS = 11\'b10101011000;
parameter AND = 11\'b10001010000;
parameter ANDI = 10\'b1001001000;
parameter ANDIS = 10\'b1111001000;
parameter ANDS = 11\'b11101010000;
parameter CBNZ = 8\'b10110101;
parameter CBZ = 8\'b10110100;
parameter EOR = 11\'b11001010000;
parameter EORI = 10\'b1101001000;
parameter LDUR = 11\'b11111000010;
parameter LSL = 11\'b11010011011;
parameter LSR = 11\'b11010011010;
parameter MOVZ = 9\'b110100101;
parameter ORR = 11\'b10101010000;
parameter ORRI = 10\'b1011001000;
parameter STUR = 11\'b11111000000;
parameter SUB = 11\'b11001011000;
parameter SUBI = 10\'b1101000100;
parameter SUBIS = 10\'b1111000100;
parameter SUBS = 11\'b11101011000;
parameter B = 6\'b000101;
parameter B_EQ = 8\'b01010101;
parameter B_NE = 8\'b01010110;
parameter B_LT = 8\'b01010111;
parameter B_GE = 8\'b01011000;
//register parameters
parameter R0 = 5\'b00000;
parameter R15 = 5\'b01111;
parameter R16 = 5\'b10000;
parameter R17 = 5\'b10001;
parameter R18 = 5\'b10010;
parameter R19 = 5\'b10011;
parameter R20 = 5\'b10100;
parameter R21 = 5\'b10101;
parameter R22 = 5\'b10110;
parameter R23 = 5\'b10111;
parameter R24 = 5\'b11000;
parameter R25 = 5\'b11001;
parameter R26 = 5\'b11010;
parameter R27 = 5\'b11011;
parameter R28 = 5\'b11100;
parameter R29 = 5\'b11101;
parameter R30 = 5\'b11110;
parameter R31 = 5\'b11111;
//other parameterz to be used
parameter zeroSham = 6\'b000000;
parameter RX = 5\'b11111;
parameter oneShamt = 6\'b000001;
parameter twoShamt = 6\'b000010;
parameter threeShamt = 6\'b000011;
parameter eightShamt = 6\'b001000;
parameter move_0 = 2\'b00;
parameter move_1 = 2\'b01;
parameter move_2 = 2\'b10;
parameter move_3 = 2\'b11;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
dontcare = 64\'hx;
//phase 1: testing basic op commands
// op, rd, rn, rm
iname[0] ="ADDI, R20, R31, #AAA";//testing addi, result in R20 = 0000000000000AAA
iaddrbusout[0] = 64\'h00000000;
// opcode rm/ALUImm rn rd
instrbusin[0] ={ADDI, 12\'hAAA, R31, R20};
daddrbusout[0] = dontcare;
databusin[0] = 64\'bz;
databusout[0] = dontcare;
// op, rd, rn, rm
iname[1] ="ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 0000000000000000
iaddrbusout[1] = 64\'h00000004;
// opcode rm/ALUImm rn rd
instrbusin[1] ={ADDI, 12\'h002, R23, R31};
daddrbusout[1] = dontcare;
databusin[1] = 64\'bz;
databusout[1] = dontcare;
// op, rd, rn, rm
iname[2] ="ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 0000000000000002
iaddrbusout[2] = 64\'h00000008;
// opcode rm/ALUImm rn rd
instrbusin[2] ={ADDI, 12\'h002, R23, R0};
daddrbusout[2] = dontcare;
databusin[2] = 64\'bz;
databusout[2] = dontcare;
// op, rd, rn, rm
iname[3] ="ORRI, R21, R24, #001";//testing ori, result in R21 = 0000000000000001
iaddrbusout[3] = 64\'h0000000C;
// opcode rm/ALUImm rn rd
instrbusin[3] ={ORRI, 12\'h001, R24, R21};
daddrbusout[3] = dontcare;
databusin[3] = 64\'bz;
databusout[3] = dontcare;
// op, rd, rn, rm
iname[4] ="EORI, R22, R20, #000";//testing xori, result in R22 = 0000000000000AAA
iaddrbusout[4] = 64\'h00000010;
// opcode rm/ALUImm rn rd
instrbusin[4] ={EORI, 12\'h000, R20, R22};
daddrbusout[4] = dontcare;
databusin[4] = 64\'bz;
databusout[4] = dontcare;
// op, rd, rn, rm
iname[5] ="ANDI, R23, R0, #003";//testing andi, result in R23 = 0000000000000002
iaddrbusout[5] = 64\'h00000014;
// opcode rm/ALUImm rn rd
instrbusin[5] ={ANDI, 12\'h003, R0, R23};
daddrbusout[5] = dontcare;
databusin[5] = 64\'bz;
databusout[5] = dontcare;
// op, rd, rn, rm
iname[6] ="SUBI, R24, R20, #00A";//testing subi, result in R24 = 0000000000000AA0
iaddrbusout[6] = 64\'h00000018;
// opcode rm/ALUImm rn rd
instrbusin[6] ={SUBI, 12\'h00A, R20, R24};
daddrbusout[6] = dontcare;
databusin[6] = 64\'bz;
databusout[6] = dontcare;
// op, rd, rn, rm
iname[7] ="ADD, R25, R20, R0";//testing add, result in R25 = 0000000000000AAC
iaddrbusout[7] = 64\'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7] ={ADD, R0, zeroSham, R20, R25};
daddrbusout[7] = dontcare;
databusin[7] = 64\'bz;
databusout[7] = dontcare;
// op, rd, rn, rm
iname[8] ="AND, R26, R20, R22";//testing and, result in R26 = 0000000000000AAA
iaddrbusout[8] = 64\'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8] ={AND, R22, zeroSham, R20, R26};
daddrbusout[8] = dontcare;
databusin[8] = 64\'bz;
databusout[8] = dontcare;
// op, rd, rn, rm
iname[9] ="EOR, R27, R23, R21";//testing xor, result in R27 = 0000000000000003
iaddrbusout[9] = 64\'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9] ={EOR, R21, zeroSham, R23, R27};
daddrbusout[9] = dontcare;
databusin[9] = 64\'bz;
databusout[9] = dontcare;
// op, rd, rn, rm
iname[10] ="ORR, R28, R25, R23";//testing or, result in R28 = 0000000000000AAE
iaddrbusout[10] = 64\'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10] ={ORR, R23, zeroSham, R25, R28};
daddrbusout[10] = dontcare;
databusin[10] = 64\'bz;
databusout[10] = dontcare;
// op, rd, rn, rm
iname[11] ="SUB, R29, R20, R22";//testing sub, result in R29 = 0000000000000000
iaddrbusout[11] = 64\'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11] ={SUB, R22, zeroSham, R20, R29};
daddrbusout[11] = dontcare;
databusin[11] = 64\'bz;
databusout[11] = dontcare;
// op, rd, rn, aluImm
iname[12] ="ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 0000000000000000
iaddrbusout[12] = 64\'h00000030;
// opcode rm/ALUImm rn rd
instrbusin[12] ={ADDI, 12\'h000, R31, R30};
daddrbusout[12] = dontcare;
databusin[12] = 64\'bz;
databusout[12] = dontcare;
//phase 2: testing basic op codes with the set flags
// op, rd, rn, aluImm
iname[13] ="SUBIS,R20, R0, #003";//testing subis, n flag, result in R20 = FFFFFFFFFFFFFFFF
iaddrbusout[13] = 64\'h00000034;
// opcode rm/ALUImm rn rd
instrbusin[13] ={SUBIS, 12\'h003, R0, R20};
daddrbusout[13] = dontcare;
databusin[13] = 64\'bz;
databusout[13] = dontcare;
// op, rd, rn, rm
iname[14] ="SUBS, R21, R25, R28";//testing subs, n flag, result in R21 = FFFFFFFFFFFFFFFE
iaddrbusout[14] = 64\'h00000038;
// op, rm, shamt, rn, rd
instrbusin[14] ={SUBS,R28,zeroSham, R25, R21};
daddrbusout[14] = dontcare;
databusin[14] = 64\'bz;
databusout[14] = dontcare;
// op, rd, rn, aluImm
iname[15] ="ADDIS,R22, R31, #000";//testing addis, z flag, result in R22 = 0000000000000000
iaddrbusout[15] = 64\'h0000003C;
// opcode rm/ALUImm rn rd
instrbusin[15] ={ADDIS, 12\'h000, R31, R22};
daddrbusout[15] = dontcare;
databusin[15] = 64\'bz;
databusout[15] = dontcare;
// op, rd, rn, rm
iname[16] ="ADDS R23, R20, R23";//testing adds, c flag, result in R23 = 0000000000000001
iaddrbusout[16] = 64\'h00000040;
// op, rm, shamt, rn, rd
instrbusin[16] ={ADDS,R23,zeroSham, R20, R23};
daddrbusout[16] = dontcare;
databusin[16] = 64\'bz;
databusout[16] = dontcare;
// op, rd, rn, aluImm
iname[17] ="ANDIS,R24, R20, #002";//testing andis, reseting n,z flags to low, result in R24 = 0000000000000002
iaddrbusout[17] = 64\'h00000044;
// opcode rm/ALUImm rn rd
instrbusin[17] ={ANDIS, 12\'h002, R20, R24};
daddrbusout[17] = dontcare;
databusin[17] = 64\'bz;
databusout[17] = dontcare;
// op, rd, rn, rm
iname[18] ="ANDS, R25, R21, R20";//testing ands, n flag, result in R25 = FFFFFFFFFFFFFFFE
iaddrbusout[18] = 64\'h00000048;
// op, rm, shamt, rn, rd
instrbusin[18] ={ANDS, R20, zeroSham, R21, R25};
daddrbusout[18] = dontcare;
databusin[18] = 64\'bz;
databusout[18] = dontcare;
//phase 3: testing LSL, LSR
//setting up the register R20 for a test of the LSL
// op, rd, rn, rm
iname[19] ="ADDI, R20, R31, #007";//setting up for left shift, result in R20 = 0000000000000007
iaddrbusout[19] = 64\'h0000004C;
// opcode rm/ALUImm rn rd
instrbusin[19] ={ADDI, 12\'h007, R31, R20};
daddrbusout[19] = dontcare;
databusin[19] = 64\'bz;
databusout[19] = dontcare;
// op, rd, rn, rm
iname[20] ="ADDI, R21, R31, #700";//setting up for right shift, n flag, result in R21 = 0000000000000700
iaddrbusout[20] = 64\'h00000050;
// opcode rm/ALUImm rn rd
instrbusin[20] ={ADDI, 12\'h700, R31, R21};
daddrbusout[20] = dontcare;
databusin[20] = 64\'bz;
databusout[20] = dontcare;
// op, rd, rn, rm
iname[21] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[21] = 64\'h00000054;
// op, rm, shamt, rn, rd
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
daddrbusout[21] = dontcare;
databusin[21] = 64\'bz;
databusout[21] = dontcare;
// op, rd, rn, rm
iname[22] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[22] = 64\'h00000058;
// op, rm, shamt, rn, rd
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
daddrbusout[22] = dontcare;
databusin[22] = 64\'bz;
databusout[22] = dontcare;
// op, rd, rn, rm
iname[23] ="LSL, R20, R20, 2";//testing left shift, result in R20 = 0000000000000700
iaddrbusout[23] = 64\'h0000005C;
// op, rm, shamt, rn, rd
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
daddrbusout[23] = dontcare;
databusin[23] = 64\'bz;
databusout[23] = dontcare;
// op, rd, rn, rm
iname[24] ="LSR, R21, R21, 2";//testing right shift, result in R21 = 0000000000000007
iaddrbusout[24] = 64\'h00000060;
// op, rm, shamt, rn, rd
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
daddrbusout[24] = dontcare;
databusin[24] = 64\'bz;
databusout[24] = dontcare;
//phase 4: testing load and store
// op, rt, rn, DT_adr
iname[25] ="LDUR, R22, R31, #1";//testing load, result in R22 = 42069 (from memory,databusin) [yes, really]
iaddrbusout[25] = 64\'h00000064;
// op, DT_ADDR, ?, rn, rt
instrbusin[25] ={LDUR, 9\'b000000001, 2\'b00, R31, R22};
daddrbusout[25] = 64\'h0000000000000001;//used for LDUR
databusin[25] = 64\'h0000000000042069;//used for LDUR
databusout[25] = dontcare;
// op, rn, DT_adr, rt
iname[26] ="STUR, R23, #068, R24";//testing story, result for databusout in R24 = 0000000000000002 (to memory)
//address is calculated from imm or 68, and R23, which is currently 1
iaddrbusout[26] = 64\'h00000068;
// op, DT_ADDR, ?, rn, rt
instrbusin[26] ={STUR, 9\'b001101000, 2\'b00, R23, R24};
daddrbusout[26] = 64\'h0000000000000069;//used for STUR
databusin[26] = 64\'bz;
databusout[26] = 64\'h0000000000000002;//used for STUR
// op, rd, rn, rm
iname[27] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[27] = 64\'h0000006C;
// op, rm, shamt, rn, rd
instrbusin[27] ={AND, R31, zeroSham, R31, R19};
daddrbusout[27] = dontcare;
databusin[27] = 64\'bz;
databusout[27] = dontcare;
// op, rd, rn, rm
iname[28] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[28] = 64\'h00000070;
// op, rm, shamt, rn, rd
instrbusin[28] ={AND, R31, zeroSham, R31, R19};
daddrbusout[28] = dontcare;
databusin[28] = 64\'bz;
databusout[28] = dontcare;
// op, rd, rn, rm
iname[29] ="AND, R17, R31, R31";//delay, result in R17 = 0000000000000000
iaddrbusout[29] = 64\'h00000074;
// op, rm, shamt, rn, rd
instrbusin[29] ={AND, R31, zeroSham, R31, R19};
daddrbusout[29] = dontcare;
databusin[29] = 64\'bz;
databusout[29] = dontcare;
//phase 5: testing B branch
// op, BR_address
iname[30] ="B, #EA";//testing branch, calculated branch address should be
// (64\'h0000000000000078 + 64\'h000000000000003A8 = 64\'h0000000000000420)
iaddrbusout[30] = 64\'h00000078;
// op, BR_address
instrbusin[30] ={B, 26\'b00000000000000000011101010};
daddrbusout[30] = dontcare;
databusin[30] = 64\'bz;
databusout[30] = dontcare;
// op, rd, rn, rm
iname[31] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[31] = 64\'h0000007C;
// op, rm, shamt, rn, rd
instrbusin[31] ={AND, R31, zeroSham, R31, R19};
daddrbusout[31] = dontcare;
databusin[31] = 64\'bz;
databusout[31] = dontcare;
// op, rd, rn, rm
iname[32] ="ADD, R20, R21, R20";//testing branch address result in R20 = 0000000000000707
iaddrbusout[32] = 64\'h00000420;
// op, rm, shamt, rn, rd
instrbusin[32] ={ADD, R20, zeroSham, R21, R20};
daddrbusout[32] = dontcare;
databusin[32] = 64\'bz;
databusout[32] = dontcare;
//phase 6: testing B.EQ and B.NE branch
// op, rd, rn, rm
iname[33] ="ADDI, R21, R31, #AAA";//testing addi, result in R21 = 0000000000000AAA
iaddrbusout[33] = 64\'h00000424;
// opcode rm/ALUImm rn rd
instrbusin[33] ={ADDI, 12\'hAAA, R31, R21};
daddrbusout[33] = dontcare;
databusin[33] = 64\'bz;
databusout[33] = dontcare;
// op, rd, rn, rm
iname[34] ="ADDI, R22, R31, #AAA";//testing addi, result in R22 = 0000000000000AAA
iaddrbusout[34] = 64\'h00000428;
// opcode rm/ALUImm rn rd
instrbusin[34] ={ADDI, 12\'hAAA, R31, R22};
daddrbusout[34] = dontcare;
databusin[34] = 64\'bz;
databusout[34] = dontcare;
//ADDIS for FAKE BRANCH
// op, rd, rn, aluImm
iname[35] ="ADDIS,R31, R31, #420";//testing fake branch, this should NOT set the Z high
iaddrbusout[35] = 64\'h0000042C;
// opcode rm/ALUImm rn rd
instrbusin[35] ={ADDIS, 12\'h420, R31, R31};
daddrbusout[35] = dontcare;
databusin[35] = 64\'bz;
databusout[35] = dontcare;
//FAKE BRANCH
// op, COND_addr, rt
iname[36] ="B_EQ, #69420, RX";//testing to NOT take the branch, Z should be LOW
iaddrbusout[36] = 64\'h00000430;
// op, COND_addr, rt
instrbusin[36] ={B_EQ, 19\'b1101001010000100000, RX};
daddrbusout[36] = dontcare;
databusin[36] = 64\'bz;
databusout[36] = dontcare;
iname[37] = "NOP";//nada
iaddrbusout[37] = 64\'h00000434;
instrbusin[37] = 64\'b0;
daddrbusout[37] = dontcare;
databusin[37] = 64\'bz;
databusout[37] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[38] ="SUBS, R31, R21, R22";//set z flag for BEQ,
iaddrbusout[38] = 64\'h00000438;
// op, rm, shamt, rn, rd
instrbusin[38] ={SUBS, R22, zeroSham, R21, R31};
daddrbusout[38] = dontcare;
databusin[38] = 64\'bz;
databusout[38] = dontcare;
//real branch for B.EQ (I have the best branches)
// op, COND_addr, rt
iname[39] ="B_EQ, #69, RX";//take the branch to instruction count ?
iaddrbusout[39] = 64\'h0000043C;
// op, COND_addr, rt
instrbusin[39] ={B_EQ, 19\'b0000000000001101001, RX};
//19\'b
daddrbusout[39] = dontcare;
databusin[39] = 64\'bz;
databusout[39] = dontcare;
iname[40] = "NOP";//nada
iaddrbusout[40] = 64\'h00000440;
instrbusin[40] = 64\'b0;
daddrbusout[40] = dontcare;
databusin[40] = 64\'bz;
databusout[40] = dontcare;
iname[41] = "NOP";//nada
iaddrbusout[41] = 64\'h000005E0;
instrbusin[41] = 64\'b0;
daddrbusout[41] = dontcare;
databusin[41] = 64\'bz;
databusout[41] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[42] ="SUBS, R31, R21, R20";//set z flag of NOT for BNE
iaddrbusout[42] = 64\'h000005E4;
// op, rm, shamt, rn, rd
instrbusin[42] ={SUBS, R20, zeroSham, R21, R31};
daddrbusout[42] = dontcare;
databusin[42] = 64\'bz;
databusout[42] = dontcare;
//test B.NE
// op, COND_addr, rt
iname[43] ="B_NE, #96, RX";//take the branch to instruction count 840
iaddrbusout[43] = 64\'h000005E8;
// op, COND_addr, rt
instrbusin[43] ={B_NE, 19\'b0000000000010010110, RX};
daddrbusout[43] = dontcare;
databusin[43] = 64\'bz;
databusout[43] = dontcare;
iname[44] = "NOP";//nada
iaddrbusout[44] = 64\'h000005EC;
instrbusin[44] = 64\'b0;
daddrbusout[44] = dontcare;
databusin[44] = 64\'bz;
databusout[44] = dontcare;
iname[45] = "NOP";//nada
iaddrbusout[45] = 64\'h00000840;
instrbusin[45] = 64\'b0;
daddrbusout[45] = dontcare;
databusin[45] = 64\'bz;
databusout[45] = dontcare;
//phase 7: testing CBNZ and CBZ branch
//DONT take the CBZ
// op, COND_addr, rt
iname[46] ="CBZ, #F, R22";//take the branch to instruction count
iaddrbusout[46] = 64\'h00000844;
// op, COND_addr, rt
instrbusin[46] ={CBZ, 19\'b0000000000000001111, R22};
daddrbusout[46] = dontcare;
databusin[46] = 64\'bz;
databusout[46] = dontcare;
iname[47] = "NOP";//nada
iaddrbusout[47] = 64\'h00000848;
instrbusin[47] = 64\'b0;
daddrbusout[47] = dontcare;
databusin[47] = 64\'bz;
databusout[47] = dontcare;
iname[48] = "NOP";//nada
iaddrbusout[48] = 64\'h0000084C;
instrbusin[48] = 64\'b0;
daddrbusout[48] = dontcare;
databusin[48] = 64\'bz;
databusout[48] = dontcare;
//TAKE the CBZ
// op, COND_addr, rt
iname[49] ="CBZ, #21, R19";//take the branch to instruction count
iaddrbusout[49] = 64\'h00000850;
// op, COND_addr, rt
instrbusin[49] ={CBZ, 19\'b0000000000000100001, R19};
daddrbusout[49] = dontcare;
databusin[49] = 64\'bz;
databusout[49] = dontcare;
iname[50] = "NOP";//nada
iaddrbusout[50] = 64\'h00000854;
instrbusin[50] = 64\'b0;
daddrbusout[50] = dontcare;
databusin[50] = 64\'bz;
databusout[50] = dontcare;
iname[51] = "NOP";//nada
iaddrbusout[51] = 64\'h000008D4;
instrbusin[51] = 64\'b0;
daddrbusout[51] = dontcare;
databusin[51] = 64\'bz;
databusout[51] = dontcare;
//DONT take the CBNZ
// op, COND_addr, rt
iname[52] ="CBNZ, #FF, R31";//take the branch to instruction count
iaddrbusout[52] = 64\'h000008D8;
// op, COND_addr, rt
instrbusin[52] ={CBNZ, 19\'b0000000000011111111, R31};
daddrbusout[52] = dontcare;
databusin[52] = 64\'bz;
databusout[52] = dontcare;
iname[53] = "NOP";//nada
iaddrbusout[53] = 64\'h000008DC;
instrbusin[53] = 64\'b0;
daddrbusout[53] = dontcare;
databusin[53] = 64\'bz;
databusout[53] = dontcare;
iname[54] = "NOP";//nada
iaddrbusout[54] = 64\'h000008E0;
instrbusin[54] = 64\'b0;
daddrbusout[54] = dontcare;
databusin[54] = 64\'bz;
databusout[54] = dontcare;
//TAKE the CBNZ
// op, COND_addr, rt
iname[55] ="CBNZ, #22, R20";//take the branch to instruction count
iaddrbusout[55] = 64\'h000008E4;
// op, COND_addr, rt
instrbusin[55] ={CBNZ, 19\'b0000000000000100010, R20};
daddrbusout[55] = dontcare;
databusin[55] = 64\'bz;
databusout[55] = dontcare;
iname[56] = "NOP";//nada
iaddrbusout[56] = 64\'h000008E8;
instrbusin[56] = 64\'b0;
daddrbusout[56] = dontcare;
databusin[56] = 64\'bz;
databusout[56] = dontcare;
iname[57] = "NOP";//nada
iaddrbusout[57] = 64\'h0000096C;
instrbusin[57] = 64\'b0;
daddrbusout[57] = dontcare;
databusin[57] = 64\'bz;
databusout[57] = dontcare;
//phase 8: testing MOVEZ and overflow bit
//4 instructions to set registers to 0
// op, rd, rn, rm
iname[58] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[58] = 64\'h00000970;
// op, rm, shamt, rn, rd
instrbusin[58] ={AND, R31, zeroSham, R31, R19};
daddrbusout[58] = dontcare;
databusin[58] = 64\'bz;
databusout[58] = dontcare;
// op, rd, rn, rm
iname[59] ="AND, R20, R31, R31";//delay, result in R20 = 0000000000000000
iaddrbusout[59] = 64\'h00000974;
// op, rm, shamt, rn, rd
instrbusin[59] ={AND, R31, zeroSham, R31, R20};
daddrbusout[59] = dontcare;
databusin[59] = 64\'bz;
databusout[59] = dontcare;
// op, rd, rn, rm
iname[60] ="AND, R21, R31, R31";//delay, result in R21 = 0000000000000000
iaddrbusout[60] = 64\'h00000978;
// op, rm, shamt, rn, rd
instrbusin[60] ={AND, R31, zeroSham, R31, R21};
daddrbusout[60] = dontcare;
databusin[60] = 64\'bz;
databusout[60] = dontcare;
// op, rd, rn, rm
iname[61] ="AND, R22, R31, R31";//delay, result in R22 = 0000000000000000
iaddrbusout[61] = 64\'h0000097C;
// op, rm, shamt, rn, rd
instrbusin[61] ={AND, R31, zeroSham, R31, R22};
daddrbusout[61] = dontcare;
databusin[61] = 64\'bz;
databusout[61] = dontcare;
//4 MOVZ commands
//move 0 amt
// op, move_amt, MOV_imm, rd
iname[62] ="MOVZ, move_0, #FFFF, R19";//testing move, result in R19 = 000000000000FFFF
iaddrbusout[62] = 64\'h00000980;
// op, move_amt, MOV_imm, rd
instrbusin[62] ={MOVZ, move_0, 16\'hFFFF, R19};
daddrbusout[62] = dontcare;
databusin[62] = 64\'bz;
databusout[62] = dontcare;
//move 1 amt
// op, move_amt, MOV_imm, rd
iname[63] ="MOVZ, move_1, #FFFF, R20";//testing move, result in R20 = 00000000FFFF0000
iaddrbusout[63] = 64\'h00000984;
// op, move_amt, MOV_imm, rd
instrbusin[63] ={MOVZ, move_1, 16\'hFFFF, R20};
daddrbusout[63] = dontcare;
databusin[63] = 64\'bz;
databusout[63] = dontcare;
//move 2 amt
// op, move_amt, MOV_imm, rd
iname[64] ="MOVZ, move_2, #FFFF, R21";//testing move, result in R21 = 0000FFFF00000000
iaddrbusout[64] = 64\'h00000988;
// op, move_amt, MOV_imm, rd
instrbusin[64] ={MOVZ, move_2, 16\'hFFFF, R21};
daddrbusout[64] = dontcare;
databusin[64] = 64\'bz;
databusout[64] = dontcare;
//move 3 amt
// op, move_amt, MOV_imm, rd
iname[65] ="MOVZ, move_3, #7FFF, R22";//testing move, result in R22 = 7FFF000000000000
iaddrbusout[65] = 64\'h0000098C;
// op, move_amt, MOV_imm, rd
instrbusin[65] ={MOVZ, move_3, 16\'h7FFF, R22};
daddrbusout[65] = dontcare;
databusin[65] = 64\'bz;
databusout[65] = dontcare;
//have or for move 0 and move 1
// op, rd, rn, rm
iname[66] ="ORR, R23, R19, R20";//testing xor, result in R23 = 00000000FFFFFFFF
iaddrbusout[66] = 64\'h00000990;
// op, rm, shamt, rn, rd
instrbusin[66] ={ORR, R20, zeroSham, R19, R23};
daddrbusout[66] = dontcare;
databusin[66] = 64\'bz;
databusout[66] = dontcare;
//delay
iname[67] = "NOP";//nada
iaddrbusout[67] = 64\'h00000994;
instrbusin[67] = 64\'b0;
daddrbusout[67] = dontcare;
databusin[67] = 64\'bz;
databusout[67] = dontcare;
//have or for move 2 and move 3
// op, rd, rn, rm
iname[68] ="ORR, R24, R21, R22";//testing xor, result in R27 = 7FFFFFFF00000000
iaddrbusout[68] = 64\'h00000998;
// op, rm, shamt, rn, rd
instrbusin[68] ={ORR, R22, zeroSham, R21, R24};
daddrbusout[68] = dontcare;
databusin[68] = 64\'bz;
databusout[68] = dontcare;
//delay
iname[69] = "NOP";//nada
iaddrbusout[69] = 64\'h0000099C;
instrbusin[69] = 64\'b0;
daddrbusout[69] = dontcare;
databusin[69] = 64\'bz;
databusout[69] = dontcare;
//delay
iname[70] = "NOP";//nada
iaddrbusout[70] = 64\'h000009A0;
instrbusin[70] = 64\'b0;
daddrbusout[70] = dontcare;
databusin[70] = 64\'bz;
databusout[70] = dontcare;
//have or for move(0|1) and move(2|3)
// op, rd, rn, rm
iname[71] ="ORR, R25, R23, R24";//testing xor, result in R25 = 7FFFFFFFFFFFFFFF
iaddrbusout[71] = 64\'h000009A4;
// op, rm, shamt, rn, rd
instrbusin[71] ={ORR, R24, zeroSham, R23, R25};
daddrbusout[71] = dontcare;
databusin[71] = 64\'bz;
databusout[71] = dontcare;
//dealy
iname[72] = "NOP";//nada
iaddrbusout[72] = 64\'h000009A8;
instrbusin[72] = 64\'b0;
daddrbusout[72] = dontcare;
databusin[72] = 64\'bz;
databusout[72] = dontcare;
//delay
iname[73] = "NOP";//nada
iaddrbusout[73] = 64\'h000009AC;
instrbusin[73] = 64\'b0;
daddrbusout[73] = dontcare;
databusin[73] = 64\'bz;
databusout[73] = dontcare;
//addis command to trigger the V bit
// op, rd, rn, aluImm
iname[74] ="ADDIS,R26, R25, #001";//testing xor and V bit and N bit, result in R26 = 8000000000000000
iaddrbusout[74] = 64\'h000009B0;
// opcode rm/ALUImm rn rd
instrbusin[74] ={ADDIS, 12\'h001, R25, R26};
daddrbusout[74] = dontcare;
databusin[74] = 64\'bz;
databusout[74] = dontcare;
iname[75] = "NOP";//nada
iaddrbusout[75] = 64\'h000009B4;
instrbusin[75] = 64\'b0;
daddrbusout[75] = dontcare;
databusin[75] = 64\'bz;
databusout[75] = dontcare;
iname[76] = "NOP";//nada
iaddrbusout[76] = 64\'h000009B8;
instrbusin[76] = 64\'b0;
daddrbusout[76] = dontcare;
databusin[76] = 64\'bz;
databusout[76] = dontcare;
//phase 9: testing B.LT and B.GE branch
//7FFF+1 = N and V, 8000-1 = V
//use SUBIS for the branch condition test (B.LT test)
// op, rd, rn, aluImm
iname[77] ="SUBIS,R26, R26, #001";//result in R26 = 7FFFFFFFFFFFFFFF
iaddrbusout[77] = 64\'h000009BC;
// opcode rm/ALUImm rn rd
instrbusin[77] ={SUBIS, 12\'h001, R26, R26};
daddrbusout[77] = dontcare;
databusin[77] = 64\'bz;
databusout[77] = dontcare;
//TAKE branch
// op, COND_addr, rt
iname[78] ="B_LT, #42, RX";//new branch address is AC8
iaddrbusout[78] = 64\'h000009C0;
// op, COND_addr, rt
instrbusin[78] ={B_LT, 19\'b0000000000001000010, RX};
daddrbusout[78] = dontcare;
databusin[78] = 64\'bz;
databusout[78] = dontcare;
//delay
iname[79] = "NOP";//nada
iaddrbusout[79] = 64\'h000009C4;
instrbusin[79] = 64\'b0;
daddrbusout[79] = dontcare;
databusin[79] = 64\'bz;
databusout[79] = dontcare;
//delay
iname[80] = "NOP";//nada
iaddrbusout[80] = 64\'h00000AC8;
instrbusin[80] = 64\'b0;
daddrbusout[80] = dontcare;
databusin[80] = 64\'bz;
databusout[80] = dontcare;
//use ADDIS for the branch condition test B.GE test
// op, rd, rn, aluImm
iname[81] ="ADDIS,R26, R26, #001";//result in R26 = 8000000000000000
iaddrbusout[81] = 64\'h00000ACC;
// opcode rm/ALUImm rn rd
instrbusin[81] ={ADDIS, 12\'h001, R26, R26};
daddrbusout[81] = dontcare;
databusin[81] = 64\'bz;
databusout[81] = dontcare;
//TAKE branch
// op, COND_addr, rt
iname[82] ="B_GE, #24, RX";//new branch address is B60
iaddrbusout[82] = 64\'h00000AD0;
// op, COND_addr, rt
instrbusin[82] ={B_GE, 19\'b0000000000000100100, RX};
daddrbusout[82] = dontcare;
databusin[82] = 64\'bz;
databusout[82] = dontcare;
//delay
iname[83] = "NOP";//nada
iaddrbusout[83] = 64\'h00000AD4;
instrbusin[83] = 64\'b0;
daddrbusout[83] = dontcare;
databusin[83] = 64\'bz;
databusout[83] = dontcare;
//delay
iname[84] = "NOP";//nada
iaddrbusout[84] = 64\'h00000B60;
instrbusin[84] = 64\'b0;
daddrbusout[84] = dontcare;
databusin[84] = 64\'bz;
databusout[84] = dontcare;
//finishing up
iname[85] = "NOP";//nada
iaddrbusout[85] = 64\'h00000B64;
instrbusin[85] = 64\'b0;
daddrbusout[85] = dontcare;
databusin[85] = 64\'bz;
databusout[85] = dontcare;
iname[86] = "NOP";//nada
iaddrbusout[86] = 64\'h00000B68;
instrbusin[86] = 64\'b0;
daddrbusout[86] = dontcare;
databusin[86] = 64\'bz;
databusout[86] = dontcare;
iname[87] = "NOP";//nada
iaddrbusout[87] = 64\'h00000B6C;
instrbusin[87] = 64\'b0;
daddrbusout[87] = dontcare;
databusin[87] = 64\'bz;
databusout[87] = dontcare;
//also remember to set k down below to ntests - 1
ntests = 88;//?
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
assign databus = clkd ? 64\'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
databusk = 64\'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
$display ("Time=%t\
clk=%b", $realtime, clk);
for (k=0; k<= 87; k=k+1) begin
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set load data for 3rd previous instruction
if (k >=3)
databusk = databusin[k-3];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check data address from 3rd previous instruction
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check store data from 3rd previous instruction
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
/************************
* Willard Wider
* 6-14-17
* ELEC3725
* regalu.v
* building a 32 bit ALU
************************/
//The regfile and ALUpipe wired together
module regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);
input [31:0] Aselect;
input [31:0] Bselect;
input [31:0] Dselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
output [31:0] dbus;
input [2:0] S;
input Cin;
regfile reggie(
.Aselect(Aselect),
.Bselect(Bselect),
.Dselect(Dselect),
.dbus(dbus),
.bbus(bbus),
.abus(abus),
.clk(clk)
);
alupipe alup(
.S(S),
.Cin(Cin),
.clk(clk),
.abus(abus),
.bbus(bbus),
.dbus(dbus)
);
endmodule
//The top module for Assignment 3, the whole register unit
module regfile(
input [31:0] Aselect,//select the register index to read from to store into abus
input [31:0] Bselect,//select the register index to read from to store into bbus
input [31:0] Dselect,//select the register to write to from dbus
input [31:0] dbus,//data in
output [31:0] abus,//data out
output [31:0] bbus,//data out
input clk
);
/*
Register index 0 is always supposed to be a 0 output, and only one select for
A, B, and D will be high at a time. Therefore, if the A or Bselect at index 0
is high, it means we can write all 0's to the corresponding bus. Otherwize
write z (don't touch it)
*/
assign abus = Aselect[0] ? 32'b0 : 32'bz;
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
//31 wide register (don't need one for index 0
DNegflipFlop myFlips[30:0](
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule
//module definiton for each register in the register file
module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [31:0] dbus;
input Dselect;//the select write bit for dbus
input Bselect;//the select read bit for bbus
input Aselect;//the select read bit for abus
input clk;
output [31:0] abus;
output [31:0] bbus;
wire wireclk;//wire for connectitng the clock to the dselect input
reg [31:0] data;
assign wireclk = clk & Dselect;//wireclk will only be high if both are high
always @(negedge wireclk) begin
data = dbus;
end
//only write to the output bus of it's select is high, otherwise write z
//(don't actually write anything)
assign abus = Aselect ? data : 32'bz;
assign bbus = Bselect ? data : 32'bz;
endmodule
|
/************************
* Willard Wider
* 08-07-17
* ELEC3725
* ARMS.v
* building a 64 bit CPU
************************/
//ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
module ARMS(ibus,clk,daddrbus,databus,reset,iaddrbus);
//just a clock
input clk;
//reset to clear the counter
input reset;
//instruction bus
output [63:0] iaddrbus;//from PC, to SIM_OUT
wire [63:0] iaddrbusWire1;//from mux, to PC
wire [63:0] iaddrbusWire2;//from PC, to mux4/iaddrbusWire4
wire [63:0] iaddrbusWire4;//from PC, to IF_ID
//SLT SLE control bits
//00 = nothing, 01 = SLT, 10 = SLE
reg [1:0] setControlBits;
wire [1:0] setControlBitsWire1;
wire [1:0] setControlBitsWire2;
//for SLT/SLE operations
//LEG_UPDATE: rs->rn, rt->rm
wire ZBit;//high when rn(a) - rm(b) = 0, 1 otherwise
wire [63:0] potentialSLEBit;//the value to set to dbus if it is a SLE operation
wire [63:0] potentialSLTBit;
wire [63:0] actualSLBit;
//the cout for the alu
wire ALUCoutWire;
//LEG_UPDATE: add the overflow counter from the ALU
wire overflowWire;
//LEG_UPDATE: 7 ways to branch, to update the control bit
//000 = noting, 001 = B, 010 = B.EQ
//011 = B.NE, 100 = B.LT, 101 = B.GE
//110 = CBNZ, 111 = CBZ
reg [2:0] branchControlBit;
wire [2:0] branchControlBitWire1;
wire [2:0] branchControlBitWire2;
wire [2:0] branchControlBitWire3;
reg takeBranch;
wire takeBranchWire1;
wire takeCondBranchWire1;
//program counter wires to be piped into the IF_ID stage
wire [63:0] PCWire1;//form IF_ID, to branchCalcWire1
//the wire for the branch calculation, part 1 (immediate sign extended, bit shifted by 2 for *4)
wire [63:0] branchCalcWire1;//from immediate, to branchCalcwire2
//the wire for the branch calculation, part 2 (+4)
wire [63:0] branchCalcWire2;//from branchCalcWire1, to mux4
//the new buses to and from the ddr memory
output [63:0] daddrbus;//from EX_MEM, to SIM_OUT
inout [63:0] databus;//from SIM_IN/EX_MEM, to SIM_OUT/MEM_WB
//decoder tings
//LEG_UPDATE: opcode is 11 bits long now
wire [10:0] opCode;//from IF_ID
//LEG_UPDATE: funktion is no longer a thing, everything is in the opcode
//wire [5:0] funktion;//from IF_ID
//LEG_UPDATE: NOP\'s should be redirected to nothing register
reg NOP;
wire NOPWire1;
wire NOPWire2;
wire NOPWire3;
//ibus
input [31:0] ibus;//in for IF_ID
wire [31:0] ibusWire;//out for IF_ID
//Aselect
wire [31:0] AselectWire;//from rs, to regfile
wire [31:0] AselectWire1;
//LEG_UPDATE: rs->rn
wire [5:0] rn;//from ibusWire, to AselectWire
//Bselect
wire [31:0] BselectWire;//from rt, to BselectWire1
wire [31:0] BselectWire1;//from BselectWire, to regfile
wire [31:0] BselectWire2;
//LEG_UPDATE: rt->rm
wire [5:0] rm;//from ibsuWire, to BselectWire and mxu1
//LEG_UPDATE: add a bit for MOVZ select
//mov select
reg movBit1;
wire movBit2;
wire [5:0] moveImmShftAmt;
wire [5:0] moveImmShftAmtWire1;
//imm select
reg immBit1;//from IF_ID(ibusWire), to mux1 and ID_EX
wire immBit2;//from ID_EX, to mux2
//LEG_UPDATE: add the NZVC bit and it\'s potential values
//the NZVC bit
wire [3:0]NZVC;
wire potentialNBit;
wire potentialZBit;
wire potentialVBit;
wire potentialCBit;
//the control for setting NZVC
reg NZVCSetBit;
wire NZVCSetBitWire1;
//LEG_UPDATE: add a control bit set for LSL and LSR
reg [1:0] shiftBit1;
wire [1:0] shiftBit2;
//LEG_UPDATE: add the potential LSL and LSR bits for shifting
wire [63:0] potentialLSLResult;
wire [63:0] potentialLSRResult;
wire [63:0] actualLSResult;
//load word save word flag
reg [1:0] lwSwFlag1;//from IF_ID, to ID_EX
wire [1:0] lwSwFlag2;//from ID_EX, to EX_MEM
wire [1:0] lwSwFlag3;//from EX_MEM, to MEM_WB
wire [1:0] lwSwFlag4;//from MEM_WB, to mux3
//Dselect
wire [31:0] DselectWire1;//from muxOut, to ID_EX
//LEG_UPDATE: rd->rd (no change)
wire [5:0] rd;//from ID_EX, to mux1
wire [31:0] DselectWire2;//from ID_EX, to EX_MM
wire [31:0] DselectWire3;//from EX_MEM, to MEM_WB
wire [31:0] DselectWire3_5;//from MEM_WB, to mux3
wire [31:0] DselectWire4;//from mux3, to regfile
//LEG_UPDATE: new rt is also rd
//abus
//output [63:0] abus;//from ID_EX, to SIM_OUT
wire [63:0] abusWire1;//from regOut, to ID_EX
wire [63:0] abusWire2;//from ID_EX, to ALU
//bbus
//output [63:0] bbus;//from mux2Out, to SIM_OUT
wire [63:0] bbusWire1;//from regOut, to ID_EX
wire [63:0] bbusWire2;//from ID_EX, to mux2/EX_MEM
wire [63:0] bbusWire3;//from EX_MEM, to memory logic
wire [63:0] bbusWire3_5;//from memory logic, to MEM_WB
wire [63:0] bbusWire4;//from MEM_WB, to mux3
//dbus
wire [63:0] dbusWire1;//from ALU, to dbusWire1_5(SLE_MUX_TEST)
wire [63:0] dbusWire1_5;//from SLE_MUX_TEST to EX_MEM
wire [63:0] dbusWire1_6;
wire [63:0] dbusWire2;//from EM_MEM, to MEM_WB
wire [63:0] dbusWire3;//from MEM_WB, to mux3
//mux3
wire [63:0] mux3Out;//from dbusWire3/bbusWire4, to regfile
//mux2
wire [63:0] mux2Out;//from bbusWire2/immWire2, to mux5
//LEG_UPDATE: mux5
wire [63:0] mux5;//from mux2Out/DTAddrWire2, to ALU (as b)
wire [63:0] mux6;
//mux4 deciding wire
wire mux4Controller;//controls the pc address bus
//LEG_UPDATE: remove sign extended IMM wire, it\'s not a thing
//immediate
//wire [63:0] immWire1;//from IF_ID, to ID_EX
//wire [63:0] immWire2;//from ID_EX, to mux2
//and add the new parsed wires
wire [63:0] ALUImmWire1;
wire [63:0] ALUImmWire2;
wire [63:0] BranchAddrWire1;
wire [63:0] CondBranchAddrType1Wire1;//for b.cond
wire [63:0] CondBranchAddrType2Wire1;//for CBZ/CBNZ
wire [63:0] MOVImmWire1;
wire [63:0] MOVImmWire2;
wire [5:0] shamt;
wire [5:0] shamtWire1;
wire [63:0] DTAddrWire1;
wire [63:0] DTAddrWire2;
wire [63:0] DTAddrWire3;
wire [63:0] DTAddrWire4;
//S
reg [2:0] SWire1;//from IF_ID, to ID_EX
wire [2:0] SWire2;//from ID_EX, to ALU
//Cin
reg CinWire1;//from IF_ID, to ID_EX
wire CinWire2;//form ID_EX, to ALU
//init
initial begin
immBit1 = 1\'bx;
movBit1 = 1\'bx;
NZVCSetBit = 1\'bx;
CinWire1 = 1\'bx;
SWire1 = 3\'bxxx;
lwSwFlag1 = 2\'bxx;
branchControlBit = 3\'b0;
setControlBits = 2\'b00;
shiftBit1 = 2\'bxx;
takeBranch = 1\'b0;
NOP = 1\'bx;
end
//latch for pipeline 0(PC)
//module pipeline_0_latch(clk, iaddrbusWire1, iaddrbusOut);
pipeline_0_latch PC(.clk(clk),.iaddrbusWire1(iaddrbusWire1),.iaddrbusOut(iaddrbusWire2),.reset(reset));
//iaddrbusWire4 gets feed into the IF_ID stage
assign iaddrbusWire4 = iaddrbusWire2;
//feed the pc back into itself. may update iaddrbusWire2 from the IF_ID stage
assign iaddrbusWire1 = mux4Controller? branchCalcWire2 : iaddrbusWire2;
//assign the output
assign iaddrbus = iaddrbusWire1;
//PIPELINE_0_END
//latch for pipeline 1(IF_ID)
//module pipeline_1_latch(clk, ibus, ibusWire);
pipeline_1_latch IF_ID(.clk(clk),.ibus(ibus),.ibusWire(ibusWire),.PCIn(iaddrbusWire4),.PCOut(PCWire1));
//PIPELINE_1_START
//decode the input command
//LEG_UPDATE: updated to new leg instruction sets
assign opCode = ibusWire[31:21];
assign rn = ibusWire[9:5];//old rs
assign rm = ibusWire[20:16];//old rt
assign rd = ibusWire[4:0];
assign shamt = ibusWire[15:10];
assign DTAddrWire1 = ibusWire[20]? {55\'b1,ibusWire[20:12]} : {55\'b0,ibusWire[20:12]};
assign moveImmShftAmt = ibusWire[22:21] << 4;
//LEG_UPDATE: added the following
assign ALUImmWire1 = {52\'b0, ibusWire[21:10]};
assign BranchAddrWire1 = ibusWire[25]? {36\'b1111,ibusWire[25:0],2\'b00} : {36\'b0000,ibusWire[25:0],2\'b00};
assign CondBranchAddrType1Wire1 = ibusWire[23]? {43\'b11111111111,ibusWire[23:5],2\'b00} : {43\'b00000000000,ibusWire[23:5],2\'b00};//b.cond
assign MOVImmWire1= {48\'b0, ibusWire[20:5]};
//LEG_UPDATE: remove the following
//assign immWire1 = ibusWire[15]? {16\'b1111111111111111,ibusWire[15:0]} : {16\'b0000000000000000,ibusWire[15:0]};
//for the change in the opcode which is like always
always @(ibusWire) begin
immBit1 = 0;
movBit1 = 0;
CinWire1 = 0;
branchControlBit = 3\'b000;
setControlBits = 0;
NZVCSetBit = 0;
//assume not doing anything with the load or save
lwSwFlag1 = 2\'b00;
shiftBit1 = 2\'b00;
NOP = 1\'b0;
//write the cases for the opcode (immediate)
//LEG_UPDATE: updated opcodes and branch condition codes
//000 = noting, 001 = B, 010 = B.EQ
//011 = B.NE, 100 = B.LT, 101 = B.GE
//110 = CBNZ, 111 = CBZ
casez (opCode)
11\'b10001011000: begin
//add
SWire1 = 3\'b010;//add
end
11\'b1001000100?: begin
//addi
SWire1 = 3\'b010;
immBit1 = 1;
end
11\'b1011000100?: begin
//addis
SWire1 = 3\'b010;
immBit1 = 1;
NZVCSetBit = 1;
end
11\'b10101011000: begin
//adds
SWire1 = 3\'b010;
NZVCSetBit = 1;
end
11\'b10001010000: begin
//and
SWire1 = 3\'b110;//and
end
11\'b1001001000?: begin
//andi
SWire1 = 3\'b110;
immBit1 = 1;
end
11\'b1111001000?: begin
//andis
SWire1 = 3\'b110;
immBit1 = 1;
NZVCSetBit = 1;
end
11\'b11101010000: begin
//ands
SWire1 = 3\'b110;
NZVCSetBit = 1;
end
11\'b10110101???: begin
//CBNZ
//add i guess
SWire1 = 3\'b010;
branchControlBit = 3\'b110;
//takeBranch = 1;
end
11\'b10110100???: begin
//CBZ
//add i guess
SWire1 = 3\'b010;
branchControlBit = 3\'b111;
//takeBranch = 1;
end
11\'b11001010000: begin
//EOR (xor)
SWire1 = 3\'b000;
end
11\'b1101001000?: begin
//EORI(xori)
SWire1 = 3\'b000;
immBit1 = 1;
end
11\'b11111000010: begin
//LDUR
//command: rt value = from memory address, of rn value added with DTAddr
//load word, but still addi
SWire1 = 3\'b010;
lwSwFlag1 = 2\'b01;
end
11\'b11010011011: begin
//LSL
//uses shamt wire and abus to set for dbus
//overwide bbus to be r31 and swire to be add
//therefore it does nothing and we\'re not jumping around the pipeline
shiftBit1 = 2\'b01;
SWire1 = 3\'b010;
end
11\'b11010011010: begin
//LSR
//see above notes
shiftBit1 = 2\'b10;
SWire1 = 3\'b010;
end
11\'b110100101??: begin
//MOVZ
movBit1 = 1;
SWire1 = 3\'b100;
end
11\'b10101010000: begin
//ORR(or)
SWire1 = 3\'b100;
end
11\'b1011001000?: begin
//ORRI(ori)
SWire1 = 3\'b100;
immBit1 = 1;
end
11\'b11111000000: begin
//STUR
//command: memory of address, rn value added with DTAddr = rt value
//store word, but still addi
SWire1 = 3\'b010;
lwSwFlag1 = 2\'b10;
end
11\'b11001011000: begin
//sub
SWire1 = 3\'b011;
CinWire1 = 1;
end
11\'b1101000100?: begin
//subi
SWire1 = 3\'b011;
CinWire1 = 1;
immBit1 = 1;
end
11\'b1111000100?: begin
//subis
SWire1 = 3\'b011;
CinWire1 = 1;
immBit1 = 1;
NZVCSetBit = 1;
end
11\'b11101011000: begin
//subs
SWire1 = 3\'b011;
CinWire1 = 1;
NZVCSetBit = 1;
end
//000 = noting, 001 = B, 010 = B.EQ
//011 = B.NE, 100 = B.LT, 101 = B.GE
//110 = CBNZ, 111 = CBZ
11\'b000101?????: begin
//B
SWire1 = 3\'b010;
//set control bit
branchControlBit = 3\'b001;
end
11\'b01010101???: begin
//B.EQ
SWire1 = 3\'b010;
//set control bit
branchControlBit = 3\'b010;
//takeBranch = (NZVC[2] == 1\'b1)? 1:0;
end
11\'b01010110???: begin
//B.NE
SWire1 = 3\'b010;
//set control bit
branchControlBit = 3\'b011;
//takeBranch = (NZVC[2] == 1\'b0)? 1:0;
end
11\'b01010111???: begin
//B.LT(signed)
SWire1 = 3\'b010;
//set control bit
branchControlBit = 3\'b100;
//takeBranch = (NZVC[3] != NZVC[1])? 1:0;
end
11\'b01011000???: begin
//B.GE(signed)
SWire1 = 3\'b010;
//set control bit
branchControlBit = 3\'b101;
//takeBranch = (NZVC[3] == NZVC[1])? 1:0;
end
11\'b00000000000: begin
//NOP
SWire1 = 3\'b010;
//set control bit
NOP = 1\'b1;
end
//TODO: figure out if these are ever used
/*11\'b: begin
//SLT
//00 = nothing, 01 = SLT, 10 = SLE
setControlBits = 2\'b01;
//set to subtraction
SWire1 = 3\'b011;
end
11\'b: begin
//SLE
//00 = nothing, 01 = SLT, 10 = SLE
setControlBits = 2\'b10;
//set to subtraction
SWire1 = 3\'b011;
end*/
endcase
end
always@(negedge clk) begin
takeBranch = 1\'b0;
//LEG_UPDATE: updated opcodes and branch condition codes
//000 = noting, 001 = B, 010 = B.EQ
//011 = B.NE, 100 = B.LT, 101 = B.GE
//110 = CBNZ, 111 = CBZ
case (branchControlBit)
3\'b000: begin//nothing
takeBranch = 0;
end
3\'b001: begin//B
takeBranch = 1;
end
3\'b010: begin//B.EQ
takeBranch = (NZVC[2] == 1\'b1)? 1:0;
end
3\'b011: begin//B.NE
takeBranch = (NZVC[2] == 1\'b0)? 1:0;
end
3\'b100: begin//B.LT
takeBranch = (NZVC[3] != NZVC[1])? 1:0;
end
3\'b101: begin//B.GE
takeBranch = (NZVC[3] == NZVC[1])? 1:0;
end
3\'b110: begin//CBNZ
takeBranch = (abusWire1 != 0)? 1:0;
end
3\'b111: begin//CBZ
takeBranch = (abusWire1 == 0)? 1:0;
end
endcase
end
//write the select lines
assign AselectWire = ((branchControlBit == 3\'b110) || (branchControlBit == 3\'b111))? 1<<rd :1 << rn;
//LEG_UPDATE: need AsSelectWire for the move command
assign AselectWire1 = (movBit1)? 32\'h80000000 : AselectWire;
//only write to Bselect for real if it\'s actually goign to use Bselect
//i don\'t think this line matters but i feel like it\'s good pratice
//assign BselectWire = immBit1? 32\'hxxxxxxxx: 1 << rt;
assign BselectWire = 1 << rm;
//LEG_UPDATE: set BselectWire to R31(0) if it\'s a LSL/LSR command
assign BselectWire1 = ((shiftBit1 > 2\'b00) || (movBit1))? 32\'h80000000:BselectWire;
//LEG_UPDATE: BselectWire may need to get data from Bbus in regfile if it\'s a store command
assign BselectWire2 = (lwSwFlag1 == 2\'b10)? 1<<rd:BselectWire1;
//LEG_UPDATE: rt->rm
//LEG_UPDATE: dbus always holds the result for the alu output now
//mux1
//Rd for R, imm = false
//Rt for I, imm = true
//assign DselectWire1 = immBit1? 1<<rm : 1<<rd;
assign DselectWire1 = 1<<rd;
regfile Reggie3(.clk(clk),.Aselect(AselectWire1),.Bselect(BselectWire2),.Dselect(DselectWire4),.abus(abusWire1),.bbus(bbusWire1),.dbus(mux3Out));
//update the muxWire4 controll if the instruction is BEQ or BNE, and if it is actually equal
//mux4Controller = 1 if ((BEQ and abus == bbus) or (BNE and bbus != abus)), 0 otherwise
//00 = noting, 01 = BEQ, 10 = BNE
//CBNZ = 110, CBZ = 111
//assign mux4Controller = ((!clk) && ((branchControlBit==2\'b01) && (abusWire1 == bbusWire1)) || ((branchControlBit==2\'b10) && (abusWire1!=bbusWire1)))? 1: 0;
//assign takeCondBranchWire1 = ((!clk) && ((branchControlBit==3\'b110) && (abusWire1 != 0)) || ((branchControlBit==3\'b111) && (abusWire1 == 0)))? 1:0;
//assign takeBranchWire1 = takeCondBranchWire1|takeBranch;
assign takeBranchWire1 = takeBranch;
assign mux4Controller = ((!clk) && (branchControlBit > 3\'b000) && (takeBranchWire1))? 1 : 0;
//LEG_UPDATE: TODO: branch calculation is done in one step from above
//the branch calculation
assign branchCalcWire1 = (branchControlBit == 3\'b001)? BranchAddrWire1:CondBranchAddrType1Wire1;
assign branchCalcWire2 = branchCalcWire1 + PCWire1 - 4;
//PIPELINE_1_END
//latch for pipeline 2(ID_EX)
pipeline_2_latch ED_EX(.clk(clk),.abusWire1(abusWire1),.bbusWire1(bbusWire1),.DselectWire1(DselectWire1),.ALUImmWire1(ALUImmWire1),.SWire1(SWire1),
.CinWire1(CinWire1),.immBit1(immBit1),.lwSwFlag1(lwSwFlag1),.abusWire2(abusWire2),.bbusWire2(bbusWire2),.ALUImmWire2(ALUImmWire2),.CinWire2(CinWire2),
.DselectWire2(DselectWire2),.immBit2(immBit2),.SWire2,.lwSwFlag2(lwSwFlag2),.setControlBits(setControlBits),.setControlBitsWire1(setControlBitsWire1),
.branchControlBit(branchControlBit),.branchControlBitWire1(branchControlBitWire1),.NZVCSetBit(NZVCSetBit),.NZVCSetBitWire1(NZVCSetBitWire1),
.shiftBit1(shiftBit1),.shiftBit2(shiftBit2),.shamt(shamt),.shamtWire1(shamtWire1),.DTAddrWire1(DTAddrWire1),.DTAddrWire2(DTAddrWire2),
.MOVImmWire1(MOVImmWire1),.MOVImmWire2(MOVImmWire2),.movBit1(movBit1),.movBit2(movBit2),.moveImmShftAmt(moveImmShftAmt),
.moveImmShftAmtWire1(moveImmShftAmtWire1),.NOP(NOP),.NOPWire1(NOPWire1));
//PIPELINE_2_START
//mux2
//ALUImmWire2 for true, Bselet for false
assign mux2Out = immBit2? ALUImmWire2: bbusWire2;
//LEG_UPDATE: add mux5 for selecting the DTAddrWire
assign mux5 = (lwSwFlag2 > 2\'b00)? DTAddrWire2:mux2Out;
assign mux6 = (movBit2)? MOVImmWire2:mux5;
//make the ALU
//module alu64 (d, Cout, V, a, b, Cin, S);
alu64 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux6),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire),.V(overflowWire));
//wipe the dbus if it\'s an SLT or an SLE
//zero result flag
assign ZBit = (dbusWire1==0)? 1:0;
//potential values for if the instruction is for SLT or SLE
assign potentialSLTBit = (!ALUCoutWire && !ZBit)? 64\'h0000000000000001:64\'h0000000000000000;
assign potentialSLEBit = (!ALUCoutWire || ZBit)? 64\'h0000000000000001:64\'h0000000000000000;
//a determinate wire that uses SLT or SLE, assuming if not one, than the other
//(a wire later decides if that always "lateer" choosen one is actually used
//00 = nothing, 01 = SLT, 10 = SLE
assign actualSLBit = (setControlBitsWire1 == 2\'b01)? potentialSLTBit: potentialSLEBit;
//the wire that is used for the new dbusWire, adds a check for if the result needs to be the SLT or not
//SLE_MUX_TEST
//LEG_UPDATE: hook into the SLE wire for the LSL-LSR commands
//assign dbusWire1_5 = (setControlBitsWire1 > 2\'b00)? actualSLBit:dbusWire1;
assign potentialLSLResult = dbusWire1 << shamtWire1;
assign potentialLSRResult = dbusWire1 >> shamtWire1;
//assumes LSR if not LSL. won\'t apply it to dbus unless it\'s actually a shift command
//2\'b01 = LSL, 2\'b10 = LSR
assign actualLSResult = (shiftBit2 == 2\'b10)? potentialLSRResult:potentialLSLResult;
assign dbusWire1_5 = (shiftBit2 > 2\'b00)? actualLSResult:dbusWire1;
//LEG_UPDATE: apply the mov command to dbus
assign dbusWire1_6 = (movBit2)? {dbusWire1_5 << moveImmShftAmtWire1}: dbusWire1_5;
//LEG_UPDATE: if the NZVCSetBit is set, then set the NZVC values with the potential values
assign potentialNBit = (dbusWire1[63] == 1\'b1)? 1\'b1:1\'b0;
assign potentialZBit = (ZBit)? 1\'b1:1\'b0;
assign potentialVBit = (overflowWire)? 1\'b1:1\'b0;
assign potentialCBit = (ALUCoutWire)? 1\'b1:1\'b0;
assign NZVC[3] = (NZVCSetBitWire1)? potentialNBit:1\'bz;//N (negative)
assign NZVC[2] = (NZVCSetBitWire1)? potentialZBit:1\'bz;//Z (zero)
assign NZVC[1] = (NZVCSetBitWire1)? potentialVBit:1\'bz;//V (overflow, signed)
assign NZVC[0] = (NZVCSetBitWire1)? potentialCBit:1\'bz;//C (carry)
//PIPELINE_2_END
//latch for pipeline 3(EX_MEM)
pipeline_3_latch EX_MEME (.clk(clk),.dbusWire1(dbusWire1_6),.DselectWire2(DselectWire2),.bbusWire2(bbusWire2),.lwSwFlag2(lwSwFlag2),.dbusWire2(dbusWire2),
.DselectWire3(DselectWire3),.bbusWire3(bbusWire3),.lwSwFlag3(lwSwFlag3),.branchControlBitWire1(branchControlBitWire1),.branchControlBitWire2(branchControlBitWire2),
.NOPWire1(NOPWire1),.NOPWire2(NOPWire2));
//PIPELINE_3_SRART
//assign output values
//LEG_UPDATE: if store, bbusWire3 has the data to be written
//if load,
assign bbusWire3_5 = (lwSwFlag3==2\'b01)? databus: bbusWire3;//2\'b01 = load
assign databus = (lwSwFlag3 == 2\'b10)? bbusWire3: 64\'hzzzzzzzz;//2\'b10 = store
assign daddrbus = dbusWire2;
//PIPELINE_3_END
//latch for pipeline 4(MEM_WB)
pipeline_4_latch MEM_WB (.clk(clk),.dbusWire2(dbusWire2),.DselectWire3(DselectWire3),.bbusWire3(bbusWire3_5),.lwSwFlag3(lwSwFlag3),.dbusWire3(dbusWire3),
.DselectWire4(DselectWire3_5),.bbusWire4(bbusWire4),.lwSwFlag4(lwSwFlag4),.branchControlBitWire2(branchControlBitWire2),
.branchControlBitWire3(branchControlBitWire3),.NOPWire2(NOPWire2),.NOPWire3(NOPWire3));
//PIPELINE_4_START
//the mux for the data writeBack
assign mux3Out = (lwSwFlag4 == 2\'b01)? bbusWire4:dbusWire3;//2\'b01 = load
//disable the writeback if it\'s a store word OR if it\'s a branch OR if it\'s a NOP
//LEG_UPDATE: the address now is R31, 13\'h80000000
assign DselectWire4 = ((lwSwFlag4 == 2\'b10) ||(branchControlBitWire3 > 3\'b000) || (NOPWire3 == 1\'b1))? 32\'h80000000: DselectWire3_5;
//PIPELINE_4_END
endmodule
//phase 0 pipeline latch (PC)
module pipeline_0_latch(clk, iaddrbusWire1, iaddrbusOut, reset);
input clk, reset;
input [63:0] iaddrbusWire1;
output [63:0] iaddrbusOut;
reg [63:0] iaddrbusOut;
reg startBit;
initial begin
startBit = 1;
end
always@(posedge clk) begin
//if reset is high, reset the counter
//else incriment
iaddrbusOut = (reset|startBit)? 0:iaddrbusWire1+4;
startBit = 0;
end
endmodule
//phase 1 pipeline latch(IF_ID)
module pipeline_1_latch(clk, ibus, ibusWire, PCIn, PCOut);
input [31:0] ibus;
input [63:0] PCIn;
input clk;
output [31:0] ibusWire;
output [63:0] PCOut;
reg [31:0] ibusWire;
reg [63:0] PCOut;
always @(posedge clk) begin
//EDIT: this is delayed branching, other instructions can be put in place\\
//what did i mean by that? ^^
ibusWire = ibus;
PCOut = PCIn;
end
endmodule
//phase 2 pipeline latch(ID_EX)
module pipeline_2_latch(clk, abusWire1, bbusWire1, DselectWire1, ALUImmWire1, SWire1, CinWire1,immBit1,lwSwFlag1,
abusWire2,bbusWire2,ALUImmWire2,SWire2,CinWire2,DselectWire2,immBit2,lwSwFlag2,setControlBits,setControlBitsWire1,
branchControlBit,branchControlBitWire1,NZVCSetBit,NZVCSetBitWire1,shiftBit1,shiftBit2,shamt,shamtWire1,DTAddrWire1,
DTAddrWire2,MOVImmWire1,MOVImmWire2,movBit1,movBit2,moveImmShftAmt,moveImmShftAmtWire1,NOP,NOPWire1);
input clk, CinWire1,immBit1,NOP;
input [63:0] abusWire1, bbusWire1, ALUImmWire1,DTAddrWire1,MOVImmWire1;
input [31:0] DselectWire1;
input [2:0] SWire1;
input [1:0] lwSwFlag1;
input [1:0] setControlBits;
input [2:0] branchControlBit;
input NZVCSetBit;
input [1:0] shiftBit1;
input [5:0] shamt,moveImmShftAmt;
input movBit1;
output CinWire2,immBit2,NOPWire1;
output [63:0] abusWire2, bbusWire2, ALUImmWire2,DTAddrWire2,MOVImmWire2;
output [31:0] DselectWire2;
output [2:0] SWire2;
output [1:0] lwSwFlag2;
output [1:0] setControlBitsWire1;
output [2:0] branchControlBitWire1;
output NZVCSetBitWire1;
output [1:0] shiftBit2;
output [5:0] shamtWire1,moveImmShftAmtWire1;
output movBit2;
reg CinWire2,immBit2,NOPWire1;
reg [63:0] abusWire2, bbusWire2, ALUImmWire2,DTAddrWire2,MOVImmWire2;
reg [31:0] DselectWire2;
reg [2:0] SWire2;
reg [1:0] lwSwFlag2;
reg [1:0] setControlBitsWire1;
reg [2:0] branchControlBitWire1;
reg NZVCSetBitWire1;
reg [1:0] shiftBit2;
reg [5:0] shamtWire1,moveImmShftAmtWire1;
reg movBit2;
always @(posedge clk) begin
abusWire2 = abusWire1;
bbusWire2 = bbusWire1;
DselectWire2 = DselectWire1;
ALUImmWire2 = ALUImmWire1;
SWire2 = SWire1;
CinWire2 = CinWire1;
immBit2 = immBit1;
lwSwFlag2 = lwSwFlag1;
setControlBitsWire1 = setControlBits;
branchControlBitWire1 = branchControlBit;
NZVCSetBitWire1 = NZVCSetBit;
shiftBit2 = shiftBit1;
shamtWire1 = shamt;
DTAddrWire2 = DTAddrWire1;
MOVImmWire2 = MOVImmWire1;
movBit2 = movBit1;
moveImmShftAmtWire1 = moveImmShftAmt;
NOPWire1 = NOP;
end
endmodule
//phase 3 pipeliune latch(EX_MEM)
module pipeline_3_latch(clk, dbusWire1, DselectWire2, bbusWire2, lwSwFlag2, dbusWire2, DselectWire3,bbusWire3,lwSwFlag3,branchControlBitWire1,
branchControlBitWire2,NOPWire1,NOPWire2);
input clk;
input [63:0] dbusWire1, bbusWire2;
input [31:0] DselectWire2;
input [1:0] lwSwFlag2;
input [2:0] branchControlBitWire1;
input NOPWire1;
output [63:0] dbusWire2, bbusWire3;
output [31:0] DselectWire3;
output [1:0] lwSwFlag3;
output [2:0] branchControlBitWire2;
output NOPWire2;
reg [63:0] dbusWire2, bbusWire3;
reg [31:0] DselectWire3;
reg [1:0] lwSwFlag3;
reg [2:0] branchControlBitWire2;
reg NOPWire2;
always @(posedge clk) begin
dbusWire2 = dbusWire1;
DselectWire3 = DselectWire2;
bbusWire3 = bbusWire2;
lwSwFlag3 = lwSwFlag2;
branchControlBitWire2 = branchControlBitWire1;
NOPWire2 = NOPWire1;
end
endmodule
//phase 4 pipeline latch(MEM_WB)
module pipeline_4_latch(clk, dbusWire2, DselectWire3, bbusWire3, lwSwFlag3, dbusWire3, DselectWire4,bbusWire4,lwSwFlag4,branchControlBitWire2,
branchControlBitWire3,NOPWire2,NOPWire3);
input clk;
input [63:0] dbusWire2, bbusWire3;
input [31:0] DselectWire3;
input [1:0] lwSwFlag3;
input [2:0] branchControlBitWire2;
input NOPWire2;
output [63:0] dbusWire3, bbusWire4;
output [31:0] DselectWire4;
output [1:0] lwSwFlag4;
output [2:0] branchControlBitWire3;
output NOPWire3;
reg [63:0] dbusWire3, bbusWire4;
reg [31:0] DselectWire4;
reg [1:0] lwSwFlag4;
reg [2:0] branchControlBitWire3;
reg NOPWire3;
always @(posedge clk) begin
dbusWire3 = dbusWire2;
DselectWire4 = DselectWire3;
bbusWire4 = bbusWire3;
lwSwFlag4 = lwSwFlag3;
branchControlBitWire3 = branchControlBitWire2;
NOPWire3 = NOPWire2;
end
endmodule
module regfile(
input [31:0] Aselect,//select the register index to read from to store into abus
input [31:0] Bselect,//select the register index to read from to store into bbus
input [31:0] Dselect,//select the register to write to from dbus
input [63:0] dbus,//data in
output [63:0] abus,//data out
output [63:0] bbus,//data out
input clk
);
assign abus = Aselect[31] ? 64\'b0 : 64\'bz;
assign bbus = Bselect[31] ? 64\'b0 : 64\'bz;
DNegflipFlop myFlips[30:0](//32 wide register
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[30:0]),
.Bselect(Bselect[30:0]),
.Aselect(Aselect[30:0]),
.bbus(bbus),
.clk(clk)
);
endmodule
module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [63:0] dbus;
input Dselect;//the select write bit for this register
input Bselect;//the select read bit for this register
input Aselect;
input clk;
output [63:0] abus;
output [63:0] bbus;
wire wireclk;
reg [63:0] data;
assign wireclk = clk & Dselect;
initial begin
data = 64\'h0000000000000000;
end
always @(negedge clk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect? data : 64\'hzzzzzzzzzzzzzzzz;
assign bbus = Bselect? data : 64\'hzzzzzzzzzzzzzzzz;
endmodule
//Below this point is code from assignment 1//
//The declaration of the entire ALU itself.
module alu64 (d, Cout, V, a, b, Cin, S);
output[63:0] d;//the output bus
output Cout, V;//Cout is the bit for it it needs to carry over ?/ V is the overflow bit.
input [63:0] a, b;//the two input buses
input Cin;//the bit for marking if it is carrying over from a ?
input [2:0] S;//The select bus. It defines the operation to do with input busses a and b
wire [63:0] c, g, p;
wire gout, pout;
//The core ALU bus
alu_cell mycell[63:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
//the top Look-Ahead-Carry module.
lac6 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
//the overflow module
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[63]),
.Cin(Cin)
);
endmodule
//The module to handle a single bit operation for the top ALU module
module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;//generate carry
p = a ^ bint;//proragate carry
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule
//The module to handle the overflow bit
module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule
//Look-Ahead Carry unit level 1. Used for the root (level 1) and first child leafs (level 2)
module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule
//Look-Ahead Carry unit level 2. Contains LACs for the root and level 1. Used in level 3
module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 3. Contains LACs for the root and level 2. Used in level 4
module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 4. Contains LACs for the root and level 3. Used in level 5
module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 5. Contains LACs for the root and level 3. Used in level 6
module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 6. Caontains LACs for the root and level 5. Used in the core alu64 module
module lac6 (c, gout, pout, Cin, g, p);
output [63:0] c;
output gout, pout;
input Cin;
input [63:0] g, p;
wire [1:0] cint, gint, pint;
lac5 leaf0(
.c(c[31:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[31:0]),
.p(p[31:0])
);
lac5 leaf1(
.c(c[63:32]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[63:32]),
.p(p[63:32])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
|
`timescale 1ns/10ps
module regalu_testbench();
//------ Ports Declaration-----//
reg [31:0] Aselect, Bselect, Dselect;
reg [2:0] S, stm_S[0:29];
reg Cin, clk, stm_CL[0:29], stm_Cin[0:29];
wire [31:0] abus;
wire [31:0] bbus;
wire [31:0] dbus;
reg [31:0] dontcare, ref_abus[0:29], ref_bbus[0:29], ref_dbus[0:29], asel[0:29], bsel[0:29], dsel[0:29];
integer error, i, k, ntests;
regalu dut(.Aselect(Aselect), .Bselect(Bselect), .Dselect(Dselect), .clk(clk), .abus(abus), .bbus(bbus), .dbus(dbus), .S(S), .Cin(Cin));
initial begin
// ---------- NO TEST 1a ---------- //
stm_CL[0]=0;
stm_Cin[0]=0;
stm_S[0] =3\'b001;
asel[0]= 32\'h00000001;
bsel[0]=32\'h00000001;
dsel[0]=32\'h00000001;
ref_abus[0]=32\'h00000000;
ref_bbus[0]=32\'h00000000; // Reading R0 for 00000000 in abus and bbus for input to alu.(XNOR R0,R0 )
ref_dbus[0]=32\'hxxxxxxxx;
stm_CL[1]=1;
stm_Cin[1]=0;
stm_S[1]=3\'b001;
asel[1]= 32\'h00000001;
bsel[1]=32\'h00000001;
dsel[1]=32\'h00000001;
ref_abus[1]=32\'hxxxxxxxx;
ref_bbus[1]=32\'hxxxxxxxx;
ref_dbus[1]=32\'hxxxxxxxx; //Doing nothing with the register
// ---------- XNOR TEST 1b ----------//
stm_CL[2]=0;
stm_Cin[2]=0;
stm_S[2]=3\'b001;
asel[2]= 32\'h00000001;
bsel[2]=32\'h00000001;
dsel[2]=32\'h00000001;
ref_abus[2]=32\'h00000000;
ref_bbus[2]=32\'h00000000; // Reading R0 in abus and bbus for input to alu.(XNOR R0,R0)
ref_dbus[2]=32\'hxxxxxxxx;
stm_CL[3]=1;
stm_Cin[3]=0;
stm_S[3]=3\'b110;
asel[3]= 32\'h00000001;
bsel[3]= 32\'h00000001;
dsel[3]=32\'h00000002;
ref_abus[3]=32\'hxxxxxxxx;
ref_bbus[3]=32\'hxxxxxxxx;
ref_dbus[3]=32\'hFFFFFFFF; // Writing R1 with FFFFFFFF (Result of XNOR R0,R0) From alu.
// ---------- XNOR TEST 2 ---------- //
stm_CL[4]=0;
stm_Cin[4]=0;
stm_S[4]=3\'b001;
asel[4]=32\'h00000001;
bsel[4]=32\'h00000002;
dsel[4]=32\'h00000001;
ref_abus[4]=32\'h00000000;
ref_bbus[4]=32\'hFFFFFFFF; //Reading R0 and R1 for input to alu (OR R0,R1)
ref_dbus[4]=32\'hxxxxxxxx;
stm_CL[5]=1;
stm_Cin[5]=0;
stm_S[5]=3\'b100;
asel[5]=32\'h00000001;
bsel[5]=32\'h00000001;
dsel[5]=32\'h00000004;
ref_abus[5]=32\'hxxxxxxxx;
ref_bbus[5]=32\'hxxxxxxxx;
ref_dbus[5]=32\'hFFFFFFFF; // Writing R2 with FFFFFFFF (Result of XNOR R0,R1) From alu.
// ---------- OR TEST 3 ---------- //
stm_CL[6]=0;
stm_Cin[6]=0;
stm_S[6]=3\'b100;
asel[6]=32\'h00000004;
bsel[6]=32\'h00000002;
dsel[6]=32\'h00000001;
ref_abus[6]=32\'hFFFFFFFF;
ref_bbus[6]=32\'hFFFFFFFF; //Reading R1 and R2 for input to alu (XOR R1,R2)
ref_dbus[6]=32\'hxxxxxxxx;
stm_CL[7]=1;
stm_Cin[7]=0;
stm_S[7]=3\'b000;
asel[7]=32\'h00000001;
bsel[7]=32\'h00000001;
dsel[7]=32\'h00000008;
ref_abus[7]=32\'hxxxxxxxx;
ref_bbus[7]=32\'hxxxxxxxx;
ref_dbus[7]=32\'hFFFFFFFF; // Writing R3 with FFFFFFFF ( Result of OR R0,R1) from alu.
// ---------- XOR TEST 4 ---------- //
stm_CL[8]=0;
stm_Cin[8]=0;
stm_S[8]=3\'b000;
asel[8]=32\'h00000008;
bsel[8]=32\'h00000004;
dsel[8]=32\'h00000000;
ref_abus[8]=32\'hFFFFFFFF;
ref_bbus[8]=32\'hFFFFFFFF; //Reading R3 and R2 for input to alu (XNOR R3,R2)
ref_dbus[8]=32\'hxxxxxxxx;
stm_CL[9]=1;
stm_Cin[9]=0;
stm_S[9]=3\'b001;
asel[9]=32\'h00000001;
bsel[9]=32\'h00000001;
dsel[9]=32\'h00000010;
ref_abus[9]=32\'hxxxxxxxx;
ref_bbus[9]=32\'hxxxxxxxx;
ref_dbus[9]=32\'h00000000; // Writing R4 With 00000000 (Result of XOR R1,R2) from alu
// ------------ XNOR NOT TEST ------------ //
stm_CL[10]=0;
stm_Cin[10]=0;
stm_S[10]=3\'b001;
asel[10]=32\'h00000008;
bsel[10]=32\'h00000010;
dsel[10]=32\'h00000000;
ref_abus[10]=32\'hFFFFFFFF;
ref_bbus[10]=32\'h00000000; // Reading R3 and R4 for input to alu (NOR R3,R4)
ref_dbus[10]=32\'hxxxxxxxx;
stm_CL[11]=1;
stm_Cin[11]=0;
stm_S[11]=3\'b101;
asel[11]=32\'h00000001;
bsel[11]=32\'h00000001;
dsel[11]=32\'h00000020;
ref_abus[11]=32\'hxxxxxxxx;
ref_bbus[11]=32\'hxxxxxxxx;
ref_dbus[11]=32\'hFFFFFFFF; // Writing R5 with FFFFFFFF (Result of XNOR R3,R2) from alu
// ------------ NOR TEST ---------------- //
stm_CL[12]=0;
stm_Cin[12]=0;
stm_S[12]=3\'b101;
asel[12]=32\'h00000010;
bsel[12]=32\'h00000020;
dsel[12]=32\'h00000000;
ref_abus[12]=32\'h00000000;
ref_bbus[12]=32\'hFFFFFFFF; //Reading R4,R5 for input to alu (ADD R4,R5)
ref_dbus[12]=32\'hxxxxxxxx;
stm_CL[13]=1;
stm_Cin[13]=0;
stm_S[13]=3\'b010;
asel[13]=32\'h00000001;
bsel[13]=32\'h00000001;
dsel[13]=32\'h00000040;
ref_abus[13]=32\'hxxxxxxxx;
ref_bbus[13]=32\'hxxxxxxxx;
ref_dbus[13]=32\'h00000000; // Writing R6 with 00000000 (Result of NOR R3,R4) From alu.
// ------------- ADD TEST --------------//
stm_CL[14]=0;
stm_Cin[14]=0;
stm_S[14]=3\'b010;
asel[14]=32\'h00000020;
bsel[14]=32\'h00000040;
dsel[14]=32\'h00000000;
ref_abus[14]=32\'hFFFFFFFF;
ref_bbus[14]=32\'h00000000; // Reading R5, R6 for input to alu (XOR R5,R6)
ref_dbus[14]=32\'hxxxxxxxx;
stm_CL[15]=1;
stm_Cin[15]=0;
stm_S[15]=3\'b000;
asel[15]=32\'h00000001;
bsel[15]=32\'h00000001;
dsel[15]=32\'h00000080;
ref_abus[15]=32\'hxxxxxxxx;
ref_bbus[15]=32\'hxxxxxxxx;
ref_dbus[15]=32\'hFFFFFFFF; // Writing R7 with FFFFFFFF (Result of ADD R4,R5)
// ------------ XOR TEST ---------------//
stm_CL[16]=0;
stm_Cin[16]=0;
stm_S[16]=3\'b000;
asel[16]=32\'h00000040;
bsel[16]=32\'h00000080;
dsel[16]=32\'h00000000;
ref_abus[16]=32\'h00000000;
ref_bbus[16]=32\'hFFFFFFFF; // Reading R6,R7 for input to alu (XNOR R6,R7)
ref_dbus[16]=32\'hxxxxxxxx;
stm_CL[17]=1;
stm_Cin[17]=0;
stm_S[17]=3\'b001;
asel[17]=32\'h00000001;
bsel[17]=32\'h00000001;
dsel[17]=32\'h00000100;
ref_abus[17]=32\'hxxxxxxxx;
ref_bbus[17]=32\'hxxxxxxxx;
ref_dbus[17]=32\'hFFFFFFFF; // Writing R8 with FFFFFFFF (Result of XOR R5,R6)
// ------------ XNOR TEST -------------//
stm_CL[18]=0;
stm_Cin[18]=0;
stm_S[18]=3\'b001;
asel[18]=32\'h00000080;
bsel[18]=32\'h00000100;
dsel[18]=32\'h00000100;
ref_abus[18]=32\'hFFFFFFFF;
ref_bbus[18]=32\'hFFFFFFFF; // Reading R7,R8 for input to alu (OR R7,R8)
ref_dbus[18]=32\'hxxxxxxxx;
stm_CL[19]=1;
stm_Cin[19]=0;
stm_S[19]=3\'b100;
asel[19]=32\'h00000001;
bsel[19]=32\'h00000001;
dsel[19]=32\'h00000200;
ref_abus[19]=32\'hxxxxxxxx;
ref_bbus[19]=32\'hxxxxxxxx;
ref_dbus[19]=32\'h00000000; // Writing R9 with 00000000 (Result of XNOR R6,R7)
// ------------- OR TEST ------------//
stm_CL[20]=0;
stm_Cin[20]=0;
stm_S[20]=3\'b100;
asel[20]=32\'h00000100;
bsel[20]=32\'h00000200;
dsel[20]=32\'h00000000;
ref_abus[20]=32\'hFFFFFFFF;
ref_bbus[20]=32\'h00000000; // Reading R8,R9 for input to alu (NOR R8,R9)
ref_dbus[20]=32\'hxxxxxxxx;
stm_CL[21]=1;
stm_Cin[21]=0;
stm_S[21]=3\'b101;
asel[21]=32\'h00000001;
bsel[21]=32\'h00000001;
dsel[21]=32\'h00000400;
ref_abus[21]=32\'hxxxxxxxx;
ref_bbus[21]=32\'hxxxxxxxx;
ref_dbus[21]=32\'hFFFFFFFF; //Writing R10 with FFFFFFFF (Result of OR R7,R8)
// ------------ NOR TEST -------------//
stm_CL[22]=0;
stm_Cin[22]=0;
stm_S[22]=3\'b101;
asel[22]=32\'h00000200;
bsel[22]=32\'h00000400;
dsel[22]=32\'h00000000;
ref_abus[22]=32\'h00000000;
ref_bbus[22]=32\'hFFFFFFFF; //Reading R9,R10 for input to alu (AND R9,R10)
ref_dbus[22]=32\'hxxxxxxxx;
stm_CL[23]=1;
stm_Cin[23]=0;
stm_S[23]=3\'b110;
asel[23]=32\'h0000001;
bsel[23]=32\'h0000001;
dsel[23]=32\'h0000800;
ref_abus[23]=32\'hxxxxxxxx;
ref_bbus[23]=32\'hxxxxxxxx;
ref_dbus[23]=32\'h00000000; // Writing R11 with 00000000 (Result of NOR R8,R9)
// ------------ AND TEST ---------------//
stm_CL[24]=0;
stm_Cin[24]=0;
stm_S[24]=3\'b110;
asel[24]=32\'h00000400;
bsel[24]=32\'h00000800;
dsel[24]=32\'h00000000;
ref_abus[24]=32\'hFFFFFFFF;
ref_bbus[24]=32\'h00000000; // Reading R10,R11 for input to alu (XOR R10,R11)
ref_dbus[24]=32\'hxxxxxxxx;
stm_CL[25]=1;
stm_Cin[25]=0;
stm_S[25]=3\'b000;
asel[25]=32\'h00000001;
bsel[25]=32\'h00000001;
dsel[25]=32\'h00001000;
ref_abus[25]=32\'hxxxxxxxx;
ref_bbus[25]=32\'hxxxxxxxx;
ref_dbus[25]=32\'h00000000; //Writing R12 with 00000000 (Result of AND R9,R10)
// ------------ XOR TEST --------------//
stm_CL[26]=0;
stm_Cin[26]=0;
stm_S[26]=3\'b000;
asel[26]=32\'h00000800;
bsel[26]=32\'h00001000;
dsel[26]=32\'h00000000;
ref_abus[26]=32\'h00000000;
ref_bbus[26]=32\'h00000000; //Reading R11,R12 for input to alu (XNOR R11,R12)
ref_dbus[26]=32\'hxxxxxxxx;
stm_CL[27]=1;
stm_Cin[27]=0;
stm_S[27]=3\'b001;
asel[27]=32\'h00000001;
bsel[27]=32\'h00000001;
dsel[27]=32\'h00002000;
ref_abus[27]=32\'hxxxxxxxx;
ref_bbus[27]=32\'hxxxxxxxx;
ref_dbus[27]=32\'hFFFFFFFF; // Writing R13 with FFFFFFFF (Result of XOR R10,R11)
// ------------ XNOR TEST ---------------//
stm_CL[28]=0;
stm_Cin[28]=0;
stm_S[28]=3\'b001;
asel[28]=32\'h00001000;
bsel[28]=32\'h00002000;
dsel[28]=32\'h00000000;
ref_abus[28]=32\'h00000000;
ref_bbus[28]=32\'hFFFFFFFF; // Reading R12,R13 for input to alu (OR R12,R13)
ref_dbus[28]=32\'hxxxxxxxx;
stm_CL[29]=1;
stm_Cin[29]=1;
stm_S[29]=3\'b110;
asel[29]=32\'h00000001;
bsel[29]=32\'h00000001;
dsel[29]=32\'h00004000;
ref_abus[29]=32\'hxxxxxxxx;
ref_bbus[29]=32\'hxxxxxxxx;
ref_dbus[29]=32\'hFFFFFFFF; //Writing R14 with FFFFFFFF (Result of XNOR R11,R12)
dontcare = 32\'hxxxxxxxx;
ntests = 30;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
for (k=0; k<= 29; k=k+1)
begin
Aselect=asel[k]; Bselect=bsel[k]; Dselect=dsel[k]; clk=stm_CL[k]; S=stm_S[k]; Cin=stm_Cin[k];
#25
if ( k >= 3) begin
if ( stm_S[k-2] == 3\'b000 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A XOR B -----");
if ( stm_S[k-2] == 3\'b001 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A XNOR B -----");
if ( stm_S[k-2] == 3\'b010 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A + B // CARRY CHAIN -----");
if ( stm_S[k-2] == 3\'b100 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A OR B -----");
if ( stm_S[k-2] == 3\'b011 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A - B -----");
if ( stm_S[k-2] == 3\'b101 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A NOR B -----");
if ( stm_S[k-2] == 3\'b110 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A AND B -----");
end
$display ("Test=%d \
Time=%t \
Clk=%b \
S=%b \
Cin=%b \
Aselect=%b \
Bselect=%b \
Dselect=%b \
abus=%b \
ref_abus=%b \
bbus=%b \
ref_bbus=%b \
dbus=%b \
ref_dbus=%b \
", k, $realtime, clk, S, Cin, Aselect, Bselect, Dselect, abus, ref_abus[k], bbus, ref_bbus[k], dbus, ref_dbus[k]);
if ( ( (ref_bbus[k] !== bbus) && (ref_bbus[k] !== dontcare) ) || ( (ref_abus[k] !== abus) && (ref_abus[k] !== dontcare)) || ( (ref_dbus[k] !== dbus) && (ref_dbus[k] !== dontcare)) )
begin
$display ("-------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
if ( error !== 0)
begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
`timescale 1ns/10ps
module cpu5_testbench();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:35];
wire [31:0] iaddrbus, daddrbus;
reg [31:0] iaddrbusout[0:35], daddrbusout[0:35];
wire [31:0] databus;
reg [31:0] databusk, databusin[0:35], databusout[0:35];
reg clk, reset;
reg clkd;
reg [31:0] dontcare;
reg [24*8:1] iname[0:35];
integer error, k, ntests;
\tparameter Rformat\t= 6\'b000000;
\tparameter ADDI\t\t= 6\'b000011;
\tparameter SUBI\t\t= 6\'b000010;
\tparameter XORI\t\t= 6\'b000001;
\tparameter ANDI\t\t= 6\'b001111;
\tparameter ORI\t\t= 6\'b001100;
\tparameter LW\t\t= 6\'b011110;
\tparameter SW\t\t= 6\'b011111;
\tparameter BEQ\t\t= 6\'b110000;
\tparameter BNE\t\t= 6\'b110001;
\tparameter ADD\t\t= 6\'b000011;
\tparameter SUB\t\t= 6\'b000010;
\tparameter XOR\t\t= 6\'b000001;
\tparameter AND\t\t= 6\'b000111;
\tparameter OR\t\t= 6\'b000100;
\tparameter SLT\t\t= 6\'b110110;
\tparameter SLE\t\t= 6\'b110111;
cpu5 dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
// This test file runs the following program.
iname[0] = "ADDI R20, R0, #-1";
iname[1] = "ADDI R21, R0, #1";
iname[2] = "ADDI R22, R0, #2";
iname[3] = "LW R24, 0(R20)";
iname[4] = "LW R25, 0(R21)";
iname[5] = "SW 1000(R22), R20";
iname[6] = "SW 2(R0), R21";
iname[7] = "ADD R26, R24, R25";
iname[8] = "SUBI R17, R24, 6420";
iname[9] = "SUB R27, R24, R25";
iname[10] = "ANDI R18, R24, #0";
iname[11] = "AND R28, R24, R0";
iname[12] = "XORI R19, R24, 6420";
iname[13] = "XOR R29, R24, R25";
iname[14] = "ORI R20, R24, 6420";
iname[15] = "OR R30, R24, R25";
iname[16] = "SW 0(R26), R26";
iname[17] = "SW 0(R17), R27";
iname[18] = "SW 1000(R18), R28";
iname[19] = "SW 0(R19), R29";
iname[20] = "SW 0(R20), R30";
iname[21] = "SLT R1, R0, R21"; // Setting R1 to 32\'h00000001 (since, R0 < R21).
iname[22] = "ADDI R5, R0, #1";
iname[23] = "ADDI R6, R0, #1";
iname[24] = "BNE R0, R1, #10"; // Branching to (32\'h00000060 + 32\'h00000004 + 32\'h00000028 = 32\'h0000008C) since, R0 != R1.
iname[25] = "ADDI R8, R0, #1"; // Delay Slot
//Branched Location - 32\'h0000008C //
iname[26] = "SLE R2, R0, R0"; // Setting R2 to 32\'h00000001 (since, R0 = R0).
iname[27] = "NOP";
iname[28] = "NOP";
iname[29] = "BEQ R0, R2, #25"; // NOT Branching since, R2 != R0.
iname[30] = "NOP"; // Delay Slot
iname[31] = "BEQ R2, R2, #10"; // Branching to (32h\'0000000A0 + 32\'h00000004 + 32\'h00000028 = 32\'h000000CC)
iname[32] = "ADDI R20, R0, #1"; // Delay Slot
//Branched Location - 32\'h000000CC //
iname[33] = "NOP";
iname[34] = "NOP";
iname[35] = "NOP";
dontcare = 32\'hx;
//* ADDI R20, R0, #-1
iaddrbusout[0] = 32\'h00000000;
// opcode source1 dest Immediate...
instrbusin[0]={ADDI, 5\'b00000, 5\'b10100, 16\'hFFFF};
daddrbusout[0] = dontcare;
databusin[0] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[0] = dontcare;
//* ADDI R21, R0, #1
iaddrbusout[1] = 32\'h00000004;
// opcode source1 dest Immediate...
instrbusin[1]={ADDI, 5\'b00000, 5\'b10101, 16\'h0001};
daddrbusout[1] = dontcare;
databusin[1] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[1] = dontcare;
//* ADDI R22, R0, #2
iaddrbusout[2] = 32\'h00000008;
// opcode source1 dest Immediate...
instrbusin[2]={ADDI, 5\'b00000, 5\'b10110, 16\'h0002};
daddrbusout[2] = dontcare;
databusin[2] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[2] = dontcare;
//* LW R24, 0(R20)
iaddrbusout[3] = 32\'h0000000C;
// opcode source1 dest Immediate...
instrbusin[3]={LW, 5\'b10100, 5\'b11000, 16\'h0000};
daddrbusout[3] = 32\'hFFFFFFFF;
databusin[3] = 32\'hCCCCCCCC;
databusout[3] = dontcare;
//* LW R25, 0(R21)
iaddrbusout[4] = 32\'h00000010;
// opcode source1 dest Immediate...
instrbusin[4]={LW, 5\'b10101, 5\'b11001, 16\'h0000};
daddrbusout[4] = 32\'h00000001;
databusin[4] = 32\'hAAAAAAAA;
databusout[4] = dontcare;
//* SW 1000(R22), R20
iaddrbusout[5] = 32\'h00000014;
// opcode source1 dest Immediate...
instrbusin[5]={SW, 5\'b10110, 5\'b10100, 16\'h1000};
daddrbusout[5] = 32\'h00001002;
databusin[5] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[5] = 32\'hFFFFFFFF;
//* SW 2(R0), R21
iaddrbusout[6] = 32\'h00000018;
// opcode source1 dest Immediate...
instrbusin[6]={SW, 5\'b00000, 5\'b10101, 16\'h0002};
daddrbusout[6] = 32\'h00000002;
databusin[6] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[6] = 32\'h00000001;
//* ADD R26, R24, R25
iaddrbusout[7] = 32\'h0000001C;
// opcode source1 source2 dest shift Function...
instrbusin[7]={Rformat, 5\'b11000, 5\'b11001, 5\'b11010, 5\'b00000, ADD};
daddrbusout[7] = dontcare;
databusin[7] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[7] = dontcare;
//* SUBI R17, R24, 6420
iaddrbusout[8] = 32\'h00000020;
// opcode source1 dest Immediate...
instrbusin[8]={SUBI, 5\'b11000, 5\'b10001, 16\'h6420};
daddrbusout[8] = dontcare;
databusin[8] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[8] = dontcare;
//* SUB R27, R24, R25
iaddrbusout[9] = 32\'h00000024;
// opcode source1 source2 dest shift Function...
instrbusin[9]={Rformat, 5\'b11000, 5\'b11001, 5\'b11011, 5\'b00000, SUB};
daddrbusout[9] = dontcare;
databusin[9] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[9] = dontcare;
//* ANDI R18, R24, #0
iaddrbusout[10] = 32\'h00000028;
// opcode source1 dest Immediate...
instrbusin[10]={ANDI, 5\'b11000, 5\'b10010, 16\'h0000};
daddrbusout[10] = dontcare;
databusin[10] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[10] = dontcare;
//* AND R28, R24, R0
iaddrbusout[11] = 32\'h0000002C;
// opcode source1 source2 dest shift Function...
instrbusin[11]={Rformat, 5\'b11000, 5\'b00000, 5\'b11100, 5\'b00000, AND};
daddrbusout[11] = dontcare;
databusin[11] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[11] = dontcare;
//* XORI R19, R24, 6420
iaddrbusout[12] = 32\'h00000030;
// opcode source1 dest Immediate...
instrbusin[12]={XORI, 5\'b11000, 5\'b10011, 16\'h6420};
daddrbusout[12] = dontcare;
databusin[12] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[12] = dontcare;
//* XOR R29, R24, R25
iaddrbusout[13] = 32\'h00000034;
// opcode source1 source2 dest shift Function...
instrbusin[13]={Rformat, 5\'b11000, 5\'b11001, 5\'b11101, 5\'b00000, XOR};
daddrbusout[13] = dontcare;
databusin[13] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[13] = dontcare;
//* ORI R20, R24, 6420
iaddrbusout[14] = 32\'h00000038;
// opcode source1 dest Immediate...
instrbusin[14]={ORI, 5\'b11000, 5\'b10100, 16\'h6420};
daddrbusout[14] = dontcare;
databusin[14] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[14] = dontcare;
//* OR R30, R24, R25
iaddrbusout[15] = 32\'h0000003C;
// opcode source1 source2 dest shift Function...
instrbusin[15]={Rformat, 5\'b11000, 5\'b11001, 5\'b11110, 5\'b00000, OR};
daddrbusout[15] = dontcare;
databusin[15] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[15] = dontcare;
//* SW 0(R26), R26
iaddrbusout[16] = 32\'h00000040;
// opcode source1 dest Immediate...
instrbusin[16]={SW, 5\'b11010, 5\'b11010, 16\'h0000};
daddrbusout[16] = 32\'h77777776;
databusin[16] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[16] = 32\'h77777776;
//18* SW 0(R17), R27
iaddrbusout[17] = 32\'h00000044;
// opcode source1 dest Immediate...
instrbusin[17]={SW, 5\'b10001, 5\'b11011, 16\'h0000};
daddrbusout[17] = 32\'hCCCC68AC;
databusin[17] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[17] = 32\'h22222222;
//19* SW 1000(R18), R28
iaddrbusout[18] = 32\'h00000048;
// opcode source1 dest Immediate...
instrbusin[18]={SW, 5\'b10010, 5\'b11100, 16\'h1000};
daddrbusout[18] = 32\'h00001000;
databusin[18] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[18] = 32\'h00000000;
//20* SW 0(R19), R29
iaddrbusout[19] = 32\'h0000004C;
// opcode source1 dest Immediate...
instrbusin[19]={SW, 5\'b10011, 5\'b11101, 16\'h0000};
daddrbusout[19] = 32\'hCCCCA8EC;
databusin[19] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[19] = 32\'h66666666;
//21* SW 0(R20), R30
iaddrbusout[20] = 32\'h00000050;
// opcode source1 dest Immediate...
instrbusin[20]={SW, 5\'b10100, 5\'b11110, 16\'h0000};
daddrbusout[20] = 32\'hCCCCECEC;
databusin[20] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[20] = 32\'hEEEEEEEE;
//22* SLT R1, R0, R21
iaddrbusout[21] = 32\'h00000054;
// opcode source1 source2 dest shift Function...
instrbusin[21]={Rformat, 5\'b00000, 5\'b10101, 5\'b00001, 5\'b00000, SLT};
daddrbusout[21] = dontcare;
databusin[21] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[21] = dontcare;
//* ADDI R5, R0, #1
iaddrbusout[22] = 32\'h00000058;
// opcode source1 dest Immediate...
instrbusin[22]={ADDI, 5\'b00000, 5\'b00101, 16\'h0001};
daddrbusout[22] = dontcare;
databusin[22] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[22] = dontcare;
//* ADDI R6, R0, #1
iaddrbusout[23] = 32\'h0000005C;
// opcode source1 dest Immediate...
instrbusin[23]={ADDI, 5\'b00000, 5\'b00110, 16\'h0001};
daddrbusout[23] = dontcare;
databusin[23] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[23] = dontcare;
//* BNE R0, R1, #10
iaddrbusout[24] = 32\'h00000060;
// opcode source1 dest Immediate...
instrbusin[24]={BNE, 5\'b00001, 5\'b00000, 16\'h000A};
daddrbusout[24] = dontcare;
databusin[24] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[24] = dontcare;
//* ADDI R8, R0, #1
iaddrbusout[25] = 32\'h00000064;
// opcode source1 dest Immediate...
instrbusin[25]={ADDI, 5\'b00000, 5\'b01000, 16\'h0001};
daddrbusout[25] = dontcare;
databusin[25] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[25] = dontcare;
//* SLE R2, R0, R0
iaddrbusout[26] = 32\'h0000008C;
// opcode source1 source2 dest shift Function...
instrbusin[26]={Rformat, 5\'b00000, 5\'b00000, 5\'b00010, 5\'b00000, SLE};
daddrbusout[26] = dontcare;
databusin[26] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[26] = dontcare;
//* NOP
iaddrbusout[27] = 32\'h00000090;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[27] = 32\'b00000000000000000000000000000000;
daddrbusout[27] = dontcare;
databusin[27] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[27] = dontcare;
//* NOP
iaddrbusout[28] = 32\'h00000094;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[28] = 32\'b00000000000000000000000000000000;
daddrbusout[28] = dontcare;
databusin[28] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[28] = dontcare;
//* BEQ R0, R2, #25
iaddrbusout[29] = 32\'h00000098;
// opcode source1 dest Immediate...
instrbusin[29]={BEQ, 5\'b00010, 5\'b00000, 16\'h0019};
daddrbusout[29] = dontcare;
databusin[29] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[29] = dontcare;
//* NOP
iaddrbusout[30] = 32\'h0000009C;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[30] = 32\'b00000000000000000000000000000000;
daddrbusout[30] = dontcare;
databusin[30] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[30] = dontcare;
//* BEQ R2, R2, #10
iaddrbusout[31] = 32\'h000000A0;
// opcode source1 dest Immediate...
instrbusin[31]={BEQ, 5\'b00010, 5\'b00010, 16\'h000A};
daddrbusout[31] = dontcare;
databusin[31] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[31] = dontcare;
//* ADDI R20, R0, #1
iaddrbusout[32] = 32\'h000000A4;
// opcode source1 dest Immediate...
instrbusin[32]={ADDI, 5\'b00000, 5\'b10100, 16\'h0001};
daddrbusout[32] = dontcare;
databusin[32] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[32] = dontcare;
//* NOP
iaddrbusout[33] = 32\'h000000CC;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[33] = 32\'b00000000000000000000000000000000;
daddrbusout[33] = dontcare;
databusin[33] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[33] = dontcare;
//* NOP
iaddrbusout[34] = 32\'h000000D0;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[34] = 32\'b00000000000000000000000000000000;
daddrbusout[34] = dontcare;
databusin[34] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[34] = dontcare;
//* NOP
iaddrbusout[35] = 32\'h000000D4;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[35] = 32\'b00000000000000000000000000000000;
daddrbusout[35] = dontcare;
databusin[35] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[35] = dontcare;
// (no. instructions) + (no. loads) + 2*(no. stores) = 35 + 2 + 2*7 = 51
ntests = 51;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
assign databus = clkd ? 32\'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
databusk = 32\'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
$display ("Time=%t\
clk=%b", $realtime, clk);
for (k=0; k<= 35; k=k+1) begin
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set load data for 3rd previous instruction
if (k >=3)
databusk = databusin[k-3];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check data address from 3rd previous instruction
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check store data from 3rd previous instruction
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
//-----------Declaring time units used in the test module-----------------//
`timescale 1ns/10ps
module regfil_testbench();
//------------------ Ports Declaration-----------------//
reg [31:0] Aselect, Bselect, Dselect;
reg [31:0] dbus;
wire [31:0] abus,bbus;
reg clk;
reg [31:0] dontcare, ref_abus[0:31], ref_bbus[0:31], stm_dbus[0:31], stm_asel[0:31], stm_bsel[0:31], stm_dsel[0:31];
integer error, i, k, ntests;
//----------- Design under test declaration ----------//
regfile dut(.Aselect(Aselect), .Bselect(Bselect), .Dselect(Dselect), .abus(abus), .bbus(bbus), .dbus(dbus), .clk(clk));
\t\t\t\t \t
//---------------EXPECTED VALUES------------------//\t \t //----------------------INPUTS TO REGISTER-------------------//
\t\t \t
initial begin
stm_dsel[0] = 32\'h02000000; stm_dbus[0] = 32\'h76543210;
ref_abus[0] = 32\'h76543210; ref_bbus[0] = 32\'h00000000; stm_asel[0] = 32\'h02000000; stm_bsel[0] = 32\'h00000001;
stm_dsel[1] = 32\'h00001000; stm_dbus[1] = 32\'hF4820000;
ref_abus[1] = 32\'hF4820000; ref_bbus[1] = 32\'h76543210; stm_asel[1] = 32\'h00001000; stm_bsel[1] = 32\'h02000000;
stm_dsel[2] = 32\'h00000001; stm_dbus[2] = 32\'h00001111;
ref_abus[2] = 32\'h00000000; ref_bbus[2] = 32\'h76543210; stm_asel[2] = 32\'h00000001; stm_bsel[2] = 32\'h02000000;
stm_dsel[3] = 32\'h00000040; stm_dbus[3] = 32\'h80876263;
ref_abus[3] = 32\'hF4820000; ref_bbus[3] = 32\'h80876263; stm_asel[3] = 32\'h00001000; stm_bsel[3] = 32\'h00000040;
stm_dsel[4] = 32\'h00040000; stm_dbus[4] = 32\'h10101010;
ref_abus[4] = 32\'h10101010; ref_bbus[4] = 32\'h10101010; stm_asel[4] = 32\'h00040000; stm_bsel[4] = 32\'h00040000;
stm_dsel[5] = 32\'h80000000; stm_dbus[5] = 32\'h33333333;
ref_abus[5] = 32\'hF4820000; ref_bbus[5] = 32\'h76543210; stm_asel[5] = 32\'h00001000; stm_bsel[5] = 32\'h02000000;
stm_dsel[6] = 32\'h00000800; stm_dbus[6] = 32\'h000062DE;
ref_abus[6] = 32\'h000062DE; ref_bbus[6] = 32\'h33333333;\t stm_asel[6] = 32\'h00000800; stm_bsel[6] = 32\'h80000000;
stm_dsel[7] = 32\'h00800000; stm_dbus[7] = 32\'h83848586;
ref_abus[7] = 32\'h80876263; ref_bbus[7] = 32\'h00000000;\t stm_asel[7] = 32\'h00000040; stm_bsel[7] = 32\'h00000001;
stm_dsel[8] = 32\'h00000010; stm_dbus[8] = 32\'h80000000;
ref_abus[8] = 32\'h00000000; ref_bbus[8] = 32\'h83848586;\t stm_asel[8] = 32\'h00000001; stm_bsel[8] = 32\'h00800000;
stm_dsel[9] = 32\'h04000000; stm_dbus[9] = 32\'hFFFFCCCC;
ref_abus[9] = 32\'hFFFFCCCC; ref_bbus[9] = 32\'h80000000;\t stm_asel[9] = 32\'h04000000; stm_bsel[9] = 32\'h00000010;
stm_dsel[10] = 32\'h00004000; stm_dbus[10] = 32\'hF393F393;
ref_abus[10] = 32\'h76543210; ref_bbus[10] = 32\'h10101010; stm_asel[10] = 32\'h02000000; stm_bsel[10] = 32\'h00040000;
stm_dsel[11] = 32\'h00000020; stm_dbus[11] = 32\'h0FEFEFEF;
ref_abus[11] = 32\'h0FEFEFEF; ref_bbus[11] = 32\'hF393F393; stm_asel[11] = 32\'h00000020; stm_bsel[11] = 32\'h00004000;
stm_dsel[12] = 32\'h20000000; stm_dbus[12] = 32\'h09876543;
ref_abus[12] = 32\'h33333333; ref_bbus[12] = 32\'hFFFFCCCC; stm_asel[12] = 32\'h80000000; stm_bsel[12] = 32\'h04000000;
stm_dsel[13] = 32\'h01000000; stm_dbus[13] = 32\'h01234567;
ref_abus[13] = 32\'h000062DE; ref_bbus[13] = 32\'h0FEFEFEF; stm_asel[13] = 32\'h00000800; stm_bsel[13] = 32\'h00000020;
stm_dsel[14] = 32\'h00200000; stm_dbus[14] = 32\'h00000008;
ref_abus[14] = 32\'h09876543; ref_bbus[14] = 32\'h01234567; stm_asel[14] = 32\'h20000000; stm_bsel[14] = 32\'h01000000;
stm_dsel[15] = 32\'h00000100; stm_dbus[15] = 32\'hFFFF0000;
ref_abus[15] = 32\'h80876263; ref_bbus[15] = 32\'h00000008; stm_asel[15] = 32\'h00000040; stm_bsel[15] = 32\'h00200000;
stm_dsel[16] = 32\'h00000008; stm_dbus[16] = 32\'hFFFFFFFF;
ref_abus[16] = 32\'hFFFFFFFF; ref_bbus[16] = 32\'hFFFF0000; stm_asel[16] = 32\'h00000008; stm_bsel[16] = 32\'h00000100;
stm_dsel[17] = 32\'h00010000; stm_dbus[17] = 32\'h0000FEAB;
ref_abus[17] = 32\'h83848586; ref_bbus[17] = 32\'hFFFFFFFF; stm_asel[17] = 32\'h00800000; stm_bsel[17] = 32\'h00000008;
stm_dsel[18] = 32\'h10000000; stm_dbus[18] = 32\'h50600000;
ref_abus[18] = 32\'h0000FEAB; ref_bbus[18] = 32\'h50600000; stm_asel[18] = 32\'h00010000; stm_bsel[18] = 32\'h10000000;
stm_dsel[19] = 32\'h00020000; stm_dbus[19] = 32\'h88887777;
ref_abus[19] = 32\'h88887777; ref_bbus[19] = 32\'h00000000; stm_asel[19] = 32\'h00020000; stm_bsel[19] = 32\'h00000001;
stm_dsel[20] = 32\'h00080000; stm_dbus[20] = 32\'hF0E0D0C0;
ref_abus[20] = 32\'h00000000; ref_bbus[20] = 32\'h00000000; stm_asel[20] = 32\'h00000001; stm_bsel[20] = 32\'h00000001;
stm_dsel[21] = 32\'h00008000; stm_dbus[21] = 32\'hAAAAAAAA;
ref_abus[21] = 32\'h88887777; ref_bbus[21] = 32\'hF0E0D0C0; stm_asel[21] = 32\'h00020000; stm_bsel[21] = 32\'h00080000;
stm_dsel[22] = 32\'h40000000; stm_dbus[22] = 32\'hFDFEFFFF;
ref_abus[22] = 32\'hFDFEFFFF; ref_bbus[22] = 32\'hAAAAAAAA; stm_asel[22] = 32\'h40000000; stm_bsel[22] = 32\'h00008000;
stm_dsel[23] = 32\'h00100000; stm_dbus[23] = 32\'hCCCCFFFF;
ref_abus[23] = 32\'h00000000; ref_bbus[23] = 32\'h00000000; stm_asel[23] = 32\'h00000001; stm_bsel[23] = 32\'h00000001;
stm_dsel[24] = 32\'h00000002; stm_dbus[24] = 32\'hF0F0F0F0;
ref_abus[24] = 32\'hF0F0F0F0; ref_bbus[24] = 32\'hCCCCFFFF; stm_asel[24] = 32\'h00000002; stm_bsel[24] = 32\'h00100000;
stm_dsel[25] = 32\'h00000400; stm_dbus[25] = 32\'hAAAAFFFF;
ref_abus[25] = 32\'hCCCCFFFF; ref_bbus[25] = 32\'hF0F0F0F0; stm_asel[25] = 32\'h00100000; stm_bsel[25] = 32\'h00000002;
stm_dsel[26] = 32\'h08000000; stm_dbus[26] = 32\'hDDDDECFA;
ref_abus[26] = 32\'hDDDDECFA; ref_bbus[26] = 32\'hAAAAFFFF; stm_asel[26] = 32\'h08000000; stm_bsel[26] = 32\'h00000400;
stm_dsel[27] = 32\'h00000004; stm_dbus[27] = 32\'h66666666;
ref_abus[27] = 32\'hFDFEFFFF; ref_bbus[27] = 32\'hF0F0F0F0; stm_asel[27] = 32\'h40000000; stm_bsel[27] = 32\'h00000002;
stm_dsel[28] = 32\'h00000080; stm_dbus[28] = 32\'h0999FFFF;
ref_abus[28] = 32\'h66666666; ref_bbus[28] = 32\'hDDDDECFA; stm_asel[28] = 32\'h00000004; stm_bsel[28] = 32\'h08000000;
stm_dsel[29] = 32\'h00000200; stm_dbus[29] = 32\'hEEEABDCE;
ref_abus[29] = 32\'hF393F393; ref_bbus[29] = 32\'hFFFFFFFF; stm_asel[29] = 32\'h00004000; stm_bsel[29] = 32\'h00000008;
stm_dsel[30] = 32\'h00002000; stm_dbus[30] = 32\'h80808080;
ref_abus[30] = 32\'h0999FFFF; ref_bbus[30] = 32\'hEEEABDCE; stm_asel[30] = 32\'h00000080; stm_bsel[30] = 32\'h00000200;
stm_dsel[31] = 32\'h00400000; stm_dbus[31] = 32\'hABCDEF90;
ref_abus[31] = 32\'hABCDEF90; ref_bbus[31] = 32\'h80808080; stm_asel[31] = 32\'h00400000; stm_bsel[31] = 32\'h00002000;
dontcare = 32\'hx;
ntests = 32;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
clk = 0;
\t #25 ;
\t
for (k=0; k<= 31; k=k+1)
begin
$display("ASSIGNING VALUE TO THE DBUS AND SELECTING DSEL REGISTER TO WRITE VALUE OF DBUS");
clk = 1;
Dselect = stm_dsel[k];
dbus = stm_dbus[k];
$display ("Time=%t \
clk =%b \
Dselect=%b \
dbus=%b \
",$realtime, clk, Dselect, dbus);
#25
$display("TEST READ OPERATION");
clk = 0;
Aselect = stm_asel[k]; Bselect = stm_bsel[k];
$display ("Time=%t \
clk =%b \
Aselect=%b \
Bselect=%b \
",$realtime, clk, Aselect, Bselect);
#20
\t
$display ("Time=%t \
clk =%b \
your abus=%b \
correct abus=%b \
your bbus=%b \
correct bbus=%b \
",$realtime, clk, abus, ref_abus[k], bbus, ref_bbus[k]);
if ( ( (ref_bbus[k] !== bbus) && (ref_bbus[k] !== dontcare) ) || ( (ref_abus[k] !== abus) && (ref_abus[k+1] !== dontcare) ) )
begin
$display ("-------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
$display("END TEST READ OPERATION");
\t
\t #5 ;
end
if ( error !== 0)
begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule |
//phase 6: testing B.EQ and B.NE branch
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:50];
wire [63:0] iaddrbus, daddrbus;
reg [63:0] iaddrbusout[0:50], daddrbusout[0:50];
wire [63:0] databus;
reg [63:0] databusk, databusin[0:50], databusout[0:50];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [24*8:1] iname[0:50];
integer error, k, ntests;
//all opcode parameters to be used
parameter ADD = 11\'b10001011000;
parameter ADDI = 10\'b1001000100;
parameter ADDIS = 10\'b1011000100;
parameter ADDS = 11\'b10101011000;
parameter AND = 11\'b10001010000;
parameter ANDI = 10\'b1001001000;
parameter ANDIS = 10\'b1111001000;
parameter ANDS = 11\'b11101010000;
parameter CBNZ = 8\'b10110101;
parameter CBZ = 8\'b10110100;
parameter EOR = 11\'b11001010000;
parameter EORI = 10\'b1101001000;
parameter LDUR = 11\'b11111000010;
parameter LSL = 11\'b11010011011;
parameter LSR = 11\'b11010011010;
parameter MOVZ = 9\'b110100101;
parameter ORR = 11\'b10101010000;
parameter ORRI = 10\'b1011001000;
parameter STUR = 11\'b11111000000;
parameter SUB = 11\'b11001011000;
parameter SUBI = 10\'b1101000100;
parameter SUBIS = 10\'b1111000100;
parameter SUBS = 11\'b11101011000;
parameter B = 6\'b000101;
parameter B_EQ = 8\'b01010101;
parameter B_NE = 8\'b01010110;
parameter B_LT = 8\'b01010111;
parameter B_GT = 8\'b01011000;
//register parameters
parameter R0 = 5\'b00000;
parameter R15 = 5\'b01111;
parameter R16 = 5\'b10000;
parameter R17 = 5\'b10001;
parameter R18 = 5\'b10010;
parameter R19 = 5\'b10011;
parameter R20 = 5\'b10100;
parameter R21 = 5\'b10101;
parameter R22 = 5\'b10110;
parameter R23 = 5\'b10111;
parameter R24 = 5\'b11000;
parameter R25 = 5\'b11001;
parameter R26 = 5\'b11010;
parameter R27 = 5\'b11011;
parameter R28 = 5\'b11100;
parameter R29 = 5\'b11101;
parameter R30 = 5\'b11110;
parameter R31 = 5\'b11111;
//other parameterz to be used
parameter zeroSham = 6\'b000000;
parameter RX = 5\'b11111;
parameter oneShamt = 6\'b000001;
parameter twoShamt = 6\'b000010;
parameter threeShamt = 6\'b000011;
parameter eightShamt = 6\'b001000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
dontcare = 64\'hx;
//phase 1: testing basic op commands
// op, rd, rn, rm
iname[0] ="ADDI, R20, R31, #AAA";//testing addi, result in R20 = 0000000000000AAA
iaddrbusout[0] = 64\'h00000000;
// opcode rm/ALUImm rn rd
instrbusin[0] ={ADDI, 12\'hAAA, R31, R20};
daddrbusout[0] = dontcare;
databusin[0] = 64\'bz;
databusout[0] = dontcare;
// op, rd, rn, rm
iname[1] ="ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 0000000000000000
iaddrbusout[1] = 64\'h00000004;
// opcode rm/ALUImm rn rd
instrbusin[1] ={ADDI, 12\'h002, R23, R31};
daddrbusout[1] = dontcare;
databusin[1] = 64\'bz;
databusout[1] = dontcare;
// op, rd, rn, rm
iname[2] ="ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 0000000000000002
iaddrbusout[2] = 64\'h00000008;
// opcode rm/ALUImm rn rd
instrbusin[2] ={ADDI, 12\'h002, R23, R0};
daddrbusout[2] = dontcare;
databusin[2] = 64\'bz;
databusout[2] = dontcare;
// op, rd, rn, rm
iname[3] ="ORRI, R21, R24, #001";//testing ori, result in R21 = 0000000000000001
iaddrbusout[3] = 64\'h0000000C;
// opcode rm/ALUImm rn rd
instrbusin[3] ={ORRI, 12\'h001, R24, R21};
daddrbusout[3] = dontcare;
databusin[3] = 64\'bz;
databusout[3] = dontcare;
// op, rd, rn, rm
iname[4] ="EORI, R22, R20, #000";//testing xori, result in R22 = 0000000000000AAA
iaddrbusout[4] = 64\'h00000010;
// opcode rm/ALUImm rn rd
instrbusin[4] ={EORI, 12\'h000, R20, R22};
daddrbusout[4] = dontcare;
databusin[4] = 64\'bz;
databusout[4] = dontcare;
// op, rd, rn, rm
iname[5] ="ANDI, R23, R0, #003";//testing andi, result in R23 = 0000000000000002
iaddrbusout[5] = 64\'h00000014;
// opcode rm/ALUImm rn rd
instrbusin[5] ={ANDI, 12\'h003, R0, R23};
daddrbusout[5] = dontcare;
databusin[5] = 64\'bz;
databusout[5] = dontcare;
// op, rd, rn, rm
iname[6] ="SUBI, R24, R20, #00A";//testing subi, result in R24 = 0000000000000AA0
iaddrbusout[6] = 64\'h00000018;
// opcode rm/ALUImm rn rd
instrbusin[6] ={SUBI, 12\'h00A, R20, R24};
daddrbusout[6] = dontcare;
databusin[6] = 64\'bz;
databusout[6] = dontcare;
// op, rd, rn, rm
iname[7] ="ADD, R25, R20, R0";//testing add, result in R25 = 0000000000000AAC
iaddrbusout[7] = 64\'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7] ={ADD, R0, zeroSham, R20, R25};
daddrbusout[7] = dontcare;
databusin[7] = 64\'bz;
databusout[7] = dontcare;
// op, rd, rn, rm
iname[8] ="AND, R26, R20, R22";//testing and, result in R26 = 0000000000000AAA
iaddrbusout[8] = 64\'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8] ={AND, R22, zeroSham, R20, R26};
daddrbusout[8] = dontcare;
databusin[8] = 64\'bz;
databusout[8] = dontcare;
// op, rd, rn, rm
iname[9] ="EOR, R27, R23, R21";//testing xor, result in R27 = 0000000000000003
iaddrbusout[9] = 64\'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9] ={EOR, R21, zeroSham, R23, R27};
daddrbusout[9] = dontcare;
databusin[9] = 64\'bz;
databusout[9] = dontcare;
// op, rd, rn, rm
iname[10] ="ORR, R28, R25, R23";//testing or, result in R28 = 0000000000000AAE
iaddrbusout[10] = 64\'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10] ={ORR, R23, zeroSham, R25, R28};
daddrbusout[10] = dontcare;
databusin[10] = 64\'bz;
databusout[10] = dontcare;
// op, rd, rn, rm
iname[11] ="SUB, R29, R20, R22";//testing sub, result in R29 = 0000000000000000
iaddrbusout[11] = 64\'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11] ={SUB, R22, zeroSham, R20, R29};
daddrbusout[11] = dontcare;
databusin[11] = 64\'bz;
databusout[11] = dontcare;
// op, rd, rn, aluImm
iname[12] ="ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 0000000000000000
iaddrbusout[12] = 64\'h00000030;
// opcode rm/ALUImm rn rd
instrbusin[12] ={ADDI, 12\'h000, R31, R30};
daddrbusout[12] = dontcare;
databusin[12] = 64\'bz;
databusout[12] = dontcare;
//phase 2: testing basic op codes with the set flags
// op, rd, rn, aluImm
iname[13] ="SUBIS,R20, R0, #003";//testing subis, n flag, result in R20 = FFFFFFFFFFFFFFFF
iaddrbusout[13] = 64\'h00000034;
// opcode rm/ALUImm rn rd
instrbusin[13] ={SUBIS, 12\'h003, R0, R20};
daddrbusout[13] = dontcare;
databusin[13] = 64\'bz;
databusout[13] = dontcare;
// op, rd, rn, rm
iname[14] ="SUBS, R21, R25, R28";//testing subs, n flag, result in R21 = FFFFFFFFFFFFFFFE
iaddrbusout[14] = 64\'h00000038;
// op, rm, shamt, rn, rd
instrbusin[14] ={SUBS,R28,zeroSham, R25, R21};
daddrbusout[14] = dontcare;
databusin[14] = 64\'bz;
databusout[14] = dontcare;
// op, rd, rn, aluImm
iname[15] ="ADDIS,R22, R31, #000";//testing addis, z flag, result in R22 = 0000000000000000
iaddrbusout[15] = 64\'h0000003C;
// opcode rm/ALUImm rn rd
instrbusin[15] ={ADDIS, 12\'h000, R31, R22};
daddrbusout[15] = dontcare;
databusin[15] = 64\'bz;
databusout[15] = dontcare;
// op, rd, rn, rm
iname[16] ="ADDS R23, R20, R23";//testing adds, c flag, result in R23 = 0000000000000001
iaddrbusout[16] = 64\'h00000040;
// op, rm, shamt, rn, rd
instrbusin[16] ={ADDS,R23,zeroSham, R20, R23};
daddrbusout[16] = dontcare;
databusin[16] = 64\'bz;
databusout[16] = dontcare;
// op, rd, rn, aluImm
iname[17] ="ANDIS,R24, R20, #002";//testing andis, reseting n,z flags to low, result in R24 = 0000000000000002
iaddrbusout[17] = 64\'h00000044;
// opcode rm/ALUImm rn rd
instrbusin[17] ={ANDIS, 12\'h002, R20, R24};
daddrbusout[17] = dontcare;
databusin[17] = 64\'bz;
databusout[17] = dontcare;
// op, rd, rn, rm
iname[18] ="ANDS, R25, R21, R20";//testing ands, n flag, result in R25 = FFFFFFFFFFFFFFFE
iaddrbusout[18] = 64\'h00000048;
// op, rm, shamt, rn, rd
instrbusin[18] ={ANDS, R20, zeroSham, R21, R25};
daddrbusout[18] = dontcare;
databusin[18] = 64\'bz;
databusout[18] = dontcare;
//phase 3: testing LSL, LSR
//setting up the register R20 for a test of the LSL
// op, rd, rn, rm
iname[19] ="ADDI, R20, R31, #007";//setting up for left shift, result in R20 = 0000000000000007
iaddrbusout[19] = 64\'h0000004C;
// opcode rm/ALUImm rn rd
instrbusin[19] ={ADDI, 12\'h007, R31, R20};
daddrbusout[19] = dontcare;
databusin[19] = 64\'bz;
databusout[19] = dontcare;
// op, rd, rn, rm
iname[20] ="ADDI, R21, R31, #700";//setting up for right shift, n flag, result in R21 = 0000000000000700
iaddrbusout[20] = 64\'h00000050;
// opcode rm/ALUImm rn rd
instrbusin[20] ={ADDI, 12\'h700, R31, R21};
daddrbusout[20] = dontcare;
databusin[20] = 64\'bz;
databusout[20] = dontcare;
// op, rd, rn, rm
iname[21] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[21] = 64\'h00000054;
// op, rm, shamt, rn, rd
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
daddrbusout[21] = dontcare;
databusin[21] = 64\'bz;
databusout[21] = dontcare;
// op, rd, rn, rm
iname[22] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[22] = 64\'h00000058;
// op, rm, shamt, rn, rd
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
daddrbusout[22] = dontcare;
databusin[22] = 64\'bz;
databusout[22] = dontcare;
// op, rd, rn, rm
iname[23] ="LSL, R20, R20, 2";//testing left shift, result in R20 = 0000000000000700
iaddrbusout[23] = 64\'h0000005C;
// op, rm, shamt, rn, rd
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
daddrbusout[23] = dontcare;
databusin[23] = 64\'bz;
databusout[23] = dontcare;
// op, rd, rn, rm
iname[24] ="LSR, R21, R21, 2";//testing right shift, result in R21 = 0000000000000007
iaddrbusout[24] = 64\'h00000060;
// op, rm, shamt, rn, rd
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
daddrbusout[24] = dontcare;
databusin[24] = 64\'bz;
databusout[24] = dontcare;
//phase 4: testing load and store
// op, rt, rn, DT_adr
iname[25] ="LDUR, R22, R31, #1";//testing load, result in R22 = 42069 (from memory,databusin) [yes, really]
iaddrbusout[25] = 64\'h00000064;
// op, DT_ADDR, ?, rn, rt
instrbusin[25] ={LDUR, 9\'b000000001, 2\'b00, R31, R22};
daddrbusout[25] = 64\'h0000000000000001;//used for LDUR
databusin[25] = 64\'h0000000000042069;//used for LDUR
databusout[25] = dontcare;
// op, rn, DT_adr, rt
iname[26] ="STUR, R23, #068, R24";//testing story, result for databusout in R24 = 0000000000000002 (to memory)
//address is calculated from imm or 68, and R23, which is currently 1
iaddrbusout[26] = 64\'h00000068;
// op, DT_ADDR, ?, rn, rt
instrbusin[26] ={STUR, 9\'b001101000, 2\'b00, R23, R24};
daddrbusout[26] = 64\'h0000000000000069;//used for STUR
databusin[26] = 64\'bz;
databusout[26] = 64\'h0000000000000002;//used for STUR
// op, rd, rn, rm
iname[27] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[27] = 64\'h0000006C;
// op, rm, shamt, rn, rd
instrbusin[27] ={AND, R31, zeroSham, R31, R19};
daddrbusout[27] = dontcare;
databusin[27] = 64\'bz;
databusout[27] = dontcare;
// op, rd, rn, rm
iname[28] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[28] = 64\'h00000070;
// op, rm, shamt, rn, rd
instrbusin[28] ={AND, R31, zeroSham, R31, R19};
daddrbusout[28] = dontcare;
databusin[28] = 64\'bz;
databusout[28] = dontcare;
// op, rd, rn, rm
iname[29] ="AND, R17, R31, R31";//delay, result in R17 = 0000000000000000
iaddrbusout[29] = 64\'h00000074;
// op, rm, shamt, rn, rd
instrbusin[29] ={AND, R31, zeroSham, R31, R19};
daddrbusout[29] = dontcare;
databusin[29] = 64\'bz;
databusout[29] = dontcare;
//phase 5: testing B branch
// op, BR_address
iname[30] ="B, #EA";//testing branch, calculated branch address should be
// (64\'h0000000000000078 + 64\'h000000000000003A8 = 64\'h0000000000000420)
iaddrbusout[30] = 64\'h00000078;
// op, BR_address
instrbusin[30] ={B, 26\'b00000000000000000011101010};
daddrbusout[30] = dontcare;
databusin[30] = 64\'bz;
databusout[30] = dontcare;
// op, rd, rn, rm
iname[31] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[31] = 64\'h0000007C;
// op, rm, shamt, rn, rd
instrbusin[31] ={AND, R31, zeroSham, R31, R19};
daddrbusout[31] = dontcare;
databusin[31] = 64\'bz;
databusout[31] = dontcare;
// op, rd, rn, rm
iname[32] ="ADD, R20, R21, R20";//testing branch address result in R20 = 0000000000000707
iaddrbusout[32] = 64\'h00000420;
// op, rm, shamt, rn, rd
instrbusin[32] ={ADD, R20, zeroSham, R21, R20};
daddrbusout[32] = dontcare;
databusin[32] = 64\'bz;
databusout[32] = dontcare;
//phase 6: testing B.EQ and B.NE branch
// op, rd, rn, rm
iname[33] ="ADDI, R21, R31, #AAA";//testing addi, result in R21 = 0000000000000AAA
iaddrbusout[33] = 64\'h00000424;
// opcode rm/ALUImm rn rd
instrbusin[33] ={ADDI, 12\'hAAA, R31, R21};
daddrbusout[33] = dontcare;
databusin[33] = 64\'bz;
databusout[33] = dontcare;
// op, rd, rn, rm
iname[34] ="ADDI, R22, R31, #AAA";//testing addi, result in R22 = 0000000000000AAA
iaddrbusout[34] = 64\'h00000428;
// opcode rm/ALUImm rn rd
instrbusin[34] ={ADDI, 12\'hAAA, R31, R22};
daddrbusout[34] = dontcare;
databusin[34] = 64\'bz;
databusout[34] = dontcare;
//ADDIS for FAKE BRANCH
// op, rd, rn, aluImm
iname[35] ="ADDIS,R31, R31, #420";//testing fake branch, this should NOT set the Z high
iaddrbusout[35] = 64\'h0000042C;
// opcode rm/ALUImm rn rd
instrbusin[35] ={ADDIS, 12\'h420, R31, R31};
daddrbusout[35] = dontcare;
databusin[35] = 64\'bz;
databusout[35] = dontcare;
//FAKE BRANCH
// op, COND_addr, rt
iname[36] ="B_EQ, #69420, RX";//testing to NOT take the branch, Z should be LOW
iaddrbusout[36] = 64\'h00000430;
// op, COND_addr, rt
instrbusin[36] ={B_EQ, 19\'b1101001010000100000, RX};
daddrbusout[36] = dontcare;
databusin[36] = 64\'bz;
databusout[36] = dontcare;
iname[37] = "NOP";//nada
iaddrbusout[37] = 64\'h00000434;
instrbusin[37] = 64\'b0;
daddrbusout[37] = dontcare;
databusin[37] = 64\'bz;
databusout[37] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[38] ="SUBS, R31, R21, R22";//set z flag for BEQ,
iaddrbusout[38] = 64\'h00000438;
// op, rm, shamt, rn, rd
instrbusin[38] ={SUBS, R22, zeroSham, R21, R31};
daddrbusout[38] = dontcare;
databusin[38] = 64\'bz;
databusout[38] = dontcare;
//real branch for B.EQ (I have the best branches)
// op, COND_addr, rt
iname[39] ="B_EQ, #69, RX";//take the branch to instruction count ?
iaddrbusout[39] = 64\'h0000043C;
// op, COND_addr, rt
instrbusin[39] ={B_EQ, 19\'b0000000000001101001, RX};
//19\'b
daddrbusout[39] = dontcare;
databusin[39] = 64\'bz;
databusout[39] = dontcare;
iname[40] = "NOP";//nada
iaddrbusout[40] = 64\'h00000440;
instrbusin[40] = 64\'b0;
daddrbusout[40] = dontcare;
databusin[40] = 64\'bz;
databusout[40] = dontcare;
iname[41] = "NOP";//nada
iaddrbusout[41] = 64\'h000005E0;
instrbusin[41] = 64\'b0;
daddrbusout[41] = dontcare;
databusin[41] = 64\'bz;
databusout[41] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[42] ="SUBS, R31, R21, R20";//set z flag of NOT for BNE
iaddrbusout[42] = 64\'h000005E4;
// op, rm, shamt, rn, rd
instrbusin[42] ={SUBS, R20, zeroSham, R21, R31};
daddrbusout[42] = dontcare;
databusin[42] = 64\'bz;
databusout[42] = dontcare;
//test B.NE
// op, COND_addr, rt
iname[43] ="B_NE, #96, RX";//take the branch to instruction count 840
iaddrbusout[43] = 64\'h000005E8;
// op, COND_addr, rt
instrbusin[43] ={B_NE, 19\'b0000000000010010110, RX};
daddrbusout[43] = dontcare;
databusin[43] = 64\'bz;
databusout[43] = dontcare;
iname[44] = "NOP";//nada
iaddrbusout[44] = 64\'h000005EC;
instrbusin[44] = 64\'b0;
daddrbusout[44] = dontcare;
databusin[44] = 64\'bz;
databusout[44] = dontcare;
iname[45] = "NOP";//nada
iaddrbusout[45] = 64\'h00000840;
instrbusin[45] = 64\'b0;
daddrbusout[45] = dontcare;
databusin[45] = 64\'bz;
databusout[45] = dontcare;
//finishing up
iname[46] = "NOP";//nada
iaddrbusout[46] = 64\'h00000844;
instrbusin[46] = 64\'b0;
daddrbusout[46] = dontcare;
databusin[46] = 64\'bz;
databusout[46] = dontcare;
iname[47] = "NOP";//nada
iaddrbusout[47] = 64\'h00000848;
instrbusin[47] = 64\'b0;
daddrbusout[47] = dontcare;
databusin[47] = 64\'bz;
databusout[47] = dontcare;
iname[48] = "NOP";//nada
iaddrbusout[48] = 64\'h0000084C;
instrbusin[48] = 64\'b0;
daddrbusout[48] = dontcare;
databusin[48] = 64\'bz;
databusout[48] = dontcare;
iname[49] = "NOP";//nada
iaddrbusout[49] = 64\'h00000850;
instrbusin[49] = 64\'b0;
daddrbusout[49] = dontcare;
databusin[49] = 64\'bz;
databusout[49] = dontcare;
iname[50] = "NOP";//nada
iaddrbusout[50] = 64\'h00000854;
instrbusin[50] = 64\'b0;
daddrbusout[50] = dontcare;
databusin[50] = 64\'bz;
databusout[50] = dontcare;
//remember to set k down below to ntests - 1
ntests = 51;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
assign databus = clkd ? 64\'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
databusk = 64\'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
$display ("Time=%t\
clk=%b", $realtime, clk);
for (k=0; k<= 50; k=k+1) begin
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set load data for 3rd previous instruction
if (k >=3)
databusk = databusin[k-3];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check data address from 3rd previous instruction
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check store data from 3rd previous instruction
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
`timescale 1ns / 1ps
/************************
* Willard Wider
* 6-6-17
* ELEC3725
* alupipe.v
* building a 32 bit ALU
************************/
//the top module, the ALU with piped input and output
module alupipe(S, abus, bbus, clk, Cin, dbus);
input [31:0] abus;
input [31:0] bbus;
input clk;
input [2:0] S;
input Cin;
output [31:0] dbus;
wire [31:0] aInput;//connects register A output to ALU A input
wire [31:0] bInput;//connects register B output to ALU B input
wire [31:0] dInput;//connects register D input to ALU D output
alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));
DflipFlop AFF(.dataIn(abus), .dataOut(aInput), .clk(clk));
DflipFlop BFF(.dataIn(bbus), .dataOut(bInput), .clk(clk));
DflipFlop DFF(.dataIn(dInput), .dataOut(dbus), .clk(clk));
endmodule
//flip flop module. requires a clock cycle to update value
module DflipFlop(dataIn, clk, dataOut);
input [31:0] dataIn;
input clk;
output [31:0] dataOut;
reg [31:0] dataOut;
always @(posedge clk) begin
dataOut = dataIn;
end
endmodule
//Below this point is code from assignment 1//
//The declaration of the entire ALU itself.
module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;//the output bus
output Cout, V;//Cout is the bit for it it needs to carry over to the next circuit/ V is the overflow bit.
input [31:0] a, b;//the two input buses
input Cin;//the bit for marking if it is carrying over from a previous circuit
input [2:0] S;//The select bus. It defines the operation to do with input busses a and b
wire [31:0] c, g, p;
wire gout, pout;
//The core ALU bus
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
//the top Look-Ahead-Carry module.
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
//the overflow module
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule
//The module to handle a single bit operation for the top ALU module
module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule
//The module to handle the overflow bit
module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule
//Look-Ahead Carry unit level 1. Used for the root (level 1) and first child leafs (level 2)
module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule
//Look-Ahead Carry unit level 2. Contains LACs for the root and level 1. Used in level 3
module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 3. Contains LACs for the root and level 2. Used in level 4
module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 4. Contains LACs for the root and level 3. Used in level 5
module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 1. Caontains LACs for the root and level 4. Used in the core alu32 module
module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
|
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:156];
wire [63:0] iaddrbus, daddrbus;
reg [63:0] iaddrbusout[0:156], daddrbusout[0:156];
wire [63:0] databus;
reg [63:0] databusk, databusin[0:156], databusout[0:156];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [24*8:1] iname[0:156];
integer error, k, ntests;
//all opcode parameters to be used
parameter ADD = 11\'b10001011000;
parameter ADDI = 10\'b1001000100;
parameter ADDIS = 10\'b1011000100;
parameter ADDS = 11\'b10101011000;
parameter AND = 11\'b10001010000;
parameter ANDI = 10\'b1001001000;
parameter ANDIS = 10\'b1111001000;
parameter ANDS = 11\'b11101010000;
parameter CBNZ = 8\'b10110101;
parameter CBZ = 8\'b10110100;
parameter EOR = 11\'b11001010000;
parameter EORI = 10\'b1101001000;
parameter LDUR = 11\'b11111000010;
parameter LSL = 11\'b11010011011;
parameter LSR = 11\'b11010011010;
parameter MOVZ = 9\'b110100101;
parameter ORR = 11\'b10101010000;
parameter ORRI = 10\'b1011001000;
parameter STUR = 11\'b11111000000;
parameter SUB = 11\'b11001011000;
parameter SUBI = 10\'b1101000100;
parameter SUBIS = 10\'b1111000100;
parameter SUBS = 11\'b11101011000;
parameter B = 6\'b000101;
parameter B_EQ = 8\'b01010101;
parameter B_NE = 8\'b01010110;
parameter B_LT = 8\'b01010111;
parameter B_GE = 8\'b01011000;
//register parameters
parameter R0 = 5\'b00000;
parameter R15 = 5\'b01111;
parameter R16 = 5\'b10000;
parameter R17 = 5\'b10001;
parameter R18 = 5\'b10010;
parameter R19 = 5\'b10011;
parameter R20 = 5\'b10100;
parameter R21 = 5\'b10101;
parameter R22 = 5\'b10110;
parameter R23 = 5\'b10111;
parameter R24 = 5\'b11000;
parameter R25 = 5\'b11001;
parameter R26 = 5\'b11010;
parameter R27 = 5\'b11011;
parameter R28 = 5\'b11100;
parameter R29 = 5\'b11101;
parameter R30 = 5\'b11110;
parameter R31 = 5\'b11111;
//other parameterz to be used
parameter zeroSham = 6\'b000000;
parameter RX = 5\'b11111;
parameter oneShamt = 6\'b000001;//shifts 1 bit
parameter twoShamt = 6\'b000010;
parameter threeShamt = 6\'b000011;
parameter fourShamt = 6\'b000100;//moves 1 hex place
parameter eightShamt = 6\'b001000;//moves 2 hex place
parameter move_0 = 2\'b00;
parameter move_1 = 2\'b01;
parameter move_2 = 2\'b10;
parameter move_3 = 2\'b11;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
dontcare = 64\'hx;
//phase 1: testing basic op commands
// op, rd, rn, rm
iname[0] ="ADDI, R20, R31, #AAA";//testing addi, result in R20 = 0000000000000AAA
iaddrbusout[0] = 64\'h00000000;
// opcode rm/ALUImm rn rd
instrbusin[0] ={ADDI, 12\'hAAA, R31, R20};
daddrbusout[0] = dontcare;
databusin[0] = 64\'bz;
databusout[0] = dontcare;
// op, rd, rn, rm
iname[1] ="ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 0000000000000000
iaddrbusout[1] = 64\'h00000004;
// opcode rm/ALUImm rn rd
instrbusin[1] ={ADDI, 12\'h002, R23, R31};
daddrbusout[1] = dontcare;
databusin[1] = 64\'bz;
databusout[1] = dontcare;
// op, rd, rn, rm
iname[2] ="ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 0000000000000002
iaddrbusout[2] = 64\'h00000008;
// opcode rm/ALUImm rn rd
instrbusin[2] ={ADDI, 12\'h002, R23, R0};
daddrbusout[2] = dontcare;
databusin[2] = 64\'bz;
databusout[2] = dontcare;
// op, rd, rn, rm
iname[3] ="ORRI, R21, R24, #001";//testing ori, result in R21 = 0000000000000001
iaddrbusout[3] = 64\'h0000000C;
// opcode rm/ALUImm rn rd
instrbusin[3] ={ORRI, 12\'h001, R24, R21};
daddrbusout[3] = dontcare;
databusin[3] = 64\'bz;
databusout[3] = dontcare;
// op, rd, rn, rm
iname[4] ="EORI, R22, R20, #000";//testing xori, result in R22 = 0000000000000AAA
iaddrbusout[4] = 64\'h00000010;
// opcode rm/ALUImm rn rd
instrbusin[4] ={EORI, 12\'h000, R20, R22};
daddrbusout[4] = dontcare;
databusin[4] = 64\'bz;
databusout[4] = dontcare;
// op, rd, rn, rm
iname[5] ="ANDI, R23, R0, #003";//testing andi, result in R23 = 0000000000000002
iaddrbusout[5] = 64\'h00000014;
// opcode rm/ALUImm rn rd
instrbusin[5] ={ANDI, 12\'h003, R0, R23};
daddrbusout[5] = dontcare;
databusin[5] = 64\'bz;
databusout[5] = dontcare;
// op, rd, rn, rm
iname[6] ="SUBI, R24, R20, #00A";//testing subi, result in R24 = 0000000000000AA0
iaddrbusout[6] = 64\'h00000018;
// opcode rm/ALUImm rn rd
instrbusin[6] ={SUBI, 12\'h00A, R20, R24};
daddrbusout[6] = dontcare;
databusin[6] = 64\'bz;
databusout[6] = dontcare;
// op, rd, rn, rm
iname[7] ="ADD, R25, R20, R0";//testing add, result in R25 = 0000000000000AAC
iaddrbusout[7] = 64\'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7] ={ADD, R0, zeroSham, R20, R25};
daddrbusout[7] = dontcare;
databusin[7] = 64\'bz;
databusout[7] = dontcare;
// op, rd, rn, rm
iname[8] ="AND, R26, R20, R22";//testing and, result in R26 = 0000000000000AAA
iaddrbusout[8] = 64\'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8] ={AND, R22, zeroSham, R20, R26};
daddrbusout[8] = dontcare;
databusin[8] = 64\'bz;
databusout[8] = dontcare;
// op, rd, rn, rm
iname[9] ="EOR, R27, R23, R21";//testing xor, result in R27 = 0000000000000003
iaddrbusout[9] = 64\'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9] ={EOR, R21, zeroSham, R23, R27};
daddrbusout[9] = dontcare;
databusin[9] = 64\'bz;
databusout[9] = dontcare;
// op, rd, rn, rm
iname[10] ="ORR, R28, R25, R23";//testing or, result in R28 = 0000000000000AAE
iaddrbusout[10] = 64\'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10] ={ORR, R23, zeroSham, R25, R28};
daddrbusout[10] = dontcare;
databusin[10] = 64\'bz;
databusout[10] = dontcare;
// op, rd, rn, rm
iname[11] ="SUB, R29, R20, R22";//testing sub, result in R29 = 0000000000000000
iaddrbusout[11] = 64\'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11] ={SUB, R22, zeroSham, R20, R29};
daddrbusout[11] = dontcare;
databusin[11] = 64\'bz;
databusout[11] = dontcare;
// op, rd, rn, aluImm
iname[12] ="ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 0000000000000000
iaddrbusout[12] = 64\'h00000030;
// opcode rm/ALUImm rn rd
instrbusin[12] ={ADDI, 12\'h000, R31, R30};
daddrbusout[12] = dontcare;
databusin[12] = 64\'bz;
databusout[12] = dontcare;
//phase 2: testing basic op codes with the set flags
// op, rd, rn, aluImm
iname[13] ="SUBIS,R20, R0, #003";//testing subis, n flag, result in R20 = FFFFFFFFFFFFFFFF
iaddrbusout[13] = 64\'h00000034;
// opcode rm/ALUImm rn rd
instrbusin[13] ={SUBIS, 12\'h003, R0, R20};
daddrbusout[13] = dontcare;
databusin[13] = 64\'bz;
databusout[13] = dontcare;
// op, rd, rn, rm
iname[14] ="SUBS, R21, R25, R28";//testing subs, n flag, result in R21 = FFFFFFFFFFFFFFFE
iaddrbusout[14] = 64\'h00000038;
// op, rm, shamt, rn, rd
instrbusin[14] ={SUBS,R28,zeroSham, R25, R21};
daddrbusout[14] = dontcare;
databusin[14] = 64\'bz;
databusout[14] = dontcare;
// op, rd, rn, aluImm
iname[15] ="ADDIS,R22, R31, #000";//testing addis, z flag, result in R22 = 0000000000000000
iaddrbusout[15] = 64\'h0000003C;
// opcode rm/ALUImm rn rd
instrbusin[15] ={ADDIS, 12\'h000, R31, R22};
daddrbusout[15] = dontcare;
databusin[15] = 64\'bz;
databusout[15] = dontcare;
// op, rd, rn, rm
iname[16] ="ADDS R23, R20, R23";//testing adds, c flag, result in R23 = 0000000000000001
iaddrbusout[16] = 64\'h00000040;
// op, rm, shamt, rn, rd
instrbusin[16] ={ADDS,R23,zeroSham, R20, R23};
daddrbusout[16] = dontcare;
databusin[16] = 64\'bz;
databusout[16] = dontcare;
// op, rd, rn, aluImm
iname[17] ="ANDIS,R24, R20, #002";//testing andis, reseting n,z flags to low, result in R24 = 0000000000000002
iaddrbusout[17] = 64\'h00000044;
// opcode rm/ALUImm rn rd
instrbusin[17] ={ANDIS, 12\'h002, R20, R24};
daddrbusout[17] = dontcare;
databusin[17] = 64\'bz;
databusout[17] = dontcare;
// op, rd, rn, rm
iname[18] ="ANDS, R25, R21, R20";//testing ands, n flag, result in R25 = FFFFFFFFFFFFFFFE
iaddrbusout[18] = 64\'h00000048;
// op, rm, shamt, rn, rd
instrbusin[18] ={ANDS, R20, zeroSham, R21, R25};
daddrbusout[18] = dontcare;
databusin[18] = 64\'bz;
databusout[18] = dontcare;
//phase 3: testing LSL, LSR
//setting up the register R20 for a test of the LSL
// op, rd, rn, rm
iname[19] ="ADDI, R20, R31, #007";//setting up for left shift, result in R20 = 0000000000000007
iaddrbusout[19] = 64\'h0000004C;
// opcode rm/ALUImm rn rd
instrbusin[19] ={ADDI, 12\'h007, R31, R20};
daddrbusout[19] = dontcare;
databusin[19] = 64\'bz;
databusout[19] = dontcare;
// op, rd, rn, rm
iname[20] ="ADDI, R21, R31, #700";//setting up for right shift, n flag, result in R21 = 0000000000000700
iaddrbusout[20] = 64\'h00000050;
// opcode rm/ALUImm rn rd
instrbusin[20] ={ADDI, 12\'h700, R31, R21};
daddrbusout[20] = dontcare;
databusin[20] = 64\'bz;
databusout[20] = dontcare;
// op, rd, rn, rm
iname[21] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[21] = 64\'h00000054;
// op, rm, shamt, rn, rd
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
daddrbusout[21] = dontcare;
databusin[21] = 64\'bz;
databusout[21] = dontcare;
// op, rd, rn, rm
iname[22] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[22] = 64\'h00000058;
// op, rm, shamt, rn, rd
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
daddrbusout[22] = dontcare;
databusin[22] = 64\'bz;
databusout[22] = dontcare;
// op, rd, rn, shamt
iname[23] ="LSL, R20, R20, #2";//testing left shift, result in R20 = 0000000000000700
iaddrbusout[23] = 64\'h0000005C;
// op, rm, shamt, rn, rd
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
daddrbusout[23] = dontcare;
databusin[23] = 64\'bz;
databusout[23] = dontcare;
// op, rd, rn, shamt
iname[24] ="LSR, R21, R21, #2";//testing right shift, result in R21 = 0000000000000007
iaddrbusout[24] = 64\'h00000060;
// op, rm, shamt, rn, rd
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
daddrbusout[24] = dontcare;
databusin[24] = 64\'bz;
databusout[24] = dontcare;
//phase 4: testing load and store and overflow bit
// op, rt, rn, DT_adr
iname[25] ="LDUR, R22, R31, #1";//testing load, result in R22 = 42069 (from memory,databusin) [yes, really]
iaddrbusout[25] = 64\'h00000064;
// op, DT_ADDR, ?, rn, rt
instrbusin[25] ={LDUR, 9\'b000000001, 2\'b00, R31, R22};
daddrbusout[25] = 64\'h0000000000000001;//used for LDUR
databusin[25] = 64\'h0000000000042069;//used for LDUR
databusout[25] = dontcare;
// op, rn, DT_adr, rt
iname[26] ="STUR, R23, #068, R24";//testing story, result for databusout in R24 = 0000000000000002 (to memory)
//address is calculated from imm or 68, and R23, which is currently 1
iaddrbusout[26] = 64\'h00000068;
// op, DT_ADDR, ?, rn, rt
instrbusin[26] ={STUR, 9\'b001101000, 2\'b00, R23, R24};
daddrbusout[26] = 64\'h0000000000000069;//used for STUR
databusin[26] = 64\'bz;
databusout[26] = 64\'h0000000000000002;//used for STUR
// op, rd, rn, rm
iname[27] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[27] = 64\'h0000006C;
// op, rm, shamt, rn, rd
instrbusin[27] ={AND, R31, zeroSham, R31, R19};
daddrbusout[27] = dontcare;
databusin[27] = 64\'bz;
databusout[27] = dontcare;
// op, rd, rn, rm
iname[28] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[28] = 64\'h00000070;
// op, rm, shamt, rn, rd
instrbusin[28] ={AND, R31, zeroSham, R31, R19};
daddrbusout[28] = dontcare;
databusin[28] = 64\'bz;
databusout[28] = dontcare;
// op, rd, rn, rm
iname[29] ="AND, R17, R31, R31";//delay, result in R17 = 0000000000000000
iaddrbusout[29] = 64\'h00000074;
// op, rm, shamt, rn, rd
instrbusin[29] ={AND, R31, zeroSham, R31, R19};
daddrbusout[29] = dontcare;
databusin[29] = 64\'bz;
databusout[29] = dontcare;
//phase 5: testing B branch
// op, BR_address
iname[30] ="B, #EA";//testing branch, calculated branch address should be
// (64\'h0000000000000078 + 64\'h000000000000003A8 = 64\'h0000000000000420)
iaddrbusout[30] = 64\'h00000078;
// op, BR_address
instrbusin[30] ={B, 26\'b00000000000000000011101010};
daddrbusout[30] = dontcare;
databusin[30] = 64\'bz;
databusout[30] = dontcare;
// op, rd, rn, rm
iname[31] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[31] = 64\'h0000007C;
// op, rm, shamt, rn, rd
instrbusin[31] ={AND, R31, zeroSham, R31, R19};
daddrbusout[31] = dontcare;
databusin[31] = 64\'bz;
databusout[31] = dontcare;
// op, rd, rn, rm
iname[32] ="ADD, R20, R21, R20";//testing branch address result in R20 = 0000000000000707
iaddrbusout[32] = 64\'h00000420;
// op, rm, shamt, rn, rd
instrbusin[32] ={ADD, R20, zeroSham, R21, R20};
daddrbusout[32] = dontcare;
databusin[32] = 64\'bz;
databusout[32] = dontcare;
//phase 6: testing B.EQ and B.NE branch
// op, rd, rn, rm
iname[33] ="ADDI, R21, R31, #AAA";//testing addi, result in R21 = 0000000000000AAA
iaddrbusout[33] = 64\'h00000424;
// opcode rm/ALUImm rn rd
instrbusin[33] ={ADDI, 12\'hAAA, R31, R21};
daddrbusout[33] = dontcare;
databusin[33] = 64\'bz;
databusout[33] = dontcare;
// op, rd, rn, rm
iname[34] ="ADDI, R22, R31, #AAA";//testing addi, result in R22 = 0000000000000AAA
iaddrbusout[34] = 64\'h00000428;
// opcode rm/ALUImm rn rd
instrbusin[34] ={ADDI, 12\'hAAA, R31, R22};
daddrbusout[34] = dontcare;
databusin[34] = 64\'bz;
databusout[34] = dontcare;
//ADDIS for FAKE BRANCH
// op, rd, rn, aluImm
iname[35] ="ADDIS,R31, R31, #420";//testing fake branch, this should NOT set the Z high
iaddrbusout[35] = 64\'h0000042C;
// opcode rm/ALUImm rn rd
instrbusin[35] ={ADDIS, 12\'h420, R31, R31};
daddrbusout[35] = dontcare;
databusin[35] = 64\'bz;
databusout[35] = dontcare;
//FAKE BRANCH
// op, COND_addr, rt
iname[36] ="B_EQ, #69420, RX";//testing to NOT take the branch, Z should be LOW
iaddrbusout[36] = 64\'h00000430;
// op, COND_addr, rt
instrbusin[36] ={B_EQ, 19\'b1101001010000100000, RX};
daddrbusout[36] = dontcare;
databusin[36] = 64\'bz;
databusout[36] = dontcare;
iname[37] = "NOP";//nada
iaddrbusout[37] = 64\'h00000434;
instrbusin[37] = 64\'b0;
daddrbusout[37] = dontcare;
databusin[37] = 64\'bz;
databusout[37] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[38] ="SUBS, R31, R21, R22";//set z flag for BEQ,
iaddrbusout[38] = 64\'h00000438;
// op, rm, shamt, rn, rd
instrbusin[38] ={SUBS, R22, zeroSham, R21, R31};
daddrbusout[38] = dontcare;
databusin[38] = 64\'bz;
databusout[38] = dontcare;
//real branch for B.EQ (I have the best branches)
// op, COND_addr, rt
iname[39] ="B_EQ, #69, RX";//take the branch to instruction count 440
iaddrbusout[39] = 64\'h0000043C;
// op, COND_addr, rt
instrbusin[39] ={B_EQ, 19\'b0000000000001101001, RX};
//19\'b
daddrbusout[39] = dontcare;
databusin[39] = 64\'bz;
databusout[39] = dontcare;
iname[40] = "NOP";//nada
iaddrbusout[40] = 64\'h00000440;
instrbusin[40] = 64\'b0;
daddrbusout[40] = dontcare;
databusin[40] = 64\'bz;
databusout[40] = dontcare;
iname[41] = "NOP";//nada
iaddrbusout[41] = 64\'h000005E0;
instrbusin[41] = 64\'b0;
daddrbusout[41] = dontcare;
databusin[41] = 64\'bz;
databusout[41] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[42] ="SUBS, R31, R21, R20";//set z flag of NOT for BNE
iaddrbusout[42] = 64\'h000005E4;
// op, rm, shamt, rn, rd
instrbusin[42] ={SUBS, R20, zeroSham, R21, R31};
daddrbusout[42] = dontcare;
databusin[42] = 64\'bz;
databusout[42] = dontcare;
//test B.NE
// op, COND_addr, rt
iname[43] ="B_NE, #96, RX";//take the branch to instruction count 840
iaddrbusout[43] = 64\'h000005E8;
// op, COND_addr, rt
instrbusin[43] ={B_NE, 19\'b0000000000010010110, RX};
daddrbusout[43] = dontcare;
databusin[43] = 64\'bz;
databusout[43] = dontcare;
iname[44] = "NOP";//nada
iaddrbusout[44] = 64\'h000005EC;
instrbusin[44] = 64\'b0;
daddrbusout[44] = dontcare;
databusin[44] = 64\'bz;
databusout[44] = dontcare;
iname[45] = "NOP";//nada
iaddrbusout[45] = 64\'h00000840;
instrbusin[45] = 64\'b0;
daddrbusout[45] = dontcare;
databusin[45] = 64\'bz;
databusout[45] = dontcare;
//phase 7: testing CBNZ and CBZ branch
//DONT take the CBZ
// op, COND_addr, rt
iname[46] ="CBZ, #F, R22";//take the branch to instruction count
iaddrbusout[46] = 64\'h00000844;
// op, COND_addr, rt
instrbusin[46] ={CBZ, 19\'b0000000000000001111, R22};
daddrbusout[46] = dontcare;
databusin[46] = 64\'bz;
databusout[46] = dontcare;
iname[47] = "NOP";//nada
iaddrbusout[47] = 64\'h00000848;
instrbusin[47] = 64\'b0;
daddrbusout[47] = dontcare;
databusin[47] = 64\'bz;
databusout[47] = dontcare;
iname[48] = "NOP";//nada
iaddrbusout[48] = 64\'h0000084C;
instrbusin[48] = 64\'b0;
daddrbusout[48] = dontcare;
databusin[48] = 64\'bz;
databusout[48] = dontcare;
//TAKE the CBZ
// op, COND_addr, rt
iname[49] ="CBZ, #21, R19";//take the branch to instruction count
iaddrbusout[49] = 64\'h00000850;
// op, COND_addr, rt
instrbusin[49] ={CBZ, 19\'b0000000000000100001, R19};
daddrbusout[49] = dontcare;
databusin[49] = 64\'bz;
databusout[49] = dontcare;
iname[50] = "NOP";//nada
iaddrbusout[50] = 64\'h00000854;
instrbusin[50] = 64\'b0;
daddrbusout[50] = dontcare;
databusin[50] = 64\'bz;
databusout[50] = dontcare;
iname[51] = "NOP";//nada
iaddrbusout[51] = 64\'h000008D4;
instrbusin[51] = 64\'b0;
daddrbusout[51] = dontcare;
databusin[51] = 64\'bz;
databusout[51] = dontcare;
//DONT take the CBNZ
// op, COND_addr, rt
iname[52] ="CBNZ, #FF, R31";//take the branch to instruction count
iaddrbusout[52] = 64\'h000008D8;
// op, COND_addr, rt
instrbusin[52] ={CBNZ, 19\'b0000000000011111111, R31};
daddrbusout[52] = dontcare;
databusin[52] = 64\'bz;
databusout[52] = dontcare;
iname[53] = "NOP";//nada
iaddrbusout[53] = 64\'h000008DC;
instrbusin[53] = 64\'b0;
daddrbusout[53] = dontcare;
databusin[53] = 64\'bz;
databusout[53] = dontcare;
iname[54] = "NOP";//nada
iaddrbusout[54] = 64\'h000008E0;
instrbusin[54] = 64\'b0;
daddrbusout[54] = dontcare;
databusin[54] = 64\'bz;
databusout[54] = dontcare;
//TAKE the CBNZ
// op, COND_addr, rt
iname[55] ="CBNZ, #22, R20";//take the branch to instruction count
iaddrbusout[55] = 64\'h000008E4;
// op, COND_addr, rt
instrbusin[55] ={CBNZ, 19\'b0000000000000100010, R20};
daddrbusout[55] = dontcare;
databusin[55] = 64\'bz;
databusout[55] = dontcare;
iname[56] = "NOP";//nada
iaddrbusout[56] = 64\'h000008E8;
instrbusin[56] = 64\'b0;
daddrbusout[56] = dontcare;
databusin[56] = 64\'bz;
databusout[56] = dontcare;
iname[57] = "NOP";//nada
iaddrbusout[57] = 64\'h0000096C;
instrbusin[57] = 64\'b0;
daddrbusout[57] = dontcare;
databusin[57] = 64\'bz;
databusout[57] = dontcare;
//phase 8: testing MOVEZ and overflow bit
//4 instructions to set registers to 0
// op, rd, rn, rm
iname[58] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[58] = 64\'h00000970;
// op, rm, shamt, rn, rd
instrbusin[58] ={AND, R31, zeroSham, R31, R19};
daddrbusout[58] = dontcare;
databusin[58] = 64\'bz;
databusout[58] = dontcare;
// op, rd, rn, rm
iname[59] ="AND, R20, R31, R31";//delay, result in R20 = 0000000000000000
iaddrbusout[59] = 64\'h00000974;
// op, rm, shamt, rn, rd
instrbusin[59] ={AND, R31, zeroSham, R31, R20};
daddrbusout[59] = dontcare;
databusin[59] = 64\'bz;
databusout[59] = dontcare;
// op, rd, rn, rm
iname[60] ="AND, R21, R31, R31";//delay, result in R21 = 0000000000000000
iaddrbusout[60] = 64\'h00000978;
// op, rm, shamt, rn, rd
instrbusin[60] ={AND, R31, zeroSham, R31, R21};
daddrbusout[60] = dontcare;
databusin[60] = 64\'bz;
databusout[60] = dontcare;
// op, rd, rn, rm
iname[61] ="AND, R22, R31, R31";//delay, result in R22 = 0000000000000000
iaddrbusout[61] = 64\'h0000097C;
// op, rm, shamt, rn, rd
instrbusin[61] ={AND, R31, zeroSham, R31, R22};
daddrbusout[61] = dontcare;
databusin[61] = 64\'bz;
databusout[61] = dontcare;
//4 MOVZ commands
//move 0 amt
// op, move_amt, MOV_imm, rd
iname[62] ="MOVZ, move_0, #FFFF, R19";//testing move, result in R19 = 000000000000FFFF
iaddrbusout[62] = 64\'h00000980;
// op, move_amt, MOV_imm, rd
instrbusin[62] ={MOVZ, move_0, 16\'hFFFF, R19};
daddrbusout[62] = dontcare;
databusin[62] = 64\'bz;
databusout[62] = dontcare;
//move 1 amt
// op, move_amt, MOV_imm, rd
iname[63] ="MOVZ, move_1, #FFFF, R20";//testing move, result in R20 = 00000000FFFF0000
iaddrbusout[63] = 64\'h00000984;
// op, move_amt, MOV_imm, rd
instrbusin[63] ={MOVZ, move_1, 16\'hFFFF, R20};
daddrbusout[63] = dontcare;
databusin[63] = 64\'bz;
databusout[63] = dontcare;
//move 2 amt
// op, move_amt, MOV_imm, rd
iname[64] ="MOVZ, move_2, #FFFF, R21";//testing move, result in R21 = 0000FFFF00000000
iaddrbusout[64] = 64\'h00000988;
// op, move_amt, MOV_imm, rd
instrbusin[64] ={MOVZ, move_2, 16\'hFFFF, R21};
daddrbusout[64] = dontcare;
databusin[64] = 64\'bz;
databusout[64] = dontcare;
//move 3 amt
// op, move_amt, MOV_imm, rd
iname[65] ="MOVZ, move_3, #7FFF, R22";//testing move, result in R22 = 7FFF000000000000
iaddrbusout[65] = 64\'h0000098C;
// op, move_amt, MOV_imm, rd
instrbusin[65] ={MOVZ, move_3, 16\'h7FFF, R22};
daddrbusout[65] = dontcare;
databusin[65] = 64\'bz;
databusout[65] = dontcare;
//have or for move 0 and move 1
// op, rd, rn, rm
iname[66] ="ORR, R23, R19, R20";//testing xor, result in R23 = 00000000FFFFFFFF
iaddrbusout[66] = 64\'h00000990;
// op, rm, shamt, rn, rd
instrbusin[66] ={ORR, R20, zeroSham, R19, R23};
daddrbusout[66] = dontcare;
databusin[66] = 64\'bz;
databusout[66] = dontcare;
//delay
iname[67] = "NOP";//nada
iaddrbusout[67] = 64\'h00000994;
instrbusin[67] = 64\'b0;
daddrbusout[67] = dontcare;
databusin[67] = 64\'bz;
databusout[67] = dontcare;
//have or for move 2 and move 3
// op, rd, rn, rm
iname[68] ="ORR, R24, R21, R22";//testing xor, result in R27 = 7FFFFFFF00000000
iaddrbusout[68] = 64\'h00000998;
// op, rm, shamt, rn, rd
instrbusin[68] ={ORR, R22, zeroSham, R21, R24};
daddrbusout[68] = dontcare;
databusin[68] = 64\'bz;
databusout[68] = dontcare;
//delay
iname[69] = "NOP";//nada
iaddrbusout[69] = 64\'h0000099C;
instrbusin[69] = 64\'b0;
daddrbusout[69] = dontcare;
databusin[69] = 64\'bz;
databusout[69] = dontcare;
//delay
iname[70] = "NOP";//nada
iaddrbusout[70] = 64\'h000009A0;
instrbusin[70] = 64\'b0;
daddrbusout[70] = dontcare;
databusin[70] = 64\'bz;
databusout[70] = dontcare;
//have or for move(0|1) and move(2|3)
// op, rd, rn, rm
iname[71] ="ORR, R25, R23, R24";//testing xor, result in R25 = 7FFFFFFFFFFFFFFF
iaddrbusout[71] = 64\'h000009A4;
// op, rm, shamt, rn, rd
instrbusin[71] ={ORR, R24, zeroSham, R23, R25};
daddrbusout[71] = dontcare;
databusin[71] = 64\'bz;
databusout[71] = dontcare;
//dealy
iname[72] = "NOP";//nada
iaddrbusout[72] = 64\'h000009A8;
instrbusin[72] = 64\'b0;
daddrbusout[72] = dontcare;
databusin[72] = 64\'bz;
databusout[72] = dontcare;
//delay
iname[73] = "NOP";//nada
iaddrbusout[73] = 64\'h000009AC;
instrbusin[73] = 64\'b0;
daddrbusout[73] = dontcare;
databusin[73] = 64\'bz;
databusout[73] = dontcare;
//addis command to trigger the V bit
// op, rd, rn, aluImm
iname[74] ="ADDIS,R26, R25, #001";//testing xor and V bit and N bit, result in R26 = 8000000000000000
iaddrbusout[74] = 64\'h000009B0;
// opcode rm/ALUImm rn rd
instrbusin[74] ={ADDIS, 12\'h001, R25, R26};
daddrbusout[74] = dontcare;
databusin[74] = 64\'bz;
databusout[74] = dontcare;
iname[75] = "NOP";//nada
iaddrbusout[75] = 64\'h000009B4;
instrbusin[75] = 64\'b0;
daddrbusout[75] = dontcare;
databusin[75] = 64\'bz;
databusout[75] = dontcare;
iname[76] = "NOP";//nada
iaddrbusout[76] = 64\'h000009B8;
instrbusin[76] = 64\'b0;
daddrbusout[76] = dontcare;
databusin[76] = 64\'bz;
databusout[76] = dontcare;
//phase 9: testing B.LT and B.GE branch
//7FFF+1 = N and V, 8000-1 = V
//use SUBIS for the branch condition test (B.LT test)
// op, rd, rn, aluImm
iname[77] ="SUBIS,R26, R26, #001";//result in R26 = 7FFFFFFFFFFFFFFF
iaddrbusout[77] = 64\'h000009BC;
// opcode rm/ALUImm rn rd
instrbusin[77] ={SUBIS, 12\'h001, R26, R26};
daddrbusout[77] = dontcare;
databusin[77] = 64\'bz;
databusout[77] = dontcare;
//TAKE branch
// op, COND_addr, rt
iname[78] ="B_LT, #42, RX";//new branch address is AC8
iaddrbusout[78] = 64\'h000009C0;
// op, COND_addr, rt
instrbusin[78] ={B_LT, 19\'b0000000000001000010, RX};
daddrbusout[78] = dontcare;
databusin[78] = 64\'bz;
databusout[78] = dontcare;
//delay
iname[79] = "NOP";//nada
iaddrbusout[79] = 64\'h000009C4;
instrbusin[79] = 64\'b0;
daddrbusout[79] = dontcare;
databusin[79] = 64\'bz;
databusout[79] = dontcare;
//delay
iname[80] = "NOP";//nada
iaddrbusout[80] = 64\'h00000AC8;
instrbusin[80] = 64\'b0;
daddrbusout[80] = dontcare;
databusin[80] = 64\'bz;
databusout[80] = dontcare;
//use ADDIS for the branch condition test B.GE test
// op, rd, rn, aluImm
iname[81] ="ADDIS,R26, R26, #001";//result in R26 = 8000000000000000
iaddrbusout[81] = 64\'h00000ACC;
// opcode rm/ALUImm rn rd
instrbusin[81] ={ADDIS, 12\'h001, R26, R26};
daddrbusout[81] = dontcare;
databusin[81] = 64\'bz;
databusout[81] = dontcare;
//TAKE branch
// op, COND_addr, rt
iname[82] ="B_GE, #24, RX";//new branch address is B60
iaddrbusout[82] = 64\'h00000AD0;
// op, COND_addr, rt
instrbusin[82] ={B_GE, 19\'b0000000000000100100, RX};
daddrbusout[82] = dontcare;
databusin[82] = 64\'bz;
databusout[82] = dontcare;
//delay
iname[83] = "NOP";//nada
iaddrbusout[83] = 64\'h00000AD4;
instrbusin[83] = 64\'b0;
daddrbusout[83] = dontcare;
databusin[83] = 64\'bz;
databusout[83] = dontcare;
//delay
iname[84] = "NOP";//nada
iaddrbusout[84] = 64\'h00000B60;
instrbusin[84] = 64\'b0;
daddrbusout[84] = dontcare;
databusin[84] = 64\'bz;
databusout[84] = dontcare;
//finishing up
iname[85] = "NOP";//nada
iaddrbusout[85] = 64\'h00000B64;
instrbusin[85] = 64\'b0;
daddrbusout[85] = dontcare;
databusin[85] = 64\'bz;
databusout[85] = dontcare;
iname[86] = "NOP";//nada
iaddrbusout[86] = 64\'h00000B68;
instrbusin[86] = 64\'b0;
daddrbusout[86] = dontcare;
databusin[86] = 64\'bz;
databusout[86] = dontcare;
iname[87] = "NOP";//nada
iaddrbusout[87] = 64\'h00000B6C;
instrbusin[87] = 64\'b0;
daddrbusout[87] = dontcare;
databusin[87] = 64\'bz;
databusout[87] = dontcare;
//done with testing: 88 instructions
//bonus round
//copy of phase 3
//phase 3: testing LSL, LSR
//setting up the register R20 for a test of the LSL
// op, rd, rn, rm
iname[88] ="ADDI, R20, R31, #640";//setting up for left shift, result in R20 = 0000000000000640
iaddrbusout[88] = 64\'h00000B70;
// opcode rm/ALUImm rn rd
instrbusin[88] ={ADDI, 12\'h007, R31, R20};
daddrbusout[88] = dontcare;
databusin[88] = 64\'bz;
databusout[88] = dontcare;
// op, rd, rn, rm
iname[89] ="ADDI, R21, R31, #480";//setting up for right shift, n flag, result in R21 = 0000000000000480
iaddrbusout[89] = 64\'h00000B74;
// opcode rm/ALUImm rn rd
instrbusin[89] ={ADDI, 12\'h700, R31, R21};
daddrbusout[89] = dontcare;
databusin[89] = 64\'bz;
databusout[89] = dontcare;
// op, rd, rn, rm
iname[90] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[90] = 64\'h00000B78;
// op, rm, shamt, rn, rd
instrbusin[90] ={AND, R31, zeroSham, R31, R19};
daddrbusout[90] = dontcare;
databusin[90] = 64\'bz;
databusout[90] = dontcare;
// op, rd, rn, rm
iname[91] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[91] = 64\'h00000B7C;
// op, rm, shamt, rn, rd
instrbusin[91] ={AND, R31, zeroSham, R31, R18};
daddrbusout[91] = dontcare;
databusin[91] = 64\'bz;
databusout[91] = dontcare;
// op, rd, rn, rm
iname[92] ="LSL, R20, R20, #1";//testing left shift, result in R20 = 0000000000006400
iaddrbusout[92] = 64\'h00000B80;
// op, rm, shamt, rn, rd
instrbusin[92] ={LSL, RX, fourShamt, R20, R20};
daddrbusout[92] = dontcare;
databusin[92] = 64\'bz;
databusout[92] = dontcare;
// op, rd, rn, rm
iname[93] ="LSR, R21, R21, #1";//testing right shift, result in R21 = 0000000000000048
iaddrbusout[93] = 64\'h00000B84;
// op, rm, shamt, rn, rd
instrbusin[93] ={LSR, RX, fourShamt, R21, R21};
daddrbusout[93] = dontcare;
databusin[93] = 64\'bz;
databusout[93] = dontcare;
//phase 4: testing load and store
// op, rt, rn, DT_adr
iname[94] ="LDUR, R22, R31, #27";//testing load, result in R22 = 666 (from memory,databusin)
iaddrbusout[94] = 64\'h00000B88;
// op, DT_ADDR, ?, rn, rt
instrbusin[94] ={LDUR, 9\'b000100111, 2\'b00, R31, R22};
daddrbusout[94] = 64\'h0000000000000027;//used for LDUR
databusin[94] = 64\'h0000000000000666;//used for LDUR
databusout[94] = dontcare;
// op, rn, DT_adr, rt
iname[95] ="STUR, R26, #21, R26";//testing store, result for databusout in R26 = 8000000000000000 (to memory)
//R20, + 21 = 6421
iaddrbusout[95] = 64\'h00000B8C;
// op, DT_ADDR, ?, rn, rt
instrbusin[95] ={STUR, 9\'b000100001, 2\'b00, R26, R26};
daddrbusout[95] = 64\'h8000000000000021;//used for STUR
databusin[95] = 64\'bz;
databusout[95] = 64\'h8000000000000000;//used for STUR
// op, rd, rn, rm
iname[96] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[96] = 64\'h00000B90;
// op, rm, shamt, rn, rd
instrbusin[96] ={AND, R31, zeroSham, R31, R19};
daddrbusout[96] = dontcare;
databusin[96] = 64\'bz;
databusout[96] = dontcare;
// op, rd, rn, rm
iname[97] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[97] = 64\'h00000B94;
// op, rm, shamt, rn, rd
instrbusin[97] ={AND, R31, zeroSham, R31, R19};
daddrbusout[97] = dontcare;
databusin[97] = 64\'bz;
databusout[97] = dontcare;
// op, rd, rn, rm
iname[98] ="AND, R17, R31, R31";//delay, result in R17 = 0000000000000000
iaddrbusout[98] = 64\'h00000B98;
// op, rm, shamt, rn, rd
instrbusin[98] ={AND, R31, zeroSham, R31, R19};
daddrbusout[98] = dontcare;
databusin[98] = 64\'bz;
databusout[98] = dontcare;
//phase 5: testing B branch
// op, BR_address
iname[99] ="B, #BEEF";//testing branch, calculated branch address should be
// (64\'h? + 64\'h0000000000000BEEF = 64\'h?)
iaddrbusout[99] = 64\'h00000B9C;
// op, BR_address
instrbusin[99] ={B, 26\'b00000000001011111011101111};
daddrbusout[99] = dontcare;
databusin[99] = 64\'bz;
databusout[99] = dontcare;
// op, rd, rn, rm
iname[100] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[100] = 64\'h00000BA0;
// op, rm, shamt, rn, rd
instrbusin[100] ={AND, R31, zeroSham, R31, R19};
daddrbusout[100] = dontcare;
databusin[100] = 64\'bz;
databusout[100] = dontcare;
// op, rd, rn, rm
iname[101] ="ADD, R20, R21, R20";//testing branch address result in R20 = 0000000000006448
iaddrbusout[101] = 64\'h00030758;
// op, rm, shamt, rn, rd
instrbusin[101] ={ADD, R20, zeroSham, R21, R20};
daddrbusout[101] = dontcare;
databusin[101] = 64\'bz;
databusout[101] = dontcare;
//copy of branch testing(@101)
//phase 5: testing B branch
// op, BR_address
iname[102] ="B, #1337";//testing branch, calculated branch address should be
// (64\'h? + 64\'h00000000000001337 = 64\'h?)
iaddrbusout[102] = 64\'h0003075C;
// op, BR_address
instrbusin[102] ={B, 26\'b00000000000001001100110111};
daddrbusout[102] = dontcare;
databusin[102] = 64\'bz;
databusout[102] = dontcare;
// op, rd, rn, rm
iname[103] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[103] = 64\'h00030760;
// op, rm, shamt, rn, rd
instrbusin[103] ={AND, R31, zeroSham, R31, R19};
daddrbusout[103] = dontcare;
databusin[103] = 64\'bz;
databusout[103] = dontcare;
// op, rd, rn, rm
iname[104] ="ADD, R17, R31, R31";//testing branch address result in R17 = 0000000000000000
iaddrbusout[104] = 64\'h00035438;
// op, rm, shamt, rn, rd
instrbusin[104] ={ADD, R31, zeroSham, R31, R17};
daddrbusout[104] = dontcare;
databusin[104] = 64\'bz;
databusout[104] = dontcare;
//phase 6: testing B.EQ and B.NE branch
// op, rd, rn, imm
iname[105] ="ADDI, R21, R31, #002";//testing addi, result in R21 = 0000000000000002
iaddrbusout[105] = 64\'h0003543C;
// opcode rm/ALUImm rn rd
instrbusin[105] ={ADDI, 12\'h002, R31, R21};
daddrbusout[105] = dontcare;
databusin[105] = 64\'bz;
databusout[105] = dontcare;
// op, rd, rn, imm
iname[106] ="ADDI, R22, R31, #002";//testing addi, result in R22 = 0000000000000002
iaddrbusout[106] = 64\'h00035440;
// opcode rm/ALUImm rn rd
instrbusin[106] ={ADDI, 12\'h002, R31, R22};
daddrbusout[106] = dontcare;
databusin[106] = 64\'bz;
databusout[106] = dontcare;
iname[107] = "NOP";//nada
iaddrbusout[107] = 64\'h00035444;
instrbusin[107] = 64\'b0;
daddrbusout[107] = dontcare;
databusin[107] = 64\'bz;
databusout[107] = dontcare;
iname[108] = "NOP";//nada
iaddrbusout[108] = 64\'h00035448;
instrbusin[108] = 64\'b0;
daddrbusout[108] = dontcare;
databusin[108] = 64\'bz;
databusout[108] = dontcare;
//TODO: find register to make this a fake branch for N bit
//SUBIS for FAKE BRANCH
// op, rd, rn, aluImm
iname[109] ="SUBIS,R31, R22, #001";//testing fake branch, this should NOT set the N high
iaddrbusout[109] = 64\'h0003544C;
// opcode rm/ALUImm rn rd
instrbusin[109] ={SUBIS, 12\'h001, R22, R31};
daddrbusout[109] = dontcare;
databusin[109] = 64\'bz;
databusout[109] = dontcare;
//FAKE BRANCH
// op, COND_addr, rt
iname[110] ="B_EQ, #69420, RX";//testing to NOT take the branch, N should be LOW
iaddrbusout[110] = 64\'h00035450;
// op, COND_addr, rt
instrbusin[110] ={B_EQ, 19\'b1101001010000100000, RX};
daddrbusout[110] = dontcare;
databusin[110] = 64\'bz;
databusout[110] = dontcare;
iname[111] = "NOP";//nada
iaddrbusout[111] = 64\'h00035454;
instrbusin[111] = 64\'b0;
daddrbusout[111] = dontcare;
databusin[111] = 64\'bz;
databusout[111] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[112] ="ADDS, R31, R31, R31";//set z flag for BEQ,
iaddrbusout[112] = 64\'h00035458;
// op, rm, shamt, rn, rd
instrbusin[112] ={ADDS, R31, zeroSham, R31, R31};
daddrbusout[112] = dontcare;
databusin[112] = 64\'bz;
databusout[112] = dontcare;
//real branch for B.EQ (I have more of the best branches)
// op, COND_addr, rt
iname[113] ="B_EQ, #AE, RX";//take the branch to instruction count 35714
iaddrbusout[113] = 64\'h0003545C;
// op, COND_addr, rt
instrbusin[113] ={B_EQ, 19\'b0000000000010101110, RX};
daddrbusout[113] = dontcare;
databusin[113] = 64\'bz;
databusout[113] = dontcare;
iname[114] = "NOP";//nada
iaddrbusout[114] = 64\'h00035460;
instrbusin[114] = 64\'b0;
daddrbusout[114] = dontcare;
databusin[114] = 64\'bz;
databusout[114] = dontcare;
iname[115] = "NOP";//nada
iaddrbusout[115] = 64\'h00035714;
instrbusin[115] = 64\'b0;
daddrbusout[115] = dontcare;
databusin[115] = 64\'bz;
databusout[115] = dontcare;
//use ADDS for branch test
// op, rd, rn, rm
iname[116] ="ADDS, R31, R21, R20";//DONT set Z bit to high
iaddrbusout[116] = 64\'h00035718;
// op, rm, shamt, rn, rd
instrbusin[116] ={ADDS, R20, zeroSham, R21, R31};
daddrbusout[116] = dontcare;
databusin[116] = 64\'bz;
databusout[116] = dontcare;
//test B.EQ
// op, COND_addr, rt
iname[117] ="B_EQ, #96, RX";//DONT take the branch to instruction count
iaddrbusout[117] = 64\'h0003571C;
// op, COND_addr, rt
instrbusin[117] ={B_EQ, 19\'b0000000000010010110, RX};
daddrbusout[117] = dontcare;
databusin[117] = 64\'bz;
databusout[117] = dontcare;
iname[118] = "NOP";//nada
iaddrbusout[118] = 64\'h00035720;
instrbusin[118] = 64\'b0;
daddrbusout[118] = dontcare;
databusin[118] = 64\'bz;
databusout[118] = dontcare;
iname[119] = "NOP";//nada
iaddrbusout[119] = 64\'h00035724;
instrbusin[119] = 64\'b0;
daddrbusout[119] = dontcare;
databusin[119] = 64\'bz;
databusout[119] = dontcare;
//copy of move and more branch testing(@117)
//phase 8: testing MOVEZ and overflow bit
//4 instructions to set registers to 0
// op, rd, rn, rm
iname[120] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[120] = 64\'h00035728;
// op, rm, shamt, rn, rd
instrbusin[120] ={AND, R31, zeroSham, R31, R19};
daddrbusout[120] = dontcare;
databusin[120] = 64\'bz;
databusout[120] = dontcare;
// op, rd, rn, rm
iname[121] ="AND, R20, R31, R31";//delay, result in R20 = 0000000000000000
iaddrbusout[121] = 64\'h0003572C;
// op, rm, shamt, rn, rd
instrbusin[121] ={AND, R31, zeroSham, R31, R20};
daddrbusout[121] = dontcare;
databusin[121] = 64\'bz;
databusout[121] = dontcare;
// op, rd, rn, rm
iname[122] ="AND, R21, R31, R31";//delay, result in R21 = 0000000000000000
iaddrbusout[122] = 64\'h00035730;
// op, rm, shamt, rn, rd
instrbusin[122] ={AND, R31, zeroSham, R31, R21};
daddrbusout[122] = dontcare;
databusin[122] = 64\'bz;
databusout[122] = dontcare;
// op, rd, rn, rm
iname[123] ="AND, R22, R31, R31";//delay, result in R22 = 0000000000000000
iaddrbusout[123] = 64\'h00035734;
// op, rm, shamt, rn, rd
instrbusin[123] ={AND, R31, zeroSham, R31, R22};
daddrbusout[123] = dontcare;
databusin[123] = 64\'bz;
databusout[123] = dontcare;
//4 MOVZ commands
//move 0 amt
// op, move_amt, MOV_imm, rd
iname[124] ="MOVZ, move_0, #FFFF, R19";//testing move, result in R19 = 000000000000FFFF
iaddrbusout[124] = 64\'h00035738;
// op, move_amt, MOV_imm, rd
instrbusin[124] ={MOVZ, move_0, 16\'hFFFF, R19};
daddrbusout[124] = dontcare;
databusin[124] = 64\'bz;
databusout[124] = dontcare;
//move 1 amt
// op, move_amt, MOV_imm, rd
iname[125] ="MOVZ, move_1, #FFFF, R20";//testing move, result in R20 = 00000000FFFF0000
iaddrbusout[125] = 64\'h0003573C;
// op, move_amt, MOV_imm, rd
instrbusin[125] ={MOVZ, move_1, 16\'hFFFF, R20};
daddrbusout[125] = dontcare;
databusin[125] = 64\'bz;
databusout[125] = dontcare;
//move 2 amt
// op, move_amt, MOV_imm, rd
iname[126] ="MOVZ, move_2, #FFFF, R21";//testing move, result in R21 = 0000FFFF00000000
iaddrbusout[126] = 64\'h00035740;
// op, move_amt, MOV_imm, rd
instrbusin[126] ={MOVZ, move_2, 16\'hFFFF, R21};
daddrbusout[126] = dontcare;
databusin[126] = 64\'bz;
databusout[126] = dontcare;
//move 3 amt
// op, move_amt, MOV_imm, rd
iname[127] ="MOVZ, move_3, #6FFF, R22";//testing move, result in R22 = 6FFF000000000000
iaddrbusout[127] = 64\'h00035744;
// op, move_amt, MOV_imm, rd
instrbusin[127] ={MOVZ, move_3, 16\'h6FFF, R22};
daddrbusout[127] = dontcare;
databusin[127] = 64\'bz;
databusout[127] = dontcare;
//have or for move 0 and move 1
// op, rd, rn, rm
iname[128] ="ORR, R23, R19, R20";//testing xor, result in R23 = 00000000FFFFFFFF
iaddrbusout[128] = 64\'h00035748;
// op, rm, shamt, rn, rd
instrbusin[128] ={ORR, R20, zeroSham, R19, R23};
daddrbusout[128] = dontcare;
databusin[128] = 64\'bz;
databusout[128] = dontcare;
//delay
iname[129] = "NOP";//nada
iaddrbusout[129] = 64\'h0003574C;
instrbusin[129] = 64\'b0;
daddrbusout[129] = dontcare;
databusin[129] = 64\'bz;
databusout[129] = dontcare;
//have or for move 2 and move 3
// op, rd, rn, rm
iname[130] ="ORR, R24, R21, R22";//testing xor, result in R27 = 6FFFFFFF00000000
iaddrbusout[130] = 64\'h00035750;
// op, rm, shamt, rn, rd
instrbusin[130] ={ORR, R22, zeroSham, R21, R24};
daddrbusout[130] = dontcare;
databusin[130] = 64\'bz;
databusout[130] = dontcare;
//delay
iname[131] = "NOP";//nada
iaddrbusout[131] = 64\'h00035754;
instrbusin[131] = 64\'b0;
daddrbusout[131] = dontcare;
databusin[131] = 64\'bz;
databusout[131] = dontcare;
//delay
iname[132] = "NOP";//nada
iaddrbusout[132] = 64\'h00035758;
instrbusin[132] = 64\'b0;
daddrbusout[132] = dontcare;
databusin[132] = 64\'bz;
databusout[132] = dontcare;
//have or for move(0|1) and move(2|3)
// op, rd, rn, rm
iname[133] ="ORR, R25, R23, R24";//testing or, result in R25 = 6FFFFFFFFFFFFFFF
iaddrbusout[133] = 64\'h0003575C;
// op, rm, shamt, rn, rd
instrbusin[133] ={ORR, R24, zeroSham, R23, R25};
daddrbusout[133] = dontcare;
databusin[133] = 64\'bz;
databusout[133] = dontcare;
//dealy
iname[134] = "NOP";//nada
iaddrbusout[134] = 64\'h00035760;
instrbusin[134] = 64\'b0;
daddrbusout[134] = dontcare;
databusin[134] = 64\'bz;
databusout[134] = dontcare;
//delay
iname[135] = "NOP";//nada
iaddrbusout[135] = 64\'h00035764;
instrbusin[135] = 64\'b0;
daddrbusout[135] = dontcare;
databusin[135] = 64\'bz;
databusout[135] = dontcare;
//addis command to NOT trigger the V bit
// op, rd, rn, aluImm
iname[136] ="ADDIS,R26, R25, #001";//for not V bit set, result in R26 = 7000000000000000
iaddrbusout[136] = 64\'h00035768;
// opcode rm/ALUImm rn rd
instrbusin[136] ={ADDIS, 12\'h001, R25, R26};
daddrbusout[136] = dontcare;
databusin[136] = 64\'bz;
databusout[136] = dontcare;
iname[137] = "NOP";//nada
iaddrbusout[137] = 64\'h0003576C;
instrbusin[137] = 64\'b0;
daddrbusout[137] = dontcare;
databusin[137] = 64\'bz;
databusout[137] = dontcare;
iname[138] = "NOP";//nada
iaddrbusout[138] = 64\'h00035770;
instrbusin[138] = 64\'b0;
daddrbusout[138] = dontcare;
databusin[138] = 64\'bz;
databusout[138] = dontcare;
//phase 9: testing B.LT and B.GE branch
//7FFF+1 = N and V, 8000-1 = V
//use SUBIS for the branch condition test (B.LT test)
//DONT take branch
// op, rd, rn, aluImm
iname[139] ="SUBIS,R26, R26, #001";//result in R26 = 6FFFFFFFFFFFFFFF
iaddrbusout[139] = 64\'h00035774;
// opcode rm/ALUImm rn rd
instrbusin[139] ={SUBIS, 12\'h001, R26, R26};
daddrbusout[139] = dontcare;
databusin[139] = 64\'bz;
databusout[139] = dontcare;
//NOT TAKE branch
// op, COND_addr, rt
iname[140] ="B_LT, #42, RX";//new branch address is
iaddrbusout[140] = 64\'h00035778;
// op, COND_addr, rt
instrbusin[140] ={B_LT, 19\'b0000000000001000010, RX};
daddrbusout[140] = dontcare;
databusin[140] = 64\'bz;
databusout[140] = dontcare;
//delay
iname[141] = "NOP";//nada
iaddrbusout[141] = 64\'h0003577C;
instrbusin[141] = 64\'b0;
daddrbusout[141] = dontcare;
databusin[141] = 64\'bz;
databusout[141] = dontcare;
//delay
iname[142] = "NOP";//nada
iaddrbusout[142] = 64\'h00035780;
instrbusin[142] = 64\'b0;
daddrbusout[142] = dontcare;
databusin[142] = 64\'bz;
databusout[142] = dontcare;
//use ADDIS for the branch condition test B.GE test
// op, rd, rn, aluImm
iname[143] ="ADDIS,R26, R26, #001";//result in R26 = 7000000000000000
iaddrbusout[143] = 64\'h00035784;
// opcode rm/ALUImm rn rd
instrbusin[143] ={ADDIS, 12\'h001, R26, R26};
daddrbusout[143] = dontcare;
databusin[143] = 64\'bz;
databusout[143] = dontcare;
//NOT TAKE branch
// op, COND_addr, rt
iname[144] ="B_LT, #24, RX";//new branch address is B60
iaddrbusout[144] = 64\'h00035788;
// op, COND_addr, rt
instrbusin[144] ={B_LT, 19\'b0000000000000100100, RX};
daddrbusout[144] = dontcare;
databusin[144] = 64\'bz;
databusout[144] = dontcare;
//delay
iname[145] = "NOP";//nada
iaddrbusout[145] = 64\'h0003578C;
instrbusin[145] = 64\'b0;
daddrbusout[145] = dontcare;
databusin[145] = 64\'bz;
databusout[145] = dontcare;
//delay
iname[146] = "NOP";//nada
iaddrbusout[146] = 64\'h00035790;
instrbusin[146] = 64\'b0;
daddrbusout[146] = dontcare;
databusin[146] = 64\'bz;
databusout[146] = dontcare;
//finishing up
iname[147] = "NOP";//nada
iaddrbusout[147] = 64\'h00035794;
instrbusin[147] = 64\'b0;
daddrbusout[147] = dontcare;
databusin[147] = 64\'bz;
databusout[147] = dontcare;
iname[148] = "NOP";//nada
iaddrbusout[148] = 64\'h00035798;
instrbusin[148] = 64\'b0;
daddrbusout[148] = dontcare;
databusin[148] = 64\'bz;
databusout[148] = dontcare;
iname[149] = "NOP";//nada
iaddrbusout[149] = 64\'h0003579C;
instrbusin[149] = 64\'b0;
daddrbusout[149] = dontcare;
databusin[149] = 64\'bz;
databusout[149] = dontcare;
//Random(@147)//TODO: test what the registers actually are
// op, rd, rn, rm
iname[150] ="ORRI, R21, R24, #AAA";//testing ori, result in R21 = 0000000000000001//TODO
iaddrbusout[150] = 64\'h000357A0;
// opcode rm/ALUImm rn rd
instrbusin[150] ={ORRI, 12\'h001, R24, R21};
daddrbusout[150] = dontcare;
databusin[150] = 64\'bz;
databusout[150] = dontcare;
// op, rd, rn, rm
iname[151] ="EORI, R22, R20, #CCC";//testing xori, result in R22 = 0000000000000AAA//TODO
iaddrbusout[151] = 64\'h000357A4;
// opcode rm/ALUImm rn rd
instrbusin[151] ={EORI, 12\'h000, R20, R22};
daddrbusout[151] = dontcare;
databusin[151] = 64\'bz;
databusout[151] = dontcare;
// op, rd, rn, rm
iname[152] ="ANDI, R23, R0, #321";//testing andi, result in R23 = 0000000000000002//TODO
iaddrbusout[152] = 64\'h000357A8;
// opcode rm/ALUImm rn rd
instrbusin[152] ={ANDI, 12\'h003, R0, R23};
daddrbusout[152] = dontcare;
databusin[152] = 64\'bz;
databusout[152] = dontcare;
// op, rd, rn, rm
iname[153] ="SUBI, R24, R20, #123";//testing subi, result in R24 = 0000000000000AA0//TODO
iaddrbusout[153] = 64\'h000357AC;
// opcode rm/ALUImm rn rd
instrbusin[153] ={SUBI, 12\'h00A, R20, R24};
daddrbusout[153] = dontcare;
databusin[153] = 64\'bz;
databusout[153] = dontcare;
//delay
iname[154] = "NOP";//nada
iaddrbusout[154] = 64\'h000357B0;
instrbusin[154] = 64\'b0;
daddrbusout[154] = dontcare;
databusin[154] = 64\'bz;
databusout[154] = dontcare;
//delay
iname[155] = "NOP";//nada
iaddrbusout[155] = 64\'h000357B4;
instrbusin[155] = 64\'b0;
daddrbusout[155] = dontcare;
databusin[155] = 64\'bz;
databusout[155] = dontcare;
//finishing up
iname[156] = "NOP";//nada
iaddrbusout[156] = 64\'h000357B8;
instrbusin[156] = 64\'b0;
daddrbusout[156] = dontcare;
databusin[156] = 64\'bz;
databusout[156] = dontcare;
//Done. 157 instructions
//this number will be inacurate for a while(the number below)
//also remember to set k down below to ntests - 1
// (no. instructions) + (no. loads) + 2*(no. stores) = 35 + 2 + 2*7 = 51
ntests = 157;//?
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
assign databus = clkd ? 64\'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
databusk = 64\'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("'b'reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
$display ("Time=%t\
clk=%b", $realtime, clk);
for (k=0; k<= 156; k=k+1) begin
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set load data for 3rd previous instruction
if (k >=3)
databusk = databusin[k-3];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check data address from 3rd previous instruction
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check store data from 3rd previous instruction
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
//phase 3: testing LSL, LSR, 64bit
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:29];
wire [63:0] iaddrbus;
reg [63:0] iaddrbusout[0:29];
wire [31:0] dselect;
reg [31:0] dselectout[0:29];
wire [63:0] dbus;
reg [63:0] dbusout[0:29];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [31:0] dontcare_addr;
reg [24*8:1] iname[0:29];
integer error, k, ntests;
//all opcode parameters to be used
parameter ADD = 11\'b10001011000;
parameter ADDI = 10\'b1001000100;
parameter ADDIS = 10\'b1011000100;
parameter ADDS = 11\'b10101011000;
parameter AND = 11\'b10001010000;
parameter ANDI = 10\'b1001001000;
parameter ANDIS = 10\'b1111001000;
parameter ANDS = 11\'b11101010000;
parameter CBNZ = 8\'b10110101;
parameter CBZ = 8\'b10110100;
parameter EOR = 11\'b11001010000;
parameter EORI = 10\'b1101001000;
parameter LDUR = 11\'b11111000010;
parameter LSL = 11\'b11010011011;
parameter LSR = 11\'b11010011010;
parameter MOVZ = 9\'b110100101;
parameter ORR = 11\'b10101010000;
parameter ORRI = 10\'b1011001000;
parameter STUR = 11\'b11111000000;
parameter SUB = 11\'b11001011000;
parameter SUBI = 10\'b1101000100;
parameter SUBIS = 10\'b1111000100;
parameter SUBS = 11\'b11101011000;
parameter B = 6\'b000101;
parameter B_EQ = 8\'b01010101;
parameter B_NE = 8\'b01010110;
parameter B_LT = 8\'b01010111;
parameter B_GT = 8\'b01011000;
//register parameters
parameter R0 = 5\'b00000;
parameter R0_dselect = 32\'b00000000000000000000000000000001;
parameter R18 = 5\'b10010;
parameter R18_dselect = 32\'b00000000000001000000000000000000;
parameter R19 = 5\'b10011;
parameter R19_dselect = 32\'b00000000000010000000000000000000;
parameter R20 = 5\'b10100;
parameter R20_dselect = 32\'b00000000000100000000000000000000;
parameter R21 = 5\'b10101;
parameter R21_dselect = 32\'b00000000001000000000000000000000;
parameter R22 = 5\'b10110;
parameter R22_dselect = 32\'b00000000010000000000000000000000;
parameter R23 = 5\'b10111;
parameter R23_dselect = 32\'b00000000100000000000000000000000;
parameter R24 = 5\'b11000;
parameter R24_dselect = 32\'b00000001000000000000000000000000;
parameter R25 = 5\'b11001;
parameter R25_dselect = 32\'b00000010000000000000000000000000;
parameter R26 = 5\'b11010;
parameter R26_dselect = 32\'b00000100000000000000000000000000;
parameter R27 = 5\'b11011;
parameter R27_dselect = 32\'b00001000000000000000000000000000;
parameter R28 = 5\'b11100;
parameter R28_dselect = 32\'b00010000000000000000000000000000;
parameter R29 = 5\'b11101;
parameter R29_dselect = 32\'b00100000000000000000000000000000;
parameter R30 = 5\'b11110;
parameter R30_dselect = 32\'b01000000000000000000000000000000;
parameter R31 = 5\'b11111;
parameter R31_dselect = 32\'b10000000000000000000000000000000;
//other parameterz to be used
parameter zeroSham = 6\'b000000;
parameter RX = 5\'b11111;
parameter oneShamt = 6\'b000001;
parameter twoShamt = 6\'b000010;
parameter threeShamt = 6\'b000011;
parameter eightShamt = 6\'b001000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.dbus(dbus),.dselect(dselect));
initial begin
dontcare = 64\'hx;
dontcare_addr = 32\'hx;
//phase 1: testing basic op commands and instruction bus
//* ADDI, R20, R31, #AAA
iname[0] = "ADDI, R20, R31, #AAA";//testing addi, result in R20 = 00000AAA
iaddrbusout[0] = 64\'h00000000;
// opcode rm/ALUImm rn rd...
instrbusin[0]={ADDI, 12\'hAAA, R31, R20};
dselectout[0] = R20_dselect;
dbusout[0] = 64\'h00000AAA;
//* ADDI, R31, R23, #002
iname[1] = "ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 00000000
iaddrbusout[1] = 64\'h00000004;
// opcode rm/ALUImm rn rd...
instrbusin[1]={ADDI, 12\'h002, R23, R31};
dselectout[1] = R31_dselect;
dbusout[1] = dontcare;
//* ADDI, R0, R23, #002
iname[2] = "ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 00000002
iaddrbusout[2] = 64\'h00000008;
// opcode rm/ALUImm rn rd...
instrbusin[2]={ADDI, 12\'h002, R23, R0};
dselectout[2] = R0_dselect;
dbusout[2] = 64\'h00000002;
//* ORRI, R21, R24, #001
iname[3] = "ORRI, R21, R24, #001";//testing ori, result in R21 = 00000001
iaddrbusout[3] = 64\'h0000000C;
// opcode rm/ALUImm rn rd...
instrbusin[3]={ORRI, 12\'h001, R24, R21};
dselectout[3] = R21_dselect;
dbusout[3] = 64\'h00000001;
//* EORI, R22, R20, #000
iname[4] = "EORI, R22, R20, #000";//testing xori, result in R22 = 00000AAA
iaddrbusout[4] = 64\'h00000010;
// opcode rm/ALUImm rn rd...
instrbusin[4]={EORI, 12\'h000, R20, R22};
dselectout[4] = R22_dselect;
dbusout[4] = 64\'h00000AAA;
//* ANDI, R23, R0, #003
iname[5] = "ANDI, R23, R0, #003";//testing andi, result in R23 = 00000002
iaddrbusout[5] = 64\'h00000014;
// opcode rm/ALUImm rn rd...
instrbusin[5]={ANDI, 12\'h003, R0, R23};
dselectout[5] = R23_dselect;
dbusout[5] = 64\'h00000002;
//* SUBI, R24, R20, #00A
iname[6] = "SUBI, R24, R20, #00A";//testing subi, result in R24 = 00000AA0
iaddrbusout[6] = 64\'h00000018;
// opcode rm/ALUImm rn rd...
instrbusin[6]={SUBI, 12\'h00A, R20, R24};
dselectout[6] = R24_dselect;
dbusout[6] = 64\'h00000AA0;
// op, rd, rn, rm
//* ADD, R25, R20, R0
iname[7] = "ADD, R25, R20, R0";//testing add, result in R25 = 00000AAC
iaddrbusout[7] = 64\'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7]={ADD, R0, zeroSham, R20, R25};
dselectout[7] = R25_dselect;
dbusout[7] = 64\'h00000AAC;
// op, rd, rn, rm
//* AND, R26, R20, R22
iname[8] = "AND, R26, R20, R22";//testing and, result in R26 = 00000AAA
iaddrbusout[8] = 64\'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8]={AND, R22, zeroSham, R20, R26};
dselectout[8] = R26_dselect;
dbusout[8] = 64\'h00000AAA;
// op, rd, rn, rm
//* XOR, R27, R23, R21
iname[9] = "EOR, R27, R23, R21";//testing xor, result in R27 = 00000003
iaddrbusout[9] = 64\'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9]={EOR, R21, zeroSham, R23, R27};
dselectout[9] = R27_dselect;
dbusout[9] = 64\'h00000003;
// op, rd, rn, rm
//* OR, R28, R25, R23
iname[10] = "ORR, R28, R25, R23";//testing or, result in R28 = 00000AAE
iaddrbusout[10] = 64\'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10]={ORR, R23, zeroSham, R25, R28};
dselectout[10] = R28_dselect;
dbusout[10] = 64\'h00000AAE;
// op, rd, rn, rm
//* SUB, R29, R20, R22
iname[11] = "SUB, R29, R20, R22";//testing sub, result in R29 = 00000000
iaddrbusout[11] = 64\'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11]={SUB, R22, zeroSham, R20, R29};
dselectout[11] = R29_dselect;
dbusout[11] = 64\'h00000000;
// op, rd, rn, aluImm
//* ADDI, R30, R31, #000
iname[12] = "ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 00000000
iaddrbusout[12] = 64\'h00000030;
// opcode rm/ALUImm rn rd...
instrbusin[12]={ADDI, 12\'h000, R31, R30};
dselectout[12] = R30_dselect;
dbusout[12] = 64\'h00000000;
//phase 2: testing basic op codes with the n,z,c flags
// op, rd, rn, aluImm
//* SUBIS,R20, R0, #003
iname[13] = "SUBIS,R20, R0, #003";//testing subis, n flag, result in R20 = FFFFFFFF
iaddrbusout[13] = 64\'h00000034;
// opcode rm/ALUImm rn rd...
instrbusin[13] = {SUBIS, 12\'h003, R0, R20};
dselectout[13] = dontcare;
dbusout[13] = dontcare;
// op, rd, rn, rm
//* SUBS, R21, R25, R28
iname[14] = "SUBS, R21, R25, R28";//testing subs, n flag, result in R21 = FFFFFFFE
iaddrbusout[14] = 64\'h00000038;
// op, rm, shamt, rn, rd
instrbusin[14] = {SUBS, R28, zeroSham, R25, R21};
dselectout[14] = dontcare;
dbusout[14] = dontcare;
// op, rd, rn, aluImm
//* ADDIS,R22, R31, #000
iname[15] = "ADDIS,R22, R31, #000";//testing addis, z flag, result in R22 = 00000000
iaddrbusout[15] = 64\'h0000003C;
// opcode rm/ALUImm rn rd...
instrbusin[15] = {ADDIS, 12\'h000, R31, R22};
dselectout[15] = dontcare;
dbusout[15] = dontcare;
// op, rd, rn, rm
//* ADDS R23, R20, R23
iname[16] = "ADDS R23, R20, R23";//testing adds, c flag, result in R23 = 00000001
iaddrbusout[16] = 64\'h00000040;
// op, rm, shamt, rn, rd
instrbusin[16] = {ADDS, R23, zeroSham, R20, R23};
dselectout[16] = dontcare;
dbusout[16] = dontcare;
// op, rd, rn, aluImm
//* ANDIS,R24, R20, #002
iname[17] = "ANDIS,R24, R20, #002";//testing andis, reseting n,z flags to low, result in R24 = 00000002
iaddrbusout[17] = 64\'h00000044;
// opcode rm/ALUImm rn rd...
instrbusin[17] = {ANDIS, 12\'h002, R20, R24};
dselectout[17] = dontcare;
dbusout[17] = dontcare;
// op, rd, rn, rm
//* ANDS, R25, R21, R20
iname[18] = "ANDS, R25, R21, R20";//testing ands, n flag, result in R25 = FFFFFFFE
iaddrbusout[18] = 64\'h00000048;
// op, rm, shamt, rn, rd
instrbusin[18] = {ANDS, R20, zeroSham, R21, R25};
dselectout[18] = dontcare;
dbusout[18] = dontcare;
//phase 3: testing LSL, LSR
//setting up the register R20 for a test of the LSL
// op, rd, rn, rm
iname[19] ="ADDI, R20, R31, #007";//setting up for left shift, result in R20 = 0000000000000007
iaddrbusout[19] = 64\'h0000004C;
// opcode rm/ALUImm rn rd
instrbusin[19] ={ADDI, 12\'h007, R31, R20};
dselectout[19] = R20_dselect;
dbusout[19] = 64\'h00000007;
// op, rd, rn, rm
iname[20] ="ADDI, R21, R31, #700";//setting up for right shift, n flag, result in R21 = 0000000000000700
iaddrbusout[20] = 64\'h00000050;
// opcode rm/ALUImm rn rd
instrbusin[20] ={ADDI, 12\'h700, R31, R21};
dselectout[20] = R21_dselect;
dbusout[20] = 64\'h00000700;
// op, rd, rn, rm
iname[21] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[21] = 64\'h00000054;
// op, rm, shamt, rn, rd
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
dselectout[21] = R19_dselect;
dbusout[21] = 64\'h00000000;
// op, rd, rn, rm
iname[22] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[22] = 64\'h00000058;
// op, rm, shamt, rn, rd
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
dselectout[22] = R18_dselect;
dbusout[22] = 64\'h00000000;
// op, rd, rn, rm
iname[23] ="LSL, R20, R20, 2";//testing left shift, result in R20 = 0000000000000700
iaddrbusout[23] = 64\'h0000005C;
// op, rm, shamt, rn, rd
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
dselectout[23] = R20_dselect;
dbusout[23] = 64\'h00000700;
// op, rd, rn, rm
iname[24] ="LSR, R21, R21, 2";//testing right shift, result in R21 = 0000000000000007
iaddrbusout[24] = 64\'h00000060;
// op, rm, shamt, rn, rd
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
dselectout[24] = R21_dselect;
dbusout[24] = 64\'h00000007;
//finishing up
iname[25] = "NOP";//nada
iaddrbusout[25] = 64\'h00000064;
instrbusin[25] = 64\'b0;
dselectout[25] = dontcare_addr;
dbusout[25] = dontcare;
iname[26] = "NOP";//nada
iaddrbusout[26] = 64\'h00000068;
instrbusin[26] = 64\'b0;
dselectout[26] = dontcare_addr;
dbusout[26] = dontcare;
iname[27] = "NOP";//nada
iaddrbusout[27] = 64\'h0000006C;
instrbusin[27] = 64\'b0;
dselectout[27] = dontcare_addr;
dbusout[27] = dontcare;
iname[28] = "NOP";//nada
iaddrbusout[28] = 64\'h00000070;
instrbusin[28] = 64\'b0;
dselectout[28] = dontcare_addr;
dbusout[28] = dontcare;
iname[29] = "NOP";//nada
iaddrbusout[29] = 64\'h00000074;
instrbusin[29] = 64\'b0;
dselectout[29] = dontcare_addr;
dbusout[29] = dontcare;
//remember to set k down below to ntests - 1
ntests = 30;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
//assign databus = clkd ? 64\'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
//databusk = 64\'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
$display ("Time=%t\
clk=%b", $realtime, clk);
for (k=0; k<= 29; k=k+1) begin
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set dbus and dselect data data for 4th previous instruction
if (k >=4)
//databusk = databusin[k-4];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b%b%b%b%b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check writeback data address from 4th previous instruction
if ( (k >= 4) && (dselectout[k-4] !== dontcare_addr) ) begin
$display (" Testing writeback data address for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dselect = %b", dselect);
$display (" Correct dselect = %b", dselectout[k-4]);
if (dselectout[k-4] !== dselect) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check writeback data from 4th previous instruction
if ( (k >= 4) && (dbusout[k-4] !== dontcare) ) begin
$display (" Testing writeback data for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dbus = %b", dbus);
$display (" Correct dbus = %b", dbusout[k-4]);
if (dbusout[k-4] !== dbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
//Phase 1: tests basic data processing instructions for a 32bit version of the ARM LEG CPU
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:17];
wire [31:0] iaddrbus, dselect;
reg [31:0] iaddrbusout[0:17], dselectout[0:17];
wire [31:0] dbus;
reg [31:0] databusk, dbusout[0:17];
reg clk, reset;
reg clkd;
reg [31:0] dontcare;
reg [24*8:1] iname[0:17];
integer error, k, ntests;
//all current opcode parameters to be used
parameter ADD = 11\'b10001011000;
parameter ADDI = 10\'b1001000100;
//parameter ADDI = \'b;
//parameter ADDI = \'b;
parameter AND = 11\'b10001010000;
parameter ANDI = 10\'b1001001000;
//parameter ANDI = \'b;
//parameter ANDI = \'b;
//CBNZ
//CBZ
parameter EOR = 11\'b11001010000;
parameter EORI = 10\'b1101001000;
//LDUR
//parameter LW = \'b;
//LSL
//LSR
//MOVZ
parameter ORR = 11\'b10101010000;
parameter ORRI = 10\'b1011001000;
//STUR
//parameter SW = \'b;
parameter SUB = 11\'b11001011000;
parameter SUBI = 10\'b1101000100;
//parameter SUBI = \'b;
//parameter SUBI = \'b;
//B
//parameter B.EQ = \'b;
//parameter B.NE = \'b;
//parameter SLT = \'b;
//parameter SLE = \'b
//register parameters
parameter R0 = 5\'b00000;
parameter R0_dselect = 32\'b00000000000000000000000000000001;
parameter R20 = 5\'b10100;
parameter R20_dselect = 32\'b00000000000100000000000000000000;
parameter R21 = 5\'b10101;
parameter R21_dselect = 32\'b00000000001000000000000000000000;
parameter R22 = 5\'b10110;
parameter R22_dselect = 32\'b00000000010000000000000000000000;
parameter R23 = 5\'b10111;
parameter R23_dselect = 32\'b00000000100000000000000000000000;
parameter R24 = 5\'b11000;
parameter R24_dselect = 32\'b00000001000000000000000000000000;
parameter R25 = 5\'b11001;
parameter R25_dselect = 32\'b00000010000000000000000000000000;
parameter R26 = 5\'b11010;
parameter R26_dselect = 32\'b00000100000000000000000000000000;
parameter R27 = 5\'b11011;
parameter R27_dselect = 32\'b00001000000000000000000000000000;
parameter R28 = 5\'b11100;
parameter R28_dselect = 32\'b00010000000000000000000000000000;
parameter R29 = 5\'b11101;
parameter R29_dselect = 32\'b00100000000000000000000000000000;
parameter R30 = 5\'b11110;
parameter R30_dselect = 32\'b01000000000000000000000000000000;
parameter R31 = 5\'b11111;
parameter R31_dselect = 32\'b10000000000000000000000000000000;
//other parameterz to be used
parameter zeroSham = 6\'b000000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.dbus(dbus),.dselect(dselect));
initial begin
dontcare = 32\'hx;
//phase 1: testing basic op commands and instruction bus
//* ADDI, R20, R31, #AAA
iname[0] = "ADDI, R20, R31, #AAA";//testing addi, result in R20 = 00000AAA
iaddrbusout[0] = 32\'h00000000;
// opcode rm/ALUImm rn rd...
instrbusin[0]={ADDI, 12\'hAAA, R31, R20};
dselectout[0] = R20_dselect;
dbusout[0] = 32\'h00000AAA;
//* ADDI, R31, R23, #002
iname[1] = "ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 00000000
iaddrbusout[1] = 32\'h00000004;
// opcode rm/ALUImm rn rd...
instrbusin[1]={ADDI, 12\'h002, R23, R31};
dselectout[1] = R31_dselect;
dbusout[1] = dontcare;
//* ADDI, R0, R23, #002
iname[2] = "ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 00000002
iaddrbusout[2] = 32\'h00000008;
// opcode rm/ALUImm rn rd...
instrbusin[2]={ADDI, 12\'h002, R23, R0};
dselectout[2] = R0_dselect;
dbusout[2] = 32\'h00000002;
//* ORRI, R21, R24, #001
iname[3] = "ORRI, R21, R24, #001";//testing ori, result in R21 = 00000001
iaddrbusout[3] = 32\'h0000000C;
// opcode rm/ALUImm rn rd...
instrbusin[3]={ORRI, 12\'h001, R24, R21};
dselectout[3] = R21_dselect;
dbusout[3] = 32\'h00000001;
//* EORI, R22, R20, #000
iname[4] = "EORI, R22, R20, #000";//testing xori, result in R22 = 00000AAA
iaddrbusout[4] = 32\'h00000010;
// opcode rm/ALUImm rn rd...
instrbusin[4]={EORI, 12\'h000, R20, R22};
dselectout[4] = R22_dselect;
dbusout[4] = 32\'h00000AAA;
//* ANDI, R23, R0, #003
iname[5] = "ANDI, R23, R0, #003";//testing andi, result in R23 = 00000002
iaddrbusout[5] = 32\'h00000014;
// opcode rm/ALUImm rn rd...
instrbusin[5]={ANDI, 12\'h003, R0, R23};
dselectout[5] = R23_dselect;
dbusout[5] = 32\'h00000002;
//* SUBI, R24, R20, #00A
iname[6] = "SUBI, R24, R20, #00A";//testing subi, result in R24 = 00000AA0
iaddrbusout[6] = 32\'h00000018;
// opcode rm/ALUImm rn rd...
instrbusin[6]={SUBI, 12\'h00A, R20, R24};
dselectout[6] = R24_dselect;
dbusout[6] = 32\'h00000AA0;
// op, rd, rn, rm
//* ADD, R25, R20, R0
iname[7] = "ADD, R25, R20, R0";//testing add, result in R25 = 00000AAC
iaddrbusout[7] = 32\'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7]={ADD, R0, zeroSham, R20, R25};
dselectout[7] = R25_dselect;
dbusout[7] = 32\'h00000AAC;
// op, rd, rn, rm
//* AND, R26, R20, R22
iname[8] = "AND, R26, R20, R22";//testing and, result in R26 = 00000AAA
iaddrbusout[8] = 32\'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8]={AND, R22, zeroSham, R20, R26};
dselectout[8] = R26_dselect;
dbusout[8] = 32\'h00000AAA;
// op, rd, rn, rm
//* XOR, R27, R23, R21
iname[9] = "EOR, R27, R23, R21";//testing xor, result in R27 = 00000003
iaddrbusout[9] = 32\'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9]={EOR, R21, zeroSham, R23, R27};
dselectout[9] = R27_dselect;
dbusout[9] = 32\'h00000003;
// op, rd, rn, rm
//* OR, R28, R25, R23
iname[10] = "ORR, R28, R25, R23";//testing or, result in R28 = 00000AAE
iaddrbusout[10] = 32\'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10]={ORR, R23, zeroSham, R25, R28};
dselectout[10] = R28_dselect;
dbusout[10] = 32\'h00000AAE;
// op, rd, rn, rm
//* SUB, R29, R20, R22
iname[11] = "SUB, R29, R20, R22";//testing sub, result in R29 = 00000000
iaddrbusout[11] = 32\'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11]={SUB, R22, zeroSham, R20, R29};
dselectout[11] = R29_dselect;
dbusout[11] = 32\'h00000000;
// op, rd, rn, aluImm
//* ADDI, R30, R31, #000
iname[12] = "ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 00000000
iaddrbusout[12] = 32\'h00000030;
// opcode rm/ALUImm rn rd...
instrbusin[12]={ADDI, 12\'h000, R31, R30};
dselectout[12] = R30_dselect;
dbusout[12] = 32\'h00000000;
//* NOP
iname[13] = "NOP";//nada
iaddrbusout[13] = 32\'h00000034;
instrbusin[13] = 32\'b00000000000000000000000000000000;
dselectout[13] = dontcare;
dbusout[13] = dontcare;
//* NOP
iname[14] = "NOP";//nada
iaddrbusout[14] = 32\'h00000038;
instrbusin[14] = 32\'b00000000000000000000000000000000;
dselectout[14] = dontcare;
dbusout[14] = dontcare;
//* NOP
iname[15] = "NOP";//nada
iaddrbusout[15] = 32\'h0000003C;
instrbusin[15] = 32\'b00000000000000000000000000000000;
dselectout[15] = dontcare;
dbusout[15] = dontcare;
//* NOP
iname[16] = "NOP";//nada
iaddrbusout[16] = 32\'h00000040;
instrbusin[16] = 32\'b00000000000000000000000000000000;
dselectout[16] = dontcare;
dbusout[16] = dontcare;
//* NOP
iname[17] = "NOP";//nada
iaddrbusout[17] = 32\'h00000044;
instrbusin[17] = 32\'b00000000000000000000000000000000;
dselectout[17] = dontcare;
dbusout[17] = dontcare;
ntests = 18;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
//assign databus = clkd ? 32\'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
//databusk = 32\'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
$display ("Time=%t\
clk=%b", $realtime, clk);
for (k=0; k<= 17; k=k+1) begin
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set dbus and dselect data data for 4th previous instruction
if (k >=4)
//databusk = databusin[k-4];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b%b%b%b%b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check writeback data address from 4th previous instruction
if ( (k >= 4) && (dselectout[k-4] !== dontcare) ) begin
$display (" Testing writeback data address for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dselect = %b", dselect);
$display (" Correct dselect = %b", dselectout[k-4]);
if (dselectout[k-4] !== dselect) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check writeback data from 4th previous instruction
if ( (k >= 4) && (dbusout[k-4] !== dontcare) ) begin
$display (" Testing writeback data for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dbus = %b", dbus);
$display (" Correct dbus = %b", dbusout[k-4]);
if (dbusout[k-4] !== dbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
`timescale 1ns/10ps
module cpu3_testbench();
reg [31:0] ibustm[0:30], ibus;
wire [31:0] abus;
wire [31:0] bbus;
wire [31:0] dbus;
reg clk;
reg [31:0] dontcare, abusin[0:30], bbusin[0:30], dbusout[0:30];
integer error, k, ntests;
parameter ADDI = 6\'b000011;
parameter SUBI = 6\'b000010;
parameter XORI = 6\'b000001;
parameter ANDI = 6\'b001111;
parameter ORI = 6\'b001100;
parameter Rformat = 6\'b000000;
parameter ADD = 6\'b000011;
parameter SUB = 6\'b000010;
parameter XOR = 6\'b000001;
parameter AND = 6\'b000111;
parameter OR = 6\'b000100;
cpu3 dut(.ibus(ibus), .clk(clk), .abus(abus), .bbus(bbus), .dbus(dbus));
initial begin
// ----------
// 1. Begin test clear SUB R13, R0, R0
// ----------
// opcode source1 source2 dest shift Function...
ibustm[0]={Rformat, 5\'b00000, 5\'b00000, 5\'b01101, 5\'b00000, SUB};
abusin[0]=32\'h00000000;
bbusin[0]=32\'h00000000;
dbusout[0]=32\'h00000000;
// ----------
// 2. ADDI R1, R0, #0000
// ----------
// opcode source1 dest Immediate...
ibustm[1]={ADDI, 5\'b00000, 5\'b00001, 16\'h0000};
abusin[1]=32\'h00000000;
bbusin[1]=32\'h00000000;
dbusout[1]=32\'h00000000;
// ----------
// 3. Begin TEST # 0 ADDI R0, R0, #FFFF
// ----------
// opcode source1 dest Immediate...
ibustm[2]={ADDI, 5\'b00000, 5\'b00000, 16\'hFFFF};
abusin[2]=32\'h00000000;
bbusin[2]=32\'hFFFFFFFF;
dbusout[2]=32\'hFFFFFFFF;
// ----------
// 4. Begin TEST # 1 ADDI R30, R1,#AFC0
// ----------
// opcode source1 dest Immediate...
ibustm[3]={ADDI, 5\'b00001, 5\'b11110, 16\'hAFC0};
abusin[3]=32\'h00000000;
bbusin[3]=32\'hFFFFAFC0;
dbusout[3]=32\'hFFFFAFC0;
// ----------
// 5. Begin TEST # 2 SUB R0, R0, R0
// ----------
// opcode source1 source2 dest shift Function...
ibustm[4]={Rformat, 5\'b00000, 5\'b00000, 5\'b00000, 5\'b00000, SUB};
abusin[4]=32\'h00000000;
bbusin[4]=32\'h00000000;
dbusout[4]=32\'h00000000;
// ----------
// 6. Begin TEST # 3 ORI R3, R1, #7334
// ----------
// opcode source1 dest Immediate...
ibustm[5]={ORI, 5\'b00001, 5\'b00011, 16\'h7334};
abusin[5]=32\'h00000000;
bbusin[5]=32\'h00007334;
dbusout[5]=32\'h00007334;
// ----------
// 7. Begin TEST # 4 ORI R21, R1, #F98B
// ----------
// opcode source1 dest Immediate...
ibustm[6]={ORI, 5\'b00001, 5\'b10101, 16\'hF98B};
abusin[6]=32\'h00000000;
bbusin[6]=32\'hFFFFF98B;
dbusout[6]=32\'hFFFFF98B;
// ----------
// 8. Begin TEST # 5 XOR R16, R1, R3
// ----------
// opcode source1 source2 dest shift Function...
ibustm[7]={Rformat, 5\'b00001, 5\'b00011, 5\'b10000, 5\'b00000, XOR};
abusin[7]=32\'h00000000;
bbusin[7]=32\'h00007334;
dbusout[7]=32\'h00007334;
// ----------
// 9. Begin TEST # 6 SUBI R31, R21, #0030
// ----------
// opcode source1 dest Immediate...
ibustm[8]={SUBI, 5\'b10101, 5\'b11111, 16\'h0030};
abusin[8]=32\'hFFFFF98B;
bbusin[8]=32\'h00000030;
dbusout[8]=32\'hFFFFF95B;
// ----------
// 10. Begin TEST # 7 ORI R5, R1, #8ABF
// ----------
// opcode source1 dest Immediate...
ibustm[9]={ORI, 5\'b00001, 5\'b00101, 16\'h8ABF};
abusin[9]=32\'h00000000;
bbusin[9]=32\'hFFFF8ABF;
dbusout[9]=32\'hFFFF8ABF;
// ------------
// 11. Begin TEST # 8 ORI R10, R1, #34FB
// ------------
// opcode source1 dest Immediate...
ibustm[10]={ORI, 5\'b00001, 5\'b01010, 16\'h34FB};
abusin[10]=32\'h00000000;
bbusin[10]=32\'h000034FB;
dbusout[10]=32\'h000034FB;
// ------------
// 12. Begin TEST # 9 XORI R18, R1, #0B31
// ------------
// opcode source1 dest Immediate...
ibustm[11]={XORI, 5\'b00001, 5\'b10010, 16\'h0B31};
abusin[11]=32\'h00000000;
bbusin[11]=32\'h00000B31;
dbusout[11]=32\'h00000B31;
// ---------
// 13. Begin TEST # 10 ADD R24, R16, R3
// ---------
// opcode source1 source2 dest shift Function...
ibustm[12]={Rformat, 5\'b10000, 5\'b00011, 5\'b11000, 5\'b00000, ADD};
abusin[12]=32\'h00007334;
bbusin[12]=32\'h00007334;
dbusout[12]=32\'h0000E668;
// ---------
// 14. Begin TEST # 11 OR R7, R10, R10
// ---------
// opcode source1 source2 dest shift Function...
ibustm[13]={Rformat, 5\'b01010, 5\'b01010, 5\'b00111, 5\'b00000, OR};
abusin[13]=32\'h000034FB;
bbusin[13]=32\'h000034FB;
dbusout[13]=32\'h000034FB;
// ---------
// 15. Begin TEST # 12 XORI R12, R21, #00F0
// ---------
// opcode source1 dest Immediate...
ibustm[14]={XORI, 5\'b10101, 5\'b01100, 16\'h00F0};
abusin[14]=32\'hFFFFF98B;
bbusin[14]=32\'h000000F0;
dbusout[14]=32\'hFFFFF97B;
// ---------
// 16. Begin TEST # 13 SUBI R28, R31, #0111
// ---------
// opcode source1 dest Immediate...
ibustm[15]={SUBI, 5\'b11111, 5\'b11100, 16\'h0111};
abusin[15]=32\'hFFFFF95B;
bbusin[15]=32\'h00000111;
dbusout[15]=32\'hFFFFF84A;
// ---------
// 17. Begin TEST # 14 ADD R17, R3, R21
// ---------
// opcode source1 source2 dest shift Function...
ibustm[16]={Rformat, 5\'b00011, 5\'b10101, 5\'b10001, 5\'b00000, ADD};
abusin[16]=32\'h00007334;
bbusin[16]=32\'hFFFFF98B;
dbusout[16]=32\'h00006CBF;
// ----------
// 18. Begin TEST # 15 ORI R15, R1, #328F
// ----------
// opcode source1 dest Immediate...
ibustm[17]={ORI, 5\'b00001, 5\'b01111, 16\'h328F};
abusin[17]=32\'h00000000;
bbusin[17]=32\'h0000328F;
dbusout[17]=32\'h0000328F;
// ---------
// 19. Begin TEST # 16 ADDI R13, R13, #FFFF
// ---------
// opcode source1 dest Immediate...
ibustm[18]={ADDI, 5\'b01101, 5\'b01101, 16\'hFFFF};
abusin[18]=32\'h00000000;
bbusin[18]=32\'hFFFFFFFF;
dbusout[18]=32\'hFFFFFFFF;
// ---------
// 20. Begin TEST # 17 ADDI R23, R1, #AFC0
// ---------
// opcode source1 dest Immediate...
ibustm[19]={ADDI, 5\'b00001, 5\'b10111, 16\'hAFC0};
abusin[19]=32\'h00000000;
bbusin[19]=32\'hFFFFAFC0;
dbusout[19]=32\'hFFFFAFC0;
// ---------
// 21. Begin TEST # 18 SUB R20, R1, R1
// ---------
// opcode source1 source2 dest shift Function...
ibustm[20]={Rformat, 5\'b00001, 5\'b00001, 5\'b10100, 5\'b00000, SUB};
abusin[20]=32\'h00000000;
bbusin[20]=32\'h00000000;
dbusout[20]=32\'h00000000;
// ----------
// 22. Begin TEST # 19 ORI R19, R1, #7334
// ----------
// opcode source1 dest Immediate...
ibustm[21]={ORI, 5\'b00001, 5\'b10011, 16\'h7334};
abusin[21]=32\'h00000000;
bbusin[21]=32\'h00007334;
dbusout[21]=32\'h00007334;
// --------
// 23. Begin TEST # 20 ORI R9, R13, #F98B
// --------
// opcode source1 dest Immediate...
ibustm[22]={ORI, 5\'b01101, 5\'b01001, 16\'hF98B};
abusin[22]=32\'hFFFFFFFF;
bbusin[22]=32\'hFFFFF98B;
dbusout[22]=32\'hFFFFFFFF;
// --------
// 24. Begin TEST # 21 XOR R2, R13, R19
// --------
// opcode source1 source2 dest shift Function...
ibustm[23]={Rformat, 5\'b01101, 5\'b10011, 5\'b00010, 5\'b00000, XOR};
abusin[23]=32\'hFFFFFFFF;
bbusin[23]=32\'h00007334;
dbusout[23]=32\'hFFFF8CCB;
// --------
// 25. Begin TEST # 22 SUBI R26, R9, #0030
// --------
// opcode source1 dest Immediate...
ibustm[24]={SUBI, 5\'b01001, 5\'b11010, 16\'h0030};
abusin[24]=32\'hFFFFFFFF;
bbusin[24]=32\'h00000030;
dbusout[24]=32\'hFFFFFFCF;
// --------
// 26. Begin TEST # 23 ORI R25, R1, #8ABF
// --------
// opcode source1 dest Immediate...
ibustm[25]={ORI, 5\'b00001, 5\'b11001, 16\'h8ABF};
abusin[25]=32\'h00000000;
bbusin[25]=32\'hFFFF8ABF;
dbusout[25]=32\'hFFFF8ABF;
// --------
// 27. Begin TEST # 24 ORI R8, R13, #34FB
// --------
// opcode source1 dest Immediate...
ibustm[26]={ORI, 5\'b01101, 5\'b01000, 16\'h34FB};
abusin[26]=32\'hFFFFFFFF;
bbusin[26]=32\'h000034FB;
dbusout[26]=32\'hFFFFFFFF;
// --------
// 28. Begin TEST # 25 XORI R27, R13, #0B31
// --------
// opcode source1 dest Immediate...
ibustm[27]={XORI, 5\'b01101, 5\'b11011, 16\'h0B31};
abusin[27]=32\'hFFFFFFFF;
bbusin[27]=32\'h00000B31;
dbusout[27]=32\'hFFFFF4CE;
// --------
// 29. Begin TEST # 26 ADD R14, R2, R19
// --------
// opcode source1 source2 dest shift Function...
ibustm[28]={Rformat, 5\'b00010, 5\'b10011, 5\'b01110, 5\'b00000, ADD};
abusin[28]=32\'hFFFF8CCB;
bbusin[28]=32\'h00007334;
dbusout[28]=32\'hFFFFFFFF;
// --------
// 30. Begin TEST # 27 OR R4, R8, R8
// --------
// opcode source1 source2 dest shift Function...
ibustm[29]={Rformat, 5\'b01000, 5\'b01000, 5\'b00100, 5\'b00000, OR};
abusin[29]=32\'hFFFFFFFF;
bbusin[29]=32\'hFFFFFFFF;
dbusout[29]=32\'hFFFFFFFF;
// --------
// 31. Begin TEST # 28 XORI R12, R21, #5555
// --------
// opcode source1 dest Immediate...
ibustm[30]={XORI, 5\'b10101, 5\'b01100, 16\'h5555};
abusin[30]=32\'hFFFFF98B;
bbusin[30]=32\'h00005555;
dbusout[30]=32\'hFFFFACDE;
// 31*2
ntests = 62;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
clk=0;
for (k=0; k<= 30; k=k+1) begin
//check input operands from 2nd previous instruction
$display ("Time=%t\
clk=%b", $realtime, clk);
if (k >= 3) begin
$display (" Testing input operands for instruction %d", k-3);
$display (" Your abus = %b", abus);
$display (" Correct abus = %b", abusin[k-3]);
$display (" Your bbus = %b", bbus);
$display (" Correct bbus = %b", bbusin[k-3]);
if ((abusin[k-3] !== abus) ||(bbusin[k-3] !== bbus)) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk=1;
#25\t
//check output operand from 3rd previous instruction on bbus
$display ("Time=%t\
clk=%b", $realtime, clk);
if (k >= 3) begin
$display (" Testing output operand for instruction %d", k-3);
$display (" Your dbus = %b", dbus);
$display (" Correct dbus = %b", dbusout[k-3]);
if (dbusout[k-3] !== dbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
ibus=ibustm[k];
$display (" ibus=%b %b %b %b %b for instruction %d", ibus[31:26], ibus[25:21], ibus[20:16], ibus[15:11], ibus[10:0], k);
clk = 0;
#25
error = error;
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule |
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
//phase 5: testing the branch command (basic forced branch)
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:37];
wire [63:0] iaddrbus, daddrbus;
reg [63:0] iaddrbusout[0:37], daddrbusout[0:37];
wire [63:0] databus;
reg [63:0] databusk, databusin[0:37], databusout[0:37];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [24*8:1] iname[0:37];
integer error, k, ntests;
//all opcode parameters to be used
parameter ADD = 11\'b10001011000;
parameter ADDI = 10\'b1001000100;
parameter ADDIS = 10\'b1011000100;
parameter ADDS = 11\'b10101011000;
parameter AND = 11\'b10001010000;
parameter ANDI = 10\'b1001001000;
parameter ANDIS = 10\'b1111001000;
parameter ANDS = 11\'b11101010000;
parameter CBNZ = 8\'b10110101;
parameter CBZ = 8\'b10110100;
parameter EOR = 11\'b11001010000;
parameter EORI = 10\'b1101001000;
parameter LDUR = 11\'b11111000010;
parameter LSL = 11\'b11010011011;
parameter LSR = 11\'b11010011010;
parameter MOVZ = 9\'b110100101;
parameter ORR = 11\'b10101010000;
parameter ORRI = 10\'b1011001000;
parameter STUR = 11\'b11111000000;
parameter SUB = 11\'b11001011000;
parameter SUBI = 10\'b1101000100;
parameter SUBIS = 10\'b1111000100;
parameter SUBS = 11\'b11101011000;
parameter B = 6\'b000101;
parameter B_EQ = 8\'b01010101;
parameter B_NE = 8\'b01010110;
parameter B_LT = 8\'b01010111;
parameter B_GT = 8\'b01011000;
//register parameters
parameter R0 = 5\'b00000;
parameter R15 = 5\'b01111;
parameter R16 = 5\'b10000;
parameter R17 = 5\'b10001;
parameter R18 = 5\'b10010;
parameter R19 = 5\'b10011;
parameter R20 = 5\'b10100;
parameter R21 = 5\'b10101;
parameter R22 = 5\'b10110;
parameter R23 = 5\'b10111;
parameter R24 = 5\'b11000;
parameter R25 = 5\'b11001;
parameter R26 = 5\'b11010;
parameter R27 = 5\'b11011;
parameter R28 = 5\'b11100;
parameter R29 = 5\'b11101;
parameter R30 = 5\'b11110;
parameter R31 = 5\'b11111;
//other parameterz to be used
parameter zeroSham = 6\'b000000;
parameter RX = 5\'b11111;
parameter oneShamt = 6\'b000001;
parameter twoShamt = 6\'b000010;
parameter threeShamt = 6\'b000011;
parameter eightShamt = 6\'b001000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
dontcare = 64\'hx;
//phase 1: testing basic op commands
// op, rd, rn, rm
iname[0] ="ADDI, R20, R31, #AAA";//testing addi, result in R20 = 0000000000000AAA
iaddrbusout[0] = 64\'h00000000;
// opcode rm/ALUImm rn rd
instrbusin[0] ={ADDI, 12\'hAAA, R31, R20};
daddrbusout[0] = dontcare;
databusin[0] = 64\'bz;
databusout[0] = dontcare;
// op, rd, rn, rm
iname[1] ="ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 0000000000000000
iaddrbusout[1] = 64\'h00000004;
// opcode rm/ALUImm rn rd
instrbusin[1] ={ADDI, 12\'h002, R23, R31};
daddrbusout[1] = dontcare;
databusin[1] = 64\'bz;
databusout[1] = dontcare;
// op, rd, rn, rm
iname[2] ="ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 0000000000000002
iaddrbusout[2] = 64\'h00000008;
// opcode rm/ALUImm rn rd
instrbusin[2] ={ADDI, 12\'h002, R23, R0};
daddrbusout[2] = dontcare;
databusin[2] = 64\'bz;
databusout[2] = dontcare;
// op, rd, rn, rm
iname[3] ="ORRI, R21, R24, #001";//testing ori, result in R21 = 0000000000000001
iaddrbusout[3] = 64\'h0000000C;
// opcode rm/ALUImm rn rd
instrbusin[3] ={ORRI, 12\'h001, R24, R21};
daddrbusout[3] = dontcare;
databusin[3] = 64\'bz;
databusout[3] = dontcare;
// op, rd, rn, rm
iname[4] ="EORI, R22, R20, #000";//testing xori, result in R22 = 0000000000000AAA
iaddrbusout[4] = 64\'h00000010;
// opcode rm/ALUImm rn rd
instrbusin[4] ={EORI, 12\'h000, R20, R22};
daddrbusout[4] = dontcare;
databusin[4] = 64\'bz;
databusout[4] = dontcare;
// op, rd, rn, rm
iname[5] ="ANDI, R23, R0, #003";//testing andi, result in R23 = 0000000000000002
iaddrbusout[5] = 64\'h00000014;
// opcode rm/ALUImm rn rd
instrbusin[5] ={ANDI, 12\'h003, R0, R23};
daddrbusout[5] = dontcare;
databusin[5] = 64\'bz;
databusout[5] = dontcare;
// op, rd, rn, rm
iname[6] ="SUBI, R24, R20, #00A";//testing subi, result in R24 = 0000000000000AA0
iaddrbusout[6] = 64\'h00000018;
// opcode rm/ALUImm rn rd
instrbusin[6] ={SUBI, 12\'h00A, R20, R24};
daddrbusout[6] = dontcare;
databusin[6] = 64\'bz;
databusout[6] = dontcare;
// op, rd, rn, rm
iname[7] ="ADD, R25, R20, R0";//testing add, result in R25 = 0000000000000AAC
iaddrbusout[7] = 64\'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7] ={ADD, R0, zeroSham, R20, R25};
daddrbusout[7] = dontcare;
databusin[7] = 64\'bz;
databusout[7] = dontcare;
// op, rd, rn, rm
iname[8] ="AND, R26, R20, R22";//testing and, result in R26 = 0000000000000AAA
iaddrbusout[8] = 64\'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8] ={AND, R22, zeroSham, R20, R26};
daddrbusout[8] = dontcare;
databusin[8] = 64\'bz;
databusout[8] = dontcare;
// op, rd, rn, rm
iname[9] ="EOR, R27, R23, R21";//testing xor, result in R27 = 0000000000000003
iaddrbusout[9] = 64\'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9] ={EOR, R21, zeroSham, R23, R27};
daddrbusout[9] = dontcare;
databusin[9] = 64\'bz;
databusout[9] = dontcare;
// op, rd, rn, rm
iname[10] ="ORR, R28, R25, R23";//testing or, result in R28 = 0000000000000AAE
iaddrbusout[10] = 64\'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10] ={ORR, R23, zeroSham, R25, R28};
daddrbusout[10] = dontcare;
databusin[10] = 64\'bz;
databusout[10] = dontcare;
// op, rd, rn, rm
iname[11] ="SUB, R29, R20, R22";//testing sub, result in R29 = 0000000000000000
iaddrbusout[11] = 64\'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11] ={SUB, R22, zeroSham, R20, R29};
daddrbusout[11] = dontcare;
databusin[11] = 64\'bz;
databusout[11] = dontcare;
// op, rd, rn, aluImm
iname[12] ="ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 0000000000000000
iaddrbusout[12] = 64\'h00000030;
// opcode rm/ALUImm rn rd
instrbusin[12] ={ADDI, 12\'h000, R31, R30};
daddrbusout[12] = dontcare;
databusin[12] = 64\'bz;
databusout[12] = dontcare;
//phase 2: testing basic op codes with the set flags
// op, rd, rn, aluImm
iname[13] ="SUBIS,R20, R0, #003";//testing subis, n flag, result in R20 = FFFFFFFFFFFFFFFF
iaddrbusout[13] = 64\'h00000034;
// opcode rm/ALUImm rn rd
instrbusin[13] ={SUBIS, 12\'h003, R0, R20};
daddrbusout[13] = dontcare;
databusin[13] = 64\'bz;
databusout[13] = dontcare;
// op, rd, rn, rm
iname[14] ="SUBS, R21, R25, R28";//testing subs, n flag, result in R21 = FFFFFFFFFFFFFFFE
iaddrbusout[14] = 64\'h00000038;
// op, rm, shamt, rn, rd
instrbusin[14] ={SUBS,R28,zeroSham, R25, R21};
daddrbusout[14] = dontcare;
databusin[14] = 64\'bz;
databusout[14] = dontcare;
// op, rd, rn, aluImm
iname[15] ="ADDIS,R22, R31, #000";//testing addis, z flag, result in R22 = 0000000000000000
iaddrbusout[15] = 64\'h0000003C;
// opcode rm/ALUImm rn rd
instrbusin[15] ={ADDIS, 12\'h000, R31, R22};
daddrbusout[15] = dontcare;
databusin[15] = 64\'bz;
databusout[15] = dontcare;
// op, rd, rn, rm
iname[16] ="ADDS R23, R20, R23";//testing adds, c flag, result in R23 = 0000000000000001
iaddrbusout[16] = 64\'h00000040;
// op, rm, shamt, rn, rd
instrbusin[16] ={ADDS,R23,zeroSham, R20, R23};
daddrbusout[16] = dontcare;
databusin[16] = 64\'bz;
databusout[16] = dontcare;
// op, rd, rn, aluImm
iname[17] ="ANDIS,R24, R20, #002";//testing andis, reseting n,z flags to low, result in R24 = 0000000000000002
iaddrbusout[17] = 64\'h00000044;
// opcode rm/ALUImm rn rd
instrbusin[17] ={ANDIS, 12\'h002, R20, R24};
daddrbusout[17] = dontcare;
databusin[17] = 64\'bz;
databusout[17] = dontcare;
// op, rd, rn, rm
iname[18] ="ANDS, R25, R21, R20";//testing ands, n flag, result in R25 = FFFFFFFFFFFFFFFE
iaddrbusout[18] = 64\'h00000048;
// op, rm, shamt, rn, rd
instrbusin[18] ={ANDS, R20, zeroSham, R21, R25};
daddrbusout[18] = dontcare;
databusin[18] = 64\'bz;
databusout[18] = dontcare;
//phase 3: testing LSL, LSR
//setting up the register R20 for a test of the LSL
// op, rd, rn, rm
iname[19] ="ADDI, R20, R31, #007";//setting up for left shift, result in R20 = 0000000000000007
iaddrbusout[19] = 64\'h0000004C;
// opcode rm/ALUImm rn rd
instrbusin[19] ={ADDI, 12\'h007, R31, R20};
daddrbusout[19] = dontcare;
databusin[19] = 64\'bz;
databusout[19] = dontcare;
// op, rd, rn, rm
iname[20] ="ADDI, R21, R31, #700";//setting up for right shift, n flag, result in R21 = 0000000000000700
iaddrbusout[20] = 64\'h00000050;
// opcode rm/ALUImm rn rd
instrbusin[20] ={ADDI, 12\'h700, R31, R21};
daddrbusout[20] = dontcare;
databusin[20] = 64\'bz;
databusout[20] = dontcare;
// op, rd, rn, rm
iname[21] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[21] = 64\'h00000054;
// op, rm, shamt, rn, rd
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
daddrbusout[21] = dontcare;
databusin[21] = 64\'bz;
databusout[21] = dontcare;
// op, rd, rn, rm
iname[22] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[22] = 64\'h00000058;
// op, rm, shamt, rn, rd
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
daddrbusout[22] = dontcare;
databusin[22] = 64\'bz;
databusout[22] = dontcare;
// op, rd, rn, rm
iname[23] ="LSL, R20, R20, 2";//testing left shift, result in R20 = 0000000000000700
iaddrbusout[23] = 64\'h0000005C;
// op, rm, shamt, rn, rd
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
daddrbusout[23] = dontcare;
databusin[23] = 64\'bz;
databusout[23] = dontcare;
// op, rd, rn, rm
iname[24] ="LSR, R21, R21, 2";//testing right shift, result in R21 = 0000000000000007
iaddrbusout[24] = 64\'h00000060;
// op, rm, shamt, rn, rd
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
daddrbusout[24] = dontcare;
databusin[24] = 64\'bz;
databusout[24] = dontcare;
//phase 4: testing load and store
// op, rt, rn, DT_adr
iname[25] ="LDUR, R22, R31, #1";//testing load, result in R22 = 42069 (from memory,databusin) [yes, really]
iaddrbusout[25] = 64\'h00000064;
// op, DT_ADDR, ?, rn, rt
instrbusin[25] ={LDUR, 9\'b000000001, 2\'b00, R31, R22};
daddrbusout[25] = 64\'h0000000000000001;//used for LDUR
databusin[25] = 64\'h0000000000042069;//used for LDUR
databusout[25] = dontcare;
// op, rn, DT_adr, rt
iname[26] ="STUR, R23, #068, R24";//testing story, result for databusout in R24 = 0000000000000002 (to memory)
//address is calculated from imm or 68, and R23, which is currently 1
iaddrbusout[26] = 64\'h00000068;
// op, DT_ADDR, ?, rn, rt
instrbusin[26] ={STUR, 9\'b001101000, 2\'b00, R23, R24};
daddrbusout[26] = 64\'h0000000000000069;//used for STUR
databusin[26] = 64\'bz;
databusout[26] = 64\'h0000000000000002;//used for STUR
// op, rd, rn, rm
iname[27] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[27] = 64\'h0000006C;
// op, rm, shamt, rn, rd
instrbusin[27] ={AND, R31, zeroSham, R31, R19};
daddrbusout[27] = dontcare;
databusin[27] = 64\'bz;
databusout[27] = dontcare;
// op, rd, rn, rm
iname[28] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[28] = 64\'h00000070;
// op, rm, shamt, rn, rd
instrbusin[28] ={AND, R31, zeroSham, R31, R19};
daddrbusout[28] = dontcare;
databusin[28] = 64\'bz;
databusout[28] = dontcare;
// op, rd, rn, rm
iname[29] ="AND, R17, R31, R31";//delay, result in R17 = 0000000000000000
iaddrbusout[29] = 64\'h00000074;
// op, rm, shamt, rn, rd
instrbusin[29] ={AND, R31, zeroSham, R31, R19};
daddrbusout[29] = dontcare;
databusin[29] = 64\'bz;
databusout[29] = dontcare;
//phase 5: testing B branch
// op, BR_address
iname[30] ="B, #EA";//testing branch, calculated branch address should be
// (64\'h0000000000000078 + 64\'h000000000000003A8 = 64\'h0000000000000420)
iaddrbusout[30] = 64\'h00000078;
// op, BR_address
instrbusin[30] ={B, 26\'b00000000000000000011101010};
daddrbusout[30] = dontcare;
databusin[30] = 64\'bz;
databusout[30] = dontcare;
// op, rd, rn, rm
iname[31] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[31] = 64\'h0000007C;
// op, rm, shamt, rn, rd
instrbusin[31] ={AND, R31, zeroSham, R31, R19};
daddrbusout[31] = dontcare;
databusin[31] = 64\'bz;
databusout[31] = dontcare;
// op, rd, rn, rm
iname[32] ="ADD, R20, R21, R20";//testing branch address result in R20 = 0000000000000707
iaddrbusout[32] = 64\'h00000420;
// op, rm, shamt, rn, rd
instrbusin[32] ={ADD, R20, zeroSham, R21, R20};
daddrbusout[32] = dontcare;
databusin[32] = 64\'bz;
databusout[32] = dontcare;
//finishing up
iname[33] = "NOP";//nada
iaddrbusout[33] = 64\'h00000424;
instrbusin[33] = 64\'b0;
daddrbusout[33] = dontcare;
databusin[33] = 64\'bz;
databusout[33] = dontcare;
iname[34] = "NOP";//nada
iaddrbusout[34] = 64\'h00000428;
instrbusin[34] = 64\'b0;
daddrbusout[34] = dontcare;
databusin[34] = 64\'bz;
databusout[34] = dontcare;
iname[35] = "NOP";//nada
iaddrbusout[35] = 64\'h0000042C;
instrbusin[35] = 64\'b0;
daddrbusout[35] = dontcare;
databusin[35] = 64\'bz;
databusout[35] = dontcare;
iname[36] = "NOP";//nada
iaddrbusout[36] = 64\'h00000430;
instrbusin[36] = 64\'b0;
daddrbusout[36] = dontcare;
databusin[36] = 64\'bz;
databusout[36] = dontcare;
iname[37] = "NOP";//nada
iaddrbusout[37] = 64\'h00000434;
instrbusin[37] = 64\'b0;
daddrbusout[37] = dontcare;
databusin[37] = 64\'bz;
databusout[37] = dontcare;
//also remember to set k down below to ntests - 1
ntests = 38;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
assign databus = clkd ? 64\'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
databusk = 64\'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
$display ("Time=%t\
clk=%b", $realtime, clk);
for (k=0; k<= 37; k=k+1) begin
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set load data for 3rd previous instruction
if (k >=3)
databusk = databusin[k-3];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check data address from 3rd previous instruction
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check store data from 3rd previous instruction
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
/************************
* Willard Wider
* 6-5-17
* ELEC3725
* alu32.v
* building a 32 bit ALU
************************/
`timescale 1ns / 1ps//Unit time
//The top module of the entire project. The declaration of the entire ALU itself.
module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;//the output bus
output Cout, V;//Cout is the bit for it it needs to carry over to the next circuit/ V is the overflow bit.
input [31:0] a, b;//the two input buses
input Cin;//the bit for marking if it is carrying over from a previous circuit
input [2:0] S;//The select bus. It defines the operation to do with input busses a and b
wire [31:0] c, g, p;
wire gout, pout;
//The core ALU bus
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
//the top Look-Ahead-Carry module.
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
//the overflow module
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule
//The module to handle a single bit operation for the top ALU module
module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;//acts as an inversion for the xnor so it can be processed as xor
g = a & bint;//used for overflow, uses xor and a value from a. covers case of last bit being high
p = a ^ bint;//xor, for xor and xnor
cint = S[1] & c;//for add or sub, already processed by the lacs
//if it's supposed to be a 1, it will be a 1 if the command is add or subtract
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;//or
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);//nor
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;//and
end
else
d = 1;
end
end
endmodule
//The module to handle the overflow bit
module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule
//Look-Ahead Carry unit level 1. Used for the root (level 1) and first child leafs (level 2)
module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule
//Look-Ahead Carry unit level 2. Contains LACs for the root and level 1. Used in level 3
module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 3. Contains LACs for the root and level 2. Used in level 4
module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 4. Contains LACs for the root and level 3. Used in level 5
module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 1. Caontains LACs for the root and level 4. Used in the core alu32 module
module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
|
//phase 8: testing MOVEZ and overflow bit
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:81];
wire [63:0] iaddrbus, daddrbus;
reg [63:0] iaddrbusout[0:81], daddrbusout[0:81];
wire [63:0] databus;
reg [63:0] databusk, databusin[0:81], databusout[0:81];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [24*8:1] iname[0:81];
integer error, k, ntests;
//all opcode parameters to be used
parameter ADD = 11\'b10001011000;
parameter ADDI = 10\'b1001000100;
parameter ADDIS = 10\'b1011000100;
parameter ADDS = 11\'b10101011000;
parameter AND = 11\'b10001010000;
parameter ANDI = 10\'b1001001000;
parameter ANDIS = 10\'b1111001000;
parameter ANDS = 11\'b11101010000;
parameter CBNZ = 8\'b10110101;
parameter CBZ = 8\'b10110100;
parameter EOR = 11\'b11001010000;
parameter EORI = 10\'b1101001000;
parameter LDUR = 11\'b11111000010;
parameter LSL = 11\'b11010011011;
parameter LSR = 11\'b11010011010;
parameter MOVZ = 9\'b110100101;
parameter ORR = 11\'b10101010000;
parameter ORRI = 10\'b1011001000;
parameter STUR = 11\'b11111000000;
parameter SUB = 11\'b11001011000;
parameter SUBI = 10\'b1101000100;
parameter SUBIS = 10\'b1111000100;
parameter SUBS = 11\'b11101011000;
parameter B = 6\'b000101;
parameter B_EQ = 8\'b01010101;
parameter B_NE = 8\'b01010110;
parameter B_LT = 8\'b01010111;
parameter B_GT = 8\'b01011000;
//register parameters
parameter R0 = 5\'b00000;
parameter R15 = 5\'b01111;
parameter R16 = 5\'b10000;
parameter R17 = 5\'b10001;
parameter R18 = 5\'b10010;
parameter R19 = 5\'b10011;
parameter R20 = 5\'b10100;
parameter R21 = 5\'b10101;
parameter R22 = 5\'b10110;
parameter R23 = 5\'b10111;
parameter R24 = 5\'b11000;
parameter R25 = 5\'b11001;
parameter R26 = 5\'b11010;
parameter R27 = 5\'b11011;
parameter R28 = 5\'b11100;
parameter R29 = 5\'b11101;
parameter R30 = 5\'b11110;
parameter R31 = 5\'b11111;
//other parameterz to be used
parameter zeroSham = 6\'b000000;
parameter RX = 5\'b11111;
parameter oneShamt = 6\'b000001;
parameter twoShamt = 6\'b000010;
parameter threeShamt = 6\'b000011;
parameter eightShamt = 6\'b001000;
parameter move_0 = 2\'b00;
parameter move_1 = 2\'b01;
parameter move_2 = 2\'b10;
parameter move_3 = 2\'b11;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
dontcare = 64\'hx;
//phase 1: testing basic op commands
// op, rd, rn, rm
iname[0] ="ADDI, R20, R31, #AAA";//testing addi, result in R20 = 0000000000000AAA
iaddrbusout[0] = 64\'h00000000;
// opcode rm/ALUImm rn rd
instrbusin[0] ={ADDI, 12\'hAAA, R31, R20};
daddrbusout[0] = dontcare;
databusin[0] = 64\'bz;
databusout[0] = dontcare;
// op, rd, rn, rm
iname[1] ="ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 0000000000000000
iaddrbusout[1] = 64\'h00000004;
// opcode rm/ALUImm rn rd
instrbusin[1] ={ADDI, 12\'h002, R23, R31};
daddrbusout[1] = dontcare;
databusin[1] = 64\'bz;
databusout[1] = dontcare;
// op, rd, rn, rm
iname[2] ="ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 0000000000000002
iaddrbusout[2] = 64\'h00000008;
// opcode rm/ALUImm rn rd
instrbusin[2] ={ADDI, 12\'h002, R23, R0};
daddrbusout[2] = dontcare;
databusin[2] = 64\'bz;
databusout[2] = dontcare;
// op, rd, rn, rm
iname[3] ="ORRI, R21, R24, #001";//testing ori, result in R21 = 0000000000000001
iaddrbusout[3] = 64\'h0000000C;
// opcode rm/ALUImm rn rd
instrbusin[3] ={ORRI, 12\'h001, R24, R21};
daddrbusout[3] = dontcare;
databusin[3] = 64\'bz;
databusout[3] = dontcare;
// op, rd, rn, rm
iname[4] ="EORI, R22, R20, #000";//testing xori, result in R22 = 0000000000000AAA
iaddrbusout[4] = 64\'h00000010;
// opcode rm/ALUImm rn rd
instrbusin[4] ={EORI, 12\'h000, R20, R22};
daddrbusout[4] = dontcare;
databusin[4] = 64\'bz;
databusout[4] = dontcare;
// op, rd, rn, rm
iname[5] ="ANDI, R23, R0, #003";//testing andi, result in R23 = 0000000000000002
iaddrbusout[5] = 64\'h00000014;
// opcode rm/ALUImm rn rd
instrbusin[5] ={ANDI, 12\'h003, R0, R23};
daddrbusout[5] = dontcare;
databusin[5] = 64\'bz;
databusout[5] = dontcare;
// op, rd, rn, rm
iname[6] ="SUBI, R24, R20, #00A";//testing subi, result in R24 = 0000000000000AA0
iaddrbusout[6] = 64\'h00000018;
// opcode rm/ALUImm rn rd
instrbusin[6] ={SUBI, 12\'h00A, R20, R24};
daddrbusout[6] = dontcare;
databusin[6] = 64\'bz;
databusout[6] = dontcare;
// op, rd, rn, rm
iname[7] ="ADD, R25, R20, R0";//testing add, result in R25 = 0000000000000AAC
iaddrbusout[7] = 64\'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7] ={ADD, R0, zeroSham, R20, R25};
daddrbusout[7] = dontcare;
databusin[7] = 64\'bz;
databusout[7] = dontcare;
// op, rd, rn, rm
iname[8] ="AND, R26, R20, R22";//testing and, result in R26 = 0000000000000AAA
iaddrbusout[8] = 64\'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8] ={AND, R22, zeroSham, R20, R26};
daddrbusout[8] = dontcare;
databusin[8] = 64\'bz;
databusout[8] = dontcare;
// op, rd, rn, rm
iname[9] ="EOR, R27, R23, R21";//testing xor, result in R27 = 0000000000000003
iaddrbusout[9] = 64\'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9] ={EOR, R21, zeroSham, R23, R27};
daddrbusout[9] = dontcare;
databusin[9] = 64\'bz;
databusout[9] = dontcare;
// op, rd, rn, rm
iname[10] ="ORR, R28, R25, R23";//testing or, result in R28 = 0000000000000AAE
iaddrbusout[10] = 64\'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10] ={ORR, R23, zeroSham, R25, R28};
daddrbusout[10] = dontcare;
databusin[10] = 64\'bz;
databusout[10] = dontcare;
// op, rd, rn, rm
iname[11] ="SUB, R29, R20, R22";//testing sub, result in R29 = 0000000000000000
iaddrbusout[11] = 64\'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11] ={SUB, R22, zeroSham, R20, R29};
daddrbusout[11] = dontcare;
databusin[11] = 64\'bz;
databusout[11] = dontcare;
// op, rd, rn, aluImm
iname[12] ="ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 0000000000000000
iaddrbusout[12] = 64\'h00000030;
// opcode rm/ALUImm rn rd
instrbusin[12] ={ADDI, 12\'h000, R31, R30};
daddrbusout[12] = dontcare;
databusin[12] = 64\'bz;
databusout[12] = dontcare;
//phase 2: testing basic op codes with the set flags
// op, rd, rn, aluImm
iname[13] ="SUBIS,R20, R0, #003";//testing subis, n flag, result in R20 = FFFFFFFFFFFFFFFF
iaddrbusout[13] = 64\'h00000034;
// opcode rm/ALUImm rn rd
instrbusin[13] ={SUBIS, 12\'h003, R0, R20};
daddrbusout[13] = dontcare;
databusin[13] = 64\'bz;
databusout[13] = dontcare;
// op, rd, rn, rm
iname[14] ="SUBS, R21, R25, R28";//testing subs, n flag, result in R21 = FFFFFFFFFFFFFFFE
iaddrbusout[14] = 64\'h00000038;
// op, rm, shamt, rn, rd
instrbusin[14] ={SUBS,R28,zeroSham, R25, R21};
daddrbusout[14] = dontcare;
databusin[14] = 64\'bz;
databusout[14] = dontcare;
// op, rd, rn, aluImm
iname[15] ="ADDIS,R22, R31, #000";//testing addis, z flag, result in R22 = 0000000000000000
iaddrbusout[15] = 64\'h0000003C;
// opcode rm/ALUImm rn rd
instrbusin[15] ={ADDIS, 12\'h000, R31, R22};
daddrbusout[15] = dontcare;
databusin[15] = 64\'bz;
databusout[15] = dontcare;
// op, rd, rn, rm
iname[16] ="ADDS R23, R20, R23";//testing adds, c flag, result in R23 = 0000000000000001
iaddrbusout[16] = 64\'h00000040;
// op, rm, shamt, rn, rd
instrbusin[16] ={ADDS,R23,zeroSham, R20, R23};
daddrbusout[16] = dontcare;
databusin[16] = 64\'bz;
databusout[16] = dontcare;
// op, rd, rn, aluImm
iname[17] ="ANDIS,R24, R20, #002";//testing andis, reseting n,z flags to low, result in R24 = 0000000000000002
iaddrbusout[17] = 64\'h00000044;
// opcode rm/ALUImm rn rd
instrbusin[17] ={ANDIS, 12\'h002, R20, R24};
daddrbusout[17] = dontcare;
databusin[17] = 64\'bz;
databusout[17] = dontcare;
// op, rd, rn, rm
iname[18] ="ANDS, R25, R21, R20";//testing ands, n flag, result in R25 = FFFFFFFFFFFFFFFE
iaddrbusout[18] = 64\'h00000048;
// op, rm, shamt, rn, rd
instrbusin[18] ={ANDS, R20, zeroSham, R21, R25};
daddrbusout[18] = dontcare;
databusin[18] = 64\'bz;
databusout[18] = dontcare;
//phase 3: testing LSL, LSR
//setting up the register R20 for a test of the LSL
// op, rd, rn, rm
iname[19] ="ADDI, R20, R31, #007";//setting up for left shift, result in R20 = 0000000000000007
iaddrbusout[19] = 64\'h0000004C;
// opcode rm/ALUImm rn rd
instrbusin[19] ={ADDI, 12\'h007, R31, R20};
daddrbusout[19] = dontcare;
databusin[19] = 64\'bz;
databusout[19] = dontcare;
// op, rd, rn, rm
iname[20] ="ADDI, R21, R31, #700";//setting up for right shift, n flag, result in R21 = 0000000000000700
iaddrbusout[20] = 64\'h00000050;
// opcode rm/ALUImm rn rd
instrbusin[20] ={ADDI, 12\'h700, R31, R21};
daddrbusout[20] = dontcare;
databusin[20] = 64\'bz;
databusout[20] = dontcare;
// op, rd, rn, rm
iname[21] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[21] = 64\'h00000054;
// op, rm, shamt, rn, rd
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
daddrbusout[21] = dontcare;
databusin[21] = 64\'bz;
databusout[21] = dontcare;
// op, rd, rn, rm
iname[22] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[22] = 64\'h00000058;
// op, rm, shamt, rn, rd
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
daddrbusout[22] = dontcare;
databusin[22] = 64\'bz;
databusout[22] = dontcare;
// op, rd, rn, rm
iname[23] ="LSL, R20, R20, 2";//testing left shift, result in R20 = 0000000000000700
iaddrbusout[23] = 64\'h0000005C;
// op, rm, shamt, rn, rd
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
daddrbusout[23] = dontcare;
databusin[23] = 64\'bz;
databusout[23] = dontcare;
// op, rd, rn, rm
iname[24] ="LSR, R21, R21, 2";//testing right shift, result in R21 = 0000000000000007
iaddrbusout[24] = 64\'h00000060;
// op, rm, shamt, rn, rd
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
daddrbusout[24] = dontcare;
databusin[24] = 64\'bz;
databusout[24] = dontcare;
//phase 4: testing load and store
// op, rt, rn, DT_adr
iname[25] ="LDUR, R22, R31, #1";//testing load, result in R22 = 42069 (from memory,databusin) [yes, really]
iaddrbusout[25] = 64\'h00000064;
// op, DT_ADDR, ?, rn, rt
instrbusin[25] ={LDUR, 9\'b000000001, 2\'b00, R31, R22};
daddrbusout[25] = 64\'h0000000000000001;//used for LDUR
databusin[25] = 64\'h0000000000042069;//used for LDUR
databusout[25] = dontcare;
// op, rn, DT_adr, rt
iname[26] ="STUR, R23, #068, R24";//testing story, result for databusout in R24 = 0000000000000002 (to memory)
//address is calculated from imm or 68, and R23, which is currently 1
iaddrbusout[26] = 64\'h00000068;
// op, DT_ADDR, ?, rn, rt
instrbusin[26] ={STUR, 9\'b001101000, 2\'b00, R23, R24};
daddrbusout[26] = 64\'h0000000000000069;//used for STUR
databusin[26] = 64\'bz;
databusout[26] = 64\'h0000000000000002;//used for STUR
// op, rd, rn, rm
iname[27] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[27] = 64\'h0000006C;
// op, rm, shamt, rn, rd
instrbusin[27] ={AND, R31, zeroSham, R31, R19};
daddrbusout[27] = dontcare;
databusin[27] = 64\'bz;
databusout[27] = dontcare;
// op, rd, rn, rm
iname[28] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[28] = 64\'h00000070;
// op, rm, shamt, rn, rd
instrbusin[28] ={AND, R31, zeroSham, R31, R19};
daddrbusout[28] = dontcare;
databusin[28] = 64\'bz;
databusout[28] = dontcare;
// op, rd, rn, rm
iname[29] ="AND, R17, R31, R31";//delay, result in R17 = 0000000000000000
iaddrbusout[29] = 64\'h00000074;
// op, rm, shamt, rn, rd
instrbusin[29] ={AND, R31, zeroSham, R31, R19};
daddrbusout[29] = dontcare;
databusin[29] = 64\'bz;
databusout[29] = dontcare;
//phase 5: testing B branch
// op, BR_address
iname[30] ="B, #EA";//testing branch, calculated branch address should be
// (64\'h0000000000000078 + 64\'h000000000000003A8 = 64\'h0000000000000420)
iaddrbusout[30] = 64\'h00000078;
// op, BR_address
instrbusin[30] ={B, 26\'b00000000000000000011101010};
daddrbusout[30] = dontcare;
databusin[30] = 64\'bz;
databusout[30] = dontcare;
// op, rd, rn, rm
iname[31] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[31] = 64\'h0000007C;
// op, rm, shamt, rn, rd
instrbusin[31] ={AND, R31, zeroSham, R31, R19};
daddrbusout[31] = dontcare;
databusin[31] = 64\'bz;
databusout[31] = dontcare;
// op, rd, rn, rm
iname[32] ="ADD, R20, R21, R20";//testing branch address result in R20 = 0000000000000707
iaddrbusout[32] = 64\'h00000420;
// op, rm, shamt, rn, rd
instrbusin[32] ={ADD, R20, zeroSham, R21, R20};
daddrbusout[32] = dontcare;
databusin[32] = 64\'bz;
databusout[32] = dontcare;
//phase 6: testing B.EQ and B.NE branch
// op, rd, rn, rm
iname[33] ="ADDI, R21, R31, #AAA";//testing addi, result in R21 = 0000000000000AAA
iaddrbusout[33] = 64\'h00000424;
// opcode rm/ALUImm rn rd
instrbusin[33] ={ADDI, 12\'hAAA, R31, R21};
daddrbusout[33] = dontcare;
databusin[33] = 64\'bz;
databusout[33] = dontcare;
// op, rd, rn, rm
iname[34] ="ADDI, R22, R31, #AAA";//testing addi, result in R22 = 0000000000000AAA
iaddrbusout[34] = 64\'h00000428;
// opcode rm/ALUImm rn rd
instrbusin[34] ={ADDI, 12\'hAAA, R31, R22};
daddrbusout[34] = dontcare;
databusin[34] = 64\'bz;
databusout[34] = dontcare;
//ADDIS for FAKE BRANCH
// op, rd, rn, aluImm
iname[35] ="ADDIS,R31, R31, #420";//testing fake branch, this should NOT set the Z high
iaddrbusout[35] = 64\'h0000042C;
// opcode rm/ALUImm rn rd
instrbusin[35] ={ADDIS, 12\'h420, R31, R31};
daddrbusout[35] = dontcare;
databusin[35] = 64\'bz;
databusout[35] = dontcare;
//FAKE BRANCH
// op, COND_addr, rt
iname[36] ="B_EQ, #69420, RX";//testing to NOT take the branch, Z should be LOW
iaddrbusout[36] = 64\'h00000430;
// op, COND_addr, rt
instrbusin[36] ={B_EQ, 19\'b1101001010000100000, RX};
daddrbusout[36] = dontcare;
databusin[36] = 64\'bz;
databusout[36] = dontcare;
iname[37] = "NOP";//nada
iaddrbusout[37] = 64\'h00000434;
instrbusin[37] = 64\'b0;
daddrbusout[37] = dontcare;
databusin[37] = 64\'bz;
databusout[37] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[38] ="SUBS, R31, R21, R22";//set z flag for BEQ,
iaddrbusout[38] = 64\'h00000438;
// op, rm, shamt, rn, rd
instrbusin[38] ={SUBS, R22, zeroSham, R21, R31};
daddrbusout[38] = dontcare;
databusin[38] = 64\'bz;
databusout[38] = dontcare;
//real branch for B.EQ (I have the best branches)
// op, COND_addr, rt
iname[39] ="B_EQ, #69, RX";//take the branch to instruction count ?
iaddrbusout[39] = 64\'h0000043C;
// op, COND_addr, rt
instrbusin[39] ={B_EQ, 19\'b0000000000001101001, RX};
//19\'b
daddrbusout[39] = dontcare;
databusin[39] = 64\'bz;
databusout[39] = dontcare;
iname[40] = "NOP";//nada
iaddrbusout[40] = 64\'h00000440;
instrbusin[40] = 64\'b0;
daddrbusout[40] = dontcare;
databusin[40] = 64\'bz;
databusout[40] = dontcare;
iname[41] = "NOP";//nada
iaddrbusout[41] = 64\'h000005E0;
instrbusin[41] = 64\'b0;
daddrbusout[41] = dontcare;
databusin[41] = 64\'bz;
databusout[41] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[42] ="SUBS, R31, R21, R20";//set z flag of NOT for BNE
iaddrbusout[42] = 64\'h000005E4;
// op, rm, shamt, rn, rd
instrbusin[42] ={SUBS, R20, zeroSham, R21, R31};
daddrbusout[42] = dontcare;
databusin[42] = 64\'bz;
databusout[42] = dontcare;
//test B.NE
// op, COND_addr, rt
iname[43] ="B_NE, #96, RX";//take the branch to instruction count 840
iaddrbusout[43] = 64\'h000005E8;
// op, COND_addr, rt
instrbusin[43] ={B_NE, 19\'b0000000000010010110, RX};
daddrbusout[43] = dontcare;
databusin[43] = 64\'bz;
databusout[43] = dontcare;
iname[44] = "NOP";//nada
iaddrbusout[44] = 64\'h000005EC;
instrbusin[44] = 64\'b0;
daddrbusout[44] = dontcare;
databusin[44] = 64\'bz;
databusout[44] = dontcare;
iname[45] = "NOP";//nada
iaddrbusout[45] = 64\'h00000840;
instrbusin[45] = 64\'b0;
daddrbusout[45] = dontcare;
databusin[45] = 64\'bz;
databusout[45] = dontcare;
//phase 7: testing CBNZ and CBZ branch
//DONT take the CBZ
// op, COND_addr, rt
iname[46] ="CBZ, #F, R22";//take the branch to instruction count
iaddrbusout[46] = 64\'h00000844;
// op, COND_addr, rt
instrbusin[46] ={CBZ, 19\'b0000000000000001111, R22};
daddrbusout[46] = dontcare;
databusin[46] = 64\'bz;
databusout[46] = dontcare;
iname[47] = "NOP";//nada
iaddrbusout[47] = 64\'h00000848;
instrbusin[47] = 64\'b0;
daddrbusout[47] = dontcare;
databusin[47] = 64\'bz;
databusout[47] = dontcare;
iname[48] = "NOP";//nada
iaddrbusout[48] = 64\'h0000084C;
instrbusin[48] = 64\'b0;
daddrbusout[48] = dontcare;
databusin[48] = 64\'bz;
databusout[48] = dontcare;
//TAKE the CBZ
// op, COND_addr, rt
iname[49] ="CBZ, #21, R19";//take the branch to instruction count
iaddrbusout[49] = 64\'h00000850;
// op, COND_addr, rt
instrbusin[49] ={CBZ, 19\'b0000000000000100001, R19};
daddrbusout[49] = dontcare;
databusin[49] = 64\'bz;
databusout[49] = dontcare;
iname[50] = "NOP";//nada
iaddrbusout[50] = 64\'h00000854;
instrbusin[50] = 64\'b0;
daddrbusout[50] = dontcare;
databusin[50] = 64\'bz;
databusout[50] = dontcare;
iname[51] = "NOP";//nada
iaddrbusout[51] = 64\'h000008D4;
instrbusin[51] = 64\'b0;
daddrbusout[51] = dontcare;
databusin[51] = 64\'bz;
databusout[51] = dontcare;
//DONT take the CBNZ
// op, COND_addr, rt
iname[52] ="CBNZ, #FF, R31";//take the branch to instruction count
iaddrbusout[52] = 64\'h000008D8;
// op, COND_addr, rt
instrbusin[52] ={CBNZ, 19\'b0000000000011111111, R31};
daddrbusout[52] = dontcare;
databusin[52] = 64\'bz;
databusout[52] = dontcare;
iname[53] = "NOP";//nada
iaddrbusout[53] = 64\'h000008DC;
instrbusin[53] = 64\'b0;
daddrbusout[53] = dontcare;
databusin[53] = 64\'bz;
databusout[53] = dontcare;
iname[54] = "NOP";//nada
iaddrbusout[54] = 64\'h000008E0;
instrbusin[54] = 64\'b0;
daddrbusout[54] = dontcare;
databusin[54] = 64\'bz;
databusout[54] = dontcare;
//TAKE the CBNZ
// op, COND_addr, rt
iname[55] ="CBNZ, #22, R20";//take the branch to instruction count
iaddrbusout[55] = 64\'h000008E4;
// op, COND_addr, rt
instrbusin[55] ={CBNZ, 19\'b0000000000000100010, R20};
daddrbusout[55] = dontcare;
databusin[55] = 64\'bz;
databusout[55] = dontcare;
iname[56] = "NOP";//nada
iaddrbusout[56] = 64\'h000008E8;
instrbusin[56] = 64\'b0;
daddrbusout[56] = dontcare;
databusin[56] = 64\'bz;
databusout[56] = dontcare;
iname[57] = "NOP";//nada
iaddrbusout[57] = 64\'h0000096C;
instrbusin[57] = 64\'b0;
daddrbusout[57] = dontcare;
databusin[57] = 64\'bz;
databusout[57] = dontcare;
//phase 8: testing MOVEZ and overflow bit
//4 instructions to set registers to 0
// op, rd, rn, rm
iname[58] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[58] = 64\'h00000970;
// op, rm, shamt, rn, rd
instrbusin[58] ={AND, R31, zeroSham, R31, R19};
daddrbusout[58] = dontcare;
databusin[58] = 64\'bz;
databusout[58] = dontcare;
// op, rd, rn, rm
iname[59] ="AND, R20, R31, R31";//delay, result in R20 = 0000000000000000
iaddrbusout[59] = 64\'h00000974;
// op, rm, shamt, rn, rd
instrbusin[59] ={AND, R31, zeroSham, R31, R20};
daddrbusout[59] = dontcare;
databusin[59] = 64\'bz;
databusout[59] = dontcare;
// op, rd, rn, rm
iname[60] ="AND, R21, R31, R31";//delay, result in R21 = 0000000000000000
iaddrbusout[60] = 64\'h00000978;
// op, rm, shamt, rn, rd
instrbusin[60] ={AND, R31, zeroSham, R31, R21};
daddrbusout[60] = dontcare;
databusin[60] = 64\'bz;
databusout[60] = dontcare;
// op, rd, rn, rm
iname[61] ="AND, R22, R31, R31";//delay, result in R22 = 0000000000000000
iaddrbusout[61] = 64\'h0000097C;
// op, rm, shamt, rn, rd
instrbusin[61] ={AND, R31, zeroSham, R31, R22};
daddrbusout[61] = dontcare;
databusin[61] = 64\'bz;
databusout[61] = dontcare;
//4 MOVZ commands
//move 0 amt
// op, move_amt, MOV_imm, rd
iname[62] ="MOVZ, move_0, #FFFF, R19";//testing move, result in R19 = 000000000000FFFF
iaddrbusout[62] = 64\'h00000980;
// op, move_amt, MOV_imm, rd
instrbusin[62] ={MOVZ, move_0, 16\'hFFFF, R19};
daddrbusout[62] = dontcare;
databusin[62] = 64\'bz;
databusout[62] = dontcare;
//move 1 amt
// op, move_amt, MOV_imm, rd
iname[63] ="MOVZ, move_1, #FFFF, R20";//testing move, result in R20 = 00000000FFFF0000
iaddrbusout[63] = 64\'h00000984;
// op, move_amt, MOV_imm, rd
instrbusin[63] ={MOVZ, move_1, 16\'hFFFF, R20};
daddrbusout[63] = dontcare;
databusin[63] = 64\'bz;
databusout[63] = dontcare;
//move 2 amt
// op, move_amt, MOV_imm, rd
iname[64] ="MOVZ, move_2, #FFFF, R21";//testing move, result in R21 = 0000FFFF00000000
iaddrbusout[64] = 64\'h00000988;
// op, move_amt, MOV_imm, rd
instrbusin[64] ={MOVZ, move_2, 16\'hFFFF, R21};
daddrbusout[64] = dontcare;
databusin[64] = 64\'bz;
databusout[64] = dontcare;
//move 3 amt
// op, move_amt, MOV_imm, rd
iname[65] ="MOVZ, move_3, #7FFF, R22";//testing move, result in R22 = 7FFF000000000000
iaddrbusout[65] = 64\'h0000098C;
// op, move_amt, MOV_imm, rd
instrbusin[65] ={MOVZ, move_3, 16\'h7FFF, R22};
daddrbusout[65] = dontcare;
databusin[65] = 64\'bz;
databusout[65] = dontcare;
//have or for move 0 and move 1
// op, rd, rn, rm
iname[66] ="ORR, R23, R19, R20";//testing xor, result in R23 = 00000000FFFFFFFF
iaddrbusout[66] = 64\'h00000990;
// op, rm, shamt, rn, rd
instrbusin[66] ={ORR, R20, zeroSham, R19, R23};
daddrbusout[66] = dontcare;
databusin[66] = 64\'bz;
databusout[66] = dontcare;
//delay
iname[67] = "NOP";//nada
iaddrbusout[67] = 64\'h00000994;
instrbusin[67] = 64\'b0;
daddrbusout[67] = dontcare;
databusin[67] = 64\'bz;
databusout[67] = dontcare;
//have or for move 2 and move 3
// op, rd, rn, rm
iname[68] ="ORR, R24, R21, R22";//testing xor, result in R27 = 7FFFFFFF00000000
iaddrbusout[68] = 64\'h00000998;
// op, rm, shamt, rn, rd
instrbusin[68] ={ORR, R22, zeroSham, R21, R24};
daddrbusout[68] = dontcare;
databusin[68] = 64\'bz;
databusout[68] = dontcare;
//delay
iname[69] = "NOP";//nada
iaddrbusout[69] = 64\'h0000099C;
instrbusin[69] = 64\'b0;
daddrbusout[69] = dontcare;
databusin[69] = 64\'bz;
databusout[69] = dontcare;
//delay
iname[70] = "NOP";//nada
iaddrbusout[70] = 64\'h000009A0;
instrbusin[70] = 64\'b0;
daddrbusout[70] = dontcare;
databusin[70] = 64\'bz;
databusout[70] = dontcare;
//have or for move(0|1) and move(2|3)
// op, rd, rn, rm
iname[71] ="ORR, R25, R23, R24";//testing xor, result in R25 = 7FFFFFFFFFFFFFFF
iaddrbusout[71] = 64\'h000009A4;
// op, rm, shamt, rn, rd
instrbusin[71] ={ORR, R24, zeroSham, R23, R25};
daddrbusout[71] = dontcare;
databusin[71] = 64\'bz;
databusout[71] = dontcare;
//dealy
iname[72] = "NOP";//nada
iaddrbusout[72] = 64\'h000009A8;
instrbusin[72] = 64\'b0;
daddrbusout[72] = dontcare;
databusin[72] = 64\'bz;
databusout[72] = dontcare;
//delay
iname[73] = "NOP";//nada
iaddrbusout[73] = 64\'h000009AC;
instrbusin[73] = 64\'b0;
daddrbusout[73] = dontcare;
databusin[73] = 64\'bz;
databusout[73] = dontcare;
//addis command to trigger the V bit
// op, rd, rn, aluImm
iname[74] ="ADDIS,R26, R25, #001";//testing xor and V bit, result in R26 = 8000000000000000
iaddrbusout[74] = 64\'h000009B0;
// opcode rm/ALUImm rn rd
instrbusin[74] ={ADDIS, 12\'h001, R25, R26};
daddrbusout[74] = dontcare;
databusin[74] = 64\'bz;
databusout[74] = dontcare;
iname[75] = "NOP";//nada
iaddrbusout[75] = 64\'h000009B4;
instrbusin[75] = 64\'b0;
daddrbusout[75] = dontcare;
databusin[75] = 64\'bz;
databusout[75] = dontcare;
iname[76] = "NOP";//nada
iaddrbusout[76] = 64\'h000009B8;
instrbusin[76] = 64\'b0;
daddrbusout[76] = dontcare;
databusin[76] = 64\'bz;
databusout[76] = dontcare;
//finishing up
iname[77] = "NOP";//nada
iaddrbusout[77] = 64\'h000009BC;
instrbusin[77] = 64\'b0;
daddrbusout[77] = dontcare;
databusin[77] = 64\'bz;
databusout[77] = dontcare;
iname[78] = "NOP";//nada
iaddrbusout[78] = 64\'h000009C0;
instrbusin[78] = 64\'b0;
daddrbusout[78] = dontcare;
databusin[78] = 64\'bz;
databusout[78] = dontcare;
iname[79] = "NOP";//nada
iaddrbusout[79] = 64\'h000009C4;
instrbusin[79] = 64\'b0;
daddrbusout[79] = dontcare;
databusin[79] = 64\'bz;
databusout[79] = dontcare;
iname[80] = "NOP";//nada
iaddrbusout[80] = 64\'h000009C8;
instrbusin[80] = 64\'b0;
daddrbusout[80] = dontcare;
databusin[80] = 64\'bz;
databusout[80] = dontcare;
iname[81] = "NOP";//nada
iaddrbusout[81] = 64\'h000009CC;
instrbusin[81] = 64\'b0;
daddrbusout[81] = dontcare;
databusin[81] = 64\'bz;
databusout[81] = dontcare;
//remember to set k down below to ntests - 1
ntests = 82;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
assign databus = clkd ? 64\'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
databusk = 64\'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
$display ("Time=%t\
clk=%b", $realtime, clk);
for (k=0; k<= 81; k=k+1) begin
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set load data for 3rd previous instruction
if (k >=3)
databusk = databusin[k-3];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check data address from 3rd previous instruction
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check store data from 3rd previous instruction
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
`timescale 1ns/10ps
module cpu4_testbench();
reg [0:31] ibus;
reg [0:31] ibusin[0:23];
wire [0:31] daddrbus;
reg [0:31] daddrbusout[0:23];
wire [0:31] databus;
reg [0:31] databusk, databusin[0:23], databusout[0:23];
reg clk;
reg clkd;
reg [0:31] dontcare;
reg [24*8:1] iname[0:23];
integer error, k, ntests;
parameter ADDI = 6\'b000011;
parameter SUBI = 6\'b000010;
parameter XORI = 6\'b000001;
parameter ANDI = 6\'b001111;
parameter ORI = 6\'b001100;
parameter LW = 6\'b011110;
parameter SW = 6\'b011111;
parameter Rformat = 6\'b000000;
parameter ADD = 6\'b000011;
parameter SUB = 6\'b000010;
parameter XOR = 6\'b000001;
parameter AND = 6\'b000111;
parameter OR = 6\'b000100;
cpu4 dut(.clk(clk),.ibus(ibus),.daddrbus(daddrbus),.databus(databus));
initial begin
// This test file runs the following program.
iname[0] = "ADDI R20, R0, #-1";
iname[1] = "ADDI R21, R0, #1";
iname[2] = "ADDI R22, R0, #2";
iname[3] = "LW R24, 0(R20)";
iname[4] = "LW R25, 0(R21)";
iname[5] = "SW 1000(R22), R20";
iname[6] = "SW 2(R0), R21";
iname[7] = "ADD R26, R24, R25";
iname[8] = "SUBI R17, R24, 6420";
iname[9] = "SUB R27, R24, R25";
iname[10] = "ANDI R18, R24, #0";
iname[11] = "AND R28, R24, R0";
iname[12] = "XORI R19, R24, 6420";
iname[13] = "XOR R29, R24, R25";
iname[14] = "ORI R20, R24, 6420";
iname[15] = "OR R30, R24, R25";
iname[16] = "SW 0(R26), R26";
iname[17] = "SW 0(R17), R27";
iname[18] = "SW 1000(R18), R28";
iname[19] = "SW 0(R19), R29";
iname[20] = "SW 0(R20), R30";
iname[21] = "NOP";
iname[22] = "NOP";
iname[23] = "NOP";
dontcare = 32\'hx;
// 1* ADDI R20, R0, #-1
// opcode source1 dest Immediate...
ibusin[0]={ADDI, 5\'b00000, 5\'b10100, 16\'hFFFF};
daddrbusout[0] = dontcare;
databusin[0] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[0] = dontcare;
// 2* ADDI R21, R0, #1
// opcode source1 dest Immediate...
ibusin[1]={ADDI, 5\'b00000, 5\'b10101, 16\'h0001};
daddrbusout[1] = dontcare;
databusin[1] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[1] = dontcare;
// 3* ADDI R22, R0, #2
// opcode source1 dest Immediate...
ibusin[2]={ADDI, 5\'b00000, 5\'b10110, 16\'h0002};
daddrbusout[2] = dontcare;
databusin[2] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[2] = dontcare;
// 4* LW R24, 0(R20)
// opcode source1 dest Immediate...
ibusin[3]={LW, 5\'b10100, 5\'b11000, 16\'h0000};
daddrbusout[3] = 32\'hFFFFFFFF;
databusin[3] = 32\'hCCCCCCCC;
databusout[3] = dontcare;
// 5* LW R25, 0(R21)
// opcode source1 dest Immediate...
ibusin[4]={LW, 5\'b10101, 5\'b11001, 16\'h0000};
daddrbusout[4] = 32\'h00000001;
databusin[4] = 32\'hAAAAAAAA;
databusout[4] = dontcare;
// 6* SW 1000(R22), R20
// opcode source1 dest Immediate...
ibusin[5]={SW, 5\'b10110, 5\'b10100, 16\'h1000};
daddrbusout[5] = 32\'h00001002;
databusin[5] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[5] = 32\'hFFFFFFFF;
// 7* SW 2(R0), R21
// opcode source1 dest Immediate...
ibusin[6]={SW, 5\'b00000, 5\'b10101, 16\'h0002};
daddrbusout[6] = 32\'h00000002;
databusin[6] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[6] = 32\'h00000001;
// 8* ADD R26, R24, R25
// opcode source1 source2 dest shift Function...
ibusin[7]={Rformat, 5\'b11000, 5\'b11001, 5\'b11010, 5\'b00000, ADD};
daddrbusout[7] = dontcare;
databusin[7] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[7] = dontcare;
// 9* SUBI R17, R24, 6420
// opcode source1 dest Immediate...
ibusin[8]={SUBI, 5\'b11000, 5\'b10001, 16\'h6420};
daddrbusout[8] = dontcare;
databusin[8] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[8] = dontcare;
// 10* SUB R27, R24, R25
// opcode source1 source2 dest shift Function...
ibusin[9]={Rformat, 5\'b11000, 5\'b11001, 5\'b11011, 5\'b00000, SUB};
daddrbusout[9] = dontcare;
databusin[9] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[9] = dontcare;
// 11* ANDI R18, R24, #0
// opcode source1 dest Immediate...
ibusin[10]={ANDI, 5\'b11000, 5\'b10010, 16\'h0000};
daddrbusout[10] = dontcare;
databusin[10] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[10] = dontcare;
// 12* AND R28, R24, R0
// opcode source1 source2 dest shift Function...
ibusin[11]={Rformat, 5\'b11000, 5\'b00000, 5\'b11100, 5\'b00000, AND};
daddrbusout[11] = dontcare;
databusin[11] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[11] = dontcare;
// 13* XORI R19, R24, 6420
// opcode source1 dest Immediate...
ibusin[12]={XORI, 5\'b11000, 5\'b10011, 16\'h6420};
daddrbusout[12] = dontcare;
databusin[12] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[12] = dontcare;
// 14* XOR R29, R24, R25
// opcode source1 source2 dest shift Function...
ibusin[13]={Rformat, 5\'b11000, 5\'b11001, 5\'b11101, 5\'b00000, XOR};
daddrbusout[13] = dontcare;
databusin[13] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[13] = dontcare;
// 15* ORI R20, R24, 6420
// opcode source1 dest Immediate...
ibusin[14]={ORI, 5\'b11000, 5\'b10100, 16\'h6420};
daddrbusout[14] = dontcare;
databusin[14] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[14] = dontcare;
// 16* OR R30, R24, R25
// opcode source1 source2 dest shift Function...
ibusin[15]={Rformat, 5\'b11000, 5\'b11001, 5\'b11110, 5\'b00000, OR};
daddrbusout[15] = dontcare;
databusin[15] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[15] = dontcare;
// 17* SW 0(R26), R26
// opcode source1 dest Immediate...
ibusin[16]={SW, 5\'b11010, 5\'b11010, 16\'h0000};
daddrbusout[16] = 32\'h77777776;
databusin[16] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[16] = 32\'h77777776;
// 18* SW 0(R17), R27
// opcode source1 dest Immediate...
ibusin[17]={SW, 5\'b10001, 5\'b11011, 16\'h0000};
daddrbusout[17] = 32\'hCCCC68AC;
databusin[17] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[17] = 32\'h22222222;
// 19* SW 1000(R18), R28
// opcode source1 dest Immediate...
ibusin[18]={SW, 5\'b10010, 5\'b11100, 16\'h1000};
daddrbusout[18] = 32\'h00001000;
databusin[18] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[18] = 32\'h00000000;
// 20* SW 0(R19), R29
// opcode source1 dest Immediate...
ibusin[19]={SW, 5\'b10011, 5\'b11101, 16\'h0000};
daddrbusout[19] = 32\'hCCCCA8EC;
databusin[19] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[19] = 32\'h66666666;
// 21* SW 0(R20), R30
// opcode source1 dest Immediate...
ibusin[20]={SW, 5\'b10100, 5\'b11110, 16\'h0000};
daddrbusout[20] = 32\'hCCCCECEC;
databusin[20] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[20] = 32\'hEEEEEEEE;
// 22* NOP
// oooooosssssdddddiiiiiiiiiiiiiiii
ibusin[21] = 32\'b00000000000000000000000000000000;
daddrbusout[21] = dontcare;
databusin[21] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[21] = dontcare;
// 23* NOP
// oooooosssssdddddiiiiiiiiiiiiiiii
ibusin[22] = 32\'b00000000000000000000000000000000;
daddrbusout[22] = dontcare;
databusin[22] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[22] = dontcare;
// 24* NOP
// oooooosssssdddddiiiiiiiiiiiiiiii
ibusin[23] = 32\'b00000000000000000000000000000000;
daddrbusout[23] = dontcare;
databusin[23] = 32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[23] = dontcare;
// (no. loads) + 2*(no. stores) = 2 + 2*7 = 16
ntests = 16;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
assign databus = clkd ? 32\'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =0;
clk=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
databusk = 32\'bz;
#25
$display ("Time=%t\
clk=%b", $realtime, clk);
for (k=0; k<= 23; k=k+1) begin
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clkd=1;
#20
$display ("Time=%t\
clk=%b", $realtime, clk);
//set load data for 3rd previous instruction
if (k >=3)
databusk = databusin[k-3];
//put next instruction on ibus
ibus=ibusin[k];
$display (" ibus=%b %b %b %b %b for instruction %d: %s", ibus[0:5], ibus[6:10], ibus[11:15], ibus[16:20], ibus[21:31], k, iname[k]);
//check data address from 3rd previous instruction
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check store data from 3rd previous instruction
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clkd = 0;
#20
$display ("Time=%t\
clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule |
//phase 7: testing CBNZ and CBZ branch
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:62];
wire [63:0] iaddrbus, daddrbus;
reg [63:0] iaddrbusout[0:62], daddrbusout[0:62];
wire [63:0] databus;
reg [63:0] databusk, databusin[0:62], databusout[0:62];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [24*8:1] iname[0:62];
integer error, k, ntests;
//all opcode parameters to be used
parameter ADD = 11\'b10001011000;
parameter ADDI = 10\'b1001000100;
parameter ADDIS = 10\'b1011000100;
parameter ADDS = 11\'b10101011000;
parameter AND = 11\'b10001010000;
parameter ANDI = 10\'b1001001000;
parameter ANDIS = 10\'b1111001000;
parameter ANDS = 11\'b11101010000;
parameter CBNZ = 8\'b10110101;
parameter CBZ = 8\'b10110100;
parameter EOR = 11\'b11001010000;
parameter EORI = 10\'b1101001000;
parameter LDUR = 11\'b11111000010;
parameter LSL = 11\'b11010011011;
parameter LSR = 11\'b11010011010;
parameter MOVZ = 9\'b110100101;
parameter ORR = 11\'b10101010000;
parameter ORRI = 10\'b1011001000;
parameter STUR = 11\'b11111000000;
parameter SUB = 11\'b11001011000;
parameter SUBI = 10\'b1101000100;
parameter SUBIS = 10\'b1111000100;
parameter SUBS = 11\'b11101011000;
parameter B = 6\'b000101;
parameter B_EQ = 8\'b01010101;
parameter B_NE = 8\'b01010110;
parameter B_LT = 8\'b01010111;
parameter B_GT = 8\'b01011000;
//register parameters
parameter R0 = 5\'b00000;
parameter R15 = 5\'b01111;
parameter R16 = 5\'b10000;
parameter R17 = 5\'b10001;
parameter R18 = 5\'b10010;
parameter R19 = 5\'b10011;
parameter R20 = 5\'b10100;
parameter R21 = 5\'b10101;
parameter R22 = 5\'b10110;
parameter R23 = 5\'b10111;
parameter R24 = 5\'b11000;
parameter R25 = 5\'b11001;
parameter R26 = 5\'b11010;
parameter R27 = 5\'b11011;
parameter R28 = 5\'b11100;
parameter R29 = 5\'b11101;
parameter R30 = 5\'b11110;
parameter R31 = 5\'b11111;
//other parameterz to be used
parameter zeroSham = 6\'b000000;
parameter RX = 5\'b11111;
parameter oneShamt = 6\'b000001;
parameter twoShamt = 6\'b000010;
parameter threeShamt = 6\'b000011;
parameter eightShamt = 6\'b001000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
dontcare = 64\'hx;
//phase 1: testing basic op commands
// op, rd, rn, rm
iname[0] ="ADDI, R20, R31, #AAA";//testing addi, result in R20 = 0000000000000AAA
iaddrbusout[0] = 64\'h00000000;
// opcode rm/ALUImm rn rd
instrbusin[0] ={ADDI, 12\'hAAA, R31, R20};
daddrbusout[0] = dontcare;
databusin[0] = 64\'bz;
databusout[0] = dontcare;
// op, rd, rn, rm
iname[1] ="ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 0000000000000000
iaddrbusout[1] = 64\'h00000004;
// opcode rm/ALUImm rn rd
instrbusin[1] ={ADDI, 12\'h002, R23, R31};
daddrbusout[1] = dontcare;
databusin[1] = 64\'bz;
databusout[1] = dontcare;
// op, rd, rn, rm
iname[2] ="ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 0000000000000002
iaddrbusout[2] = 64\'h00000008;
// opcode rm/ALUImm rn rd
instrbusin[2] ={ADDI, 12\'h002, R23, R0};
daddrbusout[2] = dontcare;
databusin[2] = 64\'bz;
databusout[2] = dontcare;
// op, rd, rn, rm
iname[3] ="ORRI, R21, R24, #001";//testing ori, result in R21 = 0000000000000001
iaddrbusout[3] = 64\'h0000000C;
// opcode rm/ALUImm rn rd
instrbusin[3] ={ORRI, 12\'h001, R24, R21};
daddrbusout[3] = dontcare;
databusin[3] = 64\'bz;
databusout[3] = dontcare;
// op, rd, rn, rm
iname[4] ="EORI, R22, R20, #000";//testing xori, result in R22 = 0000000000000AAA
iaddrbusout[4] = 64\'h00000010;
// opcode rm/ALUImm rn rd
instrbusin[4] ={EORI, 12\'h000, R20, R22};
daddrbusout[4] = dontcare;
databusin[4] = 64\'bz;
databusout[4] = dontcare;
// op, rd, rn, rm
iname[5] ="ANDI, R23, R0, #003";//testing andi, result in R23 = 0000000000000002
iaddrbusout[5] = 64\'h00000014;
// opcode rm/ALUImm rn rd
instrbusin[5] ={ANDI, 12\'h003, R0, R23};
daddrbusout[5] = dontcare;
databusin[5] = 64\'bz;
databusout[5] = dontcare;
// op, rd, rn, rm
iname[6] ="SUBI, R24, R20, #00A";//testing subi, result in R24 = 0000000000000AA0
iaddrbusout[6] = 64\'h00000018;
// opcode rm/ALUImm rn rd
instrbusin[6] ={SUBI, 12\'h00A, R20, R24};
daddrbusout[6] = dontcare;
databusin[6] = 64\'bz;
databusout[6] = dontcare;
// op, rd, rn, rm
iname[7] ="ADD, R25, R20, R0";//testing add, result in R25 = 0000000000000AAC
iaddrbusout[7] = 64\'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7] ={ADD, R0, zeroSham, R20, R25};
daddrbusout[7] = dontcare;
databusin[7] = 64\'bz;
databusout[7] = dontcare;
// op, rd, rn, rm
iname[8] ="AND, R26, R20, R22";//testing and, result in R26 = 0000000000000AAA
iaddrbusout[8] = 64\'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8] ={AND, R22, zeroSham, R20, R26};
daddrbusout[8] = dontcare;
databusin[8] = 64\'bz;
databusout[8] = dontcare;
// op, rd, rn, rm
iname[9] ="EOR, R27, R23, R21";//testing xor, result in R27 = 0000000000000003
iaddrbusout[9] = 64\'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9] ={EOR, R21, zeroSham, R23, R27};
daddrbusout[9] = dontcare;
databusin[9] = 64\'bz;
databusout[9] = dontcare;
// op, rd, rn, rm
iname[10] ="ORR, R28, R25, R23";//testing or, result in R28 = 0000000000000AAE
iaddrbusout[10] = 64\'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10] ={ORR, R23, zeroSham, R25, R28};
daddrbusout[10] = dontcare;
databusin[10] = 64\'bz;
databusout[10] = dontcare;
// op, rd, rn, rm
iname[11] ="SUB, R29, R20, R22";//testing sub, result in R29 = 0000000000000000
iaddrbusout[11] = 64\'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11] ={SUB, R22, zeroSham, R20, R29};
daddrbusout[11] = dontcare;
databusin[11] = 64\'bz;
databusout[11] = dontcare;
// op, rd, rn, aluImm
iname[12] ="ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 0000000000000000
iaddrbusout[12] = 64\'h00000030;
// opcode rm/ALUImm rn rd
instrbusin[12] ={ADDI, 12\'h000, R31, R30};
daddrbusout[12] = dontcare;
databusin[12] = 64\'bz;
databusout[12] = dontcare;
//phase 2: testing basic op codes with the set flags
// op, rd, rn, aluImm
iname[13] ="SUBIS,R20, R0, #003";//testing subis, n flag, result in R20 = FFFFFFFFFFFFFFFF
iaddrbusout[13] = 64\'h00000034;
// opcode rm/ALUImm rn rd
instrbusin[13] ={SUBIS, 12\'h003, R0, R20};
daddrbusout[13] = dontcare;
databusin[13] = 64\'bz;
databusout[13] = dontcare;
// op, rd, rn, rm
iname[14] ="SUBS, R21, R25, R28";//testing subs, n flag, result in R21 = FFFFFFFFFFFFFFFE
iaddrbusout[14] = 64\'h00000038;
// op, rm, shamt, rn, rd
instrbusin[14] ={SUBS,R28,zeroSham, R25, R21};
daddrbusout[14] = dontcare;
databusin[14] = 64\'bz;
databusout[14] = dontcare;
// op, rd, rn, aluImm
iname[15] ="ADDIS,R22, R31, #000";//testing addis, z flag, result in R22 = 0000000000000000
iaddrbusout[15] = 64\'h0000003C;
// opcode rm/ALUImm rn rd
instrbusin[15] ={ADDIS, 12\'h000, R31, R22};
daddrbusout[15] = dontcare;
databusin[15] = 64\'bz;
databusout[15] = dontcare;
// op, rd, rn, rm
iname[16] ="ADDS R23, R20, R23";//testing adds, c flag, result in R23 = 0000000000000001
iaddrbusout[16] = 64\'h00000040;
// op, rm, shamt, rn, rd
instrbusin[16] ={ADDS,R23,zeroSham, R20, R23};
daddrbusout[16] = dontcare;
databusin[16] = 64\'bz;
databusout[16] = dontcare;
// op, rd, rn, aluImm
iname[17] ="ANDIS,R24, R20, #002";//testing andis, reseting n,z flags to low, result in R24 = 0000000000000002
iaddrbusout[17] = 64\'h00000044;
// opcode rm/ALUImm rn rd
instrbusin[17] ={ANDIS, 12\'h002, R20, R24};
daddrbusout[17] = dontcare;
databusin[17] = 64\'bz;
databusout[17] = dontcare;
// op, rd, rn, rm
iname[18] ="ANDS, R25, R21, R20";//testing ands, n flag, result in R25 = FFFFFFFFFFFFFFFE
iaddrbusout[18] = 64\'h00000048;
// op, rm, shamt, rn, rd
instrbusin[18] ={ANDS, R20, zeroSham, R21, R25};
daddrbusout[18] = dontcare;
databusin[18] = 64\'bz;
databusout[18] = dontcare;
//phase 3: testing LSL, LSR
//setting up the register R20 for a test of the LSL
// op, rd, rn, rm
iname[19] ="ADDI, R20, R31, #007";//setting up for left shift, result in R20 = 0000000000000007
iaddrbusout[19] = 64\'h0000004C;
// opcode rm/ALUImm rn rd
instrbusin[19] ={ADDI, 12\'h007, R31, R20};
daddrbusout[19] = dontcare;
databusin[19] = 64\'bz;
databusout[19] = dontcare;
// op, rd, rn, rm
iname[20] ="ADDI, R21, R31, #700";//setting up for right shift, n flag, result in R21 = 0000000000000700
iaddrbusout[20] = 64\'h00000050;
// opcode rm/ALUImm rn rd
instrbusin[20] ={ADDI, 12\'h700, R31, R21};
daddrbusout[20] = dontcare;
databusin[20] = 64\'bz;
databusout[20] = dontcare;
// op, rd, rn, rm
iname[21] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[21] = 64\'h00000054;
// op, rm, shamt, rn, rd
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
daddrbusout[21] = dontcare;
databusin[21] = 64\'bz;
databusout[21] = dontcare;
// op, rd, rn, rm
iname[22] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[22] = 64\'h00000058;
// op, rm, shamt, rn, rd
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
daddrbusout[22] = dontcare;
databusin[22] = 64\'bz;
databusout[22] = dontcare;
// op, rd, rn, rm
iname[23] ="LSL, R20, R20, 2";//testing left shift, result in R20 = 0000000000000700
iaddrbusout[23] = 64\'h0000005C;
// op, rm, shamt, rn, rd
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
daddrbusout[23] = dontcare;
databusin[23] = 64\'bz;
databusout[23] = dontcare;
// op, rd, rn, rm
iname[24] ="LSR, R21, R21, 2";//testing right shift, result in R21 = 0000000000000007
iaddrbusout[24] = 64\'h00000060;
// op, rm, shamt, rn, rd
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
daddrbusout[24] = dontcare;
databusin[24] = 64\'bz;
databusout[24] = dontcare;
//phase 4: testing load and store
// op, rt, rn, DT_adr
iname[25] ="LDUR, R22, R31, #1";//testing load, result in R22 = 42069 (from memory,databusin) [yes, really]
iaddrbusout[25] = 64\'h00000064;
// op, DT_ADDR, ?, rn, rt
instrbusin[25] ={LDUR, 9\'b000000001, 2\'b00, R31, R22};
daddrbusout[25] = 64\'h0000000000000001;//used for LDUR
databusin[25] = 64\'h0000000000042069;//used for LDUR
databusout[25] = dontcare;
// op, rn, DT_adr, rt
iname[26] ="STUR, R23, #068, R24";//testing story, result for databusout in R24 = 0000000000000002 (to memory)
//address is calculated from imm or 68, and R23, which is currently 1
iaddrbusout[26] = 64\'h00000068;
// op, DT_ADDR, ?, rn, rt
instrbusin[26] ={STUR, 9\'b001101000, 2\'b00, R23, R24};
daddrbusout[26] = 64\'h0000000000000069;//used for STUR
databusin[26] = 64\'bz;
databusout[26] = 64\'h0000000000000002;//used for STUR
// op, rd, rn, rm
iname[27] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[27] = 64\'h0000006C;
// op, rm, shamt, rn, rd
instrbusin[27] ={AND, R31, zeroSham, R31, R19};
daddrbusout[27] = dontcare;
databusin[27] = 64\'bz;
databusout[27] = dontcare;
// op, rd, rn, rm
iname[28] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[28] = 64\'h00000070;
// op, rm, shamt, rn, rd
instrbusin[28] ={AND, R31, zeroSham, R31, R19};
daddrbusout[28] = dontcare;
databusin[28] = 64\'bz;
databusout[28] = dontcare;
// op, rd, rn, rm
iname[29] ="AND, R17, R31, R31";//delay, result in R17 = 0000000000000000
iaddrbusout[29] = 64\'h00000074;
// op, rm, shamt, rn, rd
instrbusin[29] ={AND, R31, zeroSham, R31, R19};
daddrbusout[29] = dontcare;
databusin[29] = 64\'bz;
databusout[29] = dontcare;
//phase 5: testing B branch
// op, BR_address
iname[30] ="B, #EA";//testing branch, calculated branch address should be
// (64\'h0000000000000078 + 64\'h000000000000003A8 = 64\'h0000000000000420)
iaddrbusout[30] = 64\'h00000078;
// op, BR_address
instrbusin[30] ={B, 26\'b00000000000000000011101010};
daddrbusout[30] = dontcare;
databusin[30] = 64\'bz;
databusout[30] = dontcare;
// op, rd, rn, rm
iname[31] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[31] = 64\'h0000007C;
// op, rm, shamt, rn, rd
instrbusin[31] ={AND, R31, zeroSham, R31, R19};
daddrbusout[31] = dontcare;
databusin[31] = 64\'bz;
databusout[31] = dontcare;
// op, rd, rn, rm
iname[32] ="ADD, R20, R21, R20";//testing branch address result in R20 = 0000000000000707
iaddrbusout[32] = 64\'h00000420;
// op, rm, shamt, rn, rd
instrbusin[32] ={ADD, R20, zeroSham, R21, R20};
daddrbusout[32] = dontcare;
databusin[32] = 64\'bz;
databusout[32] = dontcare;
//phase 6: testing B.EQ and B.NE branch
// op, rd, rn, rm
iname[33] ="ADDI, R21, R31, #AAA";//testing addi, result in R21 = 0000000000000AAA
iaddrbusout[33] = 64\'h00000424;
// opcode rm/ALUImm rn rd
instrbusin[33] ={ADDI, 12\'hAAA, R31, R21};
daddrbusout[33] = dontcare;
databusin[33] = 64\'bz;
databusout[33] = dontcare;
// op, rd, rn, rm
iname[34] ="ADDI, R22, R31, #AAA";//testing addi, result in R22 = 0000000000000AAA
iaddrbusout[34] = 64\'h00000428;
// opcode rm/ALUImm rn rd
instrbusin[34] ={ADDI, 12\'hAAA, R31, R22};
daddrbusout[34] = dontcare;
databusin[34] = 64\'bz;
databusout[34] = dontcare;
//ADDIS for FAKE BRANCH
// op, rd, rn, aluImm
iname[35] ="ADDIS,R31, R31, #420";//testing fake branch, this should NOT set the Z high
iaddrbusout[35] = 64\'h0000042C;
// opcode rm/ALUImm rn rd
instrbusin[35] ={ADDIS, 12\'h420, R31, R31};
daddrbusout[35] = dontcare;
databusin[35] = 64\'bz;
databusout[35] = dontcare;
//FAKE BRANCH
// op, COND_addr, rt
iname[36] ="B_EQ, #69420, RX";//testing to NOT take the branch, Z should be LOW
iaddrbusout[36] = 64\'h00000430;
// op, COND_addr, rt
instrbusin[36] ={B_EQ, 19\'b1101001010000100000, RX};
daddrbusout[36] = dontcare;
databusin[36] = 64\'bz;
databusout[36] = dontcare;
iname[37] = "NOP";//nada
iaddrbusout[37] = 64\'h00000434;
instrbusin[37] = 64\'b0;
daddrbusout[37] = dontcare;
databusin[37] = 64\'bz;
databusout[37] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[38] ="SUBS, R31, R21, R22";//set z flag for BEQ,
iaddrbusout[38] = 64\'h00000438;
// op, rm, shamt, rn, rd
instrbusin[38] ={SUBS, R22, zeroSham, R21, R31};
daddrbusout[38] = dontcare;
databusin[38] = 64\'bz;
databusout[38] = dontcare;
//real branch for B.EQ (I have the best branches)
// op, COND_addr, rt
iname[39] ="B_EQ, #69, RX";//take the branch to instruction count ?
iaddrbusout[39] = 64\'h0000043C;
// op, COND_addr, rt
instrbusin[39] ={B_EQ, 19\'b0000000000001101001, RX};
//19\'b
daddrbusout[39] = dontcare;
databusin[39] = 64\'bz;
databusout[39] = dontcare;
iname[40] = "NOP";//nada
iaddrbusout[40] = 64\'h00000440;
instrbusin[40] = 64\'b0;
daddrbusout[40] = dontcare;
databusin[40] = 64\'bz;
databusout[40] = dontcare;
iname[41] = "NOP";//nada
iaddrbusout[41] = 64\'h000005E0;
instrbusin[41] = 64\'b0;
daddrbusout[41] = dontcare;
databusin[41] = 64\'bz;
databusout[41] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[42] ="SUBS, R31, R21, R20";//set z flag of NOT for BNE
iaddrbusout[42] = 64\'h000005E4;
// op, rm, shamt, rn, rd
instrbusin[42] ={SUBS, R20, zeroSham, R21, R31};
daddrbusout[42] = dontcare;
databusin[42] = 64\'bz;
databusout[42] = dontcare;
//test B.NE
// op, COND_addr, rt
iname[43] ="B_NE, #96, RX";//take the branch to instruction count 840
iaddrbusout[43] = 64\'h000005E8;
// op, COND_addr, rt
instrbusin[43] ={B_NE, 19\'b0000000000010010110, RX};
daddrbusout[43] = dontcare;
databusin[43] = 64\'bz;
databusout[43] = dontcare;
iname[44] = "NOP";//nada
iaddrbusout[44] = 64\'h000005EC;
instrbusin[44] = 64\'b0;
daddrbusout[44] = dontcare;
databusin[44] = 64\'bz;
databusout[44] = dontcare;
iname[45] = "NOP";//nada
iaddrbusout[45] = 64\'h00000840;
instrbusin[45] = 64\'b0;
daddrbusout[45] = dontcare;
databusin[45] = 64\'bz;
databusout[45] = dontcare;
//phase 7: testing CBNZ and CBZ branch
//DONT take the CBZ
// op, COND_addr, rt
iname[46] ="CBZ, #F, R22";//take the branch to instruction count
iaddrbusout[46] = 64\'h00000844;
// op, COND_addr, rt
instrbusin[46] ={CBZ, 19\'b0000000000000001111, R22};
daddrbusout[46] = dontcare;
databusin[46] = 64\'bz;
databusout[46] = dontcare;
iname[47] = "NOP";//nada
iaddrbusout[47] = 64\'h00000848;
instrbusin[47] = 64\'b0;
daddrbusout[47] = dontcare;
databusin[47] = 64\'bz;
databusout[47] = dontcare;
iname[48] = "NOP";//nada
iaddrbusout[48] = 64\'h0000084C;
instrbusin[48] = 64\'b0;
daddrbusout[48] = dontcare;
databusin[48] = 64\'bz;
databusout[48] = dontcare;
//TAKE the CBZ
// op, COND_addr, rt
iname[49] ="CBZ, #21, R19";//take the branch to instruction count
iaddrbusout[49] = 64\'h00000850;
// op, COND_addr, rt
instrbusin[49] ={CBZ, 19\'b0000000000000100001, R19};
daddrbusout[49] = dontcare;
databusin[49] = 64\'bz;
databusout[49] = dontcare;
iname[50] = "NOP";//nada
iaddrbusout[50] = 64\'h00000854;
instrbusin[50] = 64\'b0;
daddrbusout[50] = dontcare;
databusin[50] = 64\'bz;
databusout[50] = dontcare;
iname[51] = "NOP";//nada
iaddrbusout[51] = 64\'h000008D4;
instrbusin[51] = 64\'b0;
daddrbusout[51] = dontcare;
databusin[51] = 64\'bz;
databusout[51] = dontcare;
//DONT take the CBNZ
// op, COND_addr, rt
iname[52] ="CBNZ, #FF, R31";//take the branch to instruction count
iaddrbusout[52] = 64\'h000008D8;
// op, COND_addr, rt
instrbusin[52] ={CBNZ, 19\'b0000000000011111111, R31};
daddrbusout[52] = dontcare;
databusin[52] = 64\'bz;
databusout[52] = dontcare;
iname[53] = "NOP";//nada
iaddrbusout[53] = 64\'h000008DC;
instrbusin[53] = 64\'b0;
daddrbusout[53] = dontcare;
databusin[53] = 64\'bz;
databusout[53] = dontcare;
iname[54] = "NOP";//nada
iaddrbusout[54] = 64\'h000008E0;
instrbusin[54] = 64\'b0;
daddrbusout[54] = dontcare;
databusin[54] = 64\'bz;
databusout[54] = dontcare;
//TAKE the CBNZ
// op, COND_addr, rt
iname[55] ="CBNZ, #22, R20";//take the branch to instruction count
iaddrbusout[55] = 64\'h000008E4;
// op, COND_addr, rt
instrbusin[55] ={CBNZ, 19\'b0000000000000100010, R20};
daddrbusout[55] = dontcare;
databusin[55] = 64\'bz;
databusout[55] = dontcare;
iname[56] = "NOP";//nada
iaddrbusout[56] = 64\'h000008E8;
instrbusin[56] = 64\'b0;
daddrbusout[56] = dontcare;
databusin[56] = 64\'bz;
databusout[56] = dontcare;
iname[57] = "NOP";//nada
iaddrbusout[57] = 64\'h0000096C;
instrbusin[57] = 64\'b0;
daddrbusout[57] = dontcare;
databusin[57] = 64\'bz;
databusout[57] = dontcare;
//finishing up
iname[58] = "NOP";//nada
iaddrbusout[58] = 64\'h00000970;
instrbusin[58] = 64\'b0;
daddrbusout[58] = dontcare;
databusin[58] = 64\'bz;
databusout[58] = dontcare;
iname[59] = "NOP";//nada
iaddrbusout[59] = 64\'h00000974;
instrbusin[59] = 64\'b0;
daddrbusout[59] = dontcare;
databusin[59] = 64\'bz;
databusout[59] = dontcare;
iname[60] = "NOP";//nada
iaddrbusout[60] = 64\'h00000978;
instrbusin[60] = 64\'b0;
daddrbusout[60] = dontcare;
databusin[60] = 64\'bz;
databusout[60] = dontcare;
iname[61] = "NOP";//nada
iaddrbusout[61] = 64\'h0000097C;
instrbusin[61] = 64\'b0;
daddrbusout[61] = dontcare;
databusin[61] = 64\'bz;
databusout[61] = dontcare;
iname[62] = "NOP";//nada
iaddrbusout[62] = 64\'h00000980;
instrbusin[62] = 64\'b0;
daddrbusout[62] = dontcare;
databusin[62] = 64\'bz;
databusout[62] = dontcare;
//remember to set k down below to ntests - 1
ntests = 63;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
assign databus = clkd ? 64\'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
databusk = 64\'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
$display ("Time=%t\
clk=%b", $realtime, clk);
for (k=0; k<= 62; k=k+1) begin
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set load data for 3rd previous instruction
if (k >=3)
databusk = databusin[k-3];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check data address from 3rd previous instruction
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check store data from 3rd previous instruction
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
/************************
* Willard Wider
* 6-18-17
* ELEC3725
* controller.v
* building a 32 bit ALU
************************/
module controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);
input [31:0] ibus;
input clk;
output [31:0] Aselect;
output [31:0] Bselect;
output [31:0] Dselect;
output [2:0] S;
output Imm;
output Cin;
reg immHolder;
reg [2:0] S_holder;
reg Cin_holder;
wire [31:0] IF_ID_OUT;//wire from IF/ID
wire [31:0] ID_EX_IN;//wire to ID/EX
wire [4:0] rs;//the wire to hold the split output from IF-ID
wire [4:0] rt;
wire [4:0] rd;
wire [5:0] opCode;
wire [5:0] funktion;
wire [5:0] opCodeThing;
wire [5:0] opCodeThing2;
wire [31:0] EX_MEM_IN;
wire [4:0] muxOut;
//pipeline the instruction register, get the output into a wire
DflipFlop IFID(.dataIn(ibus), .clk(clk), .dataOut(IF_ID_OUT));
assign opCode = IF_ID_OUT[31:26];
assign rs = IF_ID_OUT[25:21];
assign rt = IF_ID_OUT[20:16];
assign rd = IF_ID_OUT[15:11];
assign funktion = IF_ID_OUT[5:0];
//write the Aselet
assign Aselect = 1 << rs;//rs
//init
initial begin
immHolder = 1'bx;
Cin_holder = 1'bx;
S_holder = 3'bxxx;
//opCodeThing2 = 5'bxxxxx;
end
//for the change in the opcode which is like always
always @(IF_ID_OUT) begin
//first mux value is to assume 0
immHolder = 1;
Cin_holder = 0;
//write the cases for the opcode (immediate)
case (opCode)
6'b000011: begin
//addi
S_holder = 3'b010;
end
6'b000010: begin
//subi
S_holder = 3'b011;
Cin_holder = 1;
end
6'b000001: begin
//xori
S_holder = 3'b000;
end
6'b001111: begin
//andi
S_holder = 3'b110;
end
6'b001100: begin
//ori
S_holder = 3'b100;
end
//if 00000
6'b000000: begin
//write the mux value here
immHolder= 0;
//then write the cases for the funct
case (funktion)
6'b000011: begin
//add
S_holder = 3'b010;
end
6'b000010: begin
//sub
S_holder = 3'b011;
Cin_holder = 1;
end
6'b000001: begin
//xor
S_holder = 3'b000;
end
6'b000111: begin
//and
S_holder = 3'b110;
end
6'b000100: begin
//or
S_holder = 3'b100;
end
endcase
end
endcase
end
//write to Bselect
//assign Bselect = immHolder? 1 << rt: 32'bx;
assign Bselect = immHolder? 32'bx: 1 << rt;
//write the input for ID_EX_IN. it's the mux
assign muxOut = immHolder? rt:rd;//rd=R=imm low, rt=I=imm high
assign ID_EX_IN = 1 << muxOut;
assign opCodeThing = {immHolder,S_holder,Cin_holder};
DflipFlop2 ID_EX(.dataIn(ID_EX_IN),.clk(clk),.dataOut(EX_MEM_IN),.opCodeThingIn(opCodeThing),.opCodeThingOut(opCodeThing2));
//write the final outputs
/*
output [2:0] S;
output Imm;
output Cin;
*/
assign Imm = opCodeThing2[4];
assign S = opCodeThing2[3:1];
assign Cin = opCodeThing2[0];
DflipFlop EXMEMm(.dataIn(EX_MEM_IN),.clk(clk),.dataOut(Dselect));
endmodule
//a mux for selecting which output we will use
module mux(rtIn, rdIn, imSwitch, out);
input [4:0] rtIn;
input [4:0] rdIn;
input imSwitch;
output [31:0] out;
wire [4:0] whichIn;
assign whichIn = imSwitch? rtIn : rdIn;
signExtend outExtend(.in(whichIn),.out(out));
//if imm is high, use rd, else use rt
endmodule
//opcode and funct decoder
module opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);
input [5:0] opcode;
input [5:0] funct;
output [11:0] opCodeOutputThing;
assign opCodeOutputThing= {opcode,funct};
output immFlag;
assign immFlag = opcode? 1'b1 : 1'b0;
endmodule
//sign extension module
module signExtend(in,out);
input [4:0] in;
output [31:0] out;
assign out = in[4]? {27'b0, in}: {27'b1, in};
endmodule
//flip flop module. requires a clock cycle to update value
module DflipFlop(dataIn, clk, dataOut);
input [31:0] dataIn;
input clk;
output [31:0] dataOut;
reg [31:0] dataOut;
always @(posedge clk) begin
dataOut = dataIn;
end
endmodule
//flip flop module that has a thing pass through it. requires a clock cycle to update value
module DflipFlop2(dataIn, clk, dataOut, opCodeThingIn, opCodeThingOut);
input [31:0] dataIn;
input clk;
output [31:0] dataOut;
reg [31:0] dataOut;
input [5:0] opCodeThingIn;
output [5:0] opCodeThingOut;
reg [5:0] opCodeThingOut;
always @(posedge clk) begin
dataOut = dataIn;
opCodeThingOut = opCodeThingIn;
end
endmodule
module regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);
input [31:0] Aselect;
input [31:0] Bselect;
input [31:0] Dselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
output [31:0] dbus;
input [2:0] S;
input Cin;
//wire [31:0] abusW;
//wire [31:0] bbusW;
//wire [31:0] dbusW;
regfile reggie(
.Aselect(Aselect),
.Bselect(Bselect),
.Dselect(Dselect),
.dbus(dbus),
.bbus(bbus),
.abus(abus),
.clk(clk)
);
alupipe alup(
.S(S),
.Cin(Cin),
.clk(clk),
.abus(abus),
.bbus(bbus),
.dbus(dbus)
);
endmodule
module regfile(
input [31:0] Aselect,//select the register index to read from to store into abus
input [31:0] Bselect,//select the register index to read from to store into bbus
input [31:0] Dselect,//select the register to write to from dbus
input [31:0] dbus,//data in
output [31:0] abus,//data out
output [31:0] bbus,//data out
input clk
);
assign abus = Aselect[0] ? 32'b0 : 32'bz;
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
DNegflipFlop myFlips[30:0](//32 wide register
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule
module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [31:0] dbus;
input Dselect;//the select write bit for this register
input Bselect;//the select read bit for this register
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
wire wireclk;
reg [31:0] data;
assign wireclk = clk & Dselect;
always @(negedge wireclk) begin
data = dbus;
end
assign abus = Aselect ? data : 32'bz;
assign bbus = Bselect ? data : 32'bz;
endmodule
//the top module, the ALU with piped input and output
module alupipe(S, abus, bbus, clk, Cin, dbus);
input [31:0] abus;
input [31:0] bbus;
input clk;
input [2:0] S;
input Cin;
output [31:0] dbus;
wire [31:0] aInput;//connects register A output to ALU A input
wire [31:0] bInput;//connects register B output to ALU B input
wire [31:0] dInput;//connects register D input to ALU D output
alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));
DflipFlop AFF(.dataIn(abus), .dataOut(aInput), .clk(clk));
DflipFlop BFF(.dataIn(bbus), .dataOut(bInput), .clk(clk));
DflipFlop DFF(.dataIn(dInput), .dataOut(dbus), .clk(clk));
endmodule
//flip flop module. requires a clock cycle to update value
module DflipFlop(dataIn, clk, dataOut);
input [31:0] dataIn;
input clk;
output [31:0] dataOut;
reg [31:0] dataOut;
always @(posedge clk) begin
dataOut = dataIn;
end
endmodule
//Below this point is code from assignment 1//
//The declaration of the entire ALU itself.
module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;//the output bus
output Cout, V;//Cout is the bit for it it needs to carry over to the next circuit/ V is the overflow bit.
input [31:0] a, b;//the two input buses
input Cin;//the bit for marking if it is carrying over from a previous circuit
input [2:0] S;//The select bus. It defines the operation to do with input busses a and b
wire [31:0] c, g, p;
wire gout, pout;
//The core ALU bus
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
//the top Look-Ahead-Carry module.
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
//the overflow module
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule
//The module to handle a single bit operation for the top ALU module
module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule
//The module to handle the overflow bit
module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule
//Look-Ahead Carry unit level 1. Used for the root (level 1) and first child leafs (level 2)
module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule
//Look-Ahead Carry unit level 2. Contains LACs for the root and level 1. Used in level 3
module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 3. Contains LACs for the root and level 2. Used in level 4
module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 4. Contains LACs for the root and level 3. Used in level 5
module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 1. Caontains LACs for the root and level 4. Used in the core alu32 module
module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
/************************
* Willard Wider
* 6-29-17
* ELEC3725
* cpu4.v
* building a 32 bit CPU
************************/
//cpu4 dut(.clk(clk),.ibus(ibus),.daddrbus(daddrbus),.databus(databus));
module cpu4(ibus,clk,daddrbus,databus);
//just a clock
input clk;
//the new bus things
output [31:0] daddrbus;
inout [31:0] databus;
//decoder tings
wire [5:0] opCode;//from IF_ID
wire [5:0] funktion;//from IF_ID
//ibus
input [31:0] ibus;//in for IF_ID
wire [31:0] ibusWire;//out for IF_ID
//Aselect
wire [31:0] AselectWire;//from rs, to regfile
wire [5:0] rs;//from ibusWire, to AselectWire
//Bselect
wire [31:0] BselectWire;//from rt, to regfile
wire [5:0] rt;//from ibsuWire, to BselectWire and mxu1
//imm select
reg immBit1;//from IF_ID(ibusWire), to mux1 and ID_EX
wire immBit2;//from ID_EX, to mux2
//load word save word flag
reg [1:0] lwSwFlag1;//from IF_ID, to ID_EX
wire [1:0] lwSwFlag2;//from ID_EX, to EX_MEM
wire [1:0] lwSwFlag3;//from EX_MEM, to MEM_WB
wire [1:0] lwSwFlag4;//from MEM_WB, to mux3
//Dselect
wire [31:0] DselectWire1;//from muxOut, to ID_EX
wire [5:0] rd;//from ID_EX, to mux1
wire [31:0] DselectWire2;//from ID_EX, to EX_MM
wire [31:0] DselectWire3;//from EX_MEM, to MEM_WB
wire [31:0] DselectWire3_5;//from MEM_WB, to mux3
wire [31:0] DselectWire4;//from mux3, to regfile
//abus
//output [31:0] abus;//from ID_EX, to SIM_OUT
wire [31:0] abusWire1;//from regOut, to ID_EX
wire [31:0] abusWire2;//from ID_EX, to ALU
//bbus
//output [31:0] bbus;//from mux2Out, to SIM_OUT
wire [31:0] bbusWire1;//from regOut, to ID_EX
wire [31:0] bbusWire2;//from ID_EX, to mux2/EX_MEM
wire [31:0] bbusWire3;//from EX_MEM, to memory logic
wire [31:0] bbusWire3_5;//from memory logic, to MEM_WB
wire [31:0] bbusWire4;//from MEM_WB, to mux3
//dbus
//output [31:0] dbus;//from EX_MEM, to SIM_OUT
wire [31:0] dbusWire1;//from ALU, to EX_MEM
wire [31:0] dbusWire2;//from EM_MEM, to MEM_WB
wire [31:0] dbusWire3;//from MEM_WB, to mux3
//mux3
wire [31:0] mux3Out;//from dbusWire3/bbusWire4, to regfile
//mux2
wire [31:0] mux2Out;//from bbusWire2/immWire2, to ALU
//immediate
wire [31:0] immWire1;//from IF_ID, to ID_EX
wire [31:0] immWire2;//from ID_EX, to mux2
//S
reg [2:0] SWire1;//from IF_ID, to ID_EX
wire [2:0] SWire2;//from ID_EX, to ALU
//Cin
reg CinWire1;//from IF_ID, to ID_EX
wire CinWire2;//form ID_EX, to ALU
//init
initial begin
immBit1 = 1\'bx;
CinWire1 = 1\'bx;
SWire1 = 3\'bxxx;
lwSwFlag1 = 2\'bxx;
end
//latch for pipeline 1(IF_ID)
//module pipeline_1_latch(clk, ibus, ibusWire);
pipeline_1_latch IF_ID(.clk(clk),.ibus(ibus),.ibusWire(ibusWire));
//PIPELINE_1_START
//decode the input command
assign opCode = ibusWire[31:26];
assign rs = ibusWire[25:21];
assign rt = ibusWire[20:16];
assign rd = ibusWire[15:11];
assign funktion = ibusWire[5:0];
assign immWire1 = ibusWire[15]? {16\'b1111111111111111,ibusWire[15:0]} : {16\'b0000000000000000,ibusWire[15:0]};
//for the change in the opcode which is like always
always @(ibusWire) begin
//first mux value is to assume 0
immBit1 = 1;
CinWire1 = 0;
//assume not doing anything with the load or save
lwSwFlag1 = 2\'b00;
//write the cases for the opcode (immediate)
case (opCode)
6\'b000011: begin
//addi
SWire1 = 3\'b010;
end
6\'b000010: begin
//subi
SWire1 = 3\'b011;
CinWire1 = 1;
end
6\'b000001: begin
//xori
SWire1 = 3\'b000;
end
6\'b001111: begin
//andi
SWire1 = 3\'b110;
end
6\'b001100: begin
//ori
SWire1 = 3\'b100;
end
6\'b011110: begin
//load word, but still addi
SWire1 = 3\'b010;
lwSwFlag1 = 2\'b01;
end
6\'b011111: begin
//store word, but still addi
SWire1 = 3\'b010;
lwSwFlag1 = 2\'b10;
end
//if 00000
6\'b000000: begin
//write the mux value here
immBit1= 0;
//then write the cases for the funct
case (funktion)
6\'b000011: begin
//add
SWire1 = 3\'b010;
end
6\'b000010: begin
//sub
SWire1 = 3\'b011;
CinWire1 = 1;
end
6\'b000001: begin
//xor
SWire1 = 3\'b000;
end
6\'b000111: begin
//and
SWire1 = 3\'b110;
end
6\'b000100: begin
//or
SWire1 = 3\'b100;
end
endcase
end
endcase
end
//write the select lines
assign AselectWire = 1 << rs;
//only write to Bselect for real if it\'s actually goign to use Bselect
//i don\'t think this line matters but i feel like it\'s good pratice
//assign BselectWire = immBit1? 32\'hxxxxxxxx: 1 << rt;
assign BselectWire = 1 << rt;
//mux1
//Rd for R, imm = false
//Rt for I, imm = true
assign DselectWire1 = immBit1? 1<<rt : 1<<rd;
/*
module regfile(
input [31:0] Aselect,//select the register index to read from to store into abus
input [31:0] Bselect,//select the register index to read from to store into bbus
input [31:0] Dselect,//select the register to write to from dbus
input [31:0] dbus,//data in
output [31:0] abus,//data out
output [31:0] bbus,//data out
input clk
);
*/
regfile Reggie3(.clk(clk),.Aselect(AselectWire),.Bselect(BselectWire),.Dselect(DselectWire4),.abus(abusWire1),.bbus(bbusWire1),.dbus(mux3Out));
//PIPELINE_1_END
//latch for pipeline 2(ID_EX)
//module pipeline_2_latch(clk, abusWire1, bbusWire1, DselectWire1, immWire1, SWire1, CinWire1,immBit1,lwSwFlag1,abusWire2,bbusWire2,immWire2,SWire2,CinWire2,DselectWire2,immBit2,lwSwFlag2);
pipeline_2_latch ED_EX(.clk(clk),.abusWire1(abusWire1),.bbusWire1(bbusWire1),.DselectWire1(DselectWire1),.immWire1(immWire1),.SWire1(SWire1),.CinWire1(CinWire1),.immBit1(immBit1),.lwSwFlag1(lwSwFlag1),.abusWire2(abusWire2),.bbusWire2(bbusWire2),.immWire2(immWire2),.CinWire2(CinWire2),.DselectWire2(DselectWire2),.immBit2(immBit2),.SWire2,.lwSwFlag2(lwSwFlag2));
//PIPELINE_2_START
//assign abus output
//assign abus = abusWire2;
//mux2
//immWire for true, Bselet for false
assign mux2Out = immBit2? immWire2: bbusWire2;
//assign bbus output
//assign bbus = mux2Out;
//make the ALU
//module alu32 (d, Cout, V, a, b, Cin, S);
alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));
//PIPELINE_2_END
//latch for pipeline 3(EX_MEM)
//module pipeline_3_latch(clk, dbusWire1, DselectWire2, bbusWire2, lwSwFlag2, dbusWire2, DselectWire3,bbusWire3,lwSwFlag3);
pipeline_3_latch EX_MEME (.clk(clk),.dbusWire1(dbusWire1),.DselectWire2(DselectWire2),.bbusWire2(bbusWire2),.lwSwFlag2(lwSwFlag2),.dbusWire2(dbusWire2),.DselectWire3(DselectWire3),.bbusWire3(bbusWire3),.lwSwFlag3(lwSwFlag3));
//PIPELINE_3_SRART
//assign output values
//try again with ternary operators
//one for the databus and one for bbusWire3
assign bbusWire3_5 = (lwSwFlag3==2\'b01)? databus: bbusWire3;
assign databus = (lwSwFlag3 == 2\'b10)? bbusWire3: 32\'hzzzzzzzz;
/*
case(lwSwFlag3)
2\'b00:begin//none,
assign databus = 32\'hzzzzzzzz;
end
2\'b01:begin//LOAD,
assign bbusWire3 = databus;
assign databus = 32\'hzzzzzzzz;
end
2\'b10:begin//SAVE/STORE,
assign databus = bbusWire3;
end
endcase
*/
assign daddrbus = dbusWire2;
//PIPELINE_3_END
//latch for pipeline 4(MEM_WB)
//module pipeline_4_latch(clk, dbusWire2, DselectWire3, bbusWire3, lwSwFlag3, dbusWire3, DselectWire4,bbusWire4,lwSwFlag4);
pipeline_4_latch MEM_WB (.clk(clk),.dbusWire2(dbusWire2),.DselectWire3(DselectWire3),.bbusWire3(bbusWire3_5),.lwSwFlag3(lwSwFlag3),.dbusWire3(dbusWire3),.DselectWire4(DselectWire3_5),.bbusWire4(bbusWire4),.lwSwFlag4(lwSwFlag4));
//PIPELINE_4_START
//the "mux" for the data writeBack
assign mux3Out = (lwSwFlag4 == 2\'b01)? bbusWire4:dbusWire3;
assign DselectWire4 = (lwSwFlag4 == 2\'b10)? 32\'h00000001: DselectWire3_5;
/*
case(lwSwFlag4)
2\'b00:begin//none, use dbus
assign mux3Out = dbusWire3;
end
2\'b01:begin//LOAD, use bbus
assign mux3Out = bbusWire4;
end
2\'b10:begin//STORE, use dbus
assign mux3Out = dbusWire3;
//set send mux3out to R0
assign DselectWire4 = 32\'h00000001;
end
endcase
*/
//PIPELINE_4_END
endmodule
//phase 1 pipeline latch(IF_ID)
module pipeline_1_latch(clk, ibus, ibusWire);
input [31:0] ibus;
input clk;
output [31:0] ibusWire;
reg [31:0] ibusWire;
always @(posedge clk) begin
ibusWire = ibus;
end
endmodule
//phase 2 pipeline latch(ID_EX)
module pipeline_2_latch(clk, abusWire1, bbusWire1, DselectWire1, immWire1, SWire1, CinWire1,immBit1,lwSwFlag1,abusWire2,bbusWire2,immWire2,SWire2,CinWire2,DselectWire2,immBit2,lwSwFlag2);
input clk, CinWire1,immBit1;
input [31:0] abusWire1, bbusWire1, DselectWire1, immWire1;
input [2:0] SWire1;
input [1:0] lwSwFlag1;
output CinWire2,immBit2;
output [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
output [2:0] SWire2;
output [1:0] lwSwFlag2;
reg CinWire2,immBit2;
reg [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
reg [2:0] SWire2;
reg [1:0] lwSwFlag2;
always @(posedge clk) begin
abusWire2 = abusWire1;
bbusWire2 = bbusWire1;
DselectWire2 = DselectWire1;
immWire2 = immWire1;
SWire2 = SWire1;
CinWire2 = CinWire1;
immBit2 = immBit1;
lwSwFlag2 = lwSwFlag1;
end
endmodule
//phase 3 pipeliune latch(EX_MEM)
module pipeline_3_latch(clk, dbusWire1, DselectWire2, bbusWire2, lwSwFlag2, dbusWire2, DselectWire3,bbusWire3,lwSwFlag3);
input clk;
input [31:0] dbusWire1, DselectWire2, bbusWire2;
input [1:0] lwSwFlag2;
output [31:0] dbusWire2, DselectWire3, bbusWire3;
output [1:0] lwSwFlag3;
reg [31:0] dbusWire2, DselectWire3, bbusWire3;
reg [1:0] lwSwFlag3;
always @(posedge clk) begin
dbusWire2 = dbusWire1;
DselectWire3 = DselectWire2;
bbusWire3 = bbusWire2;
lwSwFlag3 = lwSwFlag2;
end
endmodule
//phase 4 pipeline latch(MEM_WB)
module pipeline_4_latch(clk, dbusWire2, DselectWire3, bbusWire3, lwSwFlag3, dbusWire3, DselectWire4,bbusWire4,lwSwFlag4);
input clk;
input [31:0] dbusWire2, DselectWire3, bbusWire3;
input [1:0] lwSwFlag3;
output [31:0] dbusWire3, DselectWire4, bbusWire4;
output [1:0] lwSwFlag4;
reg [31:0] dbusWire3, DselectWire4, bbusWire4;
reg [1:0] lwSwFlag4;
always @(posedge clk) begin
dbusWire3 = dbusWire2;
DselectWire4 = DselectWire3;
bbusWire4 = bbusWire3;
lwSwFlag4 = lwSwFlag3;
end
endmodule
module regfile(
input [31:0] Aselect,//select the register index to read from to store into abus
input [31:0] Bselect,//select the register index to read from to store into bbus
input [31:0] Dselect,//select the register to write to from dbus
input [31:0] dbus,//data in
output [31:0] abus,//data out
output [31:0] bbus,//data out
input clk
);
assign abus = Aselect[0] ? 32\'b0 : 32\'bz;
assign bbus = Bselect[0] ? 32\'b0 : 32\'bz;
DNegflipFlop myFlips[30:0](//32 wide register
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule
module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [31:0] dbus;
input Dselect;//the select write bit for this register
input Bselect;//the select read bit for this register
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
wire wireclk;
reg [31:0] data;
assign wireclk = clk & Dselect;
initial begin
data = 32\'h00000000;
end
always @(negedge clk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect? data : 32\'hzzzzzzzz;
assign bbus = Bselect? data : 32\'hzzzzzzzz;
endmodule
//Below this point is code from assignment 1//
//The declaration of the entire ALU itself.
module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;//the output bus
output Cout, V;//Cout is the bit for it it needs to carry over to the next circuit/ V is the overflow bit.
input [31:0] a, b;//the two input buses
input Cin;//the bit for marking if it is carrying over from a previous circuit
input [2:0] S;//The select bus. It defines the operation to do with input busses a and b
wire [31:0] c, g, p;
wire gout, pout;
//The core ALU bus
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
//the top Look-Ahead-Carry module.
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
//the overflow module
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule
//The module to handle a single bit operation for the top ALU module
module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule
//The module to handle the overflow bit
module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule
//Look-Ahead Carry unit level 1. Used for the root (level 1) and first child leafs (level 2)
module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule
//Look-Ahead Carry unit level 2. Contains LACs for the root and level 1. Used in level 3
module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 3. Contains LACs for the root and level 2. Used in level 4
module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 4. Contains LACs for the root and level 3. Used in level 5
module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 1. Caontains LACs for the root and level 4. Used in the core alu32 module
module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
|
`timescale 1ns / 1ps
module regfile(
input [31:0] Aselect,//select the register index to read from to store into abus
input [31:0] Bselect,//select the register index to read from to store into bbus
input [31:0] Dselect,//select the register to write to from dbus
input [31:0] dbus,//data in
output [31:0] abus,//data out
output [31:0] bbus,//data out
input clk
);
//wire [31:0] abusW;
//wire [31:0] bbusW;
//assign abus = abusW;
//assign bbus = bbusW;
assign abus = Aselect[0] ? 32'b0 : 32'bz;//in case it's the 0
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
DNegflipFlop myFlips[30:0](//32 wide register
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
/*assign abus = Aselect[0] ? 32'b0 : 32'bz;//in case it's the 0
assign bbus = Bselect[0] ? 32'b0 : 32'bz;*/
/*always @(posedge Aselect[0]) begin
abus = 32'b0;
end
always @(posedge Bselect[0]) begin
end*/
endmodule
//negedge sensitive flipflop module flip flop module
module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [31:0] dbus;
input Dselect;//the select write bit for this register
input Bselect;//the select read bit for this register
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
reg [31:0] data;
always @(negedge clk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect ? data : 32'bz;
assign bbus = Bselect ? data : 32'bz;
endmodule
|
/************************
* Willard Wider
* 6-29-17
* ELEC3725
* cpu3.v
* building a 32 bit CPU
************************/
module cpu3(ibus,clk,abus,bbus,dbus);
//just a clock
input clk;
wire [5:0] opCode;
wire [5:0] funktion;
//ibus
input [31:0] ibus;//in for IF_ID
wire [31:0] ibusWire;//out for IF_ID
//Aselect
wire [31:0] AselectWire;//from rs, to regfile
wire [5:0] rs;//from ibusWire, to AselectWire
//Bselect
wire [31:0] BselectWire;//from rt, to regfile
wire [5:0] rt;//from ibsuWire, to BselectWire and mxu1
//imm select
reg immBit1;//from IF_ID(ibusWire), to mux1 and ID_EX
wire immBit2;//from ID_EX, to mux2
//Dselect
wire [31:0] DselectWire1;//from muxOut, to ID_EX
wire [5:0] rd;//from ID_EX, to mux1
wire [31:0] DselectWire2;//from ID_EX, to EX_MM
wire [31:0] DselectWire3;//from EX_MEM, to regfile
//abus
output [31:0] abus;//from ID_EX, to SIM_OUT
wire [31:0] abusWire1;//from regOut, to ID_EX
wire [31:0] abusWire2;//from ID_EX, to ALU
//bbus
output [31:0] bbus;//from mux2Out, to SIM_OUT
wire [31:0] bbusWire1;//from regOut, to ID_EX
wire [31:0] bbusWire2;//from ID_EX, to mux2
//dbus
output [31:0] dbus;//from EX_MEM, to SIM_OUT
wire [31:0] dbusWire1;//from ALU, to EX_MEM
wire [31:0] dbusWire2;//from EM_MEM, to regile
//mux2
wire [31:0] mux2Out;//from bbusWire2/immWire2, to ALU
//immediate
wire [31:0] immWire1;//from IF_ID, to ID_EX
wire [31:0] immWire2;//from ID_EX, to mux2
//S
reg [2:0] SWire1;//from IF_ID, to ID_EX
wire [2:0] SWire2;//from ID_EX, to ALU
//Cin
reg CinWire1;//from IF_ID, to ID_EX
wire CinWire2;//form ID_EX, to ALU
//init
initial begin
immBit1 = 1'bx;
CinWire1 = 1'bx;
SWire1 = 3'bxxx;
end
//latch for pipeline 1(IF_ID)
//module pipeline_1_latch(clk, ibus, ibusWire);
pipeline_1_latch IF_ID(.clk(clk),.ibus(ibus),.ibusWire(ibusWire));
//PIPELINE_1_START
//decode the input command
assign opCode = ibusWire[31:26];
assign rs = ibusWire[25:21];
assign rt = ibusWire[20:16];
assign rd = ibusWire[15:11];
assign funktion = ibusWire[5:0];
assign immWire1 = ibusWire[15]? {16'b1111111111111111,ibusWire[15:0]} : {16'b0000000000000000,ibusWire[15:0]};
//for the change in the opcode which is like always
always @(ibusWire) begin
//first mux value is to assume 0
immBit1 = 1;
CinWire1 = 0;
//write the cases for the opcode (immediate)
case (opCode)
6'b000011: begin
//addi
SWire1 = 3'b010;
end
6'b000010: begin
//subi
SWire1 = 3'b011;
CinWire1 = 1;
end
6'b000001: begin
//xori
SWire1 = 3'b000;
end
6'b001111: begin
//andi
SWire1 = 3'b110;
end
6'b001100: begin
//ori
SWire1 = 3'b100;
end
//if 00000
6'b000000: begin
//write the mux value here
immBit1= 0;
//then write the cases for the funct
case (funktion)
6'b000011: begin
//add
SWire1 = 3'b010;
end
6'b000010: begin
//sub
SWire1 = 3'b011;
CinWire1 = 1;
end
6'b000001: begin
//xor
SWire1 = 3'b000;
end
6'b000111: begin
//and
SWire1 = 3'b110;
end
6'b000100: begin
//or
SWire1 = 3'b100;
end
endcase
end
endcase
end
//write the select lines
assign AselectWire = 1 << rs;
//only write to Bselect for real if it's actually goign to use Bselect
//i don't think this line matters but i feel like it's good pratice
//assign BselectWire = immBit1? 32'hxxxxxxxx: 1 << rt;
assign BselectWire = 1 << rt;
//mux1
//Rd for R, imm = false
//Rt for I, imm = true
assign DselectWire1 = immBit1? 1<<rt : 1<<rd;
/*
module regfile(
input [31:0] Aselect,//select the register index to read from to store into abus
input [31:0] Bselect,//select the register index to read from to store into bbus
input [31:0] Dselect,//select the register to write to from dbus
input [31:0] dbus,//data in
output [31:0] abus,//data out
output [31:0] bbus,//data out
input clk
);
*/
regfile Reggie3(.clk(clk),.Aselect(AselectWire),.Bselect(BselectWire),.Dselect(DselectWire3),.abus(abusWire1),.bbus(bbusWire1),.dbus(dbusWire2));
//PIPELINE_1_END
//latch for pipeline 2(ID_EX)
//module pipeline_2_latch(clk, abusWire1, bbusWire1, DselectWire1, immWire1, SWire1, CinWire1,immBit1,abusWire2,bbusWire2,immWire2,CinWire2,DselectWire2,immBit2);
pipeline_2_latch ED_EX(.clk(clk),.abusWire1(abusWire1),.bbusWire1(bbusWire1),.DselectWire1(DselectWire1),.immWire1(immWire1),.SWire1(SWire1),.CinWire1(CinWire1),.immBit1(immBit1),.abusWire2(abusWire2),.bbusWire2(bbusWire2),.immWire2(immWire2),.CinWire2(CinWire2),.DselectWire2(DselectWire2),.immBit2(immBit2),.SWire2);
//PIPELINE_2_START
//assign abus output
assign abus = abusWire2;
//mux2
//immWire for true, Bselet for false
assign mux2Out = immBit2? immWire2: bbusWire2;
//assign bbus output
assign bbus = mux2Out;
//make the ALU
//module alu32 (d, Cout, V, a, b, Cin, S);
alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));
//PIPELINE_2_END
//latch for pipeline 3(EX_MEM)
//module pipeline_3_latch(clk, dbusWire1, DselectWire2, dbusWire2, DselectWire3);
pipeline_3_latch EX_MEME (.clk(clk),.dbusWire1(dbusWire1),.DselectWire2(DselectWire2),.dbusWire2(dbusWire2),.DselectWire3(DselectWire3));
//PIPELINE_3_SRART
//assign out dbus
assign dbus = dbusWire2;
//PIPELINE_3_END
endmodule
//phase 1 pipeline latch(IF_ID)
module pipeline_1_latch(clk, ibus, ibusWire);
input [31:0] ibus;
input clk;
output [31:0] ibusWire;
reg [31:0] ibusWire;
always @(posedge clk) begin
ibusWire = ibus;
end
endmodule
//phase 2 pipeline latch(ID_EX)
module pipeline_2_latch(clk, abusWire1, bbusWire1, DselectWire1, immWire1, SWire1, CinWire1,immBit1,abusWire2,bbusWire2,immWire2,SWire2,CinWire2,DselectWire2,immBit2);
input clk, CinWire1,immBit1;
input [31:0] abusWire1, bbusWire1, DselectWire1, immWire1;
input [2:0] SWire1;
output CinWire2,immBit2;
output [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
output [2:0] SWire2;
reg CinWire2,immBit2;
reg [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
reg [2:0] SWire2;
always @(posedge clk) begin
abusWire2 = abusWire1;
bbusWire2 = bbusWire1;
DselectWire2 = DselectWire1;
immWire2 = immWire1;
SWire2 = SWire1;
CinWire2 = CinWire1;
immBit2 = immBit1;
end
endmodule
//phase 3 pipeliune latch(EX_MEM)
module pipeline_3_latch(clk, dbusWire1, DselectWire2, dbusWire2, DselectWire3);
input clk;
input [31:0] dbusWire1, DselectWire2;
output [31:0] dbusWire2, DselectWire3;
reg [31:0] dbusWire2, DselectWire3;
always @(posedge clk) begin
dbusWire2 = dbusWire1;
DselectWire3 = DselectWire2;
end
endmodule
module regfile(
input [31:0] Aselect,//select the register index to read from to store into abus
input [31:0] Bselect,//select the register index to read from to store into bbus
input [31:0] Dselect,//select the register to write to from dbus
input [31:0] dbus,//data in
output [31:0] abus,//data out
output [31:0] bbus,//data out
input clk
);
assign abus = Aselect[0] ? 32'b0 : 32'bz;
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
DNegflipFlop myFlips[30:0](//32 wide register
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule
module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [31:0] dbus;
input Dselect;//the select write bit for this register
input Bselect;//the select read bit for this register
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
wire wireclk;
reg [31:0] data;
assign wireclk = clk & Dselect;
initial begin
data = 32'h00000000;
end
always @(negedge wireclk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect? data : 32'hzzzzzzzz;
assign bbus = Bselect? data : 32'hzzzzzzzz;
endmodule
//Below this point is code from assignment 1//
//The declaration of the entire ALU itself.
module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;//the output bus
output Cout, V;//Cout is the bit for it it needs to carry over to the next circuit/ V is the overflow bit.
input [31:0] a, b;//the two input buses
input Cin;//the bit for marking if it is carrying over from a previous circuit
input [2:0] S;//The select bus. It defines the operation to do with input busses a and b
wire [31:0] c, g, p;
wire gout, pout;
//The core ALU bus
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
//the top Look-Ahead-Carry module.
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
//the overflow module
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule
//The module to handle a single bit operation for the top ALU module
module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule
//The module to handle the overflow bit
module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule
//Look-Ahead Carry unit level 1. Used for the root (level 1) and first child leafs (level 2)
module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule
//Look-Ahead Carry unit level 2. Contains LACs for the root and level 1. Used in level 3
module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 3. Contains LACs for the root and level 2. Used in level 4
module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 4. Contains LACs for the root and level 3. Used in level 5
module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 1. Caontains LACs for the root and level 4. Used in the core alu32 module
module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
|
/************************
* Willard Wider
* 6-6-17
* ELEC3725
* alupipe.v
* building a 32 bit ALU
************************/
//the top module, the ALU with piped input and output
module alupipe(S, abus, bbus, clk, Cin, dbus);
input [31:0] abus;
input [31:0] bbus;
input clk;
input [2:0] S;
input Cin;
output [31:0] dbus;
wire [31:0] aInput;//connects register A output to ALU A input
wire [31:0] bInput;//connects register B output to ALU B input
wire [31:0] dInput;//connects register D input to ALU D output
alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));
DflipFlop AFF(.dataIn(abus), .dataOut(aInput), .clk(clk));
DflipFlop BFF(.dataIn(bbus), .dataOut(bInput), .clk(clk));
DflipFlop DFF(.dataIn(dInput), .dataOut(dbus), .clk(clk));
endmodule
//flip flop module. requires a clock cycle to update value
module DflipFlop(dataIn, clk, dataOut);
input [31:0] dataIn;
input clk;
output [31:0] dataOut;
reg [31:0] dataOut;
always @(posedge clk) begin
dataOut = dataIn;
end
endmodule
//Below this point is code from assignment 1//
//The declaration of the entire ALU itself.
module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;//the output bus
output Cout, V;//Cout is the bit for it it needs to carry over to the next circuit/ V is the overflow bit.
input [31:0] a, b;//the two input buses
input Cin;//the bit for marking if it is carrying over from a previous circuit
input [2:0] S;//The select bus. It defines the operation to do with input busses a and b
wire [31:0] c, g, p;
wire gout, pout;
//The core ALU bus
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
//the top Look-Ahead-Carry module.
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
//the overflow module
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule
//The module to handle a single bit operation for the top ALU module
module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule
//The module to handle the overflow bit
module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule
//Look-Ahead Carry unit level 1. Used for the root (level 1) and first child leafs (level 2)
module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule
//Look-Ahead Carry unit level 2. Contains LACs for the root and level 1. Used in level 3
module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 3. Contains LACs for the root and level 2. Used in level 4
module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 4. Contains LACs for the root and level 3. Used in level 5
module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 1. Caontains LACs for the root and level 4. Used in the core alu32 module
module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
/************************
* Willard Wider
* 08-07-17
* ELEC3725
* ARMS.v
* building a 64 bit CPU
************************/
//ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.dbus(dbusout),.dselect(dselectout));
module ARMS(ibus,clk,dselect,dbus,reset,iaddrbus);
//just a clock
input clk;
//reset to clear the counter
input reset;
//instruction bus
output [63:0] iaddrbus;//from PC, to SIM_OUT
wire [63:0] iaddrbusWire1;//from mux, to PC
wire [63:0] iaddrbusWire2;//from PC, to mux4/iaddrbusWire4
wire [63:0] iaddrbusWire4;//from PC, to IF_ID
//SLT SLE control bits
//00 = nothing, 01 = SLT, 10 = SLE
reg [1:0] setControlBits;
wire [1:0] setControlBitsWire1;
wire [1:0] setControlBitsWire2;
//for SLT/SLE operations
//LEG_UPDATE: rs->rn, rt->rm
wire ZBit;//high when rn(a) - rm(b) = 0, 1 otherwise
wire [63:0] potentialSLEBit;//the value to set to dbus if it is a SLE operation
wire [63:0] potentialSLTBit;
wire [63:0] actualSLBit;
//the cout for the alu
wire ALUCoutWire;
//LEG_UPDATE: add the overflow counter from the ALU
wire overflowWire;
//LEG_UPDATE: 7 ways to branch, to update the control bit
//000 = noting, 001 = B, 010 = B.EQ
//011 = B.NE, 100 = B.LT, 101 = B.GE
//110 = CBNZ, 111 = CBZ
reg [2:0] branchControlBit;
wire [2:0] branchControlBitWire1;
wire [2:0] branchControlBitWire2;
wire [2:0] branchControlBitWire3;
reg takeBranch;
wire takeBranchWire1;
wire takeCondBranchWire1;
//program counter wires to be piped into the IF_ID stage
wire [63:0] PCWire1;//form IF_ID, to branchCalcWire1
//the wire for the branch calculation, part 1 (immediate sign extended, bit shifted by 2 for *4)
wire [63:0] branchCalcWire1;//from immediate, to branchCalcwire2
//the wire for the branch calculation, part 2 (+4)
wire [63:0] branchCalcWire2;//from branchCalcWire1, to mux4
//the new buses to and from the ddr memory
wire [63:0] daddrbus;//from EX_MEM, to SIM_OUT, was output
wire [63:0] databus;//from SIM_IN/EX_MEM, to SIM_OUT/MEM_WB, was inout
//decoder tings
//LEG_UPDATE: opcode is 11 bits long now
wire [10:0] opCode;//from IF_ID
//LEG_UPDATE: funktion is no longer a thing, everything is in the opcode
//wire [5:0] funktion;//from IF_ID
//LEG_UPDATE: NOP\'s should be redirected to nothing register
reg NOP;
wire NOPWire1;
wire NOPWire2;
wire NOPWire3;
//ibus
input [31:0] ibus;//in for IF_ID
wire [31:0] ibusWire;//out for IF_ID
//Aselect
wire [31:0] AselectWire;//from rs, to regfile
wire [31:0] AselectWire1;
//LEG_UPDATE: rs->rn
wire [5:0] rn;//from ibusWire, to AselectWire
//Bselect
wire [31:0] BselectWire;//from rt, to BselectWire1
wire [31:0] BselectWire1;//from BselectWire, to regfile
wire [31:0] BselectWire2;
//LEG_UPDATE: rt->rm
wire [5:0] rm;//from ibsuWire, to BselectWire and mxu1
//LEG_UPDATE: add a bit for MOVZ select
//mov select
reg movBit1;
wire movBit2;
wire [5:0] moveImmShftAmt;
wire [5:0] moveImmShftAmtWire1;
//imm select
reg immBit1;//from IF_ID(ibusWire), to mux1 and ID_EX
wire immBit2;//from ID_EX, to mux2
//LEG_UPDATE: add the NZVC bit and it\'s potential values
//the NZVC bit
wire [3:0]NZVC;
wire potentialNBit;
wire potentialZBit;
wire potentialVBit;
wire potentialCBit;
//the control for setting NZVC
reg NZVCSetBit;
wire NZVCSetBitWire1;
//LEG_UPDATE: add a control bit set for LSL and LSR
reg [1:0] shiftBit1;
wire [1:0] shiftBit2;
//LEG_UPDATE: add the potential LSL and LSR bits for shifting
wire [63:0] potentialLSLResult;
wire [63:0] potentialLSRResult;
wire [63:0] actualLSResult;
//load word save word flag
reg [1:0] lwSwFlag1;//from IF_ID, to ID_EX
wire [1:0] lwSwFlag2;//from ID_EX, to EX_MEM
wire [1:0] lwSwFlag3;//from EX_MEM, to MEM_WB
wire [1:0] lwSwFlag4;//from MEM_WB, to mux3
//Dselect
wire [31:0] DselectWire1;//from muxOut, to ID_EX
//LEG_UPDATE: rd->rd (no change)
wire [5:0] rd;//from ID_EX, to mux1
wire [31:0] DselectWire2;//from ID_EX, to EX_MM
wire [31:0] DselectWire3;//from EX_MEM, to MEM_WB
wire [31:0] DselectWire3_5;//from MEM_WB, to mux3
wire [31:0] DselectWire4;//from mux3, to regfile
output [31:0] dselect;
//LEG_UPDATE: new rt is also rd
//abus
//output [63:0] abus;//from ID_EX, to SIM_OUT
wire [63:0] abusWire1;//from regOut, to ID_EX
wire [63:0] abusWire2;//from ID_EX, to ALU
//bbus
//output [63:0] bbus;//from mux2Out, to SIM_OUT
wire [63:0] bbusWire1;//from regOut, to ID_EX
wire [63:0] bbusWire2;//from ID_EX, to mux2/EX_MEM
wire [63:0] bbusWire3;//from EX_MEM, to memory logic
wire [63:0] bbusWire3_5;//from memory logic, to MEM_WB
wire [63:0] bbusWire4;//from MEM_WB, to mux3
//dbus
wire [63:0] dbusWire1;//from ALU, to dbusWire1_5(SLE_MUX_TEST)
wire [63:0] dbusWire1_5;//from SLE_MUX_TEST to EX_MEM
wire [63:0] dbusWire1_6;
wire [63:0] dbusWire2;//from EM_MEM, to MEM_WB
wire [63:0] dbusWire3;//from MEM_WB, to mux3
output [63:0] dbus;
//mux3
wire [63:0] mux3Out;//from dbusWire3/bbusWire4, to regfile
//mux2
wire [63:0] mux2Out;//from bbusWire2/immWire2, to mux5
//LEG_UPDATE: mux5
wire [63:0] mux5;//from mux2Out/DTAddrWire2, to ALU (as b)
wire [63:0] mux6;
//mux4 deciding wire
wire mux4Controller;//controls the pc address bus
//LEG_UPDATE: remove sign extended IMM wire, it\'s not a thing
//immediate
//wire [63:0] immWire1;//from IF_ID, to ID_EX
//wire [63:0] immWire2;//from ID_EX, to mux2
//and add the new parsed wires
wire [63:0] ALUImmWire1;
wire [63:0] ALUImmWire2;
wire [63:0] BranchAddrWire1;
wire [63:0] CondBranchAddrType1Wire1;//for b.cond
wire [63:0] CondBranchAddrType2Wire1;//for CBZ/CBNZ
wire [63:0] MOVImmWire1;
wire [63:0] MOVImmWire2;
wire [5:0] shamt;
wire [5:0] shamtWire1;
wire [63:0] DTAddrWire1;
wire [63:0] DTAddrWire2;
wire [63:0] DTAddrWire3;
wire [63:0] DTAddrWire4;
//S
reg [2:0] SWire1;//from IF_ID, to ID_EX
wire [2:0] SWire2;//from ID_EX, to ALU
//Cin
reg CinWire1;//from IF_ID, to ID_EX
wire CinWire2;//form ID_EX, to ALU
//init
initial begin
immBit1 = 1\'bx;
movBit1 = 1\'bx;
NZVCSetBit = 1\'bx;
CinWire1 = 1\'bx;
SWire1 = 3\'bxxx;
lwSwFlag1 = 2\'bxx;
branchControlBit = 3\'b0;
setControlBits = 2\'b00;
shiftBit1 = 2\'bxx;
takeBranch = 1\'b0;
NOP = 1\'bx;
end
//latch for pipeline 0(PC)
//module pipeline_0_latch(clk, iaddrbusWire1, iaddrbusOut);
pipeline_0_latch PC(.clk(clk),.iaddrbusWire1(iaddrbusWire1),.iaddrbusOut(iaddrbusWire2),.reset(reset));
//iaddrbusWire4 gets feed into the IF_ID stage
assign iaddrbusWire4 = iaddrbusWire2;
//feed the pc back into itself. may update iaddrbusWire2 from the IF_ID stage
assign iaddrbusWire1 = mux4Controller? branchCalcWire2 : iaddrbusWire2;
//assign the output
assign iaddrbus = iaddrbusWire1;
//PIPELINE_0_END
//latch for pipeline 1(IF_ID)
//module pipeline_1_latch(clk, ibus, ibusWire);
pipeline_1_latch IF_ID(.clk(clk),.ibus(ibus),.ibusWire(ibusWire),.PCIn(iaddrbusWire4),.PCOut(PCWire1));
//PIPELINE_1_START
//decode the input command
//LEG_UPDATE: updated to new leg instruction sets
assign opCode = ibusWire[31:21];
assign rn = ibusWire[9:5];//old rs
assign rm = ibusWire[20:16];//old rt
assign rd = ibusWire[4:0];
assign shamt = ibusWire[15:10];
assign DTAddrWire1 = ibusWire[20]? {55\'b1,ibusWire[20:12]} : {55\'b0,ibusWire[20:12]};
assign moveImmShftAmt = ibusWire[22:21] << 4;
//LEG_UPDATE: added the following
assign ALUImmWire1 = {52\'b0, ibusWire[21:10]};
assign BranchAddrWire1 = ibusWire[25]? {36\'b1111,ibusWire[25:0],2\'b00} : {36\'b0000,ibusWire[25:0],2\'b00};
assign CondBranchAddrType1Wire1 = ibusWire[23]? {43\'b11111111111,ibusWire[23:5],2\'b00} : {43\'b00000000000,ibusWire[23:5],2\'b00};//b.cond
assign MOVImmWire1= {48\'b0, ibusWire[20:5]};
//LEG_UPDATE: remove the following
//assign immWire1 = ibusWire[15]? {16\'b1111111111111111,ibusWire[15:0]} : {16\'b0000000000000000,ibusWire[15:0]};
//for the change in the opcode which is like always
always @(ibusWire) begin
immBit1 = 0;
movBit1 = 0;
CinWire1 = 0;
branchControlBit = 3\'b000;
setControlBits = 0;
NZVCSetBit = 0;
//assume not doing anything with the load or save
lwSwFlag1 = 2\'b00;
shiftBit1 = 2\'b00;
NOP = 1\'b0;
//write the cases for the opcode (immediate)
//LEG_UPDATE: updated opcodes and branch condition codes
//000 = noting, 001 = B, 010 = B.EQ
//011 = B.NE, 100 = B.LT, 101 = B.GE
//110 = CBNZ, 111 = CBZ
casez (opCode)
11\'b10001011000: begin
//add
SWire1 = 3\'b010;//add
end
11\'b1001000100?: begin
//addi
SWire1 = 3\'b010;
immBit1 = 1;
end
11\'b1011000100?: begin
//addis
SWire1 = 3\'b010;
immBit1 = 1;
NZVCSetBit = 1;
end
11\'b10101011000: begin
//adds
SWire1 = 3\'b010;
NZVCSetBit = 1;
end
11\'b10001010000: begin
//and
SWire1 = 3\'b110;//and
end
11\'b1001001000?: begin
//andi
SWire1 = 3\'b110;
immBit1 = 1;
end
11\'b1111001000?: begin
//andis
SWire1 = 3\'b110;
immBit1 = 1;
NZVCSetBit = 1;
end
11\'b11101010000: begin
//ands
SWire1 = 3\'b110;
NZVCSetBit = 1;
end
11\'b10110101???: begin
//CBNZ
//add i guess
SWire1 = 3\'b010;
branchControlBit = 3\'b110;
//takeBranch = 1;
end
11\'b10110100???: begin
//CBZ
//add i guess
SWire1 = 3\'b010;
branchControlBit = 3\'b111;
//takeBranch = 1;
end
11\'b11001010000: begin
//EOR (xor)
SWire1 = 3\'b000;
end
11\'b1101001000?: begin
//EORI(xori)
SWire1 = 3\'b000;
immBit1 = 1;
end
11\'b11111000010: begin
//LDUR
//command: rt value = from memory address, of rn value added with DTAddr
//load word, but still addi
SWire1 = 3\'b010;
lwSwFlag1 = 2\'b01;
end
11\'b11010011011: begin
//LSL
//uses shamt wire and abus to set for dbus
//overwide bbus to be r31 and swire to be add
//therefore it does nothing and we\'re not jumping around the pipeline
shiftBit1 = 2\'b01;
SWire1 = 3\'b010;
end
11\'b11010011010: begin
//LSR
//see above notes
shiftBit1 = 2\'b10;
SWire1 = 3\'b010;
end
11\'b110100101??: begin
//MOVZ
movBit1 = 1;
SWire1 = 3\'b100;
end
11\'b10101010000: begin
//ORR(or)
SWire1 = 3\'b100;
end
11\'b1011001000?: begin
//ORRI(ori)
SWire1 = 3\'b100;
immBit1 = 1;
end
11\'b11111000000: begin
//STUR
//command: memory of address, rn value added with DTAddr = rt value
//store word, but still addi
SWire1 = 3\'b010;
lwSwFlag1 = 2\'b10;
end
11\'b11001011000: begin
//sub
SWire1 = 3\'b011;
CinWire1 = 1;
end
11\'b1101000100?: begin
//subi
SWire1 = 3\'b011;
CinWire1 = 1;
immBit1 = 1;
end
11\'b1111000100?: begin
//subis
SWire1 = 3\'b011;
CinWire1 = 1;
immBit1 = 1;
NZVCSetBit = 1;
end
11\'b11101011000: begin
//subs
SWire1 = 3\'b011;
CinWire1 = 1;
NZVCSetBit = 1;
end
//000 = noting, 001 = B, 010 = B.EQ
//011 = B.NE, 100 = B.LT, 101 = B.GE
//110 = CBNZ, 111 = CBZ
11\'b000101?????: begin
//B
SWire1 = 3\'b010;
//set control bit
branchControlBit = 3\'b001;
end
11\'b01010101???: begin
//B.EQ
SWire1 = 3\'b010;
//set control bit
branchControlBit = 3\'b010;
//takeBranch = (NZVC[2] == 1\'b1)? 1:0;
end
11\'b01010110???: begin
//B.NE
SWire1 = 3\'b010;
//set control bit
branchControlBit = 3\'b011;
//takeBranch = (NZVC[2] == 1\'b0)? 1:0;
end
11\'b01010111???: begin
//B.LT(signed)
SWire1 = 3\'b010;
//set control bit
branchControlBit = 3\'b100;
//takeBranch = (NZVC[3] != NZVC[1])? 1:0;
end
11\'b01011000???: begin
//B.GE(signed)
SWire1 = 3\'b010;
//set control bit
branchControlBit = 3\'b101;
//takeBranch = (NZVC[3] == NZVC[1])? 1:0;
end
11\'b00000000000: begin
//NOP
SWire1 = 3\'b010;
//set control bit
NOP = 1\'b1;
end
//TODO: figure out if these are ever used
/*11\'b: begin
//SLT
//00 = nothing, 01 = SLT, 10 = SLE
setControlBits = 2\'b01;
//set to subtraction
SWire1 = 3\'b011;
end
11\'b: begin
//SLE
//00 = nothing, 01 = SLT, 10 = SLE
setControlBits = 2\'b10;
//set to subtraction
SWire1 = 3\'b011;
end*/
endcase
end
always@(negedge clk) begin
takeBranch = 1\'b0;
//LEG_UPDATE: updated opcodes and branch condition codes
//000 = noting, 001 = B, 010 = B.EQ
//011 = B.NE, 100 = B.LT, 101 = B.GE
//110 = CBNZ, 111 = CBZ
case (branchControlBit)
3\'b000: begin//nothing
takeBranch = 0;
end
3\'b001: begin//B
takeBranch = 1;
end
3\'b010: begin//B.EQ
takeBranch = (NZVC[2] == 1\'b1)? 1:0;
end
3\'b011: begin//B.NE
takeBranch = (NZVC[2] == 1\'b0)? 1:0;
end
3\'b100: begin//B.LT
takeBranch = (NZVC[3] != NZVC[1])? 1:0;
end
3\'b101: begin//B.GE
takeBranch = (NZVC[3] == NZVC[1])? 1:0;
end
3\'b110: begin//CBNZ
takeBranch = (abusWire1 != 0)? 1:0;
end
3\'b111: begin//CBZ
takeBranch = (abusWire1 == 0)? 1:0;
end
endcase
end
//write the select lines
assign AselectWire = ((branchControlBit == 3\'b110) || (branchControlBit == 3\'b111))? 1<<rd :1 << rn;
//LEG_UPDATE: need AsSelectWire for the move command
assign AselectWire1 = (movBit1)? 32\'h80000000 : AselectWire;
//only write to Bselect for real if it\'s actually goign to use Bselect
//i don\'t think this line matters but i feel like it\'s good pratice
//assign BselectWire = immBit1? 32\'hxxxxxxxx: 1 << rt;
assign BselectWire = 1 << rm;
//LEG_UPDATE: set BselectWire to R31(0) if it\'s a LSL/LSR command
assign BselectWire1 = ((shiftBit1 > 2\'b00) || (movBit1))? 32\'h80000000:BselectWire;
//LEG_UPDATE: BselectWire may need to get data from Bbus in regfile if it\'s a store command
assign BselectWire2 = (lwSwFlag1 == 2\'b10)? 1<<rd:BselectWire1;
//LEG_UPDATE: rt->rm
//LEG_UPDATE: dbus always holds the result for the alu output now
//mux1
//Rd for R, imm = false
//Rt for I, imm = true
//assign DselectWire1 = immBit1? 1<<rm : 1<<rd;
assign DselectWire1 = 1<<rd;
regfile Reggie3(.clk(clk),.Aselect(AselectWire1),.Bselect(BselectWire2),.Dselect(DselectWire4),.abus(abusWire1),.bbus(bbusWire1),.dbus(mux3Out));
//update the muxWire4 controll if the instruction is BEQ or BNE, and if it is actually equal
//mux4Controller = 1 if ((BEQ and abus == bbus) or (BNE and bbus != abus)), 0 otherwise
//00 = noting, 01 = BEQ, 10 = BNE
//CBNZ = 110, CBZ = 111
//assign mux4Controller = ((!clk) && ((branchControlBit==2\'b01) && (abusWire1 == bbusWire1)) || ((branchControlBit==2\'b10) && (abusWire1!=bbusWire1)))? 1: 0;
//assign takeCondBranchWire1 = ((!clk) && ((branchControlBit==3\'b110) && (abusWire1 != 0)) || ((branchControlBit==3\'b111) && (abusWire1 == 0)))? 1:0;
//assign takeBranchWire1 = takeCondBranchWire1|takeBranch;
assign takeBranchWire1 = takeBranch;
assign mux4Controller = ((!clk) && (branchControlBit > 3\'b000) && (takeBranchWire1))? 1 : 0;
//LEG_UPDATE: TODO: branch calculation is done in one step from above
//the branch calculation
assign branchCalcWire1 = (branchControlBit == 3\'b001)? BranchAddrWire1:CondBranchAddrType1Wire1;
assign branchCalcWire2 = branchCalcWire1 + PCWire1 - 4;
//PIPELINE_1_END
//latch for pipeline 2(ID_EX)
pipeline_2_latch ED_EX(.clk(clk),.abusWire1(abusWire1),.bbusWire1(bbusWire1),.DselectWire1(DselectWire1),.ALUImmWire1(ALUImmWire1),.SWire1(SWire1),
.CinWire1(CinWire1),.immBit1(immBit1),.lwSwFlag1(lwSwFlag1),.abusWire2(abusWire2),.bbusWire2(bbusWire2),.ALUImmWire2(ALUImmWire2),.CinWire2(CinWire2),
.DselectWire2(DselectWire2),.immBit2(immBit2),.SWire2,.lwSwFlag2(lwSwFlag2),.setControlBits(setControlBits),.setControlBitsWire1(setControlBitsWire1),
.branchControlBit(branchControlBit),.branchControlBitWire1(branchControlBitWire1),.NZVCSetBit(NZVCSetBit),.NZVCSetBitWire1(NZVCSetBitWire1),
.shiftBit1(shiftBit1),.shiftBit2(shiftBit2),.shamt(shamt),.shamtWire1(shamtWire1),.DTAddrWire1(DTAddrWire1),.DTAddrWire2(DTAddrWire2),
.MOVImmWire1(MOVImmWire1),.MOVImmWire2(MOVImmWire2),.movBit1(movBit1),.movBit2(movBit2),.moveImmShftAmt(moveImmShftAmt),
.moveImmShftAmtWire1(moveImmShftAmtWire1),.NOP(NOP),.NOPWire1(NOPWire1));
//PIPELINE_2_START
//mux2
//ALUImmWire2 for true, Bselet for false
assign mux2Out = immBit2? ALUImmWire2: bbusWire2;
//LEG_UPDATE: add mux5 for selecting the DTAddrWire
assign mux5 = (lwSwFlag2 > 2\'b00)? DTAddrWire2:mux2Out;
assign mux6 = (movBit2)? MOVImmWire2:mux5;
//make the ALU
//module alu64 (d, Cout, V, a, b, Cin, S);
alu64 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux6),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire),.V(overflowWire));
//wipe the dbus if it\'s an SLT or an SLE
//zero result flag
assign ZBit = (dbusWire1==0)? 1:0;
//potential values for if the instruction is for SLT or SLE
assign potentialSLTBit = (!ALUCoutWire && !ZBit)? 64\'h0000000000000001:64\'h0000000000000000;
assign potentialSLEBit = (!ALUCoutWire || ZBit)? 64\'h0000000000000001:64\'h0000000000000000;
//a determinate wire that uses SLT or SLE, assuming if not one, than the other
//(a wire later decides if that always "lateer" choosen one is actually used
//00 = nothing, 01 = SLT, 10 = SLE
assign actualSLBit = (setControlBitsWire1 == 2\'b01)? potentialSLTBit: potentialSLEBit;
//the wire that is used for the new dbusWire, adds a check for if the result needs to be the SLT or not
//SLE_MUX_TEST
//LEG_UPDATE: hook into the SLE wire for the LSL-LSR commands
//assign dbusWire1_5 = (setControlBitsWire1 > 2\'b00)? actualSLBit:dbusWire1;
assign potentialLSLResult = dbusWire1 << shamtWire1;
assign potentialLSRResult = dbusWire1 >> shamtWire1;
//assumes LSR if not LSL. won\'t apply it to dbus unless it\'s actually a shift command
//2\'b01 = LSL, 2\'b10 = LSR
assign actualLSResult = (shiftBit2 == 2\'b10)? potentialLSRResult:potentialLSLResult;
assign dbusWire1_5 = (shiftBit2 > 2\'b00)? actualLSResult:dbusWire1;
//LEG_UPDATE: apply the mov command to dbus
assign dbusWire1_6 = (movBit2)? {dbusWire1_5 << moveImmShftAmtWire1}: dbusWire1_5;
//LEG_UPDATE: if the NZVCSetBit is set, then set the NZVC values with the potential values
assign potentialNBit = (dbusWire1[63] == 1\'b1)? 1\'b1:1\'b0;
assign potentialZBit = (ZBit)? 1\'b1:1\'b0;
assign potentialVBit = (overflowWire)? 1\'b1:1\'b0;
assign potentialCBit = (ALUCoutWire)? 1\'b1:1\'b0;
assign NZVC[3] = (NZVCSetBitWire1)? potentialNBit:1\'bz;//N (negative)
assign NZVC[2] = (NZVCSetBitWire1)? potentialZBit:1\'bz;//Z (zero)
assign NZVC[1] = (NZVCSetBitWire1)? potentialVBit:1\'bz;//V (overflow, signed)
assign NZVC[0] = (NZVCSetBitWire1)? potentialCBit:1\'bz;//C (carry)
//PIPELINE_2_END
//latch for pipeline 3(EX_MEM)
pipeline_3_latch EX_MEME (.clk(clk),.dbusWire1(dbusWire1_6),.DselectWire2(DselectWire2),.bbusWire2(bbusWire2),.lwSwFlag2(lwSwFlag2),.dbusWire2(dbusWire2),
.DselectWire3(DselectWire3),.bbusWire3(bbusWire3),.lwSwFlag3(lwSwFlag3),.branchControlBitWire1(branchControlBitWire1),.branchControlBitWire2(branchControlBitWire2),
.NOPWire1(NOPWire1),.NOPWire2(NOPWire2));
//PIPELINE_3_SRART
//assign output values
//LEG_UPDATE: if store, bbusWire3 has the data to be written
//if load,
assign bbusWire3_5 = (lwSwFlag3==2\'b01)? databus: bbusWire3;//2\'b01 = load
assign databus = (lwSwFlag3 == 2\'b10)? bbusWire3: 64\'hzzzzzzzz;//2\'b10 = store
assign daddrbus = dbusWire2;
//PIPELINE_3_END
//latch for pipeline 4(MEM_WB)
pipeline_4_latch MEM_WB (.clk(clk),.dbusWire2(dbusWire2),.DselectWire3(DselectWire3),.bbusWire3(bbusWire3_5),.lwSwFlag3(lwSwFlag3),.dbusWire3(dbusWire3),
.DselectWire4(DselectWire3_5),.bbusWire4(bbusWire4),.lwSwFlag4(lwSwFlag4),.branchControlBitWire2(branchControlBitWire2),
.branchControlBitWire3(branchControlBitWire3),.NOPWire2(NOPWire2),.NOPWire3(NOPWire3));
//PIPELINE_4_START
//the mux for the data writeBack
assign mux3Out = (lwSwFlag4 == 2\'b01)? bbusWire4:dbusWire3;//2\'b01 = load
assign dbus = mux3Out;
//disable the writeback if it\'s a store word OR if it\'s a branch OR if it\'s a NOP
//LEG_UPDATE: the address now is R31, 13\'h80000000
assign DselectWire4 = ((lwSwFlag4 == 2\'b10) ||(branchControlBitWire3 > 3\'b000) || (NOPWire3 == 1\'b1))? 32\'h80000000: DselectWire3_5;
assign dselect = DselectWire4;
//PIPELINE_4_END
endmodule
//phase 0 pipeline latch (PC)
module pipeline_0_latch(clk, iaddrbusWire1, iaddrbusOut, reset);
input clk, reset;
input [63:0] iaddrbusWire1;
output [63:0] iaddrbusOut;
reg [63:0] iaddrbusOut;
reg startBit;
initial begin
startBit = 1;
end
always@(posedge clk) begin
//if reset is high, reset the counter
//else incriment
iaddrbusOut = (reset|startBit)? 0:iaddrbusWire1+4;
startBit = 0;
end
endmodule
//phase 1 pipeline latch(IF_ID)
module pipeline_1_latch(clk, ibus, ibusWire, PCIn, PCOut);
input [31:0] ibus;
input [63:0] PCIn;
input clk;
output [31:0] ibusWire;
output [63:0] PCOut;
reg [31:0] ibusWire;
reg [63:0] PCOut;
always @(posedge clk) begin
//EDIT: this is delayed branching, other instructions can be put in place\\
//what did i mean by that? ^^
ibusWire = ibus;
PCOut = PCIn;
end
endmodule
//phase 2 pipeline latch(ID_EX)
module pipeline_2_latch(clk, abusWire1, bbusWire1, DselectWire1, ALUImmWire1, SWire1, CinWire1,immBit1,lwSwFlag1,
abusWire2,bbusWire2,ALUImmWire2,SWire2,CinWire2,DselectWire2,immBit2,lwSwFlag2,setControlBits,setControlBitsWire1,
branchControlBit,branchControlBitWire1,NZVCSetBit,NZVCSetBitWire1,shiftBit1,shiftBit2,shamt,shamtWire1,DTAddrWire1,
DTAddrWire2,MOVImmWire1,MOVImmWire2,movBit1,movBit2,moveImmShftAmt,moveImmShftAmtWire1,NOP,NOPWire1);
input clk, CinWire1,immBit1,NOP;
input [63:0] abusWire1, bbusWire1, ALUImmWire1,DTAddrWire1,MOVImmWire1;
input [31:0] DselectWire1;
input [2:0] SWire1;
input [1:0] lwSwFlag1;
input [1:0] setControlBits;
input [2:0] branchControlBit;
input NZVCSetBit;
input [1:0] shiftBit1;
input [5:0] shamt,moveImmShftAmt;
input movBit1;
output CinWire2,immBit2,NOPWire1;
output [63:0] abusWire2, bbusWire2, ALUImmWire2,DTAddrWire2,MOVImmWire2;
output [31:0] DselectWire2;
output [2:0] SWire2;
output [1:0] lwSwFlag2;
output [1:0] setControlBitsWire1;
output [2:0] branchControlBitWire1;
output NZVCSetBitWire1;
output [1:0] shiftBit2;
output [5:0] shamtWire1,moveImmShftAmtWire1;
output movBit2;
reg CinWire2,immBit2,NOPWire1;
reg [63:0] abusWire2, bbusWire2, ALUImmWire2,DTAddrWire2,MOVImmWire2;
reg [31:0] DselectWire2;
reg [2:0] SWire2;
reg [1:0] lwSwFlag2;
reg [1:0] setControlBitsWire1;
reg [2:0] branchControlBitWire1;
reg NZVCSetBitWire1;
reg [1:0] shiftBit2;
reg [5:0] shamtWire1,moveImmShftAmtWire1;
reg movBit2;
always @(posedge clk) begin
abusWire2 = abusWire1;
bbusWire2 = bbusWire1;
DselectWire2 = DselectWire1;
ALUImmWire2 = ALUImmWire1;
SWire2 = SWire1;
CinWire2 = CinWire1;
immBit2 = immBit1;
lwSwFlag2 = lwSwFlag1;
setControlBitsWire1 = setControlBits;
branchControlBitWire1 = branchControlBit;
NZVCSetBitWire1 = NZVCSetBit;
shiftBit2 = shiftBit1;
shamtWire1 = shamt;
DTAddrWire2 = DTAddrWire1;
MOVImmWire2 = MOVImmWire1;
movBit2 = movBit1;
moveImmShftAmtWire1 = moveImmShftAmt;
NOPWire1 = NOP;
end
endmodule
//phase 3 pipeliune latch(EX_MEM)
module pipeline_3_latch(clk, dbusWire1, DselectWire2, bbusWire2, lwSwFlag2, dbusWire2, DselectWire3,bbusWire3,lwSwFlag3,branchControlBitWire1,
branchControlBitWire2,NOPWire1,NOPWire2);
input clk;
input [63:0] dbusWire1, bbusWire2;
input [31:0] DselectWire2;
input [1:0] lwSwFlag2;
input [2:0] branchControlBitWire1;
input NOPWire1;
output [63:0] dbusWire2, bbusWire3;
output [31:0] DselectWire3;
output [1:0] lwSwFlag3;
output [2:0] branchControlBitWire2;
output NOPWire2;
reg [63:0] dbusWire2, bbusWire3;
reg [31:0] DselectWire3;
reg [1:0] lwSwFlag3;
reg [2:0] branchControlBitWire2;
reg NOPWire2;
always @(posedge clk) begin
dbusWire2 = dbusWire1;
DselectWire3 = DselectWire2;
bbusWire3 = bbusWire2;
lwSwFlag3 = lwSwFlag2;
branchControlBitWire2 = branchControlBitWire1;
NOPWire2 = NOPWire1;
end
endmodule
//phase 4 pipeline latch(MEM_WB)
module pipeline_4_latch(clk, dbusWire2, DselectWire3, bbusWire3, lwSwFlag3, dbusWire3, DselectWire4,bbusWire4,lwSwFlag4,branchControlBitWire2,
branchControlBitWire3,NOPWire2,NOPWire3);
input clk;
input [63:0] dbusWire2, bbusWire3;
input [31:0] DselectWire3;
input [1:0] lwSwFlag3;
input [2:0] branchControlBitWire2;
input NOPWire2;
output [63:0] dbusWire3, bbusWire4;
output [31:0] DselectWire4;
output [1:0] lwSwFlag4;
output [2:0] branchControlBitWire3;
output NOPWire3;
reg [63:0] dbusWire3, bbusWire4;
reg [31:0] DselectWire4;
reg [1:0] lwSwFlag4;
reg [2:0] branchControlBitWire3;
reg NOPWire3;
always @(posedge clk) begin
dbusWire3 = dbusWire2;
DselectWire4 = DselectWire3;
bbusWire4 = bbusWire3;
lwSwFlag4 = lwSwFlag3;
branchControlBitWire3 = branchControlBitWire2;
NOPWire3 = NOPWire2;
end
endmodule
module regfile(
input [31:0] Aselect,//select the register index to read from to store into abus
input [31:0] Bselect,//select the register index to read from to store into bbus
input [31:0] Dselect,//select the register to write to from dbus
input [63:0] dbus,//data in
output [63:0] abus,//data out
output [63:0] bbus,//data out
input clk
);
assign abus = Aselect[31] ? 64\'b0 : 64\'bz;
assign bbus = Bselect[31] ? 64\'b0 : 64\'bz;
DNegflipFlop myFlips[30:0](//32 wide register
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[30:0]),
.Bselect(Bselect[30:0]),
.Aselect(Aselect[30:0]),
.bbus(bbus),
.clk(clk)
);
endmodule
module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [63:0] dbus;
input Dselect;//the select write bit for this register
input Bselect;//the select read bit for this register
input Aselect;
input clk;
output [63:0] abus;
output [63:0] bbus;
wire wireclk;
reg [63:0] data;
assign wireclk = clk & Dselect;
initial begin
data = 64\'h0000000000000000;
end
always @(negedge clk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect? data : 64\'hzzzzzzzzzzzzzzzz;
assign bbus = Bselect? data : 64\'hzzzzzzzzzzzzzzzz;
endmodule
//Below this point is code from assignment 1//
//The declaration of the entire ALU itself.
module alu64 (d, Cout, V, a, b, Cin, S);
output[63:0] d;//the output bus
output Cout, V;//Cout is the bit for it it needs to carry over ?/ V is the overflow bit.
input [63:0] a, b;//the two input buses
input Cin;//the bit for marking if it is carrying over from a ?
input [2:0] S;//The select bus. It defines the operation to do with input busses a and b
wire [63:0] c, g, p;
wire gout, pout;
//The core ALU bus
alu_cell mycell[63:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
//the top Look-Ahead-Carry module.
lac6 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
//the overflow module
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[63]),
.Cin(Cin)
);
endmodule
//The module to handle a single bit operation for the top ALU module
module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;//generate carry
p = a ^ bint;//proragate carry
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule
//The module to handle the overflow bit
module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule
//Look-Ahead Carry unit level 1. Used for the root (level 1) and first child leafs (level 2)
module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule
//Look-Ahead Carry unit level 2. Contains LACs for the root and level 1. Used in level 3
module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 3. Contains LACs for the root and level 2. Used in level 4
module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 4. Contains LACs for the root and level 3. Used in level 5
module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 5. Contains LACs for the root and level 3. Used in level 6
module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 6. Caontains LACs for the root and level 5. Used in the core alu64 module
module lac6 (c, gout, pout, Cin, g, p);
output [63:0] c;
output gout, pout;
input Cin;
input [63:0] g, p;
wire [1:0] cint, gint, pint;
lac5 leaf0(
.c(c[31:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[31:0]),
.p(p[31:0])
);
lac5 leaf1(
.c(c[63:32]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[63:32]),
.p(p[63:32])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
|
//phase 3: testing LSL, LSR, 32bit
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:29];
wire [31:0] iaddrbus, dselect;
reg [31:0] iaddrbusout[0:29], dselectout[0:29];
wire [31:0] dbus;
reg [31:0] databusk, dbusout[0:29];
reg clk, reset;
reg clkd;
reg [31:0] dontcare;
reg [24*8:1] iname[0:29];
integer error, k, ntests;
//all opcode parameters to be used
parameter ADD = 11\'b10001011000;
parameter ADDI = 10\'b1001000100;
parameter ADDIS = 10\'b1011000100;
parameter ADDS = 11\'b10101011000;
parameter AND = 11\'b10001010000;
parameter ANDI = 10\'b1001001000;
parameter ANDIS = 10\'b1111001000;
parameter ANDS = 11\'b11101010000;
parameter CBNZ = 8\'b10110101;
parameter CBZ = 8\'b10110100;
parameter EOR = 11\'b11001010000;
parameter EORI = 10\'b1101001000;
parameter LDUR = 11\'b11111000010;
parameter LSL = 11\'b11010011011;
parameter LSR = 11\'b11010011010;
parameter MOVZ = 9\'b110100101;
parameter ORR = 11\'b10101010000;
parameter ORRI = 10\'b1011001000;
parameter STUR = 11\'b11111000000;
parameter SUB = 11\'b11001011000;
parameter SUBI = 10\'b1101000100;
parameter SUBIS = 10\'b1111000100;
parameter SUBS = 11\'b11101011000;
parameter B = 6\'b000101;
parameter B_EQ = 8\'b01010101;
parameter B_NE = 8\'b01010110;
parameter B_LT = 8\'b01010111;
parameter B_GT = 8\'b01011000;
//register parameters
parameter R0 = 5\'b00000;
parameter R0_dselect = 32\'b00000000000000000000000000000001;
parameter R18 = 5\'b10010;
parameter R18_dselect = 32\'b00000000000001000000000000000000;
parameter R19 = 5\'b10011;
parameter R19_dselect = 32\'b00000000000010000000000000000000;
parameter R20 = 5\'b10100;
parameter R20_dselect = 32\'b00000000000100000000000000000000;
parameter R21 = 5\'b10101;
parameter R21_dselect = 32\'b00000000001000000000000000000000;
parameter R22 = 5\'b10110;
parameter R22_dselect = 32\'b00000000010000000000000000000000;
parameter R23 = 5\'b10111;
parameter R23_dselect = 32\'b00000000100000000000000000000000;
parameter R24 = 5\'b11000;
parameter R24_dselect = 32\'b00000001000000000000000000000000;
parameter R25 = 5\'b11001;
parameter R25_dselect = 32\'b00000010000000000000000000000000;
parameter R26 = 5\'b11010;
parameter R26_dselect = 32\'b00000100000000000000000000000000;
parameter R27 = 5\'b11011;
parameter R27_dselect = 32\'b00001000000000000000000000000000;
parameter R28 = 5\'b11100;
parameter R28_dselect = 32\'b00010000000000000000000000000000;
parameter R29 = 5\'b11101;
parameter R29_dselect = 32\'b00100000000000000000000000000000;
parameter R30 = 5\'b11110;
parameter R30_dselect = 32\'b01000000000000000000000000000000;
parameter R31 = 5\'b11111;
parameter R31_dselect = 32\'b10000000000000000000000000000000;
//other parameterz to be used
parameter zeroSham = 6\'b000000;
parameter RX = 5\'b11111;
parameter oneShamt = 6\'b000001;
parameter twoShamt = 6\'b000010;
parameter threeShamt = 6\'b000011;
parameter eightShamt = 6\'b001000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.dbus(dbus),.dselect(dselect));
initial begin
dontcare = 32\'hx;
//phase 1: testing basic op commands and instruction bus
//* ADDI, R20, R31, #AAA
iname[0] = "ADDI, R20, R31, #AAA";//testing addi, result in R20 = 00000AAA
iaddrbusout[0] = 32\'h00000000;
// opcode rm/ALUImm rn rd...
instrbusin[0]={ADDI, 12\'hAAA, R31, R20};
dselectout[0] = R20_dselect;
dbusout[0] = 32\'h00000AAA;
//* ADDI, R31, R23, #002
iname[1] = "ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 00000000
iaddrbusout[1] = 32\'h00000004;
// opcode rm/ALUImm rn rd...
instrbusin[1]={ADDI, 12\'h002, R23, R31};
dselectout[1] = R31_dselect;
dbusout[1] = dontcare;
//* ADDI, R0, R23, #002
iname[2] = "ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 00000002
iaddrbusout[2] = 32\'h00000008;
// opcode rm/ALUImm rn rd...
instrbusin[2]={ADDI, 12\'h002, R23, R0};
dselectout[2] = R0_dselect;
dbusout[2] = 32\'h00000002;
//* ORRI, R21, R24, #001
iname[3] = "ORRI, R21, R24, #001";//testing ori, result in R21 = 00000001
iaddrbusout[3] = 32\'h0000000C;
// opcode rm/ALUImm rn rd...
instrbusin[3]={ORRI, 12\'h001, R24, R21};
dselectout[3] = R21_dselect;
dbusout[3] = 32\'h00000001;
//* EORI, R22, R20, #000
iname[4] = "EORI, R22, R20, #000";//testing xori, result in R22 = 00000AAA
iaddrbusout[4] = 32\'h00000010;
// opcode rm/ALUImm rn rd...
instrbusin[4]={EORI, 12\'h000, R20, R22};
dselectout[4] = R22_dselect;
dbusout[4] = 32\'h00000AAA;
//* ANDI, R23, R0, #003
iname[5] = "ANDI, R23, R0, #003";//testing andi, result in R23 = 00000002
iaddrbusout[5] = 32\'h00000014;
// opcode rm/ALUImm rn rd...
instrbusin[5]={ANDI, 12\'h003, R0, R23};
dselectout[5] = R23_dselect;
dbusout[5] = 32\'h00000002;
//* SUBI, R24, R20, #00A
iname[6] = "SUBI, R24, R20, #00A";//testing subi, result in R24 = 00000AA0
iaddrbusout[6] = 32\'h00000018;
// opcode rm/ALUImm rn rd...
instrbusin[6]={SUBI, 12\'h00A, R20, R24};
dselectout[6] = R24_dselect;
dbusout[6] = 32\'h00000AA0;
// op, rd, rn, rm
//* ADD, R25, R20, R0
iname[7] = "ADD, R25, R20, R0";//testing add, result in R25 = 00000AAC
iaddrbusout[7] = 32\'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7]={ADD, R0, zeroSham, R20, R25};
dselectout[7] = R25_dselect;
dbusout[7] = 32\'h00000AAC;
// op, rd, rn, rm
//* AND, R26, R20, R22
iname[8] = "AND, R26, R20, R22";//testing and, result in R26 = 00000AAA
iaddrbusout[8] = 32\'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8]={AND, R22, zeroSham, R20, R26};
dselectout[8] = R26_dselect;
dbusout[8] = 32\'h00000AAA;
// op, rd, rn, rm
//* XOR, R27, R23, R21
iname[9] = "EOR, R27, R23, R21";//testing xor, result in R27 = 00000003
iaddrbusout[9] = 32\'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9]={EOR, R21, zeroSham, R23, R27};
dselectout[9] = R27_dselect;
dbusout[9] = 32\'h00000003;
// op, rd, rn, rm
//* OR, R28, R25, R23
iname[10] = "ORR, R28, R25, R23";//testing or, result in R28 = 00000AAE
iaddrbusout[10] = 32\'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10]={ORR, R23, zeroSham, R25, R28};
dselectout[10] = R28_dselect;
dbusout[10] = 32\'h00000AAE;
// op, rd, rn, rm
//* SUB, R29, R20, R22
iname[11] = "SUB, R29, R20, R22";//testing sub, result in R29 = 00000000
iaddrbusout[11] = 32\'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11]={SUB, R22, zeroSham, R20, R29};
dselectout[11] = R29_dselect;
dbusout[11] = 32\'h00000000;
// op, rd, rn, aluImm
//* ADDI, R30, R31, #000
iname[12] = "ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 00000000
iaddrbusout[12] = 32\'h00000030;
// opcode rm/ALUImm rn rd...
instrbusin[12]={ADDI, 12\'h000, R31, R30};
dselectout[12] = R30_dselect;
dbusout[12] = 32\'h00000000;
//phase 2: testing basic op codes with the n,z,c flags
// op, rd, rn, aluImm
//* SUBIS,R20, R0, #003
iname[13] = "SUBIS,R20, R0, #003";//testing subis, n flag, result in R20 = FFFFFFFF
iaddrbusout[13] = 32\'h00000034;
// opcode rm/ALUImm rn rd...
instrbusin[13] = {SUBIS, 12\'h003, R0, R20};
dselectout[13] = dontcare;
dbusout[13] = dontcare;
// op, rd, rn, rm
//* SUBS, R21, R25, R28
iname[14] = "SUBS, R21, R25, R28";//testing subs, n flag, result in R21 = FFFFFFFE
iaddrbusout[14] = 32\'h00000038;
// op, rm, shamt, rn, rd
instrbusin[14] = {SUBS, R28, zeroSham, R25, R21};
dselectout[14] = dontcare;
dbusout[14] = dontcare;
// op, rd, rn, aluImm
//* ADDIS,R22, R31, #000
iname[15] = "ADDIS,R22, R31, #000";//testing addis, z flag, result in R22 = 00000000
iaddrbusout[15] = 32\'h0000003C;
// opcode rm/ALUImm rn rd...
instrbusin[15] = {ADDIS, 12\'h000, R31, R22};
dselectout[15] = dontcare;
dbusout[15] = dontcare;
// op, rd, rn, rm
//* ADDS R23, R20, R23
iname[16] = "ADDS R23, R20, R23";//testing adds, c flag, result in R23 = 00000001
iaddrbusout[16] = 32\'h00000040;
// op, rm, shamt, rn, rd
instrbusin[16] = {ADDS, R23, zeroSham, R20, R23};
dselectout[16] = dontcare;
dbusout[16] = dontcare;
// op, rd, rn, aluImm
//* ANDIS,R24, R20, #002
iname[17] = "ANDIS,R24, R20, #002";//testing andis, reseting n,z flags to low, result in R24 = 00000002
iaddrbusout[17] = 32\'h00000044;
// opcode rm/ALUImm rn rd...
instrbusin[17] = {ANDIS, 12\'h002, R20, R24};
dselectout[17] = dontcare;
dbusout[17] = dontcare;
// op, rd, rn, rm
//* ANDS, R25, R21, R20
iname[18] = "ANDS, R25, R21, R20";//testing ands, n flag, result in R25 = FFFFFFFE
iaddrbusout[18] = 32\'h00000048;
// op, rm, shamt, rn, rd
instrbusin[18] = {ANDS, R20, zeroSham, R21, R25};
dselectout[18] = dontcare;
dbusout[18] = dontcare;
//phase 3: testing LSL, LSR
//setting up the register R20 for a test of the LSL
// op, rd, rn, rm
iname[19] ="ADDI, R20, R31, #007";//setting up for left shift, result in R20 = 0000000000000007
iaddrbusout[19] = 64\'h0000004C;
// opcode rm/ALUImm rn rd
instrbusin[19] ={ADDI, 12\'h007, R31, R20};
dselectout[19] = R20_dselect;
dbusout[19] = 64\'h00000007;
// op, rd, rn, rm
iname[20] ="ADDI, R21, R31, #700";//setting up for right shift, n flag, result in R21 = 0000000000000700
iaddrbusout[20] = 64\'h00000050;
// opcode rm/ALUImm rn rd
instrbusin[20] ={ADDI, 12\'h700, R31, R21};
dselectout[20] = R21_dselect;
dbusout[20] = 64\'h00000700;
// op, rd, rn, rm
iname[21] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[21] = 64\'h00000054;
// op, rm, shamt, rn, rd
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
dselectout[21] = R19_dselect;
dbusout[21] = 64\'h00000000;
// op, rd, rn, rm
iname[22] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[22] = 64\'h00000058;
// op, rm, shamt, rn, rd
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
dselectout[22] = R18_dselect;
dbusout[22] = 64\'h00000000;
// op, rd, rn, rm
iname[23] ="LSL, R20, R20, 2";//testing left shift, result in R20 = 0000000000000700
iaddrbusout[23] = 64\'h0000005C;
// op, rm, shamt, rn, rd
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
dselectout[23] = R20_dselect;
dbusout[23] = 64\'h00000700;
// op, rd, rn, rm
iname[24] ="LSR, R21, R21, 2";//testing right shift, result in R21 = 0000000000000007
iaddrbusout[24] = 64\'h00000060;
// op, rm, shamt, rn, rd
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
dselectout[24] = R21_dselect;
dbusout[24] = 64\'h00000007;
//finishing up
iname[25] = "NOP";//nada
iaddrbusout[25] = 64\'h00000064;
instrbusin[25] = 64\'b0;
dselectout[25] = dontcare;
dbusout[25] = dontcare;
iname[26] = "NOP";//nada
iaddrbusout[26] = 64\'h00000068;
instrbusin[26] = 64\'b0;
dselectout[26] = dontcare;
dbusout[26] = dontcare;
iname[27] = "NOP";//nada
iaddrbusout[27] = 64\'h0000006C;
instrbusin[27] = 64\'b0;
dselectout[27] = dontcare;
dbusout[27] = dontcare;
iname[28] = "NOP";//nada
iaddrbusout[28] = 64\'h00000070;
instrbusin[28] = 64\'b0;
dselectout[28] = dontcare;
dbusout[28] = dontcare;
iname[29] = "NOP";//nada
iaddrbusout[29] = 64\'h00000074;
instrbusin[29] = 64\'b0;
dselectout[29] = dontcare;
dbusout[29] = dontcare;
//remember to set k down below to ntests - 1
ntests = 30;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
//assign databus = clkd ? 64\'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
//databusk = 64\'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
$display ("Time=%t\
clk=%b", $realtime, clk);
for (k=0; k<= 29; k=k+1) begin
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set dbus and dselect data data for 4th previous instruction
if (k >=4)
//databusk = databusin[k-4];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b%b%b%b%b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check writeback data address from 4th previous instruction
if ( (k >= 4) && (dselectout[k-4] !== dontcare) ) begin
$display (" Testing writeback data address for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dselect = %b", dselect);
$display (" Correct dselect = %b", dselectout[k-4]);
if (dselectout[k-4] !== dselect) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check writeback data from 4th previous instruction
if ( (k >= 4) && (dbusout[k-4] !== dontcare) ) begin
$display (" Testing writeback data for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dbus = %b", dbus);
$display (" Correct dbus = %b", dbusout[k-4]);
if (dbusout[k-4] !== dbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
//phase 4: testing load and store instructions. the processor is now 64 bit
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:34];
wire [63:0] iaddrbus, daddrbus;
reg [63:0] iaddrbusout[0:34], daddrbusout[0:34];
wire [63:0] databus;
reg [63:0] databusk, databusin[0:34], databusout[0:34];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [24*8:1] iname[0:34];
integer error, k, ntests;
//all opcode parameters to be used
parameter ADD = 11\'b10001011000;
parameter ADDI = 10\'b1001000100;
parameter ADDIS = 10\'b1011000100;
parameter ADDS = 11\'b10101011000;
parameter AND = 11\'b10001010000;
parameter ANDI = 10\'b1001001000;
parameter ANDIS = 10\'b1111001000;
parameter ANDS = 11\'b11101010000;
parameter CBNZ = 8\'b10110101;
parameter CBZ = 8\'b10110100;
parameter EOR = 11\'b11001010000;
parameter EORI = 10\'b1101001000;
parameter LDUR = 11\'b11111000010;
parameter LSL = 11\'b11010011011;
parameter LSR = 11\'b11010011010;
parameter MOVZ = 9\'b110100101;
parameter ORR = 11\'b10101010000;
parameter ORRI = 10\'b1011001000;
parameter STUR = 11\'b11111000000;
parameter SUB = 11\'b11001011000;
parameter SUBI = 10\'b1101000100;
parameter SUBIS = 10\'b1111000100;
parameter SUBS = 11\'b11101011000;
parameter B = 6\'b000101;
parameter B_EQ = 8\'b01010101;
parameter B_NE = 8\'b01010110;
parameter B_LT = 8\'b01010111;
parameter B_GT = 8\'b01011000;
//register parameters
parameter R0 = 5\'b00000;
parameter R15 = 5\'b01111;
parameter R16 = 5\'b10000;
parameter R17 = 5\'b10001;
parameter R18 = 5\'b10010;
parameter R19 = 5\'b10011;
parameter R20 = 5\'b10100;
parameter R21 = 5\'b10101;
parameter R22 = 5\'b10110;
parameter R23 = 5\'b10111;
parameter R24 = 5\'b11000;
parameter R25 = 5\'b11001;
parameter R26 = 5\'b11010;
parameter R27 = 5\'b11011;
parameter R28 = 5\'b11100;
parameter R29 = 5\'b11101;
parameter R30 = 5\'b11110;
parameter R31 = 5\'b11111;
//other parameterz to be used
parameter zeroSham = 6\'b000000;
parameter RX = 5\'b11111;
parameter oneShamt = 6\'b000001;
parameter twoShamt = 6\'b000010;
parameter threeShamt = 6\'b000011;
parameter eightShamt = 6\'b001000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
dontcare = 64\'hx;
//phase 1: testing basic op commands
// op, rd, rn, rm
iname[0] ="ADDI, R20, R31, #AAA";//testing addi, result in R20 = 0000000000000AAA
iaddrbusout[0] = 64\'h00000000;
// opcode rm/ALUImm rn rd
instrbusin[0] ={ADDI, 12\'hAAA, R31, R20};
daddrbusout[0] = dontcare;
databusin[0] = 64\'bz;
databusout[0] = dontcare;
// op, rd, rn, rm
iname[1] ="ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 0000000000000000
iaddrbusout[1] = 64\'h00000004;
// opcode rm/ALUImm rn rd
instrbusin[1] ={ADDI, 12\'h002, R23, R31};
daddrbusout[1] = dontcare;
databusin[1] = 64\'bz;
databusout[1] = dontcare;
// op, rd, rn, rm
iname[2] ="ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 0000000000000002
iaddrbusout[2] = 64\'h00000008;
// opcode rm/ALUImm rn rd
instrbusin[2] ={ADDI, 12\'h002, R23, R0};
daddrbusout[2] = dontcare;
databusin[2] = 64\'bz;
databusout[2] = dontcare;
// op, rd, rn, rm
iname[3] ="ORRI, R21, R24, #001";//testing ori, result in R21 = 0000000000000001
iaddrbusout[3] = 64\'h0000000C;
// opcode rm/ALUImm rn rd
instrbusin[3] ={ORRI, 12\'h001, R24, R21};
daddrbusout[3] = dontcare;
databusin[3] = 64\'bz;
databusout[3] = dontcare;
// op, rd, rn, rm
iname[4] ="EORI, R22, R20, #000";//testing xori, result in R22 = 0000000000000AAA
iaddrbusout[4] = 64\'h00000010;
// opcode rm/ALUImm rn rd
instrbusin[4] ={EORI, 12\'h000, R20, R22};
daddrbusout[4] = dontcare;
databusin[4] = 64\'bz;
databusout[4] = dontcare;
// op, rd, rn, rm
iname[5] ="ANDI, R23, R0, #003";//testing andi, result in R23 = 0000000000000002
iaddrbusout[5] = 64\'h00000014;
// opcode rm/ALUImm rn rd
instrbusin[5] ={ANDI, 12\'h003, R0, R23};
daddrbusout[5] = dontcare;
databusin[5] = 64\'bz;
databusout[5] = dontcare;
// op, rd, rn, rm
iname[6] ="SUBI, R24, R20, #00A";//testing subi, result in R24 = 0000000000000AA0
iaddrbusout[6] = 64\'h00000018;
// opcode rm/ALUImm rn rd
instrbusin[6] ={SUBI, 12\'h00A, R20, R24};
daddrbusout[6] = dontcare;
databusin[6] = 64\'bz;
databusout[6] = dontcare;
// op, rd, rn, rm
iname[7] ="ADD, R25, R20, R0";//testing add, result in R25 = 0000000000000AAC
iaddrbusout[7] = 64\'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7] ={ADD, R0, zeroSham, R20, R25};
daddrbusout[7] = dontcare;
databusin[7] = 64\'bz;
databusout[7] = dontcare;
// op, rd, rn, rm
iname[8] ="AND, R26, R20, R22";//testing and, result in R26 = 0000000000000AAA
iaddrbusout[8] = 64\'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8] ={AND, R22, zeroSham, R20, R26};
daddrbusout[8] = dontcare;
databusin[8] = 64\'bz;
databusout[8] = dontcare;
// op, rd, rn, rm
iname[9] ="EOR, R27, R23, R21";//testing xor, result in R27 = 0000000000000003
iaddrbusout[9] = 64\'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9] ={EOR, R21, zeroSham, R23, R27};
daddrbusout[9] = dontcare;
databusin[9] = 64\'bz;
databusout[9] = dontcare;
// op, rd, rn, rm
iname[10] ="ORR, R28, R25, R23";//testing or, result in R28 = 0000000000000AAE
iaddrbusout[10] = 64\'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10] ={ORR, R23, zeroSham, R25, R28};
daddrbusout[10] = dontcare;
databusin[10] = 64\'bz;
databusout[10] = dontcare;
// op, rd, rn, rm
iname[11] ="SUB, R29, R20, R22";//testing sub, result in R29 = 0000000000000000
iaddrbusout[11] = 64\'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11] ={SUB, R22, zeroSham, R20, R29};
daddrbusout[11] = dontcare;
databusin[11] = 64\'bz;
databusout[11] = dontcare;
// op, rd, rn, aluImm
iname[12] ="ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 0000000000000000
iaddrbusout[12] = 64\'h00000030;
// opcode rm/ALUImm rn rd
instrbusin[12] ={ADDI, 12\'h000, R31, R30};
daddrbusout[12] = dontcare;
databusin[12] = 64\'bz;
databusout[12] = dontcare;
//phase 2: testing basic op codes with the set flags
// op, rd, rn, aluImm
iname[13] ="SUBIS,R20, R0, #003";//testing subis, n flag, result in R20 = FFFFFFFFFFFFFFFF
iaddrbusout[13] = 64\'h00000034;
// opcode rm/ALUImm rn rd
instrbusin[13] ={SUBIS, 12\'h003, R0, R20};
daddrbusout[13] = dontcare;
databusin[13] = 64\'bz;
databusout[13] = dontcare;
// op, rd, rn, rm
iname[14] ="SUBS, R21, R25, R28";//testing subs, n flag, result in R21 = FFFFFFFFFFFFFFFE
iaddrbusout[14] = 64\'h00000038;
// op, rm, shamt, rn, rd
instrbusin[14] ={SUBS,R28,zeroSham, R25, R21};
daddrbusout[14] = dontcare;
databusin[14] = 64\'bz;
databusout[14] = dontcare;
// op, rd, rn, aluImm
iname[15] ="ADDIS,R22, R31, #000";//testing addis, z flag, result in R22 = 0000000000000000
iaddrbusout[15] = 64\'h0000003C;
// opcode rm/ALUImm rn rd
instrbusin[15] ={ADDIS, 12\'h000, R31, R22};
daddrbusout[15] = dontcare;
databusin[15] = 64\'bz;
databusout[15] = dontcare;
// op, rd, rn, rm
iname[16] ="ADDS R23, R20, R23";//testing adds, c flag, result in R23 = 0000000000000001
iaddrbusout[16] = 64\'h00000040;
// op, rm, shamt, rn, rd
instrbusin[16] ={ADDS,R23,zeroSham, R20, R23};
daddrbusout[16] = dontcare;
databusin[16] = 64\'bz;
databusout[16] = dontcare;
// op, rd, rn, aluImm
iname[17] ="ANDIS,R24, R20, #002";//testing andis, reseting n,z flags to low, result in R24 = 0000000000000002
iaddrbusout[17] = 64\'h00000044;
// opcode rm/ALUImm rn rd
instrbusin[17] ={ANDIS, 12\'h002, R20, R24};
daddrbusout[17] = dontcare;
databusin[17] = 64\'bz;
databusout[17] = dontcare;
// op, rd, rn, rm
iname[18] ="ANDS, R25, R21, R20";//testing ands, n flag, result in R25 = FFFFFFFFFFFFFFFE
iaddrbusout[18] = 64\'h00000048;
// op, rm, shamt, rn, rd
instrbusin[18] ={ANDS, R20, zeroSham, R21, R25};
daddrbusout[18] = dontcare;
databusin[18] = 64\'bz;
databusout[18] = dontcare;
//phase 3: testing LSL, LSR
//setting up the register R20 for a test of the LSL
// op, rd, rn, rm
iname[19] ="ADDI, R20, R31, #007";//setting up for left shift, result in R20 = 0000000000000007
iaddrbusout[19] = 64\'h0000004C;
// opcode rm/ALUImm rn rd
instrbusin[19] ={ADDI, 12\'h007, R31, R20};
daddrbusout[19] = dontcare;
databusin[19] = 64\'bz;
databusout[19] = dontcare;
// op, rd, rn, rm
iname[20] ="ADDI, R21, R31, #700";//setting up for right shift, n flag, result in R21 = 0000000000000700
iaddrbusout[20] = 64\'h00000050;
// opcode rm/ALUImm rn rd
instrbusin[20] ={ADDI, 12\'h700, R31, R21};
daddrbusout[20] = dontcare;
databusin[20] = 64\'bz;
databusout[20] = dontcare;
// op, rd, rn, rm
iname[21] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[21] = 64\'h00000054;
// op, rm, shamt, rn, rd
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
daddrbusout[21] = dontcare;
databusin[21] = 64\'bz;
databusout[21] = dontcare;
// op, rd, rn, rm
iname[22] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[22] = 64\'h00000058;
// op, rm, shamt, rn, rd
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
daddrbusout[22] = dontcare;
databusin[22] = 64\'bz;
databusout[22] = dontcare;
// op, rd, rn, rm
iname[23] ="LSL, R20, R20, 2";//testing left shift, result in R20 = 0000000000000700
iaddrbusout[23] = 64\'h0000005C;
// op, rm, shamt, rn, rd
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
daddrbusout[23] = dontcare;
databusin[23] = 64\'bz;
databusout[23] = dontcare;
// op, rd, rn, rm
iname[24] ="LSR, R21, R21, 2";//testing right shift, result in R21 = 0000000000000007
iaddrbusout[24] = 64\'h00000060;
// op, rm, shamt, rn, rd
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
daddrbusout[24] = dontcare;
databusin[24] = 64\'bz;
databusout[24] = dontcare;
//phase 4: testing load and store
// op, rt, rn, DT_adr
iname[25] ="LDUR, R22, R31, #1";//testing load, result in R22 = 42069 (from memory,databusin) [yes, really]
iaddrbusout[25] = 64\'h00000064;
// op, DT_ADDR, ?, rn, rt
instrbusin[25] ={LDUR, 9\'b000000001, 2\'b00, R31, R22};
daddrbusout[25] = 64\'h0000000000000001;//used for LDUR
databusin[25] = 64\'h0000000000042069;//used for LDUR
databusout[25] = dontcare;
// op, rn, DT_adr, rt
iname[26] ="STUR, R23, #068, R24";//testing story, result for databusout in R24 = 0000000000000002 (to memory)
//address is calculated from imm or 68, and R23, which is currently 1
iaddrbusout[26] = 64\'h00000068;
// op, DT_ADDR, ?, rn, rt
instrbusin[26] ={STUR, 9\'b001101000, 2\'b00, R23, R24};
daddrbusout[26] = 64\'h0000000000000069;//used for STUR
databusin[26] = 64\'bz;
databusout[26] = 64\'h0000000000000002;//used for STUR
// op, rd, rn, rm
iname[27] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[27] = 64\'h0000006C;
// op, rm, shamt, rn, rd
instrbusin[27] ={AND, R31, zeroSham, R31, R19};
daddrbusout[27] = dontcare;
databusin[27] = 64\'bz;
databusout[27] = dontcare;
// op, rd, rn, rm
iname[28] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[28] = 64\'h00000070;
// op, rm, shamt, rn, rd
instrbusin[28] ={AND, R31, zeroSham, R31, R19};
daddrbusout[28] = dontcare;
databusin[28] = 64\'bz;
databusout[28] = dontcare;
// op, rd, rn, rm
iname[29] ="AND, R17, R31, R31";//delay, result in R17 = 0000000000000000
iaddrbusout[29] = 64\'h00000074;
// op, rm, shamt, rn, rd
instrbusin[29] ={AND, R31, zeroSham, R31, R19};
daddrbusout[29] = dontcare;
databusin[29] = 64\'bz;
databusout[29] = dontcare;
//finishing up
iname[30] = "NOP";//nada
iaddrbusout[30] = 64\'h00000078;
instrbusin[30] = 64\'b0;
daddrbusout[30] = dontcare;
databusin[30] = 64\'bz;
databusout[30] = dontcare;
iname[31] = "NOP";//nada
iaddrbusout[31] = 64\'h0000007C;
instrbusin[31] = 64\'b0;
daddrbusout[31] = dontcare;
databusin[31] = 64\'bz;
databusout[31] = dontcare;
iname[32] = "NOP";//nada
iaddrbusout[32] = 64\'h00000080;
instrbusin[32] = 64\'b0;
daddrbusout[32] = dontcare;
databusin[32] = 64\'bz;
databusout[32] = dontcare;
iname[33] = "NOP";//nada
iaddrbusout[33] = 64\'h00000084;
instrbusin[33] = 64\'b0;
daddrbusout[33] = dontcare;
databusin[33] = 64\'bz;
databusout[33] = dontcare;
iname[34] = "NOP";//nada
iaddrbusout[34] = 64\'h00000088;
instrbusin[34] = 64\'b0;
daddrbusout[34] = dontcare;
databusin[34] = 64\'bz;
databusout[34] = dontcare;
//remember to set k down below to ntests - 1
ntests = 35;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
assign databus = clkd ? 64\'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
databusk = 64\'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
$display ("Time=%t\
clk=%b", $realtime, clk);
for (k=0; k<= 34; k=k+1) begin
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set load data for 3rd previous instruction
if (k >=3)
databusk = databusin[k-3];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check data address from 3rd previous instruction
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check store data from 3rd previous instruction
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
\tGSR_int = 1'b1;
\tPRLD_int = 1'b1;
\t#(ROC_WIDTH)
\tGSR_int = 1'b0;
\tPRLD_int = 1'b0;
end
initial begin
\tGTS_int = 1'b1;
\t#(TOC_WIDTH)
\tGTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns/10ps
module controller_testbench();
reg [31:0] ibustm[0:31], ibus, Ref_Aselect[0:31], Ref_Bselect[0:31],Ref_Dselect[0:31];
reg clk, Ref_Imm[0:31], Ref_Cin[0:31];
reg [2:0] Ref_S[0:31];
wire [2:0] S;
wire Cin,Imm;
wire [31:0] Aselect,Bselect, Dselect;
reg [31:0] dontcare;
reg neglect;
reg [2:0] neg;
integer error, k, ntests;
parameter ADDI = 6\'b000011;
parameter SUBI = 6\'b000010;
parameter XORI = 6\'b000001;
parameter ANDI = 6\'b001111;
parameter ORI = 6\'b001100;
parameter Rformat = 6\'b000000;
parameter ADD = 6\'b000011;
parameter SUB = 6\'b000010;
parameter XOR = 6\'b000001;
parameter AND = 6\'b000111;
parameter OR = 6\'b000100;
parameter SADD = 3\'b010;
parameter SSUB = 3\'b011;
parameter SXOR = 3\'b000;
parameter SAND = 3\'b110;
parameter SOR = 3\'b100;
controller dut(.ibus(ibus), .clk(clk), .Cin(Cin), .Imm(Imm), .S(S) , .Aselect(Aselect) , .Bselect(Bselect), .Dselect(Dselect));
initial begin
dontcare = 32\'hxxxxxxxx;
neglect = 1\'bx;
neg = 3\'bxxx;
// ----------
// 1. Begin test clear SUB R13, R0, R0
// ----------
// opcode source1 source2 dest shift Function...
ibustm[0]={Rformat, 5\'b00000, 5\'b00000, 5\'b01101, 5\'b00000, SUB};
ibustm[1]={Rformat, 5\'b00000, 5\'b00000, 5\'b01101, 5\'b00000, SUB};
Ref_Aselect[1] = 32\'b00000000000000000000000000000001; //input 1
Ref_Bselect[1] = 32\'b00000000000000000000000000000001; //input 1
Ref_Dselect[1] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Imm[1] =1\'bx;
Ref_Cin[1] =1\'bx;
Ref_S[1] = 3\'bxxx;
// ----------
// 2. ADDI R1, R0, #FFFF
// ----------
// opcode source1 dest Immediate...
ibustm[2]={ADDI, 5\'b00000, 5\'b00001, 16\'hFFFF};
Ref_Aselect[2] = 32\'b00000000000000000000000000000001; //input2
Ref_Bselect[2] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input2
Ref_Dselect[2] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input2
Ref_Imm[2] =1\'b0; //input1
Ref_Cin[2] =1\'b1; //input1
Ref_S[2] = SSUB; //input1
// ----------
// 3. ADDI R0, R0, #FFFF
// ----------
// opcode source1 dest Immediate...
ibustm[3]={ADDI, 5\'b00000, 5\'b00000, 16\'hFFFF};
Ref_Aselect[3] = 32\'b0000000000000000000000000000001; //input3
Ref_Bselect[3] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input3
Ref_Dselect[3] = 32\'b0000000000000000010000000000000; //input1
Ref_Imm[3] =1\'b1; //input2
Ref_Cin[3] =1\'b0; //input2
Ref_S[3] = SADD; //input2
// ----------
// 4. ADDI R30, R1,#AFC0
// ----------
// opcode source1 dest Immediate...
ibustm[4]={ADDI, 5\'b00001, 5\'b11110, 16\'hAFC0};
Ref_Aselect[4] = 32\'b00000000000000000000000000000010; //input4
Ref_Bselect[4] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input4
Ref_Dselect[4] = 32\'b00000000000000000000000000000010; //input2
Ref_Imm[4] =1\'b1; //input3
Ref_Cin[4] =1\'b0; //input3
Ref_S[4] = SADD; //input3
// ----------
// 5. SUB R0, R0, R0
// ----------
// opcode source1 source2 dest shift Function...
ibustm[5]={Rformat, 5\'b00000, 5\'b00000, 5\'b00000, 5\'b00000, SUB};
Ref_Aselect[5] = 32\'b0000000000000000000000000000001; //input5
Ref_Bselect[5] = 32\'b0000000000000000000000000000001; //input5
Ref_Dselect[5] = 32\'b0000000000000000000000000000001; //input3
Ref_Imm[5] =1\'b1; //input4
Ref_Cin[5] =1\'b0; //input4
Ref_S[5] = SADD; //input4
// ---------- // 6. XORI R3, R0, #8CCB
// ----------
// opcode source1 dest Immediate...
ibustm[6]={XORI, 5\'b00000, 5\'b00011, 16\'h8CCB};
Ref_Aselect[6] = 32\'b00000000000000000000000000000001; //input6
Ref_Bselect[6] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input6
Ref_Dselect[6] = 32\'b01000000000000000000000000000000; //input4
Ref_Imm[6] =1\'b0; //input5
Ref_Cin[6] =1\'b1; //input5
Ref_S[6] = SSUB; //input5
// ----------
// 7. ORI R21, R0, #F98B
// ----------
// opcode source1 dest Immediate...
ibustm[7]={ORI, 5\'b00000, 5\'b10101, 16\'hF98B};
Ref_Aselect[7] = 32\'b00000000000000000000000000000001;//input7
Ref_Bselect[7] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;//input7
Ref_Dselect[7] = 32\'b00000000000000000000000000000001; //input5
Ref_Imm[7] =1\'b1; //input6
Ref_Cin[7] =1\'b0; //input6
Ref_S[7] = SXOR; //input6
// ----------
// 8. XOR R16, R1, R3
// ----------
// opcode source1 source2 dest shift Function...
ibustm[8]={Rformat, 5\'b00001, 5\'b00011, 5\'b10000, 5\'b00000, XOR};
Ref_Aselect[8] = 32\'b00000000000000000000000000000010; //input8
Ref_Bselect[8] = 32\'b00000000000000000000000000001000; //input8
Ref_Dselect[8] = 32\'b00000000000000000000000000001000; //input6
Ref_Imm[8] =1\'b1; //input7
Ref_Cin[8] =1\'b0; //input7
Ref_S[8] = SOR; //input7
// ----------
// 9. SUBI R31, R21, #0030
// ----------
// opcode source1 dest Immediate...
ibustm[9]={SUBI, 5\'b10101, 5\'b11111, 16\'h0030};
Ref_Aselect[9] = 32\'b00000000001000000000000000000000;//input9
Ref_Bselect[9] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;//input9
Ref_Dselect[9] = 32\'b00000000001000000000000000000000;//input7
Ref_Imm[9] =1\'b0; //input8
Ref_Cin[9] =1\'b0; //input8
Ref_S[9] = SXOR; //input8
// ----------
// 10. XOR R5, R16, R21
// ----------
// opcode source1 source2 dest shift Function...
ibustm[10]={Rformat, 5\'b10000, 5\'b10101, 5\'b00101, 5\'b00000, XOR};
Ref_Aselect[10] = 32\'b00000000000000010000000000000000; //input10
Ref_Bselect[10] = 32\'b00000000001000000000000000000000; //input10
Ref_Dselect[10] = 32\'b00000000000000010000000000000000; //input8
Ref_Imm[10] =1\'b1; //input9
Ref_Cin[10] =1\'b1; //input9
Ref_S[10] = SSUB; //input9
// ------------
// 11. ORI R10, R0, #34FB
// ------------
// opcode source1 dest Immediate...
ibustm[11]={ORI, 5\'b00000, 5\'b01010, 16\'h34FB};
Ref_Aselect[11] = 32\'b00000000000000000000000000000001;//input11
Ref_Bselect[11] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;//input11
Ref_Dselect[11] = 32\'b10000000000000000000000000000000;//input9
Ref_Imm[11] =1\'b0; //input10
Ref_Cin[11] =1\'b0; //input10
Ref_S[11] = SXOR; //input10
// ------------
// 12. XORI R18, R1, #0B31
// ------------
// opcode source1 dest Immediate...
ibustm[12]={XORI, 5\'b00001, 5\'b10010, 16\'h0B31};
Ref_Aselect[12] = 32\'b00000000000000000000000000000010; //input12
Ref_Bselect[12] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input12
Ref_Dselect[12] = 32\'b00000000000000000000000000100000; //input10
Ref_Imm[12] =1\'b1; //input11
Ref_Cin[12] =1\'b0; //input11
Ref_S[12] = SOR; //input11
// ---------
// 13. ADD R24, R16, R3
// ---------
// opcode source1 source2 dest shift Function...
ibustm[13]={Rformat, 5\'b10000, 5\'b00011, 5\'b11000, 5\'b00000, ADD};
Ref_Aselect[13] = 32\'b00000000000000010000000000000000;//input13
Ref_Bselect[13] = 32\'b00000000000000000000000000001000;//input13
Ref_Dselect[13] = 32\'b00000000000000000000010000000000;//input11
Ref_Imm[13] =1\'b1; //input12
Ref_Cin[13] =1\'b0; //input12
Ref_S[13] = SXOR; //input12
// ---------
// 14. OR R7, R10, R10
// ---------
// opcode source1 source2 dest shift Function...
ibustm[14]={Rformat, 5\'b01010, 5\'b01010, 5\'b00111, 5\'b00000, OR};
Ref_Aselect[14] = 32\'b00000000000000000000010000000000; //input14
Ref_Bselect[14] = 32\'b00000000000000000000010000000000; //input14
Ref_Dselect[14] = 32\'b00000000000001000000000000000000; //input12
Ref_Imm[14] =1\'b0; //input13
Ref_Cin[14] =1\'b0; //input13
Ref_S[14] = SADD; //input13
// ---------
// 15. XORI R12, R21, #00F0
// ---------
// opcode source1 dest Immediate...
ibustm[15]={XORI, 5\'b10101, 5\'b01100, 16\'h00F0};
Ref_Aselect[15] = 32\'b00000000001000000000000000000000;//input15
Ref_Bselect[15] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;//input15
Ref_Dselect[15] = 32\'b00000001000000000000000000000000;//input13
Ref_Imm[15] =1\'b0; //input14
Ref_Cin[15] =1\'b0; //input14
Ref_S[15] = SOR; //input14
// ---------
// 16. SUBI R26, R31, #0111
// ---------
// opcode source1 dest Immediate...
ibustm[16]={SUBI, 5\'b11111, 5\'b11010, 16\'h0111};
Ref_Aselect[16] = 32\'b10000000000000000000000000000000; //input16
Ref_Bselect[16] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input16
Ref_Dselect[16] = 32\'b00000000000000000000000010000000; //input14
Ref_Imm[16] =1\'b1; //input15
Ref_Cin[16] =1\'b0; //input15
Ref_S[16] = SXOR; //input15
// ---------
// 17. ADD R17, R3, R21
// ---------
// opcode source1 source2 dest shift Function...
ibustm[17]={Rformat, 5\'b00011, 5\'b10101, 5\'b10001, 5\'b00000, ADD};
Ref_Aselect[17] = 32\'b00000000000000000000000000001000;//input17
Ref_Bselect[17] = 32\'b00000000001000000000000000000000;//input17
Ref_Dselect[17] = 32\'b00000000000000000001000000000000;//input15
Ref_Imm[17] =1\'b1; //input16
Ref_Cin[17] =1\'b1; //input16
Ref_S[17] = SSUB; //input16
// ---------
// 18. XOR R15, R7, R21
// ---------
// opcode source1 source2 dest shift Function...
ibustm[18]={Rformat, 5\'b00111, 5\'b10101, 5\'b01111, 5\'b00000, XOR};
Ref_Aselect[18] = 32\'b00000000000000000000000010000000; //input18
Ref_Bselect[18] = 32\'b00000000001000000000000000000000; //input18
Ref_Dselect[18] = 32\'b00000100000000000000000000000000; //input16
Ref_Imm[18] =1\'b0; //input17
Ref_Cin[18] =1\'b0; //input17
Ref_S[18] = SADD; //input17
// ---------
// 19. ADDI R13, R13, #FFFF
// ---------
// opcode source1 dest Immediate...
ibustm[19]={ADDI, 5\'b01101, 5\'b01101, 16\'hFFFF};
Ref_Aselect[19] = 32\'b00000000000000000010000000000000; //input19
Ref_Bselect[19] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input19
Ref_Dselect[19] = 32\'b00000000000000100000000000000000; //input17
Ref_Imm[19] =1\'b0; //input18
Ref_Cin[19] =1\'b0; //input18
Ref_S[19] = SXOR; //input18
// ---------
// 20. ADDI R23, R1, #AFC0
// ---------
// opcode source1 dest Immediate...
ibustm[20]={ADDI, 5\'b00001, 5\'b10111, 16\'hAFC0};
Ref_Aselect[20] = 32\'b00000000000000000000000000000010;//input20
Ref_Bselect[20] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;//input20
Ref_Dselect[20] = 32\'b00000000000000001000000000000000; //input18
Ref_Imm[20] =1\'b1; //input19
Ref_Cin[20] =1\'b0; //input19
Ref_S[20] = SADD; //input19
// ---------
// 21. SUB R20, R1, R1
// ---------
// opcode source1 source2 dest shift Function...
ibustm[21]={Rformat, 5\'b00001, 5\'b00001, 5\'b10100, 5\'b00000, SUB};
Ref_Aselect[21] = 32\'b00000000000000000000000000000010; //input21
Ref_Bselect[21] = 32\'b00000000000000000000000000000010; //input21
Ref_Dselect[21] = 32\'b00000000000000000010000000000000; //input19
Ref_Imm[21] =1\'b1; //input20
Ref_Cin[21] =1\'b0; //input20
Ref_S[21] = SADD; //input20
// ---------
// 22. XORI R19, R0, #8CCB
// ---------
// opcode source1 dest Immediate...
ibustm[22]={XORI, 5\'b00000, 5\'b10011, 16\'h8CCB};
Ref_Aselect[22] = 32\'b00000000000000000000000000000001;//input22
Ref_Bselect[22] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;//input22
Ref_Dselect[22] = 32\'b00000000100000000000000000000000;//input20
Ref_Imm[22] =1\'b0; //input21
Ref_Cin[22] =1\'b1; //input21
Ref_S[22] = SSUB; //input21
// --------
// 23. ORI R9, R20, #F98B
// --------
// opcode source1 dest Immediate...
ibustm[23]={ORI, 5\'b10100, 5\'b01001, 16\'hF98B};
Ref_Aselect[23] = 32\'b00000000000100000000000000000000; //input23
Ref_Bselect[23] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input23
Ref_Dselect[23] = 32\'b00000000000100000000000000000000; //input21
Ref_Imm[23] =1\'b1; //input22
Ref_Cin[23] =1\'b0; //input22
Ref_S[23] = SXOR; //input22
// --------
// 24. XOR R2, R13, R19
// --------
// opcode source1 source2 dest shift Function...
ibustm[24]={Rformat, 5\'b01101, 5\'b10011, 5\'b00010, 5\'b00000, XOR};
Ref_Aselect[24] = 32\'b00000000000000000010000000000000;//input24
Ref_Bselect[24] = 32\'b00000000000010000000000000000000;//input24
Ref_Dselect[24] = 32\'b00000000000010000000000000000000;//input22
Ref_Imm[24] =1\'b1; //input23
Ref_Cin[24] =1\'b0; //input23
Ref_S[24] = SOR; //input23
// --------
// 25. SUBI R26, R9, #0030
// --------
// opcode source1 dest Immediate...
ibustm[25]={SUBI, 5\'b01001, 5\'b11010, 16\'h0030};
Ref_Aselect[25] = 32\'b00000000000000000000001000000000; //input25
Ref_Bselect[25] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input25
Ref_Dselect[25] = 32\'b00000000000000000000001000000000; //input23
Ref_Imm[25] =1\'b0; //input24
Ref_Cin[25] =1\'b0; //input24
Ref_S[25] = SXOR; //input24
// --------
// 26. XOR R25, R2, R9
// --------
// opcode source1 source2 dest shift Function...
ibustm[26]={Rformat, 5\'b00010, 5\'b01001, 5\'b11001, 5\'b00000, XOR};
Ref_Aselect[26] = 32\'b00000000000000000000000000000100;//input26
Ref_Bselect[26] = 32\'b00000000000000000000001000000000;//input26
Ref_Dselect[26] = 32\'b00000000000000000000000000000100;//input24
Ref_Imm[26] =1\'b1; //input25
Ref_Cin[26] =1\'b1; //input25
Ref_S[26] = SSUB; //input25
// --------
// 27. ORI R8, R20, #34FB
// --------
// opcode source1 dest Immediate...
ibustm[27]={ORI, 5\'b10100, 5\'b01000, 16\'h34FB};
Ref_Aselect[27] = 32\'b00000000000100000000000000000000;//input27
Ref_Bselect[27] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; //input27
Ref_Dselect[27] = 32\'b00000100000000000000000000000000; //input25
Ref_Imm[27] =1\'b0; //input26
Ref_Cin[27] =1\'b0; //input26
Ref_S[27] = SXOR; //input26
// --------
// 28. XORI R27, R13, #0B31
// --------
// opcode source1 dest Immediate...
ibustm[28]={XORI, 5\'b01101, 5\'b11011, 16\'h0B31};
Ref_Aselect[28] = 32\'b00000000000000000010000000000000;//input28
Ref_Bselect[28] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;//input28
Ref_Dselect[28] = 32\'b00000010000000000000000000000000;//input26
Ref_Imm[28] =1\'b1; //input27
Ref_Cin[28] =1\'b0; //input27
Ref_S[28] = SOR; //input27
// --------
// 29. ADD R14, R2, R19
// --------
// opcode source1 source2 dest shift Function...
ibustm[29]={Rformat, 5\'b00010, 5\'b10011, 5\'b01110, 5\'b00000, ADD};
Ref_Aselect[29] = 32\'b00000000000000000000000000000100;//input29
Ref_Bselect[29] = 32\'b00000000000010000000000000000000;//input29
Ref_Dselect[29] = 32\'b00000000000000000000000100000000;//input27
Ref_Imm[29] =1\'b1; //input28
Ref_Cin[29] =1\'b0; //input28
Ref_S[29] = SXOR; //input28
// --------
// 30. OR R4, R8, R8
// --------
// opcode source1 source2 dest shift Function...
ibustm[30]={Rformat, 5\'b01000, 5\'b01000, 5\'b00100, 5\'b00000, OR};
Ref_Aselect[30] = 32\'b00000000000000000000000100000000;//input30
Ref_Bselect[30] = 32\'b00000000000000000000000100000000;//input30
Ref_Dselect[30] = 32\'b00001000000000000000000000000000;//input28
Ref_Imm[30] =1\'b0; //input29
Ref_Cin[30] =1\'b0; //input29
Ref_S[30] = SADD; //input29
// --------
// 31. XORI R12, R21, #5555
// --------
// opcode source1 dest Immediate...
ibustm[31]={XORI, 5\'b10101, 5\'b01100, 16\'h5555};
Ref_Aselect[31] = 32\'b00000000001000000000000000000000;//input31
Ref_Bselect[31] = 32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;//input31
Ref_Dselect[31] = 32\'b00000000000000000100000000000000;//input29
Ref_Imm[31] =1\'b0; //input30
Ref_Cin[31] =1\'b0; //input30
Ref_S[31] = SOR; //input30
ntests = 180;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
clk=0;
$display("-------------------------------");
$display("Time=%t Instruction Number: 0 ",$realtime);
$display("-------------------------------");
ibus = ibustm[0];
#25;
for (k=1; k<= 31; k=k+1) begin
$display("-------------------------------");
$display("Time=%t Instruction Number: %d ",$realtime,k);
$display("-------------------------------");
clk=1;
#5
if (k>=1) begin
$display (" Testing Immediate, Cin and S for instruction %d", k-1);
$display (" Your Imm = %b", Imm);
$display (" Correct Imm = %b", Ref_Imm[k]);
if ( (Imm !== Ref_Imm[k]) && (Ref_Imm[k] !== 1\'bx) ) begin
error = error+1;
$display("-------ERROR. Mismatch Has Occured--------");
end
$display (" Your Cin = %b", Cin);
$display (" Correct Cin = %b", Ref_Cin[k]);
if ( (Cin !== Ref_Cin[k]) && (Ref_Cin[k] !== 1\'bx) ) begin
error = error+1;
$display("-------ERROR. Mismatch Has Occured--------");
end
$display (" Your S = %b", S);
$display (" Correct S = %b", Ref_S[k]);
if ( (S !== Ref_S[k]) && (Ref_S[k] !== 3\'bxxx) ) begin
error = error+1;
$display("-------ERROR. Mismatch Has Occured--------");
end
end
if (k>=2) begin
$display (" Testing Destination Registers for instruction %d", k-2);
$display (" Your Dselect = %b", Dselect);
$display (" Correct Dselect = %b", Ref_Dselect[k]);
if ( (Dselect !== Ref_Dselect[k]) && (Ref_Dselect[k] !== dontcare) ) begin
error = error+1;
$display("-------ERROR. Mismatch Has Occured--------");
end
end
#20\t
clk = 0;
$display ("-------------------------------");
$display (" Time=%t ",$realtime);
$display ("-------------------------------");
ibus = ibustm[k+1];
#5
$display (" Testing Source Registers for instruction %d", k);
$display (" Your Aselect = %b", Aselect);
$display (" Correct Aselect = %b", Ref_Aselect[k]);
if ( (Aselect !== Ref_Aselect[k]) && (Ref_Aselect[k]) ) begin
error = error+1;
$display("-------------ERROR. Mismatch Has Occured---------------");
end
$display (" Your Bselect = %b", Bselect);
$display (" Correct Bselect = %b", Ref_Bselect[k]);
if ( (Bselect !== Ref_Bselect[k]) && (Ref_Bselect[k] !== dontcare) ) begin
error = error+1;
$display("-------------ERROR. Mismatch Has Occured---------------");
end
#20
clk = 0;
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("-----------YOU DID IT :-) !!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule |
/************************
* Willard Wider
* 08-04-17
* ELEC3725
* cpu5.v
* building a 32 bit CPU
************************/
//cpu5 dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
module cpu5(ibus,clk,daddrbus,databus,reset,iaddrbus);
//just a clock
input clk;
//reset to clear the counter
input reset;
//instruction bus
output [31:0] iaddrbus;//from PC, to SIM_OUT
wire [31:0] iaddrbusWire1;//from mux, to PC
wire [31:0] iaddrbusWire2;//from PC, to mux4/iaddrbusWire4
wire [31:0] iaddrbusWire4;//from PC, to IF_ID
//SLT SLE control bits
//00 = nothing, 01 = SLT, 10 = SLE
reg [1:0] setControlBits;
wire [1:0] setControlBitsWire1;
wire [1:0] setControlBitsWire2;
//for SLT/SLE operations
wire ZBit;//high when rs(a) - rt(b) = 0, 1 otherwise
wire [31:0] potentialSLEBit;//the value to set to dbus if it is a SLE operation
wire [31:0] potentialSLTBit;
wire [31:0] actualSLBit;
//the cout for the alu
wire ALUCoutWire;
//BEQ and BNE congtrol bits
//00 = noting, 01 = BEQ, 10 = BNE
reg [1:0] branchControlBit;
wire [1:0] branchControlBitWire1;
wire [1:0] branchControlBitWire2;
wire [1:0] branchControlBitWire3;
//program counter wires to be piped into the IF_ID stage
wire [31:0] PCWire1;//form IF_ID, to branchCalcWire1
//the wire for the branch calculation, part 1 (immediate sign extended, bit shifted by 2 for *4)
wire [31:0] branchCalcWire1;//from immediate, to branchCalcwire2
//the wire for the branch calculation, part 2 (+4)
wire [31:0] branchCalcWire2;//from branchCalcWire1, to mux4
//the new bus things
output [31:0] daddrbus;//from EX_MEM, to SIM_OUT
inout [31:0] databus;//from SIM_IN/EX_MEM, to SIM_OUT/MEM_WB
//decoder tings
wire [5:0] opCode;//from IF_ID
wire [5:0] funktion;//from IF_ID
//ibus
input [31:0] ibus;//in for IF_ID
wire [31:0] ibusWire;//out for IF_ID
//Aselect
wire [31:0] AselectWire;//from rs, to regfile
wire [5:0] rs;//from ibusWire, to AselectWire
//Bselect
wire [31:0] BselectWire;//from rt, to regfile
wire [5:0] rt;//from ibsuWire, to BselectWire and mxu1
//imm select
reg immBit1;//from IF_ID(ibusWire), to mux1 and ID_EX
wire immBit2;//from ID_EX, to mux2
//load word save word flag
reg [1:0] lwSwFlag1;//from IF_ID, to ID_EX
wire [1:0] lwSwFlag2;//from ID_EX, to EX_MEM
wire [1:0] lwSwFlag3;//from EX_MEM, to MEM_WB
wire [1:0] lwSwFlag4;//from MEM_WB, to mux3
//Dselect
wire [31:0] DselectWire1;//from muxOut, to ID_EX
wire [5:0] rd;//from ID_EX, to mux1
wire [31:0] DselectWire2;//from ID_EX, to EX_MM
wire [31:0] DselectWire3;//from EX_MEM, to MEM_WB
wire [31:0] DselectWire3_5;//from MEM_WB, to mux3
wire [31:0] DselectWire4;//from mux3, to regfile
//abus
//output [31:0] abus;//from ID_EX, to SIM_OUT
wire [31:0] abusWire1;//from regOut, to ID_EX
wire [31:0] abusWire2;//from ID_EX, to ALU
//bbus
//output [31:0] bbus;//from mux2Out, to SIM_OUT
wire [31:0] bbusWire1;//from regOut, to ID_EX
wire [31:0] bbusWire2;//from ID_EX, to mux2/EX_MEM
wire [31:0] bbusWire3;//from EX_MEM, to memory logic
wire [31:0] bbusWire3_5;//from memory logic, to MEM_WB
wire [31:0] bbusWire4;//from MEM_WB, to mux3
//dbus
wire [31:0] dbusWire1;//from ALU, to dbusWire1_5(SLE_MUX_TEST)
wire [31:0] dbusWire1_5;//from SLE_MUX_TEST to EX_MEM
wire [31:0] dbusWire2;//from EM_MEM, to MEM_WB
wire [31:0] dbusWire3;//from MEM_WB, to mux3
//mux3
wire [31:0] mux3Out;//from dbusWire3/bbusWire4, to regfile
//mux2
wire [31:0] mux2Out;//from bbusWire2/immWire2, to ALU
//mux4 deciding wire
wire mux4Controller;//controls the pc address bus
//immediate
wire [31:0] immWire1;//from IF_ID, to ID_EX
wire [31:0] immWire2;//from ID_EX, to mux2
wire [31:0] branchWire;
//S
reg [2:0] SWire1;//from IF_ID, to ID_EX
wire [2:0] SWire2;//from ID_EX, to ALU
//Cin
reg CinWire1;//from IF_ID, to ID_EX
wire CinWire2;//form ID_EX, to ALU
//init
initial begin
immBit1 = 1\'bx;
CinWire1 = 1\'bx;
SWire1 = 3\'bxxx;
lwSwFlag1 = 2\'bxx;
branchControlBit = 2\'b0;
setControlBits = 2\'b00;
end
//latch for pipeline 0(PC)
//module pipeline_0_latch(clk, iaddrbusWire1, iaddrbusOut);
pipeline_0_latch PC(.clk(clk),.iaddrbusWire1(iaddrbusWire1),.iaddrbusOut(iaddrbusWire2),.reset(reset));
//assign the output
assign iaddrbus = mux4Controller? branchCalcWire2 : iaddrbusWire2;
//iaddrbusWire4 gets feed into the IF_ID stage
assign iaddrbusWire4 = iaddrbusWire2;
//feed the pc back into itself. may update iaddrbusWire2 from the IF_ID stage
assign iaddrbusWire1 = mux4Controller? branchCalcWire2 : iaddrbusWire2;
//PIPELINE_0_END
//latch for pipeline 1(IF_ID)
//module pipeline_1_latch(clk, ibus, ibusWire);
pipeline_1_latch IF_ID(.clk(clk),.ibus(ibus),.ibusWire(ibusWire),.PCIn(iaddrbusWire4),.PCOut(PCWire1));
//PIPELINE_1_START
//decode the input command
assign opCode = ibusWire[31:26];
assign rs = ibusWire[25:21];
assign rt = ibusWire[20:16];
assign rd = ibusWire[15:11];
assign funktion = ibusWire[5:0];
assign immWire1 = ibusWire[15]? {16\'b1111111111111111,ibusWire[15:0]} : {16\'b0000000000000000,ibusWire[15:0]};
assign branchWire = ibusWire[15]? {14\'b11111111111111, ibusWire[15:0], 2\'b00} : {14\'b00000000000000, ibusWire[15:0], 2\'b00};
//for the change in the opcode which is like always
always @(ibusWire) begin
//first mux value is to assume 0
immBit1 = 1;
CinWire1 = 0;
branchControlBit = 0;
setControlBits = 0;
//assume not doing anything with the load or save
lwSwFlag1 = 2\'b00;
//write the cases for the opcode (immediate)
case (opCode)
6\'b000011: begin
//addi
SWire1 = 3\'b010;
end
6\'b000010: begin
//subi
SWire1 = 3\'b011;
CinWire1 = 1;
end
6\'b000001: begin
//xori
SWire1 = 3\'b000;
end
6\'b001111: begin
//andi
SWire1 = 3\'b110;
end
6\'b001100: begin
//ori
SWire1 = 3\'b100;
end
6\'b011110: begin
//load word, but still addi
SWire1 = 3\'b010;
lwSwFlag1 = 2\'b01;
end
6\'b011111: begin
//store word, but still addi
SWire1 = 3\'b010;
lwSwFlag1 = 2\'b10;
end
6\'b110000: begin
//BEQ
SWire1 = 3\'b010;
//set control bit
branchControlBit = 2\'b01;
end
6\'b110001: begin
//BNE
SWire1 = 3\'b010;
//set control bit
branchControlBit = 2\'b10;
end
//if 00000
6\'b000000: begin
//write the mux value here
immBit1= 0;
//then write the cases for the funct
case (funktion)
6\'b000011: begin
//add
SWire1 = 3\'b010;
end
6\'b000010: begin
//sub
SWire1 = 3\'b011;
CinWire1 = 1;
end
6\'b000001: begin
//xor
SWire1 = 3\'b000;
end
6\'b000111: begin
//and
SWire1 = 3\'b110;
end
6\'b000100: begin
//or
SWire1 = 3\'b100;
end
6\'b110110: begin
//SLT
//00 = nothing, 01 = SLT, 10 = SLE
setControlBits = 2\'b01;
//set to subtraction
SWire1 = 3\'b011;
end
6\'b110111: begin
//SLE
//00 = nothing, 01 = SLT, 10 = SLE
setControlBits = 2\'b10;
//set to subtraction
SWire1 = 3\'b011;
end
endcase
end
endcase
end
//write the select lines
assign AselectWire = 1 << rs;
//only write to Bselect for real if it\'s actually goign to use Bselect
//i don\'t think this line matters but i feel like it\'s good pratice
//assign BselectWire = immBit1? 32\'hxxxxxxxx: 1 << rt;
assign BselectWire = 1 << rt;
//mux1
//Rd for R, imm = false
//Rt for I, imm = true
assign DselectWire1 = immBit1? 1<<rt : 1<<rd;
regfile Reggie3(.clk(clk),.Aselect(AselectWire),.Bselect(BselectWire),.Dselect(DselectWire4),.abus(abusWire1),.bbus(bbusWire1),.dbus(mux3Out));
//update the muxWire4 controll if the instruction is BEQ or BNE, and if it is actually equal
//mux4Controller = 1 if ((BEQ and abus == bbus) or (BNE and bbus != abus)), 0 otherwise
//00 = noting, 01 = BEQ, 10 = BNE
assign mux4Controller = ((!clk) && ((branchControlBit==2\'b01) && (abusWire1 == bbusWire1)) || ((branchControlBit==2\'b10) && (abusWire1!=bbusWire1)))? 1: 0;
//the branch calculation
assign branchCalcWire1 = immWire1 << 2;
assign branchCalcWire2 = branchWire + PCWire1;
//PIPELINE_1_END
//latch for pipeline 2(ID_EX)
pipeline_2_latch ED_EX(.clk(clk),.abusWire1(abusWire1),.bbusWire1(bbusWire1),.DselectWire1(DselectWire1),.immWire1(immWire1),.SWire1(SWire1),
.CinWire1(CinWire1),.immBit1(immBit1),.lwSwFlag1(lwSwFlag1),.abusWire2(abusWire2),.bbusWire2(bbusWire2),.immWire2(immWire2),.CinWire2(CinWire2),
.DselectWire2(DselectWire2),.immBit2(immBit2),.SWire2,.lwSwFlag2(lwSwFlag2),.setControlBits(setControlBits),.setControlBitsWire1(setControlBitsWire1),
.branchControlBit(branchControlBit),.branchControlBitWire1(branchControlBitWire1));
//PIPELINE_2_START
//mux2
//immWire for true, Bselet for false
assign mux2Out = immBit2? immWire2: bbusWire2;
//make the ALU
//module alu32 (d, Cout, V, a, b, Cin, S);
alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));
//wipe the dbus if it\'s an SLT or an SLE
//zero result flag
assign ZBit = (dbusWire1==0)? 1:0;
//potential values for if the instruction is for SLT or SLE
assign potentialSLTBit = (!ALUCoutWire && !ZBit)? 32\'h00000001:32\'h00000000;
assign potentialSLEBit = (!ALUCoutWire || ZBit)? 32\'h00000001:32\'h00000000;
//a determinate wire that uses SLT or SLE, assuming if not one, than the other
//(a wire later decides if that always "lateer" choosen one is actually used
//00 = nothing, 01 = SLT, 10 = SLE
assign actualSLBit = (setControlBitsWire1 == 2\'b01)? potentialSLTBit: potentialSLEBit;
//the wire that is used for the new dbusWire, adds a check for if the result needs to be the SLT or not
//SLE_MUX_TEST
assign dbusWire1_5 = (setControlBitsWire1 > 2\'b00)? actualSLBit:dbusWire1;
//PIPELINE_2_END
//latch for pipeline 3(EX_MEM)
pipeline_3_latch EX_MEME (.clk(clk),.dbusWire1(dbusWire1_5),.DselectWire2(DselectWire2),.bbusWire2(bbusWire2),.lwSwFlag2(lwSwFlag2),.dbusWire2(dbusWire2),
.DselectWire3(DselectWire3),.bbusWire3(bbusWire3),.lwSwFlag3(lwSwFlag3),.branchControlBitWire1(branchControlBitWire1),.branchControlBitWire2(branchControlBitWire2));
//PIPELINE_3_SRART
//assign output values
assign bbusWire3_5 = (lwSwFlag3==2\'b01)? databus: bbusWire3;
assign databus = (lwSwFlag3 == 2\'b10)? bbusWire3: 32\'hzzzzzzzz;
assign daddrbus = dbusWire2;
//PIPELINE_3_END
//latch for pipeline 4(MEM_WB)
pipeline_4_latch MEM_WB (.clk(clk),.dbusWire2(dbusWire2),.DselectWire3(DselectWire3),.bbusWire3(bbusWire3_5),.lwSwFlag3(lwSwFlag3),.dbusWire3(dbusWire3),.DselectWire4(DselectWire3_5),
.bbusWire4(bbusWire4),.lwSwFlag4(lwSwFlag4),.branchControlBitWire2(branchControlBitWire2),.branchControlBitWire3(branchControlBitWire3));
//PIPELINE_4_START
//the mux for the data writeBack
assign mux3Out = (lwSwFlag4 == 2\'b01)? bbusWire4:dbusWire3;
//disable the writeback if it\'s a store word OR if it\'s a beq branch
assign DselectWire4 = ((lwSwFlag4 == 2\'b10) ||(branchControlBitWire3 > 2\'b00))? 32\'h00000001: DselectWire3_5;
//PIPELINE_4_END
endmodule
//phase 0 pipeline latch (PC)
module pipeline_0_latch(clk, iaddrbusWire1, iaddrbusOut, reset);
input clk, reset;
input [31:0] iaddrbusWire1;
output [31:0] iaddrbusOut;
reg [31:0] iaddrbusOut;
reg startBit;
initial begin
startBit = 1;
end
always@(posedge clk) begin
//if reset is high, reset the counter
//else incriment
iaddrbusOut = (reset|startBit)? 0:iaddrbusWire1+4;
startBit = 0;
end
endmodule
//phase 1 pipeline latch(IF_ID)
module pipeline_1_latch(clk, ibus, ibusWire, PCIn, PCOut);
input [31:0] ibus, PCIn;
input clk;
output [31:0] ibusWire, PCOut;
reg [31:0] ibusWire, PCOut;
always @(posedge clk) begin
//EDIT: this is delayed branching, other instructions can be put in place
ibusWire = ibus;
PCOut = PCIn;
end
endmodule
//phase 2 pipeline latch(ID_EX)
module pipeline_2_latch(clk, abusWire1, bbusWire1, DselectWire1, immWire1, SWire1, CinWire1,immBit1,lwSwFlag1,
abusWire2,bbusWire2,immWire2,SWire2,CinWire2,DselectWire2,immBit2,lwSwFlag2,setControlBits,setControlBitsWire1,
branchControlBit,branchControlBitWire1);
input clk, CinWire1,immBit1;
input [31:0] abusWire1, bbusWire1, DselectWire1, immWire1;
input [2:0] SWire1;
input [1:0] lwSwFlag1;
input [1:0] setControlBits;
input [1:0] branchControlBit;
output CinWire2,immBit2;
output [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
output [2:0] SWire2;
output [1:0] lwSwFlag2;
output [1:0] setControlBitsWire1;
output [1:0] branchControlBitWire1;
reg CinWire2,immBit2;
reg [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
reg [2:0] SWire2;
reg [1:0] lwSwFlag2;
reg [1:0] setControlBitsWire1;
reg [1:0] branchControlBitWire1;
always @(posedge clk) begin
abusWire2 = abusWire1;
bbusWire2 = bbusWire1;
DselectWire2 = DselectWire1;
immWire2 = immWire1;
SWire2 = SWire1;
CinWire2 = CinWire1;
immBit2 = immBit1;
lwSwFlag2 = lwSwFlag1;
setControlBitsWire1 = setControlBits;
branchControlBitWire1 = branchControlBit;
end
endmodule
//phase 3 pipeliune latch(EX_MEM)
module pipeline_3_latch(clk, dbusWire1, DselectWire2, bbusWire2, lwSwFlag2, dbusWire2, DselectWire3,bbusWire3,lwSwFlag3,branchControlBitWire1,branchControlBitWire2);
input clk;
input [31:0] dbusWire1, DselectWire2, bbusWire2;
input [1:0] lwSwFlag2;
input [1:0] branchControlBitWire1;
output [31:0] dbusWire2, DselectWire3, bbusWire3;
output [1:0] lwSwFlag3;
output [1:0] branchControlBitWire2;
reg [31:0] dbusWire2, DselectWire3, bbusWire3;
reg [1:0] lwSwFlag3;
reg [1:0] branchControlBitWire2;
always @(posedge clk) begin
dbusWire2 = dbusWire1;
DselectWire3 = DselectWire2;
bbusWire3 = bbusWire2;
lwSwFlag3 = lwSwFlag2;
branchControlBitWire2 = branchControlBitWire1;
end
endmodule
//phase 4 pipeline latch(MEM_WB)
module pipeline_4_latch(clk, dbusWire2, DselectWire3, bbusWire3, lwSwFlag3, dbusWire3, DselectWire4,bbusWire4,lwSwFlag4,branchControlBitWire2,branchControlBitWire3);
input clk;
input [31:0] dbusWire2, DselectWire3, bbusWire3;
input [1:0] lwSwFlag3;
input [1:0] branchControlBitWire2;
output [31:0] dbusWire3, DselectWire4, bbusWire4;
output [1:0] lwSwFlag4;
output [1:0] branchControlBitWire3;
reg [31:0] dbusWire3, DselectWire4, bbusWire4;
reg [1:0] lwSwFlag4;
reg [1:0] branchControlBitWire3;
always @(posedge clk) begin
dbusWire3 = dbusWire2;
DselectWire4 = DselectWire3;
bbusWire4 = bbusWire3;
lwSwFlag4 = lwSwFlag3;
branchControlBitWire3 = branchControlBitWire2;
end
endmodule
module regfile(
input [31:0] Aselect,//select the register index to read from to store into abus
input [31:0] Bselect,//select the register index to read from to store into bbus
input [31:0] Dselect,//select the register to write to from dbus
input [31:0] dbus,//data in
output [31:0] abus,//data out
output [31:0] bbus,//data out
input clk
);
assign abus = Aselect[0] ? 32\'b0 : 32\'bz;
assign bbus = Bselect[0] ? 32\'b0 : 32\'bz;
DNegflipFlop myFlips[30:0](//32 wide register
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule
module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [31:0] dbus;
input Dselect;//the select write bit for this register
input Bselect;//the select read bit for this register
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
wire wireclk;
reg [31:0] data;
assign wireclk = clk & Dselect;
initial begin
data = 32\'h00000000;
end
always @(negedge clk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect? data : 32\'hzzzzzzzz;
assign bbus = Bselect? data : 32\'hzzzzzzzz;
endmodule
//Below this point is code from assignment 1//
//The declaration of the entire ALU itself.
module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;//the output bus
output Cout, V;//Cout is the bit for it it needs to carry over ?/ V is the overflow bit.
input [31:0] a, b;//the two input buses
input Cin;//the bit for marking if it is carrying over from a ?
input [2:0] S;//The select bus. It defines the operation to do with input busses a and b
wire [31:0] c, g, p;
wire gout, pout;
//The core ALU bus
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
//the top Look-Ahead-Carry module.
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
//the overflow module
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule
//The module to handle a single bit operation for the top ALU module
module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;//generate carry
p = a ^ bint;//proragate carry
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule
//The module to handle the overflow bit
module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule
//Look-Ahead Carry unit level 1. Used for the root (level 1) and first child leafs (level 2)
module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule
//Look-Ahead Carry unit level 2. Contains LACs for the root and level 1. Used in level 3
module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 3. Contains LACs for the root and level 2. Used in level 4
module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 4. Contains LACs for the root and level 3. Used in level 5
module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 1. Caontains LACs for the root and level 4. Used in the core alu32 module
module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
|
/************************
* Willard Wider
* 08-07-17
* ELEC3725
* ARMS.v
* building a 64 bit CPU
************************/
//ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
module ARMS(ibus,clk,daddrbus,databus,reset,iaddrbus);
//just a clock
input clk;
//reset to clear the counter
input reset;
//instruction bus
output [63:0] iaddrbus;//from PC, to SIM_OUT
wire [63:0] iaddrbusWire1;//from mux, to PC
wire [63:0] iaddrbusWire2;//from PC, to mux4/iaddrbusWire4
wire [63:0] iaddrbusWire4;//from PC, to IF_ID
//SLT SLE control bits
//00 = nothing, 01 = SLT, 10 = SLE
reg [1:0] setControlBits;
wire [1:0] setControlBitsWire1;
wire [1:0] setControlBitsWire2;
//for SLT/SLE operations
//LEG_UPDATE: rs->rn, rt->rm
wire ZBit;//high when rn(a) - rm(b) = 0, 1 otherwise
wire [63:0] potentialSLEBit;//the value to set to dbus if it is a SLE operation
wire [63:0] potentialSLTBit;
wire [63:0] actualSLBit;
//the cout for the alu
wire ALUCoutWire;
//LEG_UPDATE: add the overflow counter from the ALU
wire overflowWire;
//LEG_UPDATE: 7 ways to branch, to update the control bit
//000 = noting, 001 = B, 010 = B.EQ
//011 = B.NE, 100 = B.LT, 101 = B.GE
//110 = CBNZ, 111 = CBZ
reg [2:0] branchControlBit;
wire [2:0] branchControlBitWire1;
wire [2:0] branchControlBitWire2;
wire [2:0] branchControlBitWire3;
reg takeBranch;
wire takeBranchWire1;
wire takeCondBranchWire1;
//program counter wires to be piped into the IF_ID stage
wire [63:0] PCWire1;//form IF_ID, to branchCalcWire1
//the wire for the branch calculation, part 1 (immediate sign extended, bit shifted by 2 for *4)
wire [63:0] branchCalcWire1;//from immediate, to branchCalcwire2
//the wire for the branch calculation, part 2 (+4)
wire [63:0] branchCalcWire2;//from branchCalcWire1, to mux4
//the new buses to and from the ddr memory
output [63:0] daddrbus;//from EX_MEM, to SIM_OUT
inout [63:0] databus;//from SIM_IN/EX_MEM, to SIM_OUT/MEM_WB
//decoder tings
//LEG_UPDATE: opcode is 11 bits long now
wire [10:0] opCode;//from IF_ID
//LEG_UPDATE: funktion is no longer a thing, everything is in the opcode
//wire [5:0] funktion;//from IF_ID
//LEG_UPDATE: NOP\'s should be redirected to nothing register
reg NOP;
wire NOPWire1;
wire NOPWire2;
wire NOPWire3;
//ibus
input [31:0] ibus;//in for IF_ID
wire [31:0] ibusWire;//out for IF_ID
//Aselect
wire [31:0] AselectWire;//from rs, to regfile
wire [31:0] AselectWire1;
//LEG_UPDATE: rs->rn
wire [5:0] rn;//from ibusWire, to AselectWire
//Bselect
wire [31:0] BselectWire;//from rt, to BselectWire1
wire [31:0] BselectWire1;//from BselectWire, to regfile
wire [31:0] BselectWire2;
//LEG_UPDATE: rt->rm
wire [5:0] rm;//from ibsuWire, to BselectWire and mxu1
//LEG_UPDATE: add a bit for MOVZ select
//mov select
reg movBit1;
wire movBit2;
wire [5:0] moveImmShftAmt;
wire [5:0] moveImmShftAmtWire1;
//imm select
reg immBit1;//from IF_ID(ibusWire), to mux1 and ID_EX
wire immBit2;//from ID_EX, to mux2
//LEG_UPDATE: add the NZVC bit and it\'s potential values
//the NZVC bit
wire [3:0]NZVC;
wire potentialNBit;
wire potentialZBit;
wire potentialVBit;
wire potentialCBit;
//the control for setting NZVC
reg NZVCSetBit;
wire NZVCSetBitWire1;
//LEG_UPDATE: add a control bit set for LSL and LSR
reg [1:0] shiftBit1;
wire [1:0] shiftBit2;
//LEG_UPDATE: add the potential LSL and LSR bits for shifting
wire [63:0] potentialLSLResult;
wire [63:0] potentialLSRResult;
wire [63:0] actualLSResult;
//load word save word flag
reg [1:0] lwSwFlag1;//from IF_ID, to ID_EX
wire [1:0] lwSwFlag2;//from ID_EX, to EX_MEM
wire [1:0] lwSwFlag3;//from EX_MEM, to MEM_WB
wire [1:0] lwSwFlag4;//from MEM_WB, to mux3
//Dselect
wire [31:0] DselectWire1;//from muxOut, to ID_EX
//LEG_UPDATE: rd->rd (no change)
wire [5:0] rd;//from ID_EX, to mux1
wire [31:0] DselectWire2;//from ID_EX, to EX_MM
wire [31:0] DselectWire3;//from EX_MEM, to MEM_WB
wire [31:0] DselectWire3_5;//from MEM_WB, to mux3
wire [31:0] DselectWire4;//from mux3, to regfile
//LEG_UPDATE: new rt is also rd
//abus
//output [63:0] abus;//from ID_EX, to SIM_OUT
wire [63:0] abusWire1;//from regOut, to ID_EX
wire [63:0] abusWire2;//from ID_EX, to ALU
//bbus
//output [63:0] bbus;//from mux2Out, to SIM_OUT
wire [63:0] bbusWire1;//from regOut, to ID_EX
wire [63:0] bbusWire2;//from ID_EX, to mux2/EX_MEM
wire [63:0] bbusWire3;//from EX_MEM, to memory logic
wire [63:0] bbusWire3_5;//from memory logic, to MEM_WB
wire [63:0] bbusWire4;//from MEM_WB, to mux3
//dbus
wire [63:0] dbusWire1;//from ALU, to dbusWire1_5(SLE_MUX_TEST)
wire [63:0] dbusWire1_5;//from SLE_MUX_TEST to EX_MEM
wire [63:0] dbusWire1_6;
wire [63:0] dbusWire2;//from EM_MEM, to MEM_WB
wire [63:0] dbusWire3;//from MEM_WB, to mux3
//mux3
wire [63:0] mux3Out;//from dbusWire3/bbusWire4, to regfile
//mux2
wire [63:0] mux2Out;//from bbusWire2/immWire2, to mux5
//LEG_UPDATE: mux5
wire [63:0] mux5;//from mux2Out/DTAddrWire2, to ALU (as b)
wire [63:0] mux6;
//mux4 deciding wire
wire mux4Controller;//controls the pc address bus
//LEG_UPDATE: remove sign extended IMM wire, it\'s not a thing
//immediate
//wire [63:0] immWire1;//from IF_ID, to ID_EX
//wire [63:0] immWire2;//from ID_EX, to mux2
//and add the new parsed wires
wire [63:0] ALUImmWire1;
wire [63:0] ALUImmWire2;
wire [63:0] BranchAddrWire1;
wire [63:0] CondBranchAddrType1Wire1;//for b.cond
wire [63:0] CondBranchAddrType2Wire1;//for CBZ/CBNZ
wire [63:0] MOVImmWire1;
wire [63:0] MOVImmWire2;
wire [5:0] shamt;
wire [5:0] shamtWire1;
wire [63:0] DTAddrWire1;
wire [63:0] DTAddrWire2;
wire [63:0] DTAddrWire3;
wire [63:0] DTAddrWire4;
//S
reg [2:0] SWire1;//from IF_ID, to ID_EX
wire [2:0] SWire2;//from ID_EX, to ALU
//Cin
reg CinWire1;//from IF_ID, to ID_EX
wire CinWire2;//form ID_EX, to ALU
//init
initial begin
immBit1 = 1\'bx;
movBit1 = 1\'bx;
NZVCSetBit = 1\'bx;
CinWire1 = 1\'bx;
SWire1 = 3\'bxxx;
lwSwFlag1 = 2\'bxx;
branchControlBit = 3\'b0;
setControlBits = 2\'b00;
shiftBit1 = 2\'bxx;
takeBranch = 1\'b0;
NOP = 1\'bx;
end
//latch for pipeline 0(PC)
//module pipeline_0_latch(clk, iaddrbusWire1, iaddrbusOut);
pipeline_0_latch PC(.clk(clk),.iaddrbusWire1(iaddrbusWire1),.iaddrbusOut(iaddrbusWire2),.reset(reset));
//iaddrbusWire4 gets feed into the IF_ID stage
assign iaddrbusWire4 = iaddrbusWire2;
//feed the pc back into itself. may update iaddrbusWire2 from the IF_ID stage
assign iaddrbusWire1 = mux4Controller? branchCalcWire2 : iaddrbusWire2;
//assign the output
assign iaddrbus = iaddrbusWire1;
//PIPELINE_0_END
//latch for pipeline 1(IF_ID)
//module pipeline_1_latch(clk, ibus, ibusWire);
pipeline_1_latch IF_ID(.clk(clk),.ibus(ibus),.ibusWire(ibusWire),.PCIn(iaddrbusWire4),.PCOut(PCWire1));
//PIPELINE_1_START
//decode the input command
//LEG_UPDATE: updated to new leg instruction sets
assign opCode = ibusWire[31:21];
assign rn = ibusWire[9:5];//old rs
assign rm = ibusWire[20:16];//old rt
assign rd = ibusWire[4:0];
assign shamt = ibusWire[15:10];
assign DTAddrWire1 = ibusWire[20]? {55\'b1,ibusWire[20:12]} : {55\'b0,ibusWire[20:12]};
assign moveImmShftAmt = ibusWire[22:21] << 4;
//LEG_UPDATE: added the following
assign ALUImmWire1 = {52\'b0, ibusWire[21:10]};
assign BranchAddrWire1 = ibusWire[25]? {36\'b1111,ibusWire[25:0],2\'b00} : {36\'b0000,ibusWire[25:0],2\'b00};
assign CondBranchAddrType1Wire1 = ibusWire[23]? {43\'b11111111111,ibusWire[23:5],2\'b00} : {43\'b00000000000,ibusWire[23:5],2\'b00};//b.cond
assign MOVImmWire1= {48\'b0, ibusWire[20:5]};
//LEG_UPDATE: remove the following
//assign immWire1 = ibusWire[15]? {16\'b1111111111111111,ibusWire[15:0]} : {16\'b0000000000000000,ibusWire[15:0]};
//for the change in the opcode which is like always
always @(ibusWire) begin
immBit1 = 0;
movBit1 = 0;
CinWire1 = 0;
branchControlBit = 3\'b000;
setControlBits = 0;
NZVCSetBit = 0;
//assume not doing anything with the load or save
lwSwFlag1 = 2\'b00;
shiftBit1 = 2\'b00;
NOP = 1\'b0;
//write the cases for the opcode (immediate)
//LEG_UPDATE: updated opcodes and branch condition codes
//000 = noting, 001 = B, 010 = B.EQ
//011 = B.NE, 100 = B.LT, 101 = B.GE
//110 = CBNZ, 111 = CBZ
casez (opCode)
11\'b10001011000: begin
//add
SWire1 = 3\'b010;//add
end
11\'b1001000100?: begin
//addi
SWire1 = 3\'b010;
immBit1 = 1;
end
11\'b1011000100?: begin
//addis
SWire1 = 3\'b010;
immBit1 = 1;
NZVCSetBit = 1;
end
11\'b10101011000: begin
//adds
SWire1 = 3\'b010;
NZVCSetBit = 1;
end
11\'b10001010000: begin
//and
SWire1 = 3\'b110;//and
end
11\'b1001001000?: begin
//andi
SWire1 = 3\'b110;
immBit1 = 1;
end
11\'b1111001000?: begin
//andis
SWire1 = 3\'b110;
immBit1 = 1;
NZVCSetBit = 1;
end
11\'b11101010000: begin
//ands
SWire1 = 3\'b110;
NZVCSetBit = 1;
end
11\'b10110101???: begin
//CBNZ
//add i guess
SWire1 = 3\'b010;
branchControlBit = 3\'b110;
//takeBranch = 1;
end
11\'b10110100???: begin
//CBZ
//add i guess
SWire1 = 3\'b010;
branchControlBit = 3\'b111;
//takeBranch = 1;
end
11\'b11001010000: begin
//EOR (xor)
SWire1 = 3\'b000;
end
11\'b1101001000?: begin
//EORI(xori)
SWire1 = 3\'b000;
immBit1 = 1;
end
11\'b11111000010: begin
//LDUR
//command: rt value = from memory address, of rn value added with DTAddr
//load word, but still addi
SWire1 = 3\'b010;
lwSwFlag1 = 2\'b01;
end
11\'b11010011011: begin
//LSL
//uses shamt wire and abus to set for dbus
//overwide bbus to be r31 and swire to be add
//therefore it does nothing and we\'re not jumping around the pipeline
shiftBit1 = 2\'b01;
SWire1 = 3\'b010;
end
11\'b11010011010: begin
//LSR
//see above notes
shiftBit1 = 2\'b10;
SWire1 = 3\'b010;
end
11\'b110100101??: begin
//MOVZ
movBit1 = 1;
SWire1 = 3\'b100;
end
11\'b10101010000: begin
//ORR(or)
SWire1 = 3\'b100;
end
11\'b1011001000?: begin
//ORRI(ori)
SWire1 = 3\'b100;
immBit1 = 1;
end
11\'b11111000000: begin
//STUR
//command: memory of address, rn value added with DTAddr = rt value
//store word, but still addi
SWire1 = 3\'b010;
lwSwFlag1 = 2\'b10;
end
11\'b11001011000: begin
//sub
SWire1 = 3\'b011;
CinWire1 = 1;
end
11\'b1101000100?: begin
//subi
SWire1 = 3\'b011;
CinWire1 = 1;
immBit1 = 1;
end
11\'b1111000100?: begin
//subis
SWire1 = 3\'b011;
CinWire1 = 1;
immBit1 = 1;
NZVCSetBit = 1;
end
11\'b11101011000: begin
//subs
SWire1 = 3\'b011;
CinWire1 = 1;
NZVCSetBit = 1;
end
//000 = noting, 001 = B, 010 = B.EQ
//011 = B.NE, 100 = B.LT, 101 = B.GE
//110 = CBNZ, 111 = CBZ
11\'b000101?????: begin
//B
SWire1 = 3\'b010;
//set control bit
branchControlBit = 3\'b001;
end
11\'b01010101???: begin
//B.EQ
SWire1 = 3\'b010;
//set control bit
branchControlBit = 3\'b010;
//takeBranch = (NZVC[2] == 1\'b1)? 1:0;
end
11\'b01010110???: begin
//B.NE
SWire1 = 3\'b010;
//set control bit
branchControlBit = 3\'b011;
//takeBranch = (NZVC[2] == 1\'b0)? 1:0;
end
11\'b01010111???: begin
//B.LT(signed)
SWire1 = 3\'b010;
//set control bit
branchControlBit = 3\'b100;
//takeBranch = (NZVC[3] != NZVC[1])? 1:0;
end
11\'b01011000???: begin
//B.GE(signed)
SWire1 = 3\'b010;
//set control bit
branchControlBit = 3\'b101;
//takeBranch = (NZVC[3] == NZVC[1])? 1:0;
end
11\'b00000000000: begin
//NOP
SWire1 = 3\'b010;
//set control bit
NOP = 1\'b1;
end
//TODO: figure out if these are ever used
/*11\'b: begin
//SLT
//00 = nothing, 01 = SLT, 10 = SLE
setControlBits = 2\'b01;
//set to subtraction
SWire1 = 3\'b011;
end
11\'b: begin
//SLE
//00 = nothing, 01 = SLT, 10 = SLE
setControlBits = 2\'b10;
//set to subtraction
SWire1 = 3\'b011;
end*/
endcase
end
always@(negedge clk) begin
takeBranch = 1\'b0;
//LEG_UPDATE: updated opcodes and branch condition codes
//000 = noting, 001 = B, 010 = B.EQ
//011 = B.NE, 100 = B.LT, 101 = B.GE
//110 = CBNZ, 111 = CBZ
case (branchControlBit)
3\'b000: begin//nothing
takeBranch = 0;
end
3\'b001: begin//B
takeBranch = 1;
end
3\'b010: begin//B.EQ
takeBranch = (NZVC[2] == 1\'b1)? 1:0;
end
3\'b011: begin//B.NE
takeBranch = (NZVC[2] == 1\'b0)? 1:0;
end
3\'b100: begin//B.LT
takeBranch = (NZVC[3] != NZVC[1])? 1:0;
end
3\'b101: begin//B.GE
takeBranch = (NZVC[3] == NZVC[1])? 1:0;
end
3\'b110: begin//CBNZ
takeBranch = (abusWire1 != 0)? 1:0;
end
3\'b111: begin//CBZ
takeBranch = (abusWire1 == 0)? 1:0;
end
endcase
end
//write the select lines
assign AselectWire = ((branchControlBit == 3\'b110) || (branchControlBit == 3\'b111))? 1<<rd :1 << rn;
//LEG_UPDATE: need AsSelectWire for the move command
assign AselectWire1 = (movBit1)? 32\'h80000000 : AselectWire;
//only write to Bselect for real if it\'s actually goign to use Bselect
//i don\'t think this line matters but i feel like it\'s good pratice
//assign BselectWire = immBit1? 32\'hxxxxxxxx: 1 << rt;
assign BselectWire = 1 << rm;
//LEG_UPDATE: set BselectWire to R31(0) if it\'s a LSL/LSR command
assign BselectWire1 = ((shiftBit1 > 2\'b00) || (movBit1))? 32\'h80000000:BselectWire;
//LEG_UPDATE: BselectWire may need to get data from Bbus in regfile if it\'s a store command
assign BselectWire2 = (lwSwFlag1 == 2\'b10)? 1<<rd:BselectWire1;
//LEG_UPDATE: rt->rm
//LEG_UPDATE: dbus always holds the result for the alu output now
//mux1
//Rd for R, imm = false
//Rt for I, imm = true
//assign DselectWire1 = immBit1? 1<<rm : 1<<rd;
assign DselectWire1 = 1<<rd;
regfile Reggie3(.clk(clk),.Aselect(AselectWire1),.Bselect(BselectWire2),.Dselect(DselectWire4),.abus(abusWire1),.bbus(bbusWire1),.dbus(mux3Out));
//update the muxWire4 controll if the instruction is BEQ or BNE, and if it is actually equal
//mux4Controller = 1 if ((BEQ and abus == bbus) or (BNE and bbus != abus)), 0 otherwise
//00 = noting, 01 = BEQ, 10 = BNE
//CBNZ = 110, CBZ = 111
//assign mux4Controller = ((!clk) && ((branchControlBit==2\'b01) && (abusWire1 == bbusWire1)) || ((branchControlBit==2\'b10) && (abusWire1!=bbusWire1)))? 1: 0;
//assign takeCondBranchWire1 = ((!clk) && ((branchControlBit==3\'b110) && (abusWire1 != 0)) || ((branchControlBit==3\'b111) && (abusWire1 == 0)))? 1:0;
//assign takeBranchWire1 = takeCondBranchWire1|takeBranch;
assign takeBranchWire1 = takeBranch;
assign mux4Controller = ((!clk) && (branchControlBit > 3\'b000) && (takeBranchWire1))? 1 : 0;
//LEG_UPDATE: TODO: branch calculation is done in one step from above
//the branch calculation
assign branchCalcWire1 = (branchControlBit == 3\'b001)? BranchAddrWire1:CondBranchAddrType1Wire1;
assign branchCalcWire2 = branchCalcWire1 + PCWire1 - 4;
//PIPELINE_1_END
//latch for pipeline 2(ID_EX)
pipeline_2_latch ED_EX(.clk(clk),.abusWire1(abusWire1),.bbusWire1(bbusWire1),.DselectWire1(DselectWire1),.ALUImmWire1(ALUImmWire1),.SWire1(SWire1),
.CinWire1(CinWire1),.immBit1(immBit1),.lwSwFlag1(lwSwFlag1),.abusWire2(abusWire2),.bbusWire2(bbusWire2),.ALUImmWire2(ALUImmWire2),.CinWire2(CinWire2),
.DselectWire2(DselectWire2),.immBit2(immBit2),.SWire2,.lwSwFlag2(lwSwFlag2),.setControlBits(setControlBits),.setControlBitsWire1(setControlBitsWire1),
.branchControlBit(branchControlBit),.branchControlBitWire1(branchControlBitWire1),.NZVCSetBit(NZVCSetBit),.NZVCSetBitWire1(NZVCSetBitWire1),
.shiftBit1(shiftBit1),.shiftBit2(shiftBit2),.shamt(shamt),.shamtWire1(shamtWire1),.DTAddrWire1(DTAddrWire1),.DTAddrWire2(DTAddrWire2),
.MOVImmWire1(MOVImmWire1),.MOVImmWire2(MOVImmWire2),.movBit1(movBit1),.movBit2(movBit2),.moveImmShftAmt(moveImmShftAmt),
.moveImmShftAmtWire1(moveImmShftAmtWire1),.NOP(NOP),.NOPWire1(NOPWire1));
//PIPELINE_2_START
//mux2
//ALUImmWire2 for true, Bselet for false
assign mux2Out = immBit2? ALUImmWire2: bbusWire2;
//LEG_UPDATE: add mux5 for selecting the DTAddrWire
assign mux5 = (lwSwFlag2 > 2\'b00)? DTAddrWire2:mux2Out;
assign mux6 = (movBit2)? MOVImmWire2:mux5;
//make the ALU
//module alu64 (d, Cout, V, a, b, Cin, S);
alu64 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux6),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire),.V(overflowWire));
//wipe the dbus if it\'s an SLT or an SLE
//zero result flag
assign ZBit = (dbusWire1==0)? 1:0;
//potential values for if the instruction is for SLT or SLE
assign potentialSLTBit = (!ALUCoutWire && !ZBit)? 64\'h0000000000000001:64\'h0000000000000000;
assign potentialSLEBit = (!ALUCoutWire || ZBit)? 64\'h0000000000000001:64\'h0000000000000000;
//a determinate wire that uses SLT or SLE, assuming if not one, than the other
//(a wire later decides if that always "lateer" choosen one is actually used
//00 = nothing, 01 = SLT, 10 = SLE
assign actualSLBit = (setControlBitsWire1 == 2\'b01)? potentialSLTBit: potentialSLEBit;
//the wire that is used for the new dbusWire, adds a check for if the result needs to be the SLT or not
//SLE_MUX_TEST
//LEG_UPDATE: hook into the SLE wire for the LSL-LSR commands
//assign dbusWire1_5 = (setControlBitsWire1 > 2\'b00)? actualSLBit:dbusWire1;
assign potentialLSLResult = dbusWire1 << shamtWire1;
assign potentialLSRResult = dbusWire1 >> shamtWire1;
//assumes LSR if not LSL. won\'t apply it to dbus unless it\'s actually a shift command
//2\'b01 = LSL, 2\'b10 = LSR
assign actualLSResult = (shiftBit2 == 2\'b10)? potentialLSRResult:potentialLSLResult;
assign dbusWire1_5 = (shiftBit2 > 2\'b00)? actualLSResult:dbusWire1;
//LEG_UPDATE: apply the mov command to dbus
assign dbusWire1_6 = (movBit2)? {dbusWire1_5 << moveImmShftAmtWire1}: dbusWire1_5;
//LEG_UPDATE: if the NZVCSetBit is set, then set the NZVC values with the potential values
assign potentialNBit = (dbusWire1[63] == 1\'b1)? 1\'b1:1\'b0;
assign potentialZBit = (ZBit)? 1\'b1:1\'b0;
assign potentialVBit = (overflowWire)? 1\'b1:1\'b0;
assign potentialCBit = (ALUCoutWire)? 1\'b1:1\'b0;
assign NZVC[3] = (NZVCSetBitWire1)? potentialNBit:1\'bz;//N (negative)
assign NZVC[2] = (NZVCSetBitWire1)? potentialZBit:1\'bz;//Z (zero)
assign NZVC[1] = (NZVCSetBitWire1)? potentialVBit:1\'bz;//V (overflow, signed)
assign NZVC[0] = (NZVCSetBitWire1)? potentialCBit:1\'bz;//C (carry)
//PIPELINE_2_END
//latch for pipeline 3(EX_MEM)
pipeline_3_latch EX_MEME (.clk(clk),.dbusWire1(dbusWire1_6),.DselectWire2(DselectWire2),.bbusWire2(bbusWire2),.lwSwFlag2(lwSwFlag2),.dbusWire2(dbusWire2),
.DselectWire3(DselectWire3),.bbusWire3(bbusWire3),.lwSwFlag3(lwSwFlag3),.branchControlBitWire1(branchControlBitWire1),.branchControlBitWire2(branchControlBitWire2),
.NOPWire1(NOPWire1),.NOPWire2(NOPWire2));
//PIPELINE_3_SRART
//assign output values
//LEG_UPDATE: if store, bbusWire3 has the data to be written
//if load,
assign bbusWire3_5 = (lwSwFlag3==2\'b01)? databus: bbusWire3;//2\'b01 = load
assign databus = (lwSwFlag3 == 2\'b10)? bbusWire3: 64\'hzzzzzzzz;//2\'b10 = store
assign daddrbus = dbusWire2;
//PIPELINE_3_END
//latch for pipeline 4(MEM_WB)
pipeline_4_latch MEM_WB (.clk(clk),.dbusWire2(dbusWire2),.DselectWire3(DselectWire3),.bbusWire3(bbusWire3_5),.lwSwFlag3(lwSwFlag3),.dbusWire3(dbusWire3),
.DselectWire4(DselectWire3_5),.bbusWire4(bbusWire4),.lwSwFlag4(lwSwFlag4),.branchControlBitWire2(branchControlBitWire2),
.branchControlBitWire3(branchControlBitWire3),.NOPWire2(NOPWire2),.NOPWire3(NOPWire3));
//PIPELINE_4_START
//the mux for the data writeBack
assign mux3Out = (lwSwFlag4 == 2\'b01)? bbusWire4:dbusWire3;//2\'b01 = load
//disable the writeback if it\'s a store word OR if it\'s a branch OR if it\'s a NOP
//LEG_UPDATE: the address now is R31, 13\'h80000000
assign DselectWire4 = ((lwSwFlag4 == 2\'b10) ||(branchControlBitWire3 > 3\'b000) || (NOPWire3 == 1\'b1))? 32\'h80000000: DselectWire3_5;
//PIPELINE_4_END
endmodule
//phase 0 pipeline latch (PC)
module pipeline_0_latch(clk, iaddrbusWire1, iaddrbusOut, reset);
input clk, reset;
input [63:0] iaddrbusWire1;
output [63:0] iaddrbusOut;
reg [63:0] iaddrbusOut;
reg startBit;
initial begin
startBit = 1;
end
always@(posedge clk) begin
//if reset is high, reset the counter
//else incriment
iaddrbusOut = (reset|startBit)? 0:iaddrbusWire1+4;
startBit = 0;
end
endmodule
//phase 1 pipeline latch(IF_ID)
module pipeline_1_latch(clk, ibus, ibusWire, PCIn, PCOut);
input [31:0] ibus;
input [63:0] PCIn;
input clk;
output [31:0] ibusWire;
output [63:0] PCOut;
reg [31:0] ibusWire;
reg [63:0] PCOut;
always @(posedge clk) begin
//EDIT: this is delayed branching, other instructions can be put in place\\
//what did i mean by that? ^^
ibusWire = ibus;
PCOut = PCIn;
end
endmodule
//phase 2 pipeline latch(ID_EX)
module pipeline_2_latch(clk, abusWire1, bbusWire1, DselectWire1, ALUImmWire1, SWire1, CinWire1,immBit1,lwSwFlag1,
abusWire2,bbusWire2,ALUImmWire2,SWire2,CinWire2,DselectWire2,immBit2,lwSwFlag2,setControlBits,setControlBitsWire1,
branchControlBit,branchControlBitWire1,NZVCSetBit,NZVCSetBitWire1,shiftBit1,shiftBit2,shamt,shamtWire1,DTAddrWire1,
DTAddrWire2,MOVImmWire1,MOVImmWire2,movBit1,movBit2,moveImmShftAmt,moveImmShftAmtWire1,NOP,NOPWire1);
input clk, CinWire1,immBit1,NOP;
input [63:0] abusWire1, bbusWire1, ALUImmWire1,DTAddrWire1,MOVImmWire1;
input [31:0] DselectWire1;
input [2:0] SWire1;
input [1:0] lwSwFlag1;
input [1:0] setControlBits;
input [2:0] branchControlBit;
input NZVCSetBit;
input [1:0] shiftBit1;
input [5:0] shamt,moveImmShftAmt;
input movBit1;
output CinWire2,immBit2,NOPWire1;
output [63:0] abusWire2, bbusWire2, ALUImmWire2,DTAddrWire2,MOVImmWire2;
output [31:0] DselectWire2;
output [2:0] SWire2;
output [1:0] lwSwFlag2;
output [1:0] setControlBitsWire1;
output [2:0] branchControlBitWire1;
output NZVCSetBitWire1;
output [1:0] shiftBit2;
output [5:0] shamtWire1,moveImmShftAmtWire1;
output movBit2;
reg CinWire2,immBit2,NOPWire1;
reg [63:0] abusWire2, bbusWire2, ALUImmWire2,DTAddrWire2,MOVImmWire2;
reg [31:0] DselectWire2;
reg [2:0] SWire2;
reg [1:0] lwSwFlag2;
reg [1:0] setControlBitsWire1;
reg [2:0] branchControlBitWire1;
reg NZVCSetBitWire1;
reg [1:0] shiftBit2;
reg [5:0] shamtWire1,moveImmShftAmtWire1;
reg movBit2;
always @(posedge clk) begin
abusWire2 = abusWire1;
bbusWire2 = bbusWire1;
DselectWire2 = DselectWire1;
ALUImmWire2 = ALUImmWire1;
SWire2 = SWire1;
CinWire2 = CinWire1;
immBit2 = immBit1;
lwSwFlag2 = lwSwFlag1;
setControlBitsWire1 = setControlBits;
branchControlBitWire1 = branchControlBit;
NZVCSetBitWire1 = NZVCSetBit;
shiftBit2 = shiftBit1;
shamtWire1 = shamt;
DTAddrWire2 = DTAddrWire1;
MOVImmWire2 = MOVImmWire1;
movBit2 = movBit1;
moveImmShftAmtWire1 = moveImmShftAmt;
NOPWire1 = NOP;
end
endmodule
//phase 3 pipeliune latch(EX_MEM)
module pipeline_3_latch(clk, dbusWire1, DselectWire2, bbusWire2, lwSwFlag2, dbusWire2, DselectWire3,bbusWire3,lwSwFlag3,branchControlBitWire1,
branchControlBitWire2,NOPWire1,NOPWire2);
input clk;
input [63:0] dbusWire1, bbusWire2;
input [31:0] DselectWire2;
input [1:0] lwSwFlag2;
input [2:0] branchControlBitWire1;
input NOPWire1;
output [63:0] dbusWire2, bbusWire3;
output [31:0] DselectWire3;
output [1:0] lwSwFlag3;
output [2:0] branchControlBitWire2;
output NOPWire2;
reg [63:0] dbusWire2, bbusWire3;
reg [31:0] DselectWire3;
reg [1:0] lwSwFlag3;
reg [2:0] branchControlBitWire2;
reg NOPWire2;
always @(posedge clk) begin
dbusWire2 = dbusWire1;
DselectWire3 = DselectWire2;
bbusWire3 = bbusWire2;
lwSwFlag3 = lwSwFlag2;
branchControlBitWire2 = branchControlBitWire1;
NOPWire2 = NOPWire1;
end
endmodule
//phase 4 pipeline latch(MEM_WB)
module pipeline_4_latch(clk, dbusWire2, DselectWire3, bbusWire3, lwSwFlag3, dbusWire3, DselectWire4,bbusWire4,lwSwFlag4,branchControlBitWire2,
branchControlBitWire3,NOPWire2,NOPWire3);
input clk;
input [63:0] dbusWire2, bbusWire3;
input [31:0] DselectWire3;
input [1:0] lwSwFlag3;
input [2:0] branchControlBitWire2;
input NOPWire2;
output [63:0] dbusWire3, bbusWire4;
output [31:0] DselectWire4;
output [1:0] lwSwFlag4;
output [2:0] branchControlBitWire3;
output NOPWire3;
reg [63:0] dbusWire3, bbusWire4;
reg [31:0] DselectWire4;
reg [1:0] lwSwFlag4;
reg [2:0] branchControlBitWire3;
reg NOPWire3;
always @(posedge clk) begin
dbusWire3 = dbusWire2;
DselectWire4 = DselectWire3;
bbusWire4 = bbusWire3;
lwSwFlag4 = lwSwFlag3;
branchControlBitWire3 = branchControlBitWire2;
NOPWire3 = NOPWire2;
end
endmodule
module regfile(
input [31:0] Aselect,//select the register index to read from to store into abus
input [31:0] Bselect,//select the register index to read from to store into bbus
input [31:0] Dselect,//select the register to write to from dbus
input [63:0] dbus,//data in
output [63:0] abus,//data out
output [63:0] bbus,//data out
input clk
);
assign abus = Aselect[31] ? 64\'b0 : 64\'bz;
assign bbus = Bselect[31] ? 64\'b0 : 64\'bz;
DNegflipFlop myFlips[30:0](//32 wide register
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[30:0]),
.Bselect(Bselect[30:0]),
.Aselect(Aselect[30:0]),
.bbus(bbus),
.clk(clk)
);
endmodule
module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [63:0] dbus;
input Dselect;//the select write bit for this register
input Bselect;//the select read bit for this register
input Aselect;
input clk;
output [63:0] abus;
output [63:0] bbus;
wire wireclk;
reg [63:0] data;
assign wireclk = clk & Dselect;
initial begin
data = 64\'h0000000000000000;
end
always @(negedge clk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect? data : 64\'hzzzzzzzzzzzzzzzz;
assign bbus = Bselect? data : 64\'hzzzzzzzzzzzzzzzz;
endmodule
//Below this point is code from assignment 1//
//The declaration of the entire ALU itself.
module alu64 (d, Cout, V, a, b, Cin, S);
output[63:0] d;//the output bus
output Cout, V;//Cout is the bit for it it needs to carry over ?/ V is the overflow bit.
input [63:0] a, b;//the two input buses
input Cin;//the bit for marking if it is carrying over from a ?
input [2:0] S;//The select bus. It defines the operation to do with input busses a and b
wire [63:0] c, g, p;
wire gout, pout;
//The core ALU bus
alu_cell mycell[63:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
//the top Look-Ahead-Carry module.
lac6 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
//the overflow module
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[63]),
.Cin(Cin)
);
endmodule
//The module to handle a single bit operation for the top ALU module
module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;//generate carry
p = a ^ bint;//proragate carry
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule
//The module to handle the overflow bit
module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule
//Look-Ahead Carry unit level 1. Used for the root (level 1) and first child leafs (level 2)
module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule
//Look-Ahead Carry unit level 2. Contains LACs for the root and level 1. Used in level 3
module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 3. Contains LACs for the root and level 2. Used in level 4
module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 4. Contains LACs for the root and level 3. Used in level 5
module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 5. Contains LACs for the root and level 3. Used in level 6
module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 6. Caontains LACs for the root and level 5. Used in the core alu64 module
module lac6 (c, gout, pout, Cin, g, p);
output [63:0] c;
output gout, pout;
input Cin;
input [63:0] g, p;
wire [1:0] cint, gint, pint;
lac5 leaf0(
.c(c[31:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[31:0]),
.p(p[31:0])
);
lac5 leaf1(
.c(c[63:32]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[63:32]),
.p(p[63:32])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
|
`timescale 1ns/10ps // THIS DEFINES A UNIT TIME FOR THE TEST BENCH AND ITS PRECISION //
module alu32_testbench();
reg [31:0] a, b; // DECLARING I/O PORTS AND ALSO INTERNAL WIRES //
wire [31:0] d;
reg [2:0] S, Stm[0:31];
reg Cin;
reg [31:0] dontcare, str[0:31], ref[0:31], stma[0:31], stmb[0:31];
reg Vstr[0:31], Vref[0:31], Coutstm[0:31], Coutstr[0:31], Coutref[0:31], Cinstm[0:31];
integer ntests, error, k, i; // VARIABLES NOT RELATED TO ALU I/O , BUT REQUIRED FOR TESTBENCH //
alu32 dut(.a(a), .b(b), .d(d), .Cin(Cin), .Cout(Cout), .V(V), .S(S)); // DECLARES THE MODULE BEING TESTED ALONG WITH ITS I/O PORTS //
////////////////////////////////////////// \t\t\t //////////////////////////////////////////
///////// EXPECTED VALUES ////////////////\t\t\t////////// INPUTS TO ALU /////////
//////////////////////////////////////////\t\t //////////////////////////////////////////
initial begin //LOADING THE TEST REGISTERS WITH INPUTS AND EXPECTED VALUES//
ref[0] = 32\'h00000000; Vref[0] = 0; Coutref[0] = 0;\t\tStm[0] = 3\'b100; stma[0] = 32\'h00000000; stmb[0] = 32\'h00000000; Cinstm[0] = 0; // Test or //
ref[1] = 32\'h00000000; Vref[1] = 0; Coutref[1] = 0;\t\tStm[1] = 3\'b100; stma[1] = 32\'h00000000; stmb[1] = 32\'h00000000; Cinstm[1] = 0;
ref[2] = 32\'hFFFFFFFF; Vref[2] = 0; Coutref[2] = 0;\t\tStm[2] = 3\'b010; stma[2] = 32\'hFFFFFFFF; stmb[2] = 32\'h00000000; Cinstm[2] = 0; // Test Carry //
ref[3] = 32\'h00000000; Vref[3] = 0; Coutref[3] = 1; \tStm[3] = 3\'b010; stma[3] = 32\'hFFFFFFFF; stmb[3] = 32\'h00000000; Cinstm[3] = 1;
ref[4] = 32\'h7FFFFFFF; Vref[4] = 0; Coutref[4] = 0; \tStm[4] = 3\'b010; stma[4] = 32\'h7FFFFFFF; stmb[4] = 32\'h00000000; Cinstm[4] = 0;
ref[5] = 32\'h80000000; Vref[5] = 1; Coutref[5] = 0; \t\tStm[5] = 3\'b010; stma[5] = 32\'h7FFFFFFF; stmb[5] = 32\'h00000000; Cinstm[5] = 1;
ref[6] = 32\'h00100166; Vref[6] = 1\'bx; Coutref[6] = 1\'bx;\tStm[6] = 3\'b000; stma[6] = 32\'hF01010CA; stmb[6] = 32\'hF00011AC; Cinstm[6] = 0; // Test xor //
ref[7] = 32\'h0EEF9997; Vref[7] = 1\'bx; Coutref[7] = 1\'bx;\tStm[7] = 3\'b001; stma[7] = 32\'hF101CBA9; stmb[7] = 32\'h0011ADC1; Cinstm[7] = 0; // Test xnor //
ref[8] = 32\'h0000FFFF; Vref[8] = 1\'bx; Coutref[8] = 1\'bx;\tStm[8] = 3\'b110; stma[8] = 32\'hFFFFFFFF; stmb[8] = 32\'h0000FFFF; Cinstm[8] = 0; // Test and //
ref[9] = 32\'hF111EFE9; Vref[9] = 1\'bx; Coutref[9] = 1\'bx;\tStm[9] = 3\'b100; stma[9] = 32\'hF101CBA9; stmb[9] = 32\'h0011ADC1; Cinstm[9] = 0; // Test or //
ref[10] = 32\'h64424220;\tVref[10] = 1\'bx; Coutref[10] = 1\'bx;\tStm[10] = 3\'b010; stma[10] = 32\'h31312020; stmb[10] = 32\'h33112200; Cinstm[10] = 0; // Test add //
ref[11] = 32\'h64424221;\tVref[11] = 1\'bx; Coutref[11] = 1\'bx;\tStm[11] = 3\'b011; stma[11] = 32\'h31312020; stmb[11] = 32\'hCCEEDDFF; Cinstm[11] = 1; // Test sub //
ref[12] = 32\'h00000001;\tVref[12] = 1\'bx; Coutref[12] = 1\'bx;\tStm[12] = 3\'b010; stma[12] = 32\'h00000000; stmb[12] = 32\'h00000000; Cinstm[12] = 1; // Test Carry //
ref[13] = 32\'h0000000F;\tVref[13] = 1\'bx; Coutref[13] = 1\'bx;\tStm[13] = 3\'b010; stma[13] = 32\'h0000000F; stmb[13] = 32\'h00000000; Cinstm[13] = 0;
ref[14] = 32\'h00000010;\tVref[14] = 1\'bx; Coutref[14] = 1\'bx;\tStm[14] = 3\'b010; stma[14] = 32\'h0000000F; stmb[14] = 32\'h00000000; Cinstm[14] = 1;
ref[15] = 32\'h000000FF;\tVref[15] = 1\'bx; Coutref[15] = 1\'bx;\tStm[15] = 3\'b010; stma[15] = 32\'h000000FF; stmb[15] = 32\'h00000000; Cinstm[15] = 0;
ref[16] = 32\'h00000100;\tVref[16] = 1\'bx; Coutref[16] = 1\'bx;\tStm[16] = 3\'b010; stma[16] = 32\'h000000FF; stmb[16] = 32\'h00000000; Cinstm[16] = 1;
ref[17] = 32\'h00000FFF;\tVref[17] = 1\'bx; Coutref[17] = 1\'bx;\tStm[17] = 3\'b010; stma[17] = 32\'h00000FFF; stmb[17] = 32\'h00000000; Cinstm[17] = 0;
ref[18] = 32\'h00001000;\tVref[18] = 1\'bx; Coutref[18] = 1\'bx;\tStm[18] = 3\'b010; stma[18] = 32\'h00000FFF; stmb[18] = 32\'h00000000; Cinstm[18] = 1;
ref[19] = 32\'h0000FFFF;\tVref[19] = 1\'bx; Coutref[19] = 1\'bx;\tStm[19] = 3\'b010; stma[19] = 32\'h0000FFFF; stmb[19] = 32\'h00000000; Cinstm[19] = 0;
ref[20] = 32\'h00010000; Vref[20] = 1\'bx; Coutref[20] = 1\'bx;\tStm[20] = 3\'b010; stma[20] = 32\'h0000FFFF; stmb[20] = 32\'h00000000; Cinstm[20] = 1;
ref[21] = 32\'h000FFFFF; Vref[21] = 1\'bx; Coutref[21] = 1\'bx;\tStm[21] = 3\'b010; stma[21] = 32\'h000FFFFF; stmb[21] = 32\'h00000000; Cinstm[21] = 0;
ref[22] = 32\'h00100000;\tVref[22] = 1\'bx; Coutref[22] = 1\'bx;\tStm[22] = 3\'b010; stma[22] = 32\'h000FFFFF; stmb[22] = 32\'h00000000; Cinstm[22] = 1;
ref[23] = 32\'h00FFFFFF;\tVref[23] = 1\'bx; Coutref[23] = 1\'bx;\tStm[23] = 3\'b010; stma[23] = 32\'h00FFFFFF; stmb[23] = 32\'h00000000; Cinstm[23] = 0;
ref[24] = 32\'h01000000;\tVref[24] = 1\'bx; Coutref[24] = 1\'bx;\tStm[24] = 3\'b010; stma[24] = 32\'h00FFFFFF; stmb[24] = 32\'h00000000; Cinstm[24] = 1;
ref[25] = 32\'h0FFFFFFF;\tVref[25] = 1\'bx; Coutref[25] = 1\'bx;\tStm[25] = 3\'b010; stma[25] = 32\'h0FFFFFFF; stmb[25] = 32\'h00000000; Cinstm[25] = 0;
ref[26] = 32\'h10000000;\tVref[26] = 1\'bx; Coutref[26] = 1\'bx;\tStm[26] = 3\'b010; stma[26] = 32\'h0FFFFFFF; stmb[26] = 32\'h00000000; Cinstm[26] = 1;
ref[27] = 32\'h00000000; Vref[27] = 1\'bx; Coutref[27] = 1\'bx;\tStm[27] = 3\'b101; stma[27] = 32\'hFFFFFFFF; stmb[27] = 32\'h0000FFFF; Cinstm[27] = 0; // Test nor //
ref[28] = 32\'hx; Vref[28] = 0; Coutref[28] = 0;\t\t\tStm[28] = 3\'b010; stma[28] = 32\'h00000000; stmb[28] = 32\'h00000000; Cinstm[28] = 0; // Test Cout, V //
ref[29] = 32\'hx; Vref[29] = 0; Coutref[29] = 1;\t\t\tStm[29] = 3\'b010; stma[29] = 32\'hFFFFFFFF; stmb[29] = 32\'hFFFFFFFF; Cinstm[29] = 0;
ref[30] = 32\'hx; Vref[30] = 1; Coutref[30] = 1;\t\t\tStm[30] = 3\'b010; stma[30] = 32\'h80000000; stmb[30] = 32\'h80000000; Cinstm[30] = 0;
ref[31] = 32\'hx; Vref[31] = 1; Coutref[31] = 0;\t\t\tStm[31] = 3\'b010; stma[31] = 32\'h40000000; stmb[31] = 32\'h40000000; Cinstm[31] = 0;
dontcare = 32\'hx;
ntests = 32;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
for (k=0; k<= ntests; k=k+1) \t\t // LOOPING THROUGH ALL THE TEST VECTORS AND ASSIGNING IT TO THE ALU INPUTS EVERY 8ns //
begin
S = Stm[k]; a = stma[k] ; b = stmb[k]; Cin = Cinstm[k];
#20 str[k] = d; Vstr[k] = V; Coutstr[k] = Cout; // #20 IS 8 ns DELAY FOR ASSIGNING THE OUTPUT TO THE REFERENCE REGISTERS //
if ( S == 3\'b000 )
$display ("----- TEST FOR A XOR B -----");
if ( S == 3\'b001 )
$display ("----- TEST FOR A XNOR B -----");
if ( S == 3\'b010 )
$display ("----- TEST FOR A + B/ CARRY CHAIN -----");
if ( S == 3\'b011 )
$display ("----- TEST FOR A - B -----");
if ( S == 3\'b100 )
$display ("----- TEST FOR A OR B -----");
if ( S == 3\'b101 )
$display ("----- TEST FOR A NOR B -----");
if ( S == 3\'b110 )
$display ("----- TEST FOR A AND B -----");
$display ("Time=%t \
S=%b \
Cin=%b \
a=%b \
b=%b \
d=%b \
ref=%b \
Cout=%b \
CoutRef=%b \
V=%b \
Vref=%b \
",$realtime, S, Cin, a, b, d, ref[k], Cout, Coutref[k], V, Vref[k]);
// THIS CONTROL BLOCK CHECKS FOR ERRORS BY COMPARING YOUR OUTPUT WITH THE EXPECTED OUTPUTS AND INCREMENTS "error" IN CASE OF ERROR //
if (( (ref[k] !== str[k]) && (ref[k] !== dontcare) ) || ( (Vref[k] !== Vstr[k]) && (Vref[k] !== 1\'bx) ) || ( (Coutref[k] !== Coutstr[k]) && (Coutref[k] !== 1\'bx) ) )
begin
$display ("-------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
if ( error != 0)
$display("---------------ERRORS. Mismatches Have Occured, sorry------------------");
$display(" Number Of Errors = %d", error);
$display(" Total Test numbers = %d", ntests);
$display(" Total number of correct operations = %d", (ntests-error));
end
endmodule
|
`timescale 1ns/10ps // THIS DEFINES A UNIT TIME FOR THE TEST BENCH AND ITS PRECISION //
module alupipe_testbench();
reg [31:0] a, b; // DECLARING I/O PORTS AND ALSO INTERNAL WIRES //
wire [31:0] d;
reg [2:0] S, Stm[0:33];
reg Cin, clk;
reg [31:0] dontcare, str[0:33], ref[0:33], stma[0:33], stmb[0:33];
reg Vstr[0:33], Vref[0:33], Coutstr[0:33], Coutref[0:33], Cinstm[0:33];
integer ntests, error, k, i; // VARIABLES NOT RELATED TO ALU I/O , BUT REQUIRED FOR TESTBENCH //
alupipe dut(.abus(a), .bbus(b), .dbus(d), .Cin(Cin), .S(S), .clk(clk)); // DECLARES THE MODULE BEING TESTED ALONG WITH ITS I/O PORTS //
////////////////////////////////////////// \t\t\t //////////////////////////////////////////
///////// EXPECTED VALUES ////////////////\t\t\t////////// INPUTS TO ALU /////////
//////////////////////////////////////////\t\t //////////////////////////////////////////
initial begin //LOADING THE TEST REGISTERS WITH INPUTS AND EXPECTED VALUES//
ref[0] = 32\'h00000000; Vref[0] = 0; Coutref[0] = 0;\t\tStm[0] = 3\'b100; stma[0] = 32\'h00000000; stmb[0] = 32\'h00000000; Cinstm[0] = 0; // Test or //
ref[1] = 32\'h00000000; Vref[1] = 0; Coutref[1] = 0;\t\tStm[1] = 3\'b100; stma[1] = 32\'h00000000; stmb[1] = 32\'h00000000; Cinstm[1] = 0;
ref[2] = 32\'hFFFFFFFF; Vref[2] = 0; Coutref[2] = 0;\t\tStm[2] = 3\'b010; stma[2] = 32\'hFFFFFFFF; stmb[2] = 32\'h00000000; Cinstm[2] = 0; // Test Carry //
ref[3] = 32\'h00000000; Vref[3] = 0; Coutref[3] = 1; \tStm[3] = 3\'b010; stma[3] = 32\'hFFFFFFFF; stmb[3] = 32\'h00000000; Cinstm[3] = 1;
ref[4] = 32\'h7FFFFFFF; Vref[4] = 0; Coutref[4] = 0; \tStm[4] = 3\'b010; stma[4] = 32\'h7FFFFFFF; stmb[4] = 32\'h00000000; Cinstm[4] = 0;
ref[5] = 32\'h80000000; Vref[5] = 1; Coutref[5] = 0; \t\tStm[5] = 3\'b010; stma[5] = 32\'h7FFFFFFF; stmb[5] = 32\'h00000000; Cinstm[5] = 1;
ref[6] = 32\'h00100166; Vref[6] = 1\'bx; Coutref[6] = 1\'bx;\tStm[6] = 3\'b000; stma[6] = 32\'hF01010CA; stmb[6] = 32\'hF00011AC; Cinstm[6] = 0; // Test xor //
ref[7] = 32\'h0EEF9997; Vref[7] = 1\'bx; Coutref[7] = 1\'bx;\tStm[7] = 3\'b001; stma[7] = 32\'hF101CBA9; stmb[7] = 32\'h0011ADC1; Cinstm[7] = 0; // Test xnor //
ref[8] = 32\'h0000FFFF; Vref[8] = 1\'bx; Coutref[8] = 1\'bx;\tStm[8] = 3\'b110; stma[8] = 32\'hFFFFFFFF; stmb[8] = 32\'h0000FFFF; Cinstm[8] = 0; // Test and //
ref[9] = 32\'hF111EFE9; Vref[9] = 1\'bx; Coutref[9] = 1\'bx;\tStm[9] = 3\'b100; stma[9] = 32\'hF101CBA9; stmb[9] = 32\'h0011ADC1; Cinstm[9] = 0; // Test or //
ref[10] = 32\'h64424220;\tVref[10] = 1\'bx; Coutref[10] = 1\'bx;\tStm[10] = 3\'b010; stma[10] = 32\'h31312020; stmb[10] = 32\'h33112200; Cinstm[10] = 0; // Test add //
ref[11] = 32\'h64424221;\tVref[11] = 1\'bx; Coutref[11] = 1\'bx;\tStm[11] = 3\'b011; stma[11] = 32\'h31312020; stmb[11] = 32\'hCCEEDDFF; Cinstm[11] = 1; // Test sub //
ref[12] = 32\'h00000001;\tVref[12] = 1\'bx; Coutref[12] = 1\'bx;\tStm[12] = 3\'b010; stma[12] = 32\'h00000000; stmb[12] = 32\'h00000000; Cinstm[12] = 1; // Test Carry //
ref[13] = 32\'h0000000F;\tVref[13] = 1\'bx; Coutref[13] = 1\'bx;\tStm[13] = 3\'b010; stma[13] = 32\'h0000000F; stmb[13] = 32\'h00000000; Cinstm[13] = 0;
ref[14] = 32\'h00000010;\tVref[14] = 1\'bx; Coutref[14] = 1\'bx;\tStm[14] = 3\'b010; stma[14] = 32\'h0000000F; stmb[14] = 32\'h00000000; Cinstm[14] = 1;
ref[15] = 32\'h000000FF;\tVref[15] = 1\'bx; Coutref[15] = 1\'bx;\tStm[15] = 3\'b010; stma[15] = 32\'h000000FF; stmb[15] = 32\'h00000000; Cinstm[15] = 0;
ref[16] = 32\'h00000100;\tVref[16] = 1\'bx; Coutref[16] = 1\'bx;\tStm[16] = 3\'b010; stma[16] = 32\'h000000FF; stmb[16] = 32\'h00000000; Cinstm[16] = 1;
ref[17] = 32\'h00000FFF;\tVref[17] = 1\'bx; Coutref[17] = 1\'bx;\tStm[17] = 3\'b010; stma[17] = 32\'h00000FFF; stmb[17] = 32\'h00000000; Cinstm[17] = 0;
ref[18] = 32\'h00001000;\tVref[18] = 1\'bx; Coutref[18] = 1\'bx;\tStm[18] = 3\'b010; stma[18] = 32\'h00000FFF; stmb[18] = 32\'h00000000; Cinstm[18] = 1;
ref[19] = 32\'h0000FFFF;\tVref[19] = 1\'bx; Coutref[19] = 1\'bx;\tStm[19] = 3\'b010; stma[19] = 32\'h0000FFFF; stmb[19] = 32\'h00000000; Cinstm[19] = 0;
ref[20] = 32\'h00010000; Vref[20] = 1\'bx; Coutref[20] = 1\'bx;\tStm[20] = 3\'b010; stma[20] = 32\'h0000FFFF; stmb[20] = 32\'h00000000; Cinstm[20] = 1;
ref[21] = 32\'h000FFFFF; Vref[21] = 1\'bx; Coutref[21] = 1\'bx;\tStm[21] = 3\'b010; stma[21] = 32\'h000FFFFF; stmb[21] = 32\'h00000000; Cinstm[21] = 0;
ref[22] = 32\'h00100000;\tVref[22] = 1\'bx; Coutref[22] = 1\'bx;\tStm[22] = 3\'b010; stma[22] = 32\'h000FFFFF; stmb[22] = 32\'h00000000; Cinstm[22] = 1;
ref[23] = 32\'h00FFFFFF;\tVref[23] = 1\'bx; Coutref[23] = 1\'bx;\tStm[23] = 3\'b010; stma[23] = 32\'h00FFFFFF; stmb[23] = 32\'h00000000; Cinstm[23] = 0;
ref[24] = 32\'h01000000;\tVref[24] = 1\'bx; Coutref[24] = 1\'bx;\tStm[24] = 3\'b010; stma[24] = 32\'h00FFFFFF; stmb[24] = 32\'h00000000; Cinstm[24] = 1;
ref[25] = 32\'h0FFFFFFF;\tVref[25] = 1\'bx; Coutref[25] = 1\'bx;\tStm[25] = 3\'b010; stma[25] = 32\'h0FFFFFFF; stmb[25] = 32\'h00000000; Cinstm[25] = 0;
ref[26] = 32\'h10000000;\tVref[26] = 1\'bx; Coutref[26] = 1\'bx;\tStm[26] = 3\'b010; stma[26] = 32\'h0FFFFFFF; stmb[26] = 32\'h00000000; Cinstm[26] = 1;
ref[27] = 32\'h00000000; Vref[27] = 1\'bx; Coutref[27] = 1\'bx;\tStm[27] = 3\'b101; stma[27] = 32\'hFFFFFFFF; stmb[27] = 32\'h0000FFFF; Cinstm[27] = 0; // Test nor //
ref[28] = 32\'hx; Vref[28] = 0; Coutref[28] = 0;\t\t\tStm[28] = 3\'b010; stma[28] = 32\'h00000000; stmb[28] = 32\'h00000000; Cinstm[28] = 0; // Test Cout, V //
ref[29] = 32\'hx; Vref[29] = 0; Coutref[29] = 1;\t\t\tStm[29] = 3\'b010; stma[29] = 32\'hFFFFFFFF; stmb[29] = 32\'hFFFFFFFF; Cinstm[29] = 0;
ref[30] = 32\'hx; Vref[30] = 1; Coutref[30] = 1;\t\t\tStm[30] = 3\'b010; stma[30] = 32\'h80000000; stmb[30] = 32\'h80000000; Cinstm[30] = 0;
ref[31] = 32\'hx; Vref[31] = 1; Coutref[31] = 0;\t\t\tStm[31] = 3\'b010; stma[31] = 32\'h40000000; stmb[31] = 32\'h40000000; Cinstm[31] = 0;
ref[32] = 32\'hx; Vref[32] = 1\'bx; Coutref[32] =1\'bx;\t\t\tStm[32] = 3\'hx; stma[32] = 32\'hx; stmb[32] = 32\'hx; Cinstm[32] =1\'bx;
ref[33] = 32\'hx; Vref[33] =1\'bx; Coutref[33] =1\'bx;\t\t\tStm[33] = 3\'hx; stma[33] = 32\'hx; stmb[33] = 32\'hx; Cinstm[33] =1\'bx;
dontcare = 32\'hx;
ntests = 32;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
for (k=0; k<= ntests+1; k=k+1) \t\t // LOOPING THROUGH ALL THE TEST VECTORS AND ASSIGNING IT TO THE ALU INPUTS EVERY 25ns //
begin
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#12.5
clk=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
a = stma[k] ; b = stmb[k];
if (k >= 1) begin
S = Stm[k-1]; Cin = Cinstm[k-1];
end
if (k >=2) begin
if ( Stm[k-2] == 3\'b000 )
$display ("----- TEST FOR A XOR B -----");
if ( Stm[k-2] == 3\'b001 )
$display ("----- TEST FOR A XNOR B -----");
if ( Stm[k-2] == 3\'b010 )
$display ("----- TEST FOR A + B/ CARRY CHAIN -----");
if ( Stm[k-2] == 3\'b011 )
$display ("----- TEST FOR A - B -----");
if ( Stm[k-2] == 3\'b100 )
$display ("----- TEST FOR A OR B -----");
if ( Stm[k-2] == 3\'b101 )
$display ("----- TEST FOR A NOR B -----");
if ( Stm[k-2] == 3\'b110 )
$display ("----- TEST FOR A AND B -----");
$display ("Time=%t \
S=%b \
Cin=%b \
a=%b \
b=%b \
d=%b \
ref=%b \
",$realtime, Stm[k-2], Cinstm[k-2], stma[k-2], stmb[k-2], d, ref[k-2]);
// THIS CONTROL BLOCK CHECKS FOR ERRORS BY COMPARING YOUR OUTPUT WITH THE EXPECTED OUTPUTS AND INCREMENTS "error" IN CASE OF ERROR //
if (( (ref[k-2] !== d) && (ref[k-2] !== dontcare) ) )
begin
$display ("-------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
#12.5 ;
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
if ( error != 0)
$display("---------------ERRORS. Mismatches Have Occured------------------");
end
endmodule
|
//Phase 1: tests basic data processing instructions for a 64bit version of the ARM LEG CPU
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:17];
wire [63:0] iaddrbus;
reg [63:0] iaddrbusout[0:17];
wire [31:0] dselect;
reg [31:0] dselectout[0:17];
wire [63:0] dbus;
reg [63:0] dbusout[0:17];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [31:0] dontcare_addr;
reg [24*8:1] iname[0:17];
integer error, k, ntests;
//all current opcode parameters to be used
parameter ADD = 11\'b10001011000;
parameter ADDI = 10\'b1001000100;
//parameter ADDI = \'b;
//parameter ADDI = \'b;
parameter AND = 11\'b10001010000;
parameter ANDI = 10\'b1001001000;
//parameter ANDI = \'b;
//parameter ANDI = \'b;
//CBNZ
//CBZ
parameter EOR = 11\'b11001010000;
parameter EORI = 10\'b1101001000;
//LDUR
//parameter LW = \'b;
//LSL
//LSR
//MOVZ
parameter ORR = 11\'b10101010000;
parameter ORRI = 10\'b1011001000;
//STUR
//parameter SW = \'b;
parameter SUB = 11\'b11001011000;
parameter SUBI = 10\'b1101000100;
//parameter SUBI = \'b;
//parameter SUBI = \'b;
//B
//parameter B.EQ = \'b;
//parameter B.NE = \'b;
//parameter SLT = \'b;
//parameter SLE = \'b
//register parameters
parameter R0 = 5\'b00000;
parameter R0_dselect = 32\'b00000000000000000000000000000001;
parameter R20 = 5\'b10100;
parameter R20_dselect = 32\'b00000000000100000000000000000000;
parameter R21 = 5\'b10101;
parameter R21_dselect = 32\'b00000000001000000000000000000000;
parameter R22 = 5\'b10110;
parameter R22_dselect = 32\'b00000000010000000000000000000000;
parameter R23 = 5\'b10111;
parameter R23_dselect = 32\'b00000000100000000000000000000000;
parameter R24 = 5\'b11000;
parameter R24_dselect = 32\'b00000001000000000000000000000000;
parameter R25 = 5\'b11001;
parameter R25_dselect = 32\'b00000010000000000000000000000000;
parameter R26 = 5\'b11010;
parameter R26_dselect = 32\'b00000100000000000000000000000000;
parameter R27 = 5\'b11011;
parameter R27_dselect = 32\'b00001000000000000000000000000000;
parameter R28 = 5\'b11100;
parameter R28_dselect = 32\'b00010000000000000000000000000000;
parameter R29 = 5\'b11101;
parameter R29_dselect = 32\'b00100000000000000000000000000000;
parameter R30 = 5\'b11110;
parameter R30_dselect = 32\'b01000000000000000000000000000000;
parameter R31 = 5\'b11111;
parameter R31_dselect = 32\'b10000000000000000000000000000000;
//other parameterz to be used
parameter zeroSham = 6\'b000000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.dbus(dbus),.dselect(dselect));
initial begin
dontcare = 64\'hx;
dontcare_addr = 32\'hx;
//phase 1: testing basic op commands and instruction bus
//* ADDI, R20, R31, #AAA
iname[0] = "ADDI, R20, R31, #AAA";//testing addi, result in R20 = 00000AAA
iaddrbusout[0] = 64\'h00000000;
// opcode rm/ALUImm rn rd...
instrbusin[0]={ADDI, 12\'hAAA, R31, R20};
dselectout[0] = R20_dselect;
dbusout[0] = 64\'h00000AAA;
//* ADDI, R31, R23, #002
iname[1] = "ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 00000000
iaddrbusout[1] = 64\'h00000004;
// opcode rm/ALUImm rn rd...
instrbusin[1]={ADDI, 12\'h002, R23, R31};
dselectout[1] = R31_dselect;
dbusout[1] = dontcare;
//* ADDI, R0, R23, #002
iname[2] = "ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 00000002
iaddrbusout[2] = 64\'h00000008;
// opcode rm/ALUImm rn rd...
instrbusin[2]={ADDI, 12\'h002, R23, R0};
dselectout[2] = R0_dselect;
dbusout[2] = 64\'h00000002;
//* ORRI, R21, R24, #001
iname[3] = "ORRI, R21, R24, #001";//testing ori, result in R21 = 00000001
iaddrbusout[3] = 64\'h0000000C;
// opcode rm/ALUImm rn rd...
instrbusin[3]={ORRI, 12\'h001, R24, R21};
dselectout[3] = R21_dselect;
dbusout[3] = 64\'h00000001;
//* EORI, R22, R20, #000
iname[4] = "EORI, R22, R20, #000";//testing xori, result in R22 = 00000AAA
iaddrbusout[4] = 64\'h00000010;
// opcode rm/ALUImm rn rd...
instrbusin[4]={EORI, 12\'h000, R20, R22};
dselectout[4] = R22_dselect;
dbusout[4] = 64\'h00000AAA;
//* ANDI, R23, R0, #003
iname[5] = "ANDI, R23, R0, #003";//testing andi, result in R23 = 00000002
iaddrbusout[5] = 64\'h00000014;
// opcode rm/ALUImm rn rd...
instrbusin[5]={ANDI, 12\'h003, R0, R23};
dselectout[5] = R23_dselect;
dbusout[5] = 64\'h00000002;
//* SUBI, R24, R20, #00A
iname[6] = "SUBI, R24, R20, #00A";//testing subi, result in R24 = 00000AA0
iaddrbusout[6] = 64\'h00000018;
// opcode rm/ALUImm rn rd...
instrbusin[6]={SUBI, 12\'h00A, R20, R24};
dselectout[6] = R24_dselect;
dbusout[6] = 64\'h00000AA0;
// op, rd, rn, rm
//* ADD, R25, R20, R0
iname[7] = "ADD, R25, R20, R0";//testing add, result in R25 = 00000AAC
iaddrbusout[7] = 64\'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7]={ADD, R0, zeroSham, R20, R25};
dselectout[7] = R25_dselect;
dbusout[7] = 64\'h00000AAC;
// op, rd, rn, rm
//* AND, R26, R20, R22
iname[8] = "AND, R26, R20, R22";//testing and, result in R26 = 00000AAA
iaddrbusout[8] = 64\'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8]={AND, R22, zeroSham, R20, R26};
dselectout[8] = R26_dselect;
dbusout[8] = 64\'h00000AAA;
// op, rd, rn, rm
//* XOR, R27, R23, R21
iname[9] = "EOR, R27, R23, R21";//testing xor, result in R27 = 00000003
iaddrbusout[9] = 64\'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9]={EOR, R21, zeroSham, R23, R27};
dselectout[9] = R27_dselect;
dbusout[9] = 64\'h00000003;
// op, rd, rn, rm
//* OR, R28, R25, R23
iname[10] = "ORR, R28, R25, R23";//testing or, result in R28 = 00000AAE
iaddrbusout[10] = 64\'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10]={ORR, R23, zeroSham, R25, R28};
dselectout[10] = R28_dselect;
dbusout[10] = 64\'h00000AAE;
// op, rd, rn, rm
//* SUB, R29, R20, R22
iname[11] = "SUB, R29, R20, R22";//testing sub, result in R29 = 00000000
iaddrbusout[11] = 64\'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11]={SUB, R22, zeroSham, R20, R29};
dselectout[11] = R29_dselect;
dbusout[11] = 64\'h00000000;
// op, rd, rn, aluImm
//* ADDI, R30, R31, #000
iname[12] = "ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 00000000
iaddrbusout[12] = 64\'h00000030;
// opcode rm/ALUImm rn rd...
instrbusin[12]={ADDI, 12\'h000, R31, R30};
dselectout[12] = R30_dselect;
dbusout[12] = 64\'h00000000;
//* NOP
iname[13] = "NOP";//nada
iaddrbusout[13] = 64\'h00000034;
instrbusin[13] = 32\'b00000000000000000000000000000000;
dselectout[13] = dontcare_addr;
dbusout[13] = dontcare;
//* NOP
iname[14] = "NOP";//nada
iaddrbusout[14] = 64\'h00000038;
instrbusin[14] = 32\'b00000000000000000000000000000000;
dselectout[14] = dontcare_addr;
dbusout[14] = dontcare;
//* NOP
iname[15] = "NOP";//nada
iaddrbusout[15] = 64\'h0000003C;
instrbusin[15] = 32\'b00000000000000000000000000000000;
dselectout[15] = dontcare_addr;
dbusout[15] = dontcare;
//* NOP
iname[16] = "NOP";//nada
iaddrbusout[16] = 64\'h00000040;
instrbusin[16] = 32\'b00000000000000000000000000000000;
dselectout[16] = dontcare_addr;
dbusout[16] = dontcare;
//* NOP
iname[17] = "NOP";//nada
iaddrbusout[17] = 64\'h00000044;
instrbusin[17] = 32\'b00000000000000000000000000000000;
dselectout[17] = dontcare_addr;
dbusout[17] = dontcare;
ntests = 18;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
//assign databus = clkd ? 32\'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
//databusk = 32\'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#5
$display ("Time=%t\
clk=%b", $realtime, clk);
for (k=0; k<= 17; k=k+1) begin
clk=1;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set dbus and dselect data data for 4th previous instruction
if (k >=4)
//databusk = databusin[k-4];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b%b%b%b%b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check writeback data address from 4th previous instruction
if ( (k >= 4) && (dselectout[k-4] !== dontcare_addr) ) begin
$display (" Testing writeback data address for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dselect = %b", dselect);
$display (" Correct dselect = %b", dselectout[k-4]);
if (dselectout[k-4] !== dselect) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check writeback data from 4th previous instruction
if ( (k >= 4) && (dbusout[k-4] !== dontcare) ) begin
$display (" Testing writeback data for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dbus = %b", dbus);
$display (" Correct dbus = %b", dbusout[k-4]);
if (dbusout[k-4] !== dbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\
clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\
clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
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