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// megafunction wizard: %FIFO%VBB%\r
// GENERATION: STANDARD\r
// VERSION: WM1.0\r
// MODULE: dcfifo \r
\r
// ============================================================\r
// File Name: gsensor_fifo.v\r
// Megafunction Name(s):\r
// \t\t\tdcfifo\r
//\r
// Simulation Library Files(s):\r
// \t\t\taltera_mf\r
// ============================================================\r
// ************************************************************\r
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
//\r
// 10.1 Build 153 11/29/2010 SJ Full Version\r
// ************************************************************\r
\r
//Copyright (C) 1991-2010 Altera Corporation\r
//Your use of Altera Corporation\'s design tools, logic functions \r
//and other software and tools, and its AMPP partner logic \r
//functions, and any output files from any of the foregoing \r
//(including device programming or simulation files), and any \r
//associated documentation or information are expressly subject \r
//to the terms and conditions of the Altera Program License \r
//Subscription Agreement, Altera MegaCore Function License \r
//Agreement, or other applicable license agreement, including, \r
//without limitation, that your use is for the sole purpose of \r
//programming logic devices manufactured by Altera and sold by \r
//Altera or its authorized distributors. Please refer to the \r
//applicable agreement for further details.\r
\r
module gsensor_fifo (\r
\taclr,\r
\tdata,\r
\trdclk,\r
\trdreq,\r
\twrclk,\r
\twrreq,\r
\tq,\r
\trdempty,\r
\trdusedw,\r
\twrfull,\r
\twrusedw);\r
\r
\tinput\t aclr;\r
\tinput\t[7:0] data;\r
\tinput\t rdclk;\r
\tinput\t rdreq;\r
\tinput\t wrclk;\r
\tinput\t wrreq;\r
\toutput\t[7:0] q;\r
\toutput\t rdempty;\r
\toutput\t[3:0] rdusedw;\r
\toutput\t wrfull;\r
\toutput\t[3:0] wrusedw;\r
`ifndef ALTERA_RESERVED_QIS\r
// synopsys translate_off\r
`endif\r
\ttri0\t aclr;\r
`ifndef ALTERA_RESERVED_QIS\r
// synopsys translate_on\r
`endif\r
\r
endmodule\r
\r
// ============================================================\r
// CNX file retrieval info\r
// ============================================================\r
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"\r
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"\r
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"\r
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"\r
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"\r
// Retrieval info: PRIVATE: Clock NUMERIC "4"\r
// Retrieval info: PRIVATE: Depth NUMERIC "16"\r
// Retrieval info: PRIVATE: Empty NUMERIC "1"\r
// Retrieval info: PRIVATE: Full NUMERIC "1"\r
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"\r
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "1"\r
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"\r
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"\r
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"\r
// Retrieval info: PRIVATE: Optimize NUMERIC "0"\r
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"\r
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"\r
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"\r
// Retrieval info: PRIVATE: UsedW NUMERIC "1"\r
// Retrieval info: PRIVATE: Width NUMERIC "8"\r
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"\r
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"\r
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"\r
// Retrieval info: PRIVATE: output_width NUMERIC "8"\r
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"\r
// Retrieval info: PRIVATE: rsFull NUMERIC "0"\r
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"\r
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"\r
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"\r
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"\r
// Retrieval info: PRIVATE: wsFull NUMERIC "1"\r
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"\r
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"\r
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"\r
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"\r
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"\r
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"\r
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"\r
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"\r
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"\r
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"\r
// Retrieval info: CONSTANT: USE_EAB STRING "OFF"\r
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"\r
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"\r
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"\r
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"\r
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"\r
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"\r
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"\r
// Retrieval info: USED_PORT: rdusedw 0 0 4 0 OUTPUT NODEFVAL "rdusedw[3..0]"\r
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"\r
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"\r
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"\r
// Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL "wrusedw[3..0]"\r
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0\r
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0\r
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0\r
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0\r
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0\r
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0\r
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0\r
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0\r
// Retrieval info: CONNECT: rdusedw 0 0 4 0 @rdusedw 0 0 4 0\r
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0\r
// Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0\r
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo.v TRUE\r
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo.inc FALSE\r
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo.cmp FALSE\r
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo.bsf FALSE\r
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo_inst.v FALSE\r
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo_bb.v TRUE\r
// Retrieval info: LIB_FILE: altera_mf\r
|
// Power management
//
// Allows the FPGA to turn on and off power, as well as monitor voltage levels
// Ignore overvoltage errors for 10 cycles or 5kHz
`define OVERVOLT_GRACE 4'd10
// Ignore undervoltage errors for 50000 cycles or 10s
`define UNDERVOLT_GRACE 16'd50000
module power_management (
output reg kill_sw,
output reg [2:0] sel,
output error,
input ack,
input data,
input start, /* Signal to turn on power */
input clk /* 50 MHz */
);
reg [9:0] wait_cnt; /* Overflow at ~49 KHz */
reg [3:0] overvolt_grace_cnt;
reg [15:0] undervolt_grace_cnt;
reg error_reg;
always @(posedge clk)
// Wait state (until start is high)
if (start == 1'd0)
begin
kill_sw <= 1'b0;
sel <= 3'b111;
wait_cnt = 10'd0;
error_reg = 1'b0;
overvolt_grace_cnt = `OVERVOLT_GRACE;
undervolt_grace_cnt = `UNDERVOLT_GRACE;
end
// Monitor voltage levels continuously
else
begin
kill_sw <= 1'b1;
if (!error_reg)
wait_cnt <= wait_cnt + 10'd1;
if (ack)
error_reg <= 1'b0;
if (!error_reg && wait_cnt == 10'd0)
begin
if (overvolt_grace_cnt != 4'd0)
overvolt_grace_cnt <= overvolt_grace_cnt - 4'd1;
if (undervolt_grace_cnt != 16'd0)
undervolt_grace_cnt <= undervolt_grace_cnt - 16'd1;
if (sel == 3'd6)
begin
sel <= 3'b000;
end
else
sel <= sel + 3'b001;
end
// Check input after waiting a ~49 KHz cycle (ignore when sel is 111)
// Power off if data is Low on an Even check or High on an Odd check
if (&wait_cnt && !(&sel)
&& ((data == 1'b0 && sel[0] == 1'b0 && undervolt_grace_cnt == 6'd0)
|| (data == 1'b1 && sel[0] == 1'b1 && overvolt_grace_cnt == 20'd0)))
begin
error_reg <= 1'd1;
end
end
assign error = error_reg;
endmodule
|
// This is the Avalon slave for the motor controller
// Registers 0-5 store the direction and on/off switch for each motor
// Registers 8-13 store the respective duty cycle
// The output should be fed to GPIO pins in the SOPC configuration
`include "defines.v"
module slave_controller(input clk, input chipselect, input write, input [3:0]addr, input [31:0] writedata, output [23:0] GPIO_out);
reg [11:0] in = 12\'d0;
reg [6*`PERIOD_LENGTH-1:0] duty_cycle = 0;
reg [15:0] period = 16\'d0;
always @(posedge clk)
if (chipselect & write)
casex (addr)
4\'b0000:
in[1:0] <= writedata[1:0];
4\'b0001:
in[3:2] <= writedata[1:0];
4\'b0010:
in[5:4] <= writedata[1:0];
4\'b0011:
in[7:6] <= writedata[1:0];
4\'b0100:
in[9:8] <= writedata[1:0];
4\'b0101:
in[11:10] <= writedata[1:0];
4\'b1000:
duty_cycle[`PERIOD_LENGTH-1:0] <= writedata[`PERIOD_LENGTH-1:0];
4\'b1001:
duty_cycle[2*`PERIOD_LENGTH-1:`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH-1:0];
4\'b1010:
duty_cycle[3*`PERIOD_LENGTH-1:2*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH-1:0];
4\'b1011:
duty_cycle[4*`PERIOD_LENGTH-1:3*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH-1:0];
4\'b1100:
duty_cycle[5*`PERIOD_LENGTH-1:4*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH:0];
4\'b1101:
duty_cycle[6*`PERIOD_LENGTH-1:5*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH:0];
4\'b1110:
period <= writedata[15:0];
default:
; // do nothing
endcase
generate
genvar i;
for (i=0; i<6; i=i+1)
begin : motor_control_loop
motor_controller mc(clk, in[i*2 + 1], in[i*2], period, duty_cycle[(i+1)*`PERIOD_LENGTH-1:i*`PERIOD_LENGTH], GPIO_out[i*4+3:i*4]);
end
endgenerate
endmodule
|
// This is the Avalon slave for the IMU
//
// Registers 0-7 store ADC outputs
module imu_controller(
input chipselect,
input [3:0]addr,
input read,
output reg [31:0] readdata,
input spi_clk,
input sys_clk,
input ADC_SDAT,
output ADC_CS_N,
output ADC_SADDR,
output ADC_SCLK
);
wire [8*32-1:0] adc_channels;
imu imu(
.reset_n(1'b1),
.spi_clk(spi_clk),
.sys_clk(sys_clk),
.sda(),
.scl(),
.adc_channels(adc_channels),
.ADC_SDAT(ADC_SDAT),
.ADC_CS_N(ADC_CS_N),
.ADC_SADDR(ADC_SADDR),
.ADC_SCLK(ADC_SCLK)
);
always @(posedge sys_clk)
if (chipselect & read)
casex (addr)
4'b0000:
readdata <= adc_channels[1*32-1:0*32];
4'b0001:
readdata <= adc_channels[2*32-1:1*32];
4'b0010:
readdata <= adc_channels[3*32-1:2*32];
4'b0011:
readdata <= adc_channels[4*32-1:3*32];
4'b0100:
readdata <= adc_channels[5*32-1:4*32];
4'b0101:
readdata <= adc_channels[6*32-1:5*32];
4'b0110:
readdata <= adc_channels[7*32-1:6*32];
4'b0111:
readdata <= adc_channels[8*32-1:7*32];
default:
readdata <= 32'd0;
endcase
endmodule
|
// Motion in perpendicular plane will cause variations on the specific axis, note that this represent motion AROUND a specific axis
// z-axis = side to side (short)
// y-axis = side to side (long)
// x-axis = vertical
/*
---------------------------------|----------------------------------
---------------------------------|- Y - Axis -----------------------
---------------------------------|----------------------------------
---------------------------------|----------------------------------
---------------------=========================----------------------
---------------------|| ||----------------------
---------------------|| ||______________________
---------------------|| DE0-Nano ||--- X - Axis ---------
---------------------|| ||----------------------
---------------------|| ||----------------------
---------------------=========================----------------------
---------------------------------|----------------------------------
---------------------------------|----------------------------------
---------------------------------|----------------------------------
---------------------------------|----------------------------------
*/
module imu(
input reset_n,
input spi_clk,
input sys_clk,
inout sda,
output scl,
output [8*32-1:0] adc_channels,
//////////// ADC //////////
input ADC_SDAT,
output ADC_CS_N,
output ADC_SADDR,
output ADC_SCLK
);
///=======================================================
// REG/WIRE declarations
//=======================================================
wire [11:0] ADC_12_bit_channel_0;
wire [11:0] ADC_12_bit_channel_1;
wire [11:0] ADC_12_bit_channel_2;
wire [11:0] ADC_12_bit_channel_3;
wire [11:0] ADC_12_bit_channel_4;
wire [11:0] ADC_12_bit_channel_5;
wire [11:0] ADC_12_bit_channel_6;
wire [11:0] ADC_12_bit_channel_7;
/* The GPIO 2 pin layout
1 0
3 2
5 4
7 6
9 8
11 10
ADC5 12
ADC7 ADC7
ADC2 ADC3
ADC0 ADC4
GND ADC1
*/
// ADC connections, on chip
ADC_CTRL adc_controller_8_channels (
.iRST(!reset_n),
.iCLK(spi_clk),
.iCLK_n(!spi_clk),
.iGO(1'b1),
\t\t\t\t\t\t
.oDIN(ADC_SADDR),
.oCS_n(ADC_CS_N),
.oSCLK(ADC_SCLK),
.iDOUT(ADC_SDAT),
\t\t\t\t\t\t
.oADC_12_bit_channel_0(ADC_12_bit_channel_0),
.oADC_12_bit_channel_1(ADC_12_bit_channel_1),
.oADC_12_bit_channel_2(ADC_12_bit_channel_2),
.oADC_12_bit_channel_3(ADC_12_bit_channel_3),
.oADC_12_bit_channel_4(ADC_12_bit_channel_4),
.oADC_12_bit_channel_5(ADC_12_bit_channel_5),
.oADC_12_bit_channel_6(ADC_12_bit_channel_6),
.oADC_12_bit_channel_7(ADC_12_bit_channel_7)
);
assign adc_channels[1*32-1:0*32] = {20'd0, ADC_12_bit_channel_0};
assign adc_channels[2*32-1:1*32] = {20'd0, ADC_12_bit_channel_1};
assign adc_channels[3*32-1:2*32] = {20'd0, ADC_12_bit_channel_2};
assign adc_channels[4*32-1:3*32] = {20'd0, ADC_12_bit_channel_3};
assign adc_channels[5*32-1:4*32] = {20'd0, ADC_12_bit_channel_4};
assign adc_channels[6*32-1:5*32] = {20'd0, ADC_12_bit_channel_5};
assign adc_channels[7*32-1:6*32] = {20'd0, ADC_12_bit_channel_6};
assign adc_channels[8*32-1:7*32] = {20'd0, ADC_12_bit_channel_7};
\t
endmodule
|
// This file defines the parameters for the motor controller
// # of dead time cycles to ensure H-bridge does not short
// 75 cycles = 1.5 microseconds
`define DEAD_TIME 75
`define PERIOD_LENGTH 16
|
// This is the motor_controller for each H-bridge circuit
// Direction and on/off can be specified, as well as duty cycle
`include "defines.v"
module motor_controller (input clk, input dir, input on, input [15:0] period, input [15:0] duty_cycle, output [3:0] out);
reg [`PERIOD_LENGTH-1:0] duty_counter = 0;
reg dir_reg;
always @(posedge clk)
begin
if (duty_counter == period)
duty_counter <= 0;
else
duty_counter <= duty_counter + 1;
dir_reg <= (on && duty_counter < duty_cycle) ? ~dir : dir;
end
motor_internal mi(clk, dir_reg, on, out);
endmodule
module motor_internal (input clk, input dir, input on, output reg [3:0] out);
reg [3:0] out_reg;
reg [9:0] dead_time_counter = `DEAD_TIME;
reg [1:0] prev_in = 2\'b00;
always @(posedge clk)
begin
if ({dir, on} != prev_in)
dead_time_counter <= 10\'d0;
if (dead_time_counter != `DEAD_TIME)
dead_time_counter <= dead_time_counter + 10\'d1;
casex ({dir, on})
2\'b00: out_reg <= 4\'b0000;
2\'b10: out_reg <= 4\'b1010;
2\'b11: out_reg <= 4\'b1001;
2\'b01: out_reg <= 4\'b0110;
endcase
prev_in <= {dir, on};
out <= (dead_time_counter != `DEAD_TIME) ? 4\'d0 : out_reg;
end
endmodule
|
// megafunction wizard: %FIFO%\r
// GENERATION: STANDARD\r
// VERSION: WM1.0\r
// MODULE: dcfifo \r
\r
// ============================================================\r
// File Name: gsensor_fifo.v\r
// Megafunction Name(s):\r
// \t\t\tdcfifo\r
//\r
// Simulation Library Files(s):\r
// \t\t\taltera_mf\r
// ============================================================\r
// ************************************************************\r
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
//\r
// 10.1 Build 153 11/29/2010 SJ Full Version\r
// ************************************************************\r
\r
\r
//Copyright (C) 1991-2010 Altera Corporation\r
//Your use of Altera Corporation\'s design tools, logic functions \r
//and other software and tools, and its AMPP partner logic \r
//functions, and any output files from any of the foregoing \r
//(including device programming or simulation files), and any \r
//associated documentation or information are expressly subject \r
//to the terms and conditions of the Altera Program License \r
//Subscription Agreement, Altera MegaCore Function License \r
//Agreement, or other applicable license agreement, including, \r
//without limitation, that your use is for the sole purpose of \r
//programming logic devices manufactured by Altera and sold by \r
//Altera or its authorized distributors. Please refer to the \r
//applicable agreement for further details.\r
\r
\r
// synopsys translate_off\r
`timescale 1 ps / 1 ps\r
// synopsys translate_on\r
module gsensor_fifo (\r
\taclr,\r
\tdata,\r
\trdclk,\r
\trdreq,\r
\twrclk,\r
\twrreq,\r
\tq,\r
\trdempty,\r
\trdusedw,\r
\twrfull,\r
\twrusedw);\r
\r
\tinput\t aclr;\r
\tinput\t[7:0] data;\r
\tinput\t rdclk;\r
\tinput\t rdreq;\r
\tinput\t wrclk;\r
\tinput\t wrreq;\r
\toutput\t[7:0] q;\r
\toutput\t rdempty;\r
\toutput\t[3:0] rdusedw;\r
\toutput\t wrfull;\r
\toutput\t[3:0] wrusedw;\r
`ifndef ALTERA_RESERVED_QIS\r
// synopsys translate_off\r
`endif\r
\ttri0\t aclr;\r
`ifndef ALTERA_RESERVED_QIS\r
// synopsys translate_on\r
`endif\r
\r
\twire sub_wire0;\r
\twire [7:0] sub_wire1;\r
\twire sub_wire2;\r
\twire [3:0] sub_wire3;\r
\twire [3:0] sub_wire4;\r
\twire wrfull = sub_wire0;\r
\twire [7:0] q = sub_wire1[7:0];\r
\twire rdempty = sub_wire2;\r
\twire [3:0] wrusedw = sub_wire3[3:0];\r
\twire [3:0] rdusedw = sub_wire4[3:0];\r
\r
\tdcfifo\tdcfifo_component (\r
\t\t\t\t.rdclk (rdclk),\r
\t\t\t\t.wrclk (wrclk),\r
\t\t\t\t.wrreq (wrreq),\r
\t\t\t\t.aclr (aclr),\r
\t\t\t\t.data (data),\r
\t\t\t\t.rdreq (rdreq),\r
\t\t\t\t.wrfull (sub_wire0),\r
\t\t\t\t.q (sub_wire1),\r
\t\t\t\t.rdempty (sub_wire2),\r
\t\t\t\t.wrusedw (sub_wire3),\r
\t\t\t\t.rdusedw (sub_wire4),\r
\t\t\t\t.rdfull (),\r
\t\t\t\t.wrempty ());\r
\tdefparam\r
\t\tdcfifo_component.clocks_are_synchronized = "FALSE",\r
\t\tdcfifo_component.intended_device_family = "Cyclone IV E",\r
\t\tdcfifo_component.lpm_numwords = 16,\r
\t\tdcfifo_component.lpm_showahead = "ON",\r
\t\tdcfifo_component.lpm_type = "dcfifo",\r
\t\tdcfifo_component.lpm_width = 8,\r
\t\tdcfifo_component.lpm_widthu = 4,\r
\t\tdcfifo_component.overflow_checking = "ON",\r
\t\tdcfifo_component.underflow_checking = "ON",\r
\t\tdcfifo_component.use_eab = "OFF",\r
\t\tdcfifo_component.write_aclr_synch = "OFF";\r
\r
\r
endmodule\r
\r
// ============================================================\r
// CNX file retrieval info\r
// ============================================================\r
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"\r
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"\r
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"\r
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"\r
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"\r
// Retrieval info: PRIVATE: Clock NUMERIC "4"\r
// Retrieval info: PRIVATE: Depth NUMERIC "16"\r
// Retrieval info: PRIVATE: Empty NUMERIC "1"\r
// Retrieval info: PRIVATE: Full NUMERIC "1"\r
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"\r
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "1"\r
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"\r
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"\r
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"\r
// Retrieval info: PRIVATE: Optimize NUMERIC "0"\r
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"\r
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"\r
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"\r
// Retrieval info: PRIVATE: UsedW NUMERIC "1"\r
// Retrieval info: PRIVATE: Width NUMERIC "8"\r
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"\r
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"\r
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"\r
// Retrieval info: PRIVATE: output_width NUMERIC "8"\r
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"\r
// Retrieval info: PRIVATE: rsFull NUMERIC "0"\r
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"\r
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"\r
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"\r
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"\r
// Retrieval info: PRIVATE: wsFull NUMERIC "1"\r
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"\r
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"\r
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"\r
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"\r
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"\r
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"\r
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"\r
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"\r
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"\r
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"\r
// Retrieval info: CONSTANT: USE_EAB STRING "OFF"\r
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"\r
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"\r
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"\r
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"\r
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"\r
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"\r
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"\r
// Retrieval info: USED_PORT: rdusedw 0 0 4 0 OUTPUT NODEFVAL "rdusedw[3..0]"\r
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"\r
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"\r
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"\r
// Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL "wrusedw[3..0]"\r
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0\r
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0\r
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0\r
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0\r
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0\r
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0\r
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0\r
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0\r
// Retrieval info: CONNECT: rdusedw 0 0 4 0 @rdusedw 0 0 4 0\r
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0\r
// Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0\r
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo.v TRUE\r
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo.inc FALSE\r
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo.cmp FALSE\r
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo.bsf FALSE\r
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo_inst.v FALSE\r
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo_bb.v TRUE\r
// Retrieval info: LIB_FILE: altera_mf\r
|
/*****************************************************************************
* *
* Module: Altera_UP_Avalon_RS232 *
* Description: *
* This module reads and writes data to the RS232 connector on Altera's *
* DE1 and DE2 Development and Education Boards. *
* *
*****************************************************************************/
/* Settings */
`define USE_DATA_WIDTH_8 1
/* End settings */
module Altera_UP_Avalon_RS232 (
\t// Inputs
\tclk,
\treset,
\t
\taddress,
\tchipselect,
\tbyteenable,
\tread,
\twrite,
\twritedata,
\tUART_RXD,
\t// Bidirectionals
\t// Outputs
\tirq,
\treaddata,
\tUART_TXD
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter BAUD_COUNTER_WIDTH\t= 9;
parameter BAUD_TICK_INCREMENT\t= 9'd1;
parameter BAUD_TICK_COUNT\t\t= 9'd433;
parameter HALF_BAUD_TICK_COUNT\t= 9'd216;
parameter TOTAL_DATA_WIDTH\t\t= 10;
parameter DATA_WIDTH\t\t\t= 8;
parameter ODD_PARITY\t\t\t= 1'b0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input\t\t\t\tclk;
input\t\t\t\treset;
input\t\t\t\taddress;
input\t\t\t\tchipselect;
input\t\t[3:0]\tbyteenable;
input\t\t\t\tread;
input\t\t\t\twrite;
input\t\t[31:0]\twritedata;
input\t\t\t\tUART_RXD;
// Bidirectionals
// Outputs
output\treg\t\t\tirq;
output\treg\t[31:0]\treaddata;
output\t\t\t\tUART_TXD;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire\t\t\t\tread_fifo_read_en;
wire\t\t[7:0]\tread_available;
`ifdef USE_PARITY
wire\t\t[DATA_WIDTH:0]\t\t\tread_data;
`else
wire\t\t[(DATA_WIDTH - 1):0]\tread_data;
`endif
wire\t\t\t\tparity_error;
wire\t\t\t\twrite_data_parity;
wire\t\t[7:0]\twrite_space;
// Internal Registers
reg\t\t\t\t\tread_interrupt_en;
reg\t\t\t\t\twrite_interrupt_en;
reg\t\t\t\t\tread_interrupt;
reg\t\t\t\t\twrite_interrupt;
reg\t\t\t\t\twrite_fifo_write_en;
reg\t\t\t[(DATA_WIDTH - 1):0]\tdata_to_uart;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\tirq <= 1'b0;
\telse
\t\tirq <= write_interrupt | read_interrupt;
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\treaddata <= 32'h00000000;
\telse if (chipselect == 1'b1)
\tbegin
\t\tif (address == 1'b0)
\t\t\treaddata <=
\t\t\t\t{8'h00,
\t\t\t\t read_available,
\t\t\t\t 6'h00,
\t\t\t\t parity_error,
`ifdef USE_DATA_WIDTH_7
\t\t\t\t 2'h0,
`endif
`ifdef USE_DATA_WIDTH_8
\t\t\t\t 1'b0,
`endif
\t\t\t\t read_data[(DATA_WIDTH - 1):0]};
\t\telse
\t\t\treaddata <=
\t\t\t\t{8'h00,
\t\t\t\t write_space,
\t\t\t\t 6'h00,
\t\t\t\t write_interrupt,
\t\t\t\t read_interrupt,
\t\t\t\t 6'h00,
\t\t\t\t write_interrupt_en,
\t\t\t\t read_interrupt_en};
\tend
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\tread_interrupt_en <= 1'b0;
\telse if ((chipselect == 1'b1) && (write == 1'b1) && (address == 1'b1) && (byteenable[0] == 1'b1))
\t\tread_interrupt_en <= writedata[0];
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\twrite_interrupt_en <= 1'b0;
\telse if ((chipselect == 1'b1) && (write == 1'b1) && (address == 1'b1) && (byteenable[0] == 1'b1))
\t\twrite_interrupt_en <= writedata[1];
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\tread_interrupt <= 1'b0;
\telse if (read_interrupt_en == 1'b0)
\t\tread_interrupt <= 1'b0;
\telse
\t\tread_interrupt <= (|read_available);
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\twrite_interrupt <= 1'b0;
\telse if (write_interrupt_en == 1'b0)
\t\twrite_interrupt <= 1'b0;
\telse
\t\twrite_interrupt <= (&(write_space[6:5]) | write_space[7]);
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\twrite_fifo_write_en <= 1'b0;
\telse
\t\twrite_fifo_write_en <=
\t\t\tchipselect & write & ~address & byteenable[0];
end
always @(posedge clk)
begin
\tif (reset == 1'b1)
\t\tdata_to_uart <= 1'b0;
\telse
\t\tdata_to_uart <= writedata[(DATA_WIDTH - 1):0];
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
`ifdef USE_PARITY
assign parity_error = (read_available != 8'h00) ?
\t\t\t\t\t\t((^(read_data[DATA_WIDTH:0])) ^ ODD_PARITY) :
\t\t\t\t\t\t1'b0;
`else
assign parity_error = 1'b0;
`endif
assign read_fifo_read_en = chipselect & read & ~address & byteenable[0];
assign write_data_parity = (^(data_to_uart)) ^ ODD_PARITY;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_RS232_In_Deserializer RS232_In_Deserializer (
\t// Inputs
\t.clk\t\t\t\t\t(clk),
\t.reset\t\t\t\t\t(reset),
\t
\t.serial_data_in\t\t\t(UART_RXD),
\t.receive_data_en\t\t(read_fifo_read_en),
\t// Bidirectionals
\t// Outputs
\t.fifo_read_available\t(read_available),
\t.received_data\t\t\t(read_data)
);
defparam
\tRS232_In_Deserializer.BAUD_COUNTER_WIDTH\t= BAUD_COUNTER_WIDTH,
\tRS232_In_Deserializer.BAUD_TICK_INCREMENT\t= BAUD_TICK_INCREMENT,
\tRS232_In_Deserializer.BAUD_TICK_COUNT\t\t= BAUD_TICK_COUNT,
\tRS232_In_Deserializer.HALF_BAUD_TICK_COUNT\t= HALF_BAUD_TICK_COUNT,
\tRS232_In_Deserializer.TOTAL_DATA_WIDTH\t\t= TOTAL_DATA_WIDTH,
`ifdef USE_PARITY
\tRS232_In_Deserializer.DATA_WIDTH\t\t\t= (DATA_WIDTH + 1);
`else
\tRS232_In_Deserializer.DATA_WIDTH\t\t\t= DATA_WIDTH;
`endif
Altera_UP_RS232_Out_Serializer RS232_Out_Serializer (
\t// Inputs
\t.clk\t\t\t\t\t(clk),
\t.reset\t\t\t\t\t(reset),
\t
`ifdef USE_PARITY
\t.transmit_data\t\t\t({write_data_parity, data_to_uart}),
`else
\t.transmit_data\t\t\t(data_to_uart),
`endif
\t.transmit_data_en\t\t(write_fifo_write_en),
\t// Bidirectionals
\t// Outputs
\t.fifo_write_space\t\t(write_space),
\t.serial_data_out\t\t(UART_TXD)
);
defparam
\tRS232_Out_Serializer.BAUD_COUNTER_WIDTH\t\t= BAUD_COUNTER_WIDTH,
\tRS232_Out_Serializer.BAUD_TICK_INCREMENT\t= BAUD_TICK_INCREMENT,
\tRS232_Out_Serializer.BAUD_TICK_COUNT\t\t= BAUD_TICK_COUNT,
\tRS232_Out_Serializer.HALF_BAUD_TICK_COUNT\t= HALF_BAUD_TICK_COUNT,
\tRS232_Out_Serializer.TOTAL_DATA_WIDTH\t\t= TOTAL_DATA_WIDTH,
`ifdef USE_PARITY
\tRS232_Out_Serializer.DATA_WIDTH\t\t\t\t= (DATA_WIDTH + 1);
`else
\tRS232_Out_Serializer.DATA_WIDTH\t\t\t\t= DATA_WIDTH;
`endif
endmodule
|
// clock polarity (CPOL) = 1 and clock phase (CPHA) = 1
// http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
// http://www.byteparadigm.com/kb/article/AA-00255/22/Introduction-to-SPI-and-IC-protocols.html
// http://read.pudn.com/downloads132/doc/561635/123.doc
module SPI_3WIRE(
\tclk,
\treset_n,
\t
\t//
\tCMD_START,
\tCMD_DONE,
\tREG_ADDR,
\tREG_RW,
\tREG_RX_NUM,
\tFIFO_CLEAR,
\tFIFO_WRITE,
\tFIFO_WRITEDATA,
\tFIFO_READ_ACK,
\tFIFO_READDATA,
\t
\t//
\tSPI_CS_n,
\tSPI_SCLK,
\tSPI_SDIO
);
parameter DIVIDER = 10;
parameter CPOL = 1;
input\t\t\t\t\tclk;
input\t\t\t\t\treset_n;
input\t\t\t\t\tCMD_START;
output\t\t\t\tCMD_DONE;
input\t\t[5:0]\t\tREG_ADDR;
input\t\t\t\t\tREG_RW; // 1: read, 0:write
input\t\t[3:0]\t\tREG_RX_NUM; // 16 max, no = value+1
input\t\t\t\t\tFIFO_CLEAR;
input\t\t[7:0]\t\tFIFO_WRITE;
input\t\t[7:0]\t\tFIFO_WRITEDATA;
input\t\t[7:0]\t\tFIFO_READ_ACK;
output\t[7:0]\t\tFIFO_READDATA;
output\t\t\t\tSPI_CS_n;
output\t\t\t\tSPI_SCLK;
inout\t\t\t\t\tSPI_SDIO;
///////////////////////////////////
// generate spi clock
reg spi_clk;
reg [7:0] clk_cnt;
always @ (posedge clk or negedge reset_n)
begin
\tif (~reset_n)
\tbegin
\t\tclk_cnt <= 0;
\t\tspi_clk <= 1;
\tend
\telse
\tbegin
\t\tif (clk_cnt > DIVIDER)
\t\t\tbegin
\t\t\tspi_clk <= ~spi_clk;
\t\t\tclk_cnt <= 0;
\t\t\tend
\t\telse
\t\t\tclk_cnt <= clk_cnt + 1;
\tend
end
///////////////////////////////
// tx fifo
reg fifo_tx_rdreq;
wire [7:0]\tfifo_tx_q;
wire fifo_tx_empty;
wire [7:0]\tfifo_tx_wrusedw;
gsensor_fifo gsensor_fifo_tx(
\t.aclr(FIFO_CLEAR),
\t.data(FIFO_WRITEDATA),
\t.rdclk(spi_clk),
\t.rdreq(fifo_tx_rdreq),
\t.wrclk(clk),
\t.wrreq(FIFO_WRITE),
\t.q(fifo_tx_q),
\t.rdempty(fifo_tx_empty),
\t.rdusedw(),
\t.wrfull(),
\t.wrusedw(fifo_tx_wrusedw)
\t);
\t
///////////////////////////////
// rx fifo
reg [7:0]\tfifo_rx_data;
reg \t\t\tfifo_rx_wrreq;
gsensor_fifo gsensor_fifo_rx(
\t.aclr(FIFO_CLEAR),
\t.data(fifo_rx_data),
\t.rdclk(clk),
\t.rdreq(FIFO_READ_ACK),
\t.wrclk(spi_clk),
\t.wrreq(fifo_rx_wrreq),
\t.q(FIFO_READDATA),
\t.rdempty(),
\t.rdusedw(),
\t.wrfull(),
\t.wrusedw()
\t);
\t
///////////////////////////////\t
// detect START edge
reg pre_CMD_START;
always @ (posedge spi_clk or negedge reset_n)
begin
\tif (~reset_n)
\t\tpre_CMD_START <= 1'b1;
\telse
\t\tpre_CMD_START <= CMD_START;
end
//////////////////////////////////
// state
`define ST_IDLE\t\t\t3'd0
`define ST_START\t\t\t3'd1
`define ST_RW_MB_ADDR\t3'd2
`define ST_DATA\t\t\t3'd3
`define ST_END\t\t\t\t3'd4
`define ST_DONE\t\t\t3'd5
reg\t[2:0]\tstate;
reg [2:0] state_at_falling;
reg\t\t\t reg_write;
reg\t[5:0] rw_reg_byte_num;
reg\t[5:0] byte_cnt;
reg\t[2:0] bit_index;
always @ (posedge spi_clk or negedge reset_n)
begin
\tif (~reset_n)
\t\tstate <= `ST_IDLE;
\telse if (~pre_CMD_START & CMD_START)
\tbegin
\t\tstate <= `ST_START;
\t\treg_write <= ~REG_RW;
\t\trw_reg_byte_num <= (REG_RW)?(REG_RX_NUM + 1):(fifo_tx_wrusedw);
\tend
\telse
\tbegin
\t\tcase (state)
\t\t\t`ST_START:
\t\t\t\t\tbegin
\t\t\t\t\t\tbit_index <= 7;
\t\t\t\t\t\tstate <= `ST_RW_MB_ADDR;\t\t\t\t\t
\t\t\t\t\tend
\t\t\t`ST_RW_MB_ADDR:
\t\t\t\t\tbegin
\t\t\t\t\t\tif (bit_index == 0)
\t\t\t\t\t\tbegin
\t\t\t\t\t\t\tstate <= `ST_DATA;
\t\t\t\t\t\t\tbyte_cnt <= rw_reg_byte_num-1;
\t\t\t\t\t\tend
\t\t\t\t\t\t//
\t\t\t\t\t\tbit_index <= bit_index - 1;
\t\t\t\t\tend
\t\t\t`ST_DATA:
\t\t\t\t\tbegin
\t\t\t\t\t\tif (bit_index == 0)
\t\t\t\t\t\tbegin
\t\t\t\t\t\t\tif (byte_cnt == 0)
\t\t\t\t\t\t\t\tstate <= `ST_END;
\t\t\t\t\t\t\telse
\t\t\t\t\t\t\t\tbyte_cnt <= byte_cnt - 1;
\t\t\t\t\t\tend
\t\t\t\t\t\t//
\t\t\t\t\t\tbit_index <= bit_index - 1;\t
\t\t\t\t\tend
\t\t\t`ST_END:
\t\t\t\t\tbegin
\t\t\t\t\t\tstate <= `ST_DONE;
\t\t\t\t\tend
\t\t\t`ST_DONE:
\t\t\t\t\tbegin
\t\t\t\t\t\tstate <= `ST_DONE;
\t\t\t\t\tend
\t\t\tdefault:
\t\t\t\t\tstate <= `ST_IDLE;
\t\t\t
\t endcase
\t\t\t\t\t
\tend
\t
end
//=========================
// get tx_byte from fifo
reg\t[7:0]\t tx_byte;
wire read_fifo_first;
wire read_fifo_other;
wire mb_flag;
assign read_fifo_first = ((state == `ST_RW_MB_ADDR) && (bit_index == 0) && reg_write)?1'b1:1'b0;
//assign read_fifo_1 = ((state == `ST_DATA) && (bit_index == 0) && reg_write)?1'b1:1'b0;
assign read_fifo_other = ((state == `ST_DATA) && (bit_index == 0) && reg_write && (byte_cnt != 0))?1'b1:1'b0;
assign mb_flag = (rw_reg_byte_num == 1)?1'b0:1'b1;
always @ (posedge spi_clk or negedge reset_n)
begin
\tif (~reset_n)
\t\tfifo_tx_rdreq <= 1'b0;
\telse if (state == `ST_START)
\tbegin
//\t\ttx_byte <= {~reg_write, (reg_write)?((fifo_tx_wrusedw==1)?1'b0:1'b1):((REG_RX_NUM==0)?1'b0:1'b1), REG_ADDR};
\t\ttx_byte <= {~reg_write, mb_flag, REG_ADDR};
\t\tfifo_tx_rdreq <= 1'b0;
\tend
\telse if (read_fifo_first | read_fifo_other)
\tbegin
\t\ttx_byte <= fifo_tx_q;
\t\tfifo_tx_rdreq <= 1'b1;
\tend
\telse
\t\tfifo_tx_rdreq <= 1'b0;
end
////////////////////////////////
// serial tx data at falling edge
reg tx_bit;
always @ (negedge spi_clk)
begin
\ttx_bit <= tx_byte[bit_index];
end
////////////////////////////////
// capture serail rx data at rising edge
reg\t[7:0] rx_byte;
always @ (posedge spi_clk or negedge reset_n)
begin
\tif (~reset_n)
\t\tfifo_rx_wrreq <= 1'b0;
\telse if (~data_out)
\tbegin
\t\tif (bit_index == 0)
\t\tbegin
\t\t\tfifo_rx_data <= {rx_byte[7:1], SPI_SDIO};
\t\t\trx_byte <= 0;
\t\t\tfifo_rx_wrreq <= 1'b1;
\t\tend
\t\telse
\t\tbegin
\t\t\trx_byte[bit_index] <= SPI_SDIO;
\t\t\tfifo_rx_wrreq <= 1'b0;
\t\tend
\t\t
\tend
\telse
\t\tfifo_rx_wrreq <= 1'b0;
end
////////////////////////////////
// phase at falling edge
always @ (negedge spi_clk or negedge reset_n)
begin
\tif (~reset_n)
\t\tstate_at_falling <= `ST_IDLE;
\telse\t
\t\tstate_at_falling <= state;
end
////////////////////////////////
// combiniation
wire data_out;
assign data_out = ((state_at_falling == `ST_RW_MB_ADDR) || (state_at_falling == `ST_DATA && reg_write))?1'b1:1'b0;
assign SPI_CS_n = (state_at_falling == `ST_IDLE || state_at_falling == `ST_DONE)?1'b1:1'b0;
assign SPI_SCLK = (~SPI_CS_n && (state != `ST_START) && (state != `ST_END))?spi_clk:1'b1;
assign SPI_SDIO = (~SPI_CS_n & data_out)?(tx_bit?1'b1:1'b0):1'bz;
assign CMD_DONE = (state == `ST_DONE)?1'b1:1'b0;
///////////////////////////////
endmodule
|
// Power management Avalon slave
module power_management_slave (
input clk,
input chipselect,
input write,
input read,
input [31:0] writedata,
input data,
output reg [31:0] readdata,
output kill_sw,
output [2:0] mux,
output error
);
reg start = 1'b0;
always @(posedge clk)
if (chipselect)
if (write)
begin
start = writedata[0];
end
else if (read)
begin
readdata[2:0] = mux;
end
power_management pm_inst (
.kill_sw(kill_sw),
.sel(mux),
.data(data),
.ack(chipselect && read),
.start(start),
.clk(clk),
.error(error)
);
endmodule
|
// Global disable
//
// If any of the shutdown inputs goes high, all GPIO outputs will be set to 0
module global_disable #(
parameter NUM_IN = 1,
parameter NUM_IOS = 1
) (
input clk,
input [NUM_IN-1:0] shutdown,
input [NUM_IOS-1:0] gpio_in,
input [NUM_IOS-1:0] gpio_out_default,
output reg [NUM_IOS-1:0] gpio_out
);
always @(posedge clk)
if (|shutdown)
// Set all GPIO outputs to low
gpio_out = gpio_out_default;
else
// Set all GPIO outputs to the input
gpio_out = gpio_in;
endmodule
|
module TERASIC_SPI_3WIRE(\r
\tclk,\r
\treset_n,\r
\t\r
\t//\r
\ts_chipselect,\r
\ts_address,\r
\ts_write,\r
\ts_writedata,\r
\ts_read,\r
\ts_readdata,\r
\t\r
\t// condui\r
\tSPI_CS_n,\r
\tSPI_SCLK,\r
\tSPI_SDIO\r
);\r
\r
\r
input\t\t\t\t\t\tclk;\r
input\t\t\t\t\t\treset_n;\r
\r
// avalon slave\r
input\t\t\t\t\t\ts_chipselect;\r
input\t[3:0]\t\t\t\ts_address;\r
input\t\t\t\t\t\ts_write;\r
input\t\t[7:0]\t\t\ts_writedata;\r
input\t\t\t\t\t\ts_read;\r
output reg\t[7:0]\t\ts_readdata;\r
\r
output\t\t\t\t\tSPI_CS_n;\r
output\t\t\t\t\tSPI_SCLK;\r
inout \t\t\t\t\tSPI_SDIO;\r
\r
//////////////////////////////////////\r
`define REG_DATA\t\t\t\t0 // r/w\r
`define REG_CTRL_STATUS\t\t1 // r/w\r
`define REG_INDEX\t\t\t\t2\t// w\r
`define REG_READ_NUM\t\t\t3\t// w\r
\r
\r
/////////////////////////////////////\r
always @ (posedge clk or negedge reset_n)\r
begin\r
\tif (~reset_n)\r
\tbegin\r
\t\tCMD_START <= 1'b0;\r
\t\tFIFO_CLEAR <= 1'b0;\r
\tend\r
\telse if (s_chipselect & s_read)\r
\tbegin\r
\t\tif (s_address == `REG_DATA)\r
\t\t\ts_readdata <= FIFO_READDATA;\r
\t\telse if (s_address == `REG_CTRL_STATUS)\r
\t\t\ts_readdata <= {7'h00, CMD_DONE};\r
\tend\r
\telse if (s_chipselect & s_write)\r
\tbegin\r
\t\tif (s_address == `REG_DATA)\r
\t\t\tFIFO_WRITEDATA <= s_writedata;\r
\t\telse if (s_address == `REG_CTRL_STATUS)\r
\t\t\t{FIFO_CLEAR, REG_RW, CMD_START} <= s_writedata[2:0];\r
\t\telse if (s_address == `REG_INDEX)\r
\t\t\tREG_ADDR <= s_writedata;\r
\t\telse if (s_address == `REG_READ_NUM)\r
\t\t\tREG_RX_NUM <= s_writedata;\r
\tend\r
end\r
\r
always @ (posedge clk or negedge reset_n)\r
begin\r
\tif (~reset_n)\r
\t\tFIFO_WRITE <= 1'b0;\r
\telse if (s_chipselect && s_write && (s_address == `REG_DATA))\r
\t\tFIFO_WRITE <= 1'b1;\r
\telse\r
\t\tFIFO_WRITE <= 1'b0;\r
end\r
\r
\r
\r
\r
/////////////////////////////////////\r
reg\tCMD_START;\r
wire\tCMD_DONE;\r
reg\t[7:0]\tREG_ADDR;\r
reg\t[7:0]\tREG_RX_NUM;\r
reg\t\t\tREG_RW;\r
reg\t\t\tFIFO_CLEAR;\r
reg\t\t\tFIFO_WRITE;\r
reg\t[7:0]\tFIFO_WRITEDATA;\r
wire\t\t\tFIFO_READ_ACK;\r
wire\t[7:0]\tFIFO_READDATA;\r
\r
\r
assign FIFO_READ_ACK = (s_chipselect && s_read && (s_address == `REG_DATA))?1'b1:1'b0;\r
//assign FIFO_WRITE = (s_chipselect && s_write && (s_address == `REG_DATA))?1'b1:1'b0;\r
\r
SPI_3WIRE SPI_3WIRE_inst(
\t.clk(clk),
\t.reset_n(reset_n),
\t
\t//
\t.CMD_START(CMD_START),
\t.CMD_DONE(CMD_DONE),
\t.REG_ADDR(REG_ADDR),
\t.REG_RW(REG_RW),
\t.REG_RX_NUM(REG_RX_NUM),
\t.FIFO_CLEAR(FIFO_CLEAR),
\t.FIFO_WRITE(FIFO_WRITE),
\t.FIFO_WRITEDATA(FIFO_WRITEDATA),
\t.FIFO_READ_ACK(FIFO_READ_ACK),
\t.FIFO_READDATA(FIFO_READDATA),
\t
\t//
\t.SPI_CS_n(SPI_CS_n),
\t.SPI_SCLK(SPI_SCLK),
\t.SPI_SDIO(SPI_SDIO)
);\r
\r
\r
\r
endmodule\r
\r
|
// Turn power on and rotate through mux outputs at about 100kHz
module power_management(input CLOCK_50, output [6:0]LED, inout [33:0]GPIO_1);
wire [2:0] voltage_mux;
wire kill_sw;
reg [11:0] counter = 12'd0;
assign kill_sw = 1'd1;
// kill switch
assign GPIO_1[33] = kill_sw;
// voltage muxes
assign {GPIO_1[29], GPIO_1[31], GPIO_1[25]} = voltage_mux;
assign voltage_mux = counter[11:9];
// LEDs
generate
genvar i;
for (i = 0; i < 7; i = i+1)
begin : led_loop
assign LED[i] = GPIO_1[27] && voltage_mux == i;
end
endgenerate
always @(posedge CLOCK_50)
counter = counter + 12'd1;
endmodule
|
module ADC_CTRL (
iRST,
iCLK,
iCLK_n,
iGO,
oDIN,
oCS_n,
oSCLK,
iDOUT,
oADC_12_bit_channel_0,
oADC_12_bit_channel_1,
oADC_12_bit_channel_2,
oADC_12_bit_channel_3,
oADC_12_bit_channel_4,
oADC_12_bit_channel_5,
oADC_12_bit_channel_6,
oADC_12_bit_channel_7
);
input iRST;
input iCLK;
input iCLK_n;
input iGO;
output oDIN;
output oCS_n;
output oSCLK;
input iDOUT;
output reg [11:0] oADC_12_bit_channel_0;
output reg [11:0] oADC_12_bit_channel_1;
output reg [11:0] oADC_12_bit_channel_2;
output reg [11:0] oADC_12_bit_channel_3;
output reg [11:0] oADC_12_bit_channel_4;
output reg [11:0] oADC_12_bit_channel_5;
output reg [11:0] oADC_12_bit_channel_6;
output reg [11:0] oADC_12_bit_channel_7;
reg [2:0] channel;
reg data;
reg go_en;
reg sclk;
reg [3:0] cont;
reg [3:0] m_cont;
reg [11:0] adc_data;
reg [31:0] adc_counter;
assign oCS_n = ~go_en;
assign oSCLK = (go_en)? iCLK:1;
assign oDIN = data;
always@( iCLK )//posedge iGO or posedge iRST)
begin
if(iRST)
go_en <= 0;
else
begin
if(iGO)
go_en <= 1;
end
end
always@(posedge iCLK or negedge go_en)
begin
if(!go_en)
cont <= 0;
else
begin
if(iCLK)
cont <= cont + 1;
end
end
always@(posedge iCLK_n)
begin
if(iCLK_n)
m_cont <= cont;
end
always@(posedge iCLK_n or negedge go_en)
begin
if(!go_en)
data <= 0;
else
begin
if(iCLK_n)
begin
if (cont == 2)
data <= channel[2];
else if (cont == 3)
data <= channel[1];
else if (cont == 4)
data <= channel[0];
else
data <= 0;
end
end
end
always@(posedge iCLK or negedge go_en)
begin
if(!go_en)
begin
adc_data <= 0;
end
else
if(iCLK)
begin
if (m_cont == 4)
adc_data[11] <= iDOUT;
else if (m_cont == 5)
adc_data[10] <= iDOUT;
else if (m_cont == 6)
adc_data[9] <= iDOUT;
else if (m_cont == 7)
adc_data[8] <= iDOUT;
else if (m_cont == 8)
adc_data[7] <= iDOUT;
else if (m_cont == 9)
adc_data[6] <= iDOUT;
else if (m_cont == 10)
adc_data[5] <= iDOUT;
else if (m_cont == 11)
adc_data[4] <= iDOUT;
else if (m_cont == 12)
adc_data[3] <= iDOUT;
else if (m_cont == 13)
adc_data[2] <= iDOUT;
else if (m_cont == 14)
adc_data[1] <= iDOUT;
else if (m_cont == 15)
adc_data[0] <= iDOUT;
else if (m_cont == 1)
begin
if ( adc_counter < 32'd20 )
begin
adc_counter <= adc_counter + 1'b1;
end
else
begin
if (channel == 3'd0)
oADC_12_bit_channel_0 <= adc_data;
else if (channel == 3'd1)
oADC_12_bit_channel_1 <= adc_data;
else if (channel == 3'd2)
oADC_12_bit_channel_2 <= adc_data;
else if (channel == 3'd3)
oADC_12_bit_channel_3 <= adc_data;
else if (channel == 3'd4)
oADC_12_bit_channel_4 <= adc_data;
else if (channel == 3'd5)
oADC_12_bit_channel_5 <= adc_data;
else if (channel == 3'd6)
oADC_12_bit_channel_6 <= adc_data;
else if (channel == 3'd7)
oADC_12_bit_channel_7 <= adc_data;
adc_counter <= 32'd0;
channel <= channel + 1'b1;
end
end
end
end
endmodule
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_parsedata_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_virtualdict_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_virtualdict_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_specialdict_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_parsedata_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_virtualdict_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_parsedata_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_virtualdict_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_virtualdict_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_parsedata_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_misc_plugin_init;
\t\t\tstardict_misc_plugin_on_mainwin_finish;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_tts_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_parsedata_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_netdict_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_tts_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
{
\tglobal:
\t\textern "C" {
\t\t\tstardict_plugin_init;
\t\t\tstardict_plugin_exit;
\t\t\tstardict_virtualdict_plugin_init;
\t\t};
\tlocal:
\t\t*;
};
|
module I2CTest(CLCK, SCL, SDA);\r
\r
//I2C\r
input CLCK;\r
input SCL;\r
inout SDA;\r
\r
parameter slaveaddress = 7'b1110010;\r
\r
//Sample registers to send to requesting device\r
reg[2:0] valuecnt = 3'b011; //Count of bytes to be sent, send read value twice\r
\r
//Synch SCL edge to the CPLD clock\r
reg [2:0] SCLSynch = 3'b000; \r
always @(posedge CLCK) \r
\tSCLSynch <= {SCLSynch[1:0], SCL};\r
\t\r
wire SCL_posedge = (SCLSynch[2:1] == 2'b01); \r
wire SCL_negedge = (SCLSynch[2:1] == 2'b10); \r
\r
//Synch SDA to the CPLD clock\r
reg [2:0] SDASynch = 3'b000;\r
always @(posedge CLCK) \r
\tSDASynch <= {SDASynch[1:0], SDA};\r
\t\r
wire SDA_synched = SDASynch[0] & SDASynch[1] & SDASynch[2];\r
\r
//Detect start and stop\r
reg start = 1'b0;\r
always @(negedge SDA)\r
\tstart = SCL;\r
\r
reg stop = 1'b0;\r
always @(posedge SDA)\r
\tstop = SCL;\r
\r
//Set cycle state \r
reg incycle = 1'b0;\r
always @(posedge start or posedge stop)\r
\tif (start)\r
\tbegin\r
\t\tif (incycle == 1'b0)\r
\t\t\tincycle = 1'b1;\r
\tend\r
\telse if (stop)\r
\tbegin\r
\t\tif (incycle == 1'b1)\r
\t\t\tincycle = 1'b0;\t\r
\tend\r
\t\r
//Address and incomming data handling\r
reg[7:0] bitcount = 0;\r
reg[6:0] address = 7'b0000000;\r
reg[7:0] datain = 8'b00000000;\r
reg rw = 1'b0;\r
reg addressmatch = 1'b0;\r
always @(posedge SCL_posedge or negedge incycle)\r
\tif (~incycle)\t\r
\tbegin\r
\t\t//Reset the bit counter at the end of a sequence\r
\t\tbitcount = 0;\r
\tend\r
\telse\r
begin\r
\t\tbitcount = bitcount + 1;\r
\t\t\r
\t //Get the address\r
\t\tif (bitcount < 8)\r
\t\t\taddress[7 - bitcount] = SDA_synched;\r
\t\t\r
\t\tif (bitcount == 8)\r
\t\tbegin\r
\t\t\trw = SDA_synched;\r
\t\t\taddressmatch = (slaveaddress == address) ? 1'b1 : 1'b0;\r
\t\tend\r
\t\t\t\r
\t\tif ((bitcount > 9) & (~rw))\r
\t\t\t//Receive data (currently only one byte)\r
\t\t\tdatain[17 - bitcount] = SDA_synched;\r
\tend\r
\t\r
//ACK's and out going data\r
reg sdadata = 1'bz; \r
reg [2:0] currvalue = \t0;\r
always @(posedge SCL_negedge) \r
\t//ACK's\r
\tif (((bitcount == 8) | ((bitcount == 17) & ~rw)) & (addressmatch))\r
\tbegin\r
\t\tsdadata = 1'b0;\r
\t\tcurrvalue = 0;\r
\tend\r
\t//Data\r
\telse if ((bitcount >= 9) & (rw) & (addressmatch) & (currvalue < valuecnt))\r
\tbegin\r
\t\t//Send Data \r
\t\tif (((bitcount - 9) - (currvalue * 9)) == 8)\r
\t\tbegin\r
\t\t\t//Release SDA so master can ACK/NAK\r
\t\t\tsdadata = 1'bz;\r
\t\t\tcurrvalue = currvalue + 1;\r
\t\tend\r
\t\telse sdadata = datain[7 - ((bitcount - 9) - (currvalue * 9))]; //Modify this to send actual data, currently echoing incomming data valuecnt times\r
\tend\r
\t//Nothing (cause nothing tastes like fresca)\r
\telse sdadata = 1'bz;\r
\t\r
assign SDA = sdadata;\r
\r
endmodule |
always @(negedge reset or posedge clk) begin
if (reset == 0) begin
d_out <= 16'h0000;
d_out_mem[resetcount] <= d_out;
laststoredvalue <= d_out;
end else begin
d_out <= d_out + 1'b1;
end
end
always @(bufreadaddr)
bufreadval = d_out_mem[bufreadaddr]; |
LIBAVFORMAT_$MAJOR {
global: *;
};
|
LIBAVFILTER_$MAJOR {
global: avfilter_*; av_*;
local: *;
};
|
LIBAVCODEC_$MAJOR {
global: *;
};
|
LIBSWSCALE_$MAJOR {
global: swscale_*; sws_*; ff_*;
local: *;
};
|
LIBPOSTPROC_$MAJOR {
global: postproc_*; pp_*;
local: *;
};
|
LIBAVDEVICE_$MAJOR {
global: avdevice_*;
local: *;
};
|
LIBAVUTIL_$MAJOR {
global: av_*; ff_*; avutil_*;
local: *;
};
|
LIBAVRESAMPLE_$MAJOR {
global: av*;
local: *;
};
|
LIBSWRESAMPLE_$MAJOR {
global: swr_*; ff_*; swresample_*;
local: *;
};
|
LIBAVFORMAT_$MAJOR {
global: av*;
#FIXME those are for ffserver
ff_inet_aton;
ff_socket_nonblock;
ffm_set_write_index;
ffm_read_write_index;
ffm_write_write_index;
ff_mpegts_parse_close;
ff_mpegts_parse_open;
ff_mpegts_parse_packet;
ff_rtsp_parse_line;
ff_rtp_get_local_rtp_port;
ff_rtp_get_local_rtcp_port;
ffio_open_dyn_packet_buf;
ffio_set_buf_size;
ffurl_close;
ffurl_open;
ffurl_read_complete;
ffurl_seek;
ffurl_size;
ffurl_write;
ffurl_protocol_next;
url_open;
url_close;
url_write;
url_get_max_packet_size;
#those are deprecated, remove on next bump
find_info_tag;
parse_date;
dump_format;
url_*;
ff_timefilter_destroy;
ff_timefilter_new;
ff_timefilter_update;
ff_timefilter_reset;
get_*;
put_*;
udp_set_remote_url;
udp_get_local_port;
init_checksum;
init_put_byte;
local: *;
};
|
LIBAVCODEC_$MAJOR {
global: av*;
audio_resample;
audio_resample_close;
#deprecated, remove after next bump
img_get_alpha_info;
dsputil_init;
ff_find_pix_fmt;
ff_framenum_to_drop_timecode;
ff_framenum_to_smtpe_timecode;
ff_raw_pix_fmt_tags;
ff_init_smtpe_timecode;
ff_fft*;
ff_mdct*;
ff_dct*;
ff_rdft*;
ff_prores_idct_put_10_sse2;
ff_simple_idct*;
ff_aanscales;
ff_faan*;
ff_mmx_idct;
ff_fdct*;
fdct_ifast;
j_rev_dct;
ff_mmxext_idct;
ff_idct_xvid*;
ff_jpeg_fdct*;
#XBMC's configure checks for ff_vdpau_vc1_decode_picture()
ff_vdpau_vc1_decode_picture;
ff_dnxhd_get_cid_table;
ff_dnxhd_cid_table;
local: *;
};
|
LIBAVFILTER_$MAJOR {
global: avfilter_*; av_*;
ff_default_query_formats;
local: *;
};
|
LIBSWSCALE_$MAJOR {
global: swscale_*; sws_*; ff_*;
local: *;
};
|
LIBPOSTPROC_$MAJOR {
global: postproc_*; pp_*;
local: *;
};
|
LIBAVUTIL_$MAJOR {
global: av*; ff_*;
local: *;
};
|
LIBAVDEVICE_$MAJOR {
global: avdevice_*;
local: *;
};
|
/* Decode Unit Testbench*/
`timescale 1ns / 100ps
`include "../decode_32.v"
module decode_test();
localparam\tMEM_SIZE =\t32;
/* Clocks */
reg clk;
always
\t#10 clk = ~ clk; //100MHz
/* Input signals to drive */
reg\t\t\treset;
reg\t\t\tstall;
reg\t[31:0]\tinsn;\t
reg\t[31:0]\tinsn_address;
//integer\t\tinsn_address;
reg\t[7:0]\tsysreg_data_input;
/* Output signals to observe*/
wire \t[4:0]\treg_select;
wire\t[4:0]\trsa;
wire\t[4:0]\trsb;
wire\t[4:0]\trd;
wire\t[20:0]\timm;
wire\t[3:0]\taluop;
wire\t\t\tjlnk;
wire\t\t\tpc_change_relative;
wire\t\t\tpc_change_absolute;
wire\t\t\tmem_read;
wire\t\t\tmem_write;
wire\t\t\tnri_flag;
wire\t[1:0]\tbranch_funct;
wire\t\t\tstall_output;
wire\t\t\tmemsync;
wire\t\t\tsyscall;
wire\t\t\tpermission_inc;
wire\t\t\tpermission_dec;
wire\t[7:0]\tsysreg_addr;
wire\t[7:0]\tsysreg_data;
wire\t[31:0]\tinsn_pc_output;
wire\t[30:0]\tcp_insn;
/* Memory Test Registers */
reg\t[31:0]\tinsn_mem\t[0:MEM_SIZE-1]; //1024 addresses, 2^10
decode_32 decode_ut(\t\t//Decode unit under test
\t.insn_in(insn),\t\t\t\t//Instruction Input
\t.reset_in(reset),\t\t\t//Reset line input (active low)
\t.clk_in(clk),\t\t\t\t//Clock input
\t.insn_pc_in(insn_address),\t\t\t//Current instruction PC Address
\t.stall_in(stall),\t\t\t//CCCP Leader... nah just a stall signal
\t.reg_select_out(reg_select),\t\t//What register bank the instruction wants to access
\t.rsa_out(rsa),\t\t\t\t//RSa address
\t.rsb_out(rsb),\t\t\t\t//RSb address
\t.rd_out(rd),\t\t\t\t//Rd address
\t.imm_out(imm),\t\t\t\t//Immediate value (if used)
\t.aluop_out(aluop),\t\t\t//What operation to tell the ALU to do
\t.jlnk_out(jlnk),\t\t\t//Saving the PC to $R4/RA?
\t.pc_change_rel_out(pc_change_relative),\t//PC Relative address change
\t.pc_change_abs_out(pc_change_absolute),\t//PC Absolute address change
\t.mem_read_out(mem_read),\t\t//Memory read access
\t.mem_write_out(mem_write),\t\t//Memory write access
\t.nri_flg_out(nri_flag),\t\t\t//Not a real instruction, flag
\t.branch_funct_out(branch_funct),\t//Branch code, determines if branch should be taken or not along with output
\t.stall_out(stall_output),\t\t\t//Send stall signal out
\t.memsync_out(memsync),\t\t\t//Sync memory signal
\t.syscall_out(syscall),\t\t\t//Instruction is system call
\t.pem_inc_req_out(permission_inc),\t\t//Permission increase request
\t.pem_dec_req_out(permission_dec),\t\t//Permission decrease request
\t.sysreg_addr_out(sysreg_addr),\t\t//System/Special purpose register address to access
\t.sysreg_data_out(sysreg_data),\t\t//Data to write to System/Special purpose register
\t.sysreg_data_in(sysreg_data_input),\t\t//Data read from System/Special purpose register
\t.insn_pc_out(insn_pc_output),\t\t\t//Output PC value (for debugging)
\t/*Co-Processor Connections*/
\t.cp_insn_out(cp_insn)\t\t\t//Output instruction to Co-Processor to decode
\t);
integer i;
integer count;
/* Initial Conditions */
initial begin
\t$dumpfile("decode.vcd");
\t$dumpvars(0,decode_test);
\t$readmemh("test_insn.txt", insn_mem); //Fill memory
\tfor( i = 0; i < MEM_SIZE; i = i + 1) begin
\t\t$display("Data read from insn_mem: %h | address: %h", insn_mem[i], i);
\t\t#10;
\tend
\t#100 //wait a bit before doing anything
\tclk\t\t\t\t\t\t<= 1\'b0;
\treset \t\t\t\t\t<= 1\'b0;\t//put into reset to start
\t#10\t//let the reset propagate
\tstall \t\t\t\t\t<= 1\'b0;\t\t
//\tinsn\t\t\t\t\t<= 32\'b0;
\tinsn_address \t\t\t<= 0;
\tsysreg_data_input \t\t<= 8\'b0;
\t#10
\treset\t\t\t\t\t<= 1\'b1;\t//and they\'re off!
\tcount\t\t\t\t\t<= 0;
/* Testing */
//always @(posedge clk) begin
\t#5
\tfor( insn_address = 0; insn_address <= MEM_SIZE; insn_address = insn_address + 1) begin
\t\t#20;
\t\tinsn\t<= insn_mem[insn_address];\t\t\t//get instruction from memory address
\t\t$display("Current Address: %h | Instruction: %h", insn_address, insn);
\tend
//end
\t$finish;
end
endmodule
|
/*
This file is part of Fusion-Core-ISA.
Fusion-Core-ISA is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Fusion-Core-ISA is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.
*/
module shift_right_32(
\tinput[31:0] a, //value to be shifted
\toutput[31:0] out //output
\t);
\t//shifts everything right by 1
\tassign out[0] = a[1];
\tassign out[1] = a[2];
\tassign out[2] = a[3];
\tassign out[3] = a[4];
\tassign out[4] = a[5];
\tassign out[5] = a[6];
\tassign out[6] = a[7];
\tassign out[7] = a[8];
\tassign out[8] = a[9];
\tassign out[9] = a[10];
\tassign out[10] = a[11];
\tassign out[11] = a[12];
\tassign out[12] = a[13];
\tassign out[13] = a[14];
\tassign out[14] = a[15];
\tassign out[15] = a[16];
\tassign out[16] = a[17];
\tassign out[17] = a[18];
\tassign out[18] = a[19];
\tassign out[19] = a[20];
\tassign out[20] = a[21];
\tassign out[21] = a[22];
\tassign out[22] = a[23];
\tassign out[23] = a[24];
\tassign out[24] = a[25];
\tassign out[25] = a[26];
\tassign out[26] = a[27];
\tassign out[27] = a[28];
\tassign out[28] = a[29];
\tassign out[29] = a[30];
\tassign out[30] = a[31];
\tassign out[31] = a[31];
endmodule
|
module General_Purpose_Regs(
\t/*Data*/
\tinput[31:0] d_in, //input data
\toutput[31:0] out_a, //register outputs
\toutput[31:0] out_b,
\t/*Address*/
\tinput[4:0] addr_a,
\tinput[4:0] addr_b,
\t
\t/*Control Lines*/
\tinput[1:0] file_sel, //register file select lines
\tinput rw, //rw == 1, then read; rw == 0, write
\tinput clk //clock for synchronous registers
\t);
\t/*Registers*/
\treg [3:0] gp_sel; //selection line for register files
\t/*Wires*/
\twire [31:0] w_out_a;
\twire [31:0] w_out_b;
\t
\t/*Instantiations of GP register files*/
RegisterFile GPRF0(
\t.in_reg(d_in), //only one input needed
\t.out_a(w_out_a),
\t.out_b(w_out_b),
\t.addr_a(addr_a), //used for input addresses
\t.addr_b(addr_b),
\t.rw(rw), //rw == 1, then read; rw == 0, write
\t.clk(clk), //clock for synchronous registers
\t.sel(gp_sel[0])
\t);
RegisterFile GPRF1(
\t.in_reg(d_in), //only one input needed
\t.out_a(w_out_a),
\t.out_b(w_out_b),
\t.addr_a(addr_a), //used for input addresses
\t.addr_b(addr_b),
\t.rw(rw), //rw == 1, then read; rw == 0, write
\t.clk(clk), //clock for synchronous registers
\t.sel(gp_sel[1])
\t);
RegisterFile GPRF2(
\t.in_reg(d_in), //only one input needed
\t.out_a(w_out_a),
\t.out_b(w_out_b),
\t.addr_a(addr_a), //used for input addresses
\t.addr_b(addr_b),
\t.rw(rw), //rw == 1, then read; rw == 0, write
\t.clk(clk), //clock for synchronous registers
\t.sel(gp_sel[2])
\t);
RegisterFile GPRF3(
\t.in_reg(d_in), //only one input needed
\t.out_a(w_out_a),
\t.out_b(w_out_b),
\t.addr_a(addr_a), //used for input addresses
\t.addr_b(addr_b),
\t.rw(rw), //rw == 1, then read; rw == 0, write
\t.clk(clk), //clock for synchronous registers
\t.sel(gp_sel[3])
\t);
initial
\tbegin
\t\t gp_sel <= 4'b1111; //no register file is selected at initialization
\tend
//select is active low
always@(*)
begin
\tcase(file_sel)
\t\t2'b00: gp_sel <= 4'b1110;
\t\t2'b01: gp_sel <= 4'b1101;
\t\t2'b10: gp_sel <= 4'b1011;
\t\t2'b11: gp_sel <= 4'b0111;
\tendcase
end
assign out_a = w_out_a;
assign out_b = w_out_b;
endmodule
|
/*
This file is part of Fusion-Core-ISA.
Fusion-Core-ISA is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Fusion-Core-ISA is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.
*/
module adder_1b(
\tinput a,
\tinput b,
\toutput sum,
\t//carry bits\t
\tinput carry_in,
\toutput carry_out\t
\t
\t);
\twire xorab = a ^ b;
\t
\t
\tassign sum \t = xorab ^ carry_in;
\tassign carry_out = ( a & b ) | (xorab & carry_in);
endmodule
|
/*
This file is part of Fusion-Core-ISA.
Fusion-Core-ISA is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Fusion-Core-ISA is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.
*/
module shift_left_32(
\tinput[31:0] a, //value to be shifted
\toutput[31:0] out //output
\t);
\t//shifts everything left by 1
\tassign out[0] = a[31];
\tassign out[1] = a[0];
\tassign out[2] = a[1];
\tassign out[3] = a[2];
\tassign out[4] = a[3];
\tassign out[5] = a[4];
\tassign out[6] = a[5];
\tassign out[7] = a[6];
\tassign out[8] = a[7];
\tassign out[9] = a[8];
\tassign out[10] = a[9];
\tassign out[11] = a[10];
\tassign out[12] = a[11];
\tassign out[13] = a[12];
\tassign out[14] = a[13];
\tassign out[15] = a[14];
\tassign out[16] = a[15];
\tassign out[17] = a[16];
\tassign out[18] = a[17];
\tassign out[19] = a[18];
\tassign out[20] = a[19];
\tassign out[21] = a[20];
\tassign out[22] = a[21];
\tassign out[23] = a[22];
\tassign out[24] = a[23];
\tassign out[25] = a[24];
\tassign out[26] = a[25];
\tassign out[27] = a[26];
\tassign out[28] = a[27];
\tassign out[29] = a[28];
\tassign out[30] = a[29];
\tassign out[31] = a[30];
endmodule
|
/*\r
This file is part of Fusion-Core-ISA.\r
\r
Fusion-Core-ISA is free software: you can redistribute it and/or modify\r
it under the terms of the GNU General Public License as published by\r
the Free Software Foundation, either version 3 of the License, or\r
(at your option) any later version.\r
\r
Fusion-Core-ISA is distributed in the hope that it will be useful,\r
but WITHOUT ANY WARRANTY; without even the implied warranty of\r
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
GNU General Public License for more details.\r
\r
You should have received a copy of the GNU General Public License\r
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.\r
*/\r
\r
\r
\r
/*ALU Module Includes*/\r
`include add_32.v\r
`include and_32.v\r
`include not_32.v\r
`include or_32.v\r
`include xor_32.v\r
`include shift_carry_right_32.v\r
`include shift_left_32.v\r
`include shift_right_32.v\r
`include compare_32.v\r
`include decrement_32.v\r
\r
module ALU(\r
//32 bit ALU, will upgrade to 64 bit after tests are done.\r
\r
\t//Values from register file to operate on\r
\tinput [31:0] op_a;\r
\tinput [31:0] op_b;\r
\r
\t//op code, decoded from instruction\r
\tinput [3:0] op_code; //4 bit opcode\r
\r
\t//output from the ALU\r
\toutput reg [31:0] out;\r
\r
\t//Flags\r
\toutput reg flag_carry;\r
\toutput flag_overflow;\r
\toutput flag_parity; //even parity of output, 1 valid, 0 invalid\r
\toutput flag_neg; //output is negative\r
\t);\r
\r
\t/*Wires*/\r
\twire [31:0] to_out;\r
\twire [31:0] w_and;\r
\twire [31:0] w_or;\r
\twire [31:0] w_xor;\r
\twire [31:0] w_not;\r
\twire [31:0] w_shl; //shift left\r
\twire [31:0] w_shr; //shift right\r
\twire [31:0] w_scr; //shift carry right\r
\twire [31:0] w_cmp; //compare; 0 if true, -1 if less, 1 if greater\r
\twire [31:0] w_add;\r
\twire [31:0] w_sub;\r
\twire [31:0] w_inc; //increment\r
\twire [31:0] w_dec; //decrement\r
\r
\twire flg_carry_sub, flg_carry_add;\r
\r
\r
\t/*Instantiations of ALU Modules*/\r
\r
\t//Add\r
\tadd_32 add_32(\r
\t.reg_a(op_a),\r
\t.reg_b(op_b),\r
\t.out(w_add),\r
\t.flg_carry(flg_carry_add),\r
\t.carryin(1'b0)\r
\r
\t);\r
\r
\t//Subtract\r
\tadd_32 sub_32(\r
\t.reg_a(op_a),\r
\t.reg_b(op_b),\r
\t.out(w_sub),\r
\t.flg_carry(flg_carry_sub),\r
\t.carryin(1'b1)\t//2's compliment, so need this to be a 1\r
\r
\t);\r
\r
\t//Increment\r
\tadd_32 inc_32(\r
\t.reg_a(op_a),\r
\t.reg_b(32'b0001),\r
\t.out(w_inc),\r
\t.flg_carry(),\r
\t.carryin(1'b0)\r
\t);\r
\r
\t//Decrement\r
\tadd_32 dec_32(\r
\t.reg_a(op_a),\r
\t.reg_b('hFffF), //-1, 2's compliment\r
\t.out(w_dec),\r
\t.flg_carry(),\r
\t.carryin(1'b1)\t//2's compliment, so need this to be a 1\r
\r
\t);\r
\r
\t//AND\r
\tand_32 and_32(\r
\t.a(op_a), //input values\r
\t.b(op_b),\r
\t.out(w_and) //output value\r
\t);\r
\r
\t//OR\r
\tor_32 or_32(\r
\t.a(op_a), //input values\r
\t.b(op_b),\r
\t.out(w_or) //output value\r
\t);\r
\r
\t//XOR\r
\txor_32 xor_32(\r
\t.a(op_a), //input values\r
\t.b(op_b),\r
\t.out(w_xor) //output value\r
\t);\r
\r
\r
\t//NOT\r
\tnot_32 not_32(\r
\t.a(op_a), //input value\r
\t.out(w_not) //output value\r
\t);\r
\r
\r
\talways@*\r
\r
\t\tcase(op_code)\r
\t\t/*0*/\t4'b0000:begin\t//for NOP\r
\t\t\t\t\tout <= 0;\r
\t\t\t\t end\r
\t\t/*1*/\t4'b0001:begin\t//output AND operation\r
\t\t\t\t\tout <= w_and;\r
\t\t\t\t end\r
\t\t/*2*/\t4'b0010:begin\t//output OR operation\r
\t\t\t\t\tout <= w_or;\r
\t\t\t\t end\r
\t\t/*3*/\t4'b0011:begin //output XOR operation\r
\t\t\t\t\tout <= w_xor;\r
\t\t\t\t end\r
\t\t/*4*/\t4'b0100:begin\t//output NOT operation\r
\t\t\t\t\tout <= w_not;\r
\t\t\t\t end\r
\t\t/*5*/\t4'b0101:begin\t//output shift left operation\r
\t\t\t\t\tout <= w_shl;\r
\t\t\t\t end\r
\t\t/*6*/\t4'b0110:begin \t//output shift right operation\r
\t\t\t\t\tout <= w_shr;\r
\t\t\t\t end\r
\t\t/*7*/\t4'b0111:begin //output shift carry right operation\r
\t\t\t\t\tout <= w_scr;\r
\t\t\t\t end\r
\t\t/*8*/\t4'b1000:begin //output compare operation\r
\t\t\t\t\tout <= w_cmp;\r
\t\t\t\t end\r
\r
\t\t/*9*/\t4'b1001:begin\t//output for ADD operation\r
\t\t\t\t\tout <= w_add;\r
\t\t\t\t\tflag_carry <= flg_carry_add;\r
\t\t\t\t end\r
\t\t/*10*/\t4'b1010:begin\t//output for SUBTRACT operation\r
\t\t\t\t\tout <= w_sub;\r
\t\t\t\t\tflag_carry <= flg_carry_sub;\r
\t\t\t\t end\r
\t\t/*11*/\t4'b1011:begin\t//output for INCREMENT operation\r
\t\t\t\t\tout <= w_inc;\r
\t\t\t\t end\r
\t\t/*12*/\t'b1100:begin\t//output for DECREMENT operation\r
\t\t\t\t\tout <= w_dec;\r
\t\t\t\t end\r
\t\t/*13*/\t4'b1101:begin\r
\t\t\t\t\tout <= 0;\r
\t\t\t\t end\r
\t\t/*14*/\t4'b1110:begin\r
\t\t\t\t\tout <= 0;\r
\t\t\t\t end\r
\t\t/*15*/\t4'b1111:begin\r
\t\t\t\t\tout <= 0;\r
\t\t\t\t end\r
\t\t\tendcase\r
\r
\r
endmodule\r
|
/*
This file is part of Fusion-Core-ISA.
Fusion-Core-ISA is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Fusion-Core-ISA is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.
*/
module or_32(
\tinput [31:0] a, //input values
\tinput [31:0] b,
\toutput [31:0] out //output value
\t);
\t//output is the OR of a and b
\tassign out[0] \t= a[0] | b[0];
\tassign out[1] \t= a[1] | b[1];
\tassign out[2] \t= a[2] | b[2];
\tassign out[3] \t= a[3] | b[3];
\tassign out[4] \t= a[4] | b[4];
\tassign out[5] \t= a[5] | b[5];
\tassign out[6] \t= a[6] | b[6];
\tassign out[7] \t= a[7] | b[7];
\tassign out[8] \t= a[8] | b[8];
\tassign out[9] \t= a[9] | b[9];
\tassign out[10]\t= a[10] | b[10];
\tassign out[11] \t= a[11] | b[11];
\tassign out[12] \t= a[12] | b[12];
\tassign out[13] \t= a[13] | b[13];
\tassign out[14] \t= a[14] | b[14];
\tassign out[15] \t= a[15] | b[15];
\tassign out[16] \t= a[16] | b[16];
\tassign out[17] \t= a[17] | b[17];
\tassign out[18] \t= a[18] | b[18];
\tassign out[19] \t= a[19] | b[19];
\tassign out[20] \t= a[20] | b[20];
\tassign out[21] \t= a[21] | b[21];
\tassign out[22] \t= a[22] | b[22];
\tassign out[23] \t= a[23] | b[23];
\tassign out[24] \t= a[24] | b[24];
\tassign out[25]\t= a[25] | b[25];
\tassign out[26] \t= a[26] | b[26];
\tassign out[27] \t= a[27] | b[27];
\tassign out[28] \t= a[28] | b[28];
\tassign out[29] \t= a[29] | b[29];
\tassign out[30] \t= a[30] | b[30];
\tassign out[31] \t= a[31] | b[31];
endmodule
|
/*\r
This file is part of Fusion-Core-ISA.\r
\r
Fusion-Core-ISA is free software: you can redistribute it and/or modify\r
it under the terms of the GNU General Public License as published by\r
the Free Software Foundation, either version 3 of the License, or\r
(at your option) any later version.\r
\r
Fusion-Core-ISA is distributed in the hope that it will be useful,\r
but WITHOUT ANY WARRANTY; without even the implied warranty of\r
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
GNU General Public License for more details.\r
\r
You should have received a copy of the GNU General Public License\r
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.\r
*/\r
\r
\r
module RegisterFile(\r
\r
\t/*Data*/\r
\tinput[31:0] in_reg, //only one input needed\r
\r
\toutput reg[31:0] out_a,\r
\toutput reg[31:0] out_b,\r
\r
\t/*Addresses*/\r
\tinput[4:0] addr_a, //used for input addresses\r
\tinput[4:0] addr_b,\r
\t\r
\t/*Control Lines*/\r
\tinput rw, //rw == 1, then read; rw == 0, write\r
\tinput clk, //clock for synchronous registers\r
\tinput sel //chip select line, active low\r
\t);\r
\r
\r
\t/*Registers*/\r
\t//reg[31:0] reg_out_a; //for keeping verilog happy\r
\t//reg[31:0] reg_out_b;\r
\r
\treg [31:0] r0;\r
\treg [31:0] r1;\r
\treg [31:0] r2;\r
\treg [31:0] r3;\r
\treg [31:0] r4;\r
\treg [31:0] r5;\r
\treg [31:0] r6;\r
\treg [31:0] r7;\r
\treg [31:0] r8;\r
\treg [31:0] r9;\r
\treg [31:0] r10;\r
\treg [31:0] r11;\r
\treg [31:0] r12;\r
\treg [31:0] r13;\r
\treg [31:0] r14;\r
\treg [31:0] r15;\r
\treg [31:0] r16;\r
\treg [31:0] r17;\r
\treg [31:0] r18;\r
\treg [31:0] r19;\r
\treg [31:0] r20;\r
\treg [31:0] r21;\r
\treg [31:0] r22;\r
\treg [31:0] r23;\r
\treg [31:0] r24;\r
\treg [31:0] r25;\r
\treg [31:0] r26;\r
\treg [31:0] r27;\r
\treg [31:0] r28;\r
\treg [31:0] r29;\r
\treg [31:0] r30;\r
\treg [31:0] r31;\r
\r
initial //initialize all registers to 0\r
begin\r
\tr0 <= 32'b0;\r
\tr1 <= 32'b0;\r
\tr2 <= 32'b0;\r
\tr3 <= 32'b0;\r
\tr4 <= 32'b0;\r
\tr5 <= 32'b0;\r
\tr6 <= 32'b0;\r
\tr7 <= 32'b0;\r
\tr8 <= 32'b0;\r
\tr9 <= 32'b0;\r
\tr10 <= 32'b0;\r
\tr11 <= 32'b0;\r
\tr12 <= 32'b0;\r
\tr13 <= 32'b0;\r
\tr14 <= 32'b0;\r
\tr15 <= 32'b0;\r
\tr16 <= 32'b0;\r
\tr17 <= 32'b0;\r
\tr18 <= 32'b0;\r
\tr19 <= 32'b0;\r
\tr20 <= 32'b0;\r
\tr21 <= 32'b0;\r
\tr22 <= 32'b0;\r
\tr23 <= 32'b0;\t\r
\tr24 <= 32'b0;\r
\tr25 <= 32'b0;\r
\tr26 <= 32'b0;\r
\tr27 <= 32'b0;\t\r
\tr28 <= 32'b0;\r
\tr29 <= 32'b0;\r
\tr30 <= 32'b0;\r
\tr31 <= 32'b0;\r
\r
end\r
\r
\r
always @(posedge clk)\r
if(rw == 0 && sel == 0)\r
begin\r
\tout_a <= 0;\r
\tout_b <= 0;\r
\t\r
\tcase(addr_a)\r
\t\t5'b00000: r0 = in_reg;\r
\t\t5'b00001: r1 <= in_reg;\r
\t\t5'b00010: r2 <= in_reg;\r
\t\t5'b00011: r3 <= in_reg;\r
\t\t5'b00100: r4 <= in_reg;\r
\t\t5'b00101: r5 <= in_reg;\r
\t\t5'b00110: r6 <= in_reg;\r
\t\t5'b00111: r7 <= in_reg;\r
\t\t5'b01000: r8 <= in_reg;\r
\t\t5'b01001: r9 <= in_reg;\r
\t\t5'b01010: r10 <= in_reg;\r
\t\t5'b01011: r11 <= in_reg;\r
\t\t5'b01100: r12 <= in_reg;\r
\t\t5'b01101: r13 <= in_reg;\r
\t\t5'b01110: r14 <= in_reg;\r
\t\t5'b01111: r15 <= in_reg;\r
\t\t5'b10000: r16 <= in_reg;\r
\t\t5'b10001: r17 <= in_reg;\r
\t\t5'b10010: r18 <= in_reg;\r
\t\t5'b10011: r19 <= in_reg;\r
\t\t5'b10100: r20 <= in_reg;\r
\t\t5'b10101: r21 <= in_reg;\r
\t\t5'b10110: r22 <= in_reg;\r
\t\t5'b10111: r23 <= in_reg;\r
\t\t5'b11000: r24 <= in_reg;\r
\t\t5'b11001: r25 <= in_reg;\r
\t\t5'b11010: r26 <= in_reg;\r
\t\t5'b11011: r27 <= in_reg; \r
\t\t5'b11100: r28 <= in_reg;\r
\t\t5'b11101: r29 <= in_reg;\r
\t\t5'b11110: r30 <= in_reg;\r
\t\t5'b11111: r31 <= in_reg;\r
\tendcase\r
\tend\r
else if(rw == 1 && sel == 0)\r
\tbegin\r
\tcase(addr_a)\r
\t\t5'b00000: out_a <= r0;\r
\t\t5'b00001: out_a <= r1;\r
\t\t5'b00010: out_a <= r2;\r
\t\t5'b00011: out_a <= r3;\r
\t\t5'b00100: out_a <= r4;\r
\t\t5'b00101: out_a <= r5;\r
\t\t5'b00110: out_a <= r6;\r
\t\t5'b00111: out_a <= r7;\r
\t\t5'b01000: out_a <= r8;\r
\t\t5'b01001: out_a <= r9;\r
\t\t5'b01010: out_a <= r10;\r
\t\t5'b01011: out_a <= r11;\r
\t\t5'b01100: out_a <= r12;\r
\t\t5'b01101: out_a <= r13;\r
\t\t5'b01110: out_a <= r14;\r
\t\t5'b01111: out_a <= r15;\r
\t\t5'b10000: out_a <= r16;\r
\t\t5'b10001: out_a <= r17;\r
\t\t5'b10010: out_a <= r18;\r
\t\t5'b10011: out_a <= r19;\r
\t\t5'b10100: out_a <= r20;\r
\t\t5'b10101: out_a <= r21;\r
\t\t5'b10110: out_a <= r22;\r
\t\t5'b10111: out_a <= r23;\r
\t\t5'b11000: out_a <= r24;\r
\t\t5'b11001: out_a <= r25;\r
\t\t5'b11010: out_a <= r26;\r
\t\t5'b11011: out_a <= r27; \r
\t\t5'b11100: out_a <= r28;\r
\t\t5'b11101: out_a <= r29;\r
\t\t5'b11110: out_a <= r30;\r
\t\t5'b11111: out_a <= r31;\r
\tendcase\r
\r
\tcase(addr_b)\r
\t\t5'b00000: out_b <= r0;\r
\t\t5'b00001: out_b <= r1;\r
\t\t5'b00010: out_b <= r2;\r
\t\t5'b00011: out_b <= r3;\r
\t\t5'b00100: out_b <= r4;\r
\t\t5'b00101: out_b <= r5;\r
\t\t5'b00110: out_b <= r6;\r
\t\t5'b00111: out_b <= r7;\r
\t\t5'b01000: out_b <= r8;\r
\t\t5'b01001: out_b <= r9;\r
\t\t5'b01010: out_b <= r10;\r
\t\t5'b01011: out_b <= r11;\r
\t\t5'b01100: out_b <= r12;\r
\t\t5'b01101: out_b <= r13;\r
\t\t5'b01110: out_b <= r14;\r
\t\t5'b01111: out_b <= r15;\r
\t\t5'b10000: out_b <= r16;\r
\t\t5'b10001: out_b <= r17;\r
\t\t5'b10010: out_b <= r18;\r
\t\t5'b10011: out_b <= r19;\r
\t\t5'b10100: out_b <= r20;\r
\t\t5'b10101: out_b <= r21;\r
\t\t5'b10110: out_b <= r22;\r
\t\t5'b10111: out_b <= r23;\r
\t\t5'b11000: out_b <= r24;\r
\t\t5'b11001: out_b <= r25;\r
\t\t5'b11010: out_b <= r26;\r
\t\t5'b11011: out_b <= r27; \r
\t\t5'b11100: out_b <= r28;\r
\t\t5'b11101: out_b <= r29;\r
\t\t5'b11110: out_b <= r30;\r
\t\t5'b11111: out_b <= r31;\r
\tendcase\r
\t\r
end\r
else\r
\tbegin\r
\t\tout_a <= 32'bz;\r
\t\tout_b <= 32'bz;\r
end\r
\r
\r
endmodule\r
|
/*
This file is part of Fusion-Core-ISA.
Fusion-Core-ISA is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Fusion-Core-ISA is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.
*/
module and_32(
\tinput [31:0] a, //input values
\tinput [31:0] b,
\toutput [31:0] out //output value
\t);
\t//output is the AND of a and b
\tassign out[0] \t= a[0] & b[0];
\tassign out[1] \t= a[1] & b[1];
\tassign out[2] \t= a[2] & b[2];
\tassign out[3] \t= a[3] & b[3];
\tassign out[4] \t= a[4] & b[4];
\tassign out[5] \t= a[5] & b[5];
\tassign out[6] \t= a[6] & b[6];
\tassign out[7] \t= a[7] & b[7];
\tassign out[8] \t= a[8] & b[8];
\tassign out[9] \t= a[9] & b[9];
\tassign out[10]\t= a[10] & b[10];
\tassign out[11] \t= a[11] & b[11];
\tassign out[12] \t= a[12] & b[12];
\tassign out[13] \t= a[13] & b[13];
\tassign out[14] \t= a[14] & b[14];
\tassign out[15] \t= a[15] & b[15];
\tassign out[16] \t= a[16] & b[16];
\tassign out[17] \t= a[17] & b[17];
\tassign out[18] \t= a[18] & b[18];
\tassign out[19] \t= a[19] & b[19];
\tassign out[20] \t= a[20] & b[20];
\tassign out[21] \t= a[21] & b[21];
\tassign out[22] \t= a[22] & b[22];
\tassign out[23] \t= a[23] & b[23];
\tassign out[24] \t= a[24] & b[24];
\tassign out[25]\t= a[25] & b[25];
\tassign out[26] \t= a[26] & b[26];
\tassign out[27] \t= a[27] & b[27];
\tassign out[28] \t= a[28] & b[28];
\tassign out[29] \t= a[29] & b[29];
\tassign out[30] \t= a[30] & b[30];
\tassign out[31] \t= a[31] & b[31];
endmodule
|
module not_32(
\tinput [31:0] a, //input value
\toutput [31:0] out //output value
\t);
\t//output is the inverse of a
\tassign out[0] \t= !a[0];
\tassign out[1] \t= !a[1];
\tassign out[2] \t= !a[2];
\tassign out[3] \t= !a[3];
\tassign out[4] \t= !a[4];
\tassign out[5] \t= !a[5];
\tassign out[6] \t= !a[6];
\tassign out[7] \t= !a[7];
\tassign out[8] \t= !a[8];
\tassign out[9] \t= !a[9];
\tassign out[10]\t= !a[10];
\tassign out[11] \t= !a[11];
\tassign out[12] \t= !a[12];
\tassign out[13] \t= !a[13];
\tassign out[14] \t= !a[14];
\tassign out[15] \t= !a[15];
\tassign out[16] \t= !a[16];
\tassign out[17] \t= !a[17];
\tassign out[18] \t= !a[18];
\tassign out[19] \t= !a[19];
\tassign out[20] \t= !a[20];
\tassign out[21] \t= !a[21];
\tassign out[22] \t= !a[22];
\tassign out[23] \t= !a[23];
\tassign out[24] \t= !a[24];
\tassign out[25]\t= !a[25];
\tassign out[26] \t= !a[26];
\tassign out[27] \t= !a[27];
\tassign out[28] \t= !a[28];
\tassign out[29] \t= !a[29];
\tassign out[30] \t= !a[30];
\tassign out[31] \t= !a[31];
endmodule
|
/*** Defines ***/
/*System because it's special*/
`define\tOPC_SYS\t\t 5'b110000;
module decode_32(
\tinput[31:0] \tinsn_in,\t\t\t//input instruction
\tinput\t\t\treset_in,\t\t\t//input reset line
\tinput\t\t\tclk_in,\t\t\t\t//input clock
\tinput[31:0]\t\tinsn_pc_in,\t\t\t//input program counter address
\tinput\t\t\tstall_in,\t\t\t//input stall signal
\t/*Operand output connections*/
\toutput reg\t[4:0] \treg_select_out,\t\t//output register bank select
\toutput reg \t[4:0]\trsa_out,\t\t\t//output of register a address
\toutput reg\t[4:0] \trsb_out,\t\t\t//output of register b address
\toutput reg\t[4:0] \trd_out, \t\t\t//output of destination register address
\toutput reg\t[20:0] \timm_out,\t\t\t//output of immediate value
\t\t\t\t\t\t\t\t\t\t\t//using largest immediate value
\t\t\t\t\t\t\t\t\t\t\t//size
\t/*Control Signals*/
\toutput \treg [3:0] aluop_out,
\toutput\treg jlnk_out,
\toutput\treg pc_change_rel_out,
\toutput\treg pc_change_abs_out,
\toutput\treg mem_read_out,
\toutput\treg mem_write_out,
\t/*Flag outputs*/
\toutput\treg nri_flg_out,\t\t//output of 'not real instruction' flag
\toutput\treg [1:0] branch_funct_out,\t//branch function; taken from the funct field
\toutput\treg stall_out,
\t/*System instruction signals*/
\toutput\t\treg \t\tmemsync_out,
\toutput\t\treg \t\tsyscall_out,
\toutput\t\treg \t\tpem_inc_req_out,
\toutput\t\treg \t\tpem_dec_req_out,
\toutput\t\treg [7:0]\tsysreg_addr_out,\t//for reading and writing to system registers
\toutput\t\treg [7:0]\tsysreg_data_out,
\tinput \t\t\t[7:0]\tsysreg_data_in,
\t/* Misc. Outputs*/
\toutput\treg [31:0] insn_pc_out,
\t/*Co-processor connections*/
\toutput\treg [30:0] cp_insn_out
\t);
\t/* Pipeline information */
\tlocalparam PIPELINE_LENGTH \t= 5;
\tlocalparam PIPELINEL_2\t\t= $clog2(PIPELINE_LENGTH);
\t/*Defining opcodes to make things easier*/
\tlocalparam OPC_INT \t \t= 5'b010011;
\tlocalparam OPC_IMM \t\t= 5'b010110;
\tlocalparam OPC_LI\t\t= 5'b010000;
\tlocalparam OPC_BRANCH\t= 5'b001101;
\tlocalparam OPC_JMP\t\t= 5'b001100;
\tlocalparam OPC_JLNK\t\t= 5'b000100;
\tlocalparam OPC_LD\t\t= 5'b011110;
\tlocalparam OPC_ST\t\t= 5'b011101;
\t/*Wire connections*/
\twire[5:0] \topcode_w;
\twire[4:0] \trsa_addr_w;
\twire[4:0] \trsb_addr_w;
\twire[4:0] \trd_addr_w;
\twire[3:0] \taluop_w;
\t/*Funct Variants*/
\twire[1:0]\tfunct_ld_w;
\twire[1:0]\tfunct_st_w;
\twire[3:0]\tdsel_li_w;
\twire[1:0]\tfunct_b_w;
\twire[7:0]\tfunct_sys_w;
\t/*Immediate Variants*/
\twire[11:0]\timm_i_w;
\twire[13:0]\timm_ld_w;
\twire[15:0]\timm_li_w;
\twire[13:0]\timm_st_w;
\twire[20:0]\timm_j_w;
\twire[13:0]\timm_b_w;
\twire[7:0]\timm_sys_w;
\t/*OPCode generated signals*/
\t/*Resouce usage*/
\twire\t\tuse_alu_w;
\twire\t\tis_cp_insn_w;\t\t\t//is coprocessor instruction
\twire\t\tpc_change_w;\t\t\t//instruction can change the pc
\twire\t\tmem_access_w;
\twire\t\tpc_link_w;\t\t\t\t//jump that requires linking to ra
\twire\t\tsys_insn_w;
\t/*secondary calculated resource usage*/
\twire\t\tmem_read_req_w;
\twire\t\tmem_write_req_w;
\twire\t\tpc_abs_w;
\twire\t\tpc_rel_w;
\twire\t\tmemsync_w;
\t
\t/*ALU op signal selection*/
\twire\t\taluop_intsig_w; // integer/register operation field used
\twire\t\taluop_addsig_w; // fixed add operation
\twire\t\taluop_bsig_w; // branch operation decode value
\t/*Operand usage*/
\twire\t\tuse_rd_w;
\twire\t\tuse_rsa_w;
\twire\t\tuse_rsb_w;
\twire\t\tuse_imm_w;
\twire [4:0]\timm_sel_w;
\t/*Assignments*/
\tassign \topcode_w \t\t= insn_in[31:26];
\tassign \trsa_addr_w \t\t= insn_in[20:16];
\tassign \trsb_addr_w \t\t= insn_in[15:11];
\tassign \trd_addr_w\t\t= insn_in[25:21];
\tassign \taluop_w \t\t= insn_in[3:0];
\tassign\tfunct_ld_w \t\t= insn_in[15:14];
\tassign\tfunct_st_w\t\t= insn_in[25:24];
\tassign\tdsel_li_w\t\t= insn_in[20:16];
\tassign\tfunct_b_w\t\t= insn_in[1:0];
\tassign\tfunct_sys_w\t\t= insn_in[15:8];
\tassign\timm_i_w \t\t= insn_in[15:4];
\tassign\timm_ld_w\t\t= insn_in[13:0];
\tassign\timm_li_w\t\t= insn_in[15:0];
\tassign\timm_st_w\t\t= {insn_in[13:11],insn_in[10:0]};
\tassign\timm_j_w\t\t\t= {insn_in[25:21],insn_in[15:0]};
\tassign\timm_b_w\t\t\t= {insn_in[25:21],insn_in[10:2]};
\tassign\timm_sys_w\t\t= insn_in[7:0];
\tassign imm_sel_w\t\t= (use_imm_w) ?opcode_w[4:0] : 5'b0; //if using immediate, need to determine output
\tassign \tis_cp_insn_w\t= opcode_w[5];
\tassign\tpc_change_w\t\t= ~opcode_w[4];\t\t\t\t
\tassign\tmem_access_w\t= opcode_w[4] & opcode_w[3];
\tassign\tpc_link_w\t\t= ~(opcode_w[4] | opcode_w[3]);\t\t\t\t
\tassign\tsys_insn_w\t\t= is_cp_insn_w & opcode_w[4];
\tassign \tmemsync_w = (sys_insn_w && ( (funct_sys_w & 8'h04) || (funct_sys_w & 8'b0 ) )); //if sync or syscall, need to sync memory
\tassign\tuse_rd_w\t\t= (opcode_w[1] | opcode_w[0]) & (~opcode_w[2] | opcode_w[1]);
\tassign\tuse_rsa_w\t\t= (opcode_w[2] | opcode_w[1]);
\tassign\tuse_rsb_w\t\t= (opcode_w[2] & opcode_w[0]) | ( opcode_w[1] & opcode_w[0] );
\tassign\tuse_imm_w \t\t= (opcode_w[2] | ~opcode_w[1]);
assign \taluop_intsig_w\t= (opcode_w[4] & opcode_w[1]) & ~(opcode_w[5] & opcode_w[3]) & (opcode_w[2] ^ opcode_w[0]); //used for imm and int
assign\taluop_addsig_w\t= pc_rel_w;//used for jump (relative)
assign\taluop_bsig_w\t= (pc_change_w) & (use_rsb_w); //is a branch
\t/*Memory read/write signal creation*/
\t/*use_rsb has simpler gate usage, which is better than using use_rd for
\t* determining read or writes */
\tassign \tmem_write_req_w = (mem_access_w & use_rsb_w); //store instructions use rsb, not rd
\tassign \tmem_read_req_w\t= (mem_access_w & ~use_rsb_w); //load instructions use rd, not rsb
\tassign pc_rel_w\t\t= (pc_change_w & \t( (opcode_w[2:0] && 3'b101) || (rsa_addr_w == (5'b0)) ) ); //not jr/jrl or branch
\tassign\tpc_abs_w\t\t= (pc_change_w & ~( (opcode_w[2:0] && 3'b101) || (rsa_addr_w == (5'b0)) ) );
/* Internal registers*/
\treg\t[PIPELINEL_2 - 1 : 0]\tmemstall_count; //counter for stalls in pipeline
/*** LOGIC SECTION ****/
always@(~reset_in or stall_in) begin //while in reset or stalling
\treg_select_out \t\t<= 5'b0;\t\t\t//output register bank select
\trsa_out \t\t\t<= 5'b0;\t\t\t//output of register a address
\trsb_out \t\t\t<= 5'b0;\t\t\t//output of register b address
\trd_out\t\t\t\t<= 5'b0; \t\t\t//output of destination register address
\timm_out\t\t\t\t<= 21'b0;\t\t\t//output of immediate value
\t \t\t\t\t\t\t\t\t\t//using largest immediate value
\t \t\t\t\t\t\t\t\t\t//size
\taluop_out\t\t\t<= 4'b0;
\tjlnk_out\t\t\t<= 1'b0;
\tpc_change_rel_out\t<= 1'b0;
\tpc_change_abs_out\t<= 1'b0;
\tmem_read_out\t\t<= 1'b0;
\tmem_write_out\t\t<= 1'b0;
\tnri_flg_out\t\t\t<= 1'b0;\t\t//output of 'not real instruction' flag
\tbranch_funct_out\t<= 2'b0;\t//branch function; taken from the funct field
\tmemsync_out\t\t\t<= 1'b0;
\tsyscall_out\t\t\t<= 1'b0;
\tpem_inc_req_out\t\t<= 1'b0;
\tpem_dec_req_out\t\t<= 1'b0;
\tsysreg_addr_out\t\t<= 8'b0;
\tsysreg_data_out\t\t<= 8'b0;
\tinsn_pc_out\t\t\t<= 32'h0;
\tcp_insn_out\t\t\t<= 32'h0;
\tstall_out\t\t\t<= 1'b0;
end
always@(posedge clk_in, reset_in, ~stall_in) begin //make sure that reset has to be high for this to work
\t/*** Determining ALUOP value ***/
\tif (aluop_intsig_w) begin //uses ALUOP field
\t\taluop_out = aluop_w;
\tend else if (aluop_addsig_w) begin //just add, so jumps
\t\taluop_out = 4'b0000;
\tend else if (aluop_bsig_w) begin //branches, so need to decode the funct field
\t\taluop_out = 4'b1100; //like compare insn, but does different things
\tend else begin
\t\taluop_out = 4'b1111; //unused code, use as nop? need to define in documentation
\tend
\t/*Branch funct assignment*/
\tbranch_funct_out = (aluop_bsig_w) ? (funct_b_w) : (2'b0);
\t/*Co-processor instruction output to co-processor decode*/
\tcp_insn_out \t<= (is_cp_insn_w) ? insn_in : 30'b0; \t//if is a co-processor instruction, output instruction to
\t\t //co-processor decoder
\t/*Memory access signal output*/
\tmem_write_out \t<= mem_write_req_w;
\tmem_read_out \t<= mem_read_req_w;
\t
\tpc_change_rel_out <= pc_rel_w;
\tpc_change_abs_out <= pc_abs_w;
\t/*Register selection and outputs*/
\tif(imm_sel_w == OPC_LI) begin //determine which register bank to use, from DSEL
\t\treg_select_out\t<= { 1'b0, dsel_li_w}; //lower 2 bits determine file, upper two bits determine signed, upper or lower 16 bits
\tend else if(sys_insn_w && ( funct_sys_w & (8'h02 ))) begin //if system instruction, need to check if accessing system registers, last two bits matter here
\t\treg_select_out\t<= 5'b10000; //upper most bit is for accessing special purpose registers; maps to memory address to make 8 bit registers easier
\tend else begin //everything else should just use general purpose register file
\t\treg_select_out\t<= 5'b0;
\tend
\trsa_out <= (use_rsa_w) ? rsa_addr_w : 5'b0;
\trsb_out <= (use_rsb_w) ? rsb_addr_w : 5'b0;
\trd_out <= (use_rd_w ) ? rd_addr_w : 5'b0;
\tinsn_pc_out <= insn_pc_in; //may need to alter this value, but unsure so leave it
\t/*** Selecting immediate values ***/
\tif(!is_cp_insn_w) begin
\t\tcase (imm_sel_w) //figure out what immediate value to use
\t\t\tOPC_IMM:\t\timm_out <= {9'b0 ,imm_i_w};
\t\t\tOPC_LD:\t\t\timm_out <= {7'b0, imm_ld_w};
\t\t\tOPC_ST:\t\t\timm_out <= {7'b0, imm_st_w};
\t\t\tOPC_LI:\t\t\timm_out <= {6'b0, imm_li_w};
\t\t\tOPC_JMP:\t\timm_out <= imm_j_w;
\t\t\tOPC_JLNK:\t\timm_out <= imm_j_w;
\t\t\tOPC_BRANCH:\t\timm_out <= {7'b0, imm_b_w};
\t\t\tdefault:\t\timm_out <= 21'b0;\t//this may be redundant or cause errors, not sure yet
\t\tendcase
\t\t/*co processor instruction immediates; right now just system insn due to direct
\t\t* affects on main core pipeline */
\tend else if(opcode_w[5] & opcode_w[4] & ~(opcode_w[3] | opcode_w[2] | opcode_w[1] | opcode_w[0] ) )begin
\t\t/*just system instructions*/\t
\t\timm_out <= imm_sys_w;
\tend else begin
\t\timm_out <= 21'b0; //no immediate, default to 0's
\tend
\t/*System decoding*/
\tif( sys_insn_w) begin //if actually a system instruction
\t\tcase (funct_sys_w)
\t\t\t8'h00: begin\t\t\t\t//system call
\t\t\t\tsyscall_out \t<= 1'b1;
\t\t\t\tmemsync_out\t\t<= 1'b0;
\t\t\t\tpem_inc_req_out\t<= 1'b0;
\t\t\t\tpem_dec_req_out\t<= 1'b0;
\t\t\tend
\t\t//\t8'h01: begin\t\t\t\t//system return
\t\t//\tend
\t\t\t8'h04: begin\t\t\t\t//memory sync
\t\t\t\tsyscall_out \t<= 1'b0;
\t\t\t\tmemsync_out\t\t<= 1'b1;
\t\t\t\tpem_inc_req_out\t<= 1'b0;
\t\t\t\tpem_dec_req_out\t<= 1'b0;
\t\t\t\tstall_out\t\t<= 1'b1;
\t\t\tend
\t\t\tdefault: begin
\t\t\t\tsyscall_out \t<= 1'b0;
\t\t\t\tmemsync_out\t\t<= 1'b0;
\t\t\t\tpem_inc_req_out\t<= 1'b0;
\t\t\t\tpem_dec_req_out\t<= 1'b0;
\t\t\tend
\t\tendcase
\tend
\t/* Ensure stall_out from memory sync doesn't make the pipeline get stuck */
\tif(memsync_w) begin
\t\tif(memstall_count > PIPELINE_LENGTH) begin
\t\t\tmemstall_count \t<= 0;
\t\t\tmemsync_out\t\t<= 1'b0;
\t\tend
\t\telse begin
\t\t\tmemstall_count = memstall_count + 1;
\t\tend
\tend
end
endmodule
|
module shift_carry_right_32(
\tinput[31:0] a, //value to be shifted
\toutput[31:0] out //output
\t);
\t//shifts everything right by 1, with carry
\tassign out[0] = a[1];
\tassign out[1] = a[2];
\tassign out[2] = a[3];
\tassign out[3] = a[4];
\tassign out[4] = a[5];
\tassign out[5] = a[6];
\tassign out[6] = a[7];
\tassign out[7] = a[8];
\tassign out[8] = a[9];
\tassign out[9] = a[10];
\tassign out[10] = a[11];
\tassign out[11] = a[12];
\tassign out[12] = a[13];
\tassign out[13] = a[14];
\tassign out[14] = a[15];
\tassign out[15] = a[16];
\tassign out[16] = a[17];
\tassign out[17] = a[18];
\tassign out[18] = a[19];
\tassign out[19] = a[20];
\tassign out[20] = a[21];
\tassign out[21] = a[22];
\tassign out[22] = a[23];
\tassign out[23] = a[24];
\tassign out[24] = a[25];
\tassign out[25] = a[26];
\tassign out[26] = a[27];
\tassign out[27] = a[28];
\tassign out[28] = a[29];
\tassign out[29] = a[30];
\tassign out[30] = a[31];
\tassign out[31] = a[0];
endmodule
|
`include "adder_1b.v"
module add_32(reg_a, reg_b, out, flg_carry, carryin);
\tparameter NBIT = 32;
\tinput[(NBIT-1):0] reg_a, reg_b;
\tinput carryin;
\toutput[(NBIT-1):0] out;
\toutput flg_carry;
\t//wire[(NBIT-1):0] bit_sum; \t//only 1 bit, make
\twire[(NBIT-1):0] p;\t \t//values for fast carry
\twire[(NBIT-1):0] g;
\twire[(NBIT-1):0] carry;\t//intermediary carry bits
\t
\t/*Carry generator intermediary step*/
\twire[(NBIT):1] carry_p; \t//p[n] & p[n-1] & ... & carryin
\twire[(NBIT):1] carry_g;\t//(g[0] & p[n] & p[n-1]...)
\tgenvar i; //for counter
\tbegin
\tfor(i = 0; i < NBIT; i = i+1)
\t\tassign g[i] = reg_a[i] & reg_b[i];
\tend
\tbegin
\tfor(i = 0; i < NBIT; i = i+1)
\t\tassign p[i] = reg_a[i] | reg_b[i];
\tend
\t/*Intermediary Carry Assignments*/
\tbegin
\t\tassign carry_p[1] = p[0] & carryin;
\t\tassign carry_p[2] = p[0] & p[1] & carryin;
\t\tassign carry_p[3] = p[0] & p[1] & p[2] & carryin;
\t\tassign carry_p[4] = p[0] & p[1] & p[2] & p[3] & carryin;
\t\tassign carry_p[5] = p[0] & p[1] & p[2] & p[3] & p[4] & carryin;
\t\tassign carry_p[6] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & carryin;
\t\tassign carry_p[7] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & carryin;
\t\tassign carry_p[8] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & carryin;
\t\tassign carry_p[9] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & carryin;
\t\tassign carry_p[10] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & carryin;
\t\tassign carry_p[11] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & carryin;
\t\tassign carry_p[12] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & carryin;
\t\tassign carry_p[13] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & carryin;
\t\tassign carry_p[14] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & carryin;
\t\tassign carry_p[15] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & carryin;
\t\tassign carry_p[16] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & p[15] & carryin;
\t\tassign carry_p[17] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & p[15] & p[16] & carryin;
\t\tassign carry_p[18] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & p[15] & p[16] & p[17] & carryin;
\t\tassign carry_p[19] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & carryin;
\t\tassign carry_p[20] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & carryin;
\t\tassign carry_p[21] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & carryin;
\t\tassign carry_p[22] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & carryin;
\t\tassign carry_p[23] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & carryin;
\t\tassign carry_p[24] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & carryin;
\t\tassign carry_p[25] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24]
\t\t\t\t & carryin;
\t\tassign carry_p[26] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24]
\t\t\t\t & p[25] & carryin;
\t\tassign carry_p[27] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24]
\t\t\t\t & p[25] & p[26] & carryin;
\t\tassign carry_p[28] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24]
\t\t\t\t & p[25] & p[26] & p[27] & carryin;
\t\tassign carry_p[29] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24]
\t\t\t\t & p[25] & p[26] & p[27] & p[28] & carryin;
\t\tassign carry_p[30] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24]
\t\t\t\t & p[25] & p[26] & p[27] & p[28] & p[29] & carryin;
\t\tassign carry_p[31] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24]
\t\t\t\t & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & carryin;
\t\tassign carry_p[32] = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12]
\t\t\t\t & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24]
\t\t\t\t & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31] & carryin;
\tend
\tbegin
\t\tassign carry_g[1] = g[0];
\t\tassign carry_g[2] = (g[0] & p[1]) + g[1];
\t\tassign carry_g[3] = (g[0] & p[1] & p[2]) + (g[1] & p[2]) + g[2];
\t\tassign carry_g[4] = (g[0] & p[1] & p[2] & p[3]) + (g[1] & p[2] & p[3]) + (g[2] & p[3]) + g[3];
\t\tassign carry_g[5] = (g[0] & p[1] & p[2] & p[3] & p[4]) + (g[1] & p[2] & p[3] & p[4]) + (g[2] & p[3] & p[4]) + (g[3] & p[4]) + g[4];
\t\tassign carry_g[6] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5]) + (g[1] & p[2] & p[3] & p[4] & p[5]) + (g[2] & p[3] & p[4] & p[5])
\t\t\t+ (g[3] & p[4] & p[5]) + (g[4] & p[5]) + g[5];
\t\tassign carry_g[7] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6]) + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]) + (g[2] & p[3] & p[4] & p[5] & p[6])
\t\t\t+ (g[3] & p[4] & p[5] & p[6]) + (g[4] & p[5] & p[6]) + (g[5] & p[6]) + g[6];
\t\tassign carry_g[8] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7]) + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7]) + (g[3] & p[4] & p[5] & p[6] & p[7]) + (g[4] & p[5] & p[6] & p[7])
\t\t\t+ (g[5] & p[6] & p[7]) + (g[6] & p[7]) + g[7];
\t\tassign carry_g[9] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8]) + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8]) + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8]) + (g[4] & p[5] & p[6] & p[7] & p[8])
\t\t\t+ (g[5] & p[6] & p[7] & p[8]) + (g[6] & p[7] & p[8]) + (g[7] & p[8]) + g[8];
\t\tassign carry_g[10] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9]) + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9]) + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9]) + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9]) + (g[6] & p[7] & p[8] & p[9]) + (g[7] & p[8] & p[9]) + (g[8] & p[9]) + g[9];
\t\tassign carry_g[11] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10]) + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10]) + (g[6] & p[7] & p[8] & p[9] & p[10]) + (g[7] & p[8] & p[9] & p[10])
\t\t + (g[8] & p[9] & p[10]) + (g[9] & p[10]) + g[10];
\t\tassign carry_g[12] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11]) + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11]) + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11])
\t\t + (g[8] & p[9] & p[10] & p[11]) + (g[9] & p[10] & p[11]) + (g[10] & p[11]) + g[11];
\t\tassign carry_g[13] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12])
\t\t + (g[9] & p[10] & p[11] & p[12]) + (g[10] & p[11] & p[12]) + (g[11] & p[12]) + g[12];
\t\tassign carry_g[14] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13])
\t\t\t+ (g[10] & p[11] & p[12] & p[13]) + (g[11] & p[12] & p[13]) + (g[12] & p[13]) + g[13];
\t\tassign carry_g[15] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14])
\t\t\t+ (g[11] & p[12] & p[13] & p[14]) + (g[12] & p[13] & p[14]) + (g[13] & p[14]) + g[14];
\t\t/*16 BITS FINISHED*/
\t\tassign carry_g[16] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14] & p[15])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14] & p[15])
\t\t\t+ (g[11] & p[12] & p[13] & p[14] & p[15])
\t\t\t+ (g[12] & p[13] & p[14] & p[15]) + (g[13] & p[14] & p[15]) + (g[14] & p[15]) + g[15];
\t\tassign carry_g[17] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14] & p[15 & p[16]])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16])
\t\t\t+ (g[11] & p[12] & p[13] & p[14] & p[15] & p[16])
\t\t\t+ (g[12] & p[13] & p[14] & p[15] & p[16])
\t\t\t+ (g[13] & p[14] & p[15] & p[16]) + (g[14] & p[15] & p[16]) + (g[15] & p[16]) + g[16];
\t\tassign carry_g[18] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14] & p[15 & p[16]] & p[17])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17])
\t\t\t+ (g[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17])
\t\t\t+ (g[12] & p[13] & p[14] & p[15] & p[16] & p[17])
\t\t\t+ (g[13] & p[14] & p[15] & p[16] & p[17])
\t\t\t+ (g[14] & p[15] & p[16] & p[17]) + (g[15] & p[16] & p[17]) + (g[16] & p[17]) + g[17];
\t\tassign carry_g[19] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14] & p[15 & p[16]] & p[17] & p[18])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18])
\t\t\t+ (g[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18])
\t\t\t+ (g[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18])
\t\t\t+ (g[13] & p[14] & p[15] & p[16] & p[17] & p[18])
\t\t\t+ (g[14] & p[15] & p[16] & p[17] & p[18])
\t\t\t+ (g[15] & p[16] & p[17] & p[18]) + (g[16] & p[17] & p[18]) + (g[17] & p[18]) + g[18];
\t\tassign carry_g[20] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14] & p[15 & p[16]] & p[17] & p[18] & p[19])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19])
\t\t\t+ (g[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19])
\t\t\t+ (g[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19])
\t\t\t+ (g[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19])
\t\t\t+ (g[14] & p[15] & p[16] & p[17] & p[18] & p[19])
\t\t\t+ (g[15] & p[16] & p[17] & p[18] & p[19])
\t\t\t+ (g[16] & p[17] & p[18] & p[19]) + (g[17] & p[18] & p[19]) + (g[18] & p[19]) + g[19];
\t\tassign carry_g[21] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14] & p[15 & p[16]] & p[17] & p[18] & p[19] & p[20])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20])
\t\t\t+ (g[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20])
\t\t\t+ (g[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20])
\t\t\t+ (g[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20])
\t\t\t+ (g[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20])
\t\t\t+ (g[15] & p[16] & p[17] & p[18] & p[19] & p[20])
\t\t\t+ (g[16] & p[17] & p[18] & p[19] & p[20])
\t\t\t+ (g[17] & p[18] & p[19] & p[20]) + (g[18] & p[19] & p[20]) + (g[19] & p[20]) + g[20];
\t\tassign carry_g[22] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14] & p[15 & p[16]] & p[17] & p[18] & p[19] & p[20] & p[21])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21])
\t\t\t+ (g[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21])
\t\t\t+ (g[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21])
\t\t\t+ (g[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21])
\t\t\t+ (g[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21])
\t\t\t+ (g[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21])
\t\t\t+ (g[16] & p[17] & p[18] & p[19] & p[20] & p[21])
\t\t\t+ (g[17] & p[18] & p[19] & p[20] & p[21])
\t\t\t+ (g[18] & p[19] & p[20] & p[21]) + (g[19] & p[20] & p[21]) + (g[20] & p[21]) + g[21];
\t\tassign carry_g[23] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14] & p[15 & p[16]] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t\t+ (g[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t\t+ (g[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t\t+ (g[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t\t+ (g[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t\t+ (g[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t\t+ (g[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t\t+ (g[17] & p[18] & p[19] & p[20] & p[21] & p[22])
\t\t\t+ (g[18] & p[19] & p[20] & p[21] & p[22])
\t\t\t+ (g[19] & p[20] & p[21] & p[22]) + (g[20] & p[21] & p[22]) + (g[21] & p[22]) + g[22];
\t\tassign carry_g[24] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14] & p[15 & p[16]] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t\t+ (g[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t\t+ (g[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t\t+ (g[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t\t+ (g[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t\t+ (g[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t\t+ (g[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t\t+ (g[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t\t+ (g[18] & p[19] & p[20] & p[21] & p[22] & p[23])
\t\t\t+ (g[19] & p[20] & p[21] & p[22] & p[23])
\t\t\t+ (g[20] & p[21] & p[22] & p[23]) + (g[21] & p[22] & p[23]) + (g[22] & p[23]) + g[23];
\t\tassign carry_g[25] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14] & p[15 & p[16]] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t\t+ (g[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t\t+ (g[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t\t+ (g[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t\t+ (g[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t\t+ (g[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t\t+ (g[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t\t+ (g[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t\t+ (g[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t\t+ (g[19] & p[20] & p[21] & p[22] & p[23] & p[24])
\t\t\t+ (g[20] & p[21] & p[22] & p[23] & p[24])
\t\t\t+ (g[21] & p[22] & p[23] & p[24]) + (g[22] & p[23] & p[24]) + (g[23] & p[24]) + g[24];
\t\tassign carry_g[26] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14] & p[15 & p[16]] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t\t+ (g[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t\t+ (g[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t\t+ (g[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t\t+ (g[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t\t+ (g[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t\t+ (g[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t\t+ (g[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t\t+ (g[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t\t+ (g[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t\t+ (g[20] & p[21] & p[22] & p[23] & p[24] & p[25])
\t\t\t+ (g[21] & p[22] & p[23] & p[24] & p[25])
\t\t\t+ (g[22] & p[23] & p[24] & p[25]) + (g[23] & p[24] & p[25]) + (g[24] & p[25]) + g[25];
\t\tassign carry_g[27] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14] & p[15 & p[16]] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t\t+ (g[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t\t+ (g[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t\t+ (g[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t\t+ (g[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t\t+ (g[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t\t+ (g[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t\t+ (g[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t\t+ (g[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t\t+ (g[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t\t+ (g[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t\t+ (g[21] & p[22] & p[23] & p[24] & p[25] & p[26])
\t\t\t+ (g[22] & p[23] & p[24] & p[25] & p[26])
\t\t\t+ (g[23] & p[24] & p[25] & p[26]) + (g[24] & p[25] & p[26]) + (g[25] & p[26]) + g[26];
\t\tassign carry_g[28] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14] & p[15 & p[16]] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t\t+ (g[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t\t+ (g[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t\t+ (g[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t\t+ (g[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t\t+ (g[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t\t+ (g[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t\t+ (g[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t\t+ (g[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t\t+ (g[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t\t+ (g[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t\t+ (g[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t\t+ (g[22] & p[23] & p[24] & p[25] & p[26] & p[27])
\t\t\t+ (g[23] & p[24] & p[25] & p[26] & p[27])
\t\t\t+ (g[24] & p[25] & p[26] & p[27]) + (g[25] & p[26] & p[27]) + (g[26] & p[27]) + g[27];
\t\tassign carry_g[29] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14] & p[15 & p[16]] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[23] & p[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[24] & p[25] & p[26] & p[27] & p[28])
\t\t\t+ (g[25] & p[26] & p[27] & p[28]) + (g[26] & p[27] & p[28]) + (g[27] & p[28]) + g[28];
\t\tassign carry_g[30] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14] & p[15 & p[16]] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[24] & p[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[25] & p[26] & p[27] & p[28] & p[29])
\t\t\t+ (g[26] & p[27] & p[28] & p[29]) + (g[27] & p[28] & p[29]) + (g[28] & p[29]) + g[29];
\t\tassign carry_g[31] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14] & p[15 & p[16]] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[25] & p[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[26] & p[27] & p[28] & p[29] & p[30])
\t\t\t+ (g[27] & p[28] & p[29] & p[30]) + (g[28] & p[29] & p[30]) + (g[29] & p[30]) + g[30];
\t\tassign carry_g[32] = (g[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t + (g[1] & p[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[2] & p[3] & p[4] & p[5] & p[6]& p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t + (g[3] & p[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t + (g[4] & p[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[5] & p[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t + (g[6] & p[7] & p[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t + (g[7] & p[8] & p[9] & p[10]& p[11] & p[12] & p[13] & p[14] & p[15 & p[16]] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t + (g[8] & p[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t + (g[9] & p[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[10] & p[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[11] & p[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[12] & p[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[13] & p[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[14] & p[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[15] & p[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[16] & p[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[17] & p[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[18] & p[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[19] & p[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[20] & p[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[21] & p[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[22] & p[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[23] & p[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[24] & p[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[25] & p[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[26] & p[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[27] & p[28] & p[29] & p[30] & p[31])
\t\t\t+ (g[28] & p[29] & p[30] & p[31]) + (g[29] & p[30] & p[31]) + (g[30] & p[31]) + g[31];
\tend
\t/*Carry assignments*/
\tbegin
\t\tassign carry[0] = carryin;
\t\tassign carry[1] = carry_p[1] + carry_g[1];
\t\tassign carry[2] = carry_p[2] + carry_g[2];
\t\tassign carry[3] = carry_p[3] + carry_g[3];
\t\tassign carry[4] = carry_p[4] + carry_g[4];
\t\tassign carry[5] = carry_p[5] + carry_g[5];
\t\tassign carry[6] = carry_p[6] + carry_g[6];
\t\tassign carry[7] = carry_p[7] + carry_g[7];
\t\tassign carry[8] = carry_p[8] + carry_g[8];
\t\tassign carry[9] = carry_p[9] + carry_g[9];
\t\tassign carry[10] = carry_p[10] + carry_g[10];
\t\tassign carry[11] = carry_p[11] + carry_g[11];
\t\tassign carry[12] = carry_p[12] + carry_g[12];
\t\tassign carry[13] = carry_p[13] + carry_g[13];
\t\tassign carry[14] = carry_p[14] + carry_g[14];
\t\tassign carry[15] = carry_p[15] + carry_g[15];
\t\tassign carry[16] = carry_p[16] + carry_g[16];
\t\tassign carry[17] = carry_p[17] + carry_g[17];
\t\tassign carry[18] = carry_p[18] + carry_g[18];
\t\tassign carry[19] = carry_p[19] + carry_g[19];
\t\tassign carry[20] = carry_p[20] + carry_g[20];
\t\tassign carry[21] = carry_p[21] + carry_g[21];
\t\tassign carry[22] = carry_p[22] + carry_g[22];
\t\tassign carry[23] = carry_p[23] + carry_g[23];
\t\tassign carry[24] = carry_p[24] + carry_g[24];
\t\tassign carry[25] = carry_p[25] + carry_g[25];
\t\tassign carry[26] = carry_p[26] + carry_g[26];
\t\tassign carry[27] = carry_p[27] + carry_g[27];
\t\tassign carry[28] = carry_p[28] + carry_g[28];
\t\tassign carry[29] = carry_p[29] + carry_g[29];
\t\tassign carry[30] = carry_p[30] + carry_g[30];
\t\tassign carry[31] = carry_p[31] + carry_g[31];
\t\tassign flg_carry = carry_p[32] + carry_g[32];
\tend
\t/*Instantiated modules*/
\t
\tadder_1b add_b0( //Bit 0
\t.a(reg_a[0]),
\t.b(reg_b[0]),
\t.sum(out[0]),
\t.carry_in(carry[0]),
\t.carry_out()
\t);
\tadder_1b add_b1( //Bit 1
\t.a(reg_a[1]),
\t.b(reg_b[1]),
\t.sum(out[1]),
\t.carry_in(carry[1]),
\t.carry_out()
\t);\t
\tadder_1b add_b2( //Bit 2
\t.a(reg_a[2]),
\t.b(reg_b[2]),
\t.sum(out[2]),
\t.carry_in(carry[2]),
\t.carry_out()
\t);
\tadder_1b add_b3( //Bit 3
\t.a(reg_a[3]),
\t.b(reg_b[3]),
\t.sum(out[3]),
\t.carry_in(carry[3]),
\t.carry_out()
\t);\t
\tadder_1b add_b4( //Bit 4
\t.a(reg_a[4]),
\t.b(reg_b[4]),
\t.sum(out[4]),
\t.carry_in(carry[4]),
\t.carry_out()
\t);
\tadder_1b add_b5( //Bit 5
\t.a(reg_a[5]),
\t.b(reg_b[5]),
\t.sum(out[5]),
\t.carry_in(carry[5]),
\t.carry_out()
\t);\t
\tadder_1b add_b6( //Bit 6
\t.a(reg_a[6]),
\t.b(reg_b[6]),
\t.sum(out[6]),
\t.carry_in(carry[6]),
\t.carry_out()
\t);
\tadder_1b add_b7( //Bit 7
\t.a(reg_a[7]),
\t.b(reg_b[7]),
\t.sum(out[7]),
\t.carry_in(carry[7]),
\t.carry_out()
\t);\t
\t
\tadder_1b add_b8( //Bit 8
\t.a(reg_a[8]),
\t.b(reg_b[8]),
\t.sum(out[8]),
\t.carry_in(carry[8]),
\t.carry_out()
\t);
\tadder_1b add_b9( //Bit 9
\t.a(reg_a[9]),
\t.b(reg_b[9]),
\t.sum(out[9]),
\t.carry_in(carry[9]),
\t.carry_out()
\t);\t
\tadder_1b add_b10( //Bit 10
\t.a(reg_a[10]),
\t.b(reg_b[10]),
\t.sum(out[10]),
\t.carry_in(carry[10]),
\t.carry_out()
\t);
\tadder_1b add_b11( //Bit 11
\t.a(reg_a[11]),
\t.b(reg_b[11]),
\t.sum(out[11]),
\t.carry_in(carry[11]),
\t.carry_out()
\t);\t
\tadder_1b add_b12( //Bit 12
\t.a(reg_a[12]),
\t.b(reg_b[12]),
\t.sum(out[12]),
\t.carry_in(carry[12]),
\t.carry_out()
\t);
\tadder_1b add_b13( //Bit 13
\t.a(reg_a[13]),
\t.b(reg_b[13]),
\t.sum(out[13]),
\t.carry_in(carry[13]),
\t.carry_out()
\t);\t
\tadder_1b add_b14( //Bit 14
\t.a(reg_a[14]),
\t.b(reg_b[14]),
\t.sum(out[14]),
\t.carry_in(carry[14]),
\t.carry_out()
\t);
\tadder_1b add_b15( //Bit 15
\t.a(reg_a[15]),
\t.b(reg_b[15]),
\t.sum(out[15]),
\t.carry_in(carry[15]),
\t.carry_out()
\t);\t
\t
\tadder_1b add_b16( //Bit 16
\t.a(reg_a[16]),
\t.b(reg_b[16]),
\t.sum(out[16]),
\t.carry_in(carry[16]),
\t.carry_out()
\t);
\tadder_1b add_b17( //Bit 17
\t.a(reg_a[17]),
\t.b(reg_b[17]),
\t.sum(out[17]),
\t.carry_in(carry[17]),
\t.carry_out()
\t);\t
\tadder_1b add_b18( //Bit 18
\t.a(reg_a[18]),
\t.b(reg_b[18]),
\t.sum(out[18]),
\t.carry_in(carry[18]),
\t.carry_out()
\t);
\tadder_1b add_b19( //Bit 19
\t.a(reg_a[19]),
\t.b(reg_b[19]),
\t.sum(out[19]),
\t.carry_in(carry[19]),
\t.carry_out()
\t);\t
\tadder_1b add_b20( //Bit 20
\t.a(reg_a[20]),
\t.b(reg_b[20]),
\t.sum(out[20]),
\t.carry_in(carry[20]),
\t.carry_out()
\t);
\tadder_1b add_b21( //Bit 21
\t.a(reg_a[21]),
\t.b(reg_b[21]),
\t.sum(out[21]),
\t.carry_in(carry[21]),
\t.carry_out()
\t);\t
\tadder_1b add_b22( //Bit 22
\t.a(reg_a[22]),
\t.b(reg_b[22]),
\t.sum(out[22]),
\t.carry_in(carry[22]),
\t.carry_out()
\t);
\tadder_1b add_b23( //Bit 23
\t.a(reg_a[23]),
\t.b(reg_b[23]),
\t.sum(out[23]),
\t.carry_in(carry[23]),
\t.carry_out()
\t);\t
\t
\tadder_1b add_b24( //Bit 24
\t.a(reg_a[24]),
\t.b(reg_b[24]),
\t.sum(out[24]),
\t.carry_in(carry[24]),
\t.carry_out()
\t);
\tadder_1b add_b25( //Bit 25
\t.a(reg_a[25]),
\t.b(reg_b[25]),
\t.sum(out[25]),
\t.carry_in(carry[25]),
\t.carry_out()
\t);\t
\tadder_1b add_b26( //Bit 26
\t.a(reg_a[26]),
\t.b(reg_b[26]),
\t.sum(out[26]),
\t.carry_in(carry[26]),
\t.carry_out()
\t);
\tadder_1b add_b27( //Bit 27
\t.a(reg_a[27]),
\t.b(reg_b[27]),
\t.sum(out[27]),
\t.carry_in(carry[27]),
\t.carry_out()
\t);\t
\tadder_1b add_b28( //Bit 28
\t.a(reg_a[28]),
\t.b(reg_b[28]),
\t.sum(out[28]),
\t.carry_in(carry[28]),
\t.carry_out()
\t);
\tadder_1b add_b29( //Bit 29
\t.a(reg_a[29]),
\t.b(reg_b[29]),
\t.sum(out[29]),
\t.carry_in(carry[29]),
\t.carry_out()
\t);\t
\tadder_1b add_b30( //Bit 30
\t.a(reg_a[30]),
\t.b(reg_b[30]),
\t.sum(out[30]),
\t.carry_in(carry[30]),
\t.carry_out()
\t);
\tadder_1b add_b31( //Bit 31
\t.a(reg_a[31]),
\t.b(reg_b[31]),
\t.sum(out[31]),
\t.carry_in(carry[31]),
\t.carry_out()
\t);\t
\t
endmodule
|
/*
This file is part of Fusion-Core-ISA.
Fusion-Core-ISA is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Fusion-Core-ISA is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.
*/
module xor_32(
\tinput [31:0] a, //input values
\tinput [31:0] b,
\toutput [31:0] out //output value
\t);
\t//output is the XOR of a and b
\tassign out[0] \t= a[0] ^ b[0];
\tassign out[1] \t= a[1] ^ b[1];
\tassign out[2] \t= a[2] ^ b[2];
\tassign out[3] \t= a[3] ^ b[3];
\tassign out[4] \t= a[4] ^ b[4];
\tassign out[5] \t= a[5] ^ b[5];
\tassign out[6] \t= a[6] ^ b[6];
\tassign out[7] \t= a[7] ^ b[7];
\tassign out[8] \t= a[8] ^ b[8];
\tassign out[9] \t= a[9] ^ b[9];
\tassign out[10]\t= a[10] ^ b[10];
\tassign out[11] \t= a[11] ^ b[11];
\tassign out[12] \t= a[12] ^ b[12];
\tassign out[13] \t= a[13] ^ b[13];
\tassign out[14] \t= a[14] ^ b[14];
\tassign out[15] \t= a[15] ^ b[15];
\tassign out[16] \t= a[16] ^ b[16];
\tassign out[17] \t= a[17] ^ b[17];
\tassign out[18] \t= a[18] ^ b[18];
\tassign out[19] \t= a[19] ^ b[19];
\tassign out[20] \t= a[20] ^ b[20];
\tassign out[21] \t= a[21] ^ b[21];
\tassign out[22] \t= a[22] ^ b[22];
\tassign out[23] \t= a[23] ^ b[23];
\tassign out[24] \t= a[24] ^ b[24];
\tassign out[25]\t= a[25] ^ b[25];
\tassign out[26] \t= a[26] ^ b[26];
\tassign out[27] \t= a[27] ^ b[27];
\tassign out[28] \t= a[28] ^ b[28];
\tassign out[29] \t= a[29] ^ b[29];
\tassign out[30] \t= a[30] ^ b[30];
\tassign out[31] \t= a[31] ^ b[31];
endmodule
|
module Quadrature(clk, enc_a, enc_b, count);\r
input clk;\r
input enc_a;\r
input enc_b;\r
output count;\r
\r
reg signed [15:0] count;\r
\r
wire [1:0] cur_state;\r
reg [1:0] last_state;\r
\r
// Debounce encoder inputs\r
Debouncer dbc_a(clk, enc_a, cur_state[0]);\r
Debouncer dbc_b(clk, enc_b, cur_state[1]);\r
\r
\r
always @ (posedge clk) begin\r
case ({last_state, cur_state})\r
4'b0001: count <= count + 1;\r
4'b0111: count <= count + 1;\r
4'b1110: count <= count + 1;\r
4'b1000: count <= count + 1;\r
\r
4'b0010: count <= count - 1;\r
4'b1011: count <= count - 1;\r
4'b1101: count <= count - 1;\r
4'b0100: count <= count - 1;\r
endcase\r
last_state <= cur_state;\r
end\r
endmodule\r
|
`include "Motor.v"\r
`include "Servo.v"\r
`include "Encoder.v"\r
`include "Debouncer.v"\r
`include "Quadrature.v"\r
`include "Pwm.v"\r
\r
module happyio(clk, ad, a, aout, ale, nRD, nWR, mot0, mot1, mot2, mot3, mot4, mot5, Servo, Enc, Digital, ramce);\r
\t// clock\r
\tinput clk;\r
\t// AVR XMEM interface\r
\tinput [7:0] a;\r
\tinout [7:0] ad;\r
\tinput ale;\r
\tinput nRD, nWR;\r
\t// address [0..7] output\r
\toutput [7:0] aout;\r
\t// IO Pins\r
\toutput [1:0] mot0;\r
\toutput [1:0] mot1;\r
\toutput [1:0] mot2;\r
\toutput [1:0] mot3;\r
\toutput [1:0] mot4;\r
\toutput [1:0] mot5;\r
\tinput [3:0] Enc;\r
\tinout [7:0] Digital;\r
\toutput [5:0] Servo;\r
\toutput ramce;\r
\r
\t\r
\t// tri-state digital IO\r
\treg [7:0] digitalPinMode = 8\'h00;\r
\twire [7:0] digitalOutput;\r
\treg [7:0] digitalPwm [7:0];\r
\r
\tassign Digital[0] = digitalPinMode[0] ? digitalOutput[0] : 1\'bz;\r
\tassign Digital[1] = digitalPinMode[1] ? digitalOutput[1] : 1\'bz;\r
\tassign Digital[2] = digitalPinMode[2] ? digitalOutput[2] : 1\'bz;\r
\tassign Digital[3] = digitalPinMode[3] ? digitalOutput[3] : 1\'bz;\r
\tassign Digital[4] = digitalPinMode[4] ? digitalOutput[4] : 1\'bz;\r
\tassign Digital[5] = digitalPinMode[5] ? digitalOutput[5] : 1\'bz;\r
\tassign Digital[6] = digitalPinMode[6] ? digitalOutput[6] : 1\'bz;\r
\tassign Digital[7] = digitalPinMode[7] ? digitalOutput[7] : 1\'bz;\r
\r
\t//reg ramce;\r
\r
\t// internal\r
\treg [15:0] addr;\r
\twire\t [7:0] aout;\r
\twire [7:0] data;\r
\treg [7:0] dataOut;\r
\r
\t// registers (motors)\r
\treg [1:0] ma1_ctl;\r
\treg [7:0] ma1_vel;\r
\treg [1:0] ma2_ctl;\r
\treg [7:0] ma2_vel;\r
\treg [1:0] mb1_ctl;\r
\treg [7:0] mb1_vel;\r
\treg [1:0] mb2_ctl;\r
\treg [7:0] mb2_vel;\r
\treg [1:0] mc1_ctl;\r
\treg [7:0] mc1_vel;\r
\treg [1:0] mc2_ctl;\r
\treg [7:0] mc2_vel;\r
\t\r
\t// registers (encoders)\r
\twire [15:0] enc0;\r
\twire [15:0] enc1;\r
\twire [15:0] enc2;\r
\twire [15:0] enc3;\r
\t\r
\t// registers (servos)\r
\treg [9:0] srv0;\r
\treg [9:0] srv1;\r
\treg [9:0] srv2;\r
\treg [9:0] srv3;\r
\treg [9:0] srv4;\r
\treg [9:0] srv5;\r
reg srv0_e;\r
reg srv1_e;\r
reg srv2_e;\r
reg srv3_e;\r
reg srv4_e;\r
reg srv5_e;\r
\r
\treg [7:0] tempLo;\r
\treg [7:0] tempHi;\r
\r
\t// bidirectional data bus\r
\t assign ad = (addr[15] | nRD ) ? 8\'hzz : dataOut ;\r
\t//assign ad = 8\'hzz;\r
\t\r
\t// latch the lower 8 bits of address\r
\tassign data = ad;\r
\talways @(negedge ale) begin\r
\t\t\taddr[7:0] = ad[7:0];\r
\t\t\taddr[15:8] = a[7:0];\r
\tend\r
\r
\tassign aout[7:0] = addr[7:0];\r
\r
\t// assign ram ce\t\r
\tassign ramce = ~addr[15];\r
\t//always @ (addr[15] or nRD or nWR) begin\r
\t//\tramce = ~addr[15];\r
\t//end \r
\r
\t// read control\r
\talways @ (negedge nRD)\r
\tbegin\r
\t\tcase (addr)\r
\t\t\t// 0x1100 - 0x110B : motors\r
\t\t\t16\'h1100:\tdataOut[1:0] = ma1_ctl;\r
\t\t\t16\'h1101:\tdataOut = ma1_vel;\r
\t\t\t16\'h1102:\tdataOut[1:0] = ma2_ctl;\r
\t\t\t16\'h1103:\tdataOut = ma2_vel;\r
\t\t\t16\'h1104:\tdataOut[1:0] = mb1_ctl;\r
\t\t\t16\'h1105:\tdataOut = mb1_vel;\r
\t\t\t16\'h1106:\tdataOut[1:0] = mb2_ctl;\r
\t\t\t16\'h1107:\tdataOut = mb2_vel;\r
\t\t\t16\'h1108:\tdataOut[1:0] = mc1_ctl;\r
\t\t\t16\'h1109:\tdataOut = mc1_vel;\r
\t\t\t16\'h110A:\tdataOut[1:0] = mc2_ctl;\r
\t\t\t16\'h110B:\tdataOut = mc2_vel;\r
\t\t\t// 0x110C - 0x1113 : encoders\r
\t\t\t16\'h110C:\t{tempHi, dataOut} = enc0;\r
\t\t\t16\'h110D:\tdataOut = tempHi;\r
\t\t\t16\'h110E:\t{tempHi, dataOut} = enc1;\r
\t\t\t16\'h110F:\tdataOut = tempHi;\r
\t\t\t16\'h1110:\t{tempHi, dataOut} = enc2;\r
\t\t\t16\'h1111:\tdataOut = tempHi;\r
\t\t\t16\'h1112:\t{tempHi, dataOut} = enc3;\r
\t\t\t16\'h1113:\tdataOut = tempHi;\r
\t\t\t// 0x1120 - 0x112B : servos\r
\t\t\t/*\r
\t\t\t16\'h1118:\tdataOut = srv0;\r
\t\t\t16\'h1119:\tdataOut = srv1;\r
\t\t\t16\'h111A:\tdataOut = srv2;\r
\t\t\t16\'h111B:\tdataOut = srv3;\r
\t\t\t16\'h111C:\tdataOut = srv4;\r
\t\t\t16\'h111D:\tdataOut = srv5;\r
\t\t\t*/\r
\t\t\t// 0x11 : digital in\r
\t\t\t16\'h111E:\tdataOut = Digital;\r
\t\t\t// 0x11FE : major version\r
\t\t\t16\'h11FE:\tdataOut = 0;\r
\t\t\t// 0x11FF : minor version\r
\t\t\t16\'h11FF:\tdataOut = 7;\r
\t\tendcase\r
\tend\r
\t\r
\t// write control\r
\talways @ (negedge nWR or posedge clk)\r
\tbegin \r
\t\tif (!nWR)\r
\t\tcase (addr)\r
\t\t\t// 0x1100 - 0x110B : motors\r
\t\t\t16\'h1100:\tma1_ctl = data;\r
\t\t\t16\'h1101:\tma1_vel = data;\r
\t\t\t16\'h1102:\tma2_ctl = data;\r
\t\t\t16\'h1103:\tma2_vel = data;\r
\t\t\t16\'h1104:\tmb1_ctl = data;\r
\t\t\t16\'h1105:\tmb1_vel = data;\r
\t\t\t16\'h1106:\tmb2_ctl = data;\r
\t\t\t16\'h1107:\tmb2_vel = data;\r
\t\t\t16\'h1108:\tmc1_ctl = data;\r
\t\t\t16\'h1109:\tmc1_vel = data;\r
\t\t\t16\'h110A:\tmc2_ctl = data;\r
\t\t\t16\'h110B:\tmc2_vel = data;\r
\t\t\t// 0x110C - 0x1113 : encoders\r
\t\t\t// ...\r
\t\t\t// 0x1120 - 0x112B : servos\r
\t\t\t16\'h1120:\ttempLo = data;\r
\t\t\t16\'h1121: \tbegin\r
\t\t\t\t\t\t\tsrv0 = {data[1:0],tempLo}; \r
\t\t\t\t\t\t\tsrv0_e = data[7];\r
\t\t\t\t\t\tend\r
\t\t\t16\'h1122:\ttempLo = data;\r
\t\t\t16\'h1123: \tbegin\r
\t\t\t\t\t\t\tsrv1 = {data[1:0],tempLo}; \r
\t\t\t\t\t\t\tsrv1_e = data[7];\r
\t\t\t\t\t\tend\r
\t\t\t16\'h1124:\ttempLo = data;\r
\t\t\t16\'h1125: \tbegin\r
\t\t\t\t\t\t\tsrv2 = {data[1:0],tempLo}; \r
\t\t\t\t\t\t\tsrv2_e = data[7];\r
\t\t\t\t\t\tend\r
\t\t\t16\'h1126:\ttempLo = data;\r
\t\t\t16\'h1127: \tbegin\r
\t\t\t\t\t\t\tsrv3 = {data[1:0],tempLo}; \r
\t\t\t\t\t\t\tsrv3_e = data[7];\r
\t\t\t\t\t\tend\r
\t\t\t16\'h1128:\ttempLo = data;\r
\t\t\t16\'h1129: \tbegin\r
\t\t\t\t\t\t\tsrv4 = {data[1:0],tempLo}; \r
\t\t\t\t\t\t\tsrv4_e = data[7];\r
\t\t\t\t\t\tend\r
\t\t\t16\'h112A:\ttempLo = data;\r
\t\t\t16\'h112B: \tbegin\r
\t\t\t\t\t\t\tsrv5 = {data[1:0],tempLo}; \r
\t\t\t\t\t\t\tsrv5_e = data[7];\r
\t\t\t\t\t\tend\r
\r
\r
\t\t\t// Digital I/O mode\r
\t\t\t16\'h1130:\tdigitalPinMode = data;\r
\r
\t\t\t// Digital Output\r
\t\t\t16\'h1131:\tdigitalPwm[0] = data;\r
\t\t\t16\'h1132:\tdigitalPwm[1] = data;\r
\t\t\t16\'h1133:\tdigitalPwm[2] = data;\r
\t\t\t16\'h1134:\tdigitalPwm[3] = data;\r
\t\t\t16\'h1135:\tdigitalPwm[4] = data;\r
\t\t\t16\'h1136:\tdigitalPwm[5] = data;\r
\t\t\t16\'h1137:\tdigitalPwm[6] = data;\r
\t\t\t16\'h1138:\tdigitalPwm[7] = data;\r
\t\t\t// ...\r
\t\tendcase\r
\tend\r
\t\r
\r
\t// motor drivers\r
\tMotor motor0(clk,mot0,ma2_ctl,ma2_vel);\r
\tMotor motor1(clk,mot1,ma1_ctl,ma1_vel);\r
\tMotor motor2(clk,mot2,mb2_ctl,mb2_vel);\r
\tMotor motor3(clk,mot3,mb1_ctl,mb1_vel);\r
\tMotor motor4(clk,mot4,mc2_ctl,mc2_vel);\r
\tMotor motor5(clk,mot5,mc1_ctl,mc1_vel);\r
\r
\t// encoder drivers\r
`ifndef QUADRATURE\r
\tEncoder encoder0(clk,Enc[0],enc0);\r
\tEncoder encoder1(clk,Enc[1],enc1);\r
\tEncoder encoder2(clk,Enc[2],enc2);\r
\tEncoder encoder3(clk,Enc[3],enc3);\r
`else\r
\tQuadrature quad0(clk,Enc[0],Enc[1], enc0);\r
\tQuadrature quad1(clk,Enc[2],Enc[3], enc1);\r
`endif\r
\r
\t// servo drivers\r
\tServo servo0(clk,Servo[0],srv0, srv0_e);\r
\tServo servo1(clk,Servo[1],srv1, srv1_e);\r
\tServo servo2(clk,Servo[2],srv2, srv2_e);\r
\tServo servo3(clk,Servo[3],srv3, srv3_e);\r
\tServo servo4(clk,Servo[4],srv4, srv4_e);\r
\tServo servo5(clk,Servo[5],srv5, srv5_e);\r
\r
\t// digital IO\r
\tPwm pwm0(clk, digitalOutput[0], digitalPwm[0]);\r
\tPwm pwm1(clk, digitalOutput[1], digitalPwm[1]);\r
\tPwm pwm2(clk, digitalOutput[2], digitalPwm[2]);\r
\tPwm pwm3(clk, digitalOutput[3], digitalPwm[3]);\r
\tPwm pwm4(clk, digitalOutput[4], digitalPwm[4]);\r
\tPwm pwm5(clk, digitalOutput[5], digitalPwm[5]);\r
\tPwm pwm6(clk, digitalOutput[6], digitalPwm[6]);\r
\tPwm pwm7(clk, digitalOutput[7], digitalPwm[7]);\r
\r
endmodule\r
|
module Servo(clk, out, pos, enable);\r
\tinput clk;\r
\toutput out;\r
\treg out;\r
\tinput [9:0] pos;\r
input enable;\r
\r
\t// fpga4fun\r
\tparameter ClkDiv = 31;\r
\tparameter PulseCountSize = 11;\r
\r
\treg [6:0] ClkCount;\r
\treg [PulseCountSize:0] PulseCount;\r
\treg ClkTick;\r
\r
\talways @(posedge clk) begin\r
\t\tClkTick <= (ClkCount==ClkDiv-2);\r
\r
\t\tif(ClkTick) \r
\t\t\tClkCount <= 0; \r
\t\telse \r
\t\t\tClkCount <= ClkCount + 1;\r
\r
\t\tif(ClkTick) \r
\t\t\tPulseCount <= PulseCount + 1;\r
\t\r
\t\tout = enable ? (PulseCount < {2'b00, pos}) : 0;\r
end\r
\t// fpga4fun\r
\r
endmodule\r
|
module Pwm(clk, out, val);\r
\tinput clk;\r
\toutput reg out;\r
\treg [7:0] pwmcount = 0;\r
\tinput [7:0] val;\r
\t\r
\talways @ (posedge clk) begin\r
\t\tpwmcount <= pwmcount + 1;\r
if (val == 0) begin\r
out <= 0;\r
end else if (val == 255) begin\r
out <= 1;\r
end else if (pwmcount==0) begin\r
\t\t\tout <= 1;\r
\t\tend else if (pwmcount==val) begin\r
\t\t\tout <= 0;\r
end\r
\tend\r
endmodule\r
|
module Debouncer (clk, dirty, clean);
input clk;
input dirty;
output reg clean;
reg [6:0] debounce;
reg last_dirty;
always @ (posedge clk) begin
if (dirty != last_dirty) begin
last_dirty <= dirty;
debounce <= 0;
end else if (debounce == 127) begin
clean <= last_dirty;
end else begin
debounce <= debounce+1;
end
end
endmodule
|
module Encoder(clk, enc, count);\r
\tinput clk;\r
\tinput enc;\r
\treg enc_clean, enc_new;\r
\treg [7:0] debounce;\r
\toutput [15:0] count;\r
\treg [15:0] count;\r
\r
\talways @ (posedge clk)\r
if (enc != enc_new) begin enc_new <= enc; debounce <= 0; end\r
else if (debounce == 127) enc_clean <= enc_new;\r
else debounce <= debounce+1;\r
\r
\talways @ (posedge enc_clean)\r
\t\tcount <= count + 1;\r
\t\r
endmodule\r
|
module Motor(clk, out, ctl, vel);\r
\tinput clk;\r
\toutput [1:0] out;\r
\treg pwmout;\r
\treg [7:0] pwmcount;\r
\tinput [7:0] vel;\r
\tinput [1:0] ctl;\r
\t\r
\talways @ (posedge clk)\r
\tbegin\r
\t\tpwmcount <= pwmcount + 1;\r
\t\tif (pwmcount==0)\r
\t\t\tpwmout = 1;\r
\t\telse\r
\t\tif (pwmcount==vel)\r
\t\t\tpwmout = 0;\r
\tend\r
\t\r
\t\r
\twire fwd = (ctl==2'b01);\t\r
\twire rev = (ctl==2'b10);\t\r
//\twire brake = (ctl==2'b00);\r
\r
\tassign out[0] = fwd ? pwmout : 0;\r
\tassign out[1] = rev ? pwmout : 0;\r
\t\r
endmodule\r
|
LIBAVCODEC_$MAJOR {
global: *;
};
|
LIBAVFORMAT_$MAJOR {
global: *;
};
|
LIBSWSCALE_$MAJOR {
global: swscale_*; sws_*; ff_*;
local: *;
};
|
LIBPOSTPROC_$MAJOR {
global: postproc_*; pp_*;
local: *;
};
|
LIBAVUTIL_$MAJOR {
global: av_*; ff_*; avutil_*;
local: *;
};
|
always @(negedge reset or posedge clk) begin
if (reset == 0) begin
d_out <= 16'h0000;
d_out_mem[resetcount] <= d_out;
laststoredvalue <= d_out;
end else begin
d_out <= d_out + 1'b1;
end
end
always @(bufreadaddr)
bufreadval = d_out_mem[bufreadaddr]; |
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
//
// There are two modes:
// - lf_ed_toggle_mode == 0: the output is set low (resp. high) when a low
// (resp. high) edge/peak is detected, with hysteresis
// - lf_ed_toggle_mode == 1: the output is toggling whenever an edge/peak
// is detected.
// That way you can detect two consecutive edges/peaks at the same level (L/H)
//
// Output:
// - ssp_frame (wired to TIOA1 on the arm) for the edge detection/state
// - ssp_clk: cross_lo
`include "lp20khz_1MSa_iir_filter.v"
`include "lf_edge_detect.v"
module lo_edge_detect(
input pck0, input pck_divclk,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk,
output ssp_frame, input ssp_dout, output ssp_clk,
input cross_lo,
output dbg,
input lf_field,
input lf_ed_toggle_mode, input [7:0] lf_ed_threshold
);
wire tag_modulation = ssp_dout & !lf_field;
wire reader_modulation = !ssp_dout & lf_field & pck_divclk;
// No logic, straight through.
assign pwr_oe1 = 1\'b0; \t\t\t\t\t\t// not used in LF mode
assign pwr_oe3 = 1\'b0; \t\t\t\t\t\t// base antenna load = 33 Ohms
// when modulating, add another 33 Ohms and 10k Ohms in parallel:
assign pwr_oe2 = tag_modulation;
assign pwr_oe4 = tag_modulation;
assign ssp_clk = cross_lo;
assign pwr_lo = reader_modulation;
assign pwr_hi = 1\'b0;
// filter the ADC values
wire data_rdy;
wire [7:0] adc_filtered;
assign adc_clk = pck0;
lp20khz_1MSa_iir_filter adc_filter(pck0, adc_d, data_rdy, adc_filtered);
// detect edges
wire [7:0] high_threshold, highz_threshold, lowz_threshold, low_threshold;
wire [7:0] max, min;
wire edge_state, edge_toggle;
lf_edge_detect lf_ed(pck0, adc_filtered, lf_ed_threshold,
\tmax, min,
\thigh_threshold, highz_threshold, lowz_threshold, low_threshold,
\tedge_state, edge_toggle);
assign dbg = lf_ed_toggle_mode ? edge_toggle : edge_state;
assign ssp_frame = lf_ed_toggle_mode ? edge_toggle : edge_state;
endmodule
|
`include "lo_simulate.v"
/*
\tpck0\t\t\t- input main 24Mhz clock (PLL / 4)
\t[7:0] adc_d\t\t- input data from A/D converter
\tpwr_lo\t\t\t- output to coil drivers (ssp_clk / 8)
\tadc_clk\t\t\t- output A/D clock signal
\tssp_frame\t\t- output SSS frame indicator (goes high while the 8 bits are shifted)
\tssp_din\t\t\t- output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
\tssp_clk\t\t\t- output SSP clock signal
\tck_1356meg\t\t- input unused
\tck_1356megb\t\t- input unused
\tssp_dout\t\t- input unused
\tcross_hi\t\t- input unused
\tcross_lo\t\t- input unused
\tpwr_hi\t\t\t- output unused, tied low
\tpwr_oe1\t\t\t- output unused, undefined
\tpwr_oe2\t\t\t- output unused, undefined
\tpwr_oe3\t\t\t- output unused, undefined
\tpwr_oe4\t\t\t- output unused, undefined
\tdbg\t\t\t\t- output alias for adc_clk
*/
module testbed_lo_simulate;
\treg pck0;
\treg [7:0] adc_d;
\twire pwr_lo;
\twire adc_clk;
\twire ck_1356meg;
\twire ck_1356megb;
\twire ssp_frame;
\twire ssp_din;
\twire ssp_clk;
\treg ssp_dout;
\twire pwr_hi;
\twire pwr_oe1;
\twire pwr_oe2;
\twire pwr_oe3;
\twire pwr_oe4;
\treg cross_lo;
\twire cross_hi;
\twire dbg;
\tlo_simulate #(5,200) dut(
\t.pck0(pck0),
\t.ck_1356meg(ck_1356meg),
\t.ck_1356megb(ck_1356megb),
\t.pwr_lo(pwr_lo),
\t.pwr_hi(pwr_hi),
\t.pwr_oe1(pwr_oe1),
\t.pwr_oe2(pwr_oe2),
\t.pwr_oe3(pwr_oe3),
\t.pwr_oe4(pwr_oe4),
\t.adc_d(adc_d),
\t.adc_clk(adc_clk),
\t.ssp_frame(ssp_frame),
\t.ssp_din(ssp_din),
\t.ssp_dout(ssp_dout),
\t.ssp_clk(ssp_clk),
\t.cross_hi(cross_hi),
\t.cross_lo(cross_lo),
\t.dbg(dbg)
\t);
\tinteger i, counter=0;
\t// main clock
\talways #5 pck0 = !pck0;
\t//cross_lo is not really synced to pck0 but it\'s roughly pck0/192 (24Mhz/192=125Khz)
\ttask crank_dut;
\tbegin
\t\t@(posedge pck0) ;
\t\tcounter = counter + 1;
\t\tif (counter == 192) begin
\t\t\tcounter = 0;
\t\t\tssp_dout = $random;
\t\t\tcross_lo = 1;
\t\tend else begin
\t\t\tcross_lo = 0;
\t\tend
\t\t\t
\tend
\tendtask
\tinitial begin
\t\tpck0 = 0;
\t\tfor (i = 0 ; i < 4096 ; i = i + 1) begin
\t\t\tcrank_dut;
\t\tend
\t\t$finish;
\tend
endmodule // main
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
module clk_divider(input clk, input [7:0] divisor, output [7:0] div_cnt, output div_clk);
\treg [7:0] div_cnt_ = 0;
\treg div_clk_;
\tassign div_cnt = div_cnt_;
\tassign div_clk = div_clk_;
\talways @(posedge clk)
\tbegin
\t\tif(div_cnt == divisor) begin
\t\t\tdiv_cnt_ <= 8'd0;
\t\t\tdiv_clk_ = !div_clk_;
\t\tend else
\t\t\tdiv_cnt_ <= div_cnt_ + 1;
\tend
endmodule
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// testbench for lp20khz_1MSa_iir_filter
`include "lp20khz_1MSa_iir_filter.v"
`define FIN "tb_tmp/data.in"
`define FOUT "tb_tmp/data.filtered"
module lp20khz_1MSa_iir_filter_tb;
\tinteger fin, fout, r;
\treg clk;
\treg [7:0] adc_d;
\twire data_rdy;
\twire [7:0] adc_filtered;
\tinitial
\tbegin
\t\tclk = 0;
\t\tfin = $fopen(`FIN, "r");
\t\tif (!fin) begin
\t\t\t$display("ERROR: can\'t open the data file");
\t\t\t$finish;
\t\tend
\t\tfout = $fopen(`FOUT, "w+");
\t\tif (!$feof(fin))
\t\t\tadc_d = $fgetc(fin); // read the first value
\tend
\talways
\t\t# 1 clk = !clk;
\talways @(posedge clk)
\t\tif (data_rdy) begin
\t\t\tif ($time > 1)
\t\t\t\tr = $fputc(adc_filtered, fout);\t\t\t\t
\t\t\tif (!$feof(fin))
\t\t\t\tadc_d <= $fgetc(fin);
\t\t\telse begin
\t\t\t\t$fclose(fin);
\t\t\t\t$fclose(fout);
\t\t\t\t$finish;\t\t\t\t
\t\t\tend
\t\tend
\t// module to test
\tlp20khz_1MSa_iir_filter filter(clk, adc_d, data_rdy, adc_filtered);
endmodule
|
//-----------------------------------------------------------------------------
// The way that we connect things in low-frequency read mode. In this case
// we are generating the unmodulated low frequency carrier.
// The A/D samples at that same rate and the result is serialized.
//
// Jonathan Westhues, April 2006
// iZsh <izsh at fail0verflow.com>, June 2014
//-----------------------------------------------------------------------------
module lo_read(
\tinput pck0, input [7:0] pck_cnt, input pck_divclk,
\toutput pwr_lo, output pwr_hi,
\toutput pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
\tinput [7:0] adc_d, output adc_clk,
\toutput ssp_frame, output ssp_din, output ssp_clk,
\toutput dbg,
\tinput lf_field
);
reg [7:0] to_arm_shiftreg;
// this task also runs at pck0 frequency (24Mhz) and is used to serialize
// the ADC output which is then clocked into the ARM SSP.
// because pck_divclk always transitions when pck_cnt = 0 we use the
// pck_div counter to sync our other signals off it
// we read the ADC value when pck_cnt=7 and shift it out on counts 8..15
always @(posedge pck0)
begin
\tif((pck_cnt == 8'd7) && !pck_divclk)
\t\tto_arm_shiftreg <= adc_d;
\telse begin
\t\tto_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
\t\t// simulation showed a glitch occuring due to the LSB of the shifter
\t\t// not being set as we shift bits out
\t\t// this ensures the ssp_din remains low after a transfer and suppresses
\t\t// the glitch that would occur when the last data shifted out ended in
\t\t// a 1 bit and the next data shifted out started with a 0 bit
\t\tto_arm_shiftreg[0] <= 1'b0;
\tend
end
// ADC samples on falling edge of adc_clk, data available on the rising edge
// example of ssp transfer of binary value 1100101
// start of transfer is indicated by the rise of the ssp_frame signal
// ssp_din changes on the rising edge of the ssp_clk clock and is clocked into
// the ARM by the falling edge of ssp_clk
// _______________________________
// ssp_frame__| |__
// _______ ___ ___
// ssp_din __| |_______| |___| |______
// _ _ _ _ _ _ _ _ _ _
// ssp_clk |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
// serialized SSP data is gated by ant_lo to suppress unwanted signal
assign ssp_din = to_arm_shiftreg[7] && !pck_divclk;
// SSP clock always runs at 24Mhz
assign ssp_clk = pck0;
// SSP frame is gated by ant_lo and goes high when pck_divider=8..15
assign ssp_frame = (pck_cnt[7:3] == 5'd1) && !pck_divclk;
// unused signals tied low
assign pwr_hi = 1'b0;
assign pwr_oe1 = 1'b0;
assign pwr_oe2 = 1'b0;
assign pwr_oe3 = 1'b0;
assign pwr_oe4 = 1'b0;
// this is the antenna driver signal
assign pwr_lo = lf_field & pck_divclk;
// ADC clock out of phase with antenna driver
assign adc_clk = ~pck_divclk;
// ADC clock also routed to debug pin
assign dbg = adc_clk;
endmodule
|
//-----------------------------------------------------------------------------
// Jonathan Westhues, March 2006
// iZsh <izsh at fail0verflow.com>, June 2014
//-----------------------------------------------------------------------------
`include "lo_read.v"
`include "lo_passthru.v"
`include "lo_edge_detect.v"
`include "util.v"
`include "clk_divider.v"
module fpga_lf(
\tinput spck, output miso, input mosi, input ncs,
\tinput pck0, input ck_1356meg, input ck_1356megb,
\toutput pwr_lo, output pwr_hi,
\toutput pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
\tinput [7:0] adc_d, output adc_clk, output adc_noe,
\toutput ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
\tinput cross_hi, input cross_lo,
\toutput dbg
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [7:0] divisor;
reg [7:0] conf_word;
reg [7:0] user_byte1;
always @(posedge ncs)
begin
\tcase(shift_reg[15:12])
\t\t4\'b0001:
\t\t\tbegin
\t\t\t\tconf_word <= shift_reg[7:0];
\t\t\t\tif (shift_reg[7:0] == 8\'b00000001) begin // LF edge detect
\t\t\t\t\tuser_byte1 <= 127; // default threshold
\t\t\t\tend
\t\t\tend
\t\t4\'b0010: divisor <= shift_reg[7:0];\t\t\t// FPGA_CMD_SET_DIVISOR
\t\t4\'b0011: user_byte1 <= shift_reg[7:0];\t\t// FPGA_CMD_SET_USER_BYTE1
\tendcase
end
always @(posedge spck)
begin
\tif(~ncs)
\tbegin
\t\tshift_reg[15:1] <= shift_reg[14:0];
\t\tshift_reg[0] <= mosi;
\tend
end
wire [2:0] major_mode = conf_word[7:5];
// For the low-frequency configuration:
wire lf_field = conf_word[0];
wire lf_ed_toggle_mode = conf_word[1]; // for lo_edge_detect
wire [7:0] lf_ed_threshold = user_byte1;
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA\'s
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
wire [7:0] pck_cnt;
wire pck_divclk;
clk_divider div_clk(pck0, divisor, pck_cnt, pck_divclk);
lo_read lr(
\tpck0, pck_cnt, pck_divclk,
\tlr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
\tadc_d, lr_adc_clk,
\tlr_ssp_frame, lr_ssp_din, lr_ssp_clk,
\tlr_dbg, lf_field
);
lo_passthru lp(
\tpck_divclk,
\tlp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,
\tlp_adc_clk,
\tlp_ssp_din, ssp_dout,
\tcross_lo,
\tlp_dbg
);
lo_edge_detect le(
\tpck0, pck_divclk,
\tle_pwr_lo, le_pwr_hi, le_pwr_oe1, le_pwr_oe2, le_pwr_oe3, le_pwr_oe4,
\tadc_d, le_adc_clk,
\tle_ssp_frame, ssp_dout, le_ssp_clk,
\tcross_lo,
\tle_dbg,
\tlf_field,
\tlf_ed_toggle_mode, lf_ed_threshold
);
// Major modes:
// 000 -- LF reader (generic)
// 001 -- LF edge detect (generic)
// 010 -- LF passthrough
mux8 mux_ssp_clk\t\t(major_mode, ssp_clk, lr_ssp_clk, le_ssp_clk, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_ssp_din\t\t(major_mode, ssp_din, lr_ssp_din, 1\'b0, lp_ssp_din, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_ssp_frame\t\t(major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_pwr_oe1\t\t(major_mode, pwr_oe1, lr_pwr_oe1, le_pwr_oe1, lp_pwr_oe1, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_pwr_oe2\t\t(major_mode, pwr_oe2, lr_pwr_oe2, le_pwr_oe2, lp_pwr_oe2, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_pwr_oe3\t\t(major_mode, pwr_oe3, lr_pwr_oe3, le_pwr_oe3, lp_pwr_oe3, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_pwr_oe4\t\t(major_mode, pwr_oe4, lr_pwr_oe4, le_pwr_oe4, lp_pwr_oe4, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_pwr_lo\t\t\t(major_mode, pwr_lo, lr_pwr_lo, le_pwr_lo, lp_pwr_lo, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_pwr_hi\t\t\t(major_mode, pwr_hi, lr_pwr_hi, le_pwr_hi, lp_pwr_hi, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_adc_clk\t\t(major_mode, adc_clk, lr_adc_clk, le_adc_clk, lp_adc_clk, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_dbg\t\t\t(major_mode, dbg, lr_dbg, le_dbg, lp_dbg, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
// In all modes, let the ADC\'s outputs be enabled.
assign adc_noe = 1\'b0;
endmodule
|
`include "fpga.v"
module testbed_fpga;
reg spck, mosi, ncs;
wire miso;
reg pck0i, ck_1356meg, ck_1356megb;
wire pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
reg [7:0] adc_d;
wire adc_clk, adc_noe;
reg ssp_dout;
wire ssp_frame, ssp_din, ssp_clk;
fpga dut(
spck, miso, mosi, ncs,
pck0i, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk, adc_noe,
ssp_frame, ssp_din, ssp_dout, ssp_clk
);
\tinteger i;
\tinitial begin
\t\t// init inputs
\t\t#5 ncs=1;
\t\t#5 spck = 1;
\t\t#5 mosi = 1;
\t\t#50 ncs=0;
\t\tfor (i = 0 ; i < 8 ; i = i + 1) begin
\t\t\t#5 mosi = $random;
\t\t\t#5 spck = 0;
\t\t\t#5 spck = 1;
\t\tend
\t\t#5 ncs=1;
\t\t#50 ncs=0;
\t\tfor (i = 0 ; i < 8 ; i = i + 1) begin
\t\t\t#5 mosi = $random;
\t\t\t#5 spck = 0;
\t\t\t#5 spck = 1;
\t\tend
\t\t#5 ncs=1;
\t\t#50 mosi=1;
\t\t$finish;
\tend
\t
endmodule // main
|
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
// iZsh <izsh at fail0verflow.com>, June 2014
//-----------------------------------------------------------------------------
`include "hi_read_tx.v"
`include "hi_read_rx_xcorr.v"
`include "hi_simulate.v"
`include "hi_iso14443a.v"
`include "util.v"
module fpga_hf(
\tinput spck, output miso, input mosi, input ncs,
\tinput pck0, input ck_1356meg, input ck_1356megb,
\toutput pwr_lo, output pwr_hi,
\toutput pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
\tinput [7:0] adc_d, output adc_clk, output adc_noe,
\toutput ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
\tinput cross_hi, input cross_lo,
\toutput dbg
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [7:0] conf_word;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
\tcase(shift_reg[15:12])
\t\t4\'b0001: conf_word <= shift_reg[7:0];\t\t// FPGA_CMD_SET_CONFREG
\tendcase
end
always @(posedge spck)
begin
\tif(~ncs)
\tbegin
\t\tshift_reg[15:1] <= shift_reg[14:0];
\t\tshift_reg[0] <= mosi;
\tend
end
wire [2:0] major_mode;
assign major_mode = conf_word[7:5];
// For the high-frequency transmit configuration: modulation depth, either
// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
// some fraction of the buffers)
wire hi_read_tx_shallow_modulation = conf_word[0];
// For the high-frequency receive correlator: frequency against which to
// correlate.
wire hi_read_rx_xcorr_848 = conf_word[0];
// and whether to drive the coil (reader) or just short it (snooper)
wire hi_read_rx_xcorr_snoop = conf_word[1];
// Divide the expected subcarrier frequency for hi_read_rx_xcorr by 4
wire hi_read_rx_xcorr_quarter = conf_word[2];
// For the high-frequency simulated tag: what kind of modulation to use.
wire [2:0] hi_simulate_mod_type = conf_word[2:0];
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA\'s
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
hi_read_tx ht(
\tpck0, ck_1356meg, ck_1356megb,
\tht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
\tadc_d, ht_adc_clk,
\tht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
\tcross_hi, cross_lo,
\tht_dbg,
\thi_read_tx_shallow_modulation
);
hi_read_rx_xcorr hrxc(
\tpck0, ck_1356meg, ck_1356megb,
\thrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3,\thrxc_pwr_oe4,
\tadc_d, hrxc_adc_clk,
\thrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
\tcross_hi, cross_lo,
\thrxc_dbg,
\thi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
);
hi_simulate hs(
\tpck0, ck_1356meg, ck_1356megb,
\ths_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
\tadc_d, hs_adc_clk,
\ths_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
\tcross_hi, cross_lo,
\ths_dbg,
\thi_simulate_mod_type
);
hi_iso14443a hisn(
\tpck0, ck_1356meg, ck_1356megb,
\thisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3,\thisn_pwr_oe4,
\tadc_d, hisn_adc_clk,
\thisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
\tcross_hi, cross_lo,
\thisn_dbg,
\thi_simulate_mod_type
);
// Major modes:
// 000 -- HF reader, transmitting to tag; modulation depth selectable
// 001 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
// 010 -- HF simulated tag
// 011 -- HF ISO14443-A
// 111 -- everything off
mux8 mux_ssp_clk\t\t(major_mode, ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_ssp_din\t\t(major_mode, ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_ssp_frame\t\t(major_mode, ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_pwr_oe1\t\t(major_mode, pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_pwr_oe2\t\t(major_mode, pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_pwr_oe3\t\t(major_mode, pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_pwr_oe4\t\t(major_mode, pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_pwr_lo\t\t\t(major_mode, pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_pwr_hi\t\t\t(major_mode, pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_adc_clk\t\t(major_mode, adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
mux8 mux_dbg\t\t\t(major_mode, dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, 1\'b0, 1\'b0, 1\'b0, 1\'b0);
// In all modes, let the ADC\'s outputs be enabled.
assign adc_noe = 1\'b0;
endmodule
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// track min and max peak values (envelope follower)
//
// NB: the min value (resp. max value) is updated only when the next high peak
// (resp. low peak) is reached/detected, since you can't know it isn't a
// local minima (resp. maxima) until then.
// This also means the peaks are detected with an unpredictable delay.
// This algorithm therefore can't be used directly for realtime peak detections,
// but it can be used as a simple envelope follower.
module min_max_tracker(input clk, input [7:0] adc_d, input [7:0] threshold,
\toutput [7:0] min, output [7:0] max);
\treg [7:0] min_val = 255;
\treg [7:0] max_val = 0;
\treg [7:0] cur_min_val = 255;
\treg [7:0] cur_max_val = 0;
\treg [1:0] state = 0;
\talways @(posedge clk)
\tbegin
\t\tcase (state)
\t\t0:
\t\t\tbegin
\t\t\t\tif (cur_max_val >= ({1'b0, adc_d} + threshold))
\t\t\t\t\tstate <= 2;
\t\t\t\telse if (adc_d >= ({1'b0, cur_min_val} + threshold))
\t\t\t\t\tstate <= 1;
\t\t\t\tif (cur_max_val <= adc_d)
\t\t\t\t\tcur_max_val <= adc_d;
\t\t\t\telse if (adc_d <= cur_min_val)
\t\t\t\t\tcur_min_val <= adc_d;\t\t\t\t\t
\t\t\tend
\t\t1:
\t\t\tbegin
\t\t\t\tif (cur_max_val <= adc_d)
\t\t\t\t\tcur_max_val <= adc_d;
\t\t\t\telse if (({1'b0, adc_d} + threshold) <= cur_max_val) begin
\t\t\t\t\tstate <= 2;
\t\t\t\t\tcur_min_val <= adc_d;
\t\t\t\t\tmax_val <= cur_max_val;
\t\t\t\tend
\t\t\tend
\t\t2:
\t\t\tbegin
\t\t\t\tif (adc_d <= cur_min_val)
\t\t\t\t\tcur_min_val <= adc_d;\t\t\t\t\t
\t\t\t\telse if (adc_d >= ({1'b0, cur_min_val} + threshold)) begin
\t\t\t\t\tstate <= 1;
\t\t\t\t\tcur_max_val <= adc_d;
\t\t\t\t\tmin_val <= cur_min_val;
\t\t\t\tend
\t\t\tend
\t\tendcase
\tend
\tassign min = min_val;
\tassign max = max_val;
endmodule
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// testbench for lf_edge_detect
`include "lf_edge_detect.v"
`define FIN "tb_tmp/data.filtered.gold"
`define FOUT_MIN "tb_tmp/data.min"
`define FOUT_MAX "tb_tmp/data.max"
`define FOUT_STATE "tb_tmp/data.state"
`define FOUT_TOGGLE "tb_tmp/data.toggle"
`define FOUT_HIGH "tb_tmp/data.high"
`define FOUT_HIGHZ "tb_tmp/data.highz"
`define FOUT_LOWZ "tb_tmp/data.lowz"
`define FOUT_LOW "tb_tmp/data.low"
module lf_edge_detect_tb;
\tinteger fin, fout_state, fout_toggle;
\tinteger fout_high, fout_highz, fout_lowz, fout_low, fout_min, fout_max;
\tinteger r;
\treg clk = 0;
\treg [7:0] adc_d;
\twire adc_clk;
\twire data_rdy;
\twire edge_state;
\twire edge_toggle;
wire [7:0] high_threshold;
wire [7:0] highz_threshold;
wire [7:0] lowz_threshold;
wire [7:0] low_threshold;
wire [7:0] max;
wire [7:0] min;
\tinitial
\tbegin
\t\tclk = 0;
\t\tfin = $fopen(`FIN, "r");
\t\tif (!fin) begin
\t\t\t$display("ERROR: can\'t open the data file");
\t\t\t$finish;
\t\tend
\t\tfout_min = $fopen(`FOUT_MIN, "w+");\t\t
\t\tfout_max = $fopen(`FOUT_MAX, "w+");\t\t
\t\tfout_state = $fopen(`FOUT_STATE, "w+");\t\t
\t\tfout_toggle = $fopen(`FOUT_TOGGLE, "w+");\t\t
\t\tfout_high = $fopen(`FOUT_HIGH, "w+");\t\t
\t\tfout_highz = $fopen(`FOUT_HIGHZ, "w+");\t\t
\t\tfout_lowz = $fopen(`FOUT_LOWZ, "w+");\t\t
\t\tfout_low = $fopen(`FOUT_LOW, "w+");\t\t
\t\tif (!$feof(fin))
\t\t\tadc_d = $fgetc(fin); // read the first value
\tend
\talways
\t\t# 1 clk = !clk;
\t// input
\tinitial
\tbegin
\t\twhile (!$feof(fin)) begin
\t\t\t@(negedge clk) adc_d <= $fgetc(fin);
\t\tend
\t\tif ($feof(fin))
\t\tbegin
\t\t\t# 3 $fclose(fin);
\t\t\t$fclose(fout_state);
\t\t\t$fclose(fout_toggle);
\t\t\t$fclose(fout_high);
\t\t\t$fclose(fout_highz);
\t\t\t$fclose(fout_lowz);
\t\t\t$fclose(fout_low);
\t\t\t$fclose(fout_min);
\t\t\t$fclose(fout_max);
\t\t\t$finish;
\t\tend
\tend
\tinitial
\tbegin
\t\t// $monitor("%d\\t S: %b, E: %b", $time, edge_state, edge_toggle);
\tend
\t// output
\talways @(negedge clk)
\tif ($time > 2) begin
\t\tr = $fputc(min, fout_min);
\t\tr = $fputc(max, fout_max);
\t\tr = $fputc(edge_state, fout_state);
\t\tr = $fputc(edge_toggle, fout_toggle);
\t\tr = $fputc(high_threshold, fout_high);
\t\tr = $fputc(highz_threshold, fout_highz);
\t\tr = $fputc(lowz_threshold, fout_lowz);
\t\tr = $fputc(low_threshold, fout_low);
\tend
\t// module to test
\tlf_edge_detect detect(clk, adc_d, 8\'d127,
\t\tmax, min,
\t\thigh_threshold, highz_threshold,
\t\tlowz_threshold, low_threshold,
\t\tedge_state, edge_toggle);
endmodule |
//-----------------------------------------------------------------------------
// The way that we connect things in low-frequency simulation mode. In this
// case just pass everything through to the ARM, which can bit-bang this
// (because it is so slow).
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module lo_simulate(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
\t divisor
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
\t input [7:0] divisor;
// No logic, straight through.
assign pwr_oe3 = 1'b0;
assign pwr_oe1 = ssp_dout;
assign pwr_oe2 = ssp_dout;
assign pwr_oe4 = ssp_dout;
assign ssp_clk = cross_lo;
assign pwr_lo = 1'b0;
assign pwr_hi = 1'b0;
assign dbg = ssp_frame;
// Divide the clock to be used for the ADC
reg [7:0] pck_divider;
reg clk_state;
always @(posedge pck0)
begin
\tif(pck_divider == divisor[7:0])
\t\tbegin
\t\t\tpck_divider <= 8'd0;
\t\t\tclk_state = !clk_state;
\t\tend
\telse
\tbegin
\t\tpck_divider <= pck_divider + 1;
\tend
end
assign adc_clk = ~clk_state;
// Toggle the output with hysteresis
// Set to high if the ADC value is above 200
// Set to low if the ADC value is below 64
reg is_high;
reg is_low;
reg output_state;
always @(posedge pck0)
begin
\tif((pck_divider == 8'd7) && !clk_state) begin
\t\tis_high = (adc_d >= 8'd200);
\t\tis_low = (adc_d <= 8'd64);
\tend
end
always @(posedge is_high or posedge is_low)
begin
\tif(is_high)
\t\toutput_state <= 1'd1;
\telse if(is_low)
\t\toutput_state <= 1'd0;
end
assign ssp_frame = output_state;
endmodule
|
//-----------------------------------------------------------------------------
// ISO14443-A support for the Proxmark III
// Gerhard de Koning Gans, April 2008
//-----------------------------------------------------------------------------
// constants for the different modes:
`define SNIFFER\t\t\t3\'b000
`define TAGSIM_LISTEN\t3\'b001
`define TAGSIM_MOD\t\t3\'b010
`define READER_LISTEN\t3\'b011
`define READER_MOD\t\t3\'b100
module hi_iso14443a(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
mod_type
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [2:0] mod_type;
wire adc_clk = ck_1356meg;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Reader -> PM3:
// detecting and shaping the reader\'s signal. Reader will modulate the carrier by 100% (signal is either on or off). Use a
// hysteresis (Schmitt Trigger) to avoid false triggers during slowly increasing or decreasing carrier amplitudes
reg after_hysteresis;
reg [11:0] has_been_low_for;
always @(negedge adc_clk)
begin
\tif(adc_d >= 16) after_hysteresis <= 1\'b1;\t\t\t// U >= 1,14V \t-> after_hysteresis = 1
else if(adc_d < 8) after_hysteresis <= 1\'b0; \t\t// U < \t1,04V \t-> after_hysteresis = 0
\t// Note: was >= 3,53V and <= 1,19V. The new trigger values allow more reliable detection of the first bit
\t// (it might not reach 3,53V due to the high time constant of the high pass filter in the analogue RF part).
\t// In addition, the new values are more in line with ISO14443-2: "The PICC shall detect the \xe2\x80\x9dEnd of Pause\xe2\x80\x9d after the field exceeds
\t// 5% of H_INITIAL and before it exceeds 60% of H_INITIAL." Depending on the signal strength, 60% might well be less than 3,53V.
\t
\t
\t// detecting a loss of reader\'s field (adc_d < 192 for 4096 clock cycles). If this is the case,
\t// set the detected reader signal (after_hysteresis) to \'1\' (unmodulated)
\tif(adc_d >= 192)
begin
has_been_low_for <= 12\'d0;
end
else
begin
if(has_been_low_for == 12\'d4095)
begin
has_been_low_for <= 12\'d0;
after_hysteresis <= 1\'b1;
end
else
\t\tbegin
has_been_low_for <= has_been_low_for + 1;
\t\tend\t
end
\t
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Reader -> PM3
// detect when a reader is active (modulating). We assume that the reader is active, if we see the carrier off for at least 8
// carrier cycles. We assume that the reader is inactive, if the carrier stayed high for at least 256 carrier cycles.
reg deep_modulation;
reg [2:0] deep_counter;
reg [8:0] saw_deep_modulation;
always @(negedge adc_clk)
begin
\tif(~(| adc_d[7:0]))\t\t\t\t\t\t\t\t\t// if adc_d == 0 (U <= 0,94V)
\tbegin
\t\tif(deep_counter == 3\'d7)\t\t\t\t\t\t// adc_d == 0 for 8 adc_clk ticks -> deep_modulation (by reader)
\t\tbegin
\t\t\tdeep_modulation <= 1\'b1;
\t\t\tsaw_deep_modulation <= 8\'d0;
\t\tend
\t\telse
\t\t\tdeep_counter <= deep_counter + 1;
\tend
\telse\t\t\t\t\t\t\t
\tbegin
\t\tdeep_counter <= 3\'d0;
\t\tif(saw_deep_modulation == 8\'d255)\t\t\t\t// adc_d != 0 for 256 adc_clk ticks -> deep_modulation is over, probably waiting for tag\'s response
\t\t\tdeep_modulation <= 1\'b0;
\t\telse
\t\t\tsaw_deep_modulation <= saw_deep_modulation + 1;
\tend
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag -> PM3
// filter the input for a tag\'s signal. The filter box needs the 4 previous input values and is a gaussian derivative filter
// for noise reduction and edge detection.
// store 4 previous samples:
reg [7:0] input_prev_4, input_prev_3, input_prev_2, input_prev_1;
always @(negedge adc_clk)
begin
\tinput_prev_4 <= input_prev_3;
\tinput_prev_3 <= input_prev_2;
\tinput_prev_2 <= input_prev_1;
\tinput_prev_1 <= adc_d;
end\t
// adc_d_filtered = 2*input_prev4 + 1*input_prev3 + 0*input_prev2 - 1*input_prev1 - 2*input
//\t\t\t\t\t= (2*input_prev4 + input_prev3) - (2*input + input_prev1)
wire [8:0] input_prev_4_times_2 = input_prev_4 << 1;
wire [8:0] adc_d_times_2 \t\t= adc_d << 1;
wire [9:0] tmp1 = input_prev_4_times_2 + input_prev_3;
wire [9:0] tmp2 = adc_d_times_2 + input_prev_1;
// convert intermediate signals to signed and calculate the filter output
wire signed [10:0] adc_d_filtered = {1\'b0, tmp1} - {1\'b0, tmp2};
\t
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// internal FPGA timing. Maximum required period is 128 carrier clock cycles for a full 8 Bit transfer to ARM. (i.e. we need a
// 7 bit counter). Adjust its frequency to external reader\'s clock when simulating a tag or sniffing.
reg pre_after_hysteresis;
reg [3:0] reader_falling_edge_time;
reg [6:0] negedge_cnt;
always @(negedge adc_clk)
begin
\t// detect a reader signal\'s falling edge and remember its timing:
\tpre_after_hysteresis <= after_hysteresis;
\tif (pre_after_hysteresis && ~after_hysteresis)
\tbegin
\t\treader_falling_edge_time[3:0] <= negedge_cnt[3:0];
\tend
\t// adjust internal timer counter if necessary:
\tif (negedge_cnt[3:0] == 4\'d13 && (mod_type == `SNIFFER || mod_type == `TAGSIM_LISTEN) && deep_modulation)
\tbegin
\t\tif (reader_falling_edge_time == 4\'d1) \t\t\t// reader signal changes right after sampling. Better sample earlier next time.
\t\tbegin
\t\t\tnegedge_cnt <= negedge_cnt + 2;\t\t\t\t// time warp
\t\tend\t
\t\telse if (reader_falling_edge_time == 4\'d0)\t\t// reader signal changes right before sampling. Better sample later next time.
\t\tbegin
\t\t\tnegedge_cnt <= negedge_cnt;\t\t\t\t\t// freeze time
\t\tend
\t\telse
\t\tbegin
\t\t\tnegedge_cnt <= negedge_cnt + 1;\t\t\t\t// Continue as usual
\t\tend
\t\treader_falling_edge_time[3:0] <= 4\'d8;\t\t\t// adjust only once per detected edge
\tend
\telse if (negedge_cnt == 7\'d127)\t\t\t\t\t\t// normal operation: count from 0 to 127
\tbegin
\t\tnegedge_cnt <= 0;
\tend\t
\telse
\tbegin
\t\tnegedge_cnt <= negedge_cnt + 1;
\tend
end\t
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag -> PM3:
// determine best possible time for starting/resetting the modulation detector.
reg [3:0] mod_detect_reset_time;
always @(negedge adc_clk)
begin
\tif (mod_type == `READER_LISTEN)
\t// (our) reader signal changes at negedge_cnt[3:0]=9, tag response expected to start n*16+4 ticks later, further delayed by
\t// 3 ticks ADC conversion. The maximum filter output (edge detected) will be detected after subcarrier zero crossing (+7 ticks).
\t// To allow some timing variances, we want to have the maximum filter outputs well within the detection window, i.e.
\t// at mod_detect_reset_time+4 and mod_detect_reset_time+12 (-4 ticks).
\t// 9 + 4 + 3 + 7 - 4 = 19. 19 mod 16 = 3
\tbegin
\t\tmod_detect_reset_time <= 4\'d4;
\tend
\telse
\tif (mod_type == `SNIFFER)
\tbegin
\t\t// detect a rising edge of reader\'s signal and sync modulation detector to the tag\'s answer:
\t\tif (~pre_after_hysteresis && after_hysteresis && deep_modulation)
\t\t// reader signal rising edge detected at negedge_cnt[3:0]. This signal had been delayed
\t\t// 9 ticks by the RF part + 3 ticks by the A/D converter + 1 tick to assign to after_hysteresis.
\t\t// Then the same as above.
\t\t// - 9 - 3 - 1 + 4 + 3 + 7 - 4 = -3
\t\tbegin
\t\t\tmod_detect_reset_time <= negedge_cnt[3:0] - 4\'d3;
\t\tend
\tend
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag -> PM3:
// modulation detector. Looks for the steepest falling and rising edges within a 16 clock period. If there is both a significant
// falling and rising edge (in any order), a modulation is detected.
reg signed [10:0] rx_mod_falling_edge_max;
reg signed [10:0] rx_mod_rising_edge_max;
reg curbit;
`define EDGE_DETECT_THRESHOLD\t5
always @(negedge adc_clk)
begin
\tif(negedge_cnt[3:0] == mod_detect_reset_time)
\tbegin
\t\t// detect modulation signal: if modulating, there must have been a falling AND a rising edge
\t\tif ((rx_mod_falling_edge_max > `EDGE_DETECT_THRESHOLD) && (rx_mod_rising_edge_max < -`EDGE_DETECT_THRESHOLD))
\t\t\t\tcurbit <= 1\'b1;\t// modulation
\t\t\telse
\t\t\t\tcurbit <= 1\'b0;\t// no modulation
\t\t// reset modulation detector
\t\trx_mod_rising_edge_max <= 0;
\t\trx_mod_falling_edge_max <= 0;
\tend
\telse\t\t\t\t\t\t\t\t\t\t\t// look for steepest edges (slopes)
\tbegin
\t\tif (adc_d_filtered > 0)
\t\tbegin
\t\t\tif (adc_d_filtered > rx_mod_falling_edge_max)
\t\t\t\trx_mod_falling_edge_max <= adc_d_filtered;
\t\tend
\t\telse
\t\tbegin
\t\t\tif (adc_d_filtered < rx_mod_rising_edge_max)
\t\t\t\trx_mod_rising_edge_max <= adc_d_filtered;
\t\tend
\tend
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag+Reader -> PM3
// sample 4 bits reader data and 4 bits tag data for sniffing
reg [3:0] reader_data;
reg [3:0] tag_data;
always @(negedge adc_clk)
begin
if(negedge_cnt[3:0] == 4\'d0)
\tbegin
reader_data[3:0] <= {reader_data[2:0], after_hysteresis};
\t\ttag_data[3:0] <= {tag_data[2:0], curbit};
\tend
end\t
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Reader:
// a delay line to ensure that we send the (emulated) tag\'s answer at the correct time according to ISO14443-3
reg [31:0] mod_sig_buf;
reg [4:0] mod_sig_ptr;
reg mod_sig;
always @(negedge adc_clk)
begin
\tif(negedge_cnt[3:0] == 4\'d0) \t// sample data at rising edge of ssp_clk - ssp_dout changes at the falling edge.
\tbegin
\t\tmod_sig_buf[31:2] <= mod_sig_buf[30:1]; \t\t\t// shift
\t\tif (~ssp_dout && ~mod_sig_buf[1])
\t\t\tmod_sig_buf[1] <= 1\'b0;\t\t\t\t\t\t\t// delete the correction bit (a single 1 preceded and succeeded by 0)
\t\telse
\t\t\tmod_sig_buf[1] <= mod_sig_buf[0];
\t\tmod_sig_buf[0] <= ssp_dout;\t\t\t\t\t\t\t// add new data to the delay line
\t\tmod_sig = mod_sig_buf[mod_sig_ptr];\t\t\t\t\t// the delayed signal.
\tend
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Reader, internal timing:
// a timer for the 1172 cycles fdt (Frame Delay Time). Start the timer with a rising edge of the reader\'s signal.
// set fdt_elapsed when we no longer need to delay data. Set fdt_indicator when we can start sending data.
// Note: the FPGA only takes care for the 1172 delay. To achieve an additional 1236-1172=64 ticks delay, the ARM must send
// a correction bit (before the start bit). The correction bit will be coded as 00010000, i.e. it adds 4 bits to the
// transmission stream, causing the required additional delay.
reg [10:0] fdt_counter;
reg fdt_indicator, fdt_elapsed;
reg [3:0] mod_sig_flip;
reg [3:0] sub_carrier_cnt;
// we want to achieve a delay of 1172. The RF part already has delayed the reader signals\'s rising edge
// by 9 ticks, the ADC took 3 ticks and there is always a delay of 32 ticks by the mod_sig_buf. Therefore need to
// count to 1172 - 9 - 3 - 32 = 1128
`define FDT_COUNT 11\'d1128
// The ARM must not send too early, otherwise the mod_sig_buf will overflow, therefore signal that we are ready
// with fdt_indicator. The mod_sig_buf can buffer 29 excess data bits, i.e. a maximum delay of 29 * 16 = 464 adc_clk ticks.
// fdt_indicator could appear at ssp_din after 1 tick, the transfer needs 16 ticks, the ARM can send 128 ticks later.
// 1128 - 464 - 1 - 128 - 8 = 535
`define FDT_INDICATOR_COUNT 11\'d535
// reset on a pause in listen mode. I.e. the counter starts when the pause is over:
assign fdt_reset = ~after_hysteresis && mod_type == `TAGSIM_LISTEN;
always @(negedge adc_clk)
begin
\tif (fdt_reset)
\tbegin
\t\tfdt_counter <= 11\'d0;
\t\tfdt_elapsed <= 1\'b0;
\t\tfdt_indicator <= 1\'b0;
\tend\t
\telse
\tbegin
\t\tif(fdt_counter == `FDT_COUNT)
\t\tbegin\t\t\t\t\t\t
\t\t\tif(~fdt_elapsed)\t\t\t\t\t\t\t// just reached fdt.
\t\t\tbegin
\t\t\t\tmod_sig_flip <= negedge_cnt[3:0];\t\t// start modulation at this time
\t\t\t\tsub_carrier_cnt <= 4\'d0;\t\t\t\t// subcarrier phase in sync with start of modulation
\t\t\t\tfdt_elapsed <= 1\'b1;
\t\t\tend
\t\t\telse
\t\t\tbegin
\t\t\t\tsub_carrier_cnt <= sub_carrier_cnt + 1;
\t\t\tend\t
\t\tend\t
\t\telse
\t\tbegin
\t\t\tfdt_counter <= fdt_counter + 1;
\t\tend
\tend
\t
\tif(fdt_counter == `FDT_INDICATOR_COUNT) fdt_indicator <= 1\'b1;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Reader or Tag
// assign a modulation signal to the antenna. This signal is either a delayed signal (to achieve fdt when sending to a reader)
// or undelayed when sending to a tag
reg mod_sig_coil;
always @(negedge adc_clk)
begin
\tif (mod_type == `TAGSIM_MOD)\t\t\t // need to take care of proper fdt timing
\tbegin
\t\tif(fdt_counter == `FDT_COUNT)
\t\tbegin
\t\t\tif(fdt_elapsed)
\t\t\tbegin
\t\t\t\tif(negedge_cnt[3:0] == mod_sig_flip) mod_sig_coil <= mod_sig;
\t\t\tend
\t\t\telse
\t\t\tbegin
\t\t\t\tmod_sig_coil <= mod_sig;\t// just reached fdt. Immediately assign signal to coil
\t\t\tend
\t\tend
\tend
\telse \t\t\t\t\t\t\t\t\t// other modes: don\'t delay
\tbegin
\t\tmod_sig_coil <= ssp_dout;
\tend\t
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Reader
// determine the required delay in the mod_sig_buf (set mod_sig_ptr).
reg temp_buffer_reset;
always @(negedge adc_clk)
begin
\tif(fdt_reset)
\tbegin
\t\tmod_sig_ptr <= 5\'d0;
\t\ttemp_buffer_reset = 1\'b0;
\tend\t
\telse
\tbegin
\t\tif(fdt_counter == `FDT_COUNT && ~fdt_elapsed)\t\t\t\t\t\t\t// if we just reached fdt
\t\t\tif(~(| mod_sig_ptr[4:0]))
\t\t\t\tmod_sig_ptr <= 5\'d8; \t\t\t\t\t\t\t\t\t\t\t// ... but didn\'t buffer a 1 yet, delay next 1 by n*128 ticks.
\t\t\telse
\t\t\t\ttemp_buffer_reset = 1\'b1; \t\t\t\t\t\t\t\t\t\t// else no need for further delays.
\t\tif(negedge_cnt[3:0] == 4\'d0) \t\t\t\t\t\t\t\t\t\t\t// at rising edge of ssp_clk - ssp_dout changes at the falling edge.
\t\tbegin
\t\t\tif((ssp_dout || (| mod_sig_ptr[4:0])) && ~fdt_elapsed)\t\t\t\t// buffer a 1 (and all subsequent data) until fdt is reached.
\t\t\t\tif (mod_sig_ptr == 5\'d31)
\t\t\t\t\tmod_sig_ptr <= 5\'d0;\t\t\t\t\t\t\t\t\t\t// buffer overflow - data loss.
\t\t\t\telse
\t\t\t\t\tmod_sig_ptr <= mod_sig_ptr + 1;\t\t\t\t\t\t\t\t// increase buffer (= increase delay by 16 adc_clk ticks). mod_sig_ptr always points ahead of first 1.
\t\t\telse if(fdt_elapsed && ~temp_buffer_reset)\t\t\t\t\t\t\t
\t\t\tbegin
\t\t\t\t// wait for the next 1 after fdt_elapsed before fixing the delay and starting modulation. This ensures that the response can only happen
\t\t\t\t// at intervals of 8 * 16 = 128 adc_clk ticks (as defined in ISO14443-3)
\t\t\t\tif(ssp_dout)
\t\t\t\t\ttemp_buffer_reset = 1\'b1;\t\t\t\t\t\t\t
\t\t\t\tif(mod_sig_ptr == 5\'d1)
\t\t\t\t\tmod_sig_ptr <= 5\'d8;\t\t\t\t\t\t\t\t\t\t// still nothing received, need to go for the next interval
\t\t\t\telse
\t\t\t\t\tmod_sig_ptr <= mod_sig_ptr - 1;\t\t\t\t\t\t\t\t// decrease buffer.
\t\t\tend
\t\tend
\tend
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGA -> ARM communication:
// buffer 8 bits data to be sent to ARM. Shift them out bit by bit.
reg [7:0] to_arm;
always @(negedge adc_clk)
begin
\tif (negedge_cnt[5:0] == 6\'d63)\t\t\t\t\t\t\t// fill the buffer
\tbegin
\t\tif (mod_type == `SNIFFER)
\t\tbegin
\t\t\tif(deep_modulation) \t\t\t\t\t\t\t// a reader is sending (or there\'s no field at all)
\t\t\tbegin
\t\t\t\tto_arm <= {reader_data[3:0], 4\'b0000};\t\t// don\'t send tag data
\t\t\tend
\t\t\telse
\t\t\tbegin
\t\t\t\tto_arm <= {reader_data[3:0], tag_data[3:0]};
\t\t\tend\t\t\t
\t\tend
\t\telse
\t\tbegin
\t\t\tto_arm[7:0] <= {mod_sig_ptr[4:0], mod_sig_flip[3:1]}; // feedback timing information
\t\tend
\tend\t
\tif(negedge_cnt[2:0] == 3\'b000 && mod_type == `SNIFFER)\t// shift at double speed
\tbegin
\t\t// Don\'t shift if we just loaded new data, obviously.
\t\tif(negedge_cnt[5:0] != 6\'d0)
\t\tbegin
\t\t\tto_arm[7:1] <= to_arm[6:0];
\t\tend
\tend
\tif(negedge_cnt[3:0] == 4\'b0000 && mod_type != `SNIFFER)
\tbegin
\t\t// Don\'t shift if we just loaded new data, obviously.
\t\tif(negedge_cnt[6:0] != 7\'d0)
\t\tbegin
\t\t\tto_arm[7:1] <= to_arm[6:0];
\t\tend
\tend
\t
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGA <-> ARM communication:
// generate a ssp clock and ssp frame signal for the synchronous transfer from/to the ARM
reg ssp_clk;
reg ssp_frame;
always @(negedge adc_clk)
begin
\tif(mod_type == `SNIFFER)
\t// SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)):
\tbegin
\t\tif(negedge_cnt[2:0] == 3\'d0)
\t\t\tssp_clk <= 1\'b1;
\t\tif(negedge_cnt[2:0] == 3\'d4)
\t\t\tssp_clk <= 1\'b0;
\t\tif(negedge_cnt[5:0] == 6\'d0)\t// ssp_frame rising edge indicates start of frame
\t\t\tssp_frame <= 1\'b1;
\t\tif(negedge_cnt[5:0] == 6\'d8)\t
\t\t\tssp_frame <= 1\'b0;
\tend
\telse
\t// all other modes (ssp_clk = adc_clk / 16, ssp_frame clock = adc_clk / 128):
\tbegin
\t\tif(negedge_cnt[3:0] == 4\'d0)
\t\t\tssp_clk <= 1\'b1;
\t\tif(negedge_cnt[3:0] == 4\'d8)
\t\t\tssp_clk <= 1\'b0;
\t\tif(negedge_cnt[6:0] == 7\'d7)\t// ssp_frame rising edge indicates start of frame
\t\t\tssp_frame <= 1\'b1;
\t\tif(negedge_cnt[6:0] == 7\'d23)
\t\t\tssp_frame <= 1\'b0;
\tend\t
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGA -> ARM communication:
// select the data to be sent to ARM
reg bit_to_arm;
reg sendbit;
always @(negedge adc_clk)
begin
\tif(negedge_cnt[3:0] == 4\'d0)
\tbegin
\t\t// What do we communicate to the ARM
\t\tif(mod_type == `TAGSIM_LISTEN)
\t\t\tsendbit = after_hysteresis;
\t\telse if(mod_type == `TAGSIM_MOD)
\t\t\t/* if(fdt_counter > 11\'d772) sendbit = mod_sig_coil; // huh?
\t\t\telse */
\t\t\tsendbit = fdt_indicator;
\t\telse if (mod_type == `READER_LISTEN)
\t\t\tsendbit = curbit;
\t\telse
\t\t\tsendbit = 1\'b0;
\tend
\tif(mod_type == `SNIFFER)
\t\t// send sampled reader and tag data:
\t\tbit_to_arm = to_arm[7];
\telse if (mod_type == `TAGSIM_MOD && fdt_elapsed && temp_buffer_reset)
\t\t// send timing information:
\t\tbit_to_arm = to_arm[7];
\telse
\t\t// send data or fdt_indicator
\t\tbit_to_arm = sendbit;
end
assign ssp_din = bit_to_arm;
// Subcarrier (adc_clk/16, for TAGSIM_MOD only).
wire sub_carrier;
assign sub_carrier = ~sub_carrier_cnt[3];
// in READER_MOD: drop carrier for mod_sig_coil==1 (pause); in READER_LISTEN: carrier always on; in other modes: carrier always off
assign pwr_hi = (ck_1356megb & (((mod_type == `READER_MOD) & ~mod_sig_coil) || (mod_type == `READER_LISTEN)));\t
// Enable HF antenna drivers:
assign pwr_oe1 = 1\'b0;
assign pwr_oe3 = 1\'b0;
// TAGSIM_MOD: short circuit antenna with different resistances (modulated by sub_carrier modulated by mod_sig_coil)
// for pwr_oe4 = 1 (tristate): antenna load = 10k || 33\t\t\t= 32,9 Ohms
// for pwr_oe4 = 0 (active): antenna load = 10k || 33 || 33 \t= 16,5 Ohms
assign pwr_oe4 = mod_sig_coil & sub_carrier & (mod_type == `TAGSIM_MOD);
// This is all LF, so doesn\'t matter.
assign pwr_oe2 = 1\'b0;
assign pwr_lo = 1\'b0;
assign dbg = negedge_cnt[3];
endmodule
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// Butterworth low pass IIR filter
// input: 8bit ADC signal, 1MS/s
// output: 8bit value, Fc=20khz
//
// coef: (using http://www-users.cs.york.ac.uk/~fisher/mkfilter/trad.html)
// Recurrence relation:
// y[n] = ( 1 * x[n- 2])
// + ( 2 * x[n- 1])
// + ( 1 * x[n- 0])
// + ( -0.8371816513 * y[n- 2])
// + ( 1.8226949252 * y[n- 1])
//
// therefore:
// a = [1,2,1]
// b = [-0.8371816513, 1.8226949252]
// b is approximated to b = [-0xd6/0x100, 0x1d3 / 0x100] (for optimization)
// gain = 2.761139367e2
//
// See details about its design see
// https://fail0verflow.com/blog/2014/proxmark3-fpga-iir-filter.html
module lp20khz_1MSa_iir_filter(input clk, input [7:0] adc_d, output rdy, output [7:0] out);
\t// clk is 24Mhz, the IIR filter is designed for 1MS/s
\t// hence we need to divide it by 24
\t// using a shift register takes less area than a counter
\treg [23:0] cnt = 1;
\tassign rdy = cnt[0];
\talways @(posedge clk)
\t\tcnt <= {cnt[22:0], cnt[23]};\t\t
\treg [7:0] x0 = 0;
\treg [7:0] x1 = 0;
\treg [16:0] y0 = 0;
\treg [16:0] y1 = 0;
\talways @(posedge clk)
\tbegin
\t\tif (rdy)
\t\tbegin
\t\t\tx0 <= x1;
\t\t\tx1 <= adc_d;
\t\t\ty0 <= y1;
\t\t\ty1 <=
\t\t\t\t// center the signal:
\t\t\t\t// input range is [0; 255]
\t\t\t\t// We want "128" to be at the center of the 17bit register
\t\t\t\t// (128+z)*gain = 17bit center
\t\t\t\t// z = (1<<16)/gain - 128 = 109
\t\t\t\t// We could use 9bit x registers for that, but that would be
\t\t\t\t// a waste, let\'s just add the constant during the computation
\t\t\t\t// (x0+109) + 2*(x1+109) + (x2+109) = x0 + 2*x1 + x2 + 436
\t\t\t\tx0 + {x1, 1\'b0} + adc_d + 436
\t\t\t\t// we want "- y0 * 0xd6 / 0x100" using only shift and add
\t\t\t\t// 0xd6 == 0b11010110
\t\t\t\t// so *0xd6/0x100 is equivalent to
\t\t\t\t// ((x << 1) + (x << 2) + (x << 4) + (x << 6) + (x << 7)) >> 8
\t\t\t\t// which is also equivalent to
\t\t\t\t// (x >> 7) + (x >> 6) + (x >> 4) + (x >> 2) + (x >> 1)
\t\t\t\t- ((y0 >> 7) + (y0 >> 6) + (y0 >> 4) + (y0 >> 2) + (y0 >> 1)) // - y0 * 0xd6 / 0x100
\t\t\t\t// we want "+ y1 * 0x1d3 / 0x100"
\t\t\t\t// 0x1d3 == 0b111010011
\t\t\t\t// so this is equivalent to
\t\t\t\t// ((x << 0) + (x << 1) + (x << 4) + (x << 6) + (x << 7) + (x << 8)) >> 8
\t\t\t\t// which is also equivalent to
\t\t\t\t// (x >> 8) + (x >> 7) + (x >> 4) + (x >> 2) + (x >> 1) + (x >> 0)
\t\t\t\t+ ((y1 >> 8) + (y1 >> 7) + (y1 >> 4) + (y1 >> 2) + (y1 >> 1) + y1);
\t\tend
\tend
\t// output: reduce to 8bit
\tassign out = y1[16:9];
endmodule
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// input clk is 24Mhz
`include "min_max_tracker.v"
module lf_edge_detect(input clk, input [7:0] adc_d, input [7:0] lf_ed_threshold,
\toutput [7:0] max, output [7:0] min,
\toutput [7:0] high_threshold, output [7:0] highz_threshold,
\toutput [7:0] lowz_threshold, output [7:0] low_threshold,
\toutput edge_state, output edge_toggle);
\tmin_max_tracker tracker(clk, adc_d, lf_ed_threshold, min, max);
\t// auto-tune
\tassign high_threshold = (max + min) / 2 + (max - min) / 4;
\tassign highz_threshold = (max + min) / 2 + (max - min) / 8;
\tassign lowz_threshold = (max + min) / 2 - (max - min) / 8;
\tassign low_threshold = (max + min) / 2 - (max - min) / 4;
\t// heuristic to see if it makes sense to try to detect an edge
\twire enabled =
\t\t(high_threshold > highz_threshold)
\t\t& (highz_threshold > lowz_threshold)
\t\t& (lowz_threshold > low_threshold)
\t\t& ((high_threshold - highz_threshold) > 8)
\t\t& ((highz_threshold - lowz_threshold) > 16)
\t\t& ((lowz_threshold - low_threshold) > 8);
\t// Toggle the output with hysteresis
\t// Set to high if the ADC value is above the threshold
\t// Set to low if the ADC value is below the threshold
\treg is_high = 0;
\treg is_low = 0;
\treg is_zero = 0;
\treg trigger_enabled = 1;
\treg output_edge = 0;
\treg output_state;
\talways @(posedge clk)
\tbegin
\t\tis_high <= (adc_d >= high_threshold);
\t\tis_low <= (adc_d <= low_threshold);
\t\tis_zero <= ((adc_d > lowz_threshold) & (adc_d < highz_threshold));
\tend
\t// all edges detection
\talways @(posedge clk)
\tif (enabled) begin
\t\t// To enable detecting two consecutive peaks at the same level
\t\t// (low or high) we check whether or not we went back near 0 in-between.
\t\t// This extra check is necessary to prevent from noise artifacts
\t\t// around the threshold values.
\t\tif (trigger_enabled & (is_high | is_low)) begin
\t\t\toutput_edge <= ~output_edge;
\t\t\ttrigger_enabled <= 0;
\t\tend else
\t\t\ttrigger_enabled <= trigger_enabled | is_zero;
\tend
\t// edge states
\talways @(posedge clk)
\tif (enabled) begin
\t\tif (is_high)
\t\t\toutput_state <= 1\'d1;
\t\telse if (is_low)
\t\t\toutput_state <= 1\'d0;
\tend
\tassign edge_state = output_state;
\tassign edge_toggle = output_edge;
endmodule
|
`include "hi_read_tx.v"
/*
\tpck0\t\t\t- input main 24Mhz clock (PLL / 4)
\t[7:0] adc_d\t\t- input data from A/D converter
\tshallow_modulation\t- modulation type
\tpwr_lo\t\t\t- output to coil drivers (ssp_clk / 8)
\tadc_clk\t\t\t- output A/D clock signal
\tssp_frame\t\t- output SSS frame indicator (goes high while the 8 bits are shifted)
\tssp_din\t\t\t- output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
\tssp_clk\t\t\t- output SSP clock signal
\tck_1356meg\t\t- input unused
\tck_1356megb\t\t- input unused
\tssp_dout\t\t- input unused
\tcross_hi\t\t- input unused
\tcross_lo\t\t- input unused
\tpwr_hi\t\t\t- output unused, tied low
\tpwr_oe1\t\t\t- output unused, undefined
\tpwr_oe2\t\t\t- output unused, undefined
\tpwr_oe3\t\t\t- output unused, undefined
\tpwr_oe4\t\t\t- output unused, undefined
\tdbg\t\t\t\t- output alias for adc_clk
*/
module testbed_hi_read_tx;
\treg pck0;
\treg [7:0] adc_d;
\treg shallow_modulation;
\twire pwr_lo;
\twire adc_clk;
\treg ck_1356meg;
\treg ck_1356megb;
\twire ssp_frame;
\twire ssp_din;
\twire ssp_clk;
\treg ssp_dout;
\twire pwr_hi;
\twire pwr_oe1;
\twire pwr_oe2;
\twire pwr_oe3;
\twire pwr_oe4;
\twire cross_lo;
\twire cross_hi;
\twire dbg;
\thi_read_tx #(5,200) dut(
\t.pck0(pck0),
\t.ck_1356meg(ck_1356meg),
\t.ck_1356megb(ck_1356megb),
\t.pwr_lo(pwr_lo),
\t.pwr_hi(pwr_hi),
\t.pwr_oe1(pwr_oe1),
\t.pwr_oe2(pwr_oe2),
\t.pwr_oe3(pwr_oe3),
\t.pwr_oe4(pwr_oe4),
\t.adc_d(adc_d),
\t.adc_clk(adc_clk),
\t.ssp_frame(ssp_frame),
\t.ssp_din(ssp_din),
\t.ssp_dout(ssp_dout),
\t.ssp_clk(ssp_clk),
\t.cross_hi(cross_hi),
\t.cross_lo(cross_lo),
\t.dbg(dbg),
\t.shallow_modulation(shallow_modulation)
\t);
\tinteger idx, i;
\t// main clock
\talways #5 begin
\t\tck_1356megb = !ck_1356megb;
\t\tck_1356meg = ck_1356megb;
\tend
\t//crank DUT
\ttask crank_dut;
\tbegin
\t\t@(posedge ssp_clk) ;
\t\tssp_dout = $random;
\tend
\tendtask
\tinitial begin
\t\t// init inputs
\t\tck_1356megb = 0;
\t\tadc_d = 0;
\t\tssp_dout=0;
\t\t// shallow modulation off
\t\tshallow_modulation=0;
\t\tfor (i = 0 ; i < 16 ; i = i + 1) begin
\t\t\tcrank_dut;
\t\tend
\t\t// shallow modulation on
\t\tshallow_modulation=1;
\t\tfor (i = 0 ; i < 16 ; i = i + 1) begin
\t\t\tcrank_dut;
\t\tend
\t\t$finish;
\tend
\t
endmodule // main
|
`include "lo_read.v"
/*
\tpck0\t\t\t- input main 24Mhz clock (PLL / 4)
\t[7:0] adc_d\t\t- input data from A/D converter
\tlo_is_125khz\t- input freq selector (1=125Khz, 0=136Khz)
\tpwr_lo\t\t\t- output to coil drivers (ssp_clk / 8)
\tadc_clk\t\t\t- output A/D clock signal
\tssp_frame\t\t- output SSS frame indicator (goes high while the 8 bits are shifted)
\tssp_din\t\t\t- output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
\tssp_clk\t\t\t- output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )
\tck_1356meg\t\t- input unused
\tck_1356megb\t\t- input unused
\tssp_dout\t\t- input unused
\tcross_hi\t\t- input unused
\tcross_lo\t\t- input unused
\tpwr_hi\t\t\t- output unused, tied low
\tpwr_oe1\t\t\t- output unused, undefined
\tpwr_oe2\t\t\t- output unused, undefined
\tpwr_oe3\t\t\t- output unused, undefined
\tpwr_oe4\t\t\t- output unused, undefined
\tdbg\t\t\t\t- output alias for adc_clk
*/
module testbed_lo_read;
\treg pck0;
\treg [7:0] adc_d;
\treg lo_is_125khz;
\treg [15:0] divisor;
\twire pwr_lo;
\twire adc_clk;
\twire ck_1356meg;
\twire ck_1356megb;
\twire ssp_frame;
\twire ssp_din;
\twire ssp_clk;
\treg ssp_dout;
\twire pwr_hi;
\twire pwr_oe1;
\twire pwr_oe2;
\twire pwr_oe3;
\twire pwr_oe4;
\twire cross_lo;
\twire cross_hi;
\twire dbg;
\tlo_read #(5,10) dut(
\t.pck0(pck0),
\t.ck_1356meg(ck_1356meg),
\t.ck_1356megb(ck_1356megb),
\t.pwr_lo(pwr_lo),
\t.pwr_hi(pwr_hi),
\t.pwr_oe1(pwr_oe1),
\t.pwr_oe2(pwr_oe2),
\t.pwr_oe3(pwr_oe3),
\t.pwr_oe4(pwr_oe4),
\t.adc_d(adc_d),
\t.adc_clk(adc_clk),
\t.ssp_frame(ssp_frame),
\t.ssp_din(ssp_din),
\t.ssp_dout(ssp_dout),
\t.ssp_clk(ssp_clk),
\t.cross_hi(cross_hi),
\t.cross_lo(cross_lo),
\t.dbg(dbg),
\t.lo_is_125khz(lo_is_125khz),
\t.divisor(divisor)
\t);
\tinteger idx, i, adc_val=8;
\t// main clock
\talways #5 pck0 = !pck0;
\ttask crank_dut;
\tbegin
\t\t@(posedge adc_clk) ;
\t\tadc_d = adc_val;
\t\tadc_val = (adc_val *2) + 53;
\tend
\tendtask
\tinitial begin
\t\t// init inputs
\t\tpck0 = 0;
\t\tadc_d = 0;
\t\tssp_dout = 0;
\t\tlo_is_125khz = 1;
\t\tdivisor = 255; //min 16, 95=125Khz, max 255
\t\t// simulate 4 A/D cycles at 125Khz
\t\tfor (i = 0 ; i < 8 ; i = i + 1) begin
\t\t\tcrank_dut;
\t\tend
\t\t$finish;
\tend
endmodule // main
|
//-----------------------------------------------------------------------------
// For reading TI tags, we need to place the FPGA in pass through mode
// and pass everything through to the ARM
//-----------------------------------------------------------------------------
// iZsh <izsh at fail0verflow.com>, June 2014
module lo_passthru(
\tinput pck_divclk,
\toutput pwr_lo, output pwr_hi,
\toutput pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
\toutput adc_clk,
\toutput ssp_din, input ssp_dout,
\tinput cross_lo,
\toutput dbg
);
// the antenna is modulated when ssp_dout = 1, when 0 the
// antenna drivers stop modulating and go into listen mode
assign pwr_oe3 = 1'b0;
assign pwr_oe1 = ssp_dout;
assign pwr_oe2 = ssp_dout;
assign pwr_oe4 = ssp_dout;
assign pwr_lo = pck_divclk && ssp_dout;
assign pwr_hi = 1'b0;
assign adc_clk = 1'b0;
assign ssp_din = cross_lo;
assign dbg = cross_lo;
endmodule
|
//-----------------------------------------------------------------------------
// The way that we connect things when transmitting a command to an ISO
// 15693 tag, using 100% modulation only for now.
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module hi_read_tx(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
shallow_modulation
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input shallow_modulation;
// The high-frequency stuff. For now, for testing, just bring out the carrier,
// and allow the ARM to modulate it over the SSP.
reg pwr_hi;
reg pwr_oe1;
reg pwr_oe2;
reg pwr_oe3;
reg pwr_oe4;
always @(ck_1356megb or ssp_dout or shallow_modulation)
begin
if(shallow_modulation)
begin
pwr_hi <= ck_1356megb;
pwr_oe1 <= ~ssp_dout;
pwr_oe2 <= ~ssp_dout;
pwr_oe3 <= ~ssp_dout;
pwr_oe4 <= 1'b0;
end
else
begin
pwr_hi <= ck_1356megb & ssp_dout;
pwr_oe1 <= 1'b0;
pwr_oe2 <= 1'b0;
pwr_oe3 <= 1'b0;
pwr_oe4 <= 1'b0;
end
end
// Then just divide the 13.56 MHz clock down to produce appropriate clocks
// for the synchronous serial port.
reg [6:0] hi_div_by_128;
always @(posedge ck_1356meg)
hi_div_by_128 <= hi_div_by_128 + 1;
assign ssp_clk = hi_div_by_128[6];
reg [2:0] hi_byte_div;
always @(negedge ssp_clk)
hi_byte_div <= hi_byte_div + 1;
assign ssp_frame = (hi_byte_div == 3'b000);
// Implement a hysteresis to give out the received signal on
// ssp_din. Sample at fc.
assign adc_clk = ck_1356meg;
// ADC data appears on the rising edge, so sample it on the falling edge
reg after_hysteresis;
always @(negedge adc_clk)
begin
if(& adc_d[7:0]) after_hysteresis <= 1'b1;
else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
end
assign ssp_din = after_hysteresis;
assign pwr_lo = 1'b0;
assign dbg = ssp_din;
endmodule
|
//-----------------------------------------------------------------------------
// General-purpose miscellany.
//
// Jonathan Westhues, April 2006.
//-----------------------------------------------------------------------------
module mux8(sel, y, x0, x1, x2, x3, x4, x5, x6, x7);
input [2:0] sel;
input x0, x1, x2, x3, x4, x5, x6, x7;
output y;
reg y;
always @(x0 or x1 or x2 or x3 or x4 or x5 or x6 or x7 or sel)
begin
case (sel)
3'b000: y = x0;
3'b001: y = x1;
3'b010: y = x2;
3'b011: y = x3;
3'b100: y = x4;
3'b101: y = x5;
3'b110: y = x6;
3'b111: y = x7;
endcase
end
endmodule
|
`include "hi_simulate.v"
/*
\tpck0\t\t\t- input main 24Mhz clock (PLL / 4)
\t[7:0] adc_d\t\t- input data from A/D converter
\tmod_type\t- modulation type
\tpwr_lo\t\t\t- output to coil drivers (ssp_clk / 8)
\tadc_clk\t\t\t- output A/D clock signal
\tssp_frame\t\t- output SSS frame indicator (goes high while the 8 bits are shifted)
\tssp_din\t\t\t- output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
\tssp_clk\t\t\t- output SSP clock signal
\tck_1356meg\t\t- input unused
\tck_1356megb\t\t- input unused
\tssp_dout\t\t- input unused
\tcross_hi\t\t- input unused
\tcross_lo\t\t- input unused
\tpwr_hi\t\t\t- output unused, tied low
\tpwr_oe1\t\t\t- output unused, undefined
\tpwr_oe2\t\t\t- output unused, undefined
\tpwr_oe3\t\t\t- output unused, undefined
\tpwr_oe4\t\t\t- output unused, undefined
\tdbg\t\t\t\t- output alias for adc_clk
*/
module testbed_hi_simulate;
\treg pck0;
\treg [7:0] adc_d;
\treg mod_type;
\twire pwr_lo;
\twire adc_clk;
\treg ck_1356meg;
\treg ck_1356megb;
\twire ssp_frame;
\twire ssp_din;
\twire ssp_clk;
\treg ssp_dout;
\twire pwr_hi;
\twire pwr_oe1;
\twire pwr_oe2;
\twire pwr_oe3;
\twire pwr_oe4;
\twire cross_lo;
\twire cross_hi;
\twire dbg;
\thi_simulate #(5,200) dut(
\t.pck0(pck0),
\t.ck_1356meg(ck_1356meg),
\t.ck_1356megb(ck_1356megb),
\t.pwr_lo(pwr_lo),
\t.pwr_hi(pwr_hi),
\t.pwr_oe1(pwr_oe1),
\t.pwr_oe2(pwr_oe2),
\t.pwr_oe3(pwr_oe3),
\t.pwr_oe4(pwr_oe4),
\t.adc_d(adc_d),
\t.adc_clk(adc_clk),
\t.ssp_frame(ssp_frame),
\t.ssp_din(ssp_din),
\t.ssp_dout(ssp_dout),
\t.ssp_clk(ssp_clk),
\t.cross_hi(cross_hi),
\t.cross_lo(cross_lo),
\t.dbg(dbg),
\t.mod_type(mod_type)
\t);
\tinteger idx, i;
\t// main clock
\talways #5 begin
\t\tck_1356megb = !ck_1356megb;
\t\tck_1356meg = ck_1356megb;
\tend
\talways begin
\t\t@(negedge adc_clk) ;
\t\tadc_d = $random;
\tend
\t//crank DUT
\ttask crank_dut;
\t\tbegin
\t\t\t@(negedge ssp_clk) ;
\t\t\tssp_dout = $random;
\t\tend
\tendtask
\tinitial begin
\t\t// init inputs
\t\tck_1356megb = 0;
\t\t// random values
\t\tadc_d = 0;
\t\tssp_dout=1;
\t\t// shallow modulation off
\t\tmod_type=0;
\t\tfor (i = 0 ; i < 16 ; i = i + 1) begin
\t\t\tcrank_dut;
\t\tend
\t\t// shallow modulation on
\t\tmod_type=1;
\t\tfor (i = 0 ; i < 16 ; i = i + 1) begin
\t\t\tcrank_dut;
\t\tend
\t\t$finish;
\tend
\t
endmodule // main
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// testbench for min_max_tracker
`include "min_max_tracker.v"
`define FIN "tb_tmp/data.filtered.gold"
`define FOUT_MIN "tb_tmp/data.min"
`define FOUT_MAX "tb_tmp/data.max"
module min_max_tracker_tb;
\tinteger fin;
\tinteger fout_min, fout_max;
\tinteger r;
\treg clk;
\treg [7:0] adc_d;
\twire [7:0] min;
\twire [7:0] max;
\tinitial
\tbegin
\t\tclk = 0;
\t\tfin = $fopen(`FIN, "r");
\t\tif (!fin) begin
\t\t\t$display("ERROR: can\'t open the data file");
\t\t\t$finish;
\t\tend
\t\tfout_min = $fopen(`FOUT_MIN, "w+");\t\t
\t\tfout_max = $fopen(`FOUT_MAX, "w+");\t\t
\t\tif (!$feof(fin))
\t\t\tadc_d = $fgetc(fin); // read the first value
\tend
\talways
\t\t# 1 clk = !clk;
\t// input
\tinitial
\tbegin
\t\twhile (!$feof(fin)) begin
\t\t\t@(negedge clk) adc_d <= $fgetc(fin);
\t\tend
\t\tif ($feof(fin))
\t\tbegin
\t\t\t# 3 $fclose(fin);
\t\t\t$fclose(fout_min);
\t\t\t$fclose(fout_max);
\t\t\t$finish;
\t\tend
\tend
\tinitial
\tbegin
\t\t// $monitor("%d\\t min: %x, max: %x", $time, min, max);\t\t
\tend
\t// output
\talways @(negedge clk)
\tif ($time > 2) begin
\t\tr = $fputc(min, fout_min);
\t\tr = $fputc(max, fout_max);
\tend
\t// module to test
\tmin_max_tracker tracker(clk, adc_d, 8\'d127, min, max);
endmodule |
//-----------------------------------------------------------------------------
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module hi_read_rx_xcorr(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
xcorr_is_848, snoop, xcorr_quarter_freq
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input xcorr_is_848, snoop, xcorr_quarter_freq;
// Carrier is steady on through this, unless we're snooping.
assign pwr_hi = ck_1356megb & (~snoop);
assign pwr_oe1 = 1'b0;
assign pwr_oe2 = 1'b0;
assign pwr_oe3 = 1'b0;
assign pwr_oe4 = 1'b0;
reg ssp_clk;
reg ssp_frame;
reg fc_div_2;
always @(posedge ck_1356meg)
fc_div_2 = ~fc_div_2;
reg fc_div_4;
always @(posedge fc_div_2)
fc_div_4 = ~fc_div_4;
reg fc_div_8;
always @(posedge fc_div_4)
fc_div_8 = ~fc_div_8;
reg adc_clk;
always @(xcorr_is_848 or xcorr_quarter_freq or ck_1356meg)
if(~xcorr_quarter_freq)
begin
\t if(xcorr_is_848)
\t // The subcarrier frequency is fc/16; we will sample at fc, so that
\t // means the subcarrier is 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 ...
\t adc_clk <= ck_1356meg;
\t else
\t // The subcarrier frequency is fc/32; we will sample at fc/2, and
\t // the subcarrier will look identical.
\t adc_clk <= fc_div_2;
end
else
begin
\t if(xcorr_is_848)
\t // The subcarrier frequency is fc/64
\t adc_clk <= fc_div_4;
\t else
\t // The subcarrier frequency is fc/128
\t adc_clk <= fc_div_8;
\tend
// When we're a reader, we just need to do the BPSK demod; but when we're an
// eavesdropper, we also need to pick out the commands sent by the reader,
// using AM. Do this the same way that we do it for the simulated tag.
reg after_hysteresis, after_hysteresis_prev;
reg [11:0] has_been_low_for;
always @(negedge adc_clk)
begin
if(& adc_d[7:0]) after_hysteresis <= 1'b1;
else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
if(after_hysteresis)
begin
has_been_low_for <= 7'b0;
end
else
begin
if(has_been_low_for == 12'd4095)
begin
has_been_low_for <= 12'd0;
after_hysteresis <= 1'b1;
end
else
has_been_low_for <= has_been_low_for + 1;
end
end
// Let us report a correlation every 4 subcarrier cycles, or 4*16 samples,
// so we need a 6-bit counter.
reg [5:0] corr_i_cnt;
reg [5:0] corr_q_cnt;
// And a couple of registers in which to accumulate the correlations.
reg signed [15:0] corr_i_accum;
reg signed [15:0] corr_q_accum;
reg signed [7:0] corr_i_out;
reg signed [7:0] corr_q_out;
// ADC data appears on the rising edge, so sample it on the falling edge
always @(negedge adc_clk)
begin
// These are the correlators: we correlate against in-phase and quadrature
// versions of our reference signal, and keep the (signed) result to
// send out later over the SSP.
if(corr_i_cnt == 7'd63)
begin
if(snoop)
begin
corr_i_out <= {corr_i_accum[12:6], after_hysteresis_prev};
corr_q_out <= {corr_q_accum[12:6], after_hysteresis};
end
else
begin
// Only correlations need to be delivered.
corr_i_out <= corr_i_accum[13:6];
corr_q_out <= corr_q_accum[13:6];
end
corr_i_accum <= adc_d;
corr_q_accum <= adc_d;
corr_q_cnt <= 4;
corr_i_cnt <= 0;
end
else
begin
if(corr_i_cnt[3])
corr_i_accum <= corr_i_accum - adc_d;
else
corr_i_accum <= corr_i_accum + adc_d;
if(corr_q_cnt[3])
corr_q_accum <= corr_q_accum - adc_d;
else
corr_q_accum <= corr_q_accum + adc_d;
corr_i_cnt <= corr_i_cnt + 1;
corr_q_cnt <= corr_q_cnt + 1;
end
// The logic in hi_simulate.v reports 4 samples per bit. We report two
// (I, Q) pairs per bit, so we should do 2 samples per pair.
if(corr_i_cnt == 6'd31)
after_hysteresis_prev <= after_hysteresis;
// Then the result from last time is serialized and send out to the ARM.
// We get one report each cycle, and each report is 16 bits, so the
// ssp_clk should be the adc_clk divided by 64/16 = 4.
if(corr_i_cnt[1:0] == 2'b10)
ssp_clk <= 1'b0;
if(corr_i_cnt[1:0] == 2'b00)
begin
ssp_clk <= 1'b1;
// Don't shift if we just loaded new data, obviously.
if(corr_i_cnt != 7'd0)
begin
corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
corr_q_out[7:1] <= corr_q_out[6:0];
end
end
if(corr_i_cnt[5:2] == 4'b000 || corr_i_cnt[5:2] == 4'b1000)
ssp_frame = 1'b1;
else
ssp_frame = 1'b0;
end
assign ssp_din = corr_i_out[7];
assign dbg = corr_i_cnt[3];
// Unused.
assign pwr_lo = 1'b0;
endmodule
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